HP DV3 LA-4732P-UMA Schematics
A
1 1
2 2
B
C
D
E
Compal confidential
Schematics Document
Mobile Penryn uFCPGA with Intel
Cantiga_GM+ICH9-M core logic
3 3
2009-02-16
REV:1.0
4 4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
2007/08/28 2006/03/10
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
D
Date: Sheet of
Compal Electronics, Inc.
Cover Sheet
Montevina UMA
E
1 46Wednesday, February 18, 2009
0.1
A
B
C
D
E
Compal confidential
1 1
LVDS Panel
Interface
CRT
Support V1.3
2 2
HDMI
RTL8103EL
(10/100M)
P25
P19
P18
P35
Mini-Card
WLAN WWAN
RJ45/11 CONN
3 3
P25
Thermal Sensor
EMC1402
Fan conn
Mini-Card
Montevina Consumer UMA
Mobile Penryn
P06
P06
PCI-E BUS*4
New Card
P26P26
DMI X4
P26
uFCPGA-478 CPU
P6, 7, 8
H_A#(3..35)
H_D#(0..63)
FSB
667/800/1066 MHz 1.05V
Intel Cantiga MCH
FCBGA 1329
GM47
P9,10, 11, 12, 13, 14
C-Link
Intel ICH9-M
mBGA-676
P20,21,22,23
LPC BUS
CK505
Clock Generator
SLG8SP553V
DDR2 800MHz 1.8V
Dual Channel
USB2.0 X12
Azalia
SATA Master-1
SATA Slave
SATA Slave
72QFN
P17
DDR2 SO-DIMM X2
BANK 0, 1, 2, 3
USB conn x1
BT Conn
USB Camera
Finger print
CardReader
P15, 16
P30
P30
P19
P30
5 in1 Slot
P27
Audio CKT AMP & Audio Jack
Codec_IDT92HD75B
MDC
P28 P29
P28
TPA6047
P27
SATA HDD Connector
P24
ENE
KB926
RTC CKT.
P21
LED
P33
ACCELEROMETER-1
ST
4 4
P24
Touch Pad CONN.
P33
SPI ROM
SST25VF080
P31
P32
Int.KBD
SPI
P32
K/B backlight Conn
P33
DC/DC Interface CKT.
A
P36
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
2006/02/13 2006/03/10
Compal Secret Data
Deciphered Date
SATA ODD Connector
e-SATA Connector
Custom
D
P24
P30
USB Board Conn
USB port x2
Capsense switch Conn
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.
Block Diagram
Montevina UMA
E
2 46Wednesday, February 18, 2009
P30
P33
0.1
A
Symbol Note :
Voltage Rails
power
plane
State
S0
S1
S3
S5 S4/AC
S5 S4/ Battery only
S5 S4/AC & Battery
don't exist
1 1
O MEANS ON X MEANS OFF
+B
O
O
O
O
O
+5VALW
+3VALW
O
O
O
O
X
XX
+1.5V
: means Digital Ground
: means Analog Ground
+5VS
+3VS
+1.5VS
+0.75V
+VCCP
+CPU_CORE
+2.5VS
+1.8V
O
O
O
X
X
X
O
O
X
X
X
X
@ : means just reserve , no build
45@ : means need be mounted when 45 level assy or rework stage.
DEBUG@ : means just reserve for debug.
BATT @ : means need be mounted when 45 level assy or rework stage.
CONN@ : means ME part
ESATA @ : means just reserve for ESATA
GS @ : means just reserve for G sensor
FP @ : means just reserve for Finger Print
Multi @ : means just reserve for Multi Bay
NewC@ : means just reserve for New card
Main@ : means just reserve for Main stream
OPP@ : means just reserve for OPP
2MiniC@ : means just reserve for 2nd Mini card slot
PA @ : means just reserve for PA
PR @ : means just reserve for PR
USB assignment:
USB-0 Right side(with eSATA)
USB-1 Left side
USB-2 Left side
USB-3 Cardreader
USB-4 Camera
USB-5 WLAN
USB-6 Bluetooth
USB-7 Finger Printer
USB-8 MiniCard(WWAN/TV)
USB-9 Express card
USB-10 X
USB-11 X
PCIe assignment:
PCIe-1 WWAN
PCIe-2 X
PCIe-3 WLAN
PCIe-4 GLAN (Realtek)
PCIe-5 X
PCIe-6 New Card
I2C / SMBUS ADDRESSING
HEX
A0
D2
ADDRESS
1 0 1 0 0 0 0 0
1 0 1 0 0 1 0 0A4
1 1 0 1 0 0 1 0
DEVICE
DDR SO-DIMM 0
DDR SO-DIMM 1
CLOCK GENERATOR (EXT.)
SMBUS Control Table
SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
SMB_CK_CLK1
SMB_CK_DAT1
LCD_CLK
LCD_DAT
SOURCE
KB926
KB926
ICH9
Cantiga
INVERTER
X
X
X
X
BATT
V
X
X
X
SERIAL
EEPROM
Thermal
Sensor
V
X
X
X
X
V
X
X
SODIMM CLK CHIP
X
X
X
X
V V V
X
X
MINI CARD
X
X
X
LCD
X
X
X
V
Cap sensor
board
V
X
X
X
NEW CARD G sensor
X X
X
X
V V
X
X
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
A
2007/08/28 2006/03/10
Compal Secret Data
Deciphered Date
Custom
Title
Size Document Number Rev
Date: Sheet of
Compal Electronics, Inc.
Notes List
Montevina UMA
3 46Wednesday, February 18, 2009
0.1
5
4
3
2
60mA
+3VAUX_BT
1
50mA
1A
0.3A
2A
+V_BATTERY
INVPWR_B+
B++
LVDS CON
1.7A
+3VALW
+1.5VS
+5VALW
177mA
300mA
ICH9
LAN
3.39A5.89A
+3VS
RT5158
657mA
2.2A0.3A
1.3A0.58A
1.56A
ICH_VCC1_5
ICH9
ICH9
+5VS
35mA
10mA
D D
VIN
AC
C C
B+
7A
25mA
20mA
10mA
1A
278mA
1.5A
250mA
1A
1A
+VDDA
IDT 9275B
+5VAMP
Finger printer
+3VS_DVDD
ALC268
+3VALW_EC
SPI ROM
New card
ICH9
+LCDVDD
LVDS CON
+3VS_CK505
Mini card (WLAN)
Mini card (TV tu/WWAN/Robeson)
1.8A
B B
3.7 X 3=11.1V
DC BATT
B+++
A A
5
CPU_B+ +VCC_CORE
12.11A1.9A
4.7A
10mA2A
+1.8V
1.05V_B+
34A/1.025V
4
3.7A
50mA
+VCCP
CPU
MCH
DDR2 800Mhz 4G x2
+0.9V
1.17A
1.26A
2.3A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
3
ICH9
MCH
CPU
2007/08/28 2006/03/10
700mA
50mA
Compal Secret Data
Deciphered Date
ODD
SATA
PC Camera(4.75V)
2
Compal Electronics, Inc.
Title
Size Document Number Rev
C
Montevina UMA
Date: Sheet of
Power delevry
1
4 46Wednesday, February 18, 2009
0.1
A
1 1
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
A
2007/08/28 2006/03/10
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
Date: Sheet of
Compal Electronics, Inc.
Notes List
Montevina UMA
5 46Wednesday, February 18, 2009
0.1
5
4
3
2
1
ITP-XDP Connector
+VCCP
XDP_TDI
D D
XDP_TMS
XDP_TDO
R2 54.9_0402_1%
1 2
R3 54.9_0402_1%
1 2
R4 54.9_0402_1%
1 2
H_A#[3..16]9
H_ADSTB#09
H_REQ#09
H_REQ#19
H_REQ#29
H_REQ#39
H_REQ#49
C C
B B
A A
H_A#[17..35]9
H_ADSTB#19
H_A20M#21
H_FERR#21
H_IGNNE#21
H_STPCLK#21
H_INTR21
H_NMI21
H_SMI#21
+VCCP
B
H_PROCHOT# OCP#
H_IERR#
E
3 1
Q1
@
MMBT3904_NL_SOT23-3
+VCCP
12
@
R17
56_0402_5%
2
C
R18
56_0402_5%
1 2
5
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1
H_A20M#
H_FERR#
H_IGNNE#
H_STPCLK#
H_INTR
H_NMI
H_SMI#
J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1
K3
H2
K2
J3
L1
Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
AA4
AB2
AA3
V1
A6
A5
C4
D5
C6
B4
A3
M4
N5
T2
V3
B2
D2
D22
D3
F6
OCP# 22
JCPU1A
A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#
REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#
A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#
A20M#
FERR#
IGNNE#
STPCLK#
LINT0
LINT1
SMI#
RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]
Penryn
ADDR GROUP_0
ADDR GROUP_1
THERMAL
ICH
THERMTRIP#
RESERVED
ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#
BR0#
IERR#
INIT#
LOCK#
CONTROL
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
HIT#
HITM#
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDO
TMS
TRST#
DBR#
XDP/ITP SIGNALS
PROCHOT#
THERMDA
THERMDC
H CLK
BCLK[0]
BCLK[1]
H_ADS#
H1
H_BNR#
E2
H_BPRI#
G5
H_DEFER#
H5
H_DRDY#
F21
H_DBSY#
E1
H_BR0#
F1
H_IERR#
D20
H_INIT#
B3
H_LOCK#
H4
H_RESET#
C1
H_RS#0
F3
H_RS#1
F4
H_RS#2
G3
H_TRDY#
G2
H_HIT#
G6
H_HITM#
E4
AD4
AD3
AD1
AC4
AC2
AC1
XDP_TCK
AC5
XDP_TDI
AA6
TDI
AB3
AB5
AB6
C20
D21
A24
B25
C7
A22
A21
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#
H_PROCHOT#
H_THERMDC_R
H_THERMTRIP#
CLK_CPU_BCLK
CLK_CPU_BCLK#
H_ADS# 9
H_BNR# 9
H_BPRI# 9
H_DEFER# 9
H_DRDY# 9
H_DBSY# 9
H_BR0# 9
H_INIT# 21
H_LOCK# 9
H_RESET# 9
H_RS#0 9
H_RS#1 9
H_RS#2 9
H_TRDY# 9
H_HIT# 9
H_HITM# 9
R13 56_0402_1%
R14 0_0402_5%
R15 0_0402_5%
H_THERMTRIP# 9,21
CLK_CPU_BCLK 17
CLK_CPU_BCLK# 17
T1
Place TP with a
GND 0.1" away
XDP_DBRESET# 22
1 2
1 2
1 2
H_THERMDA, H_THERMDC routing
together, Trace width / Spacing = 10 / 10
mil
+VCCP
H_THERMDAH _THERMDA_R
H_THERMDC
+3VS
+3VS
0.1U_0402_16V4Z
C3
1 2
2200P_0402_50V7K
R16
1 2
10K_0402_5%
1
C2
2
H_THERMDA
H_THERMDC
THERM#
U1
1
VDD
2
DP
3
DN
4
THERM#
EMC1402-1-ACZL-TR_MSOP8
Address:100_1100
Fan Control circuit
SI-1 Change to voltage control circuit
+5VS
+3VS
R1209
10K_0402_5%
1 2
1000P_0402_50V7K
3
FAN_SPEED
1
C1510
2
2007/08/28 2006/03/10
FAN_SPEED32
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
9
Thermal Pad
8
GND
7
GND
6
GND
5
GND
G996RD1U_TDFN8_3X3
Compal Secret Data
VEN
VIN
VO
VSET
FAN_SET32
Deciphered Date
U51
1
2
3
4
1
C4 2.2U_0603_6.3V4Z
2
+5VS_FAN
1
C1509
2.2U_0603_6.3V4Z
2
2
XDP_TRST#
XDP_TCK
This shall place near CPU
SMCLK
SMDATA
ALERT#
GND
+5VS
Title
Size Document Number Rev
Custom
Date: Sheet of
R7 54.9_0402_1%
1 2
R8 54.9_0402_1%
1 2
SMB_EC_CK2
8
SMB_EC_DA2
7
R6 10K_0402_5%
6
1 2
5
1
C5
0.1U_0402_16V4Z
2
CONN@
JFAN1
1
1
2
2
3
3
ACES_85204-03001
D63
3
Vcc
2
Line to be protected
1
GND
DLPT05-7-F_SOT23-3
FAN_SPEED
Compal Electronics, Inc.
Penryn(1/3)-AGTL+/ITP-XDP
Montevina UMA
1
SMB_EC_CK2 32
SMB_EC_DA2 32
+3VS
4
G1
5
G2
6 46Wednesday, February 18, 2009
0.1
5
4
3
2
1
H_D#[0..15]9
D D
H_DSTBN#09
H_DSTBP#09
H_DINV#09
H_D#[16..31]9
C C
* Route the TEST3 and TEST5 signals through
a ground referenced Zo = 55-ohm trace that
ends in a via that is near a GND via and is
accessible through an oscilloscope
connection.
B B
CPU_BSEL CPU_BSEL2 CPU_BSEL1
R21 1K_0402_5%@
R22 1K_0402_5%@
166
H_DSTBN#19
H_DSTBP#19
H_DINV#19
1 2
1 2
CPU_BSEL017
CPU_BSEL117
T2
T3
T4
T5
T6
0 1
200
266
0 0
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1
+V_CPU_GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
10
JCPU1B
E22
D[0]#
F24
D[1]#
E26
D[2]#
G22
D[3]#
F23
D[4]#
G25
D[5]#
E25
D[6]#
E23
D[7]#
K24
D[8]#
G24
D[9]#
J24
D[10]#
J23
D[11]#
H22
D[12]#
F26
D[13]#
K22
D[14]#
H23
D[15]#
J26
DSTBN[0]#
H26
DSTBP[0]#
H25
DINV[0]#
N22
D[16]#
K25
D[17]#
P26
D[18]#
R23
D[19]#
L23
D[20]#
M24
D[21]#
L22
D[22]#
M23
D[23]#
P25
D[24]#
P23
D[25]#
P22
D[26]#
T24
D[27]#
R24
D[28]#
L25
D[29]#
T25
D[30]#
N25
D[31]#
L26
DSTBN[1]#
M26
DSTBP[1]#
N24
DINV[1]#
AD26
GTLREF
C23
TEST1
D25
TEST2
C24
TEST3
AF26
TEST4
AF1
TEST5
A26
TEST6
C3
TEST7
B22
BSEL[0]
B23
BSEL[1]
C21
BSEL[2]
Penryn
CPU_BSEL0
H_D#32
Y22
MISC
DATA GRP 0
DATA GRP 1
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
DATA GRP 2DATA GRP 3
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
COMP[0]
COMP[1]
COMP[2]
COMP[3]
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22
AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20
R26
U26
AA1
Y1
E5
B5
D24
D6
D7
AE6
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3
COMP0
COMP1
COMP2
COMP3
H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGOOD
H_CPUSLP#
H_PSI#
1
0
0
H_D#[32..47] 9
H_DSTBN#2 9
H_DSTBP#2 9
H_DINV#2 9
H_D#[48..63] 9
H_DSTBN#3 9
H_DSTBP#3 9
H_DINV#3 9
H_DPRSTP# 9,21,42
H_DPSLP# 21
H_DPWR# 9
H_PWRGOOD 21
H_CPUSLP# 9
H_PSI# 42CPU_BSEL217
R23
12
54.9_0402_1%
Resistor placed within 0.5"
of CPU pin.Trace should be
at least 25 mils away from
any other toggling signal.
COMP[0,2] trace width is 18
mils. COMP[1,3] trace width
is 4 mils.
+V_CPU_GTLREF
27.4_0402_1%
12
+VCCP
12
54.9_0402_1%
12
R27
1K_0402_1%
12
R29
2K_0402_1%
R25
R24
27.4_0402_1%
+VCC_CORE +VCC_CORE
R26
12
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AC10
AB10
AB12
AB14
AB15
AB17
AB18
JCPU1C
A7
VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]
Penryn
VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]
VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]
VCCA[01]
VCCA[02]
VCCSENSE
VSSSENSE
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AB9
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
AF20
+VCCPA
G21
+VCCPB
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
B26
C26
AD6
AF5
AE5
AF4
AE3
AF3
AE2
AF7
AE7
.
1 2
1 2
VCCSENSE
VSSSENSE
R19
0_0402_5%
0_0402_5%
R20
CPU_VID0 42
CPU_VID1 42
CPU_VID2 42
CPU_VID3 42
CPU_VID4 42
CPU_VID5 42
CPU_VID6 42
VCCSENSE 42
VSSSENSE 42
Length match within 25 mils.
The trace width/space/other is 20/7/25.
+VCC_CORE
R28 100_0402_1%
1 2
R30 100_0402_1%
1 2
+VCCP
10U_0805_6.3V6M
VCCSENSE
VSSSENSE
1
+
C6
330U_D2E_2.5VM_R7
2
1
C7
2
0.01U_0402_16V7K
+1.5VS
1
C8
2
Near pin B26
Close to CPU pin within
A A
Close to CPU pin AD26
within 500mils.
500mils.
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2007/08/28 2006/03/10
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet of
Compal Electronics, Inc.
Penryn(2/3)-AGTL+/ITP-XDP
Montevina UMA
1
7 46Wednesday, February 18, 2009
0.1
5
D D
JCPU1D
A4
VSS[001]
A8
VSS[002]
A11
VSS[003]
A14
VSS[004]
A16
VSS[005]
A19
VSS[006]
A23
VSS[007]
AF2
VSS[008]
B6
VSS[009]
B8
VSS[010]
B11
VSS[011]
B13
VSS[012]
B16
VSS[013]
B19
VSS[014]
B21
VSS[015]
B24
VSS[016]
C5
VSS[017]
C8
VSS[018]
C11
VSS[019]
C14
VSS[020]
C16
VSS[021]
C19
VSS[022]
C2
VSS[023]
C22
VSS[024]
C25
VSS[025]
D1
VSS[026]
D4
VSS[027]
D8
VSS[028]
D11
C C
B B
VSS[029]
D13
VSS[030]
D16
VSS[031]
D19
VSS[032]
D23
VSS[033]
D26
VSS[034]
E3
VSS[035]
E6
VSS[036]
E8
VSS[037]
E11
VSS[038]
E14
VSS[039]
E16
VSS[040]
E19
VSS[041]
E21
VSS[042]
E24
VSS[043]
F5
VSS[044]
F8
VSS[045]
F11
VSS[046]
F13
VSS[047]
F16
VSS[048]
F19
VSS[049]
F2
VSS[050]
F22
VSS[051]
F25
VSS[052]
G4
VSS[053]
G1
VSS[054]
G23
VSS[055]
G26
VSS[056]
H3
VSS[057]
H6
VSS[058]
H21
VSS[059]
H24
VSS[060]
J2
VSS[061]
J5
VSS[062]
J22
VSS[063]
J25
VSS[064]
K1
VSS[065]
K4
VSS[066]
K23
VSS[067]
K26
VSS[068]
L3
VSS[069]
L6
VSS[070]
L21
VSS[071]
L24
VSS[072]
M2
VSS[073]
M5
VSS[074]
M22
VSS[075]
M25
VSS[076]
N1
VSS[077]
N4
VSS[078]
N23
VSS[079]
N26
VSS[080]
VSS[081]P3VSS[162]
Penryn
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[163]
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25
.
4
Place these capacitors on
L8 (North side,Secondary
Layer)
Place these capacitors on
L8 (North side,Secondary
Layer)
Place these capacitors on
L8 (North side,Secondary
Layer)
Place these capacitors on
L8 (North side,Secondary
Layer)
Mid Frequence Decoupling
Near CPU CORE regulator
+VCC_CORE
C41
+VCCP
1
C45
0.1U_0402_10V6K
2
3
+VCC_CORE
1
2
+VCC_CORE
1
2
+VCC_CORE
1
2
+VCC_CORE
1
2
C9
10U_0805_6.3V6M
C17
10U_0805_6.3V6M
C25
10U_0805_6.3V6M
C33
10U_0805_6.3V6M
1
C10
10U_0805_6.3V6M
2
1
C18
10U_0805_6.3V6M
2
1
C26
10U_0805_6.3V6M
2
1
C34
10U_0805_6.3V6M
2
ESR <= 1.5m ohm
Capacitor > 1980uF
1
1
@
+
C42
2
2
330U_D2_2VY_R7M
Inside CPU center cavity in 2 rows
1
C46
0.1U_0402_10V6K
2
1
+
C43
330U_D2_2VY_R7M
1
2
+
C44
2
330U_D2_2VY_R7M
C47
0.1U_0402_10V6K
1
+
2
330U_D2_2VY_R7M
1
C11
10U_0805_6.3V6M
2
1
C19
10U_0805_6.3V6M
2
1
C27
10U_0805_6.3V6M
2
1
C35
10U_0805_6.3V6M
2
1
C48
0.1U_0402_10V6K
2
1
C12
10U_0805_6.3V6M
2
1
C20
10U_0805_6.3V6M
2
1
C28
10U_0805_6.3V6M
2
1
C36
10U_0805_6.3V6M
2
1
C49
0.1U_0402_10V6K
2
1
C13
10U_0805_6.3V6M
2
1
C21
10U_0805_6.3V6M
2
1
C29
10U_0805_6.3V6M
2
1
C37
10U_0805_6.3V6M
2
1
C50
0.1U_0402_10V6K
2
2
1
C14
10U_0805_6.3V6M
2
1
C22
10U_0805_6.3V6M
2
1
C30
10U_0805_6.3V6M
2
1
C38
10U_0805_6.3V6M
2
1
C15
10U_0805_6.3V6M
2
1
C23
10U_0805_6.3V6M
2
1
C31
10U_0805_6.3V6M
2
1
C39
10U_0805_6.3V6M
2
1
2
1
2
1
2
1
2
1
C16
10U_0805_6.3V6M
C24
10U_0805_6.3V6M
C32
10U_0805_6.3V6M
C40
10U_0805_6.3V6M
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2007/08/28 2006/03/10
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet of
Compal Electronics, Inc.
Penryn(3/3)-AGTL+/ITP-XDP
Montevina UMA
1
8 46Wednesday, February 18, 2009
0.1
5
H_RCOMP
12
R54
AD14
AA13
AA11
AD11
AD10
AD13
AE12
AE14
AE11
U2A
F2
H_D#_0
G8
H_D#_1
F8
H_D#_2
E6
H_D#_3
G2
H_D#_4
H6
H_D#_5
H2
H_D#_6
F6
H_D#_7
D4
H_D#_8
H3
H_D#_9
M9
H_D#_10
M11
H_D#_11
J1
H_D#_12
J2
H_D#_13
N12
H_D#_14
J6
H_D#_15
P2
H_D#_16
L2
H_D#_17
R2
H_D#_18
N9
H_D#_19
L6
H_D#_20
M5
H_D#_21
J3
H_D#_22
N2
H_D#_23
R1
H_D#_24
N5
H_D#_25
N6
H_D#_26
P13
H_D#_27
N8
H_D#_28
L7
H_D#_29
N10
H_D#_30
M3
H_D#_31
Y3
H_D#_32
H_D#_33
Y6
H_D#_34
Y10
H_D#_35
Y12
H_D#_36
Y14
H_D#_37
Y7
H_D#_38
W2
H_D#_39
AA8
H_D#_40
Y9
H_D#_41
H_D#_42
AA9
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
AE9
H_D#_49
AA2
H_D#_50
AD8
H_D#_51
AA3
H_D#_52
AD3
H_D#_53
AD7
H_D#_54
H_D#_55
AF3
H_D#_56
AC1
H_D#_57
AE3
H_D#_58
AC3
H_D#_59
H_D#_60
AE8
H_D#_61
AG2
H_D#_62
AD6
H_D#_63
C5
H_SWING
E3
H_RCOMP
C12
H_CPURST#
E11
H_CPUSLP#
A11
H_AVREF
B11
H_DVREF
CANTIGA ES_FCBGA1329
+VCCP
12
221_0603_1%
12
100_0402_1%
H_ADSTB#_0
H_ADSTB#_1
H_BREQ#
H_DEFER#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
HOST
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
R47
+H_SWNG
1
C59
R55
2
0.1U_0402_16V4Z
H_D#[0..63]7
D D
C C
H_RESET#6
H_CPUSLP#7
B B
Layout note:
Route H_SCOMP and H_SCOMP# with trace
width, spacing and impedance (55 ohm) same as
FSB data traces
Layout Note:
H_RCOMP / H_VREF / H_SWNG
trace width and spacing is 10/20
+VCCP
12
R46
1K_0402_1%
A A
12
R52
2K_0402_1%
0.1U_0402_16V4Z
+H_VREF
1
C58
2
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
+H_SWNG
H_RCOMP
H_RESET#
H_CPUSLP#
+H_VREF
24.9_0402_1%
Near B3 pinwithin 100 mils from NB
5
4
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35
H_ADS#
H_BNR#
H_BPRI#
H_DBSY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
H_RS#_0
H_RS#_1
H_RS#_2
H_A#4
C15
H_A#5
F16
H_A#6
H13
H_A#7
C18
H_A#8
M16
H_A#9
J13
H_A#10
P16
H_A#11
R16
H_A#12
N17
H_A#13
M13
H_A#14
E17
H_A#15
P17
H_A#16
F17
H_A#17
G20
H_A#18
B19
H_A#19
J16
H_A#20
E20
H_A#21
H16
H_A#22
J20
H_A#23
L17
H_A#24
A17
H_A#25
B17
H_A#26
L16
H_A#27
C21
H_A#28
J17
H_A#29
H20
H_A#30
B18
H_A#31
K17
H_A#32
B20
H_A#33
F21
H_A#34
K21
H_A#35
L20
H_ADS#
H12
H_ADSTB#0
B16
H_ADSTB#1
G17
H_BNR#
A9
H_BPRI#
F11
H_BR0#
G12
H_DEFER#
E9
H_DBSY#
B10
CLK_MCH_BCLK
AH7
CLK_MCH_BCLK#
AH6
H_DPWR#
J11
H_DRDY#
F9
H_HIT#
H9
H_HITM#
E12
H_LOCK#
H11
H_TRDY#
C9
H_DINV#0
J8
H_DINV#1
L3
H_DINV#2
Y13
H_DINV#3
Y1
H_DSTBN#0
L10
H_DSTBN#1
M7
H_DSTBN#2
AA5
H_DSTBN#3
AE6
H_DSTBP#0
L9
H_DSTBP#1
M8
H_DSTBP#2
AA6
H_DSTBP#3
AE5
H_REQ#0
B15
H_REQ#1
K13
H_REQ#2
F13
H_REQ#3
B13
H_REQ#4
B14
H_RS#0
B6
H_RS#1
F12
H_RS#2
C8
Layout Note: V_DDR_MCH_REF
trace width and spacing is 20/20.
H_A#3
A14
H_A#[3..35] 6
H_ADS# 6
H_ADSTB#0 6
H_ADSTB#1 6
H_BNR# 6
H_BPRI# 6
H_BR0# 6
H_DEFER# 6
H_DBSY# 6
CLK_MCH_BCLK 17
CLK_MCH_BCLK# 17
H_DPWR# 7
H_DRDY# 6
H_HIT# 6
H_HITM# 6
H_LOCK# 6
H_TRDY# 6
H_DINV#0 7
H_DINV#1 7
H_DINV#2 7
H_DINV#3 7
H_DSTBN#0 7
H_DSTBN#1 7
H_DSTBN#2 7
H_DSTBN#3 7
H_DSTBP#0 7
H_DSTBP#1 7
H_DSTBP#2 7
H_DSTBP#3 7
H_REQ#0 6
H_REQ#1 6
H_REQ#2 6
H_REQ#3 6
H_REQ#4 6
H_RS#0 6
H_RS#1 6
H_RS#2 6
PLT_RST#20,25,26
H_THERMTRIP#6,21
+V_DDR_MCH_REF generated by DC-DC
V_DDR_MCH_REF15,16
4
2.2U_0603_6.3V4Z
SMRCOMP_VOH
80% of 1.8V VCC_SM
20% of 1.8V VCC_SM
SMRCOMP_VOL
2.2U_0603_6.3V4Z
DPRSLPVR22,42
V_DDR_MCH_REF
1
C57
2
0.1U_0402_16V4Z
3
T7
T8
T9
+1.8V
1
1
C51
2
1
C53
2
PLT_RST#
+1.8V
C52
2
1
C54
2
R41
R42
12
R45
10K_0402_1%
12
R48
10K_0402_1%
12
R31
1K_0402_1%
0.01U_0402_25V7K
12
R32
3.01K_0402_1%
12
R33
1K_0402_1%
0.01U_0402_25V7K
PM_EXTTS#0
PM_EXTTS#1
CLKREQ#_7
1 2
1 2
R38 10K_0402_5%
1 2
R39 10K_0402_5%
1 2
R40 10K_0402_5%
1 2
MCH_CLKSEL017
MCH_CLKSEL117
MCH_CLKSEL217
PM_BMBUSY#22
H_DPRSTP#7,21,42
PM_EXTTS#015
PM_EXTTS#116
PM_PWROK22,32
CFG511
CFG611
CFG711
CFG811
CFG911
CFG1011
CFG1111
CFG1211
CFG1311
CFG1411
CFG1511
CFG1611
CFG1711
CFG1811
CFG1911
CFG2011
100_0402_5%
0_0402_5%
T85
T86
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T22
T23
T24
T25
T26
T27
T28
MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
PM_BMBUSY#
H_DPRSTP#
PM_EXTTS#0
PM_EXTTS#1
PM_PWROK
THERMTRIP#
DPRSLPVR
@
1
C55
2
0.1U_0402_16V4Z
2007/08/28 2006/03/10
U2B
M36
RESERVED
N36
RESERVED
R33
RESERVED
T33
RESERVED
AH9
RESERVED
AH10
RESERVED
AH12
RESERVED
AH13
RESERVED
K12
RESERVED
AL34
RESERVED
AK34
RESERVED
AN35
RESERVED
AM35
RESERVED
T24
RESERVED
B31
RESERVED
B2
RESERVED
M1
RESERVED
AY21
RESERVED
BG23
RESERVED
BF23
RESERVED
BH18
RESERVED
BF18
RESERVED
+3VS
T25
CFG_0
R25
CFG_1
P25
CFG_2
P20
CFG_3
P24
CFG_4
C25
CFG_5
N24
CFG_6
M24
CFG_7
E21
CFG_8
C23
CFG_9
C24
CFG_10
N21
CFG_11
P21
CFG_12
T21
CFG_13
R20
CFG_14
M20
CFG_15
L21
CFG_16
H21
CFG_17
P29
CFG_18
R28
CFG_19
T28
CFG_20
R29
PM_SYNC#
B7
PM_DPRSTP#
N33
PM_EXT_TS#_0
P32
PM_EXT_TS#_1
AT40
PWROK
AT11
RSTIN#
T20
THERMTRIP#
R32
DPRSLPVR
BG48
NC
BF48
NC
BD48
NC
BC48
NC
BH47
NC
BG47
NC
BE47
NC
BH46
NC
BF46
NC
BG45
NC
BH44
NC
BH43
NC
BH6
NC
BH5
NC
BG4
NC
BH3
NC
BF3
NC
BH2
NC
BG2
NC
BE2
NC
BG1
NC
BF1
NC
BD1
NC
BC1
NC
F1
NC
A47
NC
CANTIGA ES_FCBGA1329
Compal Secret Data
Deciphered Date
RSVD
CFG
PM
NC
2
SM_RCOMP_VOH
SM_RCOMP_VOL
DDR CLK/ CONTROL/COMPENSATION
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
CLK
DMI
GRAPHICS VID
MEHDA
DDPC_CTRLDATA
SDVO_CTRLDATA
MISC
2
SA_CK_0
SA_CK_1
SB_CK_0
SB_CK_1
SA_CK#_0
SA_CK#_1
SB_CK#_0
SB_CK#_1
SA_CKE_0
SA_CKE_1
SB_CKE_0
SB_CKE_1
SA_CS#_0
SA_CS#_1
SB_CS#_0
SB_CS#_1
SA_ODT_0
SA_ODT_1
SB_ODT_0
SB_ODT_1
SM_RCOMP
SM_RCOMP#
SM_VREF
SM_PWROK
SM_REXT
SM_DRAMRST#
DPLL_REF_CLK
PEG_CLK
PEG_CLK#
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4
GFX_VR_EN
CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF
DDPC_CTRLCLK
SDVO_CTRLCLK
CLKREQ#
ICH_SYNC#
TSATN#
HDA_BCLK
HDA_RST#
HDA_SDI
HDA_SDO
HDA_SYNC
1
M_CLK_DDR0
AP24
M_CLK_DDR1
AT21
M_CLK_DDR2
AV24
M_CLK_DDR3
AU20
M_CLK_DDR#0
AR24
M_CLK_DDR#1
AR21
M_CLK_DDR#2
AU24
M_CLK_DDR#3
AV20
DDR_CKE0_DIMMA
BC28
DDR_CKE1_DIMMA
AY28
DDR_CKE2_DIMMB
AY36
DDR_CKE3_DIMMB
BB36
DDR_CS0_DIMMA#
BA17
DDR_CS1_DIMMA#
AY16
DDR_CS2_DIMMB#
AV16
DDR_CS3_DIMMB#
AR13
M_ODT0
BD17
M_ODT1
AY17
M_ODT2
BF15
M_ODT3
AY13
SMRCOMP
BG22
SMRCOMP#
BH21
SMRCOMP_VOH
BF28
SMRCOMP_VOL
BH28
V_DDR_MCH_REF
AV42
SM_PWROK
AR36
SM_REXT
BF17
TP_SM_DRAMRST#
BC36
CLK_MCH_DREFCLK
B38
CLK_MCH_DREFCLK#
A38
MCH_SSCDREFCLK
E41
MCH_SSCDREFCLK#
F41
CLK_MCH_3GPLL
F43
CLK_MCH_3GPLL#
E43
DMI_TXN0
AE41
DMI_TXN1
AE37
DMI_TXN2
AE47
DMI_TXN3
AH39
DMI_TXP0
AE40
DMI_TXP1
AE38
DMI_TXP2
AE48
DMI_TXP3
AH40
DMI_RXN0
AE35
DMI_RXN1
AE43
DMI_RXN2
AE46
DMI_RXN3
AH42
DMI_RXP0
AD35
DMI_RXP1
AE44
DMI_RXP2
AF46
DMI_RXP3
AH43
B33
B32
G33
F33
E33
C34
CL_CLK0
AH37
CL_DATA0
AH36
M_PWROK
AN36
CL_RST#
AJ35
+CL_VREF
AH34
0621 add CLK an d DAT for DVI
N28
M28
HDMICLK_NB
G36
HDMIDAT_NB
E36
CLKREQ#_7
K36
MCH_ICH_SYNC#
H36
TSATN#
B12
B28
B30
HDA_SDIN2_NB
B29
C29
A28
R737 56_0402_5 %
1 2
M_CLK_DDR0 15
M_CLK_DDR1 15
M_CLK_DDR2 16
M_CLK_DDR3 16
M_CLK_DDR#0 15
M_CLK_DDR#1 15
M_CLK_DDR#2 16
M_CLK_DDR#3 16
DDR_CKE0_DIMMA 15
DDR_CKE1_DIMMA 15
DDR_CKE2_DIMMB 16
DDR_CKE3_DIMMB 16
DDR_CS0_DIMMA# 15
DDR_CS1_DIMMA# 15
DDR_CS2_DIMMB# 16
DDR_CS3_DIMMB# 16
M_ODT0 15
M_ODT1 15
M_ODT2 16
M_ODT3 16
R34 80.6_0402_1%
1 2
R35 80.6_0402_1%
1 2
Follow Design Guide
For Cantiga: 80.6ohm
R36 0_0402_5%
1 2
R37 499_0402_1%
1 2
T29
CLK_MCH_DREFCLK 17
CLK_MCH_DREFCLK# 17
MCH_SSCDREFCLK 17
MCH_SSCDREFCLK# 17
CLK_MCH_3GPLL 17
CLK_MCH_3GPLL# 17
DMI_TXN0 22
DMI_TXN1 22
DMI_TXN2 22
DMI_TXN3 22
DMI_TXP0 22
DMI_TXP1 22
DMI_TXP2 22
DMI_TXP3 22
DMI_RXN0 22
DMI_RXN1 22
DMI_RXN2 22
DMI_RXN3 22
DMI_RXP0 22
DMI_RXP1 22
DMI_RXP2 22
DMI_RXP3 22
T30
T31
T35
CL_CLK0 22
CL_DATA0 22
M_PWROK 22,32
CL_RST# 22
0.1U_0402_16V4Z
T36
T37
HDMICLK_NB 3 4
HDMIDAT_NB 34
CLKREQ#_7 17
MCH_ICH_SYNC# 22
+VCCP
TSATN# 32
HDA_BITCLK_NB 21
HDA_RST#_NB 21
HDA_SDOUT_NB 21
HDA_SYNC_NB 21
1 2
33_0402_5%
C56
R210
+VCCP
1
2
*R44*Follow
Intel feedback
0830 Add pull-u p and pull-down resistor.
Title
Size Document Number Rev
Custom
Date: Sheet of
Compal Electronics, Inc.
Cantiga(1/6)-AGTL/DMI/DDR
Montevina UMA
9 46Wednesday, February 18, 2009
1
+1.8V
12
R43
1K_0402_1%
12
R44
499_0402_1%
HDA_SDIN2 21
0.1
5
D D
DDR_A_D[0..63]15
C C
B B
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
U2D
AJ38
SA_DQ_0
AJ41
SA_DQ_1
AN38
SA_DQ_2
AM38
SA_DQ_3
AJ36
SA_DQ_4
AJ40
SA_DQ_5
AM44
SA_DQ_6
AM42
SA_DQ_7
AN43
SA_DQ_8
AN44
SA_DQ_9
AU40
SA_DQ_10
AT38
SA_DQ_11
AN41
SA_DQ_12
AN39
SA_DQ_13
AU44
SA_DQ_14
AU42
SA_DQ_15
AV39
SA_DQ_16
AY44
SA_DQ_17
BA40
SA_DQ_18
BD43
SA_DQ_19
AV41
SA_DQ_20
AY43
SA_DQ_21
BB41
SA_DQ_22
BC40
SA_DQ_23
AY37
SA_DQ_24
BD38
SA_DQ_25
AV37
SA_DQ_26
AT36
SA_DQ_27
AY38
SA_DQ_28
BB38
SA_DQ_29
AV36
SA_DQ_30
AW36
SA_DQ_31
BD13
SA_DQ_32
AU11
SA_DQ_33
BC11
SA_DQ_34
BA12
SA_DQ_35
AU13
SA_DQ_36
AV13
SA_DQ_37
BD12
SA_DQ_38
BC12
SA_DQ_39
BB9
SA_DQ_40
BA9
SA_DQ_41
AU10
SA_DQ_42
AV9
SA_DQ_43
BA11
SA_DQ_44
BD9
SA_DQ_45
AY8
SA_DQ_46
BA6
SA_DQ_47
AV5
SA_DQ_48
AV7
SA_DQ_49
AT9
SA_DQ_50
AN8
SA_DQ_51
AU5
SA_DQ_52
AU6
SA_DQ_53
AT5
SA_DQ_54
AN10
SA_DQ_55
AM11
SA_DQ_56
AM5
SA_DQ_57
AJ9
SA_DQ_58
AJ8
SA_DQ_59
AN12
SA_DQ_60
AM13
SA_DQ_61
AJ11
SA_DQ_62
AJ12
SA_DQ_63
CANTIGA ES_FCBGA1329
DDR SYSTEM MEMORY A
SA_BS_0
SA_BS_1
SA_BS_2
SA_RAS#
SA_CAS#
SA_WE#
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
4
DDR_A_BS0
BD21
BG18
AT25
BB20
BD20
AY20
AM37
AT41
AY41
AU39
BB12
AY6
AT7
AJ5
AJ44
AT44
BA43
BC37
AW12
BC8
AU8
AM7
AJ43
AT43
BA44
BD37
AY12
BD8
AU9
AM8
BA21
BC24
BG24
BH24
BG25
BA24
BD24
BG27
BF25
AW24
BC21
BG26
BH26
BH17
AY25
DDR_A_BS1
DDR_A_BS2
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_BS0 15
DDR_A_BS1 15
DDR_A_BS2 15
DDR_A_RAS# 15
DDR_A_CAS# 15
DDR_A_WE# 15
DDR_A_DM[0..7] 15
DDR_A_DQS[0..7] 15
DDR_A_DQS#[0..7] 15
DDR_A_MA[0..14] 15
3
DDR_B_D[0..63]16
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
U2E
AK47
AH46
AP47
AP46
AJ46
AJ48
AM48
AP48
AU47
AU46
BA48
AY48
AT47
AR47
BA47
BC47
BC46
BC44
BG43
BF43
BE45
BC41
BF40
BF41
BG38
BF38
BH35
BG35
BH40
BG39
BG34
BH34
BH14
BG12
BH11
BG8
BH12
BF11
BF8
BG7
BC5
BC6
AY3
AY1
BF6
BF5
BA1
BD3
AV2
AU3
AR3
AN2
AY2
AV1
AP3
AR1
AL1
AL2
AJ1
AH1
AM2
AM3
AH3
AJ3
CANTIGA ES_FCBGA1329
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
2
DDR_B_BS0
BC16
SB_BS_0
SB_BS_1
SB_BS_2
SB_RAS#
SB_CAS#
SB_WE#
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
DDR SYSTEM MEMORY B
BB17
BB33
AU17
BG16
BF14
AM47
AY47
BD40
BF35
BG11
BA3
AP1
AK2
AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6
AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5
AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33
DDR_B_BS1
DDR_B_BS2
DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
1
DDR_B_BS0 16
DDR_B_BS1 16
DDR_B_BS2 16
DDR_B_RAS# 16
DDR_B_CAS# 16
DDR_B_WE# 16
DDR_B_DM[0..7] 16
DDR_B_DQS[0..7] 16
DDR_B_DQS#[0..7] 16
DDR_B_MA[0..14] 16
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2007/08/28 2006/03/10
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet of
Compal Electronics, Inc.
Cantiga(2/6)-DDR2 A/B CH
Montevina UMA
1
10 46Wednesday, February 18, 2009
0.1
5
R148
1 2
100K_0402_5%
D D
C C
B B
ENBKL
NB_BKLT_CTRL19
ENBKL32
+3VS
DDC2_CLK19
DDC2_DATA19
Follow Intel DG &
Checklist
ENAVDD19
T48
T49
T50
Follow Intel DG &
Checklist
+3VS
M_BLUE18
M_GREEN18
M_RED18
Follow Intel DG &
Checklist
3VDDCCL18
3VDDCDA18
CRT_HSYNC18
CRT_VSYNC18
NB_BKLT_CTRL
ENBKL
R58 10K_0402_5%
1 2
R59 10K_0402_5%
1 2
DDC2_CLK
DDC2_DATA
ENAVDD
R60 4.75K_0402_1%
1 2
LVDS_ACLKÂLVDS_ACLK+
LVDS_BCLKÂLVDS_BCLK+
LVDS_A0ÂLVDS_A1ÂLVDS_A2ÂLVDS_A3-
T38
LVDS_A0+
LVDS_A1+
LVDS_A2+
LVDS_A3+
T39
LVDS_B0ÂLVDS_B1ÂLVDS_B2ÂLVDS_B3-
T40
LVDS_B0+
LVDS_B1+
LVDS_B2+
LVDS_B3+
T41
TV_COMPS
TV_LUMA
TV_CRMA
12
75_0402_1%
R61
R62
R64 2.2K_0402_5%@
1 2
R406 0_0402_5%
1 2
M_BLUE
M_GREEN
M_RED
3VDDCCL
3VDDCDA
CRT_HSYNC
R65
R68
30.1_0402_1%
R69
30.1_0402_1%
150_0402_1%
12
1 2
1 2
R66
12
75_0402_1%
R63
150_0402_1%
12
R67
HSYNC
VSYNCCRT_VSYNC
1.02K_0402_1%
12
12
R70
4
U2C
L32
L_BKLT_CTRL
G32
L_BKLT_EN
M32
L_CTRL_CLK
M33
L_CTRL_DATA
K33
L_DDC_CLK
J33
L_DDC_DATA
M29
L_VDD_EN
C44
LVDS_IBG
B43
LVDS_VBG
E37
LVDS_VREFH
E38
LVDS_VREFL
C41
LVDSA_CLK#
C40
LVDSA_CLK
B37
LVDSB_CLK#
A37
LVDSB_CLK
H47
LVDSA_DATA#_0
E46
LVDSA_DATA#_1
G40
LVDSA_DATA#_2
A40
LVDSA_DATA#_3
H48
LVDSA_DATA_0
D45
LVDSA_DATA_1
F40
LVDSA_DATA_2
B40
LVDSA_DATA_3
A41
LVDSB_DATA#_0
H38
LVDSB_DATA#_1
G37
LVDSB_DATA#_2
J37
LVDSB_DATA#_3
B42
LVDSB_DATA_0
G38
LVDSB_DATA_1
F37
LVDSB_DATA_2
K37
LVDSB_DATA_3
F25
TVA_DAC
H25
75_0402_1%
150_0402_1%
12
TVB_DAC
K25
TVC_DAC
H24
TV_RTN
C31
TV_DCONSEL_0
E32
TV_DCONSEL_1
E28
CRT_BLUE
G28
CRT_GREEN
J28
CRT_RED
G29
CRT_IRTN
H32
CRT_DDC_CLK
J32
CRT_DDC_DATA
J29
CRT_HSYNC
E29
CRT_TVO_IREF
L29
CRT_VSYNC
CANTIGA ES_FCBGA1329
LVDS
TV VGA
PCI-EXPRESS GRAPHICS
PEG_COMPI
PEG_COMPO
PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
T37
T36
H44
J46
L44
L40
N41
P48
N44
T43
U43
Y43
Y48
Y36
AA43
AD37
AC47
AD39
H43
J44
L43
L41
N40
P47
N43
T42
U42
Y42
W47
Y37
AA42
AD36
AC48
AD40
J41
M46
M47
M40
M42
R48
N38
T40
U37
U40
Y40
AA46
AA37
AA40
AD43
AC46
J42
L46
M48
M39
M43
R47
N37
T39
U36
U39
Y39
Y46
AA36
AA39
AD42
AD46
3
R57
1 2
49.9_0402_1%
PEGCOMP trace width
and spacing is 20/25 mils.
TMDS_B_HPD#
TMDS_BDATA2#
TMDS_BDATA1#
TMDS_BDATA0#
TMDS_BCLK#
TMDS_BDATA2
TMDS_BDATA1
TMDS_BDATA0
TMDS_BCLK
C274 0.1U_0402_10V7K
C275 0.1U_0402_10V7K
C276 0.1U_0402_10V7K
C277 0.1U_0402_10V7K
C278 0.1U_0402_10V7K
C279 0.1U_0402_10V7K
C280 0.1U_0402_10V7K
C281 0.1U_0402_10V7K
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
+VCC_PEG
TMDS_B_HPD# 34
2
TMDS_B_DATA2# 34
TMDS_B_DATA1# 34
TMDS_B_DATA0# 34
TMDS_B_CLK# 34
TMDS_B_DATA2 34
TMDS_B_DATA1 34
TMDS_B_DATA0 34
TMDS_B_CLK 34
Strap Pin Table
CFG[2:0] FSB Freq
select
CFG[4:3]
CFG5 (DMI select)
CFG6
CFG7
(Intel Management
Engine Crypto strap)
CFG8
CFG9 (PCIE Graphics
Lane Reversal)
CFG10
(PCIE
Lookback
enable)
CFG11
CFG[13:12]
(XOR/ALLZ)
CFG[15:14]
CFG16 (FSB Dynamic ODT)
CFG[18:17]
CFG19 (DMI Lane Reversal)
CFG20
(PCIE/SDVO
concurrent)
+3VS
R71
@
4.02K_0402_1%
CFG59
CFG5
R74
@
2.21K_0402_1%
1
000 = FSB
1066MHz
010 = FSB
800MHz
011 = FSB
667MHz
Others =
Reserved
Reserved
0 = DMI x
1 = DMI x
2
4
0 = The iTPM Host Interface is
enable
1 = The iTPM Host Interface is
disable
0 =(TLS)chiper suite with no
confidentiality
1 =(TLS)chiper suite with
confidentiality
*
Reserved
0 = Reverse Lane,15->0,
14->1
1 = Normal Operation,Lane Number
in order
0 =
Enable
1 = Disable
Reserved
00 = Reserved
01 = XOR Mode
10 = All Z Mode
Enabled
Enabled
Operation
Reserved
0 =
1 =
Disabled
Enabled
Reserved
0 = Normal
Operation
1 = Reverse Lane
0 = Only PCIE or SDVO is
operational.
1 = PCIE/SDVO are operating
simu.
12
12
*
*
(Lane number in
Order)
CFG169
CFG199
CFG209
@
@
@
R72
R73
R75
(Default)11 = Normal
*
*
*
*
1 2
4.02K_0402_1%
1 2
4.02K_0402_1%
1 2
4.02K_0402_1%
*
*
+3VS
R76
@
@
@
@
@
@
@
R77
R78
R80
R82
R85
R87
1 2
2.21K_0402_1%
1 2
2.21K_0402_1%
1 2
2.21K_0402_1%
1 2
2.21K_0402_1%
1 2
2.21K_0402_1%
1 2
2.21K_0402_1%
1 2
2.21K_0402_1%
11 46Wednesday, February 18, 2009
0.1
For 3G
LVDS_ACLK+19
WWAN
LVDS_ACLK-19
LVDS_A0+19
LVDS_A0-19
LVDS_A1+19
LVDS_A1-19
LVDS_A2+19
A A
LVDS_A2-19
LVDS_ACLK+
LVDS_ACLKÂLVDS_A0+
LVDS_A0ÂLVDS_A1+
LVDS_A1ÂLVDS_A2+
LVDS_A2-
5
1
@
C60
0.1U_0402_10V6K
2
1
@
C61
0.1U_0402_10V6K
2
1
@
C62
0.1U_0402_10V6K
2
1
@
C63
0.1U_0402_10V6K
2
For 3G
LVDS_BCLK+19
WWAN
LVDS_BCLK-19
LVDS_B0+1 9
LVDS_B0-19
LVDS_B1+1 9
LVDS_B1-19
LVDS_B2+1 9
LVDS_B2-19
4
LVDS_BCLK+
LVDS_BCLKÂLVDS_B0+
LVDS_B0ÂLVDS_B1+
LVDS_B1ÂLVDS_B2+
LVDS_B2-
1
@
C1500
0.1U_0402_10V6K
2
1
@
C1501
0.1U_0402_10V6K
2
1
@
C1502
0.1U_0402_10V6K
2
1
@
C1503
0.1U_0402_10V6K
2
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2007/08/28 2006/03/10
Compal Secret Data
Deciphered Date
CFG69
CFG79
CFG89
CFG99
CFG109
2
R79
@
1 2
2.21K_0402_1%
R81
@
1 2
2.21K_0402_1%
R83
@
1 2
2.21K_0402_1%
R84
@
1 2
2.21K_0402_1%
R86
@
1 2
2.21K_0402_1%
Title
Cantiga(3/6)-VGA/LVDS/TV
Size Document Number Rev
Custom
Montevina UMA
Date: Sheet of
CFG119
CFG129
CFG139
CFG149
CFG159
CFG179
CFG189
Compal Electronics, Inc.
1
5
+3VS_DAC_BG
0.022U_0402_16V7K
C69
1
2
0.022U_0402_16V7K
C76
1
2
+3VS
220U_D2_4VM
R103
1 2
0_0603_5%
1U_0603_10V4Z
0.1U_0402_16V4Z
C70
1
2
R91
1 2
BLM18PG181SN1D_0603
0.1U_0402_16V4Z
1
2
R96
@
1 2
0_0603_5%
R97
1 2
0_0603_5%
1
C94
+
2
C102
1
2
C68
D D
+3VS_DAC_CRT
C75
+1.5VS
+VCCP
C C
B B
+3VS
R88
1 2
BLM18PG181SN1D_0603
10U_0805_10V4Z
+3VS
1
C89
0.1U_0402_16V4Z
2
R100
1 2
0_0805_5%
C95
1
2
+1.05VS_A_SM_CK
C103
1
1
2
2
+1.8V_TXLVDS
+1.5VS_PEG_BG
10U_0805_10V4Z
C96
4.7U_0805_10V4Z
10U_0805_10V4Z
C104
1
2
**RED Mark: Means UMA & dis@ Power select**
~It check by INTEL Graphics Disable Guidelines~
+3VS_DAC_CRT
+3VS_DAC_BG
+1.05VS_DPLLA
+1.05VS_DPLLB
+1.05VS_HPLL
+1.05VS_MPLL
1
C88
1000P_0402_50V7K
2
+1.05VS_PEGPLL
+1.05VS_A_SM
1
1
C97
2
2
1U_0603_10V4Z
0.1U_0402_16V4Z
1U_0603_10V4Z
C105
1
2
+3VS_TVDAC
+1.5VS
+1.5VS_TVDAC
+1.5VS_QDAC
+1.05VS_HPLL
+1.05VS_PEGPLL
+1.8V_LVDS
4
U2H
73mA
B27
VCCA_CRT_DAC
A26
VCCA_CRT_DAC
2.68mA
A25
VCCA_DAC_BG
B25
VSSA_DAC_BG
F47
VCCA_DPLLA
L48
VCCA_DPLLB
AD1
VCCA_HPLL
AE1
VCCA_MPLL
13.2mA
J48
VCCA_LVDS
J47
VSSA_LVDS
414uA
AD48
VCCA_PEG_BG
50mA
AA48
VCCA_PEG_PLL
AR20
VCCA_SM
AP20
VCCA_SM
AN20
VCCA_SM
AR17
VCCA_SM
AP17
VCCA_SM
AN17
VCCA_SM
AT16
VCCA_SM
AR16
VCCA_SM
AP16
VCCA_SM
AP28
VCCA_SM_CK
AN28
VCCA_SM_CK
AP25
VCCA_SM_CK
AN25
VCCA_SM_CK
AN24
VCCA_SM_CK
AM28
VCCA_SM_CK_NCTF
AM26
VCCA_SM_CK_NCTF
AM25
VCCA_SM_CK_NCTF
AL25
VCCA_SM_CK_NCTF
AM24
VCCA_SM_CK_NCTF
AL24
VCCA_SM_CK_NCTF
AM23
VCCA_SM_CK_NCTF
AL23
VCCA_SM_CK_NCTF
B24
VCCA_TV_DAC
A24
VCCA_TV_DAC
A32
VCC_HDA
M25
VCCD_TVDAC
L28
VCCD_QDAC
AF1
VCCD_HPLL
AA47
VCCD_PEG_PLL
M38
VCCD_LVDS
L37
VCCD_LVDS
60.31mA
CANTIGA ES_FCBGA1329
64.8mA
64.8mA
24mA
139.2mA
720mA
26mA
26mA
TVA 24.15mA
TVB 39.48mA
TVX 24.15mA
50mA
58.67mA
48.363mA
157.2mA
50mA
CRTPLLA PEGA SMTV
A LVDSHDA
POWER
A CK
105.3mA
1732mA
D TV/CRT
LVDS
852mA
SM CK
118.8mA
VCC_TX_LVDS
DMI
456mA
VTT
321.35mA
VCC_AXF
VCC_AXF
VCC_AXF
AXF
124mA
VCC_SM_CK
VCC_SM_CK
VCC_SM_CK
VCC_SM_CK
VCC_HV
VCC_HV
VCC_HV
HV
VCC_PEG
VCC_PEG
VCC_PEG
VCC_PEG
VCC_PEG
PEG
VCC_DMI
VCC_DMI
VCC_DMI
VCC_DMI
VTTLF
VTTLF
VTTLF
VTTLF
3
+VCCP
U13
VTT
T13
VTT
U12
VTT
T12
VTT
U11
VTT
T11
VTT
U10
VTT
T10
VTT
U9
VTT
T9
VTT
U8
VTT
T8
VTT
U7
VTT
T7
VTT
U6
VTT
T6
VTT
U5
VTT
T5
VTT
V3
VTT
U3
VTT
V2
VTT
U2
VTT
T2
VTT
V1
VTT
U1
VTT
B22
B21
A21
BF21
BH20
BG20
BF20
K47
C35
B35
A35
V48
U48
V47
U47
U46
AH48
AF48
AH47
AG47
A8
L1
AB2
C110
0.47U_0603_10V7K
+V1.05VS_AXF
+1.8V_SM_CK
+1.8V_TXLVDS
+VCC_PEG
+1.05VS_DMI
0.47U_0603_10V7K
C111
1
2
1
C71
2
1
C80
2
1
2
4.7U_0805_10V4Z
220U_D2_4VM
C72
1
+
2
4.7U_0805_10V4Z
0.47U_0603_10V7K
C81
+3VS_HV
C107
0.47U_0603_10V7K
C112
1
2
2.2U_0805_16V4Z
1
1
C82
2
2
0.1U_0402_16V4Z
1
2
0.1U_0402_16V4Z
C86
1
2
0.1U_0402_16V4Z
C73
C87
+1.05VS_PEGPLL
2
+1.05VS_DPLLA +VCCP
1 2
R90
10U_0805_10V4Z
0.1U_0402_16V4Z
1
2
10U_0805_10V4Z
1
2
+1.05VS_HPLL
+1.05VS_MPLL
C99
10U_FLC-453232-100K_0.25A_10%
C74
1
2
C91
1
2
10U_0805_10V4Z
10U_0805_10V4Z
1
C100
10U_0805_10V4Z
2
1
2
+VCCP+1.05VS_DPLLB
R98
1 2
MBK2012121YZF_0805
R101
1 2
MBK2012121YZF_0805
L1
1 2
BLM18PG121SN1D_0603
C108
+VCCP
R94
1 2
10U_FLC-453232-100K_0.25A_10%
0.1U_0402_16V4Z
C90
1
2
1
2
0.1U_0402_16V4Z
C106
1
2
2 1
+3VS
+VCCP
+VCCP
+VCCP
+VCCP_D
D3
CH751H-40PT_SOD323-2
@
C83
R105
1 2
10_0402_5%
+V1.05VS_AXF
+1.8V_SM_CK
10U_0805_10V4Z
1
2
+1.5VS_TVDAC
+VCC_PEG
C98
+1.05VS_DMI
10U_0805_10V4Z
1
2
C84
1
2
1
C92
2
1
+
2
1
2
R106
1 2
0_0402_5%
C78
10U_0805_10V4Z
0.022U_0402_16V7K
220U_D2_4VM
0.1U_0402_16V4Z
C109
1
1
C93
2
C101
1
2
R104
1 2
0_0603_5%
1U_0603_10V4Z
0.1U_0402_16V4Z
1
2
1
2
0.1U_0402_16V4Z
10U_0805_10V4Z
C79
C85
R99
1 2
0_0805_5%
R102
1 2
0_0805_5%
+VCCP
+3VS_HV
R93
1 2
0_0603_5%
R95
1 2
0_0805_5%
+VCCP
+VCCP
+1.8V
+1.5VS
+1.8V_LVDS
R107
1 2
1U_0603_10V4Z
10U_0805_10V4Z
+3VS_TVDAC
A A
0.022U_0402_16V7K
C117
1
2
C118
1
2
R111
1 2
BLM18PG181SN1D_0603
0.1U_0402_16V4Z
5
+3VS
+1.5VS_QDAC
C119
1
2
0.022U_0402_16V7K
0.1U_0402_16V4Z
C120
1
2
4
R112
1 2
100_0603_1%
+1.5VS
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2007/08/28 2006/03/10
Compal Secret Data
Deciphered Date
1
2
2
0_0603_5%
C114
C113
1
2
+1.8V
Title
Size Document Number Rev
Custom
Date: Sheet of
Compal Electronics, Inc.
Cantiga(4/6)-PWR
Montevina UMA
40 mils
+1.8V_TXLVDS
1000P_0402_50V7K
1
2
1
R108
1 2
0_0603_5%
C116
+1.8V
0.1
12 46Wednesday, February 18, 2009
5
4
3
2
1
W28
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16
AV44
BA37
AM40
AV21
AY5
AM10
BB13
+VCCP
VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7
0.1U_0402_16V4Z
1
C127
2
0.22U_0402_10V4Z
C139 0.1U_0402_16V4Z
1
2
4.7U_0603_6.3V6M
1
1
C128
C129
2
2
C140 0.1U_0402_16V4Z
C141 0.22U_0603_10V7K
1
1
1
2
2
2
C144 1U_0603_10V4Z
C143 0.47U_0402_6.3V6K
C142 0.22U_0603_10V7K
1
2
C145 1U_0603_10V4Z
1
1
2
2
U2G
3000mA
Extnal Graphic: 1210.34mA
integrated Graphic: 1930.4mA
+VCCP
D D
0.1U_0402_16V4Z
0.22U_0402_10V4Z
0.22U_0402_10V4Z
10U_0805_10V4Z
220U_D2_4VM
1
C124
C131
+
2
C C
B B
C132
1
1
2
2
C125
C133
1
1
2
2
U2F
AG34
VCC
AC34
VCC
AB34
VCC
AA34
VCC
Y34
VCC
V34
VCC
U34
VCC
AM33
VCC
AK33
VCC
AJ33
VCC
AG33
VCC
AF33
VCC
AE33
VCC
AC33
VCC
AA33
VCC
Y33
VCC
W33
VCC
V33
VCC
U33
VCC
AH28
VCC
AF28
VCC
AC28
VCC
AA28
VCC
AJ26
VCC
AG26
VCC
AE26
VCC
AC26
VCC
AH25
VCC
AG25
VCC
AF25
VCC
AG24
VCC
AJ23
VCC
AH23
VCC
AF23
VCC
T32
VCC
CANTIGA ES_FCBGA1329
VCC CORE
+VCCP
AM32
VCC_NCTF
AL32
VCC_NCTF
AK32
VCC_NCTF
AJ32
VCC_NCTF
AH32
VCC_NCTF
AG32
VCC_NCTF
AE32
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23
POWER
VCC NCTF
SI-1 Add C for GM47
+1.8V
1U_0603_10V4Z
330U_D2E_2.5VM_R7
1
1
C134
GM47@
+
C1508
2
2
22P_0402_25V8K
@
1
C1490
2
22P_0402_25V8K
@
1
C1493
2
Reserve for WWAN
330U_D2E_2.5VM_R7
1
+
2
10U_0805_10V4Z
330U_D2E_2.5VM_R7
1
+
C135
2
22P_0402_25V8K
1
2
22P_0402_25V8K
1
2
10U_0805_10V4Z
C126
C122
1
2
0317 change value
1
C136
2
10U_0805_10V4Z
22P_0402_25V8K
@
C1491
22P_0402_25V8K
@
C1494
10U_0805_10V4Z
C130
1
2
+VCCP
0.1U_0402_16V4Z
1
C137
2
@
1
C1492
2
@
1
C1495
2
0.01U_0402_16V7K
2
1
1
C138
2
T42PA D
T43PA D
AP33
VCC_SM
AN33
VCC_SM
BH32
VCC_SM
BG32
VCC_SM
BF32
VCC_SM
BD32
VCC_SM
BC32
C123
BB32
BA32
AY32
AW32
AV32
AU32
AT32
AR32
AP32
AN32
BH31
BG31
BF31
BG30
BH29
BG29
BF29
BD29
BC29
BB29
BA29
AY29
AW29
AV29
AU29
AT29
AR29
AP29
BA36
BB24
BD16
BB21
AW16
AW13
AT13
AE25
AB25
AA25
AE24
AC24
AA24
AE23
AC23
AB23
AA23
AJ21
AG21
AE21
AC21
AA21
AH20
AF20
AE20
AC20
AB20
AA20
AM15
AL15
AE15
AJ15
AH15
AG15
AF15
AB15
AA15
AN14
AM14
AJ14
AH14
Y26
Y24
Y21
T17
T16
Y15
V15
U15
U14
T14
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
6326.84mA
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG_SENSE
VSS_AXG_SENSE
VCC SMVCC GFX
POWER
VCC GFX NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC SM LF
A A
CANTIGA ES_FCBGA1329
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2007/08/28 2006/03/10
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet of
Compal Electronics, Inc.
Cantiga(5/6)-PWR/GND
Montevina UMA
1
13 46Wednesday, February 18, 2009
0.1
5
4
3
2
1
U2I
AU48
VSS
AR48
VSS
AL48
VSS
BB47
VSS
AW47
VSS
AN47
VSS
AJ47
VSS
AF47
D D
C C
B B
A A
VSS
AD47
VSS
AB47
VSS
Y47
VSS
T47
VSS
N47
VSS
L47
VSS
G47
VSS
BD46
VSS
BA46
VSS
AY46
VSS
AV46
VSS
AR46
VSS
AM46
VSS
V46
VSS
R46
VSS
P46
VSS
H46
VSS
F46
VSS
BF44
VSS
AH44
VSS
AD44
VSS
AA44
VSS
Y44
VSS
U44
VSS
T44
VSS
M44
VSS
F44
VSS
BC43
VSS
AV43
VSS
AU43
VSS
AM43
VSS
J43
VSS
C43
VSS
BG42
VSS
AY42
VSS
AT42
VSS
AN42
VSS
AJ42
VSS
AE42
VSS
N42
VSS
L42
VSS
BD41
VSS
AU41
VSS
AM41
VSS
AH41
VSS
AD41
VSS
AA41
VSS
Y41
VSS
U41
VSS
T41
VSS
M41
VSS
G41
VSS
B41
VSS
BG40
VSS
BB40
VSS
AV40
VSS
AN40
VSS
H40
VSS
E40
VSS
AT39
VSS
AM39
VSS
AJ39
VSS
AE39
VSS
N39
VSS
L39
VSS
B39
VSS
BH38
VSS
BC38
VSS
BA38
VSS
AU38
VSS
AH38
VSS
AD38
VSS
AA38
VSS
Y38
VSS
U38
VSS
T38
VSS
J38
VSS
F38
VSS
C38
VSS
BF37
VSS
BB37
VSS
AW37
VSS
AT37
VSS
AN37
VSS
AJ37
VSS
H37
VSS
C37
VSS
BG36
VSS
BD36
VSS
AK15
VSS
AU36
VSS
CANTIGA ES_FCBGA1329
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
AD12
AY24
AT24
AJ24
AH24
AF24
AB24
R24
L24
K24
J24
G24
F24
E24
BH23
AG23
Y23
B23
A23
AJ6
U2J
BG21
VSS
L12
VSS
AW21
VSS
AU21
VSS
AP21
VSS
AN21
VSS
AH21
VSS
AF21
VSS
AB21
VSS
R21
VSS
M21
VSS
J21
VSS
G21
VSS
BC20
VSS
BA20
VSS
AW20
VSS
AT20
VSS
AJ20
VSS
AG20
VSS
Y20
VSS
N20
VSS
K20
VSS
F20
VSS
C20
VSS
A20
VSS
BG19
VSS
A18
VSS
BG17
VSS
BC17
VSS
AW17
VSS
AT17
VSS
R17
VSS
M17
VSS
H17
VSS
C17
VSS
BA16
VSS
AU16
VSS
AN16
VSS
N16
VSS
K16
VSS
G16
VSS
E16
VSS
BG15
VSS
AC15
VSS
W15
VSS
A15
VSS
BG14
VSS
AA14
VSS
C14
VSS
BG13
VSS
BC13
VSS
BA13
VSS
AN13
VSS
AJ13
VSS
AE13
VSS
N13
VSS
L13
VSS
G13
VSS
E13
VSS
BF12
VSS
AV12
VSS
AT12
VSS
AM12
VSS
AA12
VSS
J12
VSS
A12
VSS
BD11
VSS
BB11
VSS
AY11
VSS
AN11
VSS
AH11
VSS
Y11
VSS
N11
VSS
G11
VSS
C11
VSS
BG10
VSS
AV10
VSS
AT10
VSS
AJ10
VSS
AE10
VSS
AA10
VSS
M10
VSS
BF9
VSS
BC9
VSS
AN9
VSS
AM9
VSS
AD9
VSS
G9
VSS
B9
VSS
BH8
VSS
BB8
VSS
AV8
VSS
AT8
VSS
CANTIGA ES_FCBGA1329
VSS
AH8
VSS
Y8
VSS
L8
VSS
E8
VSS
B8
VSS
AY7
VSS
AU7
VSS
AN7
VSS
AJ7
VSS
AE7
VSS
AA7
VSS
N7
VSS
J7
VSS
BG6
VSS
BD6
VSS
AV6
VSS
AT6
VSS
AM6
VSS
M6
VSS
C6
VSS
BA5
VSS
AH5
VSS
AD5
VSS
Y5
VSS
L5
VSS
J5
VSS
H5
VSS
F5
VSS
BE4
VSS
BC3
VSS
AV3
VSS
AL3
VSS
R3
VSS
P3
VSS
F3
VSS
BA2
VSS
AW2
VSS
AU2
VSS
AR2
VSS
AP2
VSS
AJ2
VSS
AH2
VSS
AF2
VSS
AE2
VSS
AD2
VSS
AC2
VSS
Y2
VSS
M2
VSS
K2
VSS
AM1
VSS
AA1
VSS
P1
VSS
H1
VSS
U24
VSS
U28
VSS
U25
VSS
U29
VSS
AF32
VSS_NCTF
AB32
VSS_NCTF
V32
VSS_NCTF
AJ30
VSS_NCTF
AM29
VSS_NCTF
AF29
VSS_NCTF
AB29
VSS_NCTF
U26
VSS_NCTF
U23
VSS_NCTF
AL20
VSS_NCTF
V20
VSS_NCTF
AC19
VSS_NCTF
AL17
VSS_NCTF
AJ17
VSS_NCTF
VSS NCTF
VSS SCB
NC
VSS_NCTF
VSS_NCTF
VSS_SCB
VSS_SCB
VSS_SCB
VSS_SCB
VSS_SCB
AA17
U17
BH48
BH1
A48
C1
A3
E1
NC
D2
NC
C3
NC
B4
NC
A5
NC
A6
NC
A43
NC
A44
NC
B45
NC
C46
NC
D47
NC
B47
NC
A46
NC
F48
NC
E48
NC
C48
NC
B48
NC
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2007/08/28 2006/03/10
Compal Secret Data
Deciphered Date
Title
Size Document Number Rev
Custom
2
Date: Sheet of
Compal Electronics, Inc.
Cantiga(6/6)-PWR/GND
Montevina UMA
1
14 46Wednesday, February 18, 2009
0.1
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