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DV3 CQ35 LA-4731P R10-DIS-0216
Schematics
51 pgs1.71 Mb1

HP DV3 CQ35 LA-4731P R10-DIS-0216 Schematics

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E
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
D
2008/12/10 2008/12/10
2008/12/10 2008/12/10
2008/12/10 2008/12/10
E
Cover Sheet
Cover Sheet
Cover Sheet
LA-4731P Rhett discrete
LA-4731P Rhett discrete
LA-4731P Rhett discrete
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Custom
Custom
Custom
D
Deciphered Date
Deciphered Date
Deciphered Date
C
Security Classification
Security Classification
Security Classification
C
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
REV : 1.0
2009-02-13
B
B
Schematics Document
Mobile Penryn uFCPGA with Intel
Cantiga_PM+ICH9-M core logic
A
A
Compal confidential
1 1
2 2
3 3
4 4
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P35
P39
of
of
of
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CIR Conn
E
P32
5 in1 Slot
TPA6047
P29
P36
P15, 16
P17
D
72QFN
Clock Generator
SLG8SP553V
CK505
BAK 0, 1, 2, 3
DDR2 SO-DIMM X2
DDR2 800 MHz 1.8V
P36
USB conn x3
Dual Channel
BT Conn
USB2.0 X12
USB Camera
P19
P36
P32
Finger print
CardReader
P33 P35
Codec_IDT92HD75B
Audio CKT AMP & Audio Jack
SATA ODD Connector
P29
P29
e-SATA Connector
With 3'th USB
Capsense switch Conn
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
E
Block Diagram
Block Diagram
Block Diagram
LA-4731P Rhett discrete
LA-4731P Rhett discrete
LA-4731P Rhett discrete
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Custom
Custom
Custom
D
Deciphered Date
Deciphered Date
Deciphered Date
P6,7, 8
C
Mobile Penryn
FSB
667/800/1066 MHz 1.05V
P9, 10, 11, 12, 13, 14
FCBGA 1329
uFCPGA-478 CPU
H_A#(3..35)
H_D#(0..63)
Intel Cantiga MCH
P6
B
Thermal Sensor
EMC1402
P6
PEG X16
Fan conn
Montevina Consumer Discrete
P19
C-Link
DMI X4
SATA Master-1
Azalia
SATA Slave
SATA Slave
P25,26,27,28
mBGA-676
Intel ICH9-M
PCI-E BUS*5
P31
ew Card
P31
LPC BUS
P38
EE
KB926 (D2)
P38
Int.KBD
P37
SPI
SPI ROM
25LF080A
P39
Touch Pad CO.
2008/11/04 2008/11/04
2008/11/04 2008/11/04
2008/11/04 2008/11/04
C
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Security Classification
Security Classification
Security Classification
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
page 23,24
VRAM DDR2
128/512MB
A
Compal confidential
1 1
500 MHz
Discrete
64bits
P20,21,22
vidia
10M-GE1-S
P18
LVDS Panel
CRT
Interface
2 2
P42
Support V1.3
HDMI
WLA% & WA%
Mini-Card*2
P30
Realtek
8111DL(Gbe)
P30
P39
RJ45/11 CO
LED SATA HDD Connector
3 3
P26
RTC CKT.
P41
DC/DC Interface CKT.
4 4
A
: means Digital Ground
: means Analog Ground
Symbol Note :
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USB-4 Camera
USB-5 WLAN
USB-6 Bluetooth
USB-1 Left side
USB-3 Dock
USB-2 Left side
USB-0 Right side(with ESATA)
USB assignment:
USB-8 MiniCard(WWAN/TV)
USB-7 Finger Printer
USB-9 Express card
USB-10 X
USB-11 X
PCIe assignment:
PCIe-2 X
PCIe-1 TV tuner/WWAN/Robeson
PCIe-3 WLAN
PCIe-6 New Card
PCIe-4 GLAN (Marvell)
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%otes List
%otes List
%otes List
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
LA-4731P Rhett discrete
LA-4731P Rhett discrete
LA-4731P Rhett discrete
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Custom
Custom
Custom
Deciphered Date
Deciphered Date
Deciphered Date
1 0 1 0 0 1 0 0A4
1 0 1 0 0 0 0 0
ADDRESS
X
X
G-sensor
V
HEX
X
V
N10M
A
N10M
Thermal
Sensor
X
VXX
A0
1 1 0 1 0 0 1 0
D2
@ : means just reserve , no build
BOM
NB SA00002JJ80 R1 FRU
NB SA00002JJE0 R3
SB SA00002JH50 R1 FRU
SB SA00002JHB0 R3
+3VS
+5VS
+1.5VS
45@ : means need be mounted when 45 level assy or rework stage.
BATT @ : means need be mounted when 45 level assy or rework stage.
DEBUG@ : means just reserve for debug.
+0.9V
+2.5VS
+CPU_CORE
+VCCP
+1.8VS
+NVVDD
+PCIE
+1.8V
GS @ : means just reserve for G sensor
FP @ : means just reserve for Finger Print
CONN@ : means ME part
ESATA @ : means just reserve for ESATA
O
O
Main@ : means just reserve for Main stream
NewC@ : means just reserve for New card
O
X
O
O
PA @ : means just reserve for PA
OPP@ : means just reserve for OPP
X
X
PR @ : means just reserve for PR
2MiniC@ : means just reserve for 2nd Mini card slot
X
X
X
X
V
Sensor board
X
MINI CARD
X
X
SODIMM CLK CHIP
X
Thermal
Sensor
X
I2C / SMBUS ADDRESSING
DEVICE
CLOCK GENERATOR (EXT.)
DDR SO-DIMM 1
DDR SO-DIMM 0
X X
X
HDCP
X
X
X
V V V
X
V
HDMI
X
V
X
2008/11/04 2008/11/04
2008/11/04 2008/11/04
2008/11/04 2008/11/04
A
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Security Classification
Security Classification
Security Classification
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
X MEANS
OFF
O MEANS ON
Voltage Rails
power
plane
+5VALW
+B
+3VALW
State
O
O
O
O
X
XX
O
O
O
O
O
S3
S1
S0
S5 S4/AC
S5 S4/ Battery only
S5 S4/AC & Battery
don't exist
SERIAL
EEPROM
INVERTER BATT
SOURCE
SMBUS Control Table
1 1
X
V
X
X V
X
KB926
KB926
SMB_EC_CK2
SMB_EC_DA2
SMB_EC_CK1
SMB_EC_DA1
X
V
SOURCE LVDS CRT
DDC2_DATA
X X
X
V
N10M
N10M
DDC2_CLK
3VDDCDA
3VDDCCL
X
X
ICH9
ICH_SMBCLK
ICH_SMBDATA
NB9M SMBUS Control Table
X
X VX
X
X
N10M
N10M
HDMIDAT_VGA
HDMICLK_VGA
HDCP_SDA
HDCP_SCL
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1
Finger printer
PC Camera
50mA
50mA
2
3
+3VS_DVDD
ALC268
25mA
ICH9
177mA
MDC 1.5
35mA
LAN
300mA
New card
Mini card (WLAN)
1A
1A
+3VAUX_BT
+3VALW_EC
60mA
20mA
ICH9
278mA
5.39A5.89A
SPI ROM
10mA
LVDS CON
+LCDVDD
1.5A
+3VS
JMB385
550mA
+3VS_CK505
N10M (VGA)
250mA
390mA
ICH_VCC1_5
ICH9
657mA
2.2A0.3A
Mini card (WWAN/WLAN)
1A
+VDDA
IDT 9275B
35mA
+5VS
ICH9
1.56A
1.3A0.58A
+5VAMP
10mA
ODD
SATA
1.8A
700mA
MCH
N10M (VGA)
3.7A
360mA
ICH9
MCH
1.26A
1.17A
DDR2 800Mhz 4G x2
+0.9V
50mA
8 A
2.3A
+VCCP
4.7A
CPU
CPU
2.725A
34A/1.025V
1
Power delivery
Power delivery
Power delivery
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
LA-4731P Rhett discrete
LA-4731P Rhett discrete
LA-4731P Rhett discrete
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet C
C
C
2
Deciphered Date
Deciphered Date
Deciphered Date
Compal Secret Data
Compal Secret Data
Compal Secret Data
2008/11/04 2008/11/04
2008/11/04 2008/11/04
2008/11/04 2008/11/04
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Security Classification
Security Classification
Security Classification
3
N10M (VGA)
N10M (VGA)
2A/1.1V
+3VALW
4
+V_BATTERY Dock con
1A
5
LVDS CON
INVPWR_B+
0.3A
1.7A
B++
2A
+1.5VS
VIN
AC
D D
C C
+5VALW
B+
7A
12.11A1.9A
BATT
3.7 X 3=11.1V
DC
B B
+1.8V
B+++
10mA2A
CPU_B+ +VCC_CORE
0.27A
A A
+NVVDDP +NVVDD
0.19A
4
+1.1V_PCIE +PCIE
5
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Power sequence
Power sequence
Power sequence
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
LA-4731P Rhett discrete
LA-4731P Rhett discrete
LA-4731P Rhett discrete
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Custom
Custom
Custom
Deciphered Date
Deciphered Date
Deciphered Date
2008/11/04 2008/11/04
2008/11/04 2008/11/04
2008/11/04 2008/11/04
A
Security Classification
Security Classification
Security Classification
A
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1 1
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+VCCP
+3VS
SMB_EC_DA2 21,37
1
1 2
1 2
1 2
R4 54.9_0402_1%
R4 54.9_0402_1%
R2 54.9_0402_1%
R2 54.9_0402_1%
R3 54.9_0402_1%
R3 54.9_0402_1%
1 2
1 2
This shall place near CPU
R7 54.9_0402_1%
R7 54.9_0402_1%
R8 54.9_0402_1%
R8 54.9_0402_1%
Change value in 5/02
XDP_TDI
XDP_TMS
2
XDP_TDO
XDP_TRST#
XDP_TCK
+3VS
SMB_EC_CK2 21,37
R71810K_0402_5% R71810K_0402_5%
5
G14G2
11223
JFAN1
CONN@
JFAN1
CONN@
ACES_85204-03001
1 2
SMB_EC_DA2
SMB_EC_CK2
6
8
5
7
GND
SMCLK
ALERT#
SMDATA
DN3DP2VDD
THERM#
U1
U1
1
H_THERMDC
H_THERMDA
C2
C2
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2200P_0402_50V7K
2200P_0402_50V7K
C3
C3
1 2
Address:100_1100
EMC1402-1-ACZL-TR_MSOP8
EMC1402-1-ACZL-TR_MSOP8
4
THERM#
R16
10K_0402_5%
R16
10K_0402_5%
1 2
+3VS
Line to be protected
Vcc3GND
D17
DLPT05-7-F_SOT23-3
D17
DLPT05-7-F_SOT23-3
2
1
3
FAN_SPEED
+5VS_FAN
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
ACES_85204-03001
C60
C60
1
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
6 51Monday, February 16, 2009
6 51Monday, February 16, 2009
6 51Monday, February 16, 2009
1
Penryn(1/3)-AGTL+/ITP-XDP
Penryn(1/3)-AGTL+/ITP-XDP
Penryn(1/3)-AGTL+/ITP-XDP
LA-4731P Rhett discrete
LA-4731P Rhett discrete
LA-4731P Rhett discrete
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Custom
Custom
Custom
2
Deciphered Date
Deciphered Date
Deciphered Date
ZZZ2
ZZZ2
ZZZ1
ZZZ1
2008/11/04 2008/11/04
2008/11/04 2008/11/04
2008/11/04 2008/11/04
3
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Security Classification
Security Classification
Security Classification
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
PCB
PR@
PCB
PR@
PCB
PA@
PCB
PA@
1
Fan Control circuit
+5VS +5VS+3VS
SI-1 Change to voltage control circuit
3
H_THERMDC
H_THERMDAH_THERMDA_R
+VCCP
XDP_DBRESET# 27
T1@T1
@
H_RS#0 9
H_RS#1 9
H_DEFER# 9
H_ADS# 9
H_BNR# 9
H_DRDY# 9
H_DBSY# 9
H_BR0# 9
H_BPRI# 9
4
H_BNR#
H_ADS#
H_BPRI#
H_DEFER#
H1
E2
G5
H5
ADS#
BNR#
BPRI#
DEFER#
ADDR GROUP_0
ADDR GROUP_0
A[3]#
A[4]#L5A[5]#L4A[6]#K5A[7]#M3A[8]#N2A[9]#
JCPU1A
JCPU1A
J4
H_DBSY#
H_DRDY#
H_BR0#
F1
E1
F21
BR0#
DBSY#
DRDY#
A[10]#N3A[11]#P5A[12]#P2A[13]#L2A[14]#P4A[15]#P1A[16]#
J1
H_INIT# 26
H_INIT#
H_IERR#
D20
B3
INIT#
IERR#
H_LOCK# 9
H_RESET#
H_LOCK#
H4
C1
LOCK#
CONTROL
CONTROL
ADSTB[0]#
R1
M1
H_RS#2 9
H_RESET# 9
H_TRDY# 9
H_TRDY#
H_RS#1
H_RS#2
H_RS#0
G3
G2
RS[0]#F3RS[1]#F4RS[2]#
TRDY#
RESET#
REQ[0]#K3REQ[1]#H2REQ[2]#K2REQ[3]#J3REQ[4]#
L1
H_HIT# 9
H_HITM# 9
H_HITM#
H_HIT#
G6
E4
HIT#
HITM#
A[17]#Y2A[18]#U5A[19]#R3A[20]#W6A[21]#U4A[22]#Y5A[23]#U1A[24]#R4A[25]#T5A[26]#T3A[27]#W2A[28]#W5A[29]#
XDP_TCK
AD4
AD3
AD1
AC4
AC2
AC1
AC5
PRDY#
PREQ#
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
ADDR GROUP_1
ADDR GROUP_1
XDP_TDO
XDP_TDI
AA6
TDI
TCK
AB3
XDP_TRST#
XDP_TMS
XDP_DBRESET#
C20
AB5
AB6
TDO
TMS
DBR#
TRST#
A[30]#U2A[31]#
Y4
V4
XDP/ITP SIGNALS
XDP/ITP SIGNALS
A[32]#W3A[33]#
1 2
1 2
R14 0_0402_5%
R14 0_0402_5%
R13 56_0402_1%
R13 56_0402_1%
H_PROCHOT#
D21
A24
THERMDA
PROCHOT#
THERMAL
THERMAL
ADSTB[1]#
A[34]#
A[35]#
V1
AA4
AB2
AA3
1 2
H_THERMTRIP# 9,26
R15 0_0402_5%
R15 0_0402_5%
H_THERMTRIP#
H_THERMDC_R
C7
B25
THERMDC
THERMTRIP#
ICH
ICH
A20M#
FERR#
IGNNE#
A6
A5
C4
D5
H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil
CLK_CPU_BCLK 17
CLK_CPU_BCLK# 17
CLK_CPU_BCLK#
CLK_CPU_BCLK
A22
A21
BCLK[0]
BCLK[1]
H CLK
H CLK
LINT0C6LINT1
STPCLK#
B4
SMI#
A3
RSVD[01]M4RSVD[02]N5RSVD[03]T2RSVD[04]V3RSVD[05]B2RSVD[06]D2RSVD[07]
D22
RSVD[08]
RSVD[09]
F6
D3
RESERVED
RESERVED
Penryn
Penryn
2
C4 2.2U_0603_6.3V4Z
C4 2.2U_0603_6.3V4Z
1
U51
U51
VEN
Thermal Pad
9
R50
10K_0402_5%
R50
10K_0402_5%
1 2
FAN_SPEED37
1
2VO3
4
VIN
VSET
GND8GND7GND6GND
1
C5
C5
5
C41
C41
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
FAN_SET37
G996RD1U_TDFN8_3X3
G996RD1U_TDFN8_3X3
1000P_0402_50V7K
1000P_0402_50V7K
2
OCP# 27
H_A#3
5
H_A#[3..16]9
D D
H_A#5
H_A#4
H_A#7
H_A#6
H_A#8
H_A#9
H_A#10
H_A#11
H_A#13
H_A#12
H_A#15
H_A#14
H_ADSTB#0
H_A#16
H_ADSTB#09
H_REQ#2
H_REQ#1
H_REQ#0
H_REQ#09
H_REQ#19
H_REQ#4
H_REQ#3
H_REQ#29
H_REQ#39
H_A#32
H_A#34
H_A#35
H_A#18
H_A#17
H_A#19
H_REQ#49
H_A#[17..35]9
C C
H_A#21
H_A#20
H_A#23
H_A#22
H_A#25
H_A#24
H_A#26
H_A#27
H_A#28
H_A#30
H_A#29
H_A#31
H_A#33
H_ADSTB#1
H_A20M#
H_FERR#
H_A20M#26
H_ADSTB#19
H_IGNNE#
H_FERR#26
H_IGNNE#26
H_SMI#
H_STPCLK#
H_INTR
H_NMI
H_STPCLK#26
H_INTR26
H_NMI26
R18
56_0402_5%
R18
56_0402_5%
C
56_0402_5%
56_0402_5%
2
B
B
C
Q1
MMBT3904_NL_SOT23-3
Q1
MMBT3904_NL_SOT23-3
+VCCP
E
E
@
@
3 1
H_PROCHOT# OCP#
R17
@
R17
@
12
+VCCP
H_SMI#26
B B
1 2
H_IERR#
A A
5
www.rosefix.com
0.1
0.1
0.1
of
of
of
+1.5VS
C8
C8
1
1
C7
C7
W21
VCCP[16]
B26
C26
VCCA[01]
VCCA[02]
AD6
CPU_VID0 46
AF5
VID[0]
1
CPU_VID1 46
VID[1]
AE5
CPU_VID2 46
AF4
VID[2]
CPU_VID3 46
VID[3]
C6
330U_D2E_2.5VM_R7
C6
330U_D2E_2.5VM_R7
+
+
1
0_0402_5%
0_0402_5%
R20
R20
1 2
+VCCPB
V6
VCCP[03]J6VCCP[04]K6VCCP[05]M6VCCP[06]
VCCP[02]
J21
2
K21
M21
VCCP[07]
VCCP[08]
N21
VCCP[09]
VCCP[10]N6VCCP[11]
R21
VCCP[12]R6VCCP[13]
T21
VCCP[14]T6VCCP[15]
V21
+VCCP
0_0402_5%
0_0402_5%
R19
R19
1 2
+VCCPA
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
G21
2
VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]
VCCP[01]
2
2
CPU_VID4 46
AE3
VID[4]
CPU_VID5 46
AF3
VID[5]
10U_0805_6.3V6M
10U_0805_6.3V6M
AE2
0.01U_0402_16V7K
0.01U_0402_16V7K
CPU_VID6 46
VID[6]
Near pin B26
VSSSENSE 46
VCCSENSE 46
VSSSENSE
VCCSENSE
AF7
AE7
VSSSENSE
VCCSENSE
Length match within 25 mils.
.
.
The trace width/space/other is 20/7/25.
VCCSENSE
1 2
R28 100_0402_1%R28 100_0402_1%
+VCC_CORE
VSSSENSE
1 2
Close to CPU pin within
500mils.
R30 100_0402_1%R30 100_0402_1%
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
7 51Monday, February 16, 2009
7 51Monday, February 16, 2009
7 51Monday, February 16, 2009
1
Penryn(2/3)-AGTL+/ITP-XDP
Penryn(2/3)-AGTL+/ITP-XDP
Penryn(2/3)-AGTL+/ITP-XDP
LA-4731P Rhett discrete
LA-4731P Rhett discrete
LA-4731P Rhett discrete
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Custom
Custom
Custom
2
VCC[001]A7VCC[002]A9VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]B7VCC[011]B9VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]C9VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]D9VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]E7VCC[034]E9VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]F7VCC[043]F9VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
JCPU1C
JCPU1C
F10
F12
F14
F15
F17
F18
R26
R26
12
R25
R25
12
R24
R24
12
R23
R23
12
F20
AA7
AA9
AA10
27.4_0402_1%
27.4_0402_1%
54.9_0402_1%
54.9_0402_1%
27.4_0402_1%
27.4_0402_1%
54.9_0402_1%
54.9_0402_1%
AA12
AA13
AA15
AA17
AA18
AA20
AB9
A10
A12
A13
A15
A17
A18
A20
B10
B12
B14
B15
B17
B18
B20
C10
C12
C13
C15
C17
C18
D10
D12
+VCC_CORE +VCC_CORE
3
E10
E12
E13
E15
E17
E18
D14
D15
D17
D18
E20
Resistor placed within 0.5"
H_D#[32..47] 9
H_D#35
H_D#37
H_D#34
H_D#33
H_D#32
4
Y22
D[32]#
D[0]#
JCPU1B
JCPU1B
E22
AB24
V24
D[33]#
DATA GRP 0
DATA GRP 0
D[1]#
F24
E26
V26
D[34]#
D[2]#
G22
H_D#41
H_D#39
H_D#40
H_D#38
H_D#36
V23
T22
U25
U23
Y25
W22
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
DATA GRP 2DATA GRP 3
DATA GRP 2DATA GRP 3
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
F23
E25
E23
K24
G25
G24
H_D#43
H_D#42
Y23
W24
D[42]#
D[43]#
D[10]#
D[11]#
J24
J23
H_D#45
H_D#44
W25
AA23
D[44]#
D[45]#
D[12]#
D[13]#
F26
H22
H_D#46
H_D#47
AA24
AB25
D[46]#
D[14]#
K22
H23
H_DSTBN#2 9
H_DSTBP#2 9
H_DINV#2
H_DSTBN#2
H_DSTBP#2
U22
Y26
AA26
D[47]#
DSTBP[2]#
DSTBN[2]#
D[15]#
DSTBN[0]#
DSTBP[0]#
J26
H25
H26
H_DINV#2 9
H_D#[48..63] 9
DINV[2]#
DINV[0]#
H_D#48
H_D#49
AE24
AD24
D[48]#
D[16]#
K25
N22
H_D#50
AA21
D[49]#
D[50]#
D[17]#
D[18]#
P26
H_D#51
AB22
D[51]#
D[19]#
R23
H_D#56
H_D#52
H_D#55
H_D#54
H_D#53
AB21
AC26
AD20
AE22
AF23
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
DATA GRP 1
DATA GRP 1
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
L23
L22
P25
M24
M23
H_D#58
H_D#57
AC25
AE21
D[57]#
D[25]#
P23
P22
H_D#59
AD21
D[58]#
D[26]#
T24
H_D#60
AC22
D[59]#
D[27]#
R24
H_D#61
AD23
D[60]#
D[61]#
D[28]#
D[29]#
L25
H_D#63
H_D#62
AF22
AC23
D[62]#
D[63]#
D[30]#
D[31]#
T25
N25
H_DSTBN#3 9
H_DSTBP#3 9
H_DINV#3 9
H_DINV#3
H_DSTBN#3
H_DSTBP#3
AC20
AE25
AF24
DINV[3]#
DSTBP[3]#
DSTBN[3]#
DINV[1]#
DSTBN[1]#
DSTBP[1]#
L26
N24
M26
COMP0
COMP1
R26
U26
COMP[0]
MISC
MISC
GTLREF
C23
AD26
COMP2
COMP3
AA1
Y1
COMP[1]
COMP[2]
TEST2
TEST1
C24
D25
H_DPRSTP# 9,26,46
H_DPRSTP#
E5
COMP[3]
DPRSTP#
TEST5
TEST3
TEST4
AF1
AF26
H_DPSLP# 26
H_DPWR# 9
H_PWRGOOD 26
H_PWRGOOD
H_CPUSLP#
H_DPSLP#
H_DPWR#
B5
D24
D6
DPWR#
DPSLP#
PWRGOOD
BSEL[0]
TEST6
TEST7
C3
B22
A26
H_CPUSLP# 9
H_PSI#
AE6
D7
SLP#
BSEL[1]
B23
C21
H_PSI# 46
PSI#
BSEL[2]
Penryn
Penryn
VCC[067]
Penryn
Penryn
AB10
AB12
AB14
AB15
AB17
AB18
AC10
of CPU pin.Trace should be
at least 25 mils away from
any other toggling signal.
COMP[0,2] trace width is 18
mils. COMP[1,3] trace width
is 4 mils.
1
CPU_BSEL0
Deciphered Date
Deciphered Date
Deciphered Date
2008/11/04 2008/11/04
2008/11/04 2008/11/04
R27
1K_0402_1%
R27
1K_0402_1%
12
+VCCP
0
0
R29
R29
12
+V_CPU_GTLREF
2K_0402_1%
2K_0402_1%
Close to CPU pin AD26
within 500mils.
2008/11/04 2008/11/04
3
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Security Classification
Security Classification
Security Classification
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
H_D#4
H_D#3
H_D#6
H_D#2
H_D#1
H_D#5
H_D#0
5
H_D#[0..15]9
H_D#7
D D
H_D#9
H_D#8
H_D#10
H_D#11
H_D#13
H_D#12
H_D#14
H_D#15
H_DINV#0
H_DSTBP#0
H_DSTBN#0
H_DSTBN#09
H_DSTBP#09
H_DINV#09
H_D#[16..31]9
H_D#16
H_D#17
H_D#19
H_D#18
H_D#20
H_D#21
H_D#23
H_D#22
H_D#25
H_D#24
H_D#27
H_D#26
H_D#29
H_D#28
H_D#31
H_D#30
C C
H_DINV#1
H_DSTBP#1
H_DSTBN#1
H_DSTBN#19
H_DSTBP#19
H_DINV#19
TEST4
TEST1
TEST2
TEST3
TEST5
@
@
+V_CPU_GTLREF
T2@T2
T3@T3
T4T4
1 2
1 2
R22 1K_0402_5%@R22 1K_0402_5%@
R21 1K_0402_5%@R21 1K_0402_5%@
TEST6
TEST7
T5T5
CPU_BSEL2
CPU_BSEL1
CPU_BSEL0
T6T6
CPU_BSEL017
CPU_BSEL117
CPU_BSEL217
0 1
166
connection.
B B
CPU_BSEL CPU_BSEL2 CPU_BSEL1
* Route the TEST3 and TEST5 signals through
a ground referenced Zo = 55-ohm trace that
ends in a via that is near a GND via and is
accessible through an oscilloscope
200
0 0
266
5
A A
10
www.rosefix.com
0.1
0.1
0.1
of
of
of
8 51Thursday, February 12, 2009
8 51Thursday, February 12, 2009
8 51Thursday, February 12, 2009
1
C40
10U_0805_6.3V6M
C40
C24
10U_0805_6.3V6M
C24
C16
10U_0805_6.3V6M
C16
10U_0805_6.3V6M
1
2
C15
10U_0805_6.3V6M
C15
10U_0805_6.3V6M
1
2
C14
10U_0805_6.3V6M
C14
10U_0805_6.3V6M
1
2
2
C13
10U_0805_6.3V6M
C13
10U_0805_6.3V6M
1
2
C12
10U_0805_6.3V6M
C12
10U_0805_6.3V6M
1
2
C11
10U_0805_6.3V6M
C11
10U_0805_6.3V6M
1
2
3
C10
10U_0805_6.3V6M
C10
10U_0805_6.3V6M
1
2
C9
10U_0805_6.3V6M
C9
10U_0805_6.3V6M
1
2
+VCC_CORE
1
1
1
1
1
1
1
1
+VCC_CORE
10U_0805_6.3V6M
2
C23
10U_0805_6.3V6M
C23
10U_0805_6.3V6M
2
C22
10U_0805_6.3V6M
C22
10U_0805_6.3V6M
2
C21
10U_0805_6.3V6M
C21
10U_0805_6.3V6M
2
C20
10U_0805_6.3V6M
C20
10U_0805_6.3V6M
2
C19
10U_0805_6.3V6M
C19
10U_0805_6.3V6M
2
C18
10U_0805_6.3V6M
C18
10U_0805_6.3V6M
2
C17
10U_0805_6.3V6M
C17
10U_0805_6.3V6M
2
1
1
1
1
1
1
1
1
+VCC_CORE
C32
10U_0805_6.3V6M
C32
10U_0805_6.3V6M
2
C31
10U_0805_6.3V6M
C31
10U_0805_6.3V6M
2
C30
10U_0805_6.3V6M
C30
10U_0805_6.3V6M
2
C29
10U_0805_6.3V6M
C29
10U_0805_6.3V6M
2
C28
10U_0805_6.3V6M
C28
10U_0805_6.3V6M
2
C27
10U_0805_6.3V6M
C27
10U_0805_6.3V6M
2
C26
10U_0805_6.3V6M
C26
10U_0805_6.3V6M
2
C25
10U_0805_6.3V6M
C25
10U_0805_6.3V6M
2
1
1
1
1
1
1
1
1
+VCC_CORE
10U_0805_6.3V6M
2
C39
10U_0805_6.3V6M
C39
10U_0805_6.3V6M
2
C38
10U_0805_6.3V6M
C38
10U_0805_6.3V6M
2
C37
10U_0805_6.3V6M
C37
10U_0805_6.3V6M
2
C36
10U_0805_6.3V6M
C36
10U_0805_6.3V6M
2
C35
10U_0805_6.3V6M
C35
10U_0805_6.3V6M
2
C34
10U_0805_6.3V6M
C34
10U_0805_6.3V6M
2
C33
10U_0805_6.3V6M
C33
10U_0805_6.3V6M
2
330U_D2E_2.5VM_R7
330U_D2E_2.5VM_R7
+
+
1
C44
C44
+
+
1
ESR <= 1.5m ohm
Capacitor > 1980uF
+VCC_CORE
C43
C43
+
+
1
C42
C42
2
2
2
330U_D2E_2.5VM_R7
330U_D2E_2.5VM_R7
330U_D2E_2.5VM_R7
330U_D2E_2.5VM_R7
C50
0.1U_0402_10V6K
C50
0.1U_0402_10V6K
1
2
C49
0.1U_0402_10V6K
C49
0.1U_0402_10V6K
1
2
5
C48
0.1U_0402_10V6K
C48
0.1U_0402_10V6K
1
2
C47
0.1U_0402_10V6K
C47
0.1U_0402_10V6K
1
2
C46
0.1U_0402_10V6K
C46
0.1U_0402_10V6K
1
Inside CPU center cavity in 2 rows
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
2008/11/04 2008/11/04
2008/11/04 2008/11/04
2008/11/04 2008/11/04
Security Classification
Security Classification
Security Classification
1
Penryn(3/3)-AGTL+/ITP-XDP
Penryn(3/3)-AGTL+/ITP-XDP
Penryn(3/3)-AGTL+/ITP-XDP
LA-4731P Rhett discrete
LA-4731P Rhett discrete
LA-4731P Rhett discrete
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Custom
Custom
Custom
2
Deciphered Date
Deciphered Date
Deciphered Date
3
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C45
0.1U_0402_10V6K
C45
0.1U_0402_10V6K
1
AF13
AF11
VSS[157]
VSS[156]
VSS[076]
M25
A25
AF21
AF19
AF16
VSS[162]
VSS[161]
VSS[160]
VSS[159]
VSS[158]
VSS[077]N1VSS[078]N4VSS[079]
VSS[080]
VSS[081]
P3
N23
N26
2
AF25
VSS[163]
Penryn
Penryn
4
.
.
5
A A
AE23
AE19
AE16
VSS[152]
VSS[151]
VSS[149]
VSS[150]
VSS[068]
VSS[069]L3VSS[070]L6VSS[071]
L21
AF6
A2
AE26
VSS[154]
VSS[153]
VSS[072]
VSS[073]M2VSS[074]M5VSS[075]
L24
+VCCP
AF8
VSS[155]
M22
Place these capacitors on
L8 (North side,Secondary
Layer)
4
5
Place these capacitors on
P6
P21
P24
VSS[082]
VSS[083]
VSS[084]
VSS[002]A8VSS[003]
VSS[001]
JCPU1D
JCPU1D
A4
A11
D D
L8 (North side,Secondary
Layer)
R22
R25
VSS[085]R2VSS[086]R5VSS[087]
VSS[004]
VSS[005]
VSS[006]
A14
A16
A19
A23
T23
VSS[088]
VSS[089]T1VSS[090]T4VSS[091]
VSS[007]
VSS[008]
VSS[009]B6VSS[010]B8VSS[011]
AF2
T26
VSS[092]
VSS[093]U3VSS[094]U6VSS[095]
VSS[012]
B11
B13
Place these capacitors on
U21
VSS[013]
VSS[014]
B16
B19
L8 (North side,Secondary
Layer)
U24
VSS[096]
VSS[097]V2VSS[098]V5VSS[099]
VSS[015]
VSS[016]
VSS[017]C5VSS[018]C8VSS[019]
B21
B24
V22
V25
VSS[100]
VSS[101]W1VSS[102]W4VSS[103]
VSS[020]
C11
C14
C16
W23
W26
VSS[104]
VSS[021]
VSS[022]
VSS[023]C2VSS[024]
C19
C22
Place these capacitors on
Y6
VSS[105]Y3VSS[107]
VSS[106]
VSS[025]
C25
Mid Frequence Decoupling
L8 (North side,Secondary
Layer)
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[026]D1VSS[027]D4VSS[028]D8VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]E3VSS[036]E6VSS[037]E8VSS[038]
D11
D13
D16
C C
E11
D19
D23
D26
Near CPU CORE regulator
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]F5VSS[045]F8VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]F2VSS[051]
F11
F13
F16
F19
E14
E16
E19
E21
E24
F22
AC19
AC21
AC24
VSS[133]
VSS[134]
VSS[052]
VSS[053]G4VSS[054]G1VSS[055]
F25
AD2
AD5
VSS[135]
VSS[136]
VSS[137]
VSS[056]
G23
G26
AD8
AD11
AD13
AD16
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[057]H3VSS[058]H6VSS[059]
VSS[060]
H21
H24
AD19
AD22
AD25
AE1
VSS[142]
VSS[143]
VSS[144]
VSS[061]J2VSS[062]J5VSS[063]
J22
J25
B B
AE11
AE4
AE8
VSS[148]
VSS[145]
VSS[146]
VSS[147]
VSS[064]
VSS[065]K1VSS[066]K4VSS[067]
K23
AE14
K26
www.rosefix.com
0.1
0.1
0.1
of
of
R44
499_0402_1%
R44
R43
1K_0402_1%
R43
T35T35
C34
+VCCP
1K_0402_1%
12
CL_CLK0 27
CL_CLK0
CL_DATA0
AH37
AH36
+1.8V
1
1 2
1 2
1 2
M_CLK_DDR0 15
M_CLK_DDR1 15
M_CLK_DDR2 16
M_CLK_DDR3 16
M_CLK_DDR3
M_CLK_DDR2
M_CLK_DDR0
M_CLK_DDR1
AP24
AT21
AV24
AU20
M_CLK_DDR#0 15
M_CLK_DDR#1 15
M_CLK_DDR#2 16
M_CLK_DDR#3 16
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
AR24
AR21
AU24
AV20
DDR_CS0_DIMMA# 15
DDR_CKE0_DIMMA 15
DDR_CKE1_DIMMA 15
DDR_CKE2_DIMMB 16
DDR_CKE3_DIMMB 16
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE3_DIMMB
DDR_CS1_DIMMA#
DDR_CKE2_DIMMB
DDR_CS0_DIMMA#
BC28
AY28
AY36
BB36
BA17
AY16
DDR_CS1_DIMMA# 15
DDR_CS2_DIMMB# 16
DDR_CS3_DIMMB# 16
M_ODT0 15
M_ODT1 15
M_ODT2 16
M_ODT1
M_ODT0
M_ODT2
DDR_CS3_DIMMB#
DDR_CS2_DIMMB#
AV16
AR13
BD17
AY17
BF15
1 2
M_ODT3 16
Follow Design Guide
R35 80.6_0402_1%R35 80.6_0402_1%
R34 80.6_0402_1%
R34 80.6_0402_1%
SMRCOMP_VOH
SMRCOMP#
M_ODT3
SMRCOMP
AY13
BG22
BH21
BF28
T29T29
For Cantiga: 80.6ohm
R37 499_0402_1%R37 499_0402_1%
R36 0_0402_5%R36 0_0402_5%
SM_PWROK
SM_REXT
V_DDR_MCH_REF
SMRCOMP_VOL
TP_SM_DRAMRST#
BC36
B38
A38
E41
BF17
F41
BH28
AV42
AR36
CLK_MCH_3GPLL 17
CLK_MCH_3GPLL# 17
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
E43
F43
DMI_TXN0 27
DMI_TXN1 27
DMI_TXN2 27
DMI_TXN0
DMI_TXN1
DMI_TXN2
AE41
AE37
AE47
DMI_TXP0 27
DMI_TXN3 27
DMI_TXN3
DMI_TXP0
AH39
AE40
DMI_TXP1 27
DMI_TXP2 27
DMI_TXP3 27
DMI_TXP1
DMI_TXP2
DMI_TXP3
AE38
AE48
AH40
DMI_RXN0 27
DMI_RXN1 27
DMI_RXN2 27
DMI_RXN0
DMI_RXN1
DMI_RXN2
AE35
AE43
AE46
DMI_RXP0 27
DMI_RXN3 27
DMI_RXN3
DMI_RXP0
AH42
AD35
DMI_RXP1 27
DMI_RXP2 27
DMI_RXP3 27
DMI_RXP1
DMI_RXP2
DMI_RXP3
AE44
AF46
AH43
T31T31
T33T33
T34T34
T32T32
T30T30
B33
B32
G33
F33
E33
499_0402_1%
12
1
2
C56
C56
CL_DATA0 27
M_PWROK 27,37
CL_RST# 27
+CL_VREF
CL_RST#
M_PWROK
AN36
AJ35
AH34
CLKREQ#_7 17
0.1U_0402_16V4Z
0.1U_0402_16V4Z
T38T38
T37T37
T36T36
MCH_ICH_SYNC#
CLKREQ#_7
0621 add CLK and DAT for DVI
G36
E36
K36
H36
N28
M28
TSATN# 37
MCH_ICH_SYNC# 27
+VCCP
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
R49
56_0402_5% R49
56_0402_5%
1 2
TSATN#
B12
B28
B30
B29
C29
A28
of
9 51Monday, February 16, 2009
9 51Monday, February 16, 2009
9 51Monday, February 16, 2009
1
LA-4731P Rhett discrete
Cantiga(1/6)-AGTL/DMI/DDR
LA-4731P Rhett discrete
Cantiga(1/6)-AGTL/DMI/DDR
LA-4731P Rhett discrete
Cantiga(1/6)-AGTL/DMI/DDR
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Custom
Custom
Custom
SA_CK_0
SA_CK_1
SB_CK_0
SB_CK_1
SA_CK#_0
SA_CK#_1
SB_CK#_0
SB_CK#_1
2
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
T33
N36
R33
T9T9
T10T10
T8T8
+1.8V
AH9
AH10
T11T11
RESERVED
K12
AH12
AH13
T13T13
T14T14
T12T12
R31
R31
12
1
C52
C52
1
C51
C51
RESERVED
AL34
T15T15
T16T16
1K_0402_1%
1K_0402_1%
0.01U_0402_25V7K
0.01U_0402_25V7K
2
2
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
RESERVED
U2B
U2B
M36
T7T7
3
H_A#[3..35] 6
SA_CS#_0
SA_CS#_1
SA_CKE_0
SA_CKE_1
SB_CKE_0
SB_CKE_1
RSVD
RSVD
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
B2
M1
T24
B31
AK34
AN35
AM35
T19T19
T18T18
T17T17
T22T22
T21T21
T23T23
T20T20
R32
3.01K_0402_1%
R32
3.01K_0402_1%
12
SMRCOMP_VOH
80% of 1.8V VCC_SM
20% of 1.8V VCC_SM
SB_CS#_0
SB_CS#_1
SA_ODT_0
SA_ODT_1
RESERVED
AY21
T24T24
R33
1K_0402_1%
R33
1K_0402_1%
12
1
1
SMRCOMP_VOL
SB_ODT_0
SB_ODT_1
RESERVED
RESERVED
BF23
BG23
T25T25
T26T26
2
C54
C54
2
C53
C53
SM_RCOMP
SM_RCOMP#
RESERVED
RESERVED
BF18
BH18
T28T28
T27T27
0.01U_0402_25V7K
0.01U_0402_25V7K
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
SM_VREF
SM_REXT
SM_PWROK
SM_RCOMP_VOL
SM_RCOMP_VOH
H_ADS# 6
SM_DRAMRST#
H_ADSTB#0 6
PEG_CLK
PEG_CLK#
DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
DDR CLK/ CONTROL/COMPENSATION
DDR CLK/ CONTROL/COMPENSATION
+3VS
1 2
R38 10K_0402_5%
R38 10K_0402_5%
PM_EXTTS#0
H_ADSTB#1 6
H_BNR# 6
H_BPRI# 6
H_BR0# 6
1 2
1 2
R40 10K_0402_5%R40 10K_0402_5%
R39 10K_0402_5%R39 10K_0402_5%
CLKREQ#_7
PM_EXTTS#1
H_DEFER# 6
H_DBSY# 6
CLK_MCH_BCLK 17
CLK_MCH_BCLK# 17
CLK
CLK
H_DPWR# 7
H_DRDY# 6
DMI_RXN_0
H_HIT# 6
H_HITM# 6
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
H_LOCK# 6
H_TRDY# 6
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
CFG_2
CFG_0
CFG_1
T25
P25
R25
MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2
MCH_CLKSEL017
MCH_CLKSEL117
MCH_CLKSEL217
H_DINV#0 7
H_DINV#1 7
DMI_TXN_0
CFG_3
CFG_4
P20
P24
T39T39
T40T40
H_DINV#2 7
H_DINV#3 7
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
CFG_5
CFG_6
CFG_7
C25
N24
M24
CFG7
CFG6
CFG5
CFG511
CFG611
CFG711
H_DSTBN#0 7
H_DSTBN#1 7
DMI_TXP_0
CFG
CFG
CFG_8
CFG_9
E21
C23
CFG9
CFG8
CFG911
CFG811
H_DSTBN#2 7
H_DSTBN#3 7
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
CFG_10
CFG_11
CFG_12
P21
C24
N21
CFG11
CFG10
CFG12
CFG1111
CFG1011
CFG1211
H_DSTBP#0 7
H_DSTBP#1 7
DMI
DMI
CFG_13
CFG_14
T21
R20
CFG14
CFG13
CFG1311
CFG1411
H_DSTBP#2 7
H_DSTBP#3 7
CFG_15
L21
M20
CFG16
CFG15
CFG1511
CFG_16
CFG17
CFG1611
H_REQ#0 6
CFG_17
P29
H21
CFG18
CFG1711
H_REQ#1 6
CFG_18
CFG_19
R28
CFG19
CFG20
CFG1811
CFG1911
H_REQ#3 6
H_REQ#2 6
GFX_VID_0
GFX_VID_1
GFX_VID_2
CFG_20
T28
CFG2011
H_REQ#4 6
H_RS#0 6
GFX_VID_3
GFX_VID_4
PM_SYNC#
PM_EXT_TS#_0
PM_DPRSTP#
B7
R29
N33
H_DPRSTP#
PM_EXTTS#1
PM_EXTTS#0
PM_BMBUSY#
H_DPRSTP#7,26,46
PM_EXTTS#015
PM_BMBUSY#27
H_RS#2 6
H_RS#1 6
GFX_VR_EN
GRAPHICS VID
GRAPHICS VID
PM
PM
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR
T20
P32
R32
AT40
AT11
THERMTRIP#
PM_PWROK
DPRSLPVR
100_0402_5%
100_0402_5%
0_0402_5%
0_0402_5%
PM_EXTTS#116
PM_PWROK27,37
1 2
1 2
R41
R41
R42
R42
PLT_RST#
DPRSLPVR27,46
PLT_RST#20,25,30,31
H_THERMTRIP#6,26
CL_CLK
CL_RST#
CL_DATA
CL_VREF
CL_PWROK
DDPC_CTRLCLK
DDPC_CTRLDATA
MEHDA
MEHDA
NC
NC
NC
NC
NC
NC
BF48
BE47
BD48NCBC48NCBH47
BG48
@
@
1
BH46
BG47
C55
C55
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.8V
CLKREQ#
ICH_SYNC#
SDVO_CTRLCLK
SDVO_CTRLDATA
NC
NC
NC
NC
NC
NC
BH6NCBH5
BF46
BH44NCBH43
BG45
R45
10K_0402_1%
R45
10K_0402_1%
12
TSATN#
HDA_BCLK
MISC
MISC
NC
NC
NC
NC
NC
BF3
BE2
BH3
BH2
BG4
BG2
R48
10K_0402_1%
R48
10K_0402_1%
12
C57
C57
1
V_DDR_MCH_REF
HDA_SDI
HDA_SDO
HDA_RST#
NC
NC
NC
BF1
BD1NCBC1
BG1
2
HDA_SYNC
NC
NC
NC
CANTIGA ES_FCBGA1329
CANTIGA ES_FCBGA1329
F1
A47
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
Deciphered Date
Deciphered Date
Deciphered Date
2008/11/04 2008/11/04
2008/11/04 2008/11/04
2008/11/04 2008/11/04
3
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Security Classification
Security Classification
Security Classification
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
H_A#7
H_A#6
H13
H_A#_5
H_A#_6
H_D#_1
H_D#_2
F8
H_D#3
H_D#2
H_A#8
C18
M16
H_A#_7
H_D#_3
E6
G2
H_D#4
H_A#9
H_A#10
P16
J13
H_A#_8
H_A#_9
H_D#_4
H_D#_5
H6
H2
H_D#6
H_D#5
H_A#12
H_A#11
R16
N17
H_A#_10
H_A#_11
H_A#_12
H_D#_8D4H_D#_9
H_D#_6
H_D#_7
F6
H_D#8
H_D#7
H_A#14
H_A#13
M13
E17
H_A#_13
H3
M9
H_D#9
H_D#10
H_A#16
H_A#15
P17
F17
H_A#_14
H_A#_15
H_A#_16
H_D#_10
H_D#_11
H_D#_12J1H_D#_13J2H_D#_14
M11
H_D#12
H_D#11
D D
H_A#17
G20
H_D#13
H_A#3
H_A#5
H_A#4
4
A14
C15
F16
H_A#_3
H_A#_4
H_D#_0
U2A
U2A
F2
G8
H_D#1
H_D#0
5
H_D#[0..63]7
H_A#18
H_A#21
H_A#19
H_A#20
B19
J16
E20
H16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_D#_15J6H_D#_16P2H_D#_17L2H_D#_18R2H_D#_19
N12
H_D#15
H_D#14
H_D#17
H_D#16
H_A#22
H_A#23
J20
L17
H_A#_22
H_A#_23
N9
H_D#19
H_D#18
H_A#24
H_A#25
A17
B17
H_A#_24
H_D#_20
L6
H_D#20
H_D#21
H_A#32
H_A#31
H_A#27
H_A#30
H_A#26
L16
H_A#_25
H_D#_21M5H_D#_22J3H_D#_23N2H_D#_24R1H_D#_25N5H_D#_26N6H_D#_27
H_D#22
H_A#28
C21
J17
H_A#_26
H_A#_27
H_D#24
H_D#23
H_A#29
H20
B18
H_A#_28
H_A#_29
H_A#_30
H_D#25
H_D#26
K17
B20
H_A#_31
P13
H_D#27
H_D#28
H_A#33
F21
H_A#_32
H_D#_28N8H_D#_29
L7
H_D#29
H_A#34
H_A#35
K21
L20
H_A#_33
H_A#_34
H_D#_30
N10
H_D#30
H_D#31
H_ADSTB#1
H_ADS#
H_ADSTB#0
H12
B16
G17
H_ADS#
H_A#_35
H_ADSTB#_0
H_ADSTB#_1
H_D#_31M3H_D#_32Y3H_D#_33
H_D#_34Y6H_D#_35
Y10
AD14
H_D#32
H_D#34
H_D#35
H_D#33
H_BPRI#
H_BNR#
A9
F11
H_BNR#
H_BPRI#
H_D#_36
H_D#_37
Y12
Y14
H_D#36
H_D#37
H_DEFER#
H_BR0#
H_DBSY#
G12
B10
E9
H_BREQ#
H_DEFER#
H_D#_38Y7H_D#_39
W2
AA8
H_D#40
H_D#39
H_D#38
CLK_MCH_BCLK#
CLK_MCH_BCLK
H_HIT#
H_DRDY#
H_DPWR#
AH6
AH7
J11
F9
H9
H_DBSY#
H_DRDY#
H_DPWR#
HPLL_CLK
HPLL_CLK#
H_D#_40
H_D#_41Y9H_D#_42
H_D#_43
H_D#_44
AA9
AA13
AA11
AD11
H_D#42
H_D#44
H_D#41
H_D#45
H_D#43
C C
H_LOCK#
H_HITM#
E12
H11
H_HIT#
H_HITM#
HOST
HOST
H_D#_45
H_D#_46
AD10
AD13
H_D#46
H_D#47
H_TRDY#
C9
H_TRDY#
H_LOCK#
H_D#_47
H_D#_48
H_D#_49
AE9
AE12
H_D#48
H_D#49
H_D#_50
AA2
AD8
H_D#51
H_D#50
H_DINV#0
H_DINV#1
H_DINV#_0J8H_DINV#_1L3H_DINV#_2
H_D#_51
H_D#_52
H_D#_53
H_D#_54
AA3
AD3
AD7
H_D#54
H_D#53
H_D#52
H_DINV#3
H_DINV#2
Y13
Y1
H_DINV#_3
H_D#_55
H_D#_56
AF3
AC1
AE14
H_D#55
H_D#56
H_D#57
H_DSTBN#1
H_DSTBN#0
H_DSTBN#2
L10
M7
AA5
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_D#_60
H_D#_57
H_D#_58
H_D#_59
AE3
AC3
AE11
H_D#59
H_D#60
H_D#58
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
AE6
L9
M8
H_DSTBP#_0
H_DSTBN#_3
H_D#_61
H_D#_62
H_D#_63
AE8
AD6
AG2
H_D#61
H_D#63
H_D#62
H_DSTBP#2
H_DSTBP#3
AA6
AE5
H_DSTBP#_1
H_DSTBP#_2
+H_SWNG
H_REQ#0
H_REQ#3
H_REQ#1
H_REQ#4
H_REQ#2
H_RS#1
H_RS#0
H_RS#2
F13
B13
B15
K13
B14
F12
C8
H_RS#_0B6H_RS#_1
H_RS#_2
H_REQ#_2
H_REQ#_3
H_REQ#_0
H_REQ#_1
H_REQ#_4
H_DSTBP#_3
H_CPURST#
H_SWINGC5H_CPUSLP#
H_RCOMP
E3
E11
C12
H_RCOMP
H_RESET#
H_CPUSLP#
+H_VREF
H_RESET#6
H_CPUSLP#7
B B
Layout Note: V_DDR_MCH_REF
trace width and spacing is 20/20.
H_AVREF
H_DVREF
CANTIGA ES_FCBGA1329
CANTIGA ES_FCBGA1329
A11
B11
Layout note:
Route H_SCOMP and H_SCOMP# with trace
width, spacing and impedance (55 ohm) same as
FSB data traces
+VCCP
Layout Note:
H_RCOMP / H_VREF / H_SWNG
trace width and spacing is 10/20
+VCCP
V_DDR_MCH_REF15,16
R47
R47
12
R46
R46
12
+H_SWNG
221_0603_1%
221_0603_1%
H_RCOMP
+H_VREF
1K_0402_1%
1K_0402_1%
C59
C59
1
R55
R55
12
R54
R54
12
C58
C58
1
R52
12
R52
A A
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Near B3 pinwithin 100 mils from NB
100_0402_1%
100_0402_1%
24.9_0402_1%
24.9_0402_1%
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2K_0402_1%
2K_0402_1%
4
5
www.rosefix.com
0.1
0.1
0.1
of
of
of
10 51Monday, February 16, 2009
10 51Monday, February 16, 2009
10 51Monday, February 16, 2009
DDR_B_CAS# 16
DDR_B_RAS# 16
1
DDR_B_BS0 16
DDR_B_BS0
BC16
DDR_B_BS1 16
DDR_B_BS2 16
DDR_B_BS2
DDR_B_BS1
BB17
BB33
DDR_B_WE# 16
DDR_B_RAS#
DDR_B_WE#
DDR_B_CAS#
BG16
AU17
BF14
DDR_B_DM[0..7] 16
DDR_B_DM0
DDR_B_DM2
DDR_B_DM1
AM47
AY47
BD40
DDR_B_DM3
DDR_B_DM6
DDR_B_DM4
DDR_B_DM5
BF35
BG11
BA3
AP1
DDR_B_DQS[0..7] 16
DDR_B_DQS0
DDR_B_DM7
DDR_B_DQS1
AK2
AL47
AV48
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
BG41
BG37
BH9
BB2
DDR_B_DQS#[0..7] 16
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
AU1
AN6
AL46
AV47
DDR_B_DQS#2
DDR_B_DQS#6
DDR_B_DQS#5
DDR_B_DQS#4
DDR_B_DQS#3
BH41
BH37
BG9
BC2
AT2
DDR_B_MA[0..14] 16
DDR_B_DQS#7
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
AN5
AV17
BA25
BC25
DDR_B_MA4
DDR_B_MA5
DDR_B_MA3
DDR_B_MA6
AU25
AW25
BB28
AU28
DDR_B_MA10
DDR_B_MA7
DDR_B_MA9
DDR_B_MA8
BB16
AW28
AT33
BD33
DDR_B_MA14
DDR_B_MA11
DDR_B_MA13
DDR_B_MA12
AW33
AY33
BH15
AU33
1
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
LA-4731P Rhett discrete
Cantiga(2/6)-DDR2 A/B CH
LA-4731P Rhett discrete
Cantiga(2/6)-DDR2 A/B CH
LA-4731P Rhett discrete
Cantiga(2/6)-DDR2 A/B CH
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Custom
Custom
Custom
SB_BS_1
SB_BS_2
SB_DQ_1
SB_DQ_2
SB_DQ_3
AP47
AP46
AH46
DDR_B_D3
DDR_B_D2
DDR_B_D1
DDR_A_BS1 15
DDR_A_BS2 15
SB_CAS#
SB_RAS#
SB_DQ_4
SB_DQ_5
SB_DQ_6
AJ46
AJ48
AM48
DDR_B_D7
DDR_B_D4
DDR_B_D6
DDR_B_D5
DDR_A_CAS# 15
DDR_A_RAS# 15
DDR_A_WE# 15
SB_WE#
SB_DQ_7
SB_DQ_8
AP48
AU47
AU46
DDR_B_D9
DDR_B_D8
SB_DM_0
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_9
AY48
AT47
BA48
DDR_B_D12
DDR_B_D11
DDR_B_D10
DDR_A_DM[0..7] 15
SB_DM_1
SB_DM_2
SB_DM_3
SB_DQ_13
SB_DQ_14
SB_DQ_15
BA47
AR47
BC47
BC46
DDR_B_D13
DDR_B_D15
DDR_B_D14
DDR_B_D16
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
BF43
BC44
BG43
DDR_B_D18
DDR_B_D19
DDR_B_D17
DDR_A_DQS[0..7] 15
SB_DQS_0
SB_DQS_1
SB_DQ_20
SB_DQ_21
SB_DQ_22
BF40
BF41
BE45
BC41
DDR_B_D21
DDR_B_D23
DDR_B_D20
DDR_B_D22
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQ_23
SB_DQ_24
SB_DQ_25
BF38
BH35
BG38
DDR_B_D24
DDR_B_D26
DDR_B_D25
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQ_26
SB_DQ_27
SB_DQ_28
BH40
BG35
BG39
DDR_B_D29
DDR_B_D27
DDR_B_D28
DDR_A_DQS#[0..7] 15
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
BH34
BH14
BG34
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D30
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQ_33
SB_DQ_34
SB_DQ_35
BG8
BH11
BH12
BG12
DDR_B_D36
DDR_B_D34
DDR_B_D35
DDR_A_MA[0..14] 15
SB_MA_0
SB_MA_1
SB_DQS#_7
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
BF8
BG7
BF11
DDR_B_D39
DDR_B_D38
DDR_B_D37
SB_MA_2
SB_MA_3
SB_MA_4
SB_DQ_40
SB_DQ_41
SB_DQ_42
AY3
AY1
BC5
BC6
DDR_B_D42
DDR_B_D41
DDR_B_D43
DDR_B_D40
SB_MA_5
SB_MA_6
SB_MA_7
SB_DQ_43
SB_DQ_44
SB_DQ_45
BF6
BF5
BA1
DDR_B_D46
DDR_B_D44
DDR_B_D45
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
AV2
BD3
AU3
DDR_B_D47
DDR_B_D49
DDR_B_D48
SB_MA_12
SB_MA_13
SB_MA_14
SB_DQ_50
SB_DQ_51
SB_DQ_52
AY2
AV1
AR3
AN2
DDR_B_D51
DDR_B_D50
DDR_B_D53
DDR_B_D52
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
SB_DQ_53
SB_DQ_54
SB_DQ_55
AL1
AP3
AR1
DDR_B_D54
DDR_B_D55
DDR_B_D56
SB_DQ_56
SB_DQ_57
SB_DQ_58
AJ1
AL2
AH1
DDR_B_D59
DDR_B_D57
DDR_B_D58
SB_DQ_59
SB_DQ_60
SB_DQ_61
AH3
AM2
AM3
DDR_B_D62
DDR_B_D61
DDR_B_D60
SB_DQ_62
AJ3
DDR_B_D63
SB_DQ_63
CANTIGA ES_FCBGA1329
CANTIGA ES_FCBGA1329
2
Deciphered Date
Deciphered Date
Deciphered Date
2008/11/04 2008/11/04
2008/11/04 2008/11/04
2008/11/04 2008/11/04
3
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Security Classification
Security Classification
Security Classification
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
SB_BS_0
2
SB_DQ_0
U2E
U2E
AK47
DDR_B_D0
3
DDR_B_D[0..63]16
DDR_A_BS0 15
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
BD21
BG18
AT25
BD20
BB20
SA_BS_0
SA_BS_1
SA_BS_2
SA_DQ_0
SA_DQ_1
SA_DQ_2
AJ38
AJ41
AN38
DDR_A_D2
DDR_A_D1
DDR_A_D0
SA_CAS#
SA_RAS#
SA_DQ_3
SA_DQ_4
SA_DQ_5
AJ36
AJ40
AM38
DDR_A_D5
DDR_A_D4
DDR_A_D3
DDR_A_D6
AY20
AM44
4
U2D
U2D
5
DDR_A_D[0..63]15
D D
SA_WE#
SA_DQ_6
SA_DQ_7
SA_DQ_8
AN43
AM42
DDR_A_D8
DDR_A_D7
DDR_A_DM0
AM37
SA_DM_0
SA_DQ_10
SA_DQ_11
SA_DQ_9
AT38
AU40
AN44
DDR_A_D11
DDR_A_D10
DDR_A_D9
DDR_A_DM2
DDR_A_DM1
AT41
AY41
SA_DM_1
SA_DQ_12
AN41
AN39
DDR_A_D13
DDR_A_D12
DDR_A_DM5
DDR_A_DM4
DDR_A_DM3
AU39
BB12
AY6
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
AV39
AU44
AU42
DDR_A_D15
DDR_A_D14
DDR_A_D16
DDR_A_DQS0
DDR_A_DM7
DDR_A_DM6
AT7
AJ44
AJ5
SA_DM_6
SA_DM_7
SA_DQS_0
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
AY44
BA40
AV41
BD43
DDR_A_D19
DDR_A_D18
DDR_A_D17
DDR_A_D20
DDR_A_DQS1
AT44
AY43
DDR_A_D21
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
BA43
BC37
AW12
BC8
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
AY37
BB41
BC40
BD38
DDR_A_D25
DDR_A_D24
DDR_A_D23
DDR_A_D22
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS6
DDR_A_DQS7
AU8
AM7
AJ43
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
AT36
AY38
AV37
DDR_A_D27
DDR_A_D26
DDR_A_D29
DDR_A_D28
C C
DDR_A_DQS#2
AT43
BA44
SA_DQS#_1
SA_DQ_29
BB38
AV36
DDR_A_D30
DDR_A_DQS#5
DDR_A_DQS#4
DDR_A_DQS#6
DDR_A_DQS#3
BD37
AY12
BD8
AU9
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
BD13
AU11
BC11
AW36
DDR_A_D34
DDR_A_D33
DDR_A_D32
DDR_A_D31
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_DQS#7
AM8
BA21
BC24
BG24
SA_MA_0
SA_MA_1
SA_MA_2
SA_DQS#_7
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
BA12
AV13
AU13
BD12
BC12
DDR_A_D39
DDR_A_D38
DDR_A_D35
DDR_A_D37
DDR_A_D36
DDR_A_MA4
DDR_A_MA3
DDR_A_MA5
DDR_A_MA6
BH24
BG25
BA24
BD24
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
BB9
BA9
AV9
AU10
DDR_A_D43
DDR_A_D42
DDR_A_D41
DDR_A_D40
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
BC21
BG27
BF25
AW24
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
AY8
BA6
BD9
BA11
DDR_A_D47
DDR_A_D46
DDR_A_D45
DDR_A_D44
DDR_A_MA12
DDR_A_MA13
DDR_A_MA11
DDR_A_MA14
BG26
BH26
BH17
AY25
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
AT9
AV5
AV7
AN8
DDR_A_D51
DDR_A_D50
DDR_A_D49
DDR_A_D48
DDR_A_D52
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
SA_DQ_52
SA_DQ_53
SA_DQ_54
AT5
AU5
AU6
DDR_A_D55
DDR_A_D54
DDR_A_D53
SA_DQ_55
SA_DQ_56
SA_DQ_57
AM5
AN10
AM11
DDR_A_D57
DDR_A_D56
SA_DQ_58
SA_DQ_59
SA_DQ_60
AJ9
AJ8
AN12
AM13
DDR_A_D61
DDR_A_D60
DDR_A_D59
DDR_A_D58
B B
SA_DQ_61
SA_DQ_62
SA_DQ_63
CANTIGA ES_FCBGA1329
CANTIGA ES_FCBGA1329
AJ11
AJ12
DDR_A_D63
DDR_A_D62
4
5
A A
1
000 = FSB 1066MHz
011 = FSB 667MHz
010 = FSB 800MHz
CFG[2:0] FSB Freq
select
Strap Pin Table
2
*
Others = Reserved
Reserved
0 = The iTPM Host Interface is enable
0 = DMI x 2
1 = DMI x 4
CFG[4:3]
CFG5 (DMI select)
www.rosefix.com
*
*
1 = The iTPM Host Interface is disable
0 =(TLS)chiper suite with no confidentiality
1 =(TLS)chiper suite with confidentiality
(Intel Management
Engine Crypto strap)
CFG6
CFG7
*
*
Reserved
CFG8
0 = Enable
1 = Disable
order
(PCIE
Lookback
CFG10
Reserved
enable)
CFG11
0 = Reverse Lane,15->0, 14->1
1 = Normal Operation,Lane Number in
Lane Reversal)
CFG9 (PCIE Graphics
*
(Default)11 = Normal Operation
*
10 = All Z Mode Enabled
00 = Reserved
01 = XOR Mode Enabled
Reserved
1 = Enabled
0 = Disabled
CFG[15:14]
CFG[13:12] (XOR/ALLZ)
PEG_M_TXN1 20
PEG_M_TXN0 20
CFG16 (FSB Dynamic ODT)
PEG_M_TXN3 20
PEG_M_TXN2 20
PEG_M_TXN7 20
PEG_M_TXN6 20
PEG_M_TXN5 20
PEG_M_TXN4 20
PEG_M_TXN10 20
PEG_M_TXN9 20
PEG_M_TXN8 20
Reserved
0 = Normal Operation
CFG[18:17]
CFG19 (DMI Lane Reversal)
PEG_M_TXN14 20
PEG_M_TXN13 20
PEG_M_TXN12 20
PEG_M_TXN11 20
PEG_M_TXN15 20
*
*
(Lane number in Order)
1 = Reverse Lane
1 = PCIE/SDVO are operating simu.
0 = Only PCIE or SDVO is operational.
+3VS
(PCIE/SDVO
concurrent)
CFG20
PEG_M_TXP2 20
PEG_M_TXP3 20
PEG_M_TXP1 20
PEG_M_TXP0 20
PEG_M_TXP6 20
PEG_M_TXP5 20
PEG_M_TXP4 20
PEG_M_TXP10 20
PEG_M_TXP9 20
PEG_M_TXP8 20
PEG_M_TXP7 20
PEG_M_TXP12 20
PEG_M_TXP11 20
PEG_M_TXP13 20
PEG_M_TXP14 20
+3VS
12
@
@
R71
4.02K_0402_1%
R71
4.02K_0402_1%
PEG_M_TXP15 20
4.02K_0402_1%
4.02K_0402_1%
1 2
1 2
R73
R72
@ R73
@
@R72
@
CFG169
CFG199
12
@
@
CFG5
CFG59
4.02K_0402_1%
4.02K_0402_1%
4.02K_0402_1%
4.02K_0402_1%
1 2
R75
@R75
@
CFG209
R74
2.21K_0402_1%
R74
2.21K_0402_1%
2.21K_0402_1%
2.21K_0402_1%
1 2
1 2
R76
R77
@R76
@
@R77
@
CFG119
CFG129
2.21K_0402_1%
2.21K_0402_1%
2.21K_0402_1%
2.21K_0402_1%
1 2
R78
R80
@R78
@
@R80
@
CFG139
2.21K_0402_1%
2.21K_0402_1%
1 2
R79
@R79
@
CFG69
2.21K_0402_1%
2.21K_0402_1%
2.21K_0402_1%
2.21K_0402_1%
1 2
1 2
R82
@R82
@
CFG149
CFG159
2.21K_0402_1%
2.21K_0402_1%
1 2
R81
@ R81
@
CFG79
1 2
R85
@R85
@
CFG179
2.21K_0402_1%
2.21K_0402_1%
1 2
1 2
R83
R84
@R83
@
@R84
@
CFG89
CFG99
2.21K_0402_1%
2.21K_0402_1%
2.21K_0402_1%
2.21K_0402_1%
1 2
R87
@R87
@
CFG189
2.21K_0402_1%
2.21K_0402_1%
2.21K_0402_1%
2.21K_0402_1%
1 2
R86
@R86
@
CFG109
0.1
0.1
0.1
of
of
of
11 51Monday, February 16, 2009
11 51Monday, February 16, 2009
11 51Monday, February 16, 2009
1
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
LA-4731P Rhett discrete
Cantiga(3/6)-VGA/LVDS/TV
LA-4731P Rhett discrete
Cantiga(3/6)-VGA/LVDS/TV
LA-4731P Rhett discrete
Cantiga(3/6)-VGA/LVDS/TV
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Custom
Custom
Custom
2
PEGCOMP trace width
+VCC_PEG
R57
R57
3
U2C
U2C
4
L32
and spacing is 20/25 mils.
PEG_RXN3 20
PEG_RXN2 20
PEG_RXN1 20
PEG_RXN0 20
PEG_RXN5 20
PEG_RXN7 20
PEG_RXN6 20
PEG_RXN4 20
PEG_RXN8 20
49.9_0402_1%
49.9_0402_1%
1 2
PEG_RXN4
PEG_RXN7
PEG_RXN6
PEG_RXN5
PEG_RXN0
PEG_RXN3
PEG_RXN2
PEG_RXN8
T37
T36
PEG_COMPI
PEG_COMPO
L_CTRL_CLK
L_CTRL_DATA
L_BKLT_EN
L_BKLT_CTRL
G32
M32
M33
PEG_RXN1
H44
J46
L44
PEG_RX#_0
PEG_RX#_1
L_DDC_CLK
L_DDC_DATA
J33
K33
L40
N41
P48
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
L_VDD_EN
LVDS_IBG
C44
M29
N44
T43
U43
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
LVDS
LVDS
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
B43
E37
E38
PEG_RXN9
Y43
C41
PEG_RXN13 20
PEG_RXN12 20
PEG_RXN9 20
PEG_RXN11 20
PEG_RXN10 20
PEG_RXN12
PEG_RXN10
PEG_RXN13
PEG_RXN11
Y48
Y36
AA43
AD37
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK
B37
A37
C40
PEG_RXN15 20
PEG_RXN14 20
PEG_RXP0 20
PEG_RXP1 20
PEG_RXP0
PEG_RXP1
PEG_RXN15
PEG_RXN14
AC47
AD39
H43
J44
PEG_RX_0
PEG_RX_1
PEG_RX#_14
PEG_RX#_15
LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2
LVDSA_DATA#_3
E46
A40
H47
G40
PEG_RXP5 20
PEG_RXP6 20
PEG_RXP4 20
PEG_RXP3 20
PEG_RXP2 20
PEG_RXP4
PEG_RXP6
PEG_RXP5
PEG_RXP3
PEG_RXP2
L43
L41
N40
P47
N43
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
LVDSA_DATA_1
LVDSA_DATA_2
LVDSA_DATA_0
LVDSA_DATA_3
F40
B40
D45
H48
PEG_RXP7 20
PEG_RXP8 20
PEG_RXP9 20
PEG_RXP11 20
PEG_RXP10 20
PEG_RXP7
PEG_RXP12
PEG_RXP10
PEG_RXP8
PEG_RXP9
PEG_RXP11
T42
U42
Y42
W47
Y37
AA42
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2
LVDSB_DATA#_3
J37
A41
B42
H38
G37
PEG_RXP12 20
PEG_RXP13 20
PEG_RXP15 20
PEG_RXP14 20
1 2
C1289 0.1U_0402_16V4ZC1289 0.1U_0402_16V4Z
PEG_RXP14
PEG_RXP13
PEG_RXP15
PEG_TXN0
AD36
AC48
AD40
J41
PEG_TX#_0
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
LVDSB_DATA_1
LVDSB_DATA_2
LVDSB_DATA_0
LVDSB_DATA_3
F37
K37
G38
1 2
C1290 0.1U_0402_16V4ZC1290 0.1U_0402_16V4Z
PEG_TXN1
M46
1 2
1 2
1 2
1 2
1 2
1 2
1 2
C1298 0.1U_0402_16V4ZC1298 0.1U_0402_16V4Z
C1293 0.1U_0402_16V4ZC1293 0.1U_0402_16V4Z
C1297 0.1U_0402_16V4ZC1297 0.1U_0402_16V4Z
C1292 0.1U_0402_16V4ZC1292 0.1U_0402_16V4Z
C1294 0.1U_0402_16V4ZC1294 0.1U_0402_16V4Z
C1291 0.1U_0402_16V4ZC1291 0.1U_0402_16V4Z
C1296 0.1U_0402_16V4ZC1296 0.1U_0402_16V4Z
C1299 0.1U_0402_16V4ZC1299 0.1U_0402_16V4Z
C1295 0.1U_0402_16V4ZC1295 0.1U_0402_16V4Z
PEG_TXN5
PEG_TXN7
PEG_TXN9
PEG_TXN6
PEG_TXN10
PEG_TXN8
PEG_TXN4
PEG_TXN3
PEG_TXN2
M40
M47
PEG_TX#_1
PEG_TX#_2
TVA_DAC
F25
H25
Y40
M42
R48
N38
T40
U37
U40
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
TV VGA
TV VGA
TVB_DAC
TVC_DAC
TV_RTN
K25
H24
C31
1 2
1 2
1 2
1 2
1 2
C1300 0.1U_0402_16V4ZC1300 0.1U_0402_16V4Z
C1304 0.1U_0402_16V4ZC1304 0.1U_0402_16V4Z
C1303 0.1U_0402_16V4ZC1303 0.1U_0402_16V4Z
C1301 0.1U_0402_16V4ZC1301 0.1U_0402_16V4Z
C1302 0.1U_0402_16V4ZC1302 0.1U_0402_16V4Z
PEG_TXN13
PEG_TXN14
PEG_TXN15
PEG_TXN12
PEG_TXN11
AA46
AA37
AA40
AD43
AC46
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15
PCI-EXPRESS GRAPHICS
PCI-EXPRESS GRAPHICS
TV_DCONSEL_0
TV_DCONSEL_1
E32
1 2
C1305 0.1U_0402_16V4ZC1305 0.1U_0402_16V4Z
PEG_TXP0
J42
E28
1 2
1 2
1 2
1 2
1 2
1 2
1 2
C1308 0.1U_0402_16V4ZC1308 0.1U_0402_16V4Z
C1307 0.1U_0402_16V4ZC1307 0.1U_0402_16V4Z
C1306 0.1U_0402_16V4ZC1306 0.1U_0402_16V4Z
C1310 0.1U_0402_16V4ZC1310 0.1U_0402_16V4Z
C1309 0.1U_0402_16V4ZC1309 0.1U_0402_16V4Z
PEG_TXP5
PEG_TXP4
PEG_TXP1
PEG_TXP2
PEG_TXP3
L46
M48
M39
M43
R47
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
CRT_BLUE
CRT_GREEN
CRT_RED
J28
G28
1 2
1 2
1 2
1 2
1 2
1 2
C1316 0.1U_0402_16V4ZC1316 0.1U_0402_16V4Z
C1315 0.1U_0402_16V4ZC1315 0.1U_0402_16V4Z
C1313 0.1U_0402_16V4ZC1313 0.1U_0402_16V4Z
C1311 0.1U_0402_16V4ZC1311 0.1U_0402_16V4Z
C1312 0.1U_0402_16V4ZC1312 0.1U_0402_16V4Z
C1314 0.1U_0402_16V4ZC1314 0.1U_0402_16V4Z
PEG_TXP7
PEG_TXP6
PEG_TXP11
PEG_TXP9
PEG_TXP8
PEG_TXP10
N37
T39
U36
U39
Y39
Y46
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF
CRT_IRTN
J32
J29
E29
H32
G29
1 2
1 2
1 2
1 2
C1319 0.1U_0402_16V4ZC1319 0.1U_0402_16V4Z
C1320 0.1U_0402_16V4ZC1320 0.1U_0402_16V4Z
C1317 0.1U_0402_16V4ZC1317 0.1U_0402_16V4Z
C1318 0.1U_0402_16V4ZC1318 0.1U_0402_16V4Z
PEG_TXP13
PEG_TXP12
PEG_TXP14
PEG_TXP15
AA36
AA39
AD42
AD46
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
CRT_VSYNC
L29
CANTIGA ES_FCBGA1329
CANTIGA ES_FCBGA1329
Deciphered Date
Deciphered Date
Deciphered Date
2008/11/04 2008/11/04
2008/11/04 2008/11/04
2008/11/04 2008/11/04
3
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Security Classification
Security Classification
Security Classification
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
R148
0_0402_5%
R148
0_0402_5%
1 2
@
@
5
D D
C C
B B
A A
5
www.rosefix.com
0.1
0.1
0.1
+VCCP
R93
0_0603_5%
R93
0_0603_5%
1 2
C79
C79
1
2
1U_0603_10V4Z
1U_0603_10V4Z
1
2
10U_0805_10V4Z
10U_0805_10V4Z
+V1.05VS_AXF
C78
C78
1
2
+1.8V
R95
0_0805_5%
R95
0_0805_5%
1 2
C85
C85
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
10U_0805_10V4Z
10U_0805_10V4Z
1
2
C84
+1.8V_SM_CK
10U_0805_10V4Z
10U_0805_10V4Z
C84
1
2
C83
C83
@
@
+1.5VS
R99
0_0805_5%
R99
0_0805_5%
1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.022U_0402_16V7K
0.022U_0402_16V7K
+1.5VS_TVDAC
+VCCP
R98
MBK2012121YZF_0805
R98
MBK2012121YZF_0805
1 2
10U_0805_10V4Z
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.05VS_HPLL
+VCCP
0_0805_5%
0_0805_5%
R102
R102
1 2
10U_0805_10V4Z
+VCC_PEG
+VCCP
+1.05VS_MPLL
10U_0805_10V4Z
1
C101
C101
220U_D2_4VM
220U_D2_4VM
+
+
1
C98
C98
R101
MBK2012121YZF_0805
R101
MBK2012121YZF_0805
1 2
C100
C100
1
1
C99
C99
2
2
10U_0805_10V4Z
10U_0805_10V4Z
2
2
1
2
C93
C93
1
2
C92
C92
1
2
C91
C91
1
2
C90
C90
+VCCP
R104
0_0603_5%
R104
0_0603_5%
1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.05VS_DMI
+VCCP
L1
BLM18PG121SN1D_0603
L1
BLM18PG121SN1D_0603
1 2
10U_0805_10V4Z
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.05VS_PEGPLL
C108
C108
C106
C106
C109
C109
1
2
1
2
1
2
+VCCP_D
+3VS_HV
0_0402_5%
0_0402_5%
R106
R106
1 2
R105
R105
1 2
10_0402_5%
10_0402_5%
D3
CH751H-40PT_SOD323-2
D3
CH751H-40PT_SOD323-2
2 1
+3VS
+VCCP
of
of
of
12 51Thursday, February 12, 2009
12 51Thursday, February 12, 2009
12 51Thursday, February 12, 2009
1
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
LA-4731P Rhett discrete
Cantiga(4/6)-PWR
LA-4731P Rhett discrete
Cantiga(4/6)-PWR
LA-4731P Rhett discrete
Cantiga(4/6)-PWR
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Custom
Custom
Custom
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2.2U_0805_16V4Z
2.2U_0805_16V4Z
1
2
C82
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
2
C72
C72
<BOM Structure>
<BOM Structure>
220U_D2_4VM
220U_D2_4VM
+
+
1
2
C71
+VCCP
C71
U13
T13
T12
U11
T11
U10
T10
U12
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTTU9VTTT9VTT
VTT
3
852mA
CRTPLLA PEGA SMTV
CRTPLLA PEGA SMTV
73mA
2.68mA
VCCA_CRT_DAC
VCCA_CRT_DAC
VCCA_DAC_BG
U2H
4
5
U2H
VSSA_DAC_BG
B27
A26
A25
B25
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
0.47U_0603_10V7K
0.47U_0603_10V7K
1
T7
U8
VTTU6VTTT6VTTU5VTT
VTTT8VTTU7VTT
VTT
VTT
64.8mA
64.8mA
VCCA_DPLLA
VCCA_DPLLB
L48
F47
C82
2
C81
C81
2
C80
C80
T5
VTTV3VTTU3VTTV2VTT
24mA
139.2mA
VCCA_HPLL
VCCA_MPLL
13.2mA
AE1
AD1
+1.05VS_MPLL
+1.05VS_HPLL
U2
VTTT2VTTV1VTT
VCCA_LVDS
VSSA_LVDS
J48
J47
U1
A LVDS
A LVDS
VCCA_PEG_BG
414uA
AD48
+1.5VS_PEG_BG
0_0603_5%
0_0603_5%
R96
1 2
@ R96
@
+3VS
R97
R97
50mA
0_0603_5%
0_0603_5%
1 2
+1.5VS
720mA
VCCA_PEG_PLL
VCCA_SM
VCCA_SM
AA48
AP20
AR20
AN20
+1.05VS_PEGPLL
C89
0.1U_0402_16V4Z
C89
0.1U_0402_16V4Z
1
2
POWER
POWER
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
VCCA_SM
AT16
AP17
AR17
AR16
AN17
+1.05VS_A_SM
R100
R100
+VCCP
VCCA_SM
AP16
C97
C97
1
1
C96
C96
4.7U_0805_10V4Z
4.7U_0805_10V4Z
10U_0805_10V4Z
10U_0805_10V4Z
1
C95
C95
0_0805_5%
0_0805_5%
1 2
+
+
1
C94
C94
220U_D2_4VM
220U_D2_4VM
+V1.05VS_AXF
B22
VCC_AXF
321.35mA
26mA
VCCA_SM_CK
VCCA_SM_CK
AP28
AN28
2
1U_0603_10V4Z
1U_0603_10V4Z
2
2
2
B21
A21
VCC_AXF
VCC_AXF
124mA
AXF
AXF
26mA
VCCA_SM_CK
VCCA_SM_CK
VCCA_SM_CK
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
AP25
AN25
AN24
AM28
AM26
AM25
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C105
C105
1U_0603_10V4Z
1U_0603_10V4Z
1
C104
C104
10U_0805_10V4Z
10U_0805_10V4Z
+1.05VS_A_SM_CK
1
C103
C103
1
<BOM Structure>
<BOM Structure>
C102
C102
0_0603_5%
0_0603_5%
R103
R103
1 2
+1.8V_SM_CK
BF21
BH20
BG20
BF20
VCC_SM_CK
VCC_SM_CK
VCC_SM_CK
VCC_SM_CK
118.8mA
SM CK
SM CK
A CK
A CK
TVA 24.15mA
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
VCCA_SM_CK_NCTF
AL25
AL24
AL23
AM24
AM23
2
2
2
2
1U_0603_10V4Z
1U_0603_10V4Z
+3VS_HV
K47
C35
B35
A35
VCC_HV
VCC_HV
VCC_HV
VCC_TX_LVDS
105.3mA
TVB 39.48mA
TVX 24.15mA
VCCA_TV_DAC
VCCA_TV_DAC
B24
A24
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C107
C107
+VCC_PEG
V48
U48
V47
U47
VCC_PEG
VCC_PEG
VCC_PEG
HV
HV
1732mA
HDA
HDA
50mA
VCC_HDA
A32
R107
R107
2
+1.05VS_DMI
AH48
U46
VCC_DMI
VCC_PEG
VCC_PEG
PEG
PEG
58.67mA
48.363mA
VCCD_TVDAC
VCCD_QDAC
L28
M25
+1.5VS_QDAC
+1.5VS_TVDAC
0_0402_5%
0_0402_5%
1 2
AF48
AH47
AG47
VCC_DMI
VCC_DMI
VCC_DMI
456mA
DMI
DMI
D TV/CRT
D TV/CRT
50mA
157.2mA
VCCD_PEG_PLL
VCCD_HPLL
AF1
AA47
+1.05VS_HPLL
+1.05VS_PEGPLL
VTTLFA8VTTLFL1VTTLF
VCCD_LVDS
VCCD_LVDS
L37
M38
1
0.47U_0603_10V7K
0.47U_0603_10V7K C112
C112
1
0.47U_0603_10V7K
0.47U_0603_10V7K C111
C111
1
0.47U_0603_10V7K
0.47U_0603_10V7K C110
C110
AB2
VTTLF
VTTLF
LVDS
LVDS
60.31mA
CANTIGA ES_FCBGA1329
CANTIGA ES_FCBGA1329
2
2
2
+1.5VS
R112
100_0603_1%
R112
100_0603_1%
1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C120
C120
0.01U_0402_16V7K
0.01U_0402_16V7K
1
2
C119
C119
+1.5VS_QDAC
Deciphered Date
Deciphered Date
Deciphered Date
Compal Secret Data
Compal Secret Data
Compal Secret Data
2008/11/04 2008/11/04
2008/11/04 2008/11/04
2008/11/04 2008/11/04
3
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Security Classification
Security Classification
Security Classification
4
5
D D
C C
B B
A A
www.rosefix.com
0.1
0.1
0.1
C145 1U_0603_10V4ZC145 1U_0603_10V4Z
1
2
C144 1U_0603_10V4ZC144 1U_0603_10V4Z
1
2
C143 0.47U_0402_6.3V6KC143 0.47U_0402_6.3V6K
1
2
C142 0.22U_0603_10V7KC142 0.22U_0603_10V7K
1
1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF1
VCCSM_LF4
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
W20
U20
AM19
AL19
AK19
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
POWER
POWER
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC GFX NCTF
VCC GFX NCTF
VCC SMVCC GFX
VCC SMVCC GFX
AV44
BA37
AM40
VCC_SM_LF
VCC_SM_LF
AV21
VCC_SM_LF
VCC_SM_LF
V28
W26
V26
W25
V25
W24
V24
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
W23
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
W28
VCC_AXG_NCTF
2
2
C141 0.22U_0603_10V7KC141 0.22U_0603_10V7K
1
2
C140 0.1U_0402_16V 4ZC140 0.1U_0402_16V4Z
1
2
C139 0.1U_0402_16V 4ZC139 0.1U_0402_16V4Z
1
2
VCCSM_LF6
VCCSM_LF7
VCCSM_LF5
AY5
AM10
BB13
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC SM LF
VCC SM LF
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
of
of
of
13 51Thursday, February 12, 2009
13 51Thursday, February 12, 2009
13 51Thursday, February 12, 2009
1
Cantiga(5/6)-PWR/G%D
Cantiga(5/6)-PWR/G%D
Cantiga(5/6)-PWR/G%D
LA-4731P Rhett discrete
LA-4731P Rhett discrete
LA-4731P Rhett discrete
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Custom
Custom
Custom
2
3000mA
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
BC32
C123
C123
2
C130
C130
1
C122
C122
1
C126
C126
+
+
BB32
BA32
AY32
AW32
1
2
2
2
AV32
VCC_SM
AU32
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
U2G
U2G
BF32
AP33
BD32
AN33
BH32
BG32
0.01U_0402_16V7K
0.01U_0402_16V7K
10U_0805_10V4Z
10U_0805_10V4Z
10U_0805_10V4Z
10U_0805_10V4Z
1
330U_D2E_2.5VM_R7
330U_D2E_2.5VM_R7
3
+1.8V
4
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
BF31
AT32
AP32
AR32
AN32
BH31
BG31
0317 change value
VCC_SM
VCC_SM
BH29
BG30
VCC_SM
BF29
BG29
VCC_SM
VCC_SM
VCC_SM
BD29
BC29
VCC CORE
VCC CORE
VCC_SM
VCC_SM
BB29
BA29
VCC_SM
AY29
AW29
VCC_SM
VCC_SM
AV29
AU29
VCC_SM
VCC_SM
AT29
AR29
VCC_SM
VCC_SM
AP29
VCC_SM/NC
BA36
BB24
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
BB21
BD16
AW16
+VCCP
6326.84mA
VCC_SM/NC
VCC_SM/NC
AT13
AW13
AM32
AL32
AK32
VCC_NCTF
VCC_NCTF
VCC_AXG
VCC_AXG
Y26
AE25
AJ32
AH32
AG32
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
Y24
AB25
AA25
AE24
AA24
AC24
AA32
Y32
W32
U32
AE32
AC32
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
POWER
POWER
VCC_AXG
VCC_AXG
VCC_AXG
AE23
AB23
AC23
AM30
AL30
AK30
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_AXG
VCC_AXG
VCC_AXG
AJ21
AA23
AG21
AG30
AF30
AH30
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_AXG
VCC_AXG
VCC_AXG
AE21
AA21
AC21
AC30
AE30
AB30
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_AXG
VCC_AXG
VCC_AXG
Y21
AF20
AH20
W30
AA30
Y30
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_AXG
VCC_AXG
VCC_AXG
AE20
AB20
AC20
V30
U30
AL29
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_AXG
VCC_AXG
T17
T16
AA20
AJ29
AH29
AK29
VCC_NCTF
VCC_NCTF
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
AL15
AE15
AM15
AG29
AE29
AC29
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC NCTF
VCC NCTF
VCC_AXG
VCC_AXG
VCC_AXG
AJ15
AH15
AG15
AA29
Y29
W29
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_AXG
VCC_AXG
VCC_AXG
AF15
AB15
AA15
AL28
AK28
V29
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_AXG
VCC_AXG
Y15
V15
U15
AK25
AL26
AK26
VCC_NCTF
VCC_NCTF
VCC_AXG
VCC_AXG
VCC_AXG
U14
AN14
AM14
AK24
AK23
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_AXG
VCC_AXG
T14
VCC_AXG_SENSE
VSS_AXG_SENSE
AJ14
AH14
@
T43PAD@T43PAD@T42PAD@T42PAD
CANTIGA ES_FCBGA1329
CANTIGA ES_FCBGA1329
Deciphered Date
Deciphered Date
Deciphered Date
2008/11/04 2008/11/04
2008/11/04 2008/11/04
2008/11/04 2008/11/04
Issued Date
Issued Date
Issued Date
Security Classification
Security Classification
Security Classification
3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
Extnal Graphic: 1210.34mA
integrated Graphic: 1930.4mA
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AF25
AG24
VCC
T32
AJ23
AF23
AH23
C C
B B
CANTIGA ES_FCBGA1329
CANTIGA ES_FCBGA1329
5
A A
U2F
U2F
Y34
V34
U34
AA34
AJ33
AK33
AM33
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.22U_0402_10V4Z
0.22U_0402_10V4Z
0.22U_0402_10V4Z
0.22U_0402_10V4Z
AB34
AC34
AG34
+VCCP
5
D D
AF33
AE33
AC33
AG33
C125
C125
1
C133
C133
1
C132
C132
1
C124
C124
1
10U_0805_10V4Z
10U_0805_10V4Z
C131
C131
+
+
1
220U_D2_4VM
220U_D2_4VM
AA33
Y33
V33
U33
W33
2
2
2
2
2
AH28
AF28
AC28
AA28
AJ26
AG26
AE26
AC26
AH25
AG25
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of
of
14 51Monday, February 16, 2009
14 51Monday, February 16, 2009
14 51Monday, February 16, 2009
1
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
AH8
AY7
AU7
AN7
AJ7
AE7
AA7
BG6
BD6
AV6
AT6
AM6
BA5
AH5
AD5
BE4
BC3
AV3
AL3
BA2
AR2
AU2
AP2
AW2
2
U2J
U2J
BG21
VSS
VSSY8VSSL8VSSE8VSSB8VSS
VSS
VSS
VSS
VSS
L12
AU21
AW21
AP21
VSS
VSS
AN21
VSS
VSS
AH21
AF21
VSS
VSS
VSS
VSS
AB21
VSS
VSS
VSSN7VSSJ7VSS
VSS
VSS
VSS
VSS
VSSM6VSSC6VSS
VSS
VSS
VSSY5VSSL5VSSJ5VSSH5VSSF5VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J21
R21
G21
M21
BC20
BA20
AW20
AT20
AJ20
AG20
Y20
F20
K20
N20
C20
VSS
VSS
VSS
VSSR3VSSP3VSS
VSSF3VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A20
A18
R17
H17
C17
M17
AT17
BG19
BG17
BC17
AW17
BA16
VSS
VSS
AU16
VSS
VSS
AN16
AE2
AF2
AH2
AJ2
AD2
AC2
AM1
AA1
H1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSY2VSSM2VSSK2VSS
VSS
VSSP1VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K16
E16
N16
G16
W15
AC15
BG15
VSS
A15
C14
AA14
BA13
BC13
BG14
BG13
AF32
AB32
V32
AJ30
AM29
AF29
AB29
U26
U23
AL20
V20
AC19
AL17
AJ17
AA17
U17
BH48
BH1
A48
U24
U28
U25
U29
VSS
VSS
VSS
VSS
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS NCTF
VSS NCTF
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AN13
AJ13
AE13
L13
N13
G13
J12
E13
BF12
AV12
AT12
AM12
AA12
A12
BD11
BB11
AY11
AN11
AH11
Y11
A3NCE1NCD2NCC3NCB4NCA5NCA6NCA43NCA44NCB45NCC46NCD47NCB47NCA46NCF48NCE48NCC48NCB48
VSS_SCB
VSS_SCB
VSS_SCB
VSS_SCBC1VSS_SCB
VSS_NCTF
VSS SCB
VSS SCB
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
N11
C11
G11
BG10
AV10
AT10
AJ10
AE10
AA10
BF9
M10
NC
NC
VSS
VSSB9VSSG9VSS
VSS
VSS
VSS
BC9
VSS
VSS
VSS
CANTIGA ES_FCBGA1329
CANTIGA ES_FCBGA1329
AT8
BB8
AV8
BH8
AD9
AN9
AM9
2008/11/04 2008/11/04
2008/11/04 2008/11/04
2008/11/04 2008/11/04
1
Cantiga(6/6)-PWR/G%D
Cantiga(6/6)-PWR/G%D
Cantiga(6/6)-PWR/G%D
LA-4731P Rhett discrete
LA-4731P Rhett discrete
LA-4731P Rhett discrete
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Custom
Custom
Custom
2
Deciphered Date
Deciphered Date
Deciphered Date
3
Security Classification
Security Classification
Security Classification
AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
AT24
AH24
AB24
L24
VSS
VSS
AF24
F38
VSS
VSS
G24
R24
K24
J24
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C38
BF37
AT37
BB37
AN37
AW37
AY24
AJ24
4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
U2I
U2I
Y47
AJ47
AL48
AF47
BB47
AW47
AN47
AD47
AB47
AU48
AR48
VSS
L47
T47
N47
G47
AY46
BA46
AV46
BD46
AR46
AM46
F46
Y44
BF44
AH44
AD44
AA44
T44
U44
V46
P46
R46
H46
J43
F44
BC43
AV43
AU43
AM43
C43
BG42
M44
AY42
AT42
AN42
AJ42
AE42
L42
N42
BD41
AU41
AM41
AH41
AD41
AA41
Y41
T41
B41
U41
M41
H40
G41
BB40
AV40
AN40
BG40
VSS
L39
E40
AT39
AM39
AJ39
AE39
B39
N39
VSS
VSS
VSS
VSS
BH38
VSS
VSS
BC38
BA38
VSS
VSS
VSS
VSS
AU38
AH38
VSS
VSS
VSS
VSS
AD38
AD12
AA38
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J38
Y38
T38
U38
F24
AJ37
VSS
VSS
A23
E24
AG23
B23
BH23
Y23
AJ6
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CANTIGA ES_FCBGA1329
CANTIGA ES_FCBGA1329
H37
C37
AK15
BD36
AU36
BG36
3
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
5
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C C
B B
A A
5
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15 51Monday, February 16, 2009
15 51Monday, February 16, 2009
15 51Monday, February 16, 2009
V_DDR_MCH_REF 9,16
1
C151
C151
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C146
C146
1
2
2.2U_0805_16V4Z
2.2U_0805_16V4Z
DDR_A_DM0
DDR_A_D0
DDR_A_D6
DDR_A_D5
DDR_A_D7
+1.8V
2
6
8
10
12
16
2
VSS
DQ44DQ5
VSS
DM0
VSS
DQ614DQ7
DDR_A_D12
DDR_A_D13
18
22
VSS
DQ1220DQ13
DDR_A_DM1
24
26
28
VSS
VSS
DM1
M_CLK_DDR0 9
M_CLK_DDR#0 9
M_CLK_DDR0
M_CLK_DDR#0
30
32
34
CK0
VSS
CK0#
DQ1436DQ15
38
VSS40VSS
DDR_A_D20
DDR_A_D21
42
46
DQ2044DQ21
PM_EXTTS#0 9
48NC50
VSS
DDR_A_DM2
DDR_A_D22
DDR_A_D23
52
54
58
VSS
DM2
DQ2256DQ23
DDR_A_D28DDR_A_D29
DDR_A_D25DDR_A_D24
60
64
VSS
DQ2862DQ29
DDR_A_DQS3
DDR_A_DQS#3
66
68
70
72
VSS
VSS
DQS3
DQS3#
DDR_CKE1_DIMMA 9
DDR_CKE1_DIMMA
DDR_A_D31
DDR_A_D30
76
78
80
VSS
DQ3074DQ31
NC/CKE1
DDR_A_MA14
82
86
VDD
NC/A1584NC/A14
DDR_A_MA11
DDR_A_MA6
88
90A792A694
A11
VDD
DDR_A_MA2
DDR_A_MA4
96A498A2100A0102
VDD
DDR_A_BS1 10
DDR_A_RAS# 10
DDR_A_MA0
DDR_A_BS1
DDR_A_RAS#
104
106
108
BA1
VDD
RAS#
DDR_CS0_DIMMA# 9
M_ODT0 9
DDR_CS0_DIMMA#
DDR_A_MA13
M_ODT0
110
112
114
116
118NC120
122
S0#
VDD
VDD
ODT0
NC/A13
DDR_A_D32
DDR_A_D33
124
126
128
VSS
DQ36
DQ37
DDR_A_DM4
DDR_A_D34
130
132
134
VSS
VSS
DM4
DQ38
DDR_A_D35
DDR_A_D40
DDR_A_D41
136
138
140
142
VSS
DQ39
DQ44
DDR_A_DQS5
DDR_A_DQS#5
144
146
148
VSS
DQ45
DQS5
DQS5#
150
152
VSS
DQ46
DDR_A_D53
DDR_A_D52
DDR_A_D42
154
156
158
160
VSS
DQ47
DQ52
M_CLK_DDR1 9
M_CLK_DDR1
M_CLK_DDR#1
162
164
166
CK1
VSS
DQ53
M_CLK_DDR#1 9
DDR_A_DM6
168
170
VSS
DM6
CK1#
DDR_A_D55
DDR_A_D51DDR_A_D54
172
174
176
VSS
DQ54
178
DQ55
VSS
DDR_A_D56
180
182
184
DQ60
DQ61
DDR_A_DQS7
DDR_A_DQS#7
DDR_A_D62
186
188
190
192
VSS
VSS
DQ62
DQS7
DQS7#
DDR_A_D63
194
196
198
200
VSS
SAO
DQ63
12
12
SA1
SO-DIMM A
R116
R116
R115
R115
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
1
DDRII-SODIMM SLOT1
DDRII-SODIMM SLOT1
DDRII-SODIMM SLOT1
LA-4731P Rhett discrete
LA-4731P Rhett discrete
LA-4731P Rhett discrete
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Custom
Custom
Custom
2
3
4
5
VREF1VSS3DQ05DQ17VSS9DQS0#11DQS013VSS15DQ217DQ319VSS21DQ823DQ925VSS27DQS1#29DQS131VSS33DQ1035DQ1137VSS39VSS41DQ1643DQ1745VSS47DQS2#49DQS251VSS53DQ1855DQ1957VSS59DQ2461DQ2563VSS65DM367NC69VSS71DQ2673DQ2775VSS77CKE079VDD81NC83BA285VDD87A1289A991A893VDD95A597A399A1
V_DDR_MCH_REF
JDIMM1
JDIMM1
+1.8V
DDR_A_D8
DDR_A_DQS0
DDR_A_DQS#0
DDR_A_D1
DDR_A_D2
DDR_A_D4
DDR_A_D[0..63]10
DDR_A_DQS#[0..7]10
DDR_A_DM[0..7]10
DDR_A_DQS[0..7]10
DDR_A_MA[0..14]10
DDR_A_DQS#1
DDR_A_D9
DDR_A_D3
Layout Note:
Place near
JP3
DDR_A_DQS1
DDR_A_D11 DDR_A_D15
DDR_A_D10 DDR_A_D14
330U_D2E_2.5VM_R7
330U_D2E_2.5VM_R7
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2.2U_0805_16V4Z
2.2U_0805_16V4Z
2.2U_0805_16V4Z
2.2U_0805_16V4Z
2.2U_0805_16V4Z
2.2U_0805_16V4Z
2.2U_0805_16V4Z
2.2U_0805_16V4Z
+1.8V
2.2U_0805_16V4Z
2.2U_0805_16V4Z
DDR_A_D17
DDR_A_D16
DDR_A_DQS#2
C150
C150
+
+
1
C157
C157
1
C149
C149
1
C148
C148
1
C156
C156
1
C155
C155
1
C154
C154
1
C153
C153
1
C147
C147
1
C152
C152
1
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
2
2
2
2
2
2
2
2
2
2
DDR_A_D26
DDR_A_DM3
DDR_A_D27
VDD
A10/AP
BA0
101
103
105
107
DDR_A_MA1
DDR_A_MA10
DDR_A_MA3
DDR_A_MA9 DDR_A_MA7
DDR_A_MA12
DDR_A_MA5
+0.9V
DDR_A_WE#
DDR_A_BS0
DDR_A_BS010
DDR_CKE0_DIMMA
Layout Note:
DDR_A_MA8
DDR_A_BS2
DDR_A_BS210
DDR_CKE0_DIMMA9
Place one cap close to every 2
pullup
resistors terminated to +0.9VS
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
109
111
113
115
117
119
DDR_CS1_DIMMA#
DDR_A_CAS#
M_ODT1
DDR_A_WE#10
M_ODT19
DDR_A_CAS#10
DDR_CS1_DIMMA#9
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
VSS
DQ32
DQ33
121
123
125
DDR_A_D36
DDR_A_D37
C170
C170
2
C169
C169
2
C168
C168
2
C167
C167
2
C166
C166
2
C165
C165
2
C164
C164
2
C163
C163
2
C162
C162
2
C161
C161
2
C160
C160
2
C159
C159
2
C158
C158
2
VSS
DQS4#
DQS4
VSS
127
129
131
133
DDR_A_DQS4
DDR_A_DQS#4
DQ34
DQ35
VSS
135
137
139
141
DDR_A_D39
DDR_A_D38
DDR_A_D45
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
143
145
147
149
151
153
DDR_A_DM5
DDR_A_D44
DDR_A_D46
DDR_A_D47 DDR_A_D43
Layout Note:
Place these resistor
closely JP3,all
RP26
RP26
+0.9V
RP25
RP25
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
155
157
159
161
163
165
167
169
171
173
175
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_D49
DDR_A_D48
DDR_A_D50
trace length Max=1.5"
DDR_A_BS2
DDR_CKE0_DIMMA
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA3
DDR_A_MA5
182736
1 8
2 7
DDR_A_MA6
DDR_A_MA11
182736
45
RP27
RP27
56_8P4R_0.05
56_8P4R_0.05
3 6
4 5
56_8P4R_0.05
56_8P4R_0.05
DDR_A_MA14
DDR_CKE1_DIMMA
RP556_0404_4P2R_5% RP556_0404_4P2R_5%
1 4
DDR_A_BS1
VSS
DQ56
DQ57
VSS
DM7
VSS
177
179
181
183
185
187
189
DDR_A_DM7
DDR_A_D60
DDR_A_D61 DDR_A_D57
DDR_A_D59
DDR_A_MA1
DDR_A_BS0
DDR_A_MA10
182736
45
RP29
RP29
56_8P4R_0.05
56_8P4R_0.05
RP28
RP28
2 3
1 8
2 7
DDR_A_MA0
DDR_A_RAS#
DDR_CS0_DIMMA#
DQ58
DQ59
VSS
SDA
191
193
195
197
CLK_SMBCLK
CLK_SMBDATA
DDR_A_D58
CLK_SMBDATA16,17,36
DDR_A_CAS#
DDR_A_WE#
45
56_8P4R_0.05
56_8P4R_0.05
3 6
4 5
56_8P4R_0.05
56_8P4R_0.05
DDR_A_MA4
DDR_A_MA2
SCL
VDDSPD
FOX_ASOA426-M4R-TR
FOX_ASOA426-M4R-TR
199
1
C172
C172
C171
C171
1
+3VS
CLK_SMBCLK16,17,36
DDR_A_MA13
14
23
RP12 56_0404_4P2R_5%RP12 56_0404_4P2R_5%
RP1156_0404_4P2R_5% RP1156_0404_4P2R_5%
1 4
2 3
M_ODT1
DDR_CS1_DIMMA# M_ODT0
2
2
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
1 2
DDR_A_MA7
Deciphered Date
Deciphered Date
Deciphered Date
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2008/11/04 2008/11/04
2008/11/04 2008/11/04
2008/11/04 2008/11/04
3
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Security Classification
Security Classification
Security Classification
R117 56_0402_5%R117 56_0402_5%
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
5
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C C
B B
A A
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0.1
of
of
of
16 51Monday, February 16, 2009
16 51Monday, February 16, 2009
16 51Monday, February 16, 2009
1
2
+1.8V
+1.8V
V_DDR_MCH_REF 9,15
C182
C182
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C173
C173
1
2
2.2U_0805_16V4Z
2.2U_0805_16V4Z
DDR_B_D6
DDR_B_D7
DDR_B_DM0
DDR_B_D5
DDR_B_D4
2
6
8
10
12
16
VSS
VSS
VSS
DQ44DQ5
DQ614DQ7
DM0
VREF1VSS3DQ05DQ17VSS9DQS0#11DQS013VSS15DQ217DQ319VSS21DQ823DQ925VSS27DQS1#29DQS131VSS33DQ1035DQ1137VSS39VSS41DQ1643DQ1745VSS47DQS2#49DQS251VSS53DQ1855DQ1957VSS59DQ2461DQ2563VSS65DM367NC69VSS71DQ2673DQ2775VSS77CKE079VDD81NC83BA285VDD87A1289A991A893VDD95A597A399A1
V_DDR_MCH_REF
JDIMM2
JDIMM2
DDR_B_D1
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D0
DDR_B_D13
DDR_B_D12
18
22
VSS
DQ1220DQ13
DDR_B_D2
DDR_B_D3
DDR_B_DM1
24
26
28
VSS
VSS
DM1
DDR_B_D8
DDR_B_D9
M_CLK_DDR2 9
M_CLK_DDR#2 9
DDR_B_D14
DDR_B_D15
M_CLK_DDR2
M_CLK_DDR#2
30
32
34
38
CK0
VSS
CK0#
DQ1436DQ15
DDR_B_D11
DDR_B_D10
DDR_B_DQS1
DDR_B_DQS#1
42
VSS40VSS
DDR_B_D16DDR_B_D21
DDR_B_D17
46
48NC50
VSS
DQ2044DQ21
DDR_B_DQS#2
DDR_B_D20
PM_EXTTS#1 9
DDR_B_DM2
DDR_B_D23
DDR_B_D22
52
54
58
VSS
DM2
DQ2256DQ23
DDR_B_DQS2
DDR_B_D19
DDR_B_D18
DDR_B_D29
DDR_B_D24DDR_B_D25
60
64
VSS
DQ2862DQ29
DDR_B_D28
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D26
66
68
70
72
VSS
VSS
DQS3
DQS3#
DDR_B_DM3
DDR_B_D30
DDR_CKE3_DIMMB 9
DDR_CKE3_DIMMB
DDR_B_D27
76
78
80
82
VSS
DQ3074DQ31
NC/CKE1
DDR_CKE2_DIMMB
DDR_B_D31
DDR_B_MA14
86
VDD
NC/A1584NC/A14
DDR_B_BS2
0612 add
DDR_B_MA7
DDR_B_MA11
DDR_B_MA6
88
90A792A694
96A498A2100A0102
A11
VDD
DDR_B_MA8
DDR_B_MA12
DDR_B_MA9
DDR_B_MA2
DDR_B_MA4
DDR_B_MA0
VDD
101
DDR_B_MA3
DDR_B_MA5
DDR_B_MA1
DDR_CS2_DIMMB# 9
DDR_B_BS1 10
DDR_B_RAS# 10
DDR_B_RAS#
DDR_B_BS1
DDR_CS2_DIMMB#
104
106
108
110
S0#
BA1
VDD
RAS#
VDD
A10/AP
BA0
WE#
103
105
107
109
DDR_B_WE#
DDR_B_MA10
DDR_B_BS0
M_ODT2 9
M_ODT2
DDR_B_MA13
112
114
116
118NC120
VDD
VDD
ODT0
NC/A13
VDD
CAS#
NC/S1#
VDD
NC/ODT1
111
113
115
117
119
DDR_CS3_DIMMB#
M_ODT3
DDR_B_CAS#
DDR_B_D36
DDR_B_D33
122
124
126
VSS
DQ36
DQ37
VSS
DQ32
DQ33
121
123
125
DDR_B_D32
DDR_B_D37
DDR_B_DM4
DDR_B_D38
DDR_B_D39
128
130
132
134
136
201
VSS
VSS
DM4
DQ38
VSS
DQS4#
DQS4
VSS
127
129
131
133
135
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D45
DDR_B_D44
138
140
142
VSS
VSS DQ39
DQ44
DQ34
DQ35
VSS
137
139
141
DDR_B_D40
DDR_B_D35
DDR_B_DQS5
DDR_B_DQS#5
144
146
148
VSS
DQ45
DQS5
DQS5#
DQ40
DQ41
VSS
DM5
143
145
147
DDR_B_D41
DDR_B_DM5
DDR_B_D47
DDR_B_D46
150
152
154
VSS
DQ46
DQ47
VSS
DQ42
DQ43
149
151
153
DDR_B_D42
DDR_B_D43
DDR_B_D54
DDR_B_D51
156
158
160
VSS
DQ52
VSS
DQ48
155
157
159
DDR_B_D55
DDR_B_D50
M_CLK_DDR3 9
M_CLK_DDR3
M_CLK_DDR#3
162
164
166
CK1
VSS
DQ53
DQ49
VSS
NC,TEST
161
163
165
M_CLK_DDR#3 9
DDR_B_D49
DDR_B_DM6
168
170
172
174
VSS
VSS
DM6
CK1#
DQ54
VSS
DQS6#
DQS6
VSS
DQ50
167
169
171
173
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D52
DDR_B_D48
DDR_B_D56
176
178
180
182
VSS
DQ55
DQ60
DQ51
VSS
DQ56
175
177
179
181
DDR_B_D60
DDR_B_D53
DDR_B_D61 DDR_B_D57
DDR_B_DQS#7
DDR_B_DQS7
184
186
188
VSS
DQ61
DQS7
DQS7#
DQ57
VSS
DM7
VSS
183
185
187
DDR_B_DM7
DDR_B_D62
DDR_B_D59
190
192
194
196
VSS
DQ62
DQ63
DQ58
DQ59
VSS
189
191
193
195
DDR_B_D58
DDR_B_D63
CLK_SMBDATA
+3VS
R118
R118
10K_0402_5%
10K_0402_5%
1 2
R119
R119
12
10K_0402_5%
10K_0402_5%
198
200
SA0
SA1
VSS
SDA
SCL
VDDSPD
197
199
1
1
CLK_SMBCLK
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
SO-DIMM B
FOX_AS0A426-N8RN-7F
FOX_AS0A426-N8RN-7F
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C198
C198
C197
C197
2
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
1
LA-4731P Rhett discrete
LA-4731P Rhett discrete
LA-4731P Rhett discrete
DDRII-SODIMM SLOT2
DDRII-SODIMM SLOT2
DDRII-SODIMM SLOT2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
2
Deciphered Date
Deciphered Date
Deciphered Date
2008/11/04 2008/11/04
2008/11/04 2008/11/04
2008/11/04 2008/11/04
DDR_B_MA1
DDR_B_MA8
45
56_8P4R_0.05
56_8P4R_0.05
+3VS
CLK_SMBDATA15,17,36
CLK_SMBCLK15,17,36
DDR_B_BS0
182736
RP34
RP34
DDR_B_WE#
DDR_B_MA10
DDR_B_CAS#
45
M_ODT2
DDR_B_MA13
182736
RP35
RP35
56_8P4R_0.05
56_8P4R_0.05
3
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Security Classification
Security Classification
Security Classification
DDR_B_RAS#
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
DDR_CS2_DIMMB#
45
56_8P4R_0.05
56_8P4R_0.05
5
3
DDR_B_BS210
DDR_CKE2_DIMMB9
C181
C181
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C180
5
+1.8V
C180
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C179
C179
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C178
C178
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C177
C177
1
2
2.2U_0805_16V4Z
2.2U_0805_16V4Z
C183
C183
1
2
2.2U_0805_16V4Z
2.2U_0805_16V4Z
C176
C176
1
2
2.2U_0805_16V4Z
2.2U_0805_16V4Z
C175
C175
1
2
2.2U_0805_16V4Z
2.2U_0805_16V4Z
C174
C174
1
2
2.2U_0805_16V4Z
2.2U_0805_16V4Z
Layout Note:
Place one cap close to every 2
pullup
resistors terminated to +0.9VS
4
5
DDR_B_MA[0..14]10
DDR_B_D[0..63]10
DDR_B_DQS#[0..7]10
DDR_B_DM[0..7]10
DDR_B_DQS[0..7]10
Layout Note:
Place near
JP10
5 10
+0.9V
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
M_ODT39
DDR_B_WE#10
DDR_B_BS010
DDR_B_CAS#10
DDR_CS3_DIMMB#9
C196
C196
1
2
C195
C195
1
2
C194
C194
1
2
C193
C193
1
2
C192
C192
1
2
C191
C191
1
2
C190
C190
1
2
C189
C189
1
2
C188
C188
1
2
C187
C187
1
2
C186
C186
1
2
C185
C185
1
2
C184
C184
1
2
Layout Note:
Place these resistor
closely JP3,all
trace length Max=1.5"
DDR_B_MA7
DDR_B_MA6
DDR_B_MA11
DDR_B_MA14
182736
45
RP31
RP31
56_8P4R_0.05
56_8P4R_0.05
+0.9V
RP30
RP30
1 8
2 7
3 6
4 5
56_8P4R_0.05
56_8P4R_0.05
DDR_B_MA0
DDR_B_BS1
DDR_B_MA4
DDR_B_MA2
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_CKE2_DIMMB
182736
45
RP32
RP32
56_8P4R_0.05
56_8P4R_0.05
RP2456_0404_4P2R_5% RP2456_0404_4P2R_5%
1 4
2 3
DDR_CS3_DIMMB#
M_ODT3
DDR_B_MA5
DDR_B_MA3
182736
RP33
RP33
1 2
R120 56_0402_5%
R120 56_0402_5%
DDR_CKE3_DIMMB
D D
C C
B B
A A
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