HP DV3000-DIABLO20 60502215501 Schematics

REV

P/N

DATE POWER

VER :

XXXXXXXXXXXX

TITLECHECK

SIZE

DATE

DATE

DRAWER

REV

MP Build

3

DESIGN

CHANGE NO.

DIABLO 2.0

DOC. NUMBERSIZE =

EE

OF

2008.08.11

INVENTEC

A02

1310A22155-0-MTR

1 61

A3

CS

DIABLO 2.0 MV

FILE NAME : XXXX-XXXXXX-XX

CODE

SHEET

Release version : MP 02

RESPONSIBLE

TABLE OF CONTENTS

PAGE
5- DC& BATTERY CHARGER

6- BATTERY CONN
7- SYSTEM POWER(3V/5V)

8- SYSTEM POWER(+V1.8/+VCCP)

9- GRAPHIC POWER(+VGFX_CORE)

10- SYSTEM POWER(+V1.5S)
11- CPU POWER(VCC_CORE)
12- DDR TERMINATION VOLTAGE
13- POWER(SLEEP)
14- POWER(SEQUENCE)

PAGE
15- CLOCK_ICS9LPRS397

16- PENRYN-1
17- PENRYN-2
18- PENRYN-3
19- THERMAL & FAN Conn
20- N/B Cantiga-1
21- N/B Cantiga-2
22- N/B Cantiga-3
23- N/B Cantiga-4
24- N/B Cantiga-5
25- N/B Cantiga-6
26- DDR2-DIMM0
27- DDR2-DIMM1
28- DDR2-DAMPING
29- CRT CONN
30- LCM CONN

31- S/B ICH9-1
32- S/B ICH9-2
33- S/B ICH9-3
34- S/B ICH9-4
35- S/B ICH9-5

PAGE
36­37- HDD&ODD CONN & Accelerometer
38- USB & eSATA CONN
39- KBC & IR & SPI BIOS & T/P Conn
40- KB&TP Disable CONN
41- AUDIO CODEC
42- AUDIO AMP-HP MIC VOL
43- MDC CONN & Audio Jack
44- LAN CONTROLLER- RTL8111C

45- LAN POWER
46- RJ45 CONN
47- MINICARD CONN
48- HDMI CONN & NEW CARD CONN

49- LED & BUTTON
50- SCREW
51- TOUCHPAD BOARD
52- WEB CAM & FINGER PRINT Conn
53- AU6372 Cardreader & 5 IN 1 Conn
54- nVIDIA NB9MGS-1

55- nVIDIA NB9MGS-2
56- nVIDIA NB9MGS-3
57- nVIDIA NB9MGS-4
58- nVIDIA NB9MGS-5

59- VRAM-1
60- VRAM-2
61- Release Note

CHANGE by

Wang, Alan

31-Jul-2008

INVENTEC

TITLE

DIABLO 2.0

CODE

CS

SHEET

DOC. NUMBER

OF

2 61

SIZE

A3

REV

A021310A22155-0-MTR

Clock Generator

RTM875N-606

P.15

MAIN BATT

System Charger &

DC/DC System power

V-RAM

64M X 16

(512M)

LCM

VGA
HDMI

P.59,60

P.30

P.29

P.48

DDR2 /400MHZ

LVDS

CRT

TMDS

NVIDIA

NB9M-GS

GB1-64

(G98-630-U2)

P.54~58

I2C

P.56

HDCP

PCI_EXPRESS

X16

Penrym

(478 uFCPGA)

FSB

Cantiga

PM45

(1329 FCBGA)

DMI

P.20~25

P.17~19

DDR2

DDR2

DDR II _SODIMM0

P.26

DDR II _SODIMM1

P.27

CARD READER

AU6372

5 in 1

Conn

P.53

CONNECTOR

RJ11

USB_5

P.53

MDC V1.5

USB_2

Conn

P.38

USB_3

WEB CAM

Conn

P.43

USB_1

Conn

FINGER PRINTER

P.52

P.38

Conn

DIGI MIC

P.52

ESATA + USB

USB_6

P.51

Mic IN

Conn

(USB_0)
P.38

BLUE TOOTH

Conn

P.38

USB_7

P.47

AUDIO CODEC

IDT 92HD71B

Headphone

P.42

P.42

SATA 5

USB2.0

P.41

Headphone

P.43

ICH9-M

676 mBGA

HDA

Speaker

P.42

SATA 0&1
PCI_EXPRESS (LAN)

PCI_EXPRESS

P.31~35

LPC

Keyboard

MINI CARD

CONN

(WLAN)

(USB_8)

TouchPad

P.40

ODD

ITE 8512E

P.39

P.39

CHANGE by

P.37

KBC

P.47

CIR

P.39

Wang, Alan

HDD

P.37

New Card

CONN

(USB_4)

SPI

SYSTEM

BIOS

P.48

P.36

31-Jul-2008

NIC GIGA

RTL8111C

P.44

RJ45

P.46

INVENTEC

TITLE

DIABLO 2.0

CODE

SIZE

A3

DOC. NUMBER

1310A22155-0-MTRA02

CS

SHEET

REV

OF

613

ADP_PRES

CHGCTRL_3

Adapter

(90W)

Selector

ADP_ID

(BQ24721)

+VBATR

Charger

+VBDC

+VBATT

AC_OK

CHGCTRL_3
BATT_IN

ADP_PRES
I_ADP

BATT_CLK
BATT_DATA

Main Battery

KBC_PW_ON

+V5A_PWRGD

SLP_S4#_EC

VGA_PG

5/3.3V

(TPS51120)

IO POWER

(TPS51124)

+V5AL

SLP_S3#_EC_V1.5S

SLP_S3#_EC

+V5A
+V3A

+V3AL

+V1.8

+VCCP

V1.8_PG

VCCP_PG

+V1.5S_ON

I = 100mA

I = 100mA

FDC655BN

LR

(G2997)

LR

(APL5913)

I = 13126mA

+V1.8S

+V0.9S

FDC655BN

FDC655BN

V1.5S_PG

M_VREF

+V1.5S

+V5S

I = 8860mA

I = 2000mA

I = 3610mA

+V3S

I = 7039mA

I = 4952mA

+VCORE_ON

PM_DPRSLPVR

PSI#

H_DPRSTP#

V1.5S_PG

nVIDIA

GPU POWER

(TPS51511)

IMVP VI

(ADP3208)

+VGAVCC

I MAX = 12A

+V1.1S

I MAX = 2A

VGA_PG

+VCC_CORE

I = 8360mA

I = 1653mA

VR_PWRGD

I = 38000mA

CHANGE by

INVENTEC

TITLE

DIABLO 2.0

CS

SHEET

DOC. NUMBERCODE

4 61

SIZE

31-Jul-2008Wang, Alan

A3

REV

A021310A22155-0-MTR

OF

C867

1

0603_OPEN

2

1

2

0.1uF_25v_0603

Add C848 & C850 for EMI

+VBATR

5-,7-,8-,9-,11-,13-,30-,36-

C868

1
2

0.1uF_25v_0603

1
2

1

R804
0603_OPEN

2

C747

33uF_25v

1

R805
0603_OPEN

2

2

D615

3

1

+VADP

5-

1

2

1

2

2VREF +V5AL

7-

1

2

R815
100K_1%_0402

R808

8.25K_1%_0402

R809

14.3K_1%_0402

0.022uF_16v_0402

BAT54S_30V_0.2A_OPEN

+V5AL

5

+

OUT

6

-

3

+

OUT

2

-

C880

1

2

Q629

1

S

D

2
3

G

FDS6675BZ

C869

R810

1 2

1M_5%_0402

5-,7-,49-

8

U615-B

7

ON_LM393DR2G_SOP_8P

4

1M_5%_0402

5-,7-,49-

8

U615-A

1

ON_LM393DR2G_SOP_8P

4

R811

1 2

C881

1
2

0.1uF_10v_0402

+V3AL

8
7
6
54

1

2

5-,6-,7-,31-,39-,49-

R807
15K_5%_0603

1 2

0_5%_0603

+VADP

5-

1

R364
200K_1%_0402

2

1

R365

24.3K_1%_0402

2

5-,6-,39-

1

R812
100K_5%_0402

2

For S4/5 Current 071129

1

R813

5-,6-,7-,31-,39-,49-

200K_5%_0402

2

For S4/5 Current 071129

39-

R356

ADP_PRES

AC_OK

+VADP +VADPTR

L629

5-

NFM60R30T222

1
2

C878

0.1uF_25v_0603

1 2

4

5-,6-,7-,31-,39-,49-

3

10pF_50v_0402

C877
10pF_50v_0402

1
2

0.01_1%_1W_2512

C484

1
2

0.1uF_25v_0603

CHARGE_GND

C479

1
2

2.2uF_25v_0805

+V5AL

5-,7-,49-

1

R357

8.06K_1%_0402

2

1

C478

CHARGE_GND

CHGCTRL_3

BATT_CLK

BATT_DATA

2

+V3AL

For S4/5 Current 071129

6-,39-

6-,39-

6-,39-

1

R358

22.6K_1%_0402

2

39-

1

R355

39.2K_1%_0402

2

R366

1

200K_5%_0402

1 2

10_5%_0402

1 2

10_5%_0402

1uF_10v_0603

+VADPTR

C876

1
2

0.1uF_25v_0603

R806

1 2

C483

1 2

0.1uF_25v_0603

Kevin sense

BATT_IN

2

R801

R802

5A

C879

1
2

+V3AL

CHENKO_LL4148_2P

CHARGE_GND

6-

BATT_TS

C875

1

1

2

2

1uF_25v_0603

0.1uF_25v_0603

For EMI

D17

prevent KBC latchup

C485

1
2

0.1uF_25v_0603

U19

12

VCC

3

ACN

4

ACP

6

BYPASS#

5

ACDET

11

VREF5

10

AGND

15

TS

1

CHGEN#

14

SCL

13

SDA

25

ALARM#

17

IOUT

TI_BQ24721C_QFN_32P

C471

1
2

0.1uF_10v_0402

CHARGE_GND

Add C845~6 FOR EMI

C913

1
2

0.1uF_25v_0603

21

1

1500pF_50v_0402

2

20071129

C912

C502

1
2

4.7uF_25v_0805

ACDRV#

SYS

BATDRV#

PVCC

HIDRV

PH

BTST

REGN

LODRV

PGND

SYNP

SYNN

SRP
SRN
BAT

EAO

EAI

FBO

ISYNSET

TML

R360

1 2

0_5%_0603

39-

C486

2

23

24

32

30

29

31

28

27
26
22
21
20
19
18

7

8
9

16
33

I_ADP

4.7_5%_0603

CHARGE_GND

1

R381
1K_1%_0603

2

39-

1

R382

13.7K_1%_0402

2

C870

1
2

0.01uF_50v_0603

R367

1 2

1 3

BAT54_30V_0.2A

1

R359
100K_5%_0402

2

PAD605

ADP_ID

20K_5%_0402

D16

1uF_25v_0603

1

2

DIPPAD_6P

1

2

3

4

5

6

R818

2

1

Q630

1

S

2
3

G

FDS6675BZ

C488

0.1uF_25v_0603

1 2

C487

1 2

1

2

R361
200K_5%_0402

1
2

100pF_50v_0402

+VADP

01

5-

1

R814
1_5%_0805

2

5-

AC_LED

R816

1 2

1M_5%_0402

3

+

2

-

R817

1 2

0402_OPEN

8

D

7
6
54

1

FAIR_FDMS9620S_MLP_8P

R362
18K_5%_0402

1
2

C480

5
6

8

U616-A

1

OUT

ON_LM393DR2G_SOP_8P

4

Q628

2

Q1

3
4

0.1uF_25v_0603

9

10

Q2

5
6

8

7

1 2

PCMB063T_100MS

1

R363
10K_5%_0402

2

C482

56pF_50v_0402

C481

1

1500pF_50v_0402

2

8

U616-B

+

7

OUT

-

ON_LM393DR2G_SOP_8P

4

6-

BATTDRV#

1

4.7uF_25v_0805

1

2

C874

2

L18

C865

1
2

4.7uF_25v_0805

CHANGE by

C884

1
2

0.1uF_50v_0603

C873

1

4.7uF_25v_0805

2

C866

1
2

4.7uF_25v_0805

CHARGE_GND

Wang, Alan

For DC JACK LED

AC_LED

ADP_PRES

+VBATR

5-,7-,8-,9-,11-,13-,30-,36-

C871

1
2

4.7uF_25v_0805

C872

R803

1 2

0.01_1%_1206

Kevin sense

C474

1 2

0.1uF_25v_0603

C475

1
2

0.1uF_25v_0603

C473

1
2

0.1uF_25v_0603

CHARGE_GND

31-Jul-2008

R829 330_5%_0402

1 2

5-

5-,6-,39-

SSM3K7002F

C860

1
2

0.01uF_50v_0603

1
2

C862

4.7uF_25v_0805

C472

1
2

0.1uF_25v_0603

CHARGE_GND

+V5AL

5-,7-,49-

3

2

S

D

Q634

AO3409

G

1

R828

1 2

470K_5%_0402

Q631

3

D

G

1

S

2

+VBDC

6-,36-

Q627

8

1

S

D

2

7

3

6
5

4

G

FDS6675BZ

C863

1
2

4.7uF_25v_0805

INVENTEC

TITLE

DIABLO 2.0

DC &BATTERY CHARGER

SIZE CODE

A3

CS

DOC. NUMBER

OFSHEET

5 61

REV

A021310A22155-0-MTR

CHGCTRL_3

ADP_PRES

+VBATT

6-

CHENKO_LL4148_2P

5-,39-

5-,39-

BATTDRV#

D607

2 1

12

D608

3

BAT54A

5-

R695

1 2

1.5M_5%_0402

+V3AL

5-,6-,7-,31-,39-,49-

1

R662
100K_5%_0402

2

Q623

S1

2

G1

D1
D2

5

G2

S2

2N7002DW

+VBDC

5-,36-

Q11

8

D

7
6
5

FDS6675BZ

Improve voltage loss

1
6

3
4

+VBATT

6-

1

S

2

1

R694

3
4

G

681K_1%_0402

2

1

R693

4.7K_5%_0402

2

BATT_DATA

BATT_CLK

BATT_TS

5-,39-

5-,39-

+V3AL

5-

5-,6-,7-,31-,39-,49-

1

R715

3.6K_5%_0402

2

1

3

2

CHENMKO_BAV99

D610

+V3AL

5-,6-,7-,31-,39-,49-

1

D606

2

1

R689

3.6K_5%_0402

2

Change to 100 ohm for ESD

100_5%_0402

R692

1 2

100_5%_0402

3

CHENMKO_BAV99

R690

1 2

1K_1%_0402

1

C727

2

0402_OPEN

R713

1 2

BAT_ID

5-,6-,7-,31-,39-,49-

+V3AL

R691

100K_5%_0402

C112

1

0.1uF_25v_0603

2

39-

100_5%_0402

Add R759 for ESD

1

2

R714

1 2

SYN_200275MR008G10NZL_8P

8

8

7

G

7

G2

6

G

6

G1

5

5

4

4

3

3

2

2

1

1

CN609

CHANGE by

Wang, Alan

31-Jul-2008

INVENTEC

TITLE

DIABLO 2.0

BATTERY CONN

CODE DOC. NUMBER

A3

1310A22155-0-MTRA02

CS

SHEET OF

REVSIZE

616

+VBATR

5-,8-,9-,11-,13-,30-,36-

R658
118K_1%_0402

2

1

C663

2

PAD601

3
4

POWERPAD_4A

25

5

6

TML

VFB2

ENTRIP2

7
8

VREG3
VBST2

10
11

DRVL2

SKIPSEL

EN0

14

13

TI_TPS51125_QFN_24P

R638

1

820K_1%_0402

2

+V3AL

5-,6-,7-,31-,39-,49-

1

R652
10K_5%_0402

2

Q613

3

D

1

13-,39-

KBC_PW_ON

R649

12

6.8K_1%_0402

+VBATP

7-

C638

1

L613

0402_OPEN

2

12

R622
0402_OPEN

C641

13-,30-,32-,33-,34-,36-,41-,45-,47-,49-

+V3A +V5A

4.7uF_25v_0805

PAD603

1

1
2

2

SLF7055T_4R7N5R1

C665
330uF_4v

POWERPAD_2_0610

1uF_16v_0603

C686

2N7002W

R659

10K_1%_0402

C637

1
2

4.7uF_25v_0805

1

2

1
2

G

S

2

12

51125GND

S1_D2

56
7
4

S2

Q611

FDS6900AS

D1

12
8

G1

3

G2

+V3AL

5-,6-,7-,31-,39-,49-

1

C684

4.7uF_6.3v_0805

2

Q614

S1

2

G1

D1
D2

5

G2

S2

2N7002DW

C685

0.1uF_16v_0603

1 2

R650

1 2

1
6

3
4

4.7_5%_0603

1

2

R647

1 2

0_5%_0402

R648

1

0402_OPEN

4.7uF_6.3v_0805

+VBATP

7-

1

R656

86.6K_1%_0402

2

20080620 PV change

Change R656 to 86.6K for Safty OCP (6.5A)

2VREF

5-

C682

1uF_6.3v_0402

1
2

3

4

2

1

U603

VFB1

VREF

TONSEL

GND

1
2

ENTRIP1

24

VO1VO2

23

PGOOD

229

VBST1

21

DRVH1DRVH2

20

LL1LL2

1912

DRVL1

VCLK

VIN

VREG5

18

16

17

15

C664

2.2uF_25v_0805

51125GND

+V5AL

5-,49-

C683

1
2

10uF_6.3v_0805

R654

1 2

0_5%_0603

R646

0_5%_0402

15.4K_1%_0402

10K_1%_0402

R653

R655

1 2

1 2

51125GND51125GND51125GND

+VBATP

7-

C635

1

C636

876

D

SI7326DN

8765

D

S

123

1
2

4.7uF_25v_0805

Q610

Q609
FDS6690AS

2

4.7uF_25v_0805

L615

1 2

SLF10155T_4R7N6R2

1

R637
0402_OPEN

2

C662

1
2

0402_OPEN

C680

220uF_6.3v

5

12

R645

1 2

4.7_5%_0603

C681

0.1uF_16v_0603

1 2

32-,39-

RSMRST#

G

4S123

G

4

8-,9-,10-,11-,12-,13-,29-,30-,34-,38-,39-,41-,42-,48-

PAD602

POWERPAD_2_0610

1

1

C690

2

1uF_16v_0603

2

INVENTEC

TITLE

DIABLO 2.0

SYSTEM POWER(3V/5V/12V)

CODE

CS

SHEETCHANGE by

DOC. NUMBER

7 61

SIZE

31-Jul-2008Wang, Alan

A3

REV

A021310A22155-0-MTR

OF

15-,16-,17-,18-,20-,21-,23-,24-,31-,34-,36-,37-

+VCCP

PAD2

POWERPAD_2_0610

D711

2 1

MMSZ5221B_7_F

+VBATR

5-,7-,8-,9-,11-,13-,30-,36-

C466

1
2

4.7uF_25v_0805

L16

1 2

PCMC063T_1R5MN

1

C462

2

220uF_2v_15mR_Panasonic

C467

1
2

4.7uF_25v_0805

Q20

SI7326DN

8 7 6 5

D

8D7 6 5

S

1 2

G

41S2 3

G

3

4

12.1K_1%_0603

VCCP_PG

VGA_PG

0.1uF_10v_0402_OPEN

0.1uF_16v_0603

Q19
FDS6676AS

R791

1

C856

1 2

C857

2

14-

9-

R790
0_5%_0402

1

R792

1 2

30K_1%_0402

1

2

R788

1 2

2

4.7_5%_0603

51124GND

R789

2

1

0_5%_0402_OPEN

7

PGOOD2

8

EN2

VBST2

10

DRVH2

TI_TPS51124RGER_QFN_24P

11

LL2

12

DRVL2

R793

1 2

0_5%_0603

5

6

VO2

VFB2

TRIP2

PGND2

14

13

1

R798

6.34K_1%_0402

2

51124GND

4

TONSEL

V5FILT

15

2

3

GND

VFB1

TRIP1

V5IN

17

16

1

R800

5.62K_1%_0402

2

R794

2

1

30K_1%_0402

51124GND

U614

1

VO1

25

GND

24

PGOOD1

23

EN1

R797

1 2

229

VBST1

4.7_5%_0603

21

DRVH1

20

LL1

19

DRVL1

PGND1

7-,9-,10-,11-,12-,13-,29-,30-,34-,38-,39-,41-,42-,48-

18

10_5%_0603

C861

1
2

1uF_10v_0603

R795

1

43.2K_1%_0402

R796

1 2

0_5%_0402

C858

1
2

0.1uF_10v_0402_OPEN

14-

V1.8_PG

C859

1 2

0.1uF_16v_0603

+V5A

R799

1 2

C864

1
2

4.7uF_6.3v_0805

2

12-,39-,48-

SLP_S4#_EC

65

87

D

G

4 1S23

765

G

4

3

4.7uF_25v_0805

Q23

SI7326DN

8

D

1S2

Q21

FDS6676AS

+VBATR

5-,7-,8-,9-,11-,13-,30-,36-

C477

1
2

330uF_2v_9mR_Panasonic

C476

1
2

4.7uF_25v_0805

L17

2

1

PCMC063T_1R0MN

C463

POWERPAD_2_0610

1

2

9-,10-,12-,13-,20-,23-,24-,26-,27-,36-

+V1.8

PAD3

D712

2 1

MMSZ5221B_7_F

INVENTEC

TITLE

DIABLO 2.0

SYSTEM POWER(+V1.8/+V1.25S)

SIZE

CODE

A3

CHANGE by SHEET

Wang, Alan

11-Aug-2008

CS

DOC. NUMBER

OF

8 61

REV

A021310A22155-0-MTR

+V1.1S

54-,55-,56-,57-

C705

1
2

1uF_10v_0603

Q617

2N7002W

1

12

+V3S

G

R125

1 2

10K_5%_0402

3

D

S

2

9-,10-,11-,13-,14-,15-,16-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,36-,37-,39-,40-,41-,43-,44-,47-,48-,49-,52-,53-,54-,56-,57-,58-

R126

1 2

VGA_ALTV0

20080611 Add RC for GPU Switch Voltage

57-

0_5%_0402

C926

1000pF_50v_0402_OPEN

C706

1
2

22uF_6.3v_0805

R675

1 2

0_5%_0603

V1.5S_PG

1

R679

10.7K_1%_0402

2

20080617 change to 11K for 1.1V

1

R680
20K_1%_0402

2

VGAP_AGND

10-

1

R678
130K_1%_0402

2

R128

1 2

0_5%_0402

10uF_6.3v_0805

C707

1
2

0402_OPEN

C100

1
2

0.022uF_16v_0402_OPEN

C688

2

1

U605

2

NC

3

VLDO

4

VLDOFB

5

GND

6

ODOFF

7

OD

8

COMP

9

VOSW

21

TML-PAD

R682

1 2

0_5%_0402

+V1.8

8-,10-,12-,13-,20-,23-,24-,26-,27-,36-

20

1

VBST

19

DRVH

VLDOIN

VSWFB

10

18

LL

17

DRVL

16

PGND

15

CS

14

V5IN

13

PGOOD

12

ENSW

ENLDO

TI_TPS51511_RHL_20P

11

R685

1 2

0_5%_0402

C99

0.1uF_16v_0402

1 2

R651

1 2

0_5%_0603

1 2

R686

1 2

100K_1%_0402

C689

0.1uF_16v_0603

1 2

7-,8-,10-,11-,12-,13-,29-,30-,34-,38-,39-,41-,42-,48-

7.87K_1%_0402

R127

8-

VGA_PG

+V5A

C709

1
2

4.7uF_6.3v_0603

Q619

SI7326DN

G

5

G

412

876

3

8D7654

Q612
FDS6676AS

S

123

+VBATR

5-,7-,8-,11-,13-,30-,36-

1

C712

2

1

4.7uF_25v_0805

4.7uF_25v_0805

2

PCMC063T_1R0MN

1

R687
0402_OPEN

2

C710

1

0402_OPEN

2

C711

9-,10-,11-,13-,14-,15-,16-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,36-,37-,39-,40-,41-,43-,44-,47-,48-,49-,52-,53-,54-,56-,57-,58-

+V3S

L621

1 2

1
2

1000pF_50v_0402

C708

30K_1%_0402

R684

VGAP_AGND

R676
12K_1%_0402

1

R683

13.7K_1%_0402

2

1

2

1

2

1
2

C703

1000pF_50v_0402

VGAP_AGND

1

S1

6

D1

3

D2

4

S2

2N7002DW

1

2

Q618

2

G1

5

G2

20080611 Fine tune RC for Switch Voltage

R681
10K_5%_0402

1 2

47K_1%_0402

1
2

1000pF_50v_0402

VGAP_AGND

C704

330uF_2v_9mR_Panasonic

R677

57-

VGA_ALTV1

PAD604

POWERPAD_4A

1

C726

12

+VGAVCC

54-

2
3
4

1

C739

2

10uF_6.3v_0805

CHANGE by

VGA_ALTV1

(GPIO6)

0

1

1

Wang, Alan

VGA_ALTV0

(GOIP5)

0

1

+VGAVCC

0.9

1.09

1.17

31-Jul-2008

INVENTEC

TITLE

DIABLO 2.0

GRAPHIC POWER (+VGFX_CORE)

SIZE0CODE

A3

CS

SHEET

DOC. NUMBER

OF

9 61

REV

A021310A22155-0-MTR

7-,8-,9-,11-,12-,13-,29-,30-,34-,38-,39-,41-,42-,48-

+V5A

9-,11-,13-,14-,15-,16-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,36-,37-,39-,40-,41-,43-,44-,47-,48-,49-,52-,53-,54-,56-,57-,58-

+V3S

R279

100K_5%_0402

39-

V1.5S_EN

2

0_5%_0402

R280

1

1

C399

2

0.022uF_16v_0402_OPEN

1

2

8-,9-,12-,13-,20-,23-,24-,26-,27-,36-

+V1.8

C398

1
2

1uF_10v_0603

U15

6

VCNTL

7

POK

8 2

EN

VIN
9

5

VIN

3

VOUT

4

VOUT

FB

GND

1

ANPEC_APL5913_KAC_TRL_SOP_8P

9-

V1.5S_PG

C400

1
2

22uF_6.3v_0805

C401

1
2

22uF_6.3v_0805

C402

1
2

1uF_10v_0603

1
2

39pF_50v_0402

C403

PAD1

POWERPAD_2_0610

1

R281

27.4K_1%_0402

2

1

R282
30K_1%_0402

2

+V1.5S

18-,24-,34-,47-,48-

INVENTEC

TITLE

DIABLO 2.0

SYSTEM POWER(+VCCP/+V1.5S)

CODE

SIZE

A3

CHANGE by SHEET

Wang, Alan

31-Jul-2008

CS

DOC. NUMBER

1310A22155-0-MTRA02

REV

OF

6110

H_VID6
H_VID5
H_VID4
H_VID3
H_VID2
H_VID1
H_VID0

17-

PSI#

+V3S

R42

C26

1
2

VCOREGND

17-,20-,31-

20-,32-

1

2

R44

0_5%_0402

1 2

0_5%_0402R31

1 2

12

R29

1 2

68K_1%_0603

C29

680pF_50v_0402

CSREF

18-

VCCSENSE

18-

VSSSENSE

R45499_1%_0402

1 2

Tcpudelay = 5ms

VCOREGND

4700pF_25v_0402

1

C30

18pF_50v_0402

2

1
2

+V5S

13-,19-,29-,32-,34-,37-,40-,41-,48-,49-,52-

11-

1000pF_50v_0402

C32

12

C34

1

EN

2

PWRGD

3

PGDELAY

4

CLKEN

5

FBRTN

6

FB

7

COMP

8

SS

9

ST

10

VARFREQ

11

VRTT

12

TTSEN

VCOREGND

1
2

VCOREGND

H_DPRSTP#

9-,10-,13-,14-,15-,16-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,36-,37-,39-,40-,41-,43-,44-,47-,48-,49-,52-,53-,54-,56-,57-,58-

VCORE_ON
PM_PWROK

VR_PWRGD_CK505#

330pF_50v_0402

C31

1

1000pF_50v_0402

VCOREGND

PM_DPRSLPVR

39­20-,32-,39-

1 2

R43

32-

12

C27

220pF_25v_0402

1 2

R30

1.65K_1%_0402

0.012uF_16v_0402

2

R47

1 2

0_5%_0603

2.2K_5%_0402

0_5%_0402

C28

18­18­18­18­18­18­18-

49

48

TML

U3

ADI_ADP3208_LFCSP_48P

13

R28

113K_1%_0603

47

DPRSLP

DPRSTP

PMON

PMONFS

14

2

1

45

46

PSI

VID0

LLINE

CLIM

16

15

41

44

43

VID242VID3

VID1

CSCOMP

CSFEF18CSSUM

20

17

19

1

C11

1000pF_50v_0402

2

2

R46

100K_5%_0402

1

40

39

37

38

VCC

VID4

VID5

VID6

DRVH1

PVCC1

DRVL1
PGND1
PGND2

DRVL2

PVCC2

DRVH2

VRPM

GND

RAMP22RPM23RT SP

21

24

215K_1%_0402

1 2

2

R33
150K_1%_0402

1

0.01uF_16v_0402
R18

274K_1%_0402

2

10_5%_0603

1
2

2.2uF_6.3v_0603

VCOREGND

36

BST1

35
34

SW1

33
32
31
30
29
28
27

SW2

26
25

BST2

R34

12

C13

VCOREGND

1

1

C12

2

1000pF_50v_0402

VCOREGND

R35

1 2

174K_1%_0603

R20

1 2

174K_1%_0603

R17

1 2

220K_1%_0402

1

C33

2

330pF_50v_0402

+V5A

7-,8-,9-,10-,12-,13-,29-,30-,34-,38-,39-,41-,42-,48-

2

R48

C36

1

1
2

2.2uF_6.3v_0603

C45

R50

1 2

4.7_5%_0603
1uF_16v_0603

R36

1 2

4.7_5%_0603

+VBATR

R19

1 2

100_5%_0402

2

R32

76.8K_1%_0402

1

D3

3

BAT54A

2

1

C38

1 2

1
2

1 2

C37

1uF_16v_0603

5-,7-,8-,9-,11-,13-,30-,36-

1

R605
220K_5%_0603

2

NTC thermistor, place near L16

C35

1uF_10v_0402

1

2

C615

100uF_25v

1
2

4.7uF_25v_0805

+VBATR

5-,7-,8-,9-,11-,13-,30-,36-

C18

C20

1
2

4.7uF_25v_0805

C16

1
2

4.7uF_25v_0805

C19

1
2

4.7uF_25v_0805

X 3

C14

1
2

4.7uF_25v_0805

Q1

FDS6676AS

C21

1
2

4.7uF_25v_0805

Q2
FDS6676AS

C17

1
2

4.7uF_25v_0805

6

5

87

D

G

4S123

8D765

G

S

4

123

CHANGE by

56789

Q5

SI7686DP_T1_E3

1

4G32

Q606

765

8

FDS6676AS

D

G

4 1S23

89

567

4.7_5%_0805

C15

1000pF_50v_0402

Q6

SI7686DP_T1_E3

R37

4G321

765

8

D

G

Q3
FDS6676AS

S

4

123

R22

4.7_5%_0805

C22

1000pF_50v_0402

Wang, Alan 31-Jul-2008

ETQP4LR36WFC_PANASONIC

1

2

1
2

1

2

1
2

L607

12

2

R21
10_1%_0402

1

11-

CSREF

2

R38
10_1%_0402

1

L608

12

ETQP4LR36WFC_PANASONIC

INVENTEC

TITLE

DIABLO 2.0

CPU POWER(VCC_CORE)

SIZE

A3

DOC. NUMBER

CODE REV

1310A22155-0-MTRA02

CS

SHEET

+VCC_CORE

OF

6111

18-

SLP_S4#_EC

SLP_S3#_EC

8-,9-,10-,13-,20-,23-,24-,26-,27-,36-

8-,39-,48-

39-,41-,48-

+V1.8

C846

1
2

4.7uF_6.3v_0805

+V5A

7-,8-,9-,10-,11-,13-,29-,30-,34-,38-,39-,41-,42-,48-

U613

GMT_G2997F6U_MSOP10_10P

TML11VDDQSNS

10 2

VIN

VLDOIN

9

VTT

S5
GND8PGND

7

VTTSNS

S3

6

C847
1uF_10v_0603

1
2

VTTREF

VREF_R

R787

1 2

0_5%_0603

C855

0.1uF_16v_0402

1
2

NOTE: DDR2 REGULATOR

1

3
4
5

20-,26-,27-

M_VREF

+V0.9S

1
2

28-

C854
10uF_6.3v_0805

1

C853

2

10uF_6.3v_0805

CHANGE by

Wang, Alan 31-Jul-2008

INVENTEC

TITLE

DIABLO 2.0

DDR TERMINATION VOLTAGE

SIZE

A3

DOC. NUMBERCODE

1310A22155-0-MTRA02

CS

SHEET

OF

REV

6112

V3_5S_EN#

13-,39-

7-,30-,32-,33-,34-,36-,41-,45-,47-,49-

+VBATR_S

R657

200K_1%_0402

Q622

3

D

1

G

S

2

13-

12

SSM3K7002F

+V3A

Q615

6

D

S

5
2

1 3

G

FDC655BN

C691

0.1uF_25v_0603

R660
47_5%_0805

SSM3K7002F

+V3S

9-,10-,11-,14-,15-,16-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,36-,37-,39-,40-,41-,43-,44-,47-,48-,49-,52-,53-,54-,56-,57-,58-

+V5A

+VBATR_S

4

Q616

1

7-,8-,9-,10-,11-,12-,29-,30-,34-,38-,39-,41-,42-,48-

12

V3_5S_EN#

13-,39-

1

2

3

D

G

S

2

R350

100K_1%_0603

Q17

3

D

1

G

S

SSM3K7002F

2

13-

12

11-,19-,29-,32-,34-,37-,40-,41-,48-,49-,52-

6
5

2
1

FDC655BN

+V5S

Q18

4

D

S

3

G

C464

12

0.1uF_25v_0603

1

R349
100_5%_0805

2

Q16

3

D

1

G

S

2

SSM3K7002F

Added for VGA

V1.8S_EN#

8-,9-,10-,12-,20-,23-,24-,26-,27-,36-

+V1.8

Q12

8

+VBATR_S

13-

12

R278

100K_1%_0402

Q14

3

D

G

39-

1

S

2

SSM3K7002F

7
6

5 4

SI4800BDY : 6015A0004301

0.1uF_25v_0603

D

G

SI4800DY

C397

SSM3K7002F

+V1.8S

36-,55-,56-,59-,60-

1

S

2
3

C808

12

100uF_6.3v

12

1

R277
100_5%_0805

2

Q13

3

D

1

G

S

2

+VBATR

5-,7-,8-,9-,11-,30-,36- 13-

3

2

D

S

Q621

G

AO3409

1

R688

1 2

470K_1%_0402

Q620

3

KBC_PW_ON

7-,39-

1

SSM3K7002F

D

G

S

2

2

3

1

D605

CHENMKO_BAV99

+VBATR_S

INVENTEC

TITLE

DIABLO 2.0

POWER(SLEEP)

SIZE CODE

CHANGE by SHEET OF

31-Jul-2008Wang, Alan

A3

CS

DOC. NUMBER

13 61

REV

A021310A22155-0-MTR

VCCP_PG

V1.8_PG

8-

8-

R775

1 2

100_5%_0402

R774

1 2

100_5%_0402

+V3S

9-,10-,11-,13-,15-,16-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,36-,37-,39-,40-,41-,43-,44-,47-,48-,49-,52-,53-,54-,56-,57-,58-

R776

1 2

10K_5%_0402

39-

1

C923

1000pF_50v_0402

2

VCCP_R_PG

CHANGE by

INVENTEC

TITLE

DIABLO 2.0

POWER(SEQUENCE)

SIZE

CODE

A3

CS

31-Jul-2008Wang, Alan

SHEET

14 61

REVDOC. NUMBER

A021310A22155-0-MTR

OF

+VCCP

8-,15-,16-,17-,18-,20-,21-,23-,24-,31-,34-,36-,37-

I = 100mA

C63

R75

1 2

33_1%_0402

FSB CLOCK
FREQUENCY

1067

10K_5%_0402_OPEN

10K_5%_0402

R73

1 2

12

10K_5%_0402

CLK-REF

32-

667
800

CPU_BSEL1

CPU_BSEL2

CLK_R3S_REF

CLK_R3S_REF

FSA

1
0
0

FSB

17-,20­17-,20­15-

0402_OPEN

15-

FSC

1

0
01
0

0

*CLKREQ# pin controls SRC Table.

BIT 6 = 0

BIT 4 = 0

SRC1

BIT 7 = 0 CR#_A disabled
BIT 7 = 1 CR#_A enabled

BIT 5 = 0 CR#_B disabled
BIT 7 = 1 CR#_B enabled

CR 05h [5]

CR#_A

SRC0

CR 05h [5]

CR#_B

L3
BLM18AG471SN1D

1

2

1

10uF_6.3v_0805

2

+VCCP

8-,15-,16-,17-,18-,20-,21-,23-,24-,31-,34-,36-,37-

1

R636

2

2

R74

1

10K_5%_0402_OPEN

CLK_R3S_ICH14

HOST CLOCK
FREQUENCY

166
200
266

BIT 6 = 1

SRC2

BIT 4 = 1

SRC4

Layout note: All decoupling 0.1uF disperse closed to pin

C659

C75

C660

1

0.1uF_16v_0402

2

1
2

CPU_BSEL0

0.1uF_16v_0402

C76

1

0.1uF_16v_0402

2

8-,15-,16-,17-,18-,20-,21-,23-,24-,31-,34-,36-,37-

17-,20-

22pF_50v_0402_OPEN

X601

1 2

14.318MHz

30PPM

32-

53-

+V3S CLK_PEG_MCH#

32­26-,27-,32-,37­26-,27-,32-,37-

1

C658

2

22pF_50v_0402

CLK_R3S_ICH48

CLK_R3S_CR48 CLK_PCIE_MINI#

9-,10-,11-,13-,14-,15-,16-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,36-,37-,39-,40-,41-,43-,44-,47-,48-,49-,52-,53-,54-,56-,57-,58-

1

R635

2

CLK_PWRGD

ICH_3S_SMCLK

ICH_3S_SMDATA

1

C657

22pF_50v_0402

2

Please place close to CLKGEN within 500mils

CR 05h [5]

CR#_C

BIT 3 = 0 CR#_C disabled
BIT 3 = 1 CR#_C enabled

BIT 2 = 0

SRC0

BIT 0 = 0

BIT 1 = 0 CR#_D disabled
BIT 1 = 1 CR#_D enabled

CR 05h [5]

CR#_D

SRC1

C62

1

1

0.1uF_16v_0402

2

C60

0.1uF_16v_0402

2

10K_5%_0402_OPEN

R71

1 2

2.2K_5%_0402

12

R70

1 2

1 2
1

R613
R615

1 2
1

R616

CLK_R3S_MINICARD

CLKREQ_SATA#

CLKREQ_MINI_WLAN#

CLKREQ_MCH#

BIT 2 = 1

SRC2

BIT 0 = 1

SRC4

C74

1
2

+VCCP

R68

R72

10K_5%_0402

22_5%_0402R69

1

22_5%_0402

10K_5%_0402R614

2

10K_5%_0402_OPEN
10K_5%_0402_OPEN

2

10K_5%_0402

C676

0.1uF_16v_0402

1

2

1

2

2

47-

CLK-PCI

15-,32­15-,47­15-,20-

I = 300mA

CLK_3S_ICH48

33_1%_0402

R633

1 2

1

1 2
1 2

CR#_E

CR#_F

CR#_G

CR#_H

+V3S

9-,10-,11-,13-,14-,15-,16-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,36-,37-,39-,40-,41-,43-,44-,47-,48-,49-,52-,53-,54-,56-,57-,58-

1

L614
BLM18AG471SN1D

2

C679

1
2

10uF_6.3v_0805

C61

1
2

0.1uF_16v_0402

C661

1
2

0.1uF_16v_0402

C678

1
2

0.1uF_16v_0402

C656

1
2

0.1uF_16v_0402

C677

1
2

0.1uF_16v_0402

1
2

0.1uF_16v_0402

Layout note: All decoupling 0.1uF disperse closed to pin

+V3S

9-,10-,11-,13-,14-,15-,16-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,36-,37-,39-,40-,41-,43-,44-,47-,48-,49-,52-,53-,54-,56-,57-,58-

1

1

2

CLK_3S_KBPCI
CLK_3S_ICHPCI

ITP_EN =0
SRC8/SRC8#

ITP_EN =1
ITP/ITP#

R643

10K_5%_0402_OPEN

2

33_1%_0402
33_1%_0402 R630

R76
R84

CLK_3S_MINICARD

R634

2

R642

R640

475_1%_0402

475_1%_0402

475_1%_0402

U602

33

VDD_SRC_IO

43

VDD_SRC_IO

52

VDD_SRC_IO

19

VDD_IO

46

VDD_SRC

4

VDD_REF

27

VDD_PLL3_IO

56

VDD_CPU_IO

16

VDD_48

9

VDD_PCI

62

VDD_CPU

23

VDD_PLL3

17

FSLA_USB48

64

FSLB_TEST_MODE

5

FSLC_TEST_SEL_RE

11

TME_PCI-2

12

SRC-5_EN_PCI_3

63

CK_PWRGD_PD#

7

SCLK

6

SDATA

3

X_IN

2

X_OUT

15

GND_PCI

18

GND_48

22

GND_IO

26

GND_PLL3

36

GND_SRC

49

GND_SRC

59

GND_CPU

1

GND_REF

30

GND_SRC

55

RESET#

10

CR#_B_PCI-1

8

CR#_A_PCI-0

40

CR#_H_SRC-11

39

CR#_G_SRC-11#

65

TML-PAD

CR 06h [6]

PCI_STOP#_SRC-5

CPU_STOP#_SRC-5#

CPU-1#

CPU-0#

SRC-8#_CPU_ITP#

SRC-8_CPU_ITP

SRC-10

SRC-10#

SRC-9#

SRC-7_CR#_F

SRC-7#_CR#_E

SRC-6#

27M_SEL_PCI-4

ITP_EN_PCI-5

SRC-4#

SRC-1_SE1

SRC-1#_SE2

SRC-2_SATA

SRC-2#_SATA#

SRC-0_DOT96

SRC-0#_DOT96#

CR#_C_SRC-3

CR#_D_SRC-3#

REA_RTM875N_606_QFN_64P

P/N: 6019B0491702

BIT 7 = 0 CR#_E disabled
BIT 7 = 1 CR#_E enabled

R644

10K_5%_0402_OPEN

45
44

58

CPU-1

57

61

CPU-0

60

53
54

41
42

37

SRC-9

38

51
50

48

SRC-6

47

13
14

34

SRC-4

35

24
25

28
29

20
21

31
32

9-,10-,11-,13-,14-,15-,16-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,36-,37-,39-,40-,41-,43-,44-,47-,48-,49-,52-,53-,54-,56-,57-,58-

SRC6

CR 06h [6]

SRC8

CR 06h [6]

BIT 6 = 0 CR#_F disabled
BIT 6 = 1 CR#_F enabled

BIT 5 = 0 CR#_G disabled
BIT 5 = 1 CR#_G enabled

CLKREQ_MCH#

CLKREQ_SATA#

CLKREQ_MINI_WLAN#

CLKREQ_ECARD#

SRC9

CR 06h [6]

BIT 4 = 0 CR#_H disabled
BIT 4 = 1 CR#_H enabled

SRC10

CHANGE by

C655

1 2

R632

1 2

33_1%_0402

1 2
1 2

33_1%_0402

475_1%_0402

R83

2

1

R629

2

0402_OPEN

R628

2

10K_5%_0402_OPEN

Wang, Alan

15-,20­15-,32­15-,47­15-,48-

1

1

R631

1 2

10K_5%_0402

R612

2

0402_OPEN

1 2

R639
R208 10K_5%_04021 2
R641 10K_5%_04021 2

1 2

R82

32-

PCISTOP#_3

32-

CPUSTOP#_3

21-

CLK_MCHBCLK

21-

CLK_MCHBCLK#

16-

CLK_CPUBCLK

16-

CLK_CPUBCLK#

47-

CLK_PCIE_MINI

47-

20-

CLK_PEG_MCH

20-

44-

CLK_PCIE_LAN

44-

CLK_PCIE_LAN#

54-

CLK_PEG_REF

54-

CLK_PEG_REF#

39-

CLK_R3S_KBPCI

33-

CLK_R3S_ICHPCI

48-

CLK_PCIE_NEWCARD

48-

CLK_PCIE_NEWCARD#

57-

CLK_27MNONSSC

57-

CLK_27MSSC

31-

CLK_SATA1

31-

CLK_SATA1#

32-

CLK_PCIE_ICH

32-

CLK_PCIE_ICH#

15-,48-

CLKREQ_ECARD#

9-,10-,11-,13-,14-,15-,16-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,36-,37-,39-,40-,41-,43-,44-,47-,48-,49-,52-,53-,54-,56-,57-,58-

+V3S+V3S

27_Selet =0

PIN24&25=SRC-1,PIN20&21=DOT96

1

27_Selet =1

PIN24&25=27MHZ&27M_SS,PIN20&21=SRC-0

+V3S

9-,10-,11-,13-,14-,15-,16-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,36-,37-,39-,40-,41-,43-,44-,47-,48-,49-,52-,53-,54-,56-,57-,58-

10K_5%_0402

10K_5%_0402

INVENTEC

TITLE

DIABLO 2.0

CLOCK_GENERATOR

8-Aug-2008

SIZE

A3

DOC. NUMBER

CODE

1310A22155-0-MTRA02

CS

SHEET

OF

REV

6115

H_A#(35:3)

H_ADSTB#1

H_STPCLK#

H_A20M#

H_FERR#

H_IGNNE#

H_INTR

H_NMI

H_SMI#

21-

H_A#(3)
H_A#(4)
H_A#(5)
H_A#(6)
H_A#(7)
H_A#(8)
H_A#(9)
H_A#(10)
H_A#(11)
H_A#(12)
H_A#(13)
H_A#(14)
H_A#(15)
H_A#(16)

H_REQ#(4:0) H_RS#(2:0)

H_A#(17)
H_A#(18)
H_A#(19)
H_A#(20)
H_A#(21)
H_A#(22)
H_A#(23)
H_A#(24)
H_A#(25)
H_A#(26)
H_A#(27)
H_A#(28)
H_A#(29)
H_A#(30)
H_A#(31)
H_A#(32)
H_A#(33)
H_A#(34)
H_A#(35)

21-

31­31­31-

16-,31­31­31­31-

21-

H_REQ#(0)
H_REQ#(1)
H_REQ#(2)
H_REQ#(3)
H_REQ#(4)

H_ADSTB#0

21-

CN607-1

J4

A3#

L5

A4#

L4

A5#

K5

A6#

M3

A7#

N2

A8#

J1

A9#

N3

A10#

P5

A11#

P2

A12#

L2

A13#

P4

A14#

P1

A15#

R1

A16#

M1

ADSTB0#

K3

REQ0#

H2

REQ1#

K2

REQ2#

J3

REQ3#

L1

REQ4#

Y2

A17#

U5

A18#

R3

A19#

W6

A20#

U4

A21#

Y5

A22#

U1

A23#

R4

A24#

T5

A25#

T3

A26#

W2

A27#

W5

A28#

Y4

A29#

U2

A30#

V4

A31#

W3

A32#

AA4

A33#

AB2

A34#

AA3

A35#

V1

ADSTB1#

A6

A20M#

A5

FERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

M4

RSVD01

N5

RSVD02

T2

RSVD03

V3

RSVD04

B2

RSVD05

C3

RSVD06

D2

RSVD07

D22

RSVD08

D3

RSVD09

F6

RSVD010

FOX_PZ4782K_274M_41_478P

GMCH

CPU

ADS#
BNR#

BPRI#

DEFER#

DRDY#
DBSY#

BR0#

IERR#

ADDR GROUP 0

INIT#

CONTROL

LOCK#

RESET#

RS0#
RS1#
RS2#

TRDY#

HIT#

HITM#

BPM0#
BPM1#
BPM2#
BPM3#
PRDY#
PREQ#

TCK

TDI

ADDR GROUP 1

TDO
TMS

XDP/ITP SIGNALS

TRST#

DBR#

THERMAL

PROCHOT#

THERMDA
THERMDC

THERMTRIP#

ICH

H CLK

BCLK0
BCLK1

RESERVED

H1
E2
G5

H5
F21
E1

F1

D20
B3

H4

C1
F3
F4
G3
G2

G6
E4

AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20

8-,15-,16-,17-,18-,20-,21-,23-,24-,31-,34-,36-,37-

Not use PROCHOT#

D21
A24
B25

C7

PM_THRMTRIP# SHOULD CONNECT TO ICH9 AND GMCH WITHOUT T-ING

A22
A21

ICH8

2

56_5%_0402

1

R80

+VCCP

+VCCP

10mils/10mils

21-

H_ADS#

21-

H_BNR#

21-

H_BPRI#

21-

H_DEFER#

21-

H_DRDY#

21-

H_DBSY#

21-

H_BREQ#0

31-

H_INIT#

21-

H_LOCK#

21-

H_CPURST#

21-

H_TRDY#

21-

H_HIT#

21-

H_HITM#

16-

H_BPM5_PREQ#

16-

H_TCK

16-

TDI_FLEX

16-

H_TDO

16-

H_TMS

9-,10-,11-,13-,14-,15-,19-,20-,24-,26-,27-,29-,30-,31-,32-,33-,34-,36-,37-,39-,40-,41-,43-,44-,47-,48-,49-,52-,53-,54-,56-,57-,58-

R89 1K_5%_0402_OPEN

1 2

19-

H_THERMDA

19-

H_THERMDC

20-,31-

PM_THRMTRIP#

15-

CLK_CPUBCLK

15-

CLK_CPUBCLK#

+VCCP

8-,15-,16-,17-,18-,20-,21-,23-,24-,31-,34-,36-,37-

150_5%_0402_OPEN

56_5%_0402_OPEN

R90

1 2

51_5%_

0402_OPEN

R57

1 2

0402_OPEN

R65

1 2

54.9_1%_0402
R64

1 2

54.9_1%_0402

R195

1 2

R58

1 2

+VCCP

H_RS#(0)
H_RS#(1)
H_RS#(2)

+VCCP

8-,15-,16-,17-,18-,20-,21-,23-,24-,31-,34-,36-,37-

1

R81
56_5%_0402

2

8-,15-,16-,17-,18-,20-,21-,23-,24-,31-,34-,36-,37-

21-

+V3S

R1119 Value should be 51ohm

16-

H_BPM5_PREQ#

16-

TDI_FLEX

16-

H_TMS

16-,31-

H_STPCLK#

16-

H_TDO

1

R54

54.9_1%_0603

2

CLOSED TO CPU

51 ohm +/-1% pull-up to +VCCP
(VCCP) if ITP is implemented

Close to CPU

H_TRST#

PM_THRMTRIP# should be T at CPU

CHANGE by

R53

2

1

54.9_1%_0402

Wang, Alan

16-

H_TCK

INVENTEC

TITLE

DIABLO 2.0

PENRYN-1

CODE

31-Jul-2008

SIZE

A3

CS

SHEET

DOC. NUMBER

OF

16 61

REV

A021310A22155-0-MTR

H_D#(63:0)

H_DSTBN#0
H_DSTBP#0

H_DINV#0

H_D#(63:0)

+VCCP

8-,15-,16-,17-,18-,20-,21-,23-,24-,31-,34-,36-,37-

1

R49
1K_1%_0402

2

1

2

R51
2K_1%_0402

GTLREF

Layout note: Zo=55 ohm,

0.5" max for GTLREF.

21­21­21-

17-,21-

H_DSTBN#1
H_DSTBP#1

H_DINV#1

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

CN607-2

H_D#(0)
H_D#(1)
H_D#(2)
H_D#(3)
H_D#(4)
H_D#(5)
H_D#(6)
H_D#(7)
H_D#(8)
H_D#(9)
H_D#(10)
H_D#(11)
H_D#(12)
H_D#(13)
H_D#(14)
H_D#(15)

H_D#(16)
H_D#(17)
H_D#(18)
H_D#(19)
H_D#(20)
H_D#(21)
H_D#(22)
H_D#(23)
H_D#(24)
H_D#(25)
H_D#(26)
H_D#(27)
H_D#(28)
H_D#(29)
H_D#(30)
H_D#(31)

21­21­21-

15-,20-

15-,20-

1

R87
0402_OPEN

2

C81

1

R88
0402_OPEN

2

0.1uF_16v_0402_OPEN

C46

1

1

2

2

0.1uF_16v_0402_OPEN

Place the capacitance close to the TEST3,TEST5 pin.
Make sure TEST3,TEST5 routing is reference
to GND and away from other noisy signals.

E22

D0#

F24

D1#

E26

D2#

G22

D3#

F23

D4#

G25

D5#

E25

D6#

E23

D7#

K24

D8#

G24

DATA GRP 0

D9#

J24

D10#

J23

D11#

H22

D12#

F26

D13#

K22

D14#

H23

D15#

J26

DSTBN0#

H26

DSTBP0#

H25

DINV0#

N22

D16#

K25

D17#

P26

D18#

R23

D19#

L23

D20#

M24

D21#

L22

D22#

M23

D23#

P25

D24#

P23

D25#

P22

DATA GRP 1

D26#

T24

D27#

R24

D28#

L25

D29#

T25

D30#

N25

D31#

L26

DSTBN1#

M26

DSTBP1#

N24

DINV1#

AD26

GTLREF

C23

TEST1

D25

TEST2

C24

TEST3

MISC

AF26

TEST4

AF1

TEST5

A26

TEST6

B22

BSEL0

B23

BSEL1

C21

BSEL2

FOX_PZ4782K_274M_41_478P

D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#

DATA GRP 2DATA GRP 3

D41#
D42#
D43#
D44#
D45#
D46#
D47#

DSTBN2#

DSTBP2#

DINV2#

D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

DSTBN3#

DSTBP3#

DINV3#

COMP0
COMP1
COMP2
COMP3

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

R26
U26
AA1
Y1

E5
B5
D24
D6
D7
AE6

1

R627
0402_OPEN

2

11-,20-,31-

H_D#(32)
H_D#(33)
H_D#(34)
H_D#(35)
H_D#(36)
H_D#(37)
H_D#(38)
H_D#(39)
H_D#(40)
H_D#(41)
H_D#(42)
H_D#(43)
H_D#(44)
H_D#(45)
H_D#(46)
H_D#(47)

H_D#(48)
H_D#(49)
H_D#(50)
H_D#(51)
H_D#(52)
H_D#(53)
H_D#(54)
H_D#(55)
H_D#(56)
H_D#(57)
H_D#(58)
H_D#(59)
H_D#(60)
H_D#(61)
H_D#(62)
H_D#(63)

1 2

27.4_1%_0402R63

1 2

R62

54.9_1%_0402

1 2

27.4_1%_0402

R66

1 2

54.9_1%_0402R67

H_DPRSTP#

CLOSED TO CPU

31­21­31­21­11-15-,20-

+VCCP

8-,15-,16-,17-,18-,20-,21-,23-,24-,31-,34-,36-,37-

21-

H_DSTBN#3

21-

H_DSTBP#3

21-

H_DINV#3

COMP0,2 : 18MILS

H_DPSLP#
H_DPWR#
H_PWRGD
H_CPUSLP#
PSI#

17-,21-17-,21-

H_D#(63:0)

21-

H_DSTBN#2

21-

H_DSTBP#2

21-

H_DINV#2

17-,21-

H_D#(63:0)

COMP0, 2 :TRACE SHOULD BE 27.4 OHM +/-15%

COMP1, 3 :TRACE SHOULD BE 55 OHM +/-15%

RESISTOR PLACED WITHIN 0.5" OF PROCESSOR PIN

CHANGE by

Wang, Alan 31-Jul-2008

INVENTEC

TITLE

DIABLO 2.0

PENYN-2

SIZE

CODE

A3

DOC. NUMBER

1310A22155-0-MTRA02

CS

SHEET

OF

REV

6117

PLACE THESE INSIDE SOCKET

CAVITY ON L8 (NORTH SIDE

SECONDARY)

PLACE THESE INSIDE SOCKET
CAVITY ON L8 (SOUTH SIDE
SECONDARY)

PLACE THESE INSIDE SOCKET
CAVITY ON L1 (NORTH SIDE
PRIMARY)

PLACE THESE INSIDE SOCKET
CAVITY ON L1 (SOUTH SIDE
PRIMARY)

SOUTH SIDE SECONDARY

NORTH SIDE SECONDARY

C670

1
2

10uF_6.3v_0805

C667

1
2

10uF_6.3v_0805

C650

1
2

10uF_6.3v_0805

C57

12

2.2uF_6.3v_0603

C668

1

1

2

2

10uF_6.3v_0805

C647

1

1

2

2

10uF_6.3v_0805

1

C627

2

330uF_2v_6mR

1

C626

2

330uF_2v_6mR

C672

1
2

10uF_6.3v_0805

C669

1

10uF_6.3v_0805

2

C646

1
2

10uF_6.3v_0805

C648

12

2.2uF_6.3v_0603

C71

1
2

10uF_6.3v_0805

C53

1
2

10uF_6.3v_0805

1

C73

2

330uF_2v_6mR

1

C58

330uF_2v_6mR

2

C65

1
2

10uF_6.3v_0805

C675

1

10uF_6.3v_0805

2

C651

1
2

10uF_6.3v_0805

C649

12

2.2uF_6.3v_0603

C70

1
2

10uF_6.3v_0805

C54

1
2

10uF_6.3v_0805

1
2

1
2

1
2

2.2uF_6.3v_0603

C69

10uF_6.3v_0805

C55

10uF_6.3v_0805

C66
10uF_6.3v_0805

C671

10uF_6.3v_0805

C52

10uF_6.3v_0805

C652

12

C67

1
2

10uF_6.3v_0805

C56

1
2

10uF_6.3v_0805

+VCC_CORE

C50

1
2

10uF_6.3v_0805

C64

1

10uF_6.3v_0805

2

C51

1
2

10uF_6.3v_0805

C654

12

2.2uF_6.3v_0603

C72

12

2.2uF_6.3v_0603

C49

12

2.2uF_6.3v_0603

11-,18-

CN607-3

A7

VCC001

A9

VCC002

A10

VCC003

A12

VCC004

A13

VCC005

A15

VCC006

A17

VCC007

A18

VCC008

A20

VCC009

B7

VCC010

B9

VCC011

B10

VCC012

B12

VCC013

B14

VCC014

B15

VCC015

B17

VCC016

B18

VCC017

B20

VCC018

C9

VCC019

C10

VCC020

C12

VCC021

C13

VCC022

C15

VCC023

C17

VCC024

C18

VCC025

D9

VCC026

D10

VCC027

D12

VCC028

D14

VCC029

D15

VCC030

D17

VCC031

D18

VCC032

E7

VCC033

E9

VCC034

E10

VCC035

E12

VCC036

E13

VCC037

E15

VCC038

E17

VCC039

E18

VCC040

E20

VCC041

F7

VCC042

F9

VCC043

F10

VCC044

F12

VCC045

F14

VCC046

F15

VCC047

F17

VCC048

F18

VCC049

F20

VCC050

AA7

VCC051

AA9

VCC052

AA10

VCC053

AA12

VCC054

AA13

VCC055

AA15

VCC056

AA17

VCC057

AA18

VCC058

AA20

VCC059

AB9

VCC060

AC10

VCC061

AB10

VCC062

AB12

VCC063

AB14

VCC064

AB15

VCC065

AB17

VCC066

AB18

VCC067

FOX_PZ4782K_274M_41_478P

VCC068
VCC069
VCC070
VCC071
VCC072
VCC073
VCC074
VCC075
VCC076
VCC077
VCC078
VCC079
VCC080
VCC081
VCC082
VCC083
VCC084
VCC085
VCC086
VCC087
VCC088
VCC089
VCC090
VCC091
VCC092
VCC093
VCC094
VCC095
VCC096
VCC097
VCC098
VCC099

VCC0100

VCCP01
VCCP02
VCCP03
VCCP04
VCCP05
VCCP06
VCCP07
VCCP08
VCCP09
VCCP10
VCCP11
VCCP12
VCCP13
VCCP14
VCCP15
VCCP16

VCCA01
VCCA02

VCCSENSE

VSSSENSE

+VCC_CORE

11-,18-

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6

VID0

AF5

VID1

AE5

VID2

AF4

VID3

AE3

VID4

AF3

VID5

AE2

VID6

AF7

AE7

I = 38000mA

I = 4500mA

+VCCP

8-,15-,16-,17-,18-,20-,21-,23-,24-,31-,34-,36-,37-

12

C68

220uF_2.5v

11-

H_VID0

11-

H_VID1

11-

H_VID2

11-

H_VID3

11-

H_VID4

11-

H_VID5

11-

H_VID6

LAYOUT NOTE:
ROUTE VCCSENSE AND VSSSENSE TRACE AT

24.7 OHM WITH 50 MIL SPACEING
PLACE PU AND PD WITHIN I INCH OF CPU

+VCC_CORE

11-,18-

1

R55
100_1%_0402

2

1

R52
100_1%_0402

2

11-

11-

+VCCP

8-,15-,16-,17-,18-,20-,21-,23-,24-,31-,34-,36-,37-

C673

1
2

0.1uF_16v_0402

VCCSENSE

VSSSENSE

C653

C674

1

1

2

2

0.1uF_16v_0402

0.1uF_16v_0402

LAYOUT NOTE:

PLACE CAP NEAR PIN B26

PLACE THESE INSIDE SOCKET
CAVITY ON L8 (NORTH SIDE
SECONDARY)

C666

1
2

0.1uF_16v_0402

C645

0.1uF_16v_0402

1
2

+V1.5S

10-,24-,34-,47-,48-

1

C80

0.01uF_16v_0402

2

C644

1
2

0.1uF_16v_0402

I = 130mA

1

C79

10uF_6.3v_0805

2

INVENTEC

TITLE

DIABLO 2.0

PENRYN-3

CHANGE by

SIZE

31-Jul-2008Wang, Alan

A3

CODE

CS

DOC. NUMBER

OFSHEET

18 61

REV

A021310A22155-0-MTR