HP DV2710P Schematics

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www.kythuatvitinh.com
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Wistron Confidential
C C
PV
2007/03/30 REV :PV-04
B B
<Variant Name>
<Variant Name>
<Variant Name>
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3 Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
Taipei Hsien 221, Taiwan, R.O.C.
NORN
NORN
NORN
NORN
NORN
NORN
A
PV
PV
151Friday, March 30, 2007
151Friday, March 30, 2007
151Friday, March 30, 2007
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Digitally signed by dd DN: cn=dd, o=dd, ou=dd, email=dddd@yahoo. com, c=US Date: 2009.12.04 19:46:56 +07'00'
D D
Thermal Sensor
ADT7473
50
SMBus
C C
1394
48
CLK GEN
ICS9LPRS355AKLFT
TOTAL 8GB SUPPORT
DDRII
Slot 0
533/667
DDRII
Slot 1
533/667
Ricoh
16 5,6,7
DDRII 533/667 Channel A
14
DDR II 533/667 Channel B
15
5C833
SD/MMC
48
RJ45 CONN
25
RJ11 CONN
B B
INTERNAL ARRAY MIC
MIC IN
25
PRE-AMP
TLV2462
28
Headphone
A A
5CC SPEAKER
5
CardReader
47
Intel Ninevah-MM (82566MM)
10/100/1000
24
MODEM MDC V1.5
32
AUDIO CODEC
ADI 1981HD
27
OP AMP
TPA6211A1
CRT LINE OUTLINE IN USB*4 TVOUT Ethernet
28
4
3
NORN Block Diagram
Project code : 91.4R801.001 PCB P/N : 06200 Revision : DB2
ALS
LX1970
USB 2.0
PATA
LPC Bus
SPI
Flash ROM
16Mb x 1 32Mb x 1(AMT)
ODD
3
Aceelerometer
30
33
49
SM Bus
STMicro LIS3LV02DL
DMI x 2/x4
PCI
PCIE/GLCI
PCI/LCI
HD Audio
PCIE+USB 2.0
Ricoh R5538
23
Express Card 54
4
Meron 2M/4M ULV FSB:667 or 800 MHz
HOST BUS
Crestline-GME
INTEGRATED GRAHPICS
10 USB 2.0/1.1 ports
ETHERNET
High Definition Audio
PCIE x 1
Mini-Card
802.11abg/n
23
DOCK
Intel CPU
FBS 667/800MHz
AGTL+ CPU I/F DDR Memory I/F
LVDS, CRT I/F
8,9,10,11,12,13
INTEL
ICH8-M
(10/100/1000Mb)
ATA 66/100
ACPI 1.1 LPC I/F
PCI/PCI BRIDGE
19,20,21,22
C-LINK
Mini-Card
WWAN
C-LINK0
USB 2.0 X 1
2626
RGB CRT
LVDS
26
KBC
SMSC KBC1070
Tauch Pad
Int. KB
2
2
Fingerprinter
AES2501B
CAMERA
BLUE TOOTH
USB x 2
HDD Bay
1.8" PATA
SLB9635TT
31
Capacitive Button
493232
1
SYSTEM DC/DC
INPUTS
B+
45
SYSTEM DC/DC
TPS51120
OUTPUTS
+5VALW 5A +3VALW 4A
INPUTS
B+
VGA
MAX8776
OUTPUTS
VCCGFX
TPS51124
CRT
LCD
INPUTS
B+
17
18
INPUTS
OUTPUTS
+1.5VS 4A +VCCP 6A
CHARGER
BQ24703
OUTPUTS
BATT
49
49
BATT_A BATT_B
18V 3.0A 5V 100mA
CPU DC/DC
29
29
23
TPM
30
Serial Bus
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3 Date: Sheet
Date: Sheet
Date: Sheet
W-COM
Digitizer
18
Block Diagram
Block Diagram
Block Diagram
NORN
NORN
NORN
ISL6260
INPUTS
B+
OUTPUTS
+VCC_CORE
0.844~1.3V 44A
PCB LAYER
L1:
Signal 1
L2:
Signal 2 GNDL3: Signal 3
L4: L5:
VCC
L6:
GND Signal 4
L7: L8:
GND
L9:
Signal 5
L10:
Signal 6
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
251Monday, March 05, 2007
251Monday, March 05, 2007
251Monday, March 05, 2007
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PV
PV
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D D
C C
B B
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3 Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
Change Notes List
Change Notes List
Change Notes List
Taipei Hsien 221, Taiwan, R.O.C.
NORN
NORN
NORN
A
PV
PV
351Monday, March 05, 2007
351Monday, March 05, 2007
351Monday, March 05, 2007
PV
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Voltage Rails
power plane
D D
C C
B B
A A
State
S0
S3/M1
S3
S5 S4/AC
S5 S4/Battery only
S5 S4/AC & Battery don't exist
PCI Devices
EETERNAL
Cardreader & 1394
DMA Channel
DMA1 DMA2 DMA3 DMA4 DMA5 DMA6 DMA7
USB PORT#
0
1
2
3
4
5
6
7
8
9
5
o MEANS ON x MEANS OFF
+BB
+5VALW
LDO3
+5VALW
LDO5
o
oo o o o oo o
o oo
o
x
IDSEL#
AD22
Device
Modem/LANDMA0 ECP Floppy Disk Audio (Cascade) Unused Unused Unused
Destination
FREE
Fingerprint
EXPRESS SLOT
Camera
Walk-up1 (Right Side)
Walk-up2 (Left Side)
Bluetooth
Dock 1
WWAN
Dock 2
x
x
REQ/GNT#2PIRQ
+5VS +3VS
+1.8V
+1.8VS +1.5VS +1.25VS
+0.9V
+VGA_CORE +CPU_CORE +VCCP
oo o
x
x
x
G,E
DY/DUMMY No install
4
+3VM +1.05VM +1.25VM
x x x x
x
1KR2J
1KR3F Resistor 1K ohm ,Size 0603 ,1%
GP ROHS parts
NC Pin no connect to anything
o o
x
x
DescriptionSymbols
Resistor 1K ohm ,Size 0402 ,5%
4
CLOCK
o o
o
x
x
3
IRQ Device
0
System Timer
1
Keyboard
2
N/A
3
Serial port (COM2) ,LAN/Modem
4
Serial port (COM1)
5
Audio/VGA
6
Floppy
7
Parallel port
8
System CMOS/Real-time clock
9
Microsoft ACPI
10
N/A,Modem,LAN
11
Mass storage control/PCI simple communication control
12
synactic PS2 port GlidePAD
13
Numeric Data Process
14
Primary IDE interface ,HDD
15
Secondary IDE interface ,CD-ROM
Mobile Intel Crestline Express Chipset Family Microsoft UAA Bus Drive for High Definition Audio
16
Intel 82801H (ICH8 Family) PCI Express Root Port -27D0 Broadcom NetXtreme Gigabit Ethernet
Intel 82801H (ICH8 Family) PCI Express Root Port -27D2
17
Broadcom 802.11b/g WLAN Intel 82801H (ICH8 Family) USB Universal Host Control
Intel 82801H (ICH8 Family) USB Universal Host Control
18
Richo R5C853 Integrates FlashMedia Control Richo R5C853 Gemcore based SmartCard Control
Intel 82801H (ICH8 Family) PCI Express Root Port -27D6
19
Intel 82801H (ICH8 Family) USB Universal Host Control
Intel 82801H (ICH8 Family) USB Universal Host Control
20
Intel 82801H (ICH8 Family) USB2 Enhanced Host Control
21
Intel 82801H (ICH8 Family) USB Universal Host Control
22
SDA Standard Compliant SD Host Control
23
HP Mobile Data Protection Sensor
3
2
2
1
<Variant Name>
<Variant Name>
<Variant Name>
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3 Date: Sheet
Date: Sheet
Date: Sheet
Taipei Hsien 221, Taiwan, R.O.C.
Notes List
Notes List
Notes List
NORN
NORN
NORN
451Friday, March 23, 2007
451Friday, March 23, 2007
451Friday, March 23, 2007
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DCCBBAA
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D
H_A#[3..35]8
1 OF 4
1 OF 4
U88A
U88A
H_A#3
J4
A3#
H_A#4
L5
A4#
H_A#5
L4
H_A#6
K5
H_A#7
M3
H_A#8
N2
H_A#9
J1
H_A#10
N3
H_A#11
P5
H_A#12
P2
H_A#13
L2
H_A#14
P4
H_A#15
P1
H_A#16
R1
H_ADSTB#0
H_ADSTB#08 H_REQ#08
H_REQ#18 H_REQ#28 H_REQ#38 H_REQ#48
H_ADSTB#18
H_A20M#20 H_FERR#20 H_IGNNE#20
H_STPCLK#20 H_INTR20 H_NMI20 H_SMI#20
TP19TPAD28 TP19TPAD28 TP17TPAD28 TP17TPAD28 TP24TPAD28 TP24TPAD28 TP22TPAD28 TP22TPAD28 TP32TPAD28 TP32TPAD28 TP26TPAD28 TP26TPAD28 TP27TPAD28 TP27TPAD28 TP3TPAD28 TP3TPAD28 TP21TPAD28 TP21TPAD28 TP16TPAD28 TP16TPAD28
TP31TPAD28 TP31TPAD28
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35
H_ADSTB#1 H_A20M#
H_FERR# H_IGNNE#
CPU_RSVD01 CPU_RSVD02 CPU_RSVD03 CPU_RSVD04 CPU_RSVD05 CPU_RSVD06 CPU_RSVD07 CPU_RSVD08 CPU_RSVD09 CPU_RSVD10
CPU_RSVD11
M1 K3
H2 K2
J3 L1
Y2 U5 R3 W6 U4 Y5 U1 R4
T5
T3 W2 W5 Y4 U2 V4 W3
AA4 AB2 AA3
V1 A6
A5 C4
D5 C6 B4 A3
M4 N5
T2 V3 B2 C3 D2
D22
D3
F6 B1
A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# ADSTB0#
REQ0# REQ1# REQ2# REQ3# REQ4#
A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# A32# A33# A34# A35# ADSTB1#
A20M# FERR# IGNNE#
STPCLK# LINT0 LINT1 SMI#
RSVD#M4 RSVD#N5 RSVD#T2 RSVD#V3 RSVD#B2 RSVD#C3 RSVD#D2 RSVD#D22 RSVD#D3 RSVD#F6
KEY_NC
MEROM-479P-GP-U
MEROM-479P-GP-U
ADDR GROUP 0
ADDR GROUP 0
ADDR GROUP 1
ADDR GROUP 1
ICH
ICH
RESERVED
RESERVED
DEFER#
RESET#
XDP/ITP SIGNALS CONTROL
XDP/ITP SIGNALS CONTROL THERMAL
THERMAL
PROCHOT#
THRMDA THRMDC
THERMTRIP#
HCLK
HCLK
ADS# BNR#
BPRI#
DRDY# DBSY#
BR0#
IERR#
INIT#
LOCK#
RS0# RS1# RS2#
TRDY#
HITM#
BPM0# BPM1# BPM2# BPM3# PRDY# PREQ#
TRST#
DBR#
BCLK0 BCLK1
H1 E2 G5
H5 F21 E1
F1 D20
B3 H4 C1
F3 F4 G3 G2
G6
HIT#
E4 AD4
AD3 AD1 AC4 AC2 AC1 AC5
TCK
AA6
TDI
AB3
TDO
AB5
TMS
AB6 C20
D21 A24 B25
C7
A22 A21
H_ADS# H_BNR# H_BPRI#
H_DEFER# H_DRDY# H_DBSY#
H_BR0# H_IERR#
H_INIT# H_LOCK#
H_RESET#
H_RS#0 H_RS#1 H_RS#2 H_TRDY#
H_HIT# H_HITM#
XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST#
XDP_DBRESET#
H_PROCHOT#
H_THERMDA H_THERMDC
H_THERMTRIP#
CLK_CPU_BCLK CLK_CPU_BCLK#
TP72 TPAD28TP72 TPAD28
H_ADS# 8 H_BNR# 8
H_BPRI# 8 H_DEFER# 8
H_DRDY# 8 H_DBSY# 8
H_BR0# 8
H_INIT# 20
H_LOCK# 8
H_RESET# 8
H_RS#0 8 H_RS#1 8 H_RS#2 8
H_TRDY# 8
H_HIT# 8 H_HITM# 8
XDP_DBRESET# 21
R505 68R2-GPR505 68R2-GP
H_THERMTRIP# 8,20
CLK_CPU_BCLK 16 CLK_CPU_BCLK# 16
+VCCP
12
R502
R502 56R2J-4-GP
56R2J-4-GP
H_PROCHOT# 43
1 2
+VCCP
H_THERMDA 50 H_THERMDC 50
H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil
+VCCP
H_PWRGOOD_R6
12
C334
C334 SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
XDP_BPM#5 XDP_BPM#4
XDP_BPM#3 XDP_BPM#2
XDP_BPM#1 XDP_BPM#0
XDP_HOOK1
XDP_TCK
XDP Connector
XDP1
XDP1
DY
DY
STC-CONN60A-GP-U1
STC-CONN60A-GP-U1
0630 Connector Vendor :SmaTec Part Number : QSH-030-01-F-D-TR
1 2 3 4
5 6 7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
NP1 61
62
63 64 NP2
H_RESET#_R XDP_DBRESET#_R
R266 1KR2F-3-GPR266 1KR2F-3-GP R306 200R2F-L-GPR306 200R2F-L-GP
layout note : Change R305 to 649 ohm if using XTP to ITP adapter
XDP_DBRESET#
CLK_CPU_XDP 16 CLK_CPU_XDP# 16
+VCCP
1 2
H_RESET# XDP_DBRESET#
1 2 1 2
XDP_TDO XDP_TRST# XDP_TDI XDP_TMS XDP_PRE
R310 0R2J-2-GPR310 0R2J-2-GP
(Place R310 with in 200ps (~1") to CPU
XDP_TDI XDP_TMS XDP_TDO XDP_BPM#5 XDP_HOOK1
XDP_TRST# XDP_TCK
R305
R305
1 2
DY
DY
1KR2J-1-GP
1KR2J-1-GP
1 2
R256 54D9R2F-L1-GPR256 54D9R2F-L1-GP
1 2
R259 54D9R2F-L1-GPR259 54D9R2F-L1-GP
1 2
R254 54D9R2F-L1-GPR254 54D9R2F-L1-GP
1 2
R239 54D9R2F-L1-GPR239 54D9R2F-L1-GP
1 2
DY
DY
R240 54D9R2F-L1-GP
R240 54D9R2F-L1-GP
R286
R286
1 2
51R2F-2-GP
51R2F-2-GP
1 2
R261 54D9R2F-L1-GPR261 54D9R2F-L1-GP
+3VS
+VCCP
H_PROCHOT#
DY
DY
5
+VCCP
12
R503
R503 56R2J-4-GP
56R2J-4-GP
DY
DY
CBE
Q41
Q41
MMBT3904WT1G-GP
MMBT3904WT1G-GP
OCP# 21,44
4
4 WIRE PWM Fan Control circuit
+5VS
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C237
C234
C234
SC10U10V5KX-2GP
SC10U10V5KX-2GP
FAN_PWM50
FAN_TACH50
C237
12
12
KA
D6 1SS355PT-GPD61SS355PT-GP
3
1 2 3 4
5
FAN1
FAN1 MLX-CON4-15-GP
MLX-CON4-15-GP
6
+5VS
FAN_PWM
FAN_TACH
PAD1
PAD1
1
TP28-75-GP
TP28-75-GP
PAD2
PAD2
1
TP28-75-GP
TP28-75-GP
PAD3
PAD3
1
TP28-75-GP
TP28-75-GP
PAD4
PAD4
1
TP28-75-GP
TP28-75-GP
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Meron(1/3)-AGTL+/XDP
Meron(1/3)-AGTL+/XDP
Meron(1/3)-AGTL+/XDP
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A2
A2
A2 Date: Sheet
Date: Sheet
Date: Sheet of
2
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
NORN
NORN
NORN
5
5
5
1
PV
PV
PV
51Friday, March 30, 2007
51Friday, March 30, 2007
51Friday, March 30, 2007
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H_D#[0..63]8
H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7
TP2TP2
TP1TP1 TP30TP30 TP41TP41
H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14
H_D#15 H_DSTBN#0 H_DSTBP#0 H_DINV#0
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31 H_DSTBN#1 H_DSTBP#1 H_DINV#1
TEST1 TEST2 TEST3 TEST4 TEST5 TEST6
CPU_BSEL0 CPU_BSEL1 CPU_BSEL2
D D
H_DSTBN#08 H_DSTBP#08
H_DINV#08
R510
R510 C470
C470
CPU_BSEL016 CPU_BSEL116 CPU_BSEL216
H_DSTBN#18 H_DSTBP#18 H_DINV#18
V_CPU_GTLREF
1 2
DY
DY
51R2F-2-GP
51R2F-2-GP
C C
1 2
DY
DY
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
PLACE C470 close to the TEST4 PIN, make sure TEST3,TEST4,TEST5 trace routing is reference to GND and away other noisy signals
U88B
U88B
E22
D0#
F24
D1#
E26
D2#
G22
D3#
F23
D4#
G25
D5#
E25
D6#
E23
D7#
K24
D8#
G24
D9#
J24
D10#
J23
D11#
H22
D12#
F26
D13#
K22
D14#
H23
D15#
J26
DSTBN0#
H26
DSTBP0#
H25
DINV0#
N22
D16#
K25
D17#
P26
D18#
R23
D19#
L23
D20#
M24
D21#
L22
D22#
M23
D23#
P25
D24#
P23
D25#
P22
D26#
T24
D27#
R24
D28#
L25
D29#
T25
D30#
N25
D31#
L26
DSTBN1#
M26
DSTBP1#
N24
DINV1#
AD26
GTLREF
C23
TEST1
D25
TEST2
C24
TEST3
AF26
TEST4
AF1
TEST5
A26
TEST6
B22
BSEL0
B23
BSEL1
C21
BSEL2
MEROM-479P-GP-U
MEROM-479P-GP-U
2 OF 4
2 OF 4
B B
CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0
166
200
0
00
1
11
4
DATA GRP0 DATA GRP1
DATA GRP0 DATA GRP1
DATA GRP2DATA GRP3
DATA GRP2DATA GRP3
DSTBN2# DSTBP2#
DSTBN3# DSTBP3#
MISC
MISC
DPRSTP#
PWRGOOD
D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47#
DINV2#
D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63#
DINV3# COMP0
COMP1 COMP2 COMP3
DPSLP#
DPWR#
SLP#
PSI#
Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22
AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20
R26 U26 AA1 Y1
E5 B5 D24 D6 D7 AE6
H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46
H_D#47 H_DSTBN#2 H_DSTBP#2 H_DINV#2
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63 H_DSTBN#3 H_DSTBP#3 H_DINV#3
COMP0
R35 27D4R2F-L1-GPR35 27D4R2F-L1-GP
COMP1
R113
R113
COMP2
R37
R37
COMP3
R114 54D9R2F-L1-GPR114 54D9R2F-L1-GP
H_DPRSTP# H_DPSLP# H_DPWR# H_PWRGOODH_PWRGOOD
H_PWRGOODH_PWRGOOD H_CPUSLP# H_PSI#
R82
R82
1 2
1KR2J-1-GP
1KR2J-1-GP
H_DSTBN#2 8 H_DSTBP#2 8 H_DINV#2 8
H_DSTBN#3 8 H_DSTBP#3 8 H_DINV#3 8
1 2
54D9R2F-L1-GP
54D9R2F-L1-GP
1 2
27D4R2F-L1-GP
27D4R2F-L1-GP
1 2 1 2
H_DPRSTP# 8,20,43 H_DPSLP# 20
H_DPWR# 8 H_PWRGOOD 20 H_CPUSLP# 8
H_PSI# 43
H_PWRGOOD_R 5
Resistor Placed within 0.5" of CPU pin. Trace should be at least 25 mils away from any other toggling signal . COMP[0,2] trace width is 18 mils. COMP[1,3] trace width is 4 mils .
3
+VCC_CORE +VCC_CORE
U88C
U88C
A7
VCC
A9
VCC
A10
VCC
A12
VCC
A13
VCC
A15
VCC
A17
VCC
A18
VCC
A20
VCC
B7
VCC
B9
VCC
B10
VCC
B12
VCC
B14
VCC
B15
VCC
B17
VCC
B18
VCC
B20
VCC
C9
VCC
C10
VCC
C12
VCC
C13
VCC
C15
VCC
C17
VCC
C18
VCC
D9
VCC
D10
VCC
D12
VCC
D14
VCC
D15
VCC
D17
VCC
D18
VCC
E7
VCC
E9
VCC
E10
VCC
E12
VCC
E13
VCC
E15
VCC
E17
VCC
E18
VCC
E20
VCC
F7
VCC
F9
VCC
F10
VCC
F12
VCC
F14
VCC
F15
VCC
F17
VCC
F18
VCC
F20
VCC
AA7
VCC
AA9
VCC
AA10
VCC
AA12
VCC
AA13
VCC
AA15
VCC
AA17
VCC
AA18
VCC
AA20
VCC
AB9
VCC
AC10
VCC
AB10
VCC
AB12
VCC
AB14
VCC
AB15
VCC
AB17
VCC
AB18
VCC
MEROM-479P-GP-U
MEROM-479P-GP-U
3 OF 4
3 OF 4
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP
VCCA VCCA
VID0 VID1 VID2 VID3 VID4 VID5 VID6
VCCSENSE
VSSSENSE
2
AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20
G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21
B26 C26
AD6 AF5 AE5 AF4 AE3 AF3 AE2
AF7
AE7
R49
R49
VCCP_G21
1 2
VCCP_V6
1 2
R90 0R2J-2-GPR90 0R2J-2-GP
CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6
VCCSENSE
VSSSENSE
VCCSENSE
R86
R86
VSSSENSE
R93
R93
Close to CPU pin within 500mils
0R2J-2-GP
0R2J-2-GP
CPU_VID[0..6] 43
VCCSENSE 43
VSSSENSE 43
1 2
100R2F-L1-GP-U
100R2F-L1-GP-U
1 2
100R2F-L1-GP-U
100R2F-L1-GP-U
+VCCP
ST330U2D5VDM-13GP
ST330U2D5VDM-13GP
12
C473
C473
12
Length match within 25 mils . The trace width/space/other is 20/7/25 .
+VCC_CORE
TC2
TC2
+1.5VS
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
12
1
layout note: place C473 near PIN B26
C474
C474 SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
+VCCP
Close to CPU pin AD26 Z0=55 ohm with in 500mils .
5
R506
R506 1KR2F-3-GP
1KR2F-3-GP
1 2
V_CPU_GTLREF
12
R507
R507
2KR2F-3-GP
2KR2F-3-GP
<Core Design>
<Core Design>
<Core Design>
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Meron(2/3)-AGTL+/PWR
Meron(2/3)-AGTL+/PWR
Meron(2/3)-AGTL+/PWR
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3 Date: Sheet
Date: Sheet
4
3
2
Date: Sheet
Taipei Hsien 221, Taiwan, R.O.C.
NORN
NORN
NORN
A
PV
PV
PV
51Friday, March 30, 2007
51Friday, March 30, 2007
51Friday, March 30, 2007
of
of
of
6
6
6
1
5
A
www.kythuatvitinh.com
4 OF 4
4 OF 4
U88D
U88D
A4
VSS
A8
VSS
A11
VSS
D D
C C
B B
A14
VSS
A16
VSS
A19
VSS
A23
VSS
AF2
VSS
B6
VSS
B8
VSS
B11
VSS
B13
VSS
B16
VSS
B19
VSS
B21
VSS
B24
VSS
C5
VSS
C8
VSS
C11
VSS
C14
VSS
C16
VSS
C19
VSS
C2
VSS
C22
VSS
C25
VSS
D1
VSS
D4
VSS
D8
VSS
D11
VSS
D13
VSS
D16
VSS
D19
VSS
D23
VSS
D26
VSS
E3
VSS
E6
VSS
E8
VSS
E11
VSS
E14
VSS
E16
VSS
E19
VSS
E21
VSS
E24
VSS
F5
VSS
F8
VSS
F11
VSS
F13
VSS
F16
VSS
F19
VSS
F2
VSS
F22
VSS
F25
VSS
G4
VSS
G1
VSS
G23
VSS
G26
VSS
H3
VSS
H6
VSS
H21
VSS
H24
VSS
J2
VSS
J5
VSS
J22
VSS
J25
VSS
K1
VSS
K4
VSS
K23
VSS
K26
VSS
L3
VSS
L6
VSS
L21
VSS
L24
VSS
M2
VSS
M5
VSS
M22
VSS
M25
VSS
N1
VSS
N4
VSS
N23
VSS
N26
VSS
P3
VSS
MEROM-479P-GP-U
MEROM-479P-GP-U
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25
CPU_NCTF5
CPU_NCTF3 CPU_NCTF1
CPU_NCTF2 CPU_NCTF4
4
Place these capacitors on L1 (North side ,Secondary Layer)
Place these capacitors on L1 (North side ,Secondary Layer)
3
+VCC_CORE
12
12
12
+VCC_CORE
12
+VCC_CORE
C73
C73
C125
C125
C54
C54
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
12
C83
C83
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
12
C91
C91
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
12
12
C47
C47
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
2
12
12
12
C39
C39
C115
C115
C36
C36
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
12
C46
C46
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
12
C68
C68
C67
C67
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
12
C92
C92
C71
C71
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
12
12
C82
C82
C104
C104
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
1
Mid Frequencd
12
12
12
C111
C111
C130
C130
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
+VCCP
PAD72PAD72
1
C31
C30
C30 SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
PAD73PAD73
1 1
PAD74PAD74
PAD75PAD75
1 1
PAD76PAD76
1 2
C31 SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
1 2
C151
C151 SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
1 2
C29
C29 SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
1 2
C124
C124
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
12
C105
C105
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
C149
C149 SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
1 2
Decoupling
Place these inside socket cavity on L1 (North side Secondary)
C150
C150 SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
1 2
<Core Design>
<Core Design>
<Core Design>
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Meron(3/3)-GND&Bypass
Meron(3/3)-GND&Bypass
Meron(3/3)-GND&Bypass
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3 Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
Taipei Hsien 221, Taiwan, R.O.C.
NORN
NORN
NORN
A
PV
PV
PV
51Tuesday, March 27, 2007
51Tuesday, March 27, 2007
51Tuesday, March 27, 2007
of
of
of
7
7
7
1
5
A
www.kythuatvitinh.com
D D
C C
54D9R2F-L1-GP
54D9R2F-L1-GP
H_D#[0..63]6 H_A#[3..35] 5
+VCCP
12
H_RESET#5 H_CPUSLP#6
H_VREF
12
R516
R516
R515
R515
54D9R2F-L1-GP
54D9R2F-L1-GP
H_SWNG H_RCOMP
H_SCOMP H_SCOMP#
H_RESET# H_CPUSLP#
H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63
B B
layout note : Route H_SCOMP and H_SCOMP# with trace width, spacing and impedance (55 ohm) same as FSB data traces
Layout Note : H_RCOMP / H_VREF / H_SWNG trace width and spacing is 10/20
+VCCP
12
R529
R529 1KR2F-3-GP
1KR2F-3-GP
H_VREF H_RCOMP H_SWNG
12
R527
R527
2KR2F-3-GP
2KR2F-3-GP
Layout Note : Place C484 within 100 mils of NB
12
C484
C484
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
5
U89A
U89A
E2
H_D#0
G2
H_D#1
G7
H_D#2
M6
H_D#3
H7
H_D#4
H3
H_D#5
G4
H_D#6
F3
H_D#7
N8
H_D#8
H2
H_D#9
M10
H_D#10
N12
H_D#11
N9
H_D#12
H5
H_D#13
P13
H_D#14
K9
H_D#15
M2
H_D#16
W10
H_D#17
Y8
H_D#18
V4
H_D#19
M3
H_D#20
J1
H_D#21
N5
H_D#22
N3
H_D#23
W6
H_D#24
W9
H_D#25
N2
H_D#26
Y7
H_D#27
Y9
H_D#28
P4
H_D#29
W3
H_D#30
N1
H_D#31
AD12
H_D#32
AE3
H_D#33
AD9
H_D#34
AC9
H_D#35
AC7
H_D#36
AC14
H_D#37
AD11
H_D#38
AC11
H_D#39
AB2
H_D#40
AD7
H_D#41
AB1
H_D#42
Y3
H_D#43
AC6
H_D#44
AE2
H_D#45
AC5
H_D#46
AG3
H_D#47
AJ9
H_D#48
AH8
H_D#49
AJ14
H_D#50
AE9
H_D#51
AE11
H_D#52
AH12
H_D#53
AJ5
H_D#54
AH5
H_D#55
AJ6
H_D#56
AE7
H_D#57
AJ7
H_D#58
AJ2
H_D#59
AE5
H_D#60
AJ3
H_D#61
AH2
H_D#62
AH13
H_D#63
B3
H_SWING
C2
H_RCOMP
W1
H_SCOMP
W2
H_SCOMP#
B6
H_CPURST#
E5
H_CPUSLP#
B9
H_AVREF
A9
H_DVREF
CRESTLINE-GP-U
CRESTLINE-GP-U
R50
R50 24D9R2F-L-GP
24D9R2F-L-GP
1 OF 10
1 OF 10
H_ADSTB#0 H_ADSTB#1
HOST
HOST
H_DEFER#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3
H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3
+VCCP
R521
R521
100R2F-L1-GP-U
100R2F-L1-GP-U
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8
H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35
H_ADS#
H_BNR#
H_BPRI#
H_BREQ#
H_DBSY#
H_DRDY#
H_HIT#
H_HITM# H_LOCK# H_TRDY#
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
H_RS#0 H_RS#1 H_RS#2
12
12
R523
R523 221R2F-2-GP
221R2F-2-GP
12
J13 B11 C11 M11 C15 F16 L13 G17 C14 K16 B13 L16 J17 B14 K19 P15 R17 B16 H20 L19 D17 M17 N16 J19 B18 E19 B17 B15 E17 C18 A19 B19 N19
G12 H17 G20 C8 E8 F12 D6 C10
CLK_MCH_BCLK
AM5
CLK_MCH_BCLK#
AM7 H8 K7 E4 C6 G10 B7
K5 L2 AD13 AE13
M7 K3 AD2 AH11
L7 K2 AC2 AJ10
M14 E13 A11 H13 B12
E12 D7 D8
C480
C480 SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
Layout Note : Place C480 near pin B3 of NB
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35
H_ADS# H_ADSTB#0 H_ADSTB#1 H_BNR# H_BPRI# H_BR0# H_DEFER# H_DBSY#
H_DPWR# H_DRDY#
H_HIT#
H_HITM# H_LOCK# H_TRDY#
H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3
H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3
H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
4
4
H_ADS# 5 H_ADSTB#0 5 H_ADSTB#1 5 H_BNR# 5
H_BPRI# 5
H_BR0# 5
H_DEFER# 5
H_DBSY# 5 CLK_MCH_BCLK 16 CLK_MCH_BCLK# 16
H_DPWR# 6
H_DRDY# 5
H_HIT# 5
H_HITM# 5 H_LOCK# 5
H_TRDY# 5
H_DINV#0 6 H_DINV#1 6 H_DINV#2 6 H_DINV#3 6
H_DSTBN#0 6 H_DSTBN#1 6 H_DSTBN#2 6 H_DSTBN#3 6
H_DSTBP#0 6 H_DSTBP#1 6 H_DSTBP#2 6 H_DSTBP#3 6
H_REQ#0 5 H_REQ#1 5 H_REQ#2 5 H_REQ#3 5 H_REQ#4 5
H_RS#0 5 H_RS#1 5 H_RS#2 5
PM_PWROK21,31,43,45
VGATE21,43
PLT_RST#19,23,26,30,49
+1.8V
12
C147
SC2D2U10V3ZY-1GP
C147
SC2D2U10V3ZY-1GP
SM_RCOMP_VOH
SM_RCOMP_VOL
C172
C172
1 2
SC2D2U10V3ZY-1GP
SC2D2U10V3ZY-1GP
PM_EXTTS#0
PM_EXTTS#1
CLKREQ#_B
CFG[17:3] have inernal pull up CFG[19:18] have inernal pull down
R581 0R0402-PADR581 0R0402-PAD
H_THERMTRIP#5,20
1 2
R118 10KR2J-3-GPR118 10KR2J-3-GP
1 2
R109 10KR2J-3-GPR109 10KR2J-3-GP
1 2
R117 10KR2J-3-GPR117 10KR2J-3-GP
R582 0R2J-2-GP
R582 0R2J-2-GP
1 2
DY
DY
1 2
PLT_RST# RSTIN#
12
12
C153
C153
SCD01U25V2KX-3GP
SCD01U25V2KX-3GP
12
12
C167
C167
1 2
SCD01U25V2KX-3GP
SCD01U25V2KX-3GP
PM_BMBUSY#21 H_DPRSTP#6,20,43 PM_EXTTS#014 PM_EXTTS#115
DPRSLPVR21,43
R850
R850
1 2
100R2J-2-GP
100R2J-2-GP
1 2
R79 0R0402-PADR79 0R0402-PAD
3
R92
R92 1KR2F-3-GP
1KR2F-3-GP
R94
R94 3K01R2F-3-GP
3K01R2F-3-GP
R96
R96 1KR2F-3-GP
1KR2F-3-GP
+3VS
MCH_CLKSEL016 MCH_CLKSEL116 MCH_CLKSEL216
PM_POK_R
PAD79PAD79
PAD77PAD77
PAD81PAD81
3
MCH_CLKSEL0 MCH_CLKSEL1 MCH_CLKSEL2
TP8TP8 TP12TP12 TP4TP4 TP5TP5 TP7TP7 TP15TP15 TP14TP14 TP9TP9 TP13TP13
TP10TP10 TP18TP18
TP25TP25 TP29TP29
H_THERMTRIP#_N20
CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13
CFG16 CFG18
CFG19 CFG20
PM_BMBUSY# H_DPRSTP# PM_EXTTS#0 PM_EXTTS#1 PM_POK_R RSTIN#
H_THERMTRIP#_N20
DPRSLPVR
MCH_NCTF4
1
MCH_NCTF5
1
MCH_NCTF3
1
AR12 AR13 AM12 AN13
AR37 AM36 AL36 AM37
BJ20 BK22 BF19 BH20 BK18
BJ18 BF23 BG23 BC23 BD24
BH39
AW20
BK20
AW49
AV20
BJ51 BK51 BK50 BL50 BL49
P36 P37 R35 N35
J12
D20
H10 B51
B44 C44 A35 B37 B36 B34 C34
P27 N27 N24 C21 C23 F23 N23 G23 J20 C20 R24 L23 J23 E23 E20
K23 M20 M24
L32 N33
L35
G41
L39
L36
J36
N20 G36
BL3
BL2 BK1
BJ1
E1 A5
C51
B50
A50
A49 BK2
2 OF 10
2 OF 10
U89B
U89B
RSVD#P36 RSVD#P37 RSVD#R35 RSVD#N35 RSVD#AR12 RSVD#AR13 RSVD#AM12 RSVD#AN13 RSVD#J12 RSVD#AR37 RSVD#AM36 RSVD#AL36 RSVD#AM37 RSVD#D20
RSVD#H10 RSVD#B51 RSVD#BJ20 RSVD#BK22 RSVD#BF19 RSVD#BH20 RSVD#BK18 RSVD#BJ18 RSVD#BF23 RSVD#BG23 RSVD#BC23 RSVD#BD24
RSVD#BH39 RSVD#AW20 RSVD#BK20
RSVD#B44 RSVD#C44 RSVD#A35 RSVD#B37 RSVD#B36 RSVD#B34 RSVD#C34
CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20
PM_BM_BUSY# PM_DPRSTP# PM_EXT_TS#0 PM_EXT_TS#1 PWROK RSTIN# THERMTRIP# DPRSLPVR
NC#BJ51 NC#BK51 NC#BK50 NC#BL50 NC#BL49 NC#BL3 NC#BL2 NC#BK1 NC#BJ1 NC#E1 NC#A5 NC#C51 NC#B50 NC#A50 NC#A49 NC#BK2
CRESTLINE-GP-U
CRESTLINE-GP-U
RSVD
RSVD
DDR MUXING
DDR MUXING
SM_RCOMP_VOH
SM_RCOMP_VOL
SM_RCOMP#
SM_VREF#AR49
SM_VREF#AW4
DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
CLK
CLK
DMI
DMI
CFG PM NC
CFG PM NC
SDVO_CTRL_CLK
SDVO_CTRL_DATA
MISC ME GRAPHICS VID
MISC ME GRAPHICS VID
2
SM_CK0 SM_CK1 SM_CK3 SM_CK4
SM_CK#0 SM_CK#1 SM_CK#3 SM_CK#4
SM_CKE0 SM_CKE1 SM_CKE3 SM_CKE4
SM_CS#0 SM_CS#1 SM_CS#2 SM_CS#3
SM_ODT0 SM_ODT1 SM_ODT2 SM_ODT3
SM_RCOMP
PEG_CLK
PEG_CLK#
DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3
DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3
DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3
DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3
GFX_VID0 GFX_VID1 GFX_VID2 GFX_VID3
GFX_VR_EN
CL_CLK
CL_DATA
CL_PWROK
CL_RST# CL_VREF
CLKREQ#
ICH_SYNC#
TEST1 TEST2
2
M_CLK_DDR0
AV29
M_CLK_DDR1
BB23
M_CLK_DDR2
BA25
M_CLK_DDR3
AV23
M_CLK_DDR#0
AW30
M_CLK_DDR#1
BA23
M_CLK_DDR#2
AW25
M_CLK_DDR#3
AW23
DDR_CKE0_DIMMA
BE29
DDR_CKE1_DIMMA
AY32
DDR_CKE2_DIMMB
BD39
DDR_CKE3_DIMMB
BG37
DDR_CS0_DIMMA#
BG20
DDR_CS1_DIMMA#
BK16
DDR_CS2_DIMMB#
BG16
DDR_CS3_DIMMB#
BE13
M_ODT0
BH18
M_ODT1
BJ15
M_ODT2
BJ14
M_ODT3
BE16
SM_RCOMP_VOH
BK31
SM_RCOMP_VOL
BL31
SM_RCOMP
BL15
SM_RCOMP#
BK14 AR49
AW4
CLK_MCH_DREFCLK
B42
CLK_MCH_DREFCLK#
C42
MCH_SSCDREFCLK
H48
MCH_SSCDREFCLK#
H47
CLK_MCH_3GPLL
K44
CLK_MCH_3GPLL#
K45
AN47 AJ38 AN42 AN46
AM47 AJ39 AN41 AN45
AJ46 AJ41 AM40 AM44
AJ47 AJ42 AM39 AM43
DFGT_VID0
E35
DFGT_VID1
A39
DFGT_VID2
C38
DFGT_VID3
B39
DFGT_VR_EN
E36
AM49 AK50
CLPWROK_MCH
AT43 AN49
CL_VREF
AM50
H35 K36 G39
MCH_ICH_SYNC#
G40
TEST1_GMCH
A37
TEST2_GMCH
R32
M_CLK_DDR0 14 M_CLK_DDR1 14 M_CLK_DDR2 15 M_CLK_DDR3 15
M_CLK_DDR#0 14 M_CLK_DDR#1 14 M_CLK_DDR#2 15 M_CLK_DDR#3 15
DDR_CKE0_DIMMA 14 DDR_CKE1_DIMMA 14 DDR_CKE2_DIMMB 15 DDR_CKE3_DIMMB 15
DDR_CS0_DIMMA# 14 DDR_CS1_DIMMA# 14 DDR_CS2_DIMMB# 15 DDR_CS3_DIMMB# 15
M_ODT0 14 M_ODT1 14 M_ODT2 15 M_ODT3 15
1 2
R76 20R2F-GPR76 20R2F-GP
1 2
R73 20R2F-GPR73 20R2F-GP
V_DDR_MCH_REF
DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3
DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3
DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3
DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3
R139 0R2J-2-GPR139 0R2J-2-GP
ICH_SDVO_CLK ICH_SDVO_DATA
1 2
R103
R103 20KR2J-L2-GP
20KR2J-L2-GP
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev Custom
Custom
Custom Date: Sheet
Date: Sheet
Date: Sheet
V_DDR_MCH_REF
CLK_MCH_DREFCLK 16 CLK_MCH_DREFCLK# 16 MCH_SSCDREFCLK 16 MCH_SSCDREFCLK# 16
CLK_MCH_3GPLL 16 CLK_MCH_3GPLL# 16
DMI_TXN0 21 DMI_TXN1 21 DMI_TXN2 21 DMI_TXN3 21
DMI_TXP0 21 DMI_TXP1 21 DMI_TXP2 21 DMI_TXP3 21
DMI_RXN0 21 DMI_RXN1 21 DMI_RXN2 21 DMI_RXN3 21
DMI_RXP0 21 DMI_RXP1 21 DMI_RXP2 21 DMI_RXP3 21
DFGT_VID0 45 DFGT_VID1 45 DFGT_VID2 45 DFGT_VID3 45 DFGT_VR_EN 45
1 2
TP28TP28 TP33TP33
CLKREQ#_B 16 MCH_ICH_SYNC# 21
1 2
R557
R557 0R0402-PAD
0R0402-PAD
CRESTLINE(1/6)-AGTL+/DMI/DDR2
CRESTLINE(1/6)-AGTL+/DMI/DDR2
CRESTLINE(1/6)-AGTL+/DMI/DDR2
+1.8V
V_DDR_MCH_REF
DUMMY-R2
DUMMY-R2
CL_CLK0 21
CL_DATA0 21 M_PWROK 21,35 CL_RST# 21
C548
C548
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
NORN
NORN
NORN
1
R170
R170
+1.25VM_AXD
12
1
12
1 2
12
12
R583
R583 1KR2F-3-GP
1KR2F-3-GP
R584
R584 392R2F-GP
392R2F-GP
8
8
8
R58
R58 DUMMY-R3
DUMMY-R3
of
of
of
A
PV
PV
PV
51Friday, March 30, 2007
51Friday, March 30, 2007
51Friday, March 30, 2007
5
A
www.kythuatvitinh.com
4
3
2
1
DDR_A_D[0..63] 14 DDR_A_BS[0..2] 14 DDR_A_DM[0..7] 14
SA_BS0 SA_BS1 SA_BS2
SA_CAS#
SA_DM0 SA_DM1 SA_DM2 SA_DM3 SA_DM4 SA_DM5 SA_DM6 SA_DM7
SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6
SA_DQS7 SA_DQS#0 SA_DQS#1 SA_DQS#2 SA_DQS#3 SA_DQS#4 SA_DQS#5 SA_DQS#6 SA_DQS#7
SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8
SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14
SA_RAS#
SA_WE#
DDR_A_DQS[0..7] 14 DDR_A_DQS#[0..7] 14 DDR_A_MA[0..13] 14
DDR_A_BS0
BB19
DDR_A_BS1
BK19
DDR_A_BS2
BF29
DDR_A_CAS#
BL17
DDR_A_DM0
AT45
DDR_A_DM1
BD44
DDR_A_DM2
BD42
DDR_A_DM3
AW38
DDR_A_DM4
AW13
DDR_A_DM5
BG8
DDR_A_DM6
AY5
DDR_A_DM7
AN6
DDR_A_DQS0
AT46
DDR_A_DQS1
BE48
DDR_A_DQS2
BB43
DDR_A_DQS3
BC37
DDR_A_DQS4
BB16
DDR_A_DQS5
BH6
DDR_A_DQS6
BB2
DDR_A_DQS7
AP3
DDR_A_DQS#0
AT47
DDR_A_DQS#1
BD47
DDR_A_DQS#2
BC41
DDR_A_DQS#3
BA37
DDR_A_DQS#4
BA16
DDR_A_DQS#5
BH7
DDR_A_DQS#6
BC1
DDR_A_DQS#7
AP2
DDR_A_MA0
BJ19
DDR_A_MA1
BD20
DDR_A_MA2
BK27
DDR_A_MA3
BH28
DDR_A_MA4
BL24
DDR_A_MA5
BK28
DDR_A_MA6
BJ27
DDR_A_MA7
BJ25
DDR_A_MA8
BL28
DDR_A_MA9
BA28
DDR_A_MA10
BC19
DDR_A_MA11
BE28
DDR_A_MA12
BG30
DDR_A_MA13
BJ16 BJ29
DDR_A_RAS#
BE18
SA_RCVEN#
AY20
DDR_A_WE#
BA19
5 OF 10
5 OF 10
U89E
DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3
DDR_A_CAS# 14 DDR_B_CAS# 15
DDR_A_MA14 14 DDR_B_MA14 15
DDR_A_RAS# 14
DDR_A_WE# 14
DDR_B_D4 DDR_B_D5 DDR_B_D6
DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63
AP49
AR51 AW50 AW51
AN51
AN50
AV50
AV49
BA50
BB50
BA49
BE50
BA51
AY49
BF50
BF49
BJ50 BJ44 BJ43
BL43 BK47 BK49 BK43 BK42
BJ41
BL41
BJ37
BJ36 BK41
BJ40
BL35 BK37 BK13 BE11 BK11 BC11 BC13 BE12 BC12
BG12
BJ10
BK5 BK9
BK10
BH5 BG1 BC2 BK3 BE4 BD3
BA3 BB3 AR1
AY2 AY3 AU2
BL9 BL5
BJ8 BJ6 BF4
BJ2
AT3
AT2
U89E
SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63
CRESTLINE-GP-U
CRESTLINE-GP-U
D D
4 OF 10
4 OF 10
U89D
DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8
DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
C C
B B
DDR_A_D21
DDR_A_D22
DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63
AR43
AW44
BA45 AY46 AR41 AR45 AT42
AW47
BB45 BF48 BG47
BJ45 BB47 BG50 BH49 BE45
AW43
BE44 BG42 BE40 BF44 BH45 BG40 BF40 AR40
AW40
AT39
AW36 AW41
AY41 AV38 AT38 AV13 AT13
AW11
AV11 AU15 AT11 BA13 BA11 BE10 BD10
BD8 AY9
BG10
AW9
BD7 BB9 BB5 AY7 AT5 AT7 AY6 BB7 AR5 AR8 AR9 AN3 AM8
AN10
AT9 AN9 AM9
AN11
U89D
SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63
CRESTLINE-GP-U
CRESTLINE-GP-U
DDR SYSTEM MEMORRY A
DDR SYSTEM MEMORRY A
SA_RCVEN#
DDR_B_D[0..63] 15 DDR_B_BS[0..2] 15 DDR_B_DM[0..7] 15 DDR_B_DQS[0..7] 15 DDR_B_DQS#[0..7] 15 DDR_B_MA[0..13] 15
DDR_B_BS0
AY17
SB_BS0 SB_BS1 SB_BS2
SB_CAS#
SB_DM0 SB_DM1 SB_DM2 SB_DM3 SB_DM4 SB_DM5 SB_DM6 SB_DM7
SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6
SB_DQS7 SB_DQS#0 SB_DQS#1 SB_DQS#2 SB_DQS#3 SB_DQS#4 SB_DQS#5 SB_DQS#6 SB_DQS#7
SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_RAS#
SB_RCVEN#
SB_WE#
BG18 BG36
BE17 AR50
BD49 BK45 BL39 BH12 BJ7 BF3 AW2
AT50 BD50 BK46 BK39 BJ12 BL7 BE2 AV2 AU50 BC50 BL45 BK38 BK12 BK7 BF2 AV3
BC18 BG28 BG25 AW17 BF25 BE25 BA29 BC28 AY28 BD37 BG17 BE37 BA39 BG13 BE24
AV16 AY18
BC17
DDR_B_BS1 DDR_B_BS2
DDR_B_CAS# DDR_B_DM0
DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7
DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7
DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13
DDR_B_MA14DDR_A_MA14
DDR_B_RAS# SB_RCVEN#
DDR_B_WE#
DDR_B_RAS# 15
TP11TP11TP6TP6
DDR_B_WE# 15
<Core Design>
<Core Design>
<Core Design>
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
CRESTLINE(2/6)-DDR2 A/B CH
CRESTLINE(2/6)-DDR2 A/B CH
CRESTLINE(2/6)-DDR2 A/B CH
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3 Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
Taipei Hsien 221, Taiwan, R.O.C.
NORN
NORN
NORN
A
PV
PV
PV
51Friday, March 30, 2007
51Friday, March 30, 2007
51Friday, March 30, 2007
of
of
of
9
9
9
1
5
A
www.kythuatvitinh.com
BLON_PWM49 ENABLT18
+3VS
DDC2_CLK18 DDC2_DATA18 ENAVDD18
D D
M_COMP M_LUMA
DDC1_CLK17 DDC1_DATA17 M_VSYNC17
M_HSYNC17
M_CRMA
+3VS
M_BLUE M_GREEN M_RED
DDC2_CLK
2K2R2J-2-GP
2K2R2J-2-GP
DDC2_DATA
2K2R2J-2-GP
2K2R2J-2-GP
C C
B B
+3VS
1 2
R111
R111
1 2
R108
R108
R140 2K4R2F-GPR140 2K4R2F-GP
TXCLK_L-18 TXCLK_L+18
TXOUT_L0-18 TXOUT_L1-18 TXOUT_L2-18
TXOUT_L0+18 TXOUT_L1+18 TXOUT_L2+18
12
R816 2K2R2J-2-GP
R816 2K2R2J-2-GP
12
BLON_PWM ENABLT
1 2
R128
R128
1 2
1 2
R84
R84
R85
R85
12
12
75R2F-2-GP
75R2F-2-GP
75R2F-2-GP
75R2F-2-GP
1 2
DY
DY
1 2
DY
DY
R110 2K2R2J-2-GP
R110 2K2R2J-2-GP
12
R532
R532 75R2F-2-GP
75R2F-2-GP
DDC1_CLK DDC1_DATA
12
R537
R537 75R2F-2-GP
75R2F-2-GP
1 2
R104 39R3J-1-GPR104 39R3J-1-GP
1 2
R107 39R3J-1-GPR107 39R3J-1-GP
1 2
R556 1K3R2F-1-GPR556 1K3R2F-1-GP
FOR Calero: 255 ohm Crestline: 1.3k ohm
R116
R116 10KR2J-3-GP
10KR2J-3-GP 10KR2J-3-GP
10KR2J-3-GP
LVDS_IBG
R89
R89
75R2F-2-GP
75R2F-2-GP
R550
R550 75R2F-2-GP
75R2F-2-GP
CRT_VSYNC CRT_HSYNC CRTIREF
4
U89C
U89C
J40
L_BKLT_CTRL
H39
L_BKLT_EN
E39
L_CTRL_CLK
E40
L_CTRL_DATA
C37
L_DDC_CLK
D35
L_DDC_DATA
K40
L_VDD_EN
L41
LVDS_IBG
L43
LVDS_VBG
N41
LVDS_VREFH
N40
LVDS_VREFL
D46
LVDSA_CLK#
C45
LVDSA_CLK
D44
LVDSB_CLK#
E42
LVDSB_CLK
G51
LVDSA_DATA#0
E51
LVDSA_DATA#1
F49
LVDSA_DATA#2
C48
LVDSA_DATA#3
G50
LVDSA_DATA0
E50
LVDSA_DATA1
F48
LVDSA_DATA2
D47
LVDSA_DATA3
G44
LVDSB_DATA#0
B47
LVDSB_DATA#1
B45
LVDSB_DATA#2
E44
LVDSB_DATA0
A47
LVDSB_DATA1
A45
LVDSB_DATA2
E27
TVA_DAC
G27
TVB_DAC
K27
TVC_DAC
F27
TVA_RTN
J27
TVB_RTN
L27
TVC_RTN
M35
TV_DCONSEL0
P33
TV_DCONSEL1
H32
CRT_BLUE
G32
CRT_BLUE#
K29
CRT_GREEN
J29
CRT_GREEN#
F29
CRT_RED
E29
CRT_RED#
K33
CRT_DDC_CLK
G35
CRT_DDC_DATA
E33
CRT_VSYNC
C32
CRT_TVO_IREF
F33
CRT_HSYNC
CRESTLINE-GP-U
CRESTLINE-GP-U
3 OF 10
3 OF 10
LVDS
LVDS
TV VGA
TV VGA
CRT Termination/EMI Filter Place Close Connector
TV-Out Terminination/EMI Filter
Place Close N/B
M_COMP
M_LUMA
M_CRMA
12
5
L7 IND-2D2NH-4-GPL7 IND-2D2NH-4-GP
1 2
L5 IND-2D2NH-4-GPL5 IND-2D2NH-4-GP
1 2
L4 IND-2D2NH-4-GPL4 IND-2D2NH-4-GP
1 2
12
12
C117
C117
C140
C140
C170
C170
SC470P50V2KX-3GP
SC470P50V2KX-3GP
SC270P50V2KX-1GP
SC270P50V2KX-1GP
SC150P50V2JN-3GP
SC150P50V2JN-3GP
COMP 33
LUMA 33
CRMA 33
12
12
12
C139
C139
C116
C116
C169
C169
SC470P50V2KX-3GP
SC470P50V2KX-3GP
SC270P50V2KX-1GP
SC270P50V2KX-1GP
SC150P50V2JN-3GP
SC150P50V2JN-3GP
4
+VCCP
PEG_COMPI
PEG_COMPO
PEG_RX#0 PEG_RX#1 PEG_RX#2 PEG_RX#3 PEG_RX#4 PEG_RX#5 PEG_RX#6 PEG_RX#7 PEG_RX#8
PEG_RX#9 PEG_RX#10 PEG_RX#11 PEG_RX#12 PEG_RX#13 PEG_RX#14 PEG_RX#15
PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8
PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15
PEG_TX#0 PEG_TX#1 PEG_TX#2 PEG_TX#3 PEG_TX#4 PEG_TX#5 PEG_TX#6 PEG_TX#7 PEG_TX#8 PEG_TX#9
PEG_TX#10
PCI_EXPRESS GRAPHICS
PCI_EXPRESS GRAPHICS
PEG_TX#11 PEG_TX#12 PEG_TX#13 PEG_TX#14 PEG_TX#15
PEG_TX0
PEG_TX1
PEG_TX2
PEG_TX3
PEG_TX4
PEG_TX5
PEG_TX6
PEG_TX7
PEG_TX8
PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15
1 2
24D9R2F-L-GP
24D9R2F-L-GP
PEGCOMP
N43 M43
J51 L51 N47 T45 T50 U40 Y44 Y40 AB51 W49 AD44 AD40 AG46 AH49 AG45 AG41
J50 L50 M47 U44 T49 T41 W45 W41 AB50 Y48 AC45 AC41 AH47 AG49 AH45 AG42
N45 U39 U47 N51 R50 T42 Y43 W46 W38 AD39 AC46 AC49 AC42 AH39 AE49 AH44
M45 T38 T46 N50 R51 U43 W42 Y47 Y39 AC38 AD47 AC50 AD43 AG39 AE50 AH43
L22
IND-39NH-3-GP
IND-39NH-3-GP
L22
1 2
L24
L24
1 2
L26
L26
1 2
M_RED M_RED_M
M_GREEN
M_BLUE
3
R125
R125
PEGCOMP trace width and spacing is 20/25 mils.
IND-39NH-3-GP
IND-39NH-3-GP
IND-39NH-3-GP
IND-39NH-3-GP
12
3
M_GREEN_M
M_BLUE_M
C506
C506
12
SC18P50V2JN-1-GP
SC18P50V2JN-1-GP
CFG[2:0] FSB Freq select
CFG5 (DMI select)
CFG6 Reserved
CFG7 (CPU Strap)
CFG8 (Low power PCIE)
(PCIE Graphics Lane Reversal)
CFG[11:10] Reserved
CFG[13:12] (XOR/ALLZ)
CFG[15:14] Reserved
CFG16 (FSB Dynamic ODT)
CFG[18:17] Reversed
SDVO_CTRLDATA 0 = No SDVO Device Present *
CFG19(DMI Lane Reversal)
CFG20(PCIE/SDVO consurrent)
L21
L21
C500
C500
12
SC18P50V2JN-1-GP
SC18P50V2JN-1-GP
1 2
1 2
1 2
C489
C489
IND-120NH-4-GP
IND-120NH-4-GP
L23
L23
IND-120NH-4-GP
IND-120NH-4-GP
L25
L25
IND-120NH-4-GP
IND-120NH-4-GP
SC18P50V2JN-1-GP
SC18P50V2JN-1-GP
2
Strap Pin Table
010 = FSB 800MHz 011 = FSB 667MHz Others = Reserved
0 = DMI x 2 1 = DMI x 4 *
0 = Reserved 1 = Mobile CPU *
0 = Normal mode 1 = Low Power mode *
CFG9
RED 33
GREEN 33
BLUE 33
2
0 = Reverse Lane 1 = Normal Operation *
00 = Reserved 01 = XOR Mode Enabled 10 = All Z Mode Enabled 11 = Normal Operation (Default)*
0 = Disable 1 = Enable *
1 = SDVO Device Present
0 = Normal Operation * (Lane number in Order) 1 = Reverse lane
0 = Only PCIE or SDVO is operational * 1 = PCIE/SDVO are operating simu.
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3 Date: Sheet
Date: Sheet
Date: Sheet
1
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
CRESTLINE(3/6)-VGA/LVDS/TV
CRESTLINE(3/6)-VGA/LVDS/TV
CRESTLINE(3/6)-VGA/LVDS/TV
NORN
NORN
NORN
of
of
of
10
10
10
1
A
PV
PV
PV
51Friday, March 30, 2007
51Friday, March 30, 2007
51Friday, March 30, 2007
D D
A
www.kythuatvitinh.com
+3VS_DAC_CRT
C C
B B
SCD022U16V2KX-3GP
SCD022U16V2KX-3GP
12
C242
C242
SCD022U16V2KX-3GP
SCD022U16V2KX-3GP
12
C186
C186
1 2
0R3-0-U-GP
0R3-0-U-GP
+3VS_TVDACC
SCD022U16V2KX-3GP
SCD022U16V2KX-3GP
C158
C158
12
+3VS_TVDACA
SCD022U16V2KX-3GP
SCD022U16V2KX-3GP
12
+3VS_TVDACB
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
+1.25VM
R106
R106
C491
C491
C159
C159
12
12
C181
C181
12
12
C539
C539
1 2
12
TC9
TC9 ST150U4VBM-2GP
ST150U4VBM-2GP
12
1 2
C225
C225
12
1 2
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C504
C504
1 2
12
C207
C207
SCD022U16V2KX-3GP
SCD022U16V2KX-3GP
5
L9
L9
1 2
BLM18PG181SN-3GP
BLM18PG181SN-3GP
C662
C662 SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
L27
L27
1 2
BLM18PG181SN-3GP
BLM18PG181SN-3GP
C663
C663 SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
+1.8V_TXLVDS
+3VS
R72
R72
0R5J-5-GP
0R5J-5-GP
+1.25VM_SM_CK
12
C189
C189
C174
C174
SC1U10V3KX-3GP
SC1U10V3KX-3GP
R146
R146
0R3-0-U-GP
0R3-0-U-GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
R543
R543
0R3-0-U-GP
0R3-0-U-GP
R135
R135
0R3-0-U-GP
0R3-0-U-GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
5
+3VS
+3VS+3VS_DAC_BG
+3VS
R588
R588
1 2
0R3-0-U-GP
0R3-0-U-GP
12
C98
C98
12
C164
C164
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
+3VS
+3VS
+3VS
R571
R571
1 2
0R3-0-U-GP
0R3-0-U-GP
+3VS_PEG_BG
12
12
C94
C94
ST22U6D3VBM-1GP
ST22U6D3VBM-1GP
12
C165
C165
SC1U10V3KX-3GP
SC1U10V3KX-3GP
VCCSYNC
12
+3VS_DAC_CRT
+3VS_DAC_BG
+1.25VS_DPLLA +1.25VS_DPLLB +1.25VM_HPLL +1.25VM_MPLL
C516
C516
C546
C546 SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
+1.25VS_PEGPLL
+1.25VM_A_SM
12
C109
C109
SC4D7U25V5KX-GP
SC4D7U25V5KX-GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
+3VS_TVDACA +3VS_TVDACB +3VS_TVDACC
+1.5VS_TVDAC
+1.5VS_QDAC +1.25VM_HPLL +1.25VS_PEGPLL
+1.8V_LVDS
SCD022U16V2KX-3GP
SCD022U16V2KX-3GP
SC10U10V5KX-2GP
SC10U10V5KX-2GP
C177
C177 SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
20mil
12
C114
C114
SCD22U16V3ZY-GP
SCD22U16V3ZY-GP
SC1U10V3KX-3GP
SC1U10V3KX-3GP
0328 PV
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
12
C179
C179
C163
C163
+1.8V_LVDS
12
C531
C531
J32 A33
B33
A30 B32
B49 H49 AL2
AM2
A41 B41
K50 K49
U51
AW18
AV19 AU19 AU18 AU17
AT22 AT21 AT19 AT18 AT17 AR17 AR16
BC29 BB29
C25 B25 C27 B27 B28 A28
M32
L29 N28
AN2
U48 J41
H42
12
C700
C700
ST220U2VBM-3GP
ST220U2VBM-3GP
1 2
12
C213
C213
SC1U10V3KX-3GP
SC1U10V3KX-3GP
4
U89H
U89H
VCC_SYNC VCCA_CRT_DAC
VCCA_CRT_DAC
VCCA_DAC_BG VSSA_DAC_BG
VCCA_DPLLA VCCA_DPLLB VCCA_HPLL VCCA_MPLL
VCCA_LVDS VSSA_LVDS
VCCA_PEG_BG VSSA_PEG_BG
VCCA_PEG_PLL
VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM
VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM VCCA_SM_NCTF VCCA_SM_NCTF
VCCA_SM_CK VCCA_SM_CK
VCCA_TVA_DAC VCCA_TVA_DAC VCCA_TVB_DAC VCCA_TVB_DAC VCCA_TVC_DAC VCCA_TVC_DAC
VCCD_CRT VCCD_TVDAC
VCCD_QDAC VCCD_HPLL VCCD_PEG_PLL VCCD_LVDS
VCCD_LVDS
1 2
R576
R576
0R3-0-U-GP
0R3-0-U-GP
4
8 OF 10
8 OF 10
+1.5VS+1.5VS_QDAC
100R2J-2-GP
100R2J-2-GP R115
R115
+1.8V
A LVDS PLL CRT
A LVDS PLL CRT
A PEG
A PEG
LVDS TV/CRT
LVDS TV/CRT
12
C671
C671
POWER
POWER
AXD
AXD
VCC_AXD_NCTF
AXF
AXF
VCC_SM_CK VCC_SM_CK VCC_SM_CK VCC_SM_CK
SM CK
SM CK
VCC_TX_LVDS
HV
HV
TV A CK A SM
TV A CK A SM
PEG
PEG
VCC_RXR_DMI VCC_RXR_DMI
DMI
DMI
VTTLF
VTTLF
CRESTLINE-GP-U
CRESTLINE-GP-U
SC1U10V3KX-3GP
SC1U10V3KX-3GP
VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT
VTT
VTT
VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT
VCC_AXD VCC_AXD VCC_AXD VCC_AXD VCC_AXD VCC_AXD
VCC_AXF VCC_AXF VCC_AXF
VCC_DMI
VCC_HV VCC_HV
VCC_PEG VCC_PEG VCC_PEG VCC_PEG VCC_PEG
VTTLF VTTLF VTTLF
U13 U12 U11 U9 U8 U7 U5 U3 U2 U1 T13 T11 T10 T9 T7 T6 T5 T3 T2 R3 R2 R1
AT23 AU28 AU24 AT29 AT25 AT30
AR29
B23 B21 A21
AJ50
BK24 BK23 BJ24 BJ23
A43
C40 B40
AD51 W50 W51 V49 V50
AH50 AH51
A7 F2 AH1
40mil
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
+VCCP
+1.25VM_AXD
VTTLF1 VTTLF2 VTTLF3
+1.8V_TXLVDS
12
C518
C518
3
ST220U2VBM-3GP
ST220U2VBM-3GP
12
TC1
TC1
12
SCD47U16V3ZY-3GP
SCD47U16V3ZY-3GP
C146
C146
12
SC1U10V3KX-3GP
SC1U10V3KX-3GP
+1.25VS_AXF
+1.25VS_DMI
+1.8V_SM_CK
+1.8V_TXLVDS
+VCC_PEG
20mil
C477
C477
12
12
SCD47U16V3ZY-3GP
SCD47U16V3ZY-3GP
R574
R574
1 2
12
TC23
TC23
ST220U2VBM-3GP
ST220U2VBM-3GP
3
12
C65
C65 SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
12
C88
C88
12
C126
C126 SC10U10V5KX-2GP
SC10U10V5KX-2GP
C43
C43
C483
C483
12
SCD47U16V3ZY-3GP
SCD47U16V3ZY-3GP
0R3-0-U-GP
0R3-0-U-GP
C40
C40
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
1 2
+3VS_HV
SCD47U16V3ZY-3GP
SCD47U16V3ZY-3GP
+1.8V
12
12
C26
C26
0R5J-5-GP
0R5J-5-GP
C513
C513
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
2
+1.25VS_DPLLB
1 2
L32 L-10UH-11-GPL32 L-10UH-11-GP
C560
C560
12
12
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
+1.25VS_DMI
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C559
C559
12
SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
+1.25VM
R75
R75
+1.25VS_PEGPLL
C553
C553
12
SC10U10V5KX-2GP
SC10U10V5KX-2GP
+1.25VS_DPLLA
C552
C552
12
SC10U10V5KX-2GP
SC10U10V5KX-2GP
+VCC_PEG
12
TC15
TC15
ST220U2VBM-3GP
ST220U2VBM-3GP
+VCCP
R596
R596
1 2
0R3-0-U-GP
0R3-0-U-GP
1 2
C545
C545
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C549
C549
12
12
C547
C547
D4
D4
21
SSM5818SLPT-GP
SSM5818SLPT-GP
C557
C557 SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
L29
L29
BLM18PG121SN-1GP
BLM18PG121SN-1GP
12
TC25
TC25
SC10U10V5KX-2GP
SC10U10V5KX-2GP
+3VS
+1.25VS
+1.25VS
+1.25VS
1 2
L28 L-10UH-11-GPL28 L-10UH-11-GP
ST220U2VBM-3GP
ST220U2VBM-3GP
1 2
0R5J-5-GP
0R5J-5-GP
R604
R604
1 2
DY
DY
0R5J-5-GP
0R5J-5-GP
R603
R603
+VCCP_D
R144 10R2J-2-GPR144 10R2J-2-GP
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3 Date: Sheet
Date: Sheet
Date: Sheet
+1.25VS_AXF
12
C486
C486
SC10U10V5KX-2GP
SC10U10V5KX-2GP
+1.8V_SM_CK
C132
C132
C148
C148
12
12
SC10U10V5KX-2GP
SC10U10V5KX-2GP
SC10U10V5KX-2GP
SC10U10V5KX-2GP
+1.5VS_TVDAC
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD022U16V2KX-3GP
SCD022U16V2KX-3GP
+1.25VS
+VCCP
+1.25VS
12
CRESTLINE(4/6)-PWR
CRESTLINE(4/6)-PWR
CRESTLINE(4/6)-PWR
R171
R171
C162
C162
12
+1.25VM_HPLL
C476
C476
SC10U10V5KX-2GP
SC10U10V5KX-2GP
+1.25VM_MPLL
C475
C475
SC10U10V5KX-2GP
SC10U10V5KX-2GP
12
0R2J-2-GP
0R2J-2-GP
C178
C178
12
12
12
+3VS_HV
NORN
NORN
NORN
2
1
R530
R530
1 2
0R3-0-U-GP
0R3-0-U-GP
12
C485
C485 SC1U16V3ZY-GP
SC1U16V3ZY-GP
1 2
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C141
C141
12
R121
R121
1 2
0R3-0-U-GP
0R3-0-U-GP
1 2
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C479
C479
12
1 2
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C478
C478
12
12
C231
C231 SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
+1.25VS
R95 0R5J-5-GPR95 0R5J-5-GP
+1.5VS
L19
L19
BLM18AG121SN-1GP
BLM18AG121SN-1GP
L18
L18
BLM18AG121SN-1GP
BLM18AG121SN-1GP
11
11
11
+1.8V
+1.25VM
+1.25VM
of
of
of
1
A
PV
PV
PV
51Thursday, March 29, 2007
51Thursday, March 29, 2007
51Thursday, March 29, 2007
5
A
www.kythuatvitinh.com
7 OF 10
7 OF 10
U89G
+VCCP
C195 SCD22U10V2KX-1GPC195 SCD22U10V2KX-1GP
C191 SCD22U10V2KX-1GPC191 SCD22U10V2KX-1GP
C202
C202
ST220U2VBM-3GP
ST220U2VBM-3GP
12
12
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
D D
12
TC24
TC24
C184 SCD1U16V2ZY-2GPC184 SCD1U16V2ZY-2GP
12
12
C C
+1.05VM
12
SC10U10V5KX-2GP
SC10U10V5KX-2GP
12
C185
C185
SC10U10V5KX-2GP
SC10U10V5KX-2GP
C183 SCD1U16V2ZY-2GPC183 SCD1U16V2ZY-2GP
C155 SCD1U16V2ZY-2GPC155 SCD1U16V2ZY-2GP
12
12
C161
C161
B B
12
C171
C171
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
C138 SCD1U16V2ZY-2GPC138 SCD1U16V2ZY-2GP
C188
C188
12
12
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
AB33 AB36 AB37 AC33 AC35 AC36 AD35 AD36 AF33 AF36 AH33 AH35 AH36 AH37
AJ33
AJ35 AK33 AK35 AK36 AK37 AD33
AJ36
AM35
AL33
AL35 AA33 AA35 AA36 AP35 AP36 AR35 AR36
AL24
AL26
AL28
AM26 AM28 AM29 AM31 AM32 AM33
AP29 AP31 AP32 AP33
AL29
AL31
AL32 AR31 AR32 AR33
Y32 Y33 Y35 Y36 Y37
T30 T34
T35 U29 U31 U32 U33 U35 U36 V32 V33 V36 V37
U89G
VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF VCC_NCTF
VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF VCC_AXM_NCTF
CRESTLINE-GP-U
CRESTLINE-GP-U
R511
R511
100KR2J-1-GP
100KR2J-1-GP
CRACK_GPIO
VSS NCTF
VSS NCTF
VCC NCTF
VCC NCTF
POWER
POWER
CH751H-40PT-1GP
CH751H-40PT-1GP
+3VS
12
2N7002DW-7F-GP
2N7002DW-7F-GP
4
T27
VSS_NCTF
T37
VSS_NCTF
U24
VSS_NCTF
U28
VSS_NCTF
V31
VSS_NCTF
V35
VSS_NCTF
AA19
VSS_NCTF
AB17
VSS_NCTF
AB35
VSS_NCTF
AD19
VSS_NCTF
AD37
VSS_NCTF
AF17
VSS_NCTF
AF35
VSS_NCTF
AK17
VSS_NCTF
AM17
VSS_NCTF
AM24
VSS_NCTF
AP26
VSS_NCTF
AP28
VSS_NCTF
AR15
VSS_NCTF
AR19
VSS_NCTF
AR28
VSS_NCTF
MCHGND1
A3
VSS_SCB VSS_SCB VSS_SCB VSS_SCB VSS_SCB VSS_SCB
VSS SCBVSS AXM
VSS SCBVSS AXM
VCC_AXM VCC_AXM VCC_AXM VCC_AXM VCC_AXM VCC_AXM VCC_AXM
VSS AXM NCTF
VSS AXM NCTF
+VCCP +3VS
100KR2J-1-GP
100KR2J-1-GP
U83
U83
1 2 3 4
R509
R509
B2 C1 BL1 BL51 A51
AT33 AT31 AK29 AK24 AK23 AJ26 AJ23
6 5
MCHGND2 MCHGND3 MCHGND4 MCHGND5 MCHGND6
D5
D5
12
1 2
R519 0R2J-2-GPR519 0R2J-2-GP
1 2
DY
DY
R56 0R2J-2-GP
R56 0R2J-2-GP
1 2
R518 0R2J-2-GPR518 0R2J-2-GP
1 2
DY
DY
R512 0R2J-2-GP
R512 0R2J-2-GP
1 2
DY
DY
R183 0R2J-2-GP
R183 0R2J-2-GP
1 2
DY
DY
R585 0R2J-2-GP
R585 0R2J-2-GP
+1.05VM
+VCCP_+3VS
KA
CRACK_GPIO
MCHGND6MCHGND4
R151
R151
12
10R2J-2-GP
10R2J-2-GP
R517
R517
100KR2J-1-GP
100KR2J-1-GP
CRACK_GPIO
+3VS
12
U86
U86
1 2 3 4
2N7002DW-7F-GP
2N7002DW-7F-GP
3
C135
C135
12
SC1U10V3KX-3GP
SC1U10V3KX-3GP
R522
R522
100KR2J-1-GP
100KR2J-1-GP
6 5
+1.8V
+VCCP
AT35
AT34 AH28 AC32 AC31
AK32
AJ31
AJ28 AH32 AH31 AH29
AF32
R99
R99
VCC_GMCH1
AU32 AU33 AU35
AV33
AW33 AW35
AY35
BA32
BA33
BA35
BB33 BC32 BC33 BC35 BD32 BD35
BE32
BE33
BE35
BF33
BF34 BG32 BG33 BG35 BH32 BH34 BH35
BJ32
BJ33
BJ34
BK32
BK33
BK34
BK35
BL33 AU30
W13 W14
AA20
AA23
AA26
AA28
AB21
AB24
AB29 AC20 AC21 AC23 AC24 AC26 AC28 AC29 AD20 AD23 AD24 AD28
AF21
AF26
AA31 AH20 AH21 AH23 AH24 AH26 AD31
AJ20 AN14
R30
R20
T14
Y12
1 2
0R3-0-U-GP
0R3-0-U-GP
C194
C194
12
12
TC12
TC12
ST330U2D5VDM-13GP
ST330U2D5VDM-13GP
C110
C110
12
12
TC10
TC10
ST330U2D5VDM-13GP
ST330U2D5VDM-13GP
12
MCHGND5MCHGND2
C192
C192
12
12
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
VCCGFX
C144
C144
12
SC10U10V5KX-2GP
SC10U10V5KX-2GP
CRACK_GPIO 22,31
SC10U10V5KX-2GP
SC10U10V5KX-2GP
C180 SCD01U16V2KX-3GPC180 SCD01U16V2KX-3GP
C93
C93
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
LIB C
6 OF 10
6 OF 10
U89F
U89F
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
VCC CORE
VCC CORE
VCC
POWER
POWER
VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM
VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG VCC_AXG
CRESTLINE-GP-U
CRESTLINE-GP-U
VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF
VCC SM
VCC SM
VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF
VCC GFX NCTF
VCC GFX NCTF
VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF VCC_AXG_NCTF
VCC GFX
VCC GFX
VCC SM LF
VCC SM LF
VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF VCC_SM_LF
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev Custom
Custom
Custom Date: Sheet
Date: Sheet
Date: Sheet
2
VCCGFX
T17 T18 T19 T21 T22 T23 T25 U15 U16 U17 U19 U20 U21 U23 U26 V16 V17 V19 V20 V21 V23 V24 Y15 Y16 Y17 Y19 Y20 Y21 Y23 Y24 Y26 Y28 Y29 AA16 AA17 AB16 AB19 AC16 AC17 AC19 AD15 AD16 AD17 AF16 AF19 AH15 AH16 AH17 AH19 AJ16 AJ17 AJ19 AK16 AK19 AL16 AL17 AL19 AL20 AL21 AL23 AM15 AM16 AM19 AM20 AM21 AM23 AP15 AP16 AP17 AP19 AP20 AP21 AP23 AP24 AR20 AR21 AR23 AR24 AR26 V26 V28 V29 Y31
VCCSM_LF1
AW45
VCCSM_LF2
BC39
VCCSM_LF3
BE39
VCCSM_LF4
BD17
VCCSM_LF5
BD4
VCCSM_LF6
AW8
VCCSM_LF7
AT6
CRESTLINE(5/6)-PWR/GND
CRESTLINE(5/6)-PWR/GND
CRESTLINE(5/6)-PWR/GND
C128
C128
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C74SCD1U16V2ZY-2GP C74SCD1U16V2ZY-2GP
12
12
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
NORN
NORN
NORN
1
C166
C166
C123
C123
12
12
SCD22U10V2KX-1GP
SCD22U10V2KX-1GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
C53SCD22U10V2KX-1GP C53SCD22U10V2KX-1GP
C75SCD1U16V2ZY-2GP C75SCD1U16V2ZY-2GP
12
C200SCD47U16V3ZY-3GP C200SCD47U16V3ZY-3GP
C107SCD22U10V2KX-1GP C107SCD22U10V2KX-1GP
12
12
C239SC1U10V3KX-3GP C239SC1U10V3KX-3GP
C199SC1U10V3KX-3GP C199SC1U10V3KX-3GP
12
12
A
PV
PV
PV
51Friday, March 30, 2007
51Friday, March 30, 2007
51Friday, March 30, 2007
of
of
of
12
12
12
5
A
www.kythuatvitinh.com
U89I
U89I
A13
VSS
A15
VSS
A17
VSS
A24
VSS
D D
C C
B B
AA21 AA24 AA29 AB20 AB23 AB26 AB28 AB31 AC10 AC13
AC39 AC43 AC47
AD21 AD26 AD29
AD41 AD45 AD49
AD50 AE10
AE14 AF20
AF23 AF24 AF31
AG38 AG43 AG47 AG50
AH40 AH41
AJ11 AJ13 AJ21 AJ24 AJ29 AJ32 AJ43 AJ45
AJ49 AK20 AK21 AK26 AK28 AK31 AK51
AM11 AM13
AM41 AM45
AN38 AN39 AN43
AP48 AP50 AR11
AR39 AR44 AR47
AT10 AT14 AT41 AT49
AU23 AU29
AU36 AU49 AU51 AV39 AV48
AW1
AW12 AW16
AC3
AD1
AD3
AD5 AD8
AE6
AG2
AH3
AH7 AH9
AM3 AM4
AN1
AN5 AN7 AP4
AR2
AR7
AU1
AU3
AL1
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
CRESTLINE-GP-U
CRESTLINE-GP-U
5
9 OF 10
9 OF 10
VSS
VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
4
AW24 AW29 AW32 AW5 AW7 AY10 AY24 AY37 AY42 AY43 AY45 AY47 AY50 B10 B20 B24 B29 B30 B35 B38 B43 B46 B5 B8 BA1 BA17 BA18 BA2 BA24 BB12 BB25 BB40 BB44 BB49 BB8 BC16 BC24 BC25 BC36 BC40 BC51 BD13 BD2 BD28 BD45 BD48 BD5 BE1 BE19 BE23 BE30 BE42 BE51 BE8 BF12 BF16 BF36 BG19 BG2 BG24 BG29 BG39 BG48 BG5 BG51 BH17 BH30 BH44 BH46 BH8 BJ11 BJ13 BJ38 BJ4 BJ42 BJ46 BK15 BK17 BK25 BK29 BK36 BK40 BK44 BK6 BK8 BL11 BL13 BL19 BL22 BL37 BL47 C12 C16 C19 C28 C29 C33 C36 C41
4
3
10 OF 10
10 OF 10
U89J
U89J
C46
VSS
C50
VSS
C7
VSS
D13
VSS
D24
VSS
D3
VSS
D32
VSS
D39
VSS
D45
VSS
D49
VSS
E10
VSS
E16
VSS
E24
VSS
E28
VSS
E32
VSS
E47
VSS
F19
VSS
F36
VSS
F4
VSS
F40
VSS
F50
VSS
G1
VSS
G13
VSS
G16
VSS
G19
VSS
G24
VSS
G28
VSS
G29
VSS
G33
VSS
G42
VSS
G45
VSS
G48
VSS
G8
VSS
H24
VSS
H28
VSS
H4
VSS
H45
VSS
J11
VSS
J16
VSS
J2
VSS
J24
VSS
J28
VSS
J33
VSS
J35
VSS
J39
VSS
K12
VSS
K47
VSS
K8
VSS
L1
VSS
L17
VSS
L20
VSS
L24
VSS
L28
VSS
L3
VSS
L33
VSS
L49
VSS
M28
VSS
M42
VSS
M46
VSS
M49
VSS
M5
VSS
M50
VSS
M9
VSS
N11
VSS
N14
VSS
N17
VSS
N29
VSS
N32
VSS
N36
VSS
N39
VSS
N44
VSS
N49
VSS
N7
VSS
P19
VSS
P2
VSS
P23
VSS
P3
VSS
P50
VSS
R49
VSS
T39
VSS
T43
VSS
T47
VSS
U41
VSS
U45
VSS
U50
VSS
V2
VSS
V3
VSS
CRESTLINE-GP-U
CRESTLINE-GP-U
VSS
VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS
W11 W39 W43 W47 W5 W7 Y13 Y2 Y41 Y45 Y49 Y5 Y50 Y11 P29 T29 T31 T33 R28
AA32 AB32 AD32 AF28 AF29 AT27 AV25 H50
3
2
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
CRESTLINE(6/6)-PWR/GND
CRESTLINE(6/6)-PWR/GND
CRESTLINE(6/6)-PWR/GND
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3 Date: Sheet
Date: Sheet
Date: Sheet
NORN
NORN
NORN
2
1
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
51Monday, March 05, 2007
51Monday, March 05, 2007
51Monday, March 05, 2007
of
of
of
13
13
13
1
PV
PV
PV
A
5
www.kythuatvitinh.com
DDR_A_DQS#[0..7]9
DDR_A_D[0..63]9 DDR_A_DM[0..7]9 DDR_A_DQS[0..7]9 DDR_A_MA[0..13]9
C118
C118
C120
C120
SC2D2U10V3ZY-1GP
SC2D2U10V3ZY-1GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C60
C60
12
C80
C80
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1 23
1 23
1 23
1 23
1 23
1 23
1 23
DDR_A_BS[0..2]9
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C69
C69
12
DDR_A_BS2 DDR_CKE0_DIMMA
DDR_A_MA7 DDR_A_MA6
DDR_A_MA12 DDR_A_MA9
DDR_A_MA0 DDR_A_MA4
DDR_A_RAS# DDR_CS0_DIMMA#
M_ODT0
DDR_A_MA11 DDR_A_MA2
D D
C C
B B
A A
Layout Note: Place near DM1
+1.8V
12
12
12
Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9VS
+0.9V
12
DDR_A_MA8 DDR_A_MA5
DDR_A_MA3 DDR_A_MA1
DDR_A_MA13 DDR_A_BS1
DDR_A_MA10 DDR_A_BS0
DDR_A_WE# DDR_A_CAS#
DDR_CS1_DIMMA# M_ODT1
DDR_A_MA14 DDR_CKE1_DIMMA
C37
C37
C76
C76
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SC2D2U10V3ZY-1GP
SC2D2U10V3ZY-1GP
C55
C55
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
RN19 SRN56J-4-GPRN19 SRN56J-4-GP
RN16 SRN56J-4-GPRN16 SRN56J-4-GP
RN12 SRN56J-4-GPRN12 SRN56J-4-GP
RN13 SRN56J-4-GPRN13 SRN56J-4-GP
RN10 SRN56J-4-GPRN10 SRN56J-4-GP
RN7 SRN56J-4-GPRN7 SRN56J-4-GP
RN27 SRN56J-4-GPRN27 SRN56J-4-GP
5
C134
C134
SC2D2U10V3ZY-1GP
SC2D2U10V3ZY-1GP
12
1 2 3
1 2 3
1 2 3
1 2 3
1 2 3
1 2 3
1 2 3
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
+0.9V
C38
C38
C113
C113
12
12
SC2D2U10V3ZY-1GP
SC2D2U10V3ZY-1GP
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
RN25 SRN56J-4-GPRN25 SRN56J-4-GP
4
RN21 SRN56J-4-GPRN21 SRN56J-4-GP
4
RN22 SRN56J-4-GPRN22 SRN56J-4-GP
4
RN18 SRN56J-4-GPRN18 SRN56J-4-GP
4
RN15 SRN56J-4-GPRN15 SRN56J-4-GP
4
RN9 SRN56J-4-GPRN9 SRN56J-4-GP
4
RN24 SRN56J-4-GPRN24 SRN56J-4-GP
4
C106
C106
SC2D2U10V3ZY-1GP
SC2D2U10V3ZY-1GP
C41
C41
C97
C97
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
4
4
4
4
4
4
4
4
DDR_A_MA149
TC11
C95
C95
C89
C89
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C51
C51
C136
C136
12
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
4
TC11
C63
C63
12
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C96
C96
C108
C108
12
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
Layout Note: Place these resistors closely DM1,all trace length Max=1.5"
ST470U2D5VDM-LGP
ST470U2D5VDM-LGP
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
TC28
TC28
12
DY
DY
C44
C44
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
V_DDR_MCH_REF
ST220U2VBM-3GP
ST220U2VBM-3GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
V_DDR_MCH_REF
C228
C228
3
DM1
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14
DDR_A_BS2 DDR_A_DM0 DDR_A_BS0
DDR_A_BS1 DDR_A_D0
DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63
DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7
DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7
M_ODT08 M_ODT18
M_ODT0 M_ODT1
12
12
C226
C226
SC2D2U16V5ZY-2GP
SC2D2U16V5ZY-2GP
DM1
102
A0
101
A1
100
A2
99
A3
98
A4
97
A5
94
A6
92
A7
93
A8
91
A9
105
A10/AP
90
A11
89
A12
116
A13
86
A14
84
A15
85
A16/BA2
107
BA0
106
BA1
5
DQ0
7
DQ1
17
DQ2
19
DQ3
4
DQ4
6
DQ5
14
DQ6
16
DQ7
23
DQ8
25
DQ9
35
DQ10
37
DQ11
20
DQ12
22
DQ13
36
DQ14
38
DQ15
43
DQ16
45
DQ17
55
DQ18
57
DQ19
44
DQ20
46
DQ21
56
DQ22
58
DQ23
61
DQ24
63
DQ25
73
DQ26
75
DQ27
62
DQ28
64
DQ29
74
DQ30
76
DQ31
123
DQ32
125
DQ33
135
DQ34
137
DQ35
124
DQ36
126
DQ37
134
DQ38
136
DQ39
141
DQ40
143
DQ41
151
DQ42
153
DQ43
140
DQ44
142
DQ45
152
DQ46
154
DQ47
157
DQ48
159
DQ49
173
DQ50
175
DQ51
158
DQ52
160
DQ53
174
DQ54
176
DQ55
179
DQ56
181
DQ57
189
DQ58
191
DQ59
180
DQ60
182
DQ61
192
DQ62
194
DQ63
11
/DQS0
29
/DQS1
49
/DQS2
68
/DQS3
129
/DQS4
146
/DQS5
167
/DQS6
186
/DQS7
13
DQS0
31
DQS1
51
DQS2
70
DQS3
131
DQS4
148
DQS5
169
DQS6
188
DQS7
114
ODT0
119
ODT1
1
VREF
2
VSS
202
GND
DDR2-200P-12-GP-U1
DDR2-200P-12-GP-U1
NC#163/TEST
SO-DIMM 1 REVERSE Foxcon Black
62.10017.E11
3
/RAS /CAS /CS0
/CS1
CKE0 CKE1
/CK0
/CK1
DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7
SDA SCL
VDDSPD
NC#50 NC#69 NC#83
NC#120
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
GND
2
DDR_A_RAS#
108
DDR_A_WE#
109
/WE
CK0
CK1
SA0 SA1
113 110
115 79
80 30
32 164
166 10
26 52 67 130 147 170 185
195 197
199 198
200 50
69 83 120 163
81 82 87 88 95 96 103 104 111 112 117 118
3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54 59 60 65 66 71 72 77 78 121 122 127 128 132 133 138 139 144 145 149 150 155 156 161 162 165 168 171 172 177 178 183 184 187 190 193 196
201
DDR_A_CAS# DDR_CS0_DIMMA#
DDR_CS1_DIMMA# DDR_CKE0_DIMMA
DDR_CKE1_DIMMA M_CLK_DDR0
M_CLK_DDR#0 M_CLK_DDR1
M_CLK_DDR#1
DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7
ICH_SMBDATA ICH_SMBCLK
DM1_SA0 DM1_SA1
2
1 2 1 2
+1.8V
DDR_A_RAS# 9
DDR_A_WE# 9
DDR_A_CAS# 9 DDR_CS0_DIMMA# 8
DDR_CS1_DIMMA# 8
DDR_CKE0_DIMMA 8
DDR_CKE1_DIMMA 8 M_CLK_DDR0 8
M_CLK_DDR#0 8 M_CLK_DDR1 8
M_CLK_DDR#1 8
ICH_SMBDATA 15,16,21 ICH_SMBCLK 15,16,21
R10
R10 10KR2J-3-GP
10KR2J-3-GP R4
R4 10KR2J-3-GP
10KR2J-3-GP
PM_EXTTS#0 8
<Variant Name>
<Variant Name>
<Variant Name>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev Custom
Custom
Custom Date: Sheet
Date: Sheet
Date: Sheet
C2
SCD1U16V2ZY-2GPC2SCD1U16V2ZY-2GP
DDRII-SODIMM SLOT1
DDRII-SODIMM SLOT1
DDRII-SODIMM SLOT1
1
+3VM
12
12
C1
C1 SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
NORN
NORN
NORN
14 51Friday, March 30, 2007
14 51Friday, March 30, 2007
14 51Friday, March 30, 2007
1
PV
PV
PV
of
of
of
5
www.kythuatvitinh.com
DDR_B_DQS#[0..7]9
DDR_B_D[0..63]9 DDR_B_DM[0..7]9 DDR_B_DQS[0..7]9
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
+0.9V
DDR_B_MA[0..13]9
DDR_B_BS[0..2]9
C99
C99
12
12
12
C48
C48
C121
C121
SC2D2U10V3ZY-1GP
SC2D2U10V3ZY-1GP
C127
C127
12
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
RN29
RN29
4
RN14
RN14
4
RN17
RN17
4
RN28
RN28
4
RN20
RN20
4
RN4
RN4
4
RN31
RN31
4
SRN56J-4-GP
SRN56J-4-GP
C112
C112
SC2D2U10V3ZY-1GP
SC2D2U10V3ZY-1GP
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C101
C101
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
DDR_B_MA9
1
DDR_B_MA12
23
SRN56J-4-GP
SRN56J-4-GP
DDR_B_MA3
1
DDR_B_MA1
23
SRN56J-4-GP
SRN56J-4-GP
DDR_B_MA7
1
DDR_B_MA6
23
SRN56J-4-GP
SRN56J-4-GP
DDR_B_MA4
1
DDR_B_MA2
23
SRN56J-4-GP
SRN56J-4-GP
DDR_B_WE#
1
DDR_B_MA10
23
SRN56J-4-GP
SRN56J-4-GP
DDR_B_MA5M_ODT2
1
DDR_B_MA8
23
SRN56J-4-GP
SRN56J-4-GP
DDR_B_BS2
1
DDR_CKE2_DIMMB
23
C90
C90
D D
C C
B B
A A
Layout Note: Place near DM2
+1.8V
12
12
12
5
C122
C122
SC2D2U10V3ZY-1GP
SC2D2U10V3ZY-1GP
C173
C173
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1 2 3
1 2 3
1 2 3
1 2 3
1 2 3
1 2 3
1 2 3
C156
C156
12
C42
C42
SC2D2U10V3ZY-1GP
SC2D2U10V3ZY-1GP
C142
C142
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
4
4
4
4
4
4
4
C81
C81
SC2D2U10V3ZY-1GP
SC2D2U10V3ZY-1GP
Layout Note: Place one cap close to every 2 pullup resistors terminated to +0.9VS
+0.9V
C23
C23
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
RN8 SRN56J-4-GPRN8 SRN56J-4-GP
DDR_B_MA0 DDR_B_BS1
RN11 SRN56J-4-GPRN11 SRN56J-4-GP
M_ODT3 DDR_CS3_DIMMB#
RN26 SRN56J-4-GPRN26 SRN56J-4-GP
DDR_B_MA14 DDR_B_MA11
RN6 SRN56J-4-GPRN6 SRN56J-4-GP
DDR_B_CAS#
DDR_B_BS0
RN23 SRN56J-4-GPRN23 SRN56J-4-GP
DDR_CKE3_DIMMB
RN3 SRN56J-4-GPRN3 SRN56J-4-GP
DDR_B_MA13
RN5 SRN56J-4-GPRN5 SRN56J-4-GP
DDR_B_RAS# DDR_CS2_DIMMB#
4
DDR_B_MA149
C66
C66
C100
C100
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C72
C72
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C70
C70
12
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C45
C45
C62
C62
12
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
V_DDR_MCH_REF
4
C27
C27
C35
C35
12
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
Layout Note: Place these resistors closely DM2,all trace length Max=1.5"
V_DDR_MCH_REF
M_ODT38
C263
C263
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
M_ODT28
12
3
DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14
DDR_B_BS2 DDR_B_BS0
DDR_B_BS1
DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63
DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7
DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7
M_ODT2 M_ODT3
SC2D2U16V5ZY-2GP
SC2D2U16V5ZY-2GP
12
C257
C257
3
MH1
102
A0
101
A1
100
A2
99
A3
98
A4
97
A5
94
A6
92
A7
93
A8
91
A9
105
A10/AP
90
A11
89
A12
116
A13
86
A14
84
A15
85
A16/BA2
107
BA0
106
BA1
5
DQ0
7
DQ1
17
DQ2
19
DQ3
4
DQ4
6
DQ5
14
DQ6
16
DQ7
23
DQ8
25
DQ9
35
DQ10
37
DQ11
20
DQ12
22
DQ13
36
DQ14
38
DQ15
43
DQ16
45
DQ17
55
DQ18
57
DQ19
44
DQ20
46
DQ21
56
DQ22
58
DQ23
61
DQ24
63
DQ25
73
DQ26
75
DQ27
62
DQ28
64
DQ29
74
DQ30
76
DQ31
123
DQ32
125
DQ33
135
DQ34
137
DQ35
124
DQ36
126
DQ37
134
DQ38
136
DQ39
141
DQ40
143
DQ41
151
DQ42
153
DQ43
140
DQ44
142
DQ45
152
DQ46
154
DQ47
157
DQ48
159
DQ49
173
DQ50
175
DQ51
158
DQ52
160
DQ53
174
DQ54
176
DQ55
179
DQ56
181
DQ57
189
DQ58
191
DQ59
180
DQ60
182
DQ61
192
DQ62
194
DQ63
11
DQS0#
29
DQS1#
49
DQS2#
68
DQS3#
129
DQS4#
146
DQS5#
167
DQS6#
186
DQS7#
13
DQS0
31
DQS1
51
DQS2
70
DQS3
131
DQS4
148
DQS5
169
DQS6
188
DQS7
114
OTD0
119
OTD1
1
VREF
2
VSS
202
GND MH1
DM2
DM2
DDR2-200P-20-GP-U
DDR2-200P-20-GP-U
SO-DIMM 2 STANDARD
RAS#
WE#
CAS# CS0#
CS1# CKE0
CKE1
CK0#
CK1#
DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7
VDDSPD
NC#50 NC#69 NC#83
NC#120
NC#163/TEST
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
GND MH2
CK0
CK1
SDA SCL
SA0 SA1
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
108 109 113
110 115
79 80
30 32
164 166
10 26 52 67 130 147 170 185
195 197
199 198
200 50
69 83 120 163
81 82 87 88 95 96 103 104 111 112 117 118
3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54 59 60 65 66 71 72 77 78 121 122 127 128 132 133 138 139 144 145 149 150 155 156 161 162 165 168 171 172 177 178 183 184 187 190 193 196
201 MH2
2
2
DDR_B_RAS# DDR_B_WE# DDR_B_CAS#
DDR_CS2_DIMMB# DDR_CS3_DIMMB#
DDR_CKE2_DIMMB DDR_CKE3_DIMMB
M_CLK_DDR2 M_CLK_DDR#2
M_CLK_DDR3 M_CLK_DDR#3
DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7
ICH_SMBDATA ICH_SMBCLK
DM2_SA0 DM2_SA1
+1.8V
1
DDR_B_RAS# 9
DDR_B_WE# 9
DDR_B_CAS# 9 DDR_CS2_DIMMB# 8
DDR_CS3_DIMMB# 8 DDR_CKE2_DIMMB 8
DDR_CKE3_DIMMB 8 M_CLK_DDR2 8
M_CLK_DDR#2 8 M_CLK_DDR3 8
M_CLK_DDR#3 8
ICH_SMBDATA 14,16,21
ICH_SMBCLK 14,16,21
R9
R9 10KR2J-3-GP
10KR2J-3-GP
1 2
R8
R8
1 2
10KR2J-3-GP
10KR2J-3-GP
<Variant Name>
<Variant Name>
<Variant Name>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev Custom
Custom
Custom Date: Sheet
Date: Sheet
Date: Sheet
+3VM
PM_EXTTS#1 8
DDRII-SODIMM SLOT2
DDRII-SODIMM SLOT2
DDRII-SODIMM SLOT2
12
C16
C16
12
C17
C17 SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Norn
Norn
Norn
1
+3VM
PV
PV
PV
of
of
of
15 51Friday, March 30, 2007
15 51Friday, March 30, 2007
15 51Friday, March 30, 2007
A
+3VM +3VM_CK505
www.kythuatvitinh.com
L10
L10
1 2
MLB-160808-18-GP
MLB-160808-18-GP
12
C262
C262
SC1U10V3KX-3GP
SC1U10V3KX-3GP
5
12
12
12
C260
C260
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
C318
C318
12
C261
C261
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
12
C310
C310
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C276
C276
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C303
C303
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C328
C328
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
D D
4
12
C288
C288
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
CLK_XTAL_IN
1 2
X-14D31818M-40GP
X-14D31818M-40GP
12
C293
C293 SC33P50V2JN-3GP
SC33P50V2JN-3GP
X2
X2
CLK_XTAL_OUT
12
C285
C285 SC33P50V2JN-3GP
SC33P50V2JN-3GP
3
+1.25VM_CK505+3VM_CK505
U34
U34
46
62
23
4
9
16
19
33
43
52
56
27
2
1
+1.25VM +1.25VM_CK505
L8
L8
1 2
MLB-160808-18-GP
MLB-160808-18-GP
12
C211
C211
SC1U10V3KX-3GP
SC1U10V3KX-3GP
12
12
C212
C212
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
C329
C329
12
C327
C327
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
12
12
C325
C325
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C322
C322
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C277
C277
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C C
CLKSATAREQ#21
CLKREQ#_B8
CLK_DEBUG_PORT26,30
CLK_PCI_TCG30 CLK_PCI_EC31 CLK_PCI_ICH19 CLK_R5C83347
CLK_14M_ICH21 CLK_14M_KBC31
+3VS
12
R279
R279 10KR2J-3-GP
10KR2J-3-GP
PCI2_TME
ITP_EN
12
R280
R280 10KR2J-3-GP
10KR2J-3-GP
DY
DY
ITP_EN Output
0 SRC8 1 CPU_ITP
B B
+3VS
12
R309
R309 10KR2J-3-GP
10KR2J-3-GP
12
R315
R315 10KR2J-3-GP
10KR2J-3-GP
DY
DY
12
12
12
C317SC4D7P50V2CN-1GP C317SC4D7P50V2CN-1GP
C309SC4D7P50V2CN-1GP C309SC4D7P50V2CN-1GP
CPU_BSEL06 CPU_BSEL16 CPU_BSEL26
Design Note:
1. All of Input pin didn't have internal pull up resistor.
2. Clock Request (CR) function are enable by registers.
3. CY28548 integrated serial resistor of differential clock, so put 0 ohm serial resistor in the schematic.
5
CLK_48M_ICH21
C273
C273
SC10U10V5KX-2GP
SC10U10V5KX-2GP
12
12
12
C342SC4D7P50V2CN-1GP C342SC4D7P50V2CN-1GP
C313SC4D7P50V2CN-1GP C313SC4D7P50V2CN-1GP
C320SC4D7P50V2CN-1GP C320SC4D7P50V2CN-1GP
1 2
R830 0R2J-2-GPR830 0R2J-2-GP
1 2
R831 0R2J-2-GPR831 0R2J-2-GP
1 2
R832 0R2J-2-GPR832 0R2J-2-GP
4
C343 SC4D7P50V2CN-1GPC343 SC4D7P50V2CN-1GP
1 2
H_STP_PCI#21 H_STP_CPU#21
ICH_SMBCLK14,15,21
ICH_SMBDATA14,15,21
CK_PWRGD21
0322 PV
R264
R264
1 2
R270
R270
1 2
R265
R265
1 2
R281 0R2J-2-GPR281 0R2J-2-GP
1 2
R284 22R2J-2-GPR284 22R2J-2-GP
1 2
R313
R313
1 2
R274 22R2J-2-GPR274 22R2J-2-GP
1 2
R260 22R2J-2-GPR260 22R2J-2-GP
R257 22R2J-2-GPR257 22R2J-2-GP
12
C301SC4D7P50V2CN-1GP C301SC4D7P50V2CN-1GP
C306SC4D7P50V2CN-1GP C306SC4D7P50V2CN-1GP
1 2
R314 33R2J-2-GPR314 33R2J-2-GP
33R2J-2-GP
33R2J-2-GP 33R2J-2-GP
33R2J-2-GP 33R2J-2-GP
33R2J-2-GP
33R2J-2-GP
33R2J-2-GP
1 2
1 2
+VCCP +VCCP +VCCP
R827
R827
DY
DY
1KR2J-1-GP
1KR2J-1-GP
1 2
R833
R833
DY
DY
0R2J-2-GP
0R2J-2-GP
1 2
DY
DY
1KR2J-1-GP
1KR2J-1-GP
1 2
DY
DY
1 2
CLK_XTAL_IN CLK_XTAL_OUT
FSA
CLKSATAREQ#_U3 CLKREQ#_B_U3
CLK_PCI_TCG_U3
R828
R828
R834
R834 0R2J-2-GP
0R2J-2-GP
PCI2_TME 27_SEL
ITP_EN
FSB FSC
ICS9LPRS355AKLFT-GP
ICS9LPRS355AKLFT-GP
12
R829
R829
DY
DY
56R2J-4-GP
56R2J-4-GP
R835
R835
DY
DY
1KR2J-1-GP
1KR2J-1-GP
1 2
VDD48
VDDPCI
VDDREF
3
X1
2
X2
17
USB_48MHZ/FSLA
45
PCI_STOP#
44
CPU_STOP#
7
SCLK
6
SDATA
63
CK_PWRGD/PD#
8
PCI0/CR#_A
10
PCI1/CR#_B
11
PCI2/TME
12
PCI3
13
PCI4/27_SELECT
14
PCI_F5/ITP_EN
64
FSLB/TEST_MODE
5
REF0/FSLC/TEST_SEL
55
NC#55
GNDREF
GNDPCI
GND48
1
15
18
FS_C FS_B FS_A CPU
1 0 1 100M 0 0 1 133M 0 1 0 200M 0 1 1 166M
1 2
R195 2K2R2J-2-GPR195 2K2R2J-2-GP
1 2
R197 0R2J-2-GPR197 0R2J-2-GP
1 2
R196 10KR2J-3-GPR196 10KR2J-3-GP R167 1KR2J-1-GPR167 1KR2J-1-GP
1 2
R169 1KR2J-1-GPR169 1KR2J-1-GP
1 2
R168 1KR2J-1-GPR168 1KR2J-1-GP
1 2
3
VDDSRC
VDDCPU
VDDPLL3
GND
22
GNDSRC
GNDSRC
30
36
GNDSRC
49
VDD96_IO
VDDSRC_IO
VDDSRC_IO
VDDSRC_IO
VDDCPU_IO
VDDPLL3_IO
27MHZ_NONSS/SRCT1/SE1
27MHZ_SS/SRCC1/SE2
GND
GNDCPU
GND
26
59
65
FSA FSB FSC
MCH_CLKSEL0 8 MCH_CLKSEL1 8 MCH_CLKSEL2 8
CPUT0 CPUC0
CPUT1_F CPUC1_F
CPUT2_ITP/SRCT8
CPUC2_ITP/SRCC8
SRCT7/CR#_F
SRCC7/CR#_E
SRCT6 SRCC6
SRCT10
SRCC10
SRCT11/CR#_H
SRCC11/CR#_G
SRCT9 SRCC9
SRCT4 SRCC4
SRCT3/CR#_C
SRCC3/CR#_D
SRCT2/SATAT
SRCC2/SATAC
SRCT0/DOTT_96
SRCC0/DOTC_96
+3VS
12
R303
R303 10KR2J-3-GP
10KR2J-3-GP
DY
DY
12
R287
R287 10KR2J-3-GP
10KR2J-3-GP
SRN0J-6-GP
61 60
58 57
54 53
51 50
48 47
41 42
40 39
37 38
34 35
31 32
28 29
24 25
20 21
27_SEL
CPUT0
RN35
RN35
CPUC0 CPUT1
CPUC1 SRCT8
SRCC8
SRCT10 SRCC10
SRCT9 SRCC9
SRCT4 SRCC4
SRCT3 SRCC3
SRCT1 SRCC1
SRCT0 SRCC0
1 2 3
RN36
RN36
1 2 3
RN37
RN37
1 2 3
RN43
RN43
2 3 1
RN47
RN47
2 3 1
RN49
RN49
2 3 1
RN52
RN52
2 3 1
RN54 SRN0J-6-GPRN54 SRN0J-6-GP
2 3 1
RN53 SRN0J-6-GPRN53 SRN0J-6-GP
2 3 1
SRN0J-6-GP
4
SRN0J-6-GP
SRN0J-6-GP
4
SRN0J-6-GP
SRN0J-6-GP
4
0322 PV
4
SRN0J-6-GP
SRN0J-6-GP
1 2
R262 10KR2J-3-GPR262 10KR2J-3-GP R267
R267
1 2
4
SRN33J-5-GP-U
SRN33J-5-GP-U
4
SRN0J-6-GP
SRN0J-6-GP
4
SRN0J-6-GP
SRN0J-6-GP
4
4
10KR2J-3-GP
10KR2J-3-GP
CLK_CPU_BCLK 5 CLK_CPU_BCLK# 5
CLK_MCH_BCLK 8 CLK_MCH_BCLK# 8
CLK_CPU_XDP 5 CLK_CPU_XDP# 5
CLK_PCIE_NEW 23 CLK_PCIE_NEW# 23
+3VS
NEWCARD_CLKREQ# 23 CLKREQ#_G 26
+3VS
CLK_PCIE_MCARD 26 CLK_PCIE_MCARD# 26
CLK_MCH_3GPLL 8 CLK_MCH_3GPLL# 8
CLK_PCIE_ICH 21 CLK_PCIE_ICH# 21
MCH_SSCDREFCLK 8 MCH_SSCDREFCLK# 8
CLK_MCH_DREFCLK 8 CLK_MCH_DREFCLK# 8
27_SEL PIN 20 PIN 21 PIN 24 PIN 25
0 DOT96T DOT96C SRCT1/LCDT_100 SRCT1/LCDT_100 1 SRCT0 SRCC0 27M_NSS 27M_SS
<Variant Name>
<Variant Name>
<Variant Name>
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev A3
A3
A3 Date: Sheet
Date: Sheet
Date: Sheet
Clock generator CY28548
Clock generator CY28548
Clock generator CY28548
2
Taipei Hsien 221, Taiwan, R.O.C.
NORN
NORN
NORN
1
16 51Friday, March 30, 2007
16 51Friday, March 30, 2007
16 51Friday, March 30, 2007
A
PV
PV
PV
of
of
of
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