HP DV2000 INTEL 945 Schematics
NMC
5
4
3
2
1
KAI Block Diagram
Project code : 91.4F601.001
D D
CLK GEN
ICS954305
3
Intel CPU
Yonah/Merom
4,5
Host BUS
533/667MHz
DDRII
533/667
DDRII
533/667
C C
1394
23
SD/SDIO/MMC
MS/MS Pro/xD
23
1394
CardReader
Slot 0
Slot 1
Ricoh
R5C832
11
11
22,23
DDRII 667 Channel A
DDR II 667 Channel B
PCI
Calistoga
PM
6,7,8,9,10
DMI I/F
100MHz
PCIE x 16
PCB P/N : 05233
Revision : 1
nVIDIA
G72M-Z G3-64
38,39,40
RGB CRT
LVDS
SVIDEO
CRT
LCD
TVOUT
CAMERA
BLUE
TOOTH
13
14
13
30
30
SYSTEM DC/DC
TPS51120
INPUTS
DCBATOUT
OUTPUTS
5V_S5
3V_S5
SYSTEM DC/DC
MAX8743
INPUTS
DCBATOUT
OUTPUTS
1D05V_S0
1D8V_S3
MAXIM CHARGER
MAX8725
INPUTS
OUTPUTS
BT+
DCBATOUT
18V 3.0A
5V 100mA
CPU DC/DC
MAX8736ETL
RJ45
CONN
26 25
10/100 NIC
Intel 82562
LCI
USB 2.0
ICH7-M
SATA
USB x 3
HDD
21
INPUTS
OUTPUTS
VCC_CORE
20
DCBATOUT
0.844~1.3V
44A
PATA
B B
RJ11
MODEM
CONN
INTERNAL
ARRAY MIC
MIC IN
LINE OUT
AMOM
WAKIKI
AUDIO CODEC
27
SPDIF
OP AMP
A A
APA2031
28
2CH
SPEAKER
CRT LINE OUTMIC IN S/PDIF TVOUT
HD Audio
Ricoh
R5538
26
New Card
PCIE+USB 2.0
26
DOCK
PCIE x 1
Mini-Card
802.11a/b/g
24
15,16,17,18
PCIE x 1
USB 2.0 x 1
Mini-Card
10/100
Ethernet
LPC Bus
KBC
ENE KB3910SF
Capacity
24
Button
CIR
Touch
Pad
15
Int.
KB
30 30 19
29
CIR
30
Thermal
& Fan
G792
5
4
3
2
ODD
20
Flash ROM
1MB
31
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
PCB LAYER
L1:
Signal 1
L2:
GND
Signal 2
L3:
L4:
Signal 3
VCC
L5:
L6:
Signal 4
L7:
GND
L8:
Signal 5
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Block Diagram
Block Diagram
Block Diagram
KAI 1
KAI 1
KAI 1
144Wednesday, April 19, 2006
144Wednesday, April 19, 2006
144Wednesday, April 19, 2006
1
of
of
of
NMC
A
B
C
D
E
Calistoga Strapping Signals and
Configuration
Pin Name
CFG[2:0]
CFG[4:3]
4 4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG[11:10] Reserved
CFG[13:12]
CFG[15:14]
CFG16
CFG17
CFG18
3 3
CFG19
CFG20
SDVOCRTL
_DATA
All strap signals are sampled with respect to the leading
NOTE:
edge of the Alviso GMCH PWORK In signal.
Strap Description
FSB Frequency Select
Reserved
DMI x2 Select
CPU Strap
Reserved
PCI Express Graphics
Lane Reversal
Reserved
Reserved
FSB Dynamic ODT
Global R-comp Disable
(All R-comps)
VCC Select
DMI Lane Reversal
SDVO/PCIE
Concurrent
SDVO Present
Configuration
001 = FSB533
011 = FSB667
others = Reserved
0 = DMI x2
1 = DMI x4
0=Moby Dick
1=Calistoga
0 = Reserved
1 =Mobile CPU(Default)
0 = Reverse Lanes,15->0,14->1 ect..
1= Normal operation(Default):Lane
Numbered in order
0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled
0 = All R-comp Disable
1 = Normal Operation (Default)
0 = 1.05V
1 = 1.5V
0 = Normal operation (Default):lane
Numbered in order
1 =Reverse Lane,4->0,3->1 ect...
0 = Only SDVO or PCIE x1 is
operational (Default)
1 =SDVO and PCIE x1 are operating
simultaneously via the PEG port
0 = No SDVO device present
1= SDVO device present
(Default)
(Default)
page 7 page 3
(Default)
ICS954305 Spread Spectrum Select
SS3 SS2 SS1 SS0 Spread Amount%
000
0000
0
0
0
1
0
1
0
0
1
0
11
0
1 +/-0.25
1
00
1
001
0
1
1
1
1
1
1
11
11
0
1
1
0
1
1
0
0
0
1
1
0
1
0
0
1
0
1
1
0
0
1
0
1
1
-0.5
-1.0
-1.5
-2.0
-0.75
-1.25
-1.75
-2.25
+/-0.5
+/-0.75
+/-1.0
+/-0.25
+/-0.5
+/-0.75
+/-1.0
PCI Routing
REQ/GNTIDSEL
IRQ
R5C832
(Default)
25 0
ICH7M Integrated Pull-up
and Pull-down Resistors
ACZ_BIT_CLK,
EE_DOUT,
GNT[6]#/GPO[16],
LAD[3:0]#/FB[3:0]#, LDRQ[0],
PME#, PWRBTN#,
LAN_RXD[2:0]
ACZ_RST#, ACZ_SDIN[2:0], ACZ_SYNC,
ACZ_SDOUT,ACZ_BITCLK,
SPKR,
USB[7:0][P,N]
DD[7],
LAN_CLK
DPRSLP#, EE_DIN,
GNT[5]#/GPO[17],
TP[3]
EE_CS,
SDDREQ
LDRQ[1]/GPI[41],
DPRSLPVR,
ICH6 internal 20K pull-ups
ICH6 internal 10K pull-ups
ICH6 internal 20K pull-downs
ICH6 internal 15K pull-downs
ICH6 internal 11.5K pull-downs
ICH6 internal 100K pull-downs
ICH6-M EDS 14308 0.8V1
ICH7M IDE Integrated Series
Termination Resistors
DD[15:0],
DDACK#,
DCS3#,
IORDY,
IDEIRQ
DIOR#, DREQ,DIOW#,
DA[2:0],
DCS1#,
approximately 33 ohm
R72
R72
54D9R2F-L1-GP
54D9R2F-L1-GP
3D3V_S0
12
R73
R73
220R2J-L2-GP
220R2J-L2-GP
1D05V_S0
12
1D05V_S0
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
12
R66
R66
39D2R2F-L-GP
R68
R68
54D9R2F-L1-GP
54D9R2F-L1-GP
R69 22D6R2F-L1-GP
R69 22D6R2F-L1-GP
DY
DY
1 2
DY
DY
1 2
R71 22D6R2F-L1-GP
R71 22D6R2F-L1-GP
XDP_BPM#54
XDP_BPM#44
XDP_BPM#04
XDP_BPM#14
XDP_BPM#24
XDP_BPM#34
C105
C105
DY
DY
39D2R2F-L-GP
TDO_FLEX#
RESET_FLEX#
12
CLK_XDP#
CLK_XDP
CN1
CN1
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
30
MLX-CON28-U
MLX-CON28-U
DY
DY
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
ITP
ITP
ITP
KAI -1
KAI -1
KAI -1
244Thursday, April 13, 2006
244Thursday, April 13, 2006
244Thursday, April 13, 2006
of
of
of
History
2 2
11.18.2004: mini card not ready
1 1
ITP Debug Conn.
XDP_TDI4
XDP_TMS4
XDP_TRST#4
XDP_TCK4
XDP_TDO4
CLK_XDP#3
CLK_XDP3
H_CPURST#4,6
12
12
R67
R67
680R2J-3-GP
680R2J-3-GP
XDP_TCK
R70
R70
27D4R2F-L1-GP
27D4R2F-L1-GP
XDP_DBRESET#4,17
NMC
A
3D3V_S0 3D3V_S03D3V_S0
1 2
R439 0R3-0-U-GPR439 0R3-0-U-GP
SC4D7U10V5ZY-3GP
SC4D7U10V5ZY-3GP
3D3V_S0
4 4
12
R146
R146
10KR2J-3-GP
10KR2J-3-GP
12
R148
R148
10KR2J-3-GP
10KR2J-3-GP
DY
DY
3 3
CONN_CLKREQ#26
3D3V_APWR_S0 3D3V_CLKGEN_S03D3V_48MPWR_S0
12
C334
C334
12
R149
R149
10KR2J-3-GP
10KR2J-3-GP
H/L : CPU_ITP/SRC10
ITP_EN
SS_SEL
H/L: 27MHz/96MHz
12
R147
R147
10KR2J-3-GP
10KR2J-3-GP
DY
DY
CLK48_ICH17
3D3V_S0
12
12
CPU_SEL0
R169
R169
10KR2J-3-GP
10KR2J-3-GP
1 2
R168 0R2J-2-GPR168 0R2J-2-GP
VGA_27MHZSS40
C311
C311
X-14D31818M-30GP
X-14D31818M-30GP
C313 SC39P50V2JN-1GPC313 SC39P50V2JN-1GP
C333
C333
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
IN
(3D3V_S0)
CLKREQ2#
VGA_27MHZ40
SC27P50V2JN-2-GP
SC27P50V2JN-2-GP
1 2
1 2
1 2
R171 0R3-0-U-GPR171 0R3-0-U-GP
SC4D7U10V5ZY-3GP
SC4D7U10V5ZY-3GP
EN
(6218_PGOOD)
H
X
12
R4262K2R2J-2-GP R4262K2R2J-2-GP
R423 33R2J-2-GPR423 33R2J-2-GP
R430 1KR2J-1-GP
R430 1KR2J-1-GP
R170 1KR2J-1-GP
R170 1KR2J-1-GP
R153 1KR2J-1-GP
R153 1KR2J-1-GP
R431 1KR2J-1-GP
R431 1KR2J-1-GP
R152 1KR2J-1-GP
R152 1KR2J-1-GP
R433 1KR2J-1-GP
R433 1KR2J-1-GP
R150 1KR2J-1-GP
R150 1KR2J-1-GP
R437 1KR2J-1-GP
R437 1KR2J-1-GP
R190 1KR2J-1-GP
R190 1KR2J-1-GP
GEN_XTAL_OUT_R
12
X1
X1
C331
C331
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
B
12
L
H
12
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
12
R42833R2J-2-GP R42833R2J-2-GP
12
R42933R2J-2-GP R42933R2J-2-GP
1 2
R156 0R2J-2-GPR156 0R2J-2-GP
SMBC_ICH11,19
SMBD_ICH11,19
12
C332
C332
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
OUT
(VTT_PWRGD#)
H
Hi - Z
FSA
CLKREQ1#
CLKREQ2#
CLKREQ3#
CLKREQ4#
CLKREQ5#
CLKREQ6#
CLKREQ7#
CLKREQ8#
CLKREQ9#
VGA_27MHZ_1
VGA_27MHZSS_1
GEN_XTAL_IN
GEN_XTAL_OUT
1 2
R172 0R3-0-U-GPR172 0R3-0-U-GP
3D3V_48MPWR_S0
3D3V_APWR_S0
3D3V_CLKGEN_S0
U24
U24
46
CLKREQ1#
26
CLKREQ2#
28
CLKREQ3#
57
CLKREQ4#
29
CLKREQ5#
62
CLKREQ6#
38
CLKREQ7#
71
CLKREQ8#
72
CLKREQ9#
47
LCD100/96/SRC0_T
48
LCD100/96/SRCO_C
43
DOTT_96MHZ/27MHZ_NONSPREAD
44
DOTC_96MHZ/27MHZ_SPREAD
20
X1
19
X2
16
SMBCLK
17
SMBDAT
65
VDDSRC
12
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
1
54
49
VDDSRC
VDDSRC
VDDSRC
C
PCICLK4/FCTSEL1
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
PCLK_FWH_1
PCLK_PCM_1
PCLK_KBC_1
SS_SEL
CPU_SEL2_1
CPU_SEL1
23
45
41
USB_48MHZ/FSLA
FSLB/TEST_MODE
REF0/FSLC/TEST_SEL
C554
C554
FSA
1 2
R546 2K2R2J-2-GPR546 2K2R2J-2-GP
24
39
CPU_STOP#
VTT_PWRGD#/PD
SRCT1
SRCT2
SRCT3
SRCT4
SRCT5
SRCT6
SRCT7
SRCT8
SRCT9
SRCC1
SRCC2
SRCC3
SRCC4
SRCC5
SRCC6
SRCC7
SRCC8
SRCC9
PCI_SRC_STOP#
ITP_EN/PCICLK_F0
12
C310
C310
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1016
PM_STPCPU# 17
CLK_EN# 34
50
52
55
58
60
63
66
70
3
51
53
56
59
61
64
67
69
2
25
37
12
C555
18
VDD48
12
VDDREF
VDDCPU
C555
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
34
27
33
PCICLK1
PCICLK232PCICLK3
C351
C351
7
40
30
36
VDDA
VDDPCI
VDDPCI
D
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
R43533R2J-2-GP R43533R2J-2-GP
12
12
R43433R2J-2-GP R43433R2J-2-GP
12
R43233R2J-2-GP R43233R2J-2-GP
CPU_SEL2
PEG_REFCLKP_1
CLK_PCIE_NEW_1
CLK_MCH_3GPLL_1
CLK_PCIE_SATA_1
CLK_PCIE_ICH_1
CLK_PCIE_MINI1_1
CLK_PCIE_MINI2_1
PEG_REFCLKN_1
CLK_PCIE_NEW_1#
CLK_MCH_3GPLL_1#
CLK_PCIE_SATA_1#
CLK_PCIE_ICH_1#
CLK_PCIE_MINI1_1#
CLK_PCIE_MINI2_1#
ITP_EN
C557
C557
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
PCLK_FWH 31
PCLK_PCM 22
PCLK_KBC 29
CLK_CPU_BCLK_1
CLK_CPU_BCLK_1#
CLK_MCH_BCLK_1
CLK_MCH_BCLK_1#
C312
C312
PEG_REFCLKP_1
PEG_REFCLKN_1
CLK_PCIE_NEW_1
CLK_PCIE_NEW_1#
CLK_MCH_3GPLL_1
CLK_MCH_3GPLL_1#
CLK_PCIE_SATA_1
CLK_PCIE_SATA_1#
CLK_PCIE_ICH_1
CLK_PCIE_ICH_1#
CLK_PCIE_MINI1_1
CLK_PCIE_MINI1_1#
CLK_PCIE_MINI2_1
CLK_PCIE_MINI2_1#
12
R15133R2J-2-GP R15133R2J-2-GP
12
C556
C556
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1
2 3
RN25 SRN33J-5-GP-URN25 SRN33J-5-GP-U
1
2 3
RN23 SRN33J-5-GP-URN23 SRN33J-5-GP-U
PM_STPPCI# 17
CLK_ICHPCI 17
12
4
4
2 3
1
RN22 SRN33J-5-GP-URN22 SRN33J-5-GP-U
2 3
1
RN21 SRN33J-5-GP-URN21 SRN33J-5-GP-U
2 3
1
RN28 SRN33J-5-GP-URN28 SRN33J-5-GP-U
2 3
1
RN29 SRN33J-5-GP-URN29 SRN33J-5-GP-U
2 3
1
RN30 SRN33J-5-GP-URN30 SRN33J-5-GP-U
2 3
1
RN32 SRN33J-5-GP-URN32 SRN33J-5-GP-U
1
2 3
RN33 SRN33J-5-GP-URN33 SRN33J-5-GP-U
E
C553
C553
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
4
4
4
4
4
4
4
CLK_CPU_BCLK 4
CLK_CPU_BCLK# 4
CLK_MCH_BCLK 6
CLK_MCH_BCLK# 6
PEG_REFCLKP 38
PEG_REFCLKN 38
CLK_PCIE_NEW 26
CLK_PCIE_NEW# 26
CLK_MCH_3GPLL 7
CLK_MCH_3GPLL# 7
CLK_PCIE_SATA 16
CLK_PCIE_SATA# 16
CLK_PCIE_ICH 17
CLK_PCIE_ICH# 17
CLK_PCIE_MINI1 24
CLK_PCIE_MINI1# 24
CLK_PCIE_MINI2 24
CLK_PCIE_MINI2# 24
2 2
11
ICS954305EKLF-GP
ICS954305EKLF-GP
CLK_MCH_BCLK_1
CLK_CPU_BCLK_1
CLK_MCH_BCLK_1#
CLK_CPU_BCLK_1#
1D05V_S0
12
12
R425
R425
1KR2J-1-GP
1KR2J-1-GP
DY
DY
1 1
DUMMY-R2
DUMMY-R2
R427
R427
12
R422
R422
DUMMY-R2
DUMMY-R2
12
R424
R424
1KR2J-1-GP
1KR2J-1-GP
DY
DY
12
R154
R154
DUMMY-R2
DUMMY-R2
12
R155
R155
1KR2J-1-GP
1KR2J-1-GP
DY
DY
FS_B
FS_C
0
0
0
1
1 100M
1
1
0
0
1
1
0
0
1
1
FS_A
0
01200M
1
00333M
1
0
1 Reserved
CPU_SEL0 4,7
CPU_SEL1 4,7
CPU_SEL2 4,7
CPU
266M
133M
166M
400M
PEG_REFCLKP
PEG_REFCLKN
CLK_PCIE_NEW
CLK_PCIE_NEW#
CLK_PCIE_MINI1
CLK_PCIE_MINI1#
CLK_PCIE_SATA
CLK_PCIE_SATA#
CLK_PCIE_ICH
CLK_PCIE_ICH#
CLK_PCIE_MINI2
CLK_PCIE_MINI2#
1
2 3
RN65 SRN49D9F-GPRN65 SRN49D9F-GP
2 3
1
RN46 SRN49D9F-GPRN46 SRN49D9F-GP
2 3
1
RN54 SRN49D9F-GPRN54 SRN49D9F-GP
2 3
1
RN51 SRN49D9F-GPRN51 SRN49D9F-GP
2 3
1
RN52 SRN49D9F-GPRN52 SRN49D9F-GP
1
2 3
RN55 SRN49D9F-GPRN55 SRN49D9F-GP
14
1022
4
4
4
4
4
4
CPUCLKC110CPUCLKT1
CPUCLKC013CPUCLKT0
CPUC_ITP/SRCC10
CPUT_ITP/SRCT10
5
6
9
CLK_XDP_1
CLK_XDP_1#
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_MCH_BCLK
CLK_MCH_BCLK#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
CLK_XDP
CLK_XDP#
GNDA
IREF
REF1
22
GNDCPU
GNDREF
GND48
GND
8
15
21
42
73
GEN_REF
GEN_IREF
2 3
1
RN24 SRN33J-5-GP-U
RN24 SRN33J-5-GP-U
DY
DY
A
B
C
GNDSRC
GNDPCI
GNDPCI
GNDSRC
4
31
35
68
12
R43633R2J-2-GP R43633R2J-2-GP
12
R438475R2F-L1-GP R438475R2F-L1-GP
4
1
2 3
RN26 SRN49D9F-GPRN26 SRN49D9F-GP
1
2 3
RN47 SRN49D9F-GPRN47 SRN49D9F-GP
2 3
1
RN50 SRN49D9F-GPRN50 SRN49D9F-GP
2 3
1
RN48 SRN49D9F-GP
RN48 SRN49D9F-GP
DY
DY
CLK_XDP 2
CLK_XDP# 2
4
4
4
4
CLK_ICH14 17
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet of
D
Date: Sheet of
Clock Generator
Clock Generator
Clock Generator
KAI -1
KAI -1
KAI -1
E
of
344Thursday, April 13, 2006
344Thursday, April 13, 2006
344Thursday, April 13, 2006
NMC
A
U56A
1
1
1
1
1
1
1
1
1
1
1
U56A
J4
A[3]#
L4
A[4]#
M3
A[5]#
K5
A[6]#
M1
A[7]#
N2
A[8]#
J1
A[9]#
N3
A[10]#
P5
A[11]#
P2
A[12]#
L1
A[13]#
P4
A[14]#
P1
A[15]#
R1
A[16]#
L2
ADSTB[0]#
K3
REQ[0]#
H2
REQ[1]#
K2
REQ[2]#
J3
REQ[3]#
L5
REQ[4]#
Y2
A[17]#
U5
A[18]#
R3
A[19]#
W6
A[20]#
U4
A[21]#
Y5
A[22]#
U2
A[23]#
R4
A[24]#
T5
A[25]#
T3
A[26]#
W3
A[27]#
W5
A[28]#
Y4
A[29]#
W2
A[30]#
Y1
A[31]#
V4
ADSTB[1]#
A6
A20M#
A5
FERR#
C4
IGNNE#
D5
STPCLK#
C6
LINT0
B4
LINT1
A3
SMI#
AA1
RSVD[01]
AA4
RSVD[02]
AB2
RSVD[03]
AA3
RSVD[04]
M4
RSVD[05]
N5
RSVD[06]
T2
RSVD[07]
V3
RSVD[08]
B2
RSVD[09]
C3
RSVD[10]
B25
RSVD[11]
BGA479-SKT6-GPU2
BGA479-SKT6-GPU2
ADDR GROUP 0
ADDR GROUP 0
ADDR GROUP 1
ADDR GROUP 1
XDP/ITP SIGNALSH CLK
XDP/ITP SIGNALSH CLK
PROCHOT#
THERMDA
THERMDC
THERM
THERM
THERMTRIP#
RESERVED
RESERVED
4 4
3 3
2 2
H_A#[31..3]6
H_ADSTB#06
H_REQ#[4..0]6
H_ADSTB#16
H_A20M#16
H_FERR#16
H_IGNNE#16
H_STPCLK#16
H_INTR16
H_NMI16
H_SMI#16
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
TP15TPAD30 TP15TPAD30
TP18TPAD30 TP18TPAD30
TP16TPAD30 TP16TPAD30
TP17TPAD30 TP17TPAD30
TP11TPAD30 TP11TPAD30
TP12TPAD30 TP12TPAD30
TP13TPAD30 TP13TPAD30
TP14TPAD30 TP14TPAD30
TP4TPAD30 TP4TPAD30
TP5TPAD30 TP5TPAD30
TP20TPAD30 TP20TPAD30
ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#
BR0#
IERR#
INIT#
LOCK#
CONTROL
CONTROL
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
HIT#
HITM#
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDO
TMS
TRST#
DBR#
BCLK[0]
BCLK[1]
RSVD[12]
RSVD[13]
RSVD[14]
RSVD[15]
RSVD[16]
RSVD[17]
RSVD[18]
RSVD[19]
RSVD[20]
B
TP10TPAD30TP10TPAD30
1
H1
E2
G5
H5
F21
E1
F1
D20
B3
H4
B1
H_RS#0
F3
H_RS#1
F4
H_RS#2
G3
G2
G6
E4
XDP_BPM#0
AD4
XDP_BPM#1
AD3
XDP_BPM#2
AD1
XDP_BPM#3
AC4
XDP_BPM#4
AC2
XDP_BPM#5
AC1
XDP_TCK
AC5
XDP_TDI
AA6
TDI
AB3
AB5
AB6
C20
D21
A24
A25
C7
A22
A21
T22
D2
F6
D3
C1
AF1
D22
C23
C24
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#
1
1
1
1
1
1
1
1
1
H_ADS# 6
H_BNR# 6
H_BPRI# 6
H_DEFER# 6
H_DRDY# 6
H_DBSY# 6
H_BREQ#0 6
H_INIT# 16
H_LOCK# 6
H_CPURST# 2,6
H_TRDY# 6
H_HIT# 6
H_HITM# 6
CPU_PROCHOT#_1
H_THERMDA 20
H_THERMDC 20
PM_THRMTRIP-A# 7
1 2
R109 0R0402-PADR109 0R0402-PAD
CLK_CPU_BCLK 3
CLK_CPU_BCLK# 3
TP24 TPAD30TP24 TPAD30
TP7 TPAD30TP7 TPAD30
TP9 TPAD30TP9 TPAD30
TP8 TPAD30TP8 TPAD30
TP6 TPAD30TP6 TPAD30
TP19 TPAD30TP19 TPAD30
TP23 TPAD30TP23 TPAD30
TP22 TPAD30TP22 TPAD30
TP21 TPAD30TP21 TPAD30
XDP_BPM#0 2
XDP_BPM#1 2
XDP_BPM#2 2
XDP_BPM#3 2
XDP_BPM#4 2
XDP_BPM#5 2
XDP_TCK 2
XDP_TDI 2
XDP_TDO 2
XDP_TMS 2
XDP_TRST# 2
XDP_DBRESET# 2,17
H_IERR#
H_RS#[2..0] 6
1D05V_S0
12
R122
R122
56R2J-4-GP
56R2J-4-GP
Place testpoint on
H_IERR# with a GND
0.1" away
1D05V_S0
12
1 2
R127 0R2J-2-GPDYR127 0R2J-2-GPDY
PM_THRMTRIP-I# 16
Layout Note:
0.5" max length.
R123
R123
68R2-GP
68R2-GP
1D05V_S0
12
12
C
R131
R131
1KR2F-3-GP
1KR2F-3-GP
R130
R130
2KR2F-3-GP
2KR2F-3-GP
H_DSTBN#06
H_DSTBP#06
H_DINV#06
CPU_PROCHOT# 34
H_DSTBN#16
H_DSTBP#16
H_DINV#16
CPU_GTLREF0
CPU_SEL03,7
CPU_SEL13,7
CPU_SEL23,7
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
TEST1
12
R406 1KR2J-1-GPDYR406 1KR2J-1-GPDY
R407 51R2J-2-GPR407 51R2J-2-GP
1 2
TEST2
U56B
U56B
E22
D[0]#
F24
D[1]#
E26
D[2]#
H22
D[3]#
F23
D[4]#
G25
D[5]#
E25
D[6]#
E23
D[7]#
K24
D[8]#
G24
D[9]#
J24
D[10]#
J23
D[11]#
H26
D[12]#
F26
D[13]#
K22
D[14]#
H25
D[15]#
H23
DSTBN[0]#
G22
DSTBP[0]#
J26
DINV[0]#
N22
D[16]#
K25
D[17]#
P26
D[18]#
R23
D[19]#
L25
D[20]#
L22
D[21]#
L23
D[22]#
M23
D[23]#
P25
D[24]#
P22
D[25]#
P23
D[26]#
T24
D[27]#
R24
D[28]#
L26
D[29]#
T25
D[30]#
N24
D[31]#
M24
DSTBN[1]#
N25
DSTBP[1]#
M26
DINV[1]#
AD26
GTLREF
C26
TEST1
D25
TEST2
B22
BSEL[0]
B23
BSEL[1]
C21
BSEL[2]
BGA479-SKT6-GPU2
BGA479-SKT6-GPU2
D
MISC
MISC
DATA GRP 0 DATA GRP 1
DATA GRP 0 DATA GRP 1
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
DATA GRP 2
DATA GRP 2
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
DATA GRP 3
DATA GRP 3
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
COMP[0]
COMP[1]
COMP[2]
COMP[3]
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#
AA23
AB24
V24
V26
W25
U23
U25
U22
AB25
W22
Y23
AA26
Y26
Y22
AC26
AA24
W24
Y25
V23
AC22
AC23
AB22
AA21
AB21
AC25
AD20
AE22
AF23
AD24
AE21
AD21
AE25
AF25
AF22
AF26
AD23
AE24
AC20
R26
U26
U1
V1
E5
B5
D24
D6
D7
AE6
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
COMP0
COMP1
COMP2
COMP3
1 2
R128 27D4R2F-L1-GPR128 27D4R2F-L1-GP
1 2
R129 54D9R2F-L1-GPR129 54D9R2F-L1-GP
1 2
R112 27D4R2F-L1-GPR112 27D4R2F-L1-GP
1 2
R113 54D9R2F-L1-GPR113 54D9R2F-L1-GP
H_DPRSTP# 16
H_DPSLP# 16
H_DPWR# 6
H_PWRGD 16
H_CPUSLP# 6,16
PSI# 34
E
H_DINV#[3..0] 6
H_DSTBN#[3..0] 6
H_DSTBP#[3..0] 6
H_D#[63..0] 6
H_DSTBN#2 6
H_DSTBP#2 6
H_DINV#2 6
Layout Note:
Comp0, 2 connect with Zo=27.4 ohm, make
trace length shorter than 0.5" .
Comp1, 3 connect with Zo=55 ohm, make
trace length shorter than 0.5" .
H_DSTBN#3 6
H_DSTBP#3 6
H_DINV#3 6
1D05V_S0
R120
XDP_TDI
1 1
A
R120
1 2
150R2J-L1-GP-U
150R2J-L1-GP-U
B
H_PWRGD
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet of
C
D
Date: Sheet of
1 2
R111 200R2J-L1-GPR111 200R2J-L1-GP
1D05V_S0
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
CPU (1 of 2)
CPU (1 of 2)
CPU (1 of 2)
KAI -1
KAI -1
KAI -1
444Thursday, April 13, 2006
444Thursday, April 13, 2006
444Thursday, April 13, 2006
E
of
NMC
A
VCC_CORE_S0
U56C
U56C
A7
VCC[001]
A9
VCC[002]
A10
VCC[003]
A12
VCC[004]
A13
VCC[005]
A15
VCC[006]
A17
VCC[007]
4 4
3 3
2 2
A18
VCC[008]
A20
VCC[009]
B7
VCC[010]
B9
VCC[011]
B10
VCC[012]
B12
VCC[013]
B14
VCC[014]
B15
VCC[015]
B17
VCC[016]
B18
VCC[017]
B20
VCC[018]
C9
VCC[019]
C10
VCC[020]
C12
VCC[021]
C13
VCC[022]
C15
VCC[023]
C17
VCC[024]
C18
VCC[025]
D9
VCC[026]
D10
VCC[027]
D12
VCC[028]
D14
VCC[029]
D15
VCC[030]
D17
VCC[031]
D18
VCC[032]
E7
VCC[033]
E9
VCC[034]
E10
VCC[035]
E12
VCC[036]
E13
VCC[037]
E15
VCC[038]
E17
VCC[039]
E18
VCC[040]
E20
VCC[041]
F7
VCC[042]
F9
VCC[043]
F10
VCC[044]
F12
VCC[045]
F14
VCC[046]
F15
VCC[047]
F17
VCC[048]
F18
VCC[049]
F20
VCC[050]
AA7
VCC[051]
AA9
VCC[052]
AA10
VCC[053]
AA12
VCC[054]
AA13
VCC[055]
AA15
VCC[056]
AA17
VCC[057]
AA18
VCC[058]
AA20
VCC[059]
AB9
VCC[060]
AC10
VCC[061]
AB10
VCC[062]
AB12
VCC[063]
AB14
VCC[064]
AB15
VCC[065]
AB17
VCC[066]
AB18
VCC[067]
BGA479-SKT6-GPU2
BGA479-SKT6-GPU2
VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]
VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]
VCCA
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
VCCSENSE
VSSSENSE
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
V6
G21
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
B26
AD6
AF5
AE5
AF4
AE3
AF2
AE2
AF7
AE7
VCC_CORE_S0
100R2F-L1-GP-U
100R2F-L1-GP-U
R114
R114
1D05V_S0
H_VID0 34
H_VID1 34
H_VID2 34
H_VID3 34
H_VID4 34
H_VID5 34
H_VID6 34
12
H_VID[0..6]34
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
1D5V_VCCA_S0
C291
C291
VCC_CORE_S0
12
VSS_SENSE 34
VCC_CORE_S0
12
C236
C236
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
B
12
R121
R121
100R2F-L1-GP-U
100R2F-L1-GP-U
12
C232
C232
DY
DY
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
12
C290
C290
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
VCC_SENSE 34
12
12
C233
C233
C235
C235
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
1D5V_S0 1D5V_VCCA_S0
1 2
R126 0R0603-PADR126 0R0603-PAD
1D05V_S0
12
C271
C271
12
12
C266
C266
C268
C268
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
12
12
C264
C264
SCD1U10V2MX-3GP
SCD1U10V2MX-3GP
12
C267
C267
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
12
C274
C274
SCD1U10V2MX-3GP
SCD1U10V2MX-3GP
SCD1U10V2MX-3GP
SCD1U10V2MX-3GP
12
12
C229
C229
C265
C265
DY
DY
DY
DY
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
C239
C239
C
12
12
C269
C269
C270
C270
SCD1U10V2MX-3GP
SCD1U10V2MX-3GP
SCD1U10V2MX-3GP
SCD1U10V2MX-3GP
12
12
C230
C230
C231
C231
DY
DY
DY
DY
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
12
12
C240
C240
C238
C238
SCD1U10V2MX-3GP
SCD1U10V2MX-3GP
SCD1U10V2MX-3GP
SCD1U10V2MX-3GP
12
12
C275
C275
C272
C272
DY
DY
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
12
12
C234
C234
C237
C237
SCD1U10V2MX-3GP
SCD1U10V2MX-3GP
SCD1U10V2MX-3GP
SCD1U10V2MX-3GP
SCD1U10V2MX-3GP
SCD1U10V2MX-3GP
12
12
C276
C276
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
C273
C273
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
12
C244
C244
12
TC4
TC4
ST220U2D5VBM-LGP
ST220U2D5VBM-LGP
DY
DY
12
C242
C242
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
D
U56D
U56D
A4
VSS[001]
A8
VSS[002]
A11
VSS[003]
A14
VSS[004]
A16
VSS[005]
A19
VSS[006]
A23
VSS[007]
A26
VSS[008]
B6
VSS[009]
B8
VSS[010]
B11
VSS[011]
B13
VSS[012]
B16
VSS[013]
B19
VSS[014]
B21
VSS[015]
B24
VSS[016]
C5
VSS[017]
C8
VSS[018]
C11
VSS[019]
C14
VSS[020]
C16
VSS[021]
C19
VSS[022]
C2
VSS[023]
C22
VSS[024]
C25
VSS[025]
D1
VSS[026]
D4
VSS[027]
D8
VSS[028]
D11
VSS[029]
D13
VSS[030]
D16
VSS[031]
D19
VSS[032]
D23
VSS[033]
D26
VSS[034]
E3
VSS[035]
E6
VSS[036]
E8
VSS[037]
E11
VSS[038]
E14
VSS[039]
E16
VSS[040]
E19
VSS[041]
E21
VSS[042]
E24
VSS[043]
F5
VSS[044]
F8
VSS[045]
F11
VSS[046]
F13
VSS[047]
F16
VSS[048]
F19
VSS[049]
F2
VSS[050]
F22
VSS[051]
F25
VSS[052]
G4
VSS[053]
G1
VSS[054]
G23
VSS[055]
G26
VSS[056]
H3
VSS[057]
H6
VSS[058]
H21
VSS[059]
H24
VSS[060]
J2
VSS[061]
J5
VSS[062]
J22
VSS[063]
J25
VSS[064]
K1
VSS[065]
K4
VSS[066]
K23
VSS[067]
K26
VSS[068]
L3
VSS[069]
L6
VSS[070]
L21
VSS[071]
L24
VSS[072]
M2
VSS[073]
M5
VSS[074]
M22
VSS[075]
M25
VSS[076]
N1
VSS[077]
N4
VSS[078]
12
C243
C243
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
N23
VSS[079]
N26
VSS[080]
VSS[081]P3VSS[162]
BGA479-SKT6-GPU2
BGA479-SKT6-GPU2
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
E
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
AF3
AF6
AF8
AF11
AF13
AF16
AF19
AF21
AF24
VCC_CORE_S0VCC_CORE_S0
Layout Note:
1 1
VCCSENSE and VSSSENSE lines
should be of equal length.
12
C241
C241
DY
DY
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
12
12
C262
C262
C263
C263
DY
DY
DY
DY
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
12
12
C247
C247
C228
C228
DY
DY
DY
DY
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
A
B
12
12
C248
C248
C246
C246
DY
DY
DY
DY
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
C
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
12
12
C279
C279
C245
C245
DY
DY
DY
DY
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
12
12
C277
C277
DY
DY
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
C278
C278
DY
DY
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
12
C261
C261
DY
DY
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
D
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet
CPU (2 of 2)
CPU (2 of 2)
CPU (2 of 2)
KAI -1
KAI -1
KAI -1
544Thursday, April 13, 2006
544Thursday, April 13, 2006
544Thursday, April 13, 2006
E
of
NMC
A
H_XRCOMP
12
R136
R136
24D9R2F-L-GP
24D9R2F-L-GP
4 4
1D05V_S0
R135
R135
54D9R2F-L1-GP
54D9R2F-L1-GP
1 2
H_XSCOMP
1D05V_S0
12
R132
R132
221R2F-2-GP
221R2F-2-GP
H_XSWING
3 3
2 2
100R2F-L1-GP-U
100R2F-L1-GP-U
100R2F-L1-GP-U
100R2F-L1-GP-U
R133
R133
1D05V_S0
1D05V_S0
R138
R138
12
H_YRCOMP
12
R140
R140
24D9R2F-L-GP
24D9R2F-L-GP
R137
R137
54D9R2F-L1-GP
54D9R2F-L1-GP
1 2
H_YSCOMP
12
R139
R139
221R2F-2-GP
221R2F-2-GP
12
H_YSWING
H_D#[63..0]4
C294
C294
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1 2
C296
C296
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1 2
B
U19A
W11
AB7
AA9
AB8
AA4
AA7
AA2
AA6
AA10
AA1
AB4
AC9
AB11
AC11
AB3
AC2
AD1
AD9
AC1
AD7
AC6
AB5
AD10
AD4
AC8
AG2
AG1
K11
T10
U11
T11
Y10
F1
J1
H1
J6
H3
K2
G1
G2
K9
K1
K7
J8
H4
J3
G4
T3
U7
U9
W9
T1
T8
T4
W7
U5
T9
W6
T5
W4
W3
Y3
Y7
W5
W2
Y8
E1
E2
E4
Y1
U1
W1
U19A
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
H_XRCOMP
H_XSCOMP
H_XSWING
H_YRCOMP
H_YSCOMP
H_YSWING
H_CLKIN
H_CLKIN#
CALISTOGA
CALISTOGA
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_XRCOMP
H_XSCOMP
H_XSWING
H_YRCOMP
H_YSCOMP
H_YSWING
CLK_MCH_BCLK3
CLK_MCH_BCLK#3
C
HOST
HOST
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_VREF_0
H_BNR#
H_BPRI#
H_BREQ#0
H_CPURST#
H_DBSY#
H_DEFER#
H_DPWR#
H_DRDY#
H_VREF_1
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
H_HIT#
H_HITM#
H_LOCK#
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
H_RS#_0
H_RS#_1
H_RS#_2
H_SLPCPU#
H_TRDY#
H9
C9
E11
G11
F11
G12
F9
H11
J12
G14
D9
J14
H13
J15
F14
D12
A11
C11
A12
A13
E13
G13
F12
B12
B14
C12
A14
C14
D14
E8
B9
C13
J13
C6
F6
C7
B7
A7
C3
J9
H8
K13
J7
W8
U3
AB10
K4
T7
Y5
AC4
K3
T6
AA5
AC5
D3
D4
B3
D8
G8
B8
F8
A8
B4
E6
D6
E3
E7
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_VREF
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
H_CPUSLP#_1
1 2
R134 0R0402-PADR134 0R0402-PAD
D
H_ADS# 4
H_ADSTB#0 4
H_ADSTB#1 4
H_BNR# 4
H_BPRI# 4
H_BREQ#0 4
H_CPURST# 2,4
H_DBSY# 4
H_DEFER# 4
H_DPWR# 4
H_DRDY# 4
H_HIT# 4
H_HITM# 4
H_LOCK# 4
H_A#[31..3] 4
H_CPUSLP# 4,16
H_TRDY# 4
C537
C537
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1 2
H_DINV#[3..0] 4
H_DSTBN#[3..0] 4
H_DSTBP#[3..0] 4
H_REQ#[4..0] 4
H_RS#[2..0] 4
1D05V_S0
12
12
R396
R396
100R2F-L1-GP-U
100R2F-L1-GP-U
R395
R395
200R2F-L-GP
200R2F-L-GP
E
100mils or less
from GMCH pin
1 1
Place them near to the chip
A
B
C
D
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet of
Date: Sheet of
GMCH (1 of 5)
GMCH (1 of 5)
GMCH (1 of 5)
KAI -1
KAI -1
KAI -1
E
644Thursday, April 13, 2006
644Thursday, April 13, 2006
644Thursday, April 13, 2006
of
NMC
A
M_CLK_DDR011
M_CLK_DDR111
M_CLK_DDR211
M_CLK_DDR311
M_CLK_DDR#011
M_CLK_DDR#111
M_CLK_DDR#211
M_CLK_DDR#311
4 4
12
R374
R374
40D2R2F-GP
40D2R2F-GP
DY
DY
DDR_VREF_S3
DY BC3
DY
SC2D2U10V3ZY-1GP
SC2D2U10V3ZY-1GP
3 3
3D3V_S0
2 2
1D8V_S3
12
12
1 1
M_CKE011,12
M_CKE111,12
M_CKE211,12
M_CKE311,12
M_CS0#11,12
M_CS1#11,12
M_CS2#11,12
M_CS3#11,12
M_OCDCOMP0
M_OCDCOMP1
12
R397
R397
40D2R2F-GP
40D2R2F-GP
DY
DY
12
12
12
BC5
BC5
BC3
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
DMI_TXN[3..0]17
DMI_TXP[3..0]17
DMI_RXN[3..0]17
DMI_RXP[3..0]17
1 2
R318 10KR2J-3-GPR318 10KR2J-3-GP
R398
R398
80D6R2F-L-GP
80D6R2F-L-GP
R399
R399
80D6R2F-L-GP
80D6R2F-L-GP
BC6
BC6
SC2D2U10V3ZY-1GP
SC2D2U10V3ZY-1GP
DY
DY
M_RCOMPN
M_RCOMPP
12
BC4
BC4
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
PM_EXTTS#0
M_ODT011,12
M_ODT111,12
M_ODT211,12
M_ODT311,12
M_RCOMPN
M_RCOMPP
Connect to GND
if not used
CLK_MCH_3GPLL#3
CLK_MCH_3GPLL3
DMI_TXP3
1D05V_S0
Stitch CAP for DMI
cross moat
AY35
SM_CK_0
AR1
SM_CK_1
AW7
SM_CK_2
AW40
SM_CK_3
AW35
SM_CK#_0
AT1
SM_CK#_1
AY7
SM_CK#_2
AY40
SM_CK#_3
AU20
SM_CKE_0
AT20
SM_CKE_1
BA29
SM_CKE_2
AY29
SM_CKE_3
AW13
SM_CS#_0
AW12
SM_CS#_1
AY21
SM_CS#_2
AW21
SM_CS#_3
AL20
SM_OCDCOMP_0
AF10
SM_OCDCOMP_1
BA13
SM_ODT_0
BA12
SM_ODT_1
AY20
SM_ODT_2
AU21
SM_ODT_3
AV9
SM_RCOMP#
AT9
SM_RCOMP
AK1
SM_VREF_0
AK41
SM_VREF_1
AF33
G_CLKIN#
AG33
G_CLKIN
A27
D_REFCLKIN#
A26
D_REFCLKIN
C40
D_REFSSCLKIN#
D41
D_REFSSCLKIN
DMI_TXN0
AE35
AF39
AG35
AH39
AC35
AE39
AF35
AG39
AE37
AF41
AG37
AH41
AC37
AE41
AF37
AG41
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
CALISTOGA
CALISTOGA
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
DY
DY
1 2
C325 SCD1U16V2ZY-2GP
C325 SCD1U16V2ZY-2GP
DY
DY
1 2
C326 SCD1U16V2ZY-2GP
C326 SCD1U16V2ZY-2GP
DY
DY
1 2
C329 SCD1U16V2ZY-2GP
C329 SCD1U16V2ZY-2GP
DY
DY
1 2
C328 SCD1U16V2ZY-2GP
C328 SCD1U16V2ZY-2GP
A
B
CFGRSVD
CFGRSVD
DDR MUXINGCLKDMI
DDR MUXINGCLKDMI
B
PM_BMBUSY#
PM
PM
PM_EXTTS#_0
PM_EXTTS#_1
PM_THRMTRIP#
MISC
MISC
SDVO_CTRLCLK
SDVO_CTRLDATA
NC
NC
3D3V_S0
1 2
R356
R356
1 2
R358
R358
1 2
R357
R357
1 2
R385
R385
1 2
R387
R387
1 2
R388
R388
1 2
R386
R386
1 2
R383
R383
1 2
R392
R392
1 2
R384 2K2R2J-2-GPR384 2K2R2J-2-GP
1 2
R393
R393
1 2
R394
R394
1 2
R391
R391
1 2
R402
R402
1 2
R389
R389
1 2
R390
R390
1 2
R382
R382
1 2
R401
R401
RSVD_0
RSVD_1
RSVD_2
RSVD_3
RSVD_4
RSVD_5
RSVD_6
RSVD_7
RSVD_8
RSVD_9
RSVD_10
RSVD_11
RSVD_12
RSVD_13
RSVD_14
RSVD_15
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20
PWROK
RSTIN#
LT_RESET#
NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
DUMMY-R2
DUMMY-R2
DUMMY-R2
DUMMY-R2
DUMMY-R2
DUMMY-R2
DUMMY-R2
DUMMY-R2
DUMMY-R2
DUMMY-R2
DUMMY-R2
DUMMY-R2
DUMMY-R2
DUMMY-R2
DUMMY-R2
DUMMY-R2
DUMMY-R2
DUMMY-R2
DUMMY-R2
DUMMY-R2
DUMMY-R2
DUMMY-R2
DUMMY-R2
DUMMY-R2
DUMMY-R2
DUMMY-R2
DUMMY-R2
DUMMY-R2
DUMMY-R2
DUMMY-R2
DUMMY-R2
DUMMY-R2
DUMMY-R2
DUMMY-R2
U19B
U19B
H32
T32
R32
F3
F7
AG11
AF11
H7
J19
K30
J29
A41
A35
A34
D28
D27
K16
K18
J18
CFG3
F18
CFG4
E15
CFG5
F15
CFG6
E18
CFG7
D19
CFG8
D16
CFG9
G16
CFG10
E16
CFG11
D15
CFG12
G15
CFG13
K15
CFG14
C15
CFG15
H16
CFG16
G18
CFG17
H15
CFG18
J25
CFG19
K27
CFG20
J26
G28
F25
H26
G6
AH33
R547 0R2J-2-GPR547 0R2J-2-GP
AH34
1 2
R359
R359
100R2J-2-GP
100R2J-2-GP
H28
H27
K28
D1
C41
C1
BA41
BA40
BA39
BA3
BA2
BA1
B41
B2
AY41
AY1
AW41
AW1
A40
A4
A39
A3
CLK_MCH_OE#
1 2
CFG18
CFG19
CFG20
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
C
1
TP47
TP47
TPAD30
TPAD30
CPU_SEL0 3,4
CPU_SEL1 3,4
CPU_SEL2 3,4
PM_BMBUSY# 17
PM_EXTTS#0 11
PM_EXTTS#1 17
PM_THRMTRIP-A# 4
VGATE_PWRGD 17,34
1016
PLT_RST1# 19,24,26,29,31,38
MCH_ICH_SYNC# 17
CFG[2:0] : No internal pull-up or pull-down.
CFG[17:3] : Internal pull-up.
CFG[19:18] : Internal pull-down.
CFG[6] : 0=Moby Dick ,1=Calistoga (default)
CFG[11] : PSB 4X CLK ENABLE
0=Calistoga ,1=Reserved (default)
When Low choice
lower than 3.5K
Ohm
for calistoga configuration
1D5V_S0
Connect to 1D5V_S0
if not used
1D05V_S0
U19C
U19C
D32
L_BKLTCTL
J30
L_BKLTEN
H30
L_CLKCTLA
H29
L_CLKCTLB
G26
L_DDC_CLK
G25
L_DDC_DATA
B38
L_IBG
C35
L_VBG
F32
L_VDDEN
C33
L_VREFH
C32
L_VREFL
A33
LA_CLK#
A32
LA_CLK
E27
LB_CLK#
E26
LB_CLK
C37
LA_DATA#_0
B35
LA_DATA#_1
A37
LA_DATA#_2
B37
LA_DATA_0
B34
LA_DATA_1
A36
LA_DATA_2
G30
LB_DATA#_0
D30
LB_DATA#_1
F29
LB_DATA#_2
F30
LB_DATA_0
D29
LB_DATA_1
F28
LB_DATA_2
A16
TV_DACA_OUT
C18
TV_DACB_OUT
A19
TV_DACC_OUT
J20
TV_IREF
B16
TV_IRTNA
B18
TV_IRTNB
B19
TV_IRTNC
E23
CRT_BLUE
D23
CRT_BLUE#
C22
CRT_GREEN
B22
CRT_GREEN#
A21
CRT_RED
B21
CRT_RED#
C26
CRT_DDC_CLK
C25
CRT_DDC_DATA
G23
CRT_HSYNC
J22
CRT_IREF
H23
CRT_VSYNC
CALISTOGA
CALISTOGA
When High 1K Ohm
C
D
LVDS
LVDS
TV
TV
VGA
VGA
D
E
1D5V_PCIE_S0
R97
EXP_A_COMPI
EXP_A_COMPO
EXP_A_RXN_0
EXP_A_RXN_1
EXP_A_RXN_2
EXP_A_RXN_3
EXP_A_RXN_4
EXP_A_RXN_5
EXP_A_RXN_6
EXP_A_RXN_7
EXP_A_RXN_8
EXP_A_RXN_9
EXP_A_RXN_10
EXP_A_RXN_11
EXP_A_RXN_12
EXP_A_RXN_13
EXP_A_RXN_14
EXP_A_RXN_15
EXP_A_RXP_0
EXP_A_RXP_1
EXP_A_RXP_2
EXP_A_RXP_3
EXP_A_RXP_4
EXP_A_RXP_5
EXP_A_RXP_6
EXP_A_RXP_7
EXP_A_RXP_8
EXP_A_RXP_9
EXP_A_RXP_10
EXP_A_RXP_11
EXP_A_RXP_12
EXP_A_RXP_13
EXP_A_RXP_14
EXP_A_RXP_15
EXP_A_TXN_0
EXP_A_TXN_1
EXP_A_TXN_2
EXP_A_TXN_3
EXP_A_TXN_4
EXP_A_TXN_5
EXP_A_TXN_6
EXP_A_TXN_7
EXP_A_TXN_8
EXP_A_TXN_9
EXP_A_TXN_10
EXP_A_TXN_11
EXP_A_TXN_12
PCI-EXPRESS GRAPHICS
PCI-EXPRESS GRAPHICS
EXP_A_TXN_13
EXP_A_TXN_14
EXP_A_TXN_15
EXP_A_TXP_0
EXP_A_TXP_1
EXP_A_TXP_2
EXP_A_TXP_3
EXP_A_TXP_4
EXP_A_TXP_5
EXP_A_TXP_6
EXP_A_TXP_7
EXP_A_TXP_8
EXP_A_TXP_9
EXP_A_TXP_10
EXP_A_TXP_11
EXP_A_TXP_12
EXP_A_TXP_13
EXP_A_TXP_14
EXP_A_TXP_15
D40
D38
F34
G38
H34
J38
L34
M38
N34
P38
R34
T38
V34
W38
Y34
AA38
AB34
AC38
D34
F38
G34
H38
J34
L38
M34
N38
P34
R38
T34
V38
W34
Y38
AA34
AB38
F36
G40
H36
J40
L36
M40
N36
P40
R36
T40
V36
W40
Y36
AA40
AB36
AC40
D36
F40
G36
H40
J36
L40
M36
N40
P36
R40
T36
V40
W36
Y40
AA36
AB40
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
R97
12
24D9R2F-L-GP
24D9R2F-L-GP
TXN0
TXN1
TXN2
TXN3
TXN4
TXN5
TXN6
TXN7
TXN8
TXN9
TXN10
TXN11
TXN12
TXN13
TXN14
TXN15
TXP0
TXP1
TXP2
TXP3
TXP4
TXP5
TXP6
TXP7
TXP8
TXP9
TXP10
TXP11
TXP12
TXP13
TXP14
TXP15
PEG_RXP15 38
PEG_RXP14 38
PEG_RXP13 38
PEG_RXP12 38
PEG_RXP11 38
PEG_RXP10 38
PEG_RXP9 38
PEG_RXP8 38
PEG_RXP7 38
PEG_RXP6 38
PEG_RXP5 38
PEG_RXP4 38
PEG_RXP3 38
PEG_RXP2 38
PEG_RXP1 38
PEG_RXP0 38
PEG_RXN15 38
PEG_RXN14 38
PEG_RXN13 38
PEG_RXN12 38
PEG_RXN11 38
PEG_RXN10 38
PEG_RXN9 38
PEG_RXN8 38
PEG_RXN7 38
PEG_RXN6 38
PEG_RXN5 38
PEG_RXN4 38
PEG_RXN3 38
PEG_RXN2 38
PEG_RXN1 38
PEG_RXN0 38
1 2
C492 SCD1U10V2KX-5GPC492 SCD1U10V2KX-5GP
1 2
C161 SCD1U10V2KX-5GPC161 SCD1U10V2KX-5GP
1 2
C494 SCD1U10V2KX-5GPC494 SCD1U10V2KX-5GP
1 2
C163 SCD1U10V2KX-5GPC163 SCD1U10V2KX-5GP
1 2
C496 SCD1U10V2KX-5GPC496 SCD1U10V2KX-5GP
1 2
C165 SCD1U10V2KX-5GPC165 SCD1U10V2KX-5GP
1 2
C498 SCD1U10V2KX-5GPC498 SCD1U10V2KX-5GP
1 2
C167 SCD1U10V2KX-5GPC167 SCD1U10V2KX-5GP
1 2
C500 SCD1U10V2KX-5GPC500 SCD1U10V2KX-5GP
1 2
C169 SCD1U10V2KX-5GPC169 SCD1U10V2KX-5GP
1 2
C502 SCD1U10V2KX-5GPC502 SCD1U10V2KX-5GP
1 2
C171 SCD1U10V2KX-5GPC171 SCD1U10V2KX-5GP
1 2
C504 SCD1U10V2KX-5GPC504 SCD1U10V2KX-5GP
1 2
C173 SCD1U10V2KX-5GPC173 SCD1U10V2KX-5GP
1 2
C506 SCD1U10V2KX-5GPC506 SCD1U10V2KX-5GP
1 2
C175 SCD1U10V2KX-5GPC175 SCD1U10V2KX-5GP
1 2
C491 SCD1U10V2KX-5GPC491 SCD1U10V2KX-5GP
1 2
C160 SCD1U10V2KX-5GPC160 SCD1U10V2KX-5GP
1 2
C493 SCD1U10V2KX-5GPC493 SCD1U10V2KX-5GP
1 2
C162 SCD1U10V2KX-5GPC162 SCD1U10V2KX-5GP
1 2
C495 SCD1U10V2KX-5GPC495 SCD1U10V2KX-5GP
1 2
C164 SCD1U10V2KX-5GPC164 SCD1U10V2KX-5GP
1 2
C497 SCD1U10V2KX-5GPC497 SCD1U10V2KX-5GP
1 2
C166 SCD1U10V2KX-5GPC166 SCD1U10V2KX-5GP
1 2
C499 SCD1U10V2KX-5GPC499 SCD1U10V2KX-5GP
1 2
C168 SCD1U10V2KX-5GPC168 SCD1U10V2KX-5GP
1 2
C501 SCD1U10V2KX-5GPC501 SCD1U10V2KX-5GP
1 2
C170 SCD1U10V2KX-5GPC170 SCD1U10V2KX-5GP
1 2
C503 SCD1U10V2KX-5GPC503 SCD1U10V2KX-5GP
1 2
C172 SCD1U10V2KX-5GPC172 SCD1U10V2KX-5GP
1 2
C505 SCD1U10V2KX-5GPC505 SCD1U10V2KX-5GP
1 2
C174 SCD1U10V2KX-5GPC174 SCD1U10V2KX-5GP
GMCH (2 of 5)
GMCH (2 of 5)
GMCH (2 of 5)
KAI SE
KAI SE
KAI SE
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
E
744Friday, March 24, 2006
744Friday, March 24, 2006
744Friday, March 24, 2006
PEG_TXP15 38
PEG_TXP14 38
PEG_TXP13 38
PEG_TXP12 38
PEG_TXP11 38
PEG_TXP10 38
PEG_TXP9 38
PEG_TXP8 38
PEG_TXP7 38
PEG_TXP6 38
PEG_TXP5 38
PEG_TXP4 38
PEG_TXP3 38
PEG_TXP2 38
PEG_TXP1 38
PEG_TXP0 38
PEG_TXN15 38
PEG_TXN14 38
PEG_TXN13 38
PEG_TXN12 38
PEG_TXN11 38
PEG_TXN10 38
PEG_TXN9 38
PEG_TXN8 38
PEG_TXN7 38
PEG_TXN6 38
PEG_TXN5 38
PEG_TXN4 38
PEG_TXN3 38
PEG_TXN2 38
PEG_TXN1 38
PEG_TXN0 38
NMC
A
4 4
U19D
M_A_DQ[63..0]11
3 3
2 2
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
AJ35
AJ34
AM31
AM33
AJ36
AK35
AJ32
AH31
AN35
AP33
AR31
AP31
AN38
AM36
AM34
AN33
AK26
AL27
AM26
AN24
AK28
AL28
AM24
AP26
AP23
AL22
AP21
AN20
AL23
AP24
AP20
AT21
AR12
AR14
AP13
AP12
AT13
AT12
AL14
AL12
AK9
AN7
AK8
AK7
AP9
AN9
AT5
AL5
AY2
AW2
AP1
AN2
AV2
AT3
AN1
AL2
AG7
AF9
AG4
AF6
AG9
AH6
AF4
AF8
U19D
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
CALISTOGA
CALISTOGA
B
M_B_DQ[63..0]11
AU12
SA_BS_0
AV14
SA_BS_1
BA20
SA_BS_2
AY13
SA_CAS#
AJ33
SA_DM_0
AM35
SA_DM_1
AL26
SA_DM_2
AN22
SA_DM_3
AM14
SA_DM_4
AL9
SA_DM_5
AR3
SA_DM_6
AH4
SA_DM_7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_RAS#
SA_WE#
AK33
AT33
AN28
AM22
AN12
AN8
AP3
AG5
AK32
AU33
AN27
AM21
AM12
AL8
AN3
AH5
AY16
AU14
AW16
BA16
BA17
AU16
AV17
AU17
AW17
AT16
AU13
AT17
AV20
AV12
AW14
AK23
AK24
AY14
SA_RCVENIN#
SA_RCVENOUT#
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_RCVENIN#
SA_RCVENOUT#
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
M_A_CAS# 11,12
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
Place Test PAD Near to Chip
as could as possible
M_A_DQS[7..0] 11
M_A_DQS#[7..0] 11
M_A_RAS# 11,12
TP51 TPAD30TP51 TPAD30
1
TP50 TPAD30TP50 TPAD30
1
M_A_BS#0 11,12
M_A_BS#1 11,12
M_A_BS#2 11,12
M_A_DM[7..0] 11
M_A_A[13..0] 11,12
M_A_WE# 11,12
C
U19E
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
AK39
AJ37
AP39
AR41
AJ38
AK38
AN41
AP41
AT40
AV41
AU38
AV38
AP38
AR40
AW38
AY38
BA38
AV36
AR36
AP36
BA36
AU36
AP35
AP34
AY33
BA33
AT31
AU29
AU31
AW31
AV29
AW29
AM19
AL19
AP14
AN14
AN17
AM16
AP15
AL15
AJ11
AH10
AN10
AK13
AH11
AK10
BA10
AW10
AW4
AY10
AW5
BA4
AY9
AY5
AV4
AR5
AK4
AK3
AT4
AK5
AJ9
AJ8
AJ5
AJ3
U19E
SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
CALISTOGA
CALISTOGA
D
AT24
SB_BS_0
AV23
SB_BS_1
AY28
SB_BS_2
AR24
SB_CAS#
AK36
SB_DM_0
AR38
SB_DM_1
AT36
SB_DM_2
BA31
SB_DM_3
AL17
SB_DM_4
AH8
SB_DM_5
BA5
SB_DM_6
AN4
SB_DM_7
AM39
SB_DQS_0
AT39
SB_DQS_1
AU35
SB_DQS_2
AR29
SB_DQS_3
AR16
SB_DQS_4
AR10
SB_DQS_5
AR7
SB_DQS_6
AN5
SB_DQS_7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_RAS#
SB_WE#
AM40
AU39
AT35
AP29
AP16
AT10
AT7
AP5
AY23
AW24
AY24
AR28
AT27
AT28
AU27
AV28
AV27
AW27
AV24
BA27
AY27
AR23
AU23
AK16
AK18
AR27
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
SB_RCVENIN#
SB_RCVENOUT#
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
M_B_CAS# 11,12
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7M_A_DQS5
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
SB_RCVENIN#
SB_RCVENOUT#
Place Test PAD Near to Chip
ascould as possible
E
M_B_BS#0 11,12
M_B_BS#1 11,12
M_B_BS#2 11,12
M_B_DM[7..0] 11
M_B_DQS[7..0] 11
M_B_DQS#[7..0] 11
M_B_A[13..0] 11,12
M_B_RAS# 11,12
1
1
M_B_WE# 11,12
TP52 TPAD30TP52 TPAD30
TP49 TPAD30TP49 TPAD30
1 1
A
B
C
D
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet of
Date: Sheet of
GMCH (3 of 5)
GMCH (3 of 5)
GMCH (3 of 5)
KAI SE
KAI SE
KAI SE
844Friday, March 24, 2006
844Friday, March 24, 2006
844Friday, March 24, 2006
E
of
NMC
A
4 4
1D5V_S0
3 3
2 2
1 1
L38
L38
1 2
IND-1D2UH-5-GP
IND-1D2UH-5-GP
DY
DY
L15
L15
1 2
IND-1D2UH-5-GP
IND-1D2UH-5-GP
DY
DY
L18
L18
1 2
IND-1D2UH-5-GP
IND-1D2UH-5-GP
L19
L19
1 2
IND-1D2UH-5-GP
IND-1D2UH-5-GP
1D5V_AUX
R373
R373
12
0R0805-PAD
0R0805-PAD
C538
C538
SCD1U10V2MX-3GP
SCD1U10V2MX-3GP
12
12
12
12
12
Discrete Dummy
C524
C524
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
DY
DY
C151
C151
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
DY
DY
C298
C298
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
C301
C301
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
1D5V_S0
1D5V_DPLLA_S0
12
C525
C525
SCD1U10V2MX-3GP
SCD1U10V2MX-3GP
DY
DY
1D5V_DPLLB_S0
12
C153
C153
SCD1U10V2MX-3GP
SCD1U10V2MX-3GP
DY
DY
1D5V_HPLL_S0
12
C299
C299
SCD1U10V2MX-3GP
SCD1U10V2MX-3GP
1D5V_MPLL_S0
12
C300
C300
SCD1U10V2MX-3GP
SCD1U10V2MX-3GP
A
1D5V_S0
B
1D5V_S0 1D5V_PCIE_S0
R78 0R3-0-U-GPR78 0R3-0-U-GP
B
R98
R98
0R5J-6-GP
0R5J-6-GP
ST100U4VBM-L-GP
ST100U4VBM-L-GP
1D5V_3GPLL_S0
12
12
12
TC2
TC2
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
12
C131
C131
SCD1U10V2MX-3GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SCD1U10V2MX-3GP
3D3V_S0
R372 0R3-0-U-GPR372 0R3-0-U-GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
12
C510
C510
C152
C152
12
C176
C176
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
2D5V_S0
12
C156
C156
SCD1U10V2MX-3GP
SCD1U10V2MX-3GP
SCD1U10V2MX-3GP
SCD1U10V2MX-3GP
12
12
C526
C526
C
12
C154
C154
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
12
1D05V_S0
12
C528
C528
12
C527
C527
SCD1U10V2MX-3GP
SCD1U10V2MX-3GP
C
1D5V_DPLLA_S0
1D5V_DPLLB_S0
1D5V_HPLL_S0
1D5V_MPLL_S0
1D5V_S0
1D5V_S0
1D5V_S0
1D5V_S0
1D5V_AUX
H22
C30
B30
A30
AJ41
AB41
Y41
V41
R41
N41
AC33
G41
H41
F21
E21
G21
B26
C39
AF1
A38
B39
AF2
H20
G20
E19
F19
C20
D20
E20
F20
AH1
AH2
A28
B28
C28
D21
A23
B23
B25
H19
AK31
AF31
AE31
AC31
AL30
AK30
AJ30
AH30
AG30
AF30
AE30
AD30
AC30
AG29
AF29
AE29
AD29
AC29
AG28
AF28
AE28
AH22
AJ21
AH21
AJ20
AH20
AH19
P19
P16
AH15
P15
AH14
AG14
AF14
AE14
Y14
AF13
AE13
AF12
AE12
AD12
L41
U19H
U19H
VCCSYNC
VCC_TXLVDS0
VCC_TXLVDS1
VCC_TXLVDS2
VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6
VCCA_3GPLL
VCCA_3GBG
VSSA_3GBG
VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_LVDS
VSSA_LVDS
VCCA_MPLL
VCCA_TVBG
VSSA_TVBG
VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1
VCCD_HMPLL0
VCCD_HMPLL1
VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2
VCCD_TVDAC
VCC_HV0
VCC_HV1
VCC_HV2
VCCD_QTVDAC
VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8
VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VCCAUX29
VCCAUX30
VCCAUX31
VCCAUX32
VCCAUX33
VCCAUX34
VCCAUX35
VCCAUX36
VCCAUX37
VCCAUX38
VCCAUX39
VCCAUX40
POWER
POWER
CALISTOGA
CALISTOGA
D
AC14
VTT_0
AB14
VTT_1
W14
VTT_2
V14
VTT_3
T14
VTT_4
R14
VTT_5
P14
VTT_6
N14
VTT_7
M14
VTT_8
L14
VTT_9
AD13
VTT_10
AC13
VTT_11
AB13
VTT_12
AA13
VTT_13
Y13
VTT_14
W13
VTT_15
V13
VTT_16
U13
VTT_17
T13
VTT_18
R13
VTT_19
N13
VTT_20
M13
VTT_21
L13
VTT_22
AB12
VTT_23
AA12
VTT_24
Y12
VTT_25
W12
VTT_26
V12
VTT_27
U12
VTT_28
T12
VTT_29
R12
VTT_30
P12
VTT_31
N12
VTT_32
M12
VTT_33
L12
VTT_34
R11
VTT_35
P11
VTT_36
N11
VTT_37
M11
VTT_38
R10
VTT_39
P10
VTT_40
N10
VTT_41
M10
VTT_42
P9
VTT_43
N9
VTT_44
M9
VTT_45
R8
VTT_46
P8
VTT_47
N8
VTT_48
M8
VTT_49
P7
VTT_50
N7
VTT_51
M7
VTT_52
R6
VTT_53
P6
VTT_54
M6
VTT_55
VTT_56
VTT_57
VTT_58
VTT_59
VTT_60
VTT_61
VTT_62
VTT_63
VTT_64
VTT_65
VTT_66
VTT_67
VTT_68
VTT_69
VTT_70
VTT_71
VTT_72
VTT_73
VTT_74
VTT_75
VTT_76
D
VCCP_GMCH_CAP3
A6
R5
P5
N5
M5
P4
N4
M4
R3
P3
N3
M3
R2
P2
M2
VCCP_GMCH_CAP2
D2
VCCP_GMCH_CAP1
AB1
R1
P1
SCD47U16V3ZY-3GP
SCD47U16V3ZY-3GP
N1
M1
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet
12
SCD1U10V2MX-3GP
SCD1U10V2MX-3GP
C292
C292
12
SCD47U16V3ZY-3GP
SCD47U16V3ZY-3GP
12
C297
C297
GMCH (4 of 5)
GMCH (4 of 5)
GMCH (4 of 5)
KAI SE
KAI SE
KAI SE
E
1D05V_S0
12
12
C529
C529
SC2D2U10V3ZY-1GP
SC2D2U10V3ZY-1GP
12
C293
C293
SCD22U16V3ZY-GP
SCD22U16V3ZY-GP
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
C540
C540
E
944Friday, March 24, 2006
944Friday, March 24, 2006
944Friday, March 24, 2006
C295
C295
SC4D7U10V5ZY-3GP
SC4D7U10V5ZY-3GP
of
NMC
A
U19G
1D05V_S0
4 4
3 3
2 2
1 1
AA33
W33
AA32
W32
M32
AA31
W31
M31
AA30
W30
M30
AA29
W29
M29
AB28
AA28
M28
M27
M25
M24
AB23
AA23
M23
AC22
AB22
W22
M22
AC21
AA21
W21
M21
AC20
AB20
W20
M20
AB19
AA19
M19
M18
M17
M16
U19G
VCC_0
VCC_1
P33
VCC_2
N33
VCC_3
L33
VCC_4
J33
VCC_5
VCC_6
Y32
VCC_7
VCC_8
V32
VCC_9
P32
VCC_10
N32
VCC_11
VCC_12
L32
VCC_13
J32
VCC_14
VCC_15
VCC_16
V31
VCC_17
T31
VCC_18
R31
VCC_19
P31
VCC_20
N31
VCC_21
VCC_22
VCC_23
Y30
VCC_24
VCC_25
V30
VCC_26
U30
VCC_27
T30
VCC_28
R30
VCC_29
P30
VCC_30
N30
VCC_31
VCC_32
L30
VCC_33
VCC_34
Y29
VCC_35
VCC_36
V29
VCC_37
U29
VCC_38
R29
VCC_39
P29
VCC_40
VCC_41
L29
VCC_42
VCC_43
VCC_44
Y28
VCC_45
V28
VCC_46
U28
VCC_47
T28
VCC_48
R28
VCC_49
P28
VCC_50
N28
VCC_51
VCC_52
L28
VCC_53
P27
VCC_54
N27
VCC_55
VCC_56
L27
VCC_57
P26
VCC_58
N26
VCC_59
L26
VCC_60
N25
VCC_61
VCC_62
L25
VCC_63
P24
VCC_64
N24
VCC_65
VCC_66
VCC_67
VCC_68
Y23
P23
N23
Y22
P22
N22
N21
Y20
P20
N20
Y19
N19
N18
P17
N17
N16
VCC_69
VCC_70
VCC_71
VCC_72
L23
VCC_73
VCC_74
VCC_75
VCC_76
VCC_77
VCC_78
VCC_79
VCC_80
L22
VCC_81
VCC_82
VCC_83
VCC_84
VCC_85
VCC_86
L21
VCC_87
VCC_88
VCC_89
VCC_90
VCC_91
VCC_92
VCC_93
VCC_94
L20
VCC_95
VCC_96
VCC_97
VCC_98
VCC_99
VCC_100
L19
VCC_101
VCC_102
VCC_103
L18
VCC_104
VCC_105
VCC_106
VCC_107
VCC_108
VCC_109
L16
VCC_110
VCC
VCC
A
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36
VCC_SM_37
VCC_SM_38
VCC_SM_39
VCC_SM_40
VCC_SM_41
VCC_SM_42
VCC_SM_43
VCC_SM_44
VCC_SM_45
VCC_SM_46
VCC_SM_47
VCC_SM_48
VCC_SM_49
VCC_SM_50
VCC_SM_51
VCC_SM_52
VCC_SM_53
VCC_SM_54
VCC_SM_55
VCC_SM_56
VCC_SM_57
VCC_SM_58
VCC_SM_59
VCC_SM_60
VCC_SM_61
VCC_SM_62
VCC_SM_63
VCC_SM_64
VCC_SM_65
VCC_SM_66
VCC_SM_67
VCC_SM_68
VCC_SM_69
VCC_SM_70
VCC_SM_71
VCC_SM_72
VCC_SM_73
VCC_SM_74
VCC_SM_75
VCC_SM_76
VCC_SM_77
VCC_SM_78
VCC_SM_79
VCC_SM_80
VCC_SM_81
VCC_SM_82
VCC_SM_83
VCC_SM_84
VCC_SM_85
VCC_SM_86
VCC_SM_87
VCC_SM_88
VCC_SM_89
VCC_SM_90
VCC_SM_91
VCC_SM_92
VCC_SM_93
VCC_SM_94
VCC_SM_95
VCC_SM_96
VCC_SM_97
VCC_SM_98
VCC_SM_99
VCC_SM_100
VCC_SM_101
VCC_SM_102
VCC_SM_103
VCC_SM_104
VCC_SM_105
VCC_SM_106
VCC_SM_107
VCC_SM_0
VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
AU41
AT41
AM41
AU40
BA34
AY34
AW34
AV34
AU34
AT34
AR34
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6
AR6
AP6
AN6
AL6
AK6
AJ6
AV1
AJ1
VCCSM_LF4
VCCSM_LF5
VCCSM_LF3
VCCSM_LF2
VCCSM_LF1
CALISTOGA
CALISTOGA
12
12
C177
C177
C178
C178
SCD47U16V3ZY-3GP
SCD47U16V3ZY-3GP
SCD47U16V3ZY-3GP
SCD47U16V3ZY-3GP
12
C250
C250
SCD47U16V3ZY-3GP
SCD47U16V3ZY-3GP
1D05V_S0
12
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
1 2
1 2
B
U19F
U19F
AD27
VCC_NCTF0
AC27
VCC_NCTF1
AB27
VCC_NCTF2
AA27
VCC_NCTF3
Y27
VCC_NCTF4
W27
VCC_NCTF5
V27
VCC_NCTF6
U27
VCC_NCTF7
T27
VCC_NCTF8
R27
VCC_NCTF9
AD26
VCC_NCTF10
AC26
VCC_NCTF11
AB26
VCC_NCTF12
AA26
VCC_NCTF13
Y26
VCC_NCTF14
W26
VCC_NCTF15
V26
VCC_NCTF16
U26
VCC_NCTF17
T26
VCC_NCTF18
R26
VCC_NCTF19
AD25
VCC_NCTF20
AC25
VCC_NCTF21
AB25
VCC_NCTF22
AA25
VCC_NCTF23
Y25
VCC_NCTF24
W25
VCC_NCTF25
V25
VCC_NCTF26
U25
VCC_NCTF27
T25
VCC_NCTF28
R25
VCC_NCTF29
AD24
VCC_NCTF30
AC24
VCC_NCTF31
AB24
VCC_NCTF32
AA24
VCC_NCTF33
Y24
VCC_NCTF34
W24
VCC_NCTF35
V24
VCC_NCTF36
U24
VCC_NCTF37
T24
VCC_NCTF38
R24
VCC_NCTF39
AD23
VCC_NCTF40
V23
VCC_NCTF41
U23
VCC_NCTF42
T23
VCC_NCTF43
R23
VCC_NCTF44
AD22
VCC_NCTF45
V22
VCC_NCTF46
U22
VCC_NCTF47
T22
VCC_NCTF48
R22
VCC_NCTF49
AD21
VCC_NCTF50
V21
VCC_NCTF51
U21
VCC_NCTF52
T21
VCC_NCTF53
R21
VCC_NCTF54
AD20
VCC_NCTF55
V20
VCC_NCTF56
U20
VCC_NCTF57
T20
VCC_NCTF58
R20
VCC_NCTF59
AD19
VCC_NCTF60
V19
VCC_NCTF61
U19
VCC_NCTF62
T19
VCC_NCTF63
AD18
VCC_NCTF64
AC18
VCC_NCTF65
AB18
VCC_NCTF66
AA18
VCC_NCTF67
Y18
VCC_NCTF68
W18
VCC_NCTF69
V18
VCC_NCTF70
U18
VCC_NCTF71
T18
VCC_NCTF72
12
C539
C539
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
12
C195
C195
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
PLACE IN CAVITY PLACE IN CAVITY
C303 SCD47U16V3ZY-3GPC303 SCD47U16V3ZY-3GP
C302 SCD47U16V3ZY-3GPC302 SCD47U16V3ZY-3GP
B
12
C533
C533
SC1U10V3ZY-6GP
SC1U10V3ZY-6GP
SCD22U16V3ZY-GP
SCD22U16V3ZY-GP
1D8V_S3
12
C249
C249
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
C541
C541
NCTF
NCTF
CALISTOGA
CALISTOGA
12
C531
C531
SCD22U16V3ZY-GP
SCD22U16V3ZY-GP
12
C280
C280
SCD47U16V3ZY-3GP
SCD47U16V3ZY-3GP
PLACE NEAR PIN BA15
VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8
VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12
VCCAUX_NCTF0
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8
VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36
VCCAUX_NCTF37
VCCAUX_NCTF38
VCCAUX_NCTF39
VCCAUX_NCTF40
VCCAUX_NCTF41
VCCAUX_NCTF42
VCCAUX_NCTF43
VCCAUX_NCTF44
VCCAUX_NCTF45
VCCAUX_NCTF46
VCCAUX_NCTF47
VCCAUX_NCTF48
VCCAUX_NCTF49
VCCAUX_NCTF50
VCCAUX_NCTF51
VCCAUX_NCTF52
VCCAUX_NCTF53
VCCAUX_NCTF54
VCCAUX_NCTF55
VCCAUX_NCTF56
VCCAUX_NCTF57
12
C532
C532
SCD22U16V3ZY-GP
SCD22U16V3ZY-GP
AE27
AE26
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AC17
Y17
U17
AG27
AF27
AG26
AF26
AG25
AF25
AG24
AF24
AG23
AF23
AG22
AF22
AG21
AF21
AG20
AF20
AG19
AF19
R19
AG18
AF18
R18
AG17
AF17
AE17
AD17
AB17
AA17
W17
V17
T17
R17
AG16
AF16
AE16
AD16
AC16
AB16
AA16
Y16
W16
V16
U16
T16
R16
AG15
AF15
AE15
AD15
AC15
AB15
AA15
Y15
W15
V15
U15
T15
R15
12
C530
C530
12
TC6
TC6
ST220U2D5VBM-LGP
ST220U2D5VBM-LGP
C
1D5V_AUX
12
TC5
TC5
ST220U2D5VBM-LGP
ST220U2D5VBM-LGP
C
AC41
AA41
W41
P41
M41
AV40
AP40
AN40
AK40
AJ40
AH40
AG40
AF40
AE40
B40
AY39
AW39
AV39
AR39
AN39
AJ39
AC39
AB39
AA39
Y39
W39
V39
R39
P39
N39
M39
H39
G39
D39
AT38
AM38
AH38
AG38
AF38
AE38
C38
AK37
AH37
AB37
AA37
Y37
W37
V37
R37
P37
N37
M37
H37
G37
D37
AY36
AW36
AN36
AH36
AG36
AF36
AE36
AC36
C36
B36
BA35
AV35
AR35
AH35
AB35
AA35
Y35
W35
V35
R35
P35
N35
M35
H35
G35
D35
AN34
T41
J41
F41
T39
L39
J39
F39
T37
L37
J37
F37
T35
L35
J35
F35
U19I
U19I
VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
CALISTOGA
CALISTOGA
VSS
VSS
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
D
AK34
AG34
AF34
AE34
AC34
C34
AW33
AV33
AR33
AE33
AB33
Y33
V33
T33
R33
M33
H33
G33
F33
D33
B33
AH32
AG32
AF32
AE32
AC32
AB32
G32
B32
AY31
AV31
AN31
AJ31
AG31
AB31
Y31
AB30
E30
AT29
AN29
AB29
T29
N29
K29
G29
E29
C29
B29
A29
BA28
AW28
AU28
AP28
AM28
AD28
AC28
W28
J28
E28
AP27
AM27
AK27
J27
G27
F27
C27
B27
AN26
M26
K26
F26
D26
AK25
P25
K25
H25
E25
D25
A25
BA24
AU24
AL24
AW23
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet of
D
Date: Sheet of
AT23
AN23
AM23
AH23
AC23
W23
AA22
BA21
AV21
AR21
AN21
AL21
AB21
AW20
AR20
AM20
AA20
AN19
AC19
W19
AH18
AY17
AR17
AP17
AM17
AK17
AV16
AN16
AL16
AN15
AM15
AK15
M15
BA14
AT14
AK14
AD14
AA14
U14
H14
AV13
AR13
AN13
AM13
AL13
AG13
D13
AY12
AC12
H12
AD11
AA11
K23
F23
C23
K22
G22
F22
E22
D22
A22
Y21
P21
K21
H21
C21
K20
B20
A20
K19
G19
C19
P18
H18
D18
A18
F16
C16
N15
L15
B15
A15
K14
E14
P13
F13
B13
K12
E12
Y11
U19J
U19J
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
J23
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
J21
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
J16
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS
VSS
CALISTOGA
CALISTOGA
GMCH (5 of 5)
GMCH (5 of 5)
GMCH (5 of 5)
KAI
KAI
KAI
E
J11
VSS_273
D11
VSS_274
B11
VSS_275
AV10
VSS_276
AP10
VSS_277
AL10
VSS_278
AJ10
VSS_279
AG10
VSS_280
AC10
VSS_281
W10
VSS_282
U10
VSS_283
BA9
VSS_284
AW9
VSS_285
AR9
VSS_286
AH9
VSS_287
AB9
VSS_288
Y9
VSS_289
R9
VSS_290
G9
VSS_291
E9
VSS_292
A9
VSS_293
AG8
VSS_294
AD8
VSS_295
AA8
VSS_296
U8
VSS_297
K8
VSS_298
C8
VSS_299
BA7
VSS_300
AV7
VSS_301
AP7
VSS_302
AL7
VSS_303
AJ7
VSS_304
AH7
VSS_305
AF7
VSS_306
AC7
VSS_307
R7
VSS_308
G7
VSS_309
D7
VSS_310
AG6
VSS_311
AD6
VSS_312
AB6
VSS_313
Y6
VSS_314
U6
VSS_315
N6
VSS_316
K6
VSS_317
H6
VSS_318
B6
VSS_319
AV5
VSS_320
AF5
VSS_321
AD5
VSS_322
AY4
VSS_323
AR4
VSS_324
AP4
VSS_325
AL4
VSS_326
AJ4
VSS_327
Y4
VSS_328
U4
VSS_329
R4
VSS_330
J4
VSS_331
F4
VSS_332
C4
VSS_333
AY3
VSS_334
AW3
VSS_335
AV3
VSS_336
AL3
VSS_337
AH3
VSS_338
AG3
VSS_339
AF3
VSS_340
AD3
VSS_341
AC3
VSS_342
AA3
VSS_343
G3
VSS_344
AT2
VSS_345
AR2
VSS_346
AP2
VSS_347
AK2
VSS_348
AJ2
VSS_349
AD2
VSS_350
AB2
VSS_351
Y2
VSS_352
U2
VSS_353
T2
VSS_354
N2
VSS_355
J2
VSS_356
H2
VSS_357
F2
VSS_358
C2
VSS_359
AL1
VSS_360
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
10 44Friday, March 24, 2006
10 44Friday, March 24, 2006
10 44Friday, March 24, 2006
E
of
SE
SE
SE
NMC
A
DM1
M_A_A[13..0]8,12
4 4
M_A_BS#28,12
M_A_BS#08,12
M_A_BS#18,12
M_A_DQ[63..0]8
3 3
2 2
M_A_DQS#[7..0]8
M_A_DQS[7..0]8
1 1
M_ODT07,12
M_ODT17,12
DDR_VREF_S3 DDR_VREF_S3
C93
SC2D2U10V3ZY-1GP
SC2D2U10V3ZY-1GP
C93
12
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
12
BC1
BC1
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
102
A0
101
A1
100
A2
99
A3
98
A4
97
A5
94
A6
92
A7
93
A8
91
A9
105
A10/AP
90
A11
89
A12
116
A13
86
A14
84
A15
85
A16/BA2
107
BA0
106
BA1
5
DQ0
7
DQ1
17
DQ2
19
DQ3
4
DQ4
6
DQ5
14
DQ6
16
DQ7
23
DQ8
25
DQ9
35
DQ10
37
DQ11
20
DQ12
22
DQ13
36
DQ14
38
DQ15
43
DQ16
45
DQ17
55
DQ18
57
DQ19
44
DQ20
46
DQ21
56
DQ22
58
DQ23
61
DQ24
63
DQ25
73
DQ26
75
DQ27
62
DQ28
64
DQ29
74
DQ30
76
DQ31
123
DQ32
125
DQ33
135
DQ34
137
DQ35
124
DQ36
126
DQ37
134
DQ38
136
DQ39
141
DQ40
143
DQ41
151
DQ42
153
DQ43
140
DQ44
142
DQ45
152
DQ46
154
DQ47
157
DQ48
159
DQ49
173
DQ50
175
DQ51
158
DQ52
160
DQ53
174
DQ54
176
DQ55
179
DQ56
181
DQ57
189
DQ58
191
DQ59
180
DQ60
182
DQ61
192
DQ62
194
DQ63
11
DQS0#
29
DQS1#
49
DQS2#
68
DQS3#
129
DQS4#
146
DQS5#
167
DQS6#
186
DQS7#
13
DQS0
31
DQS1
51
DQS2
70
DQS3
131
DQS4
148
DQS5
169
DQS6
188
DQS7
114
OTD0
119
OTD1
1
VREF
2
VSS
202
GND
MH1
MH1
DDR2-200P-20-GP
DDR2-200P-20-GP
DM1
NC#163/TEST
NORMAL TYPE
A
B
108
RAS#
109
WE#
113
CAS#
110
CS0#
115
CS1#
79
CKE0
80
CKE1
30
CK0
32
CK0#
164
CK1
166
CK1#
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
SDA
SCL
VDDSPD
SA0
SA1
NC#50
NC#69
NC#83
NC#120
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GND
MH2
M_A_DM0
10
M_A_DM1
26
M_A_DM2
52
M_A_DM3
67
M_A_DM4
130
M_A_DM5
147
M_A_DM6
170
M_A_DM7
185
SMBD_ICH
195
SMBC_ICH
197
199
198
200
50
69
83
120
163
81
82
87
88
95
96
103
104
111
112
117
118
3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
145
149
150
155
156
161
162
165
168
171
172
177
178
183
184
187
190
193
196
201
MH2
Main Source : 62.10017.A41
Second Source : 62.10017.661
PM_EXTTS#07
10KR2J-3-GP
10KR2J-3-GP
B
R403
R403
1D8V_S3
M_A_RAS# 8,12
M_A_WE# 8,12
M_A_CAS# 8,12
M_CS0# 7,12
M_CS1# 7,12
M_CKE0 7,12
M_CKE1 7,12
M_CLK_DDR0 7
M_CLK_DDR#0 7
M_CLK_DDR1 7
M_CLK_DDR#1 7
M_A_DM[7..0] 8
12
12
R400
R400
10KR2J-3-GP
10KR2J-3-GP
3D3V_S0
12
BC9
BC9
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SC2D2U10V3ZY-1GP
SC2D2U10V3ZY-1GP
C
M_B_A[13..0]8,12
M_B_BS#28,12
M_B_BS#08,12
M_B_BS#18,12
M_B_DQ[63..0]8
M_B_DQS#[7..0]8
M_B_DQS[7..0]8
M_ODT27,12
M_ODT37,12
12
C94
C94
Main Source : 62.10017.A51
Second Source : 62.10017.A61
12
BC2
BC2
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
MH1
DM2
DM2
102
A0
101
A1
100
A2
99
A3
98
A4
97
A5
94
A6
92
A7
93
A8
91
A9
105
A10/AP
90
A11
89
A12
116
A13
86
A14
84
A15
85
A16/BA2
107
BA0
106
BA1
5
DQ0
7
DQ1
17
DQ2
19
DQ3
4
DQ4
6
DQ5
14
DQ6
16
DQ7
23
DQ8
25
DQ9
35
DQ10
37
DQ11
20
DQ12
22
DQ13
36
DQ14
38
DQ15
43
DQ16
45
DQ17
55
DQ18
57
DQ19
44
DQ20
46
DQ21
56
DQ22
58
DQ23
61
DQ24
63
DQ25
73
DQ26
75
DQ27
62
DQ28
64
DQ29
74
DQ30
76
DQ31
123
DQ32
125
DQ33
135
DQ34
137
DQ35
124
DQ36
126
DQ37
134
DQ38
136
DQ39
141
DQ40
143
DQ41
151
DQ42
153
DQ43
140
DQ44
142
DQ45
152
DQ46
154
DQ47
157
DQ48
159
DQ49
173
DQ50
175
DQ51
158
DQ52
160
DQ53
174
DQ54
176
DQ55
179
DQ56
181
DQ57
189
DQ58
191
DQ59
180
DQ60
182
DQ61
192
DQ62
194
DQ63
11
DQS0#
29
DQS1#
49
DQS2#
68
DQS3#
129
DQS4#
146
DQS5#
167
DQS6#
186
DQS7#
13
DQS0
31
DQS1
51
DQS2
70
DQS3
131
DQS4
148
DQS5
169
DQS6
188
DQS7
114
OTD0
119
OTD1
1
VREF
2
VSS
202
GND
MH1
High 9.2mm
DDR2-200P-21-GP-U
DDR2-200P-21-GP-U
D
108
RAS#
109
WE#
113
CAS#
110
CS0#
115
CS1#
79
CKE0
80
CKE1
30
CK0
32
CK0#
164
CK1
166
CK1#
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
SDA
SCL
VDDSPD
SA0
SA1
NC#50
NC#69
NC#83
NC#120
NC#163/TEST
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NORMAL TYPE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GND
MH2
D
10
26
52
67
130
147
170
185
195
197
199
198
200
50
69
83
120
163
81
82
87
88
95
96
103
104
111
112
117
118
3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
145
149
150
155
156
161
162
165
168
171
172
177
178
183
184
187
190
193
196
201
MH2
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
PM_EXTTS#0
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
12
10KR2J-3-GP
10KR2J-3-GP
1D8V_S3
M_B_RAS# 8,12
M_B_WE# 8,12
M_B_CAS# 8,12
M_CS2# 7,12
M_CS3# 7,12
M_CKE2 7,12
M_CKE3 7,12
M_CLK_DDR3 7
M_CLK_DDR#3 7
M_CLK_DDR2 7
M_CLK_DDR#2 7
M_B_DM[7..0] 8
SMBD_ICH 3,19
SMBC_ICH 3,19
R404
R404
1 2
10KR2J-3-GP
10KR2J-3-GP
R405
R405
3D3V_S0
DDR2 Socket
DDR2 Socket
DDR2 Socket
E
3D3V_S0
12
BC10
BC10
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
KAI SE
KAI SE
KAI SE
E
of
of
of
11 44Thursday, April 13, 2006
11 44Thursday, April 13, 2006
11 44Thursday, April 13, 2006
NMC
A
B
C
D
PARALLEL TERMINATION Decoupling Capacitor
E
DDR_VREF_S0
4 4
3 3
2 2
1 1
A
Put decap near power(0.9V) and pull-up resistor
RN13
RN13
M_B_A11
1
8
7
6
SRN56J-3-GP
SRN56J-3-GP
8
7
6
SRN56J-3-GP
SRN56J-3-GP
1
2 3
1
2 3
RN17 SRN56J-4-GPRN17 SRN56J-4-GP
8
7
6
SRN56J-3-GP
SRN56J-3-GP
8
7
6
SRN56J-3-GP
SRN56J-3-GP
8
7
6
SRN56J-3-GP
SRN56J-3-GP
8
7
6
SRN56J-3-GP
SRN56J-3-GP
8
7
6
SRN56J-3-GP
SRN56J-3-GP
8
7
6
SRN56J-3-GP
SRN56J-3-GP
8
7
6
SRN56J-3-GP
SRN56J-3-GP
8
7
6
SRN56J-3-GP
SRN56J-3-GP
8
7
6
SRN56J-3-GP
SRN56J-3-GP
2
3
45
RN12
RN12
8
7
6
SRN56J-3-GP
SRN56J-3-GP
RN15
RN15
1
2
3
45
RN11
RN11
4
SRN56J-4-GP
SRN56J-4-GP
4
RN16
RN16
1
2
3
45
RN14
RN14
1
2
3
45
RN18
RN18
1
2
3
45
RN44
RN44
1
2
3
45
RN42
RN42
1
2
3
45
RN9
RN9
1
2
3
45
RN10
RN10
1
2
3
45
RN43
RN43
1
2
3
45
RN8
RN8
1
2
3
45
M_B_A6
M_B_A7
M_B_A0
1
M_B_A2
2
M_B_A1
3
M_B_A4
45
M_B_A5
M_B_A8
M_B_A3
M_B_A10
M_B_A13
M_A_A10
M_B_A12
M_B_A9
M_A_A13
M_A_A4
M_A_A2
M_A_A0
M_A_A12
M_A_A9
M_A_A11
M_A_A7
M_A_A6
M_A_A8
M_A_A5
M_A_A3
M_A_A1
M_CKE3 7,11
M_CS2# 7,11
M_ODT1 7,11
M_B_BS#0 8,11
M_B_WE# 8,11
M_B_RAS# 8,11
M_B_BS#1 8,11
M_CKE2 7,11
M_B_BS#2 8,11
M_CS3# 7,11
M_B_CAS# 8,11
M_ODT2 7,11
M_ODT3 7,11
M_A_RAS# 8,11
M_CS0# 7,11
M_ODT0 7,11
M_A_BS#1 8,11
M_A_WE# 8,11
M_A_BS#0 8,11
M_CS1# 7,11
M_A_CAS# 8,11
M_CKE0 7,11
M_A_BS#2 8,11
M_CKE1 7,11
B
M_A_A[13..0] 8,11
M_B_A[13..0] 8,11
DDR_VREF_S0
1D8V_S3
1D8V_S3
12
C182
C182
DY
DY
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C208
C208
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C535
C535
SC2D2U10V3ZY-1GP
SC2D2U10V3ZY-1GP
12
C252
C252
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
Put decap near power(0.9V)
and pull-up resistor
12
12
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C254
C254
DY
DY
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C207
C207
DY
DY
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C516
C516
SC2D2U10V3ZY-1GP
SC2D2U10V3ZY-1GP
12
C518
C518
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C197
C197
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C
12
C534
C534
C214
C214
C511
C511
DY
DY
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
DY
DY
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C514
C514
DY
DY
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
Place these Caps near DM1
12
C199
C199
SC2D2U10V3ZY-1GP
SC2D2U10V3ZY-1GP
12
12
C517
C517
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C209
C209
Place these Caps near DM2
12
C202
C202
SC2D2U10V3ZY-1GP
SC2D2U10V3ZY-1GP
12
12
C210
C210
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C183
C183
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C515
C515
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C200
C200
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C201
C201
SC2D2U10V3ZY-1GP
SC2D2U10V3ZY-1GP
C196
C196
12
C253
C253
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C212
C212
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C185
C185
SC2D2U10V3ZY-1GP
SC2D2U10V3ZY-1GP
12
C205
C205
DY
DY
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C213
C213
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
12
C198
C198
SC2D2U10V3ZY-1GP
SC2D2U10V3ZY-1GP
12
C204
C204
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C256
C256
DY
DY
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C257
C257
SC2D2U10V3ZY-1GP
SC2D2U10V3ZY-1GP
D
12
C181
C181
DY
DY
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C258
C258
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
12
C251
C251
SC2D2U10V3ZY-1GP
SC2D2U10V3ZY-1GP
12
12
C203
C203
SC2D2U10V3ZY-1GP
SC2D2U10V3ZY-1GP
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
12
C513
C513
DY
DY
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C211
C211
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
DDR2 Termination Resistor
DDR2 Termination Resistor
DDR2 Termination Resistor
12
C512
C512
DY
DY
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C186
C186
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C184
C184
C206
C206
DY
DY
DY
DY
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
12
C255
C255
C215
C215
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
KAI SE
KAI SE
KAI SE
12 44Friday, March 24, 2006
12 44Friday, March 24, 2006
12 44Friday, March 24, 2006
of
of
E
of
NMC
A
CRT I/F & CONNECTOR
Layout Note:
Place these resistors
close to the CRT-out
connector
4 4
VGA_RED39
VGA_GREEN39
VGA_BLUE39
150R2F-1-GP
150R2F-1-GP
R15
R15
12
R16
R16
150R2F-1-GP
150R2F-1-GP
12
12
12
R5
R5
150R2F-1-GP
150R2F-1-GP
SC10P50V2JN-4GP
SC10P50V2JN-4GP
C23
C23
Layout Note:
* Must be a ground return path between this ground and the ground on
the VGA connector.
Pi-filter & 150 Ohm pull-down resistors should be as close as to CRT
3 3
CONN. RGB will hit 75 Ohm first, pi-filter, then CRT CONN.
Hsync & Vsync level shift
VGA_HSYNC15,39
14
4
2 2
VGA_VSYNC15,39
TV OUT CONN
VGA_TV_CRMA39
Layout Note:
Place this 2 resistors
close to the TV-out
connector
VGA_TV_COMP39
1 1
VGA_TV_LUMA39
Place this 2 resistors
close to the TV-out
connector
R1
R1
150R2F-1-GP
150R2F-1-GP
150R2F-1-GP
150R2F-1-GP
150R2F-1-GP
150R2F-1-GP
12
SC82P50V2JN-3GP
SC82P50V2JN-3GP
12
R2
R2
12
R3
R3
5 6
1 2
C447 SC8P50V2CN-3GPC447 SC8P50V2CN-3GP
1 2
L27 IND-D56UH-16-GPL27 IND-D56UH-16-GP
12
C453
C453
C451 SC8P50V2CN-3GPC451 SC8P50V2CN-3GP
1 2
L29 IND-D56UH-16-GPL29 IND-D56UH-16-GP
12
C454
C454
SC82P50V2JN-3GP
SC82P50V2JN-3GP
C449 SC8P50V2CN-3GPC449 SC8P50V2CN-3GP
1 2
L28 IND-D56UH-16-GPL28 IND-D56UH-16-GP
12
C450
C450
SC82P50V2JN-3GP
SC82P50V2JN-3GP
U6B TSAHCT125PW-GPU6B TSAHCT125PW-GP
7
12
SC82P50V2JN-3GP
SC82P50V2JN-3GP
1 2
SC82P50V2JN-3GP
SC82P50V2JN-3GP
1 2
SC82P50V2JN-3GP
SC82P50V2JN-3GP
A
B
12
C24
C24
SC10P50V2JN-4GP
SC10P50V2JN-4GP
C446
C446
12
12
SC10P50V2JN-4GP
SC10P50V2JN-4GP
5V_S0
14
1
2 3
U6A TSAHCT125PW-GPU6A TSAHCT125PW-GP
7
C452
C452
C448
C448
B
1 2
L4 BLM18BB470SN1-GPL4 BLM18BB470SN1-GP
1 2
L5 BLM18BB470SN1-GPL5 BLM18BB470SN1-GP
1 2
L1 BLM18BB470SN1-GPL1 BLM18BB470SN1-GP
12
C12
C12
DDC_DATA_CON
DDC_CLK_CON
12
C43
C43
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
PR_INSERT 15
HSYNC_5
VSYNC_5
SRN33J-5-GP-U
SRN33J-5-GP-U
TV_CRMA 15
TV_COMP 15
TV_LUMA 15
RN3
RN3
1
2 3
TV_LUMA
TV_CRMA
TV_COMP
12
C22
C22
SC10P50V2JN-4GP
SC10P50V2JN-4GP
D10
D10
DY
DY
3
BAV99TPT-GP
BAV99TPT-GP
D11
D11
DY
DY
3
BAV99TPT-GP
BAV99TPT-GP
JVGA_HS
4
JVGA_VS
4
6
7
5
12
SC10P50V2JN-4GP
SC10P50V2JN-4GP
5V_CRT1_S0
2
1
2
1
TV1
TV1
NC#2
LUMA
CRMA
GND
COMP
GND
GND
NC#5
GND
MINDIN7-16-GP
MINDIN7-16-GP
C
CRT_R
CRT_G
CRT_B
C9
C9
SC10P50V2JN-4GP
SC10P50V2JN-4GP
VGA_HSYNC
VGA_VSYNC
2
1
3
8
9
C
12
C10
C10
5V_CRT1_S0
CRT_R
CRT_R 15
CRT_G 15
CRT_B 15
U2
U2
DY
DY
5 4
6
7
8
PACDN009MR-GP-U
PACDN009MR-GP-U
VGA_TV_COMP
VGA_TV_LUMA
VGA_TV_CRMA
12
C11
C11
SCD01U16V2KX-3GP
SCD01U16V2KX-3GP
CRT_R
CRT_G
CRT_B
CRT_G
3
2
CRT_B
1
VGA_DDCDATA39
DDC_CLK_CON15
D3
D3
DY
DY
3
BAV99TPT-GP
BAV99TPT-GP
D4
D4
DY
DY
3
BAV99TPT-GP
BAV99TPT-GP
D1
D1
DY
DY
3
BAV99TPT-GP
BAV99TPT-GP
D
F1
F1
12
FUSE-1D1A6V-8GP
FUSE-1D1A6V-8GP
CRT1
CRT1
17
6
1
11
7
2
12
8
3
9
4
10
5
VIDEO-15-57-GP-U
VIDEO-15-57-GP-U
SC33P50V2JN-3GP
SC33P50V2JN-3GP
DDC_CLK_CON
3D3V_S0
2
12
C2
C2
SCD1U16V2ZY-2GP
1
2
1
2
1
SCD1U16V2ZY-2GP
3D3V_S0
12
3D3V_S0
12
C3
C3
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
DY
DY
C1
C1
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
DY
DY
D
JVGA_HS
13
JVGA_VS
14
15
16
12
C8
C8
DY
DY
3D3V_S0
U50
U50
5
6
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet of
Date: Sheet of
2N7002DW-7F-GP
2N7002DW-7F-GP
RN5
RN5
1
2 3
SRN0J-6-GP
SRN0J-6-GP
DY
DY
CRT/TV Connector
CRT/TV Connector
CRT/TV Connector
5V_CRT1_S0
DDC_DATA_CON
DDC_CLK_CON
12
C6
C6
SC33P50V2JN-3GP
SC33P50V2JN-3GP
SC22P50V2JN-4GP
SC22P50V2JN-4GP
DY
DY
DDC_DATA_CON
34
2
1
4
KAI SE
KAI SE
KAI SE
E
5V_S05V_CRT_S0
D2
D2
CH751H-40PT-1GP
CH751H-40PT-1GP
K A
1
23
SRN4K7J-8-GP
SRN4K7J-8-GP
RN1
RN1
4
12
12
C7
C7
C13
C13
SC22P50V2JN-4GP
SC22P50V2JN-4GP
3D3V_S0
4
RN41
RN41
SRN2K2J-1-GP
SRN2K2J-1-GP
1
2 3
DDC_DATA_CON 15
VGA_DDCCLK 39
5V @ ext. CRT side
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
of
13 44Wednesday, March 29, 2006
13 44Wednesday, March 29, 2006
13 44Wednesday, March 29, 2006
E
NMC
5V_S5
5V_S5
1 2
R518 255R2F-L-GPR518 255R2F-L-GP
1 2
R516 255R2F-L-GPR516 255R2F-L-GP
5V_S0
1 2
R107 560R2J-3-GPR107 560R2J-3-GP
5V_S0
1 2
R192 560R2J-3-GPR192 560R2J-3-GP
5V_S0
1 2
R520 255R2F-L-GPR520 255R2F-L-GP
5V_S0
R477 560R2J-3-GPR477 560R2J-3-GP
1 2
LED5
LED5
1 2
LED-B-27-U-GP
LED-B-27-U-GP
LED4
LED4
1 2
LED-B-27-U-GP
LED-B-27-U-GP
LED1
LED1
1 2
LED-B-27-U-GP
LED-B-27-U-GP
LED3
LED3
1 2
LED-B-27-U-GP
LED-B-27-U-GP
LED6
LED6
1 2
LED-B-27-U-GP
LED-B-27-U-GP
CHG_LED#
PWR_LED#
U44C
U44C
TSAHCT08PWR-1GP
TSAHCT08PWR-1GP
MEDIA_LED#
TSAHCT08PWR-1GP
TSAHCT08PWR-1GP
NC
LED7
LED7
KA
LED-B-67-GP-U2
LED-B-67-GP-U2
TSAHCT08PWR-1GP
TSAHCT08PWR-1GP
C
E
PDTC124EU-1-GP
PDTC124EU-1-GP
C
E
PDTC124EU-1-GP
PDTC124EU-1-GP
5V_S0
8
U62
U62
1
2
3 4
2N7002DW-7F-GP
2N7002DW-7F-GP
U44B
U44B
6
R2
R2
R2
R2
147
U44A
U44A
5V_S0
Q37
Q37
R1
R1
Q36
Q36
R1
R1
LED / INVERTER INTERFACE
B
B
9
10
6
5
5V_S0
3
147
4
5
147
CHG_LED 29
PWR_LED 29,31
LED2
LED2
LED-O-16-GP
LED-O-16-GP
TP_LED 29
1
2
CAPS_LED 29
AK
1016
MS_LED# 23
3D3V_S0
12
R191255R2F-L-GP R191255R2F-L-GP
CDROM_LED# 21
1016
LDDC_DATA39
3D3V_S0
12
LCD/INV CONN
LCDVDD_S0
12
12
C89
C89
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
5V_S0
BRIGHTNESS_CONN
C84
C84
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
3D3V_S0
12
C85
C85
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
R312
R312
100KR2J-1-GP
100KR2J-1-GP
DY
DY
1 2
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
LDDC_CLK39
BLON_OUT29
R272
R272
10KR2J-3-GP
10KR2J-3-GP
C466
C466
SATA_LED# 16
BRIGHTNESS_CONN
DCBATOUT
12
12
C82
C82
SCD01U25V2KX-3GP
SCD01U25V2KX-3GP
1 2
R314 0R0402-PADR314 0R0402-PAD
1 2
R313 0R2J-2-GP
R313 0R2J-2-GP
DY
DY
LCD1
LCD1
42
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
ACES-CONN40C-GP
ACES-CONN40C-GP
BRIGHTNESS 29
LBKLT_CRTL 39
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
VGA_TXACLK- 39
VGA_TXACLK+ 39
VGA_TXAOUT0- 39
VGA_TXAOUT0+ 39
VGA_TXAOUT1- 39
VGA_TXAOUT1+ 39
VGA_TXAOUT2- 39
VGA_TXAOUT2+ 39
VGA_TXBCLK- 39
VGA_TXBCLK+ 39
VGA_TXBOUT0- 39
VGA_TXBOUT0+ 39
VGA_TXBOUT1- 39
VGA_TXBOUT1+ 39
VGA_TXBOUT2- 39
VGA_TXBOUT2+ 39
LDDC_CLK
LDDC_DATA
1 2
C83 SC1000P50V3JN-GPC83 SC1000P50V3JN-GP
1 2
C465 SCD1U16V2ZY-2GPC465 SCD1U16V2ZY-2GP
3D3V_S0
4
1
2 3
RN4
RN4
SRN2K2J-1-GP
SRN2K2J-1-GP
BLON_OUT
BRIGHTNESS_CONN
Layout 40 mil
LCDVDD_S0
LCDVDD_ON39
R317
R317
100KR2J-1-GP
100KR2J-1-GP
1 2
U52
U52
1
OUT
2
GND
ON/OFF#3IN
AAT4280IGU-1-T1GP
AAT4280IGU-1-T1GP
GND
IN
3D3V_S0
6
5
4
12
BC8
BC8
SC1U10V3ZY-6GP
SC1U10V3ZY-6GP
12
EC89
EC89
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
LCDVDD_S0
LCDVDD_ON
1 2
R316 100R2J-2-GPR316 100R2J-2-GP
Discharge circuit
U51
U51
1
2
3 4
2N7002DW-7F-GP
2N7002DW-7F-GP
5V_S5
12
R315
R315
10KR2J-3-GP
10KR2J-3-GP
6
5
<Core Design>
<Core Design>
<Core Design>
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
LCD/Inverter Connector
LCD/Inverter Connector
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
LCD/Inverter Connector
KAI SE
KAI SE
KAI SE
14 44Thursday, April 13, 2006
14 44Thursday, April 13, 2006
14 44Thursday, April 13, 2006
of
of
of
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