HP DV1000 Schematics
A
hexainf@hotmail.com
Leopard 3 Block Diagram
CLK GEN
3
ICS954206AG
4 4
26
1394
Conn
22,23
PCMCIA
1 SLOT
SD/MS
6 in 1
24 22
24
Power
Switch
TPS2220A
PCI7411
CARDBUS
1394
SD/MS/MMC/SM
Card Slost
3 3
Mini-PCI
29
802.11a/b/g
RJ45
CONN
RJ11
CONN
26
10/100 RTL8100C
25
MODEM
MDC Card
25,26
PCI BUS
30
AC97-LINK
B
4,5
Mobile CPU
C
Project code: 91.4C901.001
PCB P/N : 48.4C901.001
REVISION : 05205-1
D
E
SYSTEM DC/DC
36
MAX1999
INPUTS
DCBATOUT
OUTPUTS
5V_S3
3V_S5
Dothan
11,12
LVDS
SVIDEO/COMP
RGB CRT
BLUE THUMB
MASTER
SLAVE
14
LCD
13
TVOUT
CRT
DAUGHTER BOARD
USB x 2
USB x 2
HDD
DVD/
CD-RW
30
21
21
SYSTEM DC/DC
37
INPUTS
DCBATOUT
TPS5130
OUTPUTS
1D05V_S0
1D2V_S0
1D8V_S3
MAXIM CHARGER
34
INPUTS
DCBATOUT
MAX1909
OUTPUTS
BT+
18V 4.0A
5V 100mA
CPU DC/DC
35
MAX1907
INPUTS
DCBATOUT
OUTPUTS
VCC_CORE
0.844~1.3V
27A
6,7,8,9,10
Alviso
GM
16,17,18,19
ICH6-M
DDR2*2
533MHz
Host BUS
400/533MHz
DMI I/F
100MHz
USB 2.0
P IDE
13
2 2
MIC IN
AC'97 CODEC
27
AD1981B
PCI EXPRESS/ USB2.0
LPC Bus
EXPRESSCARD
LINE OUT
13
KBC
NS97551
29 3231
Comsumer
IR
31\
Touch
Pad
C
OP AMP
28
Docking
G1420BF3U
2CH
SPEAKER
1 1
A
B
31
Int.
KB
X-BUS
Thermal
& Fan
G768D
19
FlashRom
4Mb
(512kB)
LPC
Debug
Conn
D
33
21
PCB LAYER
Signal 1
L1:
GND
L2:
Signal 2
21
Power
Switch
TPS2231
Title
Title
Title
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Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
Block Diagram
Block Diagram
Block Diagram
L3:
Signal 3
L4:
VCC
L5:
Signal 4
L6:
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Leopard 3
Leopard 3
Leopard 3
141Tuesday, July 19, 2005
141Tuesday, July 19, 2005
141Tuesday, July 19, 2005
E
-1
-1
of
of
of
-1
A
B
C
D
E
ICH6-M Integrated Pull-up
and Pull-down Resistors
ACZ_BIT_CLK,
EE_DOUT, EE_CS, GNT[5]#/GPO[17],
GNT[6]#/GPO[16],
4 4
LAD[3:0]#/FB[3:0]#, LDRQ[0],
PME#, PWRBTN#,
LAN_RXD[2:0]
ACZ_RST#, ACZ_SDIN[2:0], ACZ_SYNC,
ACZ_SDOUT,ACZ_BITCLK,
SPKR
USB[7:0][P,N]
DD[7],
LAN_CLK
3 3
ICH6-M IDE Integrated Series
DPRSLP#, EE_DIN,
TP[3]
SDDREQ
LDRQ[1]/GPI[41],
DPRSLPVR,
ICH6 internal 20K pull-ups
ICH6 internal 10K pull-ups
ICH6 internal 20K pull-downs
ICH6 internal 15K pull-downs
ICH6 internal 11.5K pull-downs
ICH6 internal 100K pull-downs
ICH6-M EDS 14308 0.8V1
Termination Resistors
DD[15:0],
DDACK#,
DCS3#,
IORDY,
IDEIRQ
DIOR#, DREQ,DIOW#,
DA[2:0],
DCS1#,
approximately 33 ohm
Power name description
5V_S0= 5 Voltage power up on system work(S0 state)
5V_S3= 5 Voltage suspend to RAM(S3 state)
5V_S5= 5 Voltage soft off(S5 state)
3D3V_S0= 3.3 Voltage power up on system work(S0 state)
3D3V_S3= 3.3 Voltage suspend to RAM(S3 state)
3D3V_S5= 3.3 Voltage soft off(S5 state)
LVDDR_1D8V= 1.8 Voltage power up on system work(S0 state)
1D8V_S3= 1.8Voltage suspend to RAM(S3 state)
2D5V_S0= 2.5 Voltage power up on system work(S0 state)
VCC_CORE_S0= CPU VID Voltage power up on system work(S0 state)
1D5V_VCCA_S0= 1.5 Voltage power up on system work(S0 state)
1D5V_S0= 1.5 Voltage power up on system work(S0 state)
1D5V_S5= 1.5 Voltage soft off(S5 state)
DDR_VREF_S3= 0.9 Voltage suspend to RAM(S3 state)
0D9V_S0= 1.25 Voltage power up on system work(S0 state)
1D2_VGA_S0= 1.2 Voltage power up on system work(S0 state) for VGA
1D05V_S0= 1.05 Voltage power up on system work(S0 state)
CORE_GMCH_S0= 1.05 Voltage power up on system work(S0 state) for ALVISO core power
VCCP_GMCH_S0= 1.05 Voltage power up on system work(S0 state)for ALVISO BUSIO power
PCI RESOURCE TABLE
2 2
1 1
A
B
C
DEVICE IDSEL
Mini-PCI
Cardbus Controller
TI7411
LAN
Blue Thumb
D
AD21
AD22
AD23
AD24
Title
Title
Title
Size Document Number Rev
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A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
PCI IRQ
P_INTE#
(CARBUS)P_INTG#
(1394)P_INTF#
(CARD READER)P_INTG#
P_INTE#
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
ITP
ITP
ITP
Leopard 3
Leopard 3
Leopard 3
REQ# / GNT#
REQ0#/GNT0#
REQ1#/GNT1#
REQ2#/GNT2#
241Tuesday, July 12, 2005
241Tuesday, July 12, 2005
241Tuesday, July 12, 2005
E
-1
-1
of
of
of
-1
A
hexainf@hotmail.com
1 2
L17
L17
4 4
3D3V_S0
L34
L34
1 2
MLB-201209-11
MLB-201209-11
12
3D3V_APWR_S0 3D3V_48MPWR_S0
MLB-201209-11
MLB-201209-11
12
C362
C362
SC10U10V6ZY-U
SC10U10V6ZY-U
C156
C156
SC4D7U10V5ZY
SC4D7U10V5ZY
12
12
3D3V_CLKGEN_S0
C374
C374
SCD1U16V
SCD1U16V
C373
C373
SCD1U16V
SCD1U16V
DY
DY
12
C371
C371
SCD1U16V
SCD1U16V
B
3D3V_S03D3V_S0
12
1 2
C378
C378
SCD1U16V
SCD1U16V
R114
R114
4D7R3
4D7R3
12
12
C379
C379
SCD1U16V
SCD1U16V
C154
C154
SC4D7U10V5ZY
SC4D7U10V5ZY
12
DY
DY
12
C155
C155
SCD1U16V
SCD1U16V
DY
DY
C372
C372
SCD1U16V
SCD1U16V
12
DY
DY
C
C361
C361
SCD1U16V
SCD1U16V
12
DY
DY
C382
C382
SCD1U16V
SCD1U16V
3D3V_S0
12
12
R118
R118
10KR2
10KR2
ITP_EN
R125
R125
10KR2
10KR2
DY
DY
D
DummyR118(up side),Mounting R125(down side)
--SRC7 on
Mounting R118(up side),DummyR125(down side)
--CPU2_ITP on
E
3D3V_S0
3D3V_S05,7,9,11,13,14,16,17,18,19,20,21,22,23,24,25,27,29,30,31,32,36,38,40,41
CLK_PWRGD#20,36
C380
C380
1 2
SC22P
SC22P
X6
X6
X-14D31818M-17
X-14D31818M-17
1 2
RN58
RN58
1
CLK_PCIE_NEW#21
3 3
CLK_PCIE_NEW21
CLK_MCH_3GPLL#7
CLK_MCH_3GPLL7
CLK_PCIE_ICH#17
CLK_PCIE_ICH17
TP57TPAD30 TP57TPAD30
TP56TPAD30 TP56TPAD30
PREQ2#21
CPU_SEL04,7
SMBC_ICH11,19
SMBD_ICH11,19
2 2
TP_SRCC6 CLK_SRCT6
TP_SRCT6 CLK_SRCC6
CLK_ICH1417
CLK_CODEC27
3D3V_S0
4
23
SRN33-2-U2
SRN33-2-U2
RN40
RN40
1
4
23
SRN33-2-U2
SRN33-2-U2
RN41
RN41
1
4
23
SRN33-2-U2
SRN33-2-U2
R523 0R2-0
R523 0R2-0
R524 0R2-0
R524 0R2-0
R468 22R2R468 22R2
R467 22R2R467 22R2
R522 2K2R2R522 2K2R2
DY
DY
DY
DY
1 2
1 2
12
12
12
1 2
C381
C381
SC22P
SC22P
CLK_SRCC1
CLK_SRCT1
CLK_SRCC3
CLK_SRCT3
CLK_SRCC5
CLK_SRCT5
CLK_REF14
PCLK_KBC31
PM_STPPCI#17
CLK_ICHPCI17
NEAR CLKGEN
CLK_XOUT
CLK_XIN
20
SRCCLKC1
23
SRCCLKC2
25
SRCCLKC3
27
SRCCLKC4_SATA
30
SRCCLKC5
32
SRCCLKC6
19
SRCCLKT1
22
SRCCLKT2
24
SRCCLKT3
26
SRCCLKT4_SATA
31
SRCCLKT5
33
SRCCLKT6
52
REF0
53
REF1/FSLC/TEST_SEL
46
SCLK
47
SDATA
51
R458
R458
1 2
R126
R126
1 2
10X150X249
22R2
22R2
33R2
33R2
VTT_PWRGD#/PD
34
GND2GND6GND13GND29GND45GND
GNDA
38
SS_SEL
VDDSRC21VDDSRC28VDDSRC
SEL100_96MHZ#/PCICLK_F1
9
ITP_EN
7
CPUCLKC2_ITP/SRCCLKC7
CPUCLKT2_ITP/SRCCLKT7
55
SD 0817
12
R525
R525
10KR2
10KR2
1 1
12
REQSEL
R526
R526
DUMMY-R2
DUMMY-R2
DY
DY
A
3D3V_CLKGEN_S0
1 2
FS_B
FS_C
0
0
0
0
1
1
0
1
0
1 100M
0
1
1
1
1
R113
R113
FS_A
10KR2
10KR2
CPU
FS_A
266M
0
133M
01200M
166M
1
00333M
1
400M
0
1 Reserved
B
3D3V_APWR_S0
3D3V_48MPWR_S0
3D3V_CLKGEN_S0
11
37
42
48
VDDA
VDD48
VDDPCI1VDDPCI
VDDREF
VDDCPU
CPU_STOP#
CPUCLKC0
CPUCLKC1
CPUCLKT0
CPUCLKT1
FSLA/USB_48MHZ
FSLB/TEST_MODE
96MHZ_SSC/SRCCLKC0
96MHZ_SST/SRCCLKT0
DOTC_96MHZ
DOTT_96MHZ
IREF
ITP_EN/PCICLK_F08PCI/SRC_STOP#
PCICLK256PCICLK33PCICLK44PCICLK5
5
39
CLK_IREF
REQSEL
CLK_PCI3
CLK_PCI4
CLK_PCI5
CLK_CPU_BCLK
CLK_CPU_BCLK#
close to CPU
U57
U57
54
43
40
35
44
41
36
12
16
18
17
15
14
ICS954206AG
ICS954206AG
R115
R115
12
475R2F
475R2F
R466 33R2R466 33R2
12
R123 33R2R123 33R2
12
R124 33R2R124 33R2
12
TP87 TPAD30TP87 TPAD30
TP88 TPAD30TP88 TPAD30
CLK_CPUC1
CLK_CPUT1
CLK_CPUC2
CLK_CPUT2
CLK_CPUT0
CLK_CPUC0
FS_A
CLK_SRCC0
CLK_SRCT0
DOT96C
DOT96T
C
RN61
RN61
1
2 3
SRN33-2-U2
SRN33-2-U2
RN60
RN60
2 3
DY
DY
1
SRN33-2-U2
SRN33-2-U2
RN59
RN59
1
2 3
SRN33-2-U2
SRN33-2-U2
RN56
RN56
1
2 3
SRN33-2-U2
SRN33-2-U2
PCLK_PCM 22
PCLK_LAN 25
PCLK_MINI 29
4
4
4
4
R117 33R2R117 33R2
12
R116 33R2R116 33R2
12
R459 10R2R459 10R2
1 2
1 2
R460 33R2R460 33R2
SB
CLK_MCH_BCLK 6
CLK_MCH_BCLK# 6
PM_STPCPU# 17,36
CLK_XDP_CPU# 4
CLK_XDP_CPU 4
CLK_CPU_BCLK 4
CLK_CPU_BCLK# 4
CLK48_USB 17
CLK48_CARDBUS 22
CPU_SEL1 4,7
DREFSSCLK# 7
DREFSSCLK 7
DREFCLK# 7
DREFCLK 7
ICS954206AG Spread
Spectrum Select
SS3 SS2 SS1 SS0 Spread Amount%
000
0000
0
0
0
0
1
0
1
1
0
11
0
1 +-0.3
0
00
1
001
1
1
0
1
1
1
1
11
1
11
0
1
0
1
1
1
0
0
1
0
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
-0.8
-1.0
-1.25
-1.5
-1.75
-2.0
-2.5
-3.0
+-0.4
+-0.5
+-0.6
+-0.8
+-1.0
+-1.25
+-1.5
D
DREFCLK
DREFCLK#
CLK_PCIE_NEW
CLK_PCIE_NEW#
CLK_XDP_CPU
CLK_XDP_CPU#
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_MCH_BCLK
CLK_MCH_BCLK#
DREFSSCLK
DREFSSCLK#
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
CLK_PCIE_ICH
CLK_PCIE_ICH#
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
Clock Generator (ICS954206AG )
Clock Generator (ICS954206AG )
Clock Generator (ICS954206AG )
3D3V_S0
12
R453
R453
10KR2
10KR2
H/L: 100/96MHz
SS_SEL
12
R455
R455
10KR2
10KR2
DY
DY
R520
DY
DY
DY
DY
E
R520
49D9R2F
49D9R2F
R521
R521
49D9R2F
49D9R2F
R451
R451
49D9R2F
49D9R2F
R452
R452
49D9R2F
49D9R2F
R470
R470
49D9R2F
49D9R2F
R465
R465
49D9R2F
49D9R2F
R461
R461
49D9R2F
49D9R2F
R464
R464
49D9R2F
49D9R2F
R463
R463
49D9R2F
49D9R2F
R462
R462
49D9R2F
49D9R2F
R450
R450
49D9R2F
49D9R2F
R457
R457
49D9R2F
49D9R2F
R441
R441
49D9R2F
49D9R2F
R442
R442
49D9R2F
49D9R2F
R444
R444
49D9R2F
49D9R2F
R443
R443
49D9R2F
49D9R2F
341Monday, August 15, 2005
341Monday, August 15, 2005
341Monday, August 15, 2005
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Leopard 3
Leopard 3
Leopard 3
-1
-1
of
of
of
-1
A
H_A#[31..3]6
U45A
U45A
62.10055.011
62.10055.011
H_A#3
4 4
H_ADSTB#06
H_REQ#[4..0]6
3 3
H_ADSTB#16
H_A20M#16
H_FERR#16
H_IGNNE#16
H_STPCLK#16
H_INTR16
H_NMI16
H_SMI#16
CPU
2 2
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
P4
A3#
U4
A4#
V3
A5#
R3
A6#
V2
A7#
W1
A8#
T4
A9#
W2
A10#
Y4
A11#
Y1
A12#
U1
A13#
AA3
A14#
Y3
A15#
AA2
A16#
U3
ADSTB#0
R2
REQ0#
P3
REQ1#
T2
REQ2#
P1
REQ3#
T1
REQ4#
AF4
A17#
AC4
A18#
AC7
A19#
AC3
A20#
AD3
A21#
AE4
A22#
AD2
A23#
AB4
A24#
AC6
A25#
AD5
A26#
AE2
A27#
AD6
A28#
AF3
A29#
AE1
A30#
AF1
A31#
AE5
ADSTB#1
C2
A20M#
D3
FERR#
A3
IGNNE#
C6
STPCLK#
D1
LINT0
D4
LINT1
B4
SMI#
PZ47903
PZ47903
ITP Conn.
ADDR GROUP 0
ADDR GROUP 1
THERMTRIP#
HCLK THERM XTP/ITP SIGNALS CONTROL
TCK(PIN 5)
TCK(PIN A13)
FBO(PIN 11)
VCCP_GMCH_S0
H_CPURST#
XDP_TDO
CPU_PROCHOT#
1 1
XDP_TDI
XDP_TMS
XDP_TRST#
XDP_TCK
1 2
1 2
1 2
1 2
R283
R283
12
54D9R2F
54D9R2F
R275
R275
12
54D9R2F
54D9R2F
R274
R274
12
56R2J
56R2J
R277
R277
150R2
150R2
R279
R279
39D2R2F
39D2R2F
R278
R278
680R2
680R2
R280
R280
27D4R2F
27D4R2F
All place within 2" to CPU
A
ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#
BR0#
IERR#
INIT#
LOCK#
RESET#
RS0#
RS1#
RS2#
TRDY#
HIT#
HITM#
BPM#0
BPM#1
BPM#2
BPM#3
PRDY#
PREQ#
TCK
TDO
TMS
TRST#
DBR#
PROCHOT#
THERMDA
THERMDC
ITP_CLK1
ITP_CLK0
BCLK1
BCLK0
B
N2
L1
J3
L4
H2
M2
N4
A4
B5
J2
B11
H_RS#0
H1
H_RS#1
K1
H_RS#2
L2
M3
K3
K4
C8
B8
A9
C9
A10
XDP_BPM#5
B10
XDP_TCK
A13
XDP_TDI
C12
TDI
A12
C11
B13
A7
B17
B18
A18
C17
A15
A16
B14
B15
B
XDP_TDO
XDP_TMS
XDP_TRST#
DBR#
CPU_PROCHOT#
H_ADS# 6
H_BNR# 6
H_BPRI# 6
H_DEFER# 6
H_DRDY# 6
H_DBSY# 6
H_BREQ#0 6
H_INIT# 16
H_LOCK# 6
H_TRDY# 6
H_HIT# 6
H_HITM# 6
THERMDP1 20
THERMDN 20
PM_THRMTRIP-A# 7,16
PM_THRMTRIP-I# 7,16
CLK_XDP_CPU# 3
CLK_XDP_CPU 3
CLK_CPU_BCLK# 3
CLK_CPU_BCLK 3
VCCP_GMCH_S0
12
R289
R289
56R2J
56R2J
H_IERR#
H_CPURST# 6
H_RS#[2..0] 6
VCCP_GMCH_S0
12
R285
R285
56R2J
56R2J
VCC_CORE_S0
12
R16
R16
150R2
150R2
Dothan A: R43,R44=DUMMY
Dothan B: R43,R44=0R
Place testpoint on
H_IERR# with a GND
0.1" away
PM_THRMTRIP#
should connect to
ICH6 and Alviso
without T-ing
( No stub)
CPU_SEL03,7
CPU_SEL13,7
C
VCCP_GMCH_S0
1 2
C
R23
R23
1KR2F
1KR2F
H_DSTBN#06
H_DSTBP#06
H_DINV#06
H_DSTBN#16
H_DSTBP#16
H_DINV#16
0R0402-PAD
0R0402-PAD
R273
R273
1 2
R276
R276
1 2
0R0402-PAD
0R0402-PAD
12
R22
R22
2KR2F
2KR2F
CPU_SEL0_CPU
CPU_SEL1_CPU
TP1TPAD30 TP1TPAD30
TP5TPAD30 TP5TPAD30
TP6TPAD30 TP6TPAD30
TP38TPAD30 TP38TPAD30
Layout Note:
0.5" max length.
BSEL[1:0] Freq.(MHz)
L H 100
L L 133
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
CPU_TP3
CPU_TP4
CPU_TP5
CPU_TP6
GTLREF
PSI#
C20
D24
C26
C25
C23
C22
D25
H23
G25
M26
H24
G24
M23
N24
M25
H26
N25
C16
C14
AF7
AC1
AD26
A19
A25
A22
B21
A24
B26
A21
B20
B24
E24
B23
E23
L23
F25
K25
K24
L24
E26
J23
J25
L26
J26
E1
C3
D
U45B
U45B
62.10055.011
62.10055.011
D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
DATA GRP 0DATA GRP 1
D13#
D14#
D15#
DSTBN0#
DSTBP0#
DINV0#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
DSTBN1#
DSTBP1#
DINV1#
PSI#
BSEL0
BSEL1
MISC
RSVD2
RSVD3
RSVD4
RSVD5
GTLREF0
PZ47903
PZ47903
D
Y26
D32#
AA24
D33#
T25
D34#
U23
D35#
V23
D36#
R24
D37#
R26
D38#
R23
D39#
AA23
D40#
U26
D41#
V24
D42#
U25
D43#
V26
D44#
DATA GRP 2
Y23
D45#
AA26
D46#
Y25
D47#
W25
DSTBN2#
W24
DSTBP2#
T24
DINV2#
AB25
D48#
AC23
D49#
AB24
D50#
AC20
D51#
AC22
D52#
AC25
D53#
AD23
D54#
AE22
D55#
AF23
D56#
AD24
D57#
AF20
D58#
AE21
D59#
AD21
D60#
DATA GRP 3
AF25
D61#
AF22
D62#
AF26
D63#
AE24
DSTBN3#
AE25
DSTBP3#
AD20
DINV3#
P25
COMP0
P26
COMP1
AB2
COMP2
AB1
COMP3
G1
DPRSTP#
B7
DPSLP#
C19
DPWR#
SLP#
TEST1
TEST2
E4
A6
C5
F23
NO STUFF
PWRGOOD
E
VCCP_GMCH_S05,6,7,9,10,16,18,36,40,41
3D3V_S03,5,7,9,11,13,14,16,17,18,19,20,21,22,23,24,25,27,29,30,31,32,36,38,40,41
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
COMP0
R302 27D4R2FR302 27D4R2FTP3TPAD30 TP3TPAD30
COMP1
R301 54D9R2FR301 54D9R2F
COMP2
R25 27D4R2FR25 27D4R2F
COMP3
R24 54D9R2FR24 54D9R2F
TEST1
TEST2
12
12
R18
R18
1KR2
1KR2
DY
DY
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
H_DSTBN#2 6
H_DSTBP#2 6
H_DINV#2 6
Layout Note:
Comp0, 2 connect with Zo=27.4 ohm, make
trace length shorter than 0.5" .
Comp1, 3 connect with Zo=55 ohm, make
trace length shorter than 0.5" .
H_DSTBN#3 6
H_DSTBP#3 6
H_DINV#3 6
1 2
1 2
1 2
1 2
H_DPRSLP# 16
H_DPSLP# 16
H_DPWR# 6
H_CPUSLP# 6,16
R284
R284
1KR2
1KR2
DY
DY
H_D#[63..0] 6
VCCP_GMCH_S0
12
R288
R288
200R2J
200R2J
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
CPU (1 of 2)
CPU (1 of 2)
CPU (1 of 2)
Leopard 3
Leopard 3
Leopard 3
441Monday, August 15, 2005
441Monday, August 15, 2005
441Monday, August 15, 2005
E
H_PWRGD 16
of
of
of
VCCP_GMCH_S0
3D3V_S0
-1
-1
-1
A
hexainf@hotmail.com
VCC_CORE_S0 VCC_CORE_S0
4 4
3 3
2 2
1 1
AA11
AA13
AA15
AA17
AA19
AA21
AA5
AA7
AA9
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AB6
AB8
AC11
AC13
AC15
AC17
AC19
AC9
AD10
AD12
AD14
AD16
AD18
AD8
AE11
AE13
AE15
AE17
AE19
AE9
AF10
AF12
AF14
AF16
AF18
AF8
D18
D20
D22
D6
D8
E17
E19
E21
E5
E7
E9
F18
F20
F22
F6
F8
G21
Layout Note:
U45C
U45C
62.10055.011
62.10055.011
VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
PZ47903
PZ47903
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCCA0
VCCA1
VCCA2
VCCA3
VCCP0
VCCP1
VCCP2
VCCP3
VCCP4
VCCP5
VCCP6
VCCP7
VCCP8
VCCP9
VCCP10
VCCP11
VCCP12
VCCP13
VCCP14
VCCP15
VCCP16
VCCP17
VCCP18
VCCP19
VCCP20
VCCP21
VCCP22
VCCP23
VCCP24
VCCQ0
VCCQ1
VID0
VID1
VID2
VID3
VID4
VID5
VCCSENSE
VSSSENSE
VCCSENSE and VSSSENSE lines
should be of equal length.
Layout Note:
Provide a test point (with
no stub) to connect a
differential probe
between VCCSENSE and
VSSSENSE at the location
where the two 54.9ohm
resistors terminate the
55 ohm transmission line.
A
G5
H22
H6
J21
J5
K22
U5
V22
V6
W21
W5
Y22
Y6
F26
B1
N1
AC26
D10
D12
D14
D16
E11
E13
E15
F10
F12
F14
F16
K6
L21
L5
M22
M6
N21
N5
P22
P6
R21
R5
T22
T6
U21
P23
W4
E2
F2
F3
G3
G4
H4
AE7
AF6
CPU_D10
1.8V is for Dothan
A2 before.
1D5V OR 1D8V
Intel suggest Dothan
A2 or later only use
1.5V
1D5V_VCCA_S0
SCD01U16V3KX
SCD01U16V3KX
TP_VCCA1
TP_VCCA2
TP_VCCA3
TP_VCCSENSE
1 2
TP_VSSSENSE
R34
R34
54D9R2F
54D9R2F
TP2 TPAD30TP2 TPAD30
TP4 TPAD30TP4 TPAD30
TP39 TPAD30TP39 TPAD30
H_VID0 36
H_VID1 36
H_VID2 36
H_VID3 36
H_VID4 36
H_VID5 36
DY
DY
R286
R286
0R2-0
0R2-0
12
C15
C15
12
VCCP_GMCH_S0
12
R33
R33
54D9R2F
54D9R2F
DY
DY
B
12
C10
C10
SC10U10V6ZY-U
SC10U10V6ZY-U
B
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AA25
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB26
AC2
AC5
AC8
AC10
AC12
AC14
AC16
AC18
AC21
AC24
AD1
AD4
AD7
AD9
AD11
AD13
AD15
AD17
AD19
AD22
AD25
AE10
AE12
AE14
AE16
AE18
AE20
AE23
AE26
AF11
AF13
AF15
AF17
AF19
AF21
AF24
A11
A14
A17
A20
A23
A26
AA1
AA4
AA6
AA8
AB3
AB5
AB7
AB9
AE3
AE6
AE8
AF2
AF5
AF9
B12
B16
B19
B22
B25
C10
C13
C15
C18
C21
C24
D11
U45D
U45D
A2
VSS0
A5
VSS1
A8
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
B3
VSS75
B6
VSS76
B9
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
C1
VSS83
C4
VSS84
C7
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
D2
VSS92
D5
VSS93
D7
VSS94
D9
VSS95
VSS96
PZ47903
PZ47903
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
D13
D15
D17
D19
D21
D23
D26
E3
E6
E8
E10
E12
E14
E16
E18
E20
E22
E25
F1
F4
F5
F7
F9
F11
F13
F15
F17
F19
F21
F24
G2
G6
G22
G23
G26
H3
H5
H21
H25
J1
J4
J6
J22
J24
K2
K5
K21
K23
K26
L3
L6
L22
L25
M1
M4
M5
M21
M24
N3
N6
N22
N23
N26
P2
P5
P21
P24
R1
R4
R6
R22
R25
T3
T5
T21
T23
T26
U2
U6
U22
U24
V1
V4
V5
V21
V25
W3
W6
W22
W23
W26
Y2
Y5
Y21
Y24
62.10055.011
62.10055.011
C
VCCP_GMCH_S0
12
C18
C18
SCD1U10V2MX-1
SCD1U10V2MX-1
C
3D3V_S0
12
BC53
BC53
SC1U10V3ZY
SC1U10V3ZY
DY
DY
0.1u *10 150u *1
12
12
C19
C19
SCD1U10V2MX-1
SCD1U10V2MX-1
VCC_CORE_S0
12
C16
C16
C27
C27
SC10U6D3V5MX
SC10U6D3V5MX
1
2
3
12
SCD1U10V2MX-1
SCD1U10V2MX-1
12
C17
C17
SC10U6D3V5MX
SC10U6D3V5MX
I max = 120 mA
U44
U44
SHDN#
GND
IN
G913C-U
G913C-U
DY
DY
12
C22
C22
C33
C33
SCD1U10V2MX-1
SCD1U10V2MX-1
SCD1U10V2MX-1
SCD1U10V2MX-1
12
12
C21
C21
C23
C23
SC10U6D3V5MX
SC10U6D3V5MX
SC10U6D3V5MX
SC10U6D3V5MX
12
C29
C29
SET
OUT
12
5
4
C11
C11
SCD1U10V2MX-1
SCD1U10V2MX-1
12
C31
C31
SC10U6D3V5MX
SC10U6D3V5MX
1D5V_VCCA_S0
12
SC10U6D3V5MX
SC10U6D3V5MX
C28
C28
12
C32
C32
SCD1U10V2MX-1
SCD1U10V2MX-1
12
DY
DY
12
12
C36
C36
SC10U6D3V5MX
SC10U6D3V5MX
D
12
BC54
BC54
SC22P
SC22P
DY
DY
BC2
BC2
SC1U10V3ZY
SC1U10V3ZY
12
C34
C34
C20
C20
SCD1U10V2MX-1
SCD1U10V2MX-1
12
C37
C37
DY
DY
SC10U6D3V5MX
SC10U6D3V5MX
SC10U6D3V5MX
SC10U6D3V5MX
D
1D5V_VCCA_SET
12
R296
R296
49K9R2F
49K9R2F
DY
DY
12
C26
C26
SCD1U10V2MX-1
SCD1U10V2MX-1
SCD1U10V2MX-1
SCD1U10V2MX-1
12
12
C39
C39
C38
C38
DY
DY
SC10U6D3V5MX
SC10U6D3V5MX
SC10U10V5ZY-L
SC10U10V5ZY-L
E
VCC_CORE_S04,36
VCCP_GMCH_S04,6,7,9,10,16,18,36,40,41
3D3V_S03,7,9,11,13,14,16,17,18,19,20,21,22,23,24,25,27,29,30,31,32,36,38,40,41
12
DY
DY
NO STUFF
12
TC1
TC1
ST100U6D3VM-U
ST100U6D3VM-U
12
C44
C44
12
12
C277
C277
C276
C276
DY
DY
DY
DY
SC10U10V5ZY-L
SC10U10V5ZY-L
SC10U10V5ZY-L
SC10U10V5ZY-L
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
1D5V_VCCA_S0 1D5V_S0
R295
R295
12K7R3F
12K7R3F
12
12
C280
C280
C279
C279
DY
DY
DY
DY
SC10U10V5ZY-L
SC10U10V5ZY-L
SC10U10V5ZY-L
SC10U10V5ZY-L
R17
R17
1 2
0R2-0
0R2-0
12
12
C282
C282
C281
C281
DY
DY
DY
DY
SC10U10V5ZY-L
SC10U10V5ZY-L
SC10U10V5ZY-L
SC10U10V5ZY-L
CPU (2 of 2)
CPU (2 of 2)
CPU (2 of 2)
Leopard 3
Leopard 3
Leopard 3
12
12
C284
C284
C283
C283
SC10U10V5ZY-L
SC10U10V5ZY-L
DY
DY
DY
DY
SC10U10V5ZY-L
SC10U10V5ZY-L
SC10U10V5ZY-L
SC10U10V5ZY-L
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
E
of
541Monday, August 15, 2005
of
541Monday, August 15, 2005
of
541Monday, August 15, 2005
VCC_CORE_S0
VCCP_GMCH_S0
3D3V_S0
-1
-1
-1
A
12/12 Trace 10 mil wide with 20 mil spacing
H_XRCOMP
12
R69
R69
24D9R2F
24D9R2F
4 4
VCCP_GMCH_S0
R70
R70
54D9R2F
54D9R2F
1 2
H_XSCOMP
VCCP_GMCH_S0
12
R67
R67
221R3F
221R3F
H_XSWING
12
R68
R68
100R2F
3 3
100R2F
1 2
C73
C73
SCD1U16V
SCD1U16V
VCCP_GMCH_S0
VCCP_GMCH_S0
12
1 2
12
12
H_YRCOMP
R87
R87
24D9R2F
24D9R2F
R89
R89
54D9R2F
54D9R2F
H_YSCOMP
R86
R86
221R3F
221R3F
H_YSWING
R88
R88
100R2F
100R2F
1 2
C91
C91
SCD1U16V
SCD1U16V
H_D#[63..0]4 H_A#[31..3] 4
12/12 Trace 10 mil wide with 20 mil spacing
Alviso Strapping Signals
and Configuration
Pin Name
CFG[2:0]
CFG[4:3] Reserved
CFG5 DMI x2 Select
2 2
CFG6 Reserved 0 = DDR2
CFG7
CFG8
CFG9
CFG[11:10]
CFG[13:12]
CFG[15:14] Reversed
CFG16
CFG17
CFG18
1 1
CFG19
CFG20
SDVOCRTL
_DATA
All strap signals are sampled with respect to the leading
NOTE:
edge of the Alviso GMCH PWORK In signal.
Strap Description Configuration
CPU Strap
Reserved
PCI Express Graphics
Lane Reversal
Reserved
XOR/ALL Z test
straps
FSB Dynamic ODT
Reversed
GMCH core VCC
Select
CPU VTT Select
Reversed
SDVO Present
A
REV.NO. 1.0
REF. NO. 15577
001 = FSB533FSB Frequency Select
101 = FSB400
others = Reversed
0 = DMI x2
1 = DMI x4
1 = DDR1
0 = Reserved
1 = Dothan
0 = Reserve Lanes
1 = Normal
00 = Reserved
01 = XOR mode enabled
10 = All Z mode enabled
11 = Normal Operation
0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled
0 = 1.05V
1 = 1.5V
0 = 1.05V
1 = 1.2V
(Default)
(Default)
(Default)
(Default)
(Default)
(Default)
0 = No SDVO device present
1= SDVO device present
page 183
(Default)
(Default)
(Default)
B
C
D
E
CORE_GMCH_S0
CORE_GMCH_S09,10,40,41
VCCP_GMCH_S0
VCCP_GMCH_S04,5,7,9,10,16,18,36,40,41
Power On Sequencing
U17A
U17A
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_XRCOMP
H_XSCOMP
H_XSWING
H_YRCOMP
H_YSCOMP
H_YSWING
E4
E1
F4
H7
E2
F1
E3
D3
K7
F2
J7
J8
H6
F3
K8
H5
H1
H2
K5
K6
J4
G3
H3
J1
L5
K4
J5
P7
L7
J3
P5
L3
U7
V6
R6
R5
P3
T8
R7
R8
U8
R4
T4
T5
R1
T3
V8
U6
W6
U3
V5
W8
W7
U2
U1
Y5
Y2
V4
Y7
W1
W3
Y3
Y6
W2
C1
C2
D1
T1
L1
P1
HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#
HXRCOMP
HXSCOMP
HXSWING
HYRCOMP
HYSCOMP
HYSWING
ALVISO-GM
ALVISO-GM
HADSTB#0
HADSTB#1
HCPURST#
HOST
HOST
HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3
HCPUSLP#
HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HADS#
HVREF
HBNR#
HBPRI#
HBREQ0#
HCLKINN
HCLKINP
HDBSY#
HDEFER#
HDINV#0
HDINV#1
HDINV#2
HDINV#3
HDPWR#
HDRDY#
HEDRDY#
HHIT#
HHITM#
HLOCK#
HPCREQ#
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
HRS0#
HRS1#
HRS2#
HTRDY#
G9
C9
E9
B7
A10
F9
D8
B10
E10
G10
D9
E11
F10
G11
G13
C10
C11
D11
C12
B13
A12
F12
G12
E12
C13
B11
D13
A13
F13
F8
B9
E13
J11
A5
D5
E7
H10
AB1
AB2
C6
E6
H8
K3
T7
U5
G6
F7
G4
K1
R3
V3
G5
K2
R2
W4
F6
D4
D6
B3
A11
A7
D7
B8
C7
A8
A4
C5
B4
G8
B5
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
TP_H_EDRDY#
TP_H_PCREQ#
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
H_CPUSLP#_GMCH
H_ADS# 4
H_ADSTB#0 4
H_ADSTB#1 4
H_BNR# 4
H_BPRI# 4
H_BREQ#0 4
H_CPURST# 4
CLK_MCH_BCLK# 3
CLK_MCH_BCLK 3
H_DBSY# 4
H_DEFER# 4
H_DPWR# 4
H_DRDY# 4
TP42 TPAD30TP42 TPAD30
H_HIT# 4
H_HITM# 4
H_LOCK# 4
TP9 TPAD30TP9 TPAD30
H_TRDY# 4
C308
C308
SCD1U10V2KX
SCD1U10V2KX
VCCP_GMCH_S0
12
R336
R336
100R2F
100R2F
H_VREF
12
12
R337
R337
200R2F
200R2F
H_DINV#[3..0] 4
H_DSTBN#[3..0] 4
H_DSTBP#[3..0] 4
H_REQ#[4..0] 4
H_RS#[2..0] 4
0R0402-PAD
0R0402-PAD
R311
R311
1 2
For Banias/Celeron-M:R93=DUMMY
For Dothan A:R93=DUMMY
For Dothan B:R93=0R
ALVISO-GM:71.0GMCH.08U
ALVISO-PM:71.0GMCH.0BU
ALVISO-GML:71.0GMCH.0JU
B
C
D
VID
VR_ON
Vcc_core
Vccp
Vcc_mch
MCH_PWERGD
CLK_ENABLE#
VGATE TO ICH6
H_CPUSLP# 4,16
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
>3mS
10~30uS
Vboot
<10uS
CORE_GMCH_S0
12
H_DPWR#
GMCH (1 of 5)
GMCH (1 of 5)
GMCH (1 of 5)
Leopard 3
Leopard 3
Leopard 3
Vboot Vvid
>100uS
3~10mS
R391
R391
0R2-0
0R2-0
DY
DY
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
641Monday, August 15, 2005
641Monday, August 15, 2005
641Monday, August 15, 2005
of
of
E
of
-1
-1
-1
A
hexainf@hotmail.com
U17B
U17B
AA31
DMIRXN0
AB35
DMIRXN1
AC31
DMIRXN2
AD35
DMIRXN3
Y31
DMIRXP0
AA35
DMIRXP1
AB31
DMIRXP2
AC35
DMIRXP3
AA33
DMITXN0
AB37
DMITXN1
AC33
DMITXN2
AD37
DMITXN3
Y33
DMITXP0
AA37
DMITXP1
AB33
DMITXP2
AC37
DMITXP3
AM33
SM_CK0
AL1
SM_CK1
AE11
SM_CK2
AJ34
SM_CK3
AF6
SM_CK4
AC10
SM_CK5
AN33
SM_CK0#
AK1
SM_CK1#
AE10
SM_CK2#
AJ33
SM_CK3#
AF5
SM_CK4#
AD10
SM_CK5#
AP21
SM_CKE0
AM21
SM_CKE1
AH21
SM_CKE2
AK21
SM_CKE3
AN16
SM_CS0#
AM14
SM_CS1#
AH15
SM_CS2#
AG16
SM_CS3#
AF22
SM_OCDCOMP0
AF16
SM_OCDCOMP1
AP14
SM_ODT0
AL15
SM_ODT1
AM11
SM_ODT2
AN10
SM_ODT3
AK10
SMRCOMPN
AK11
SMRCOMPP
AF37
SMVREF0
AD1
SMVREF1
AE27
SMXSLEWIN
AE28
SMXSLEWOUT
AF9
SMYSLEWIN
AF10
SMYSLEWOUT
ALVISO-GM
ALVISO-GM
Ref ALVISO EDS-1 Page 115
For Dothan-B
R50
R50
1KR2
1KR2
CFG2
CFG1
CFG0
R51
R51
4K7R2
4K7R2
CFG2=0(R51):133MHZ
CFG2=1(R50):100MHZ
CPU_SEL0 3,4
CPU_SEL1 3,4
CFG(2..1) FREQ.(MHz)
10 400
00 533
11 Reserved
R404
R404
40D2R2F
40D2R2F
SCD1U10V2MX-1
SCD1U10V2MX-1
R375 10KR2R375 10KR2
R378 10KR2R378 10KR2
FOR DDR2
R403
R403
80D6R2F
80D6R2F
M_RCOMPN
M_RCOMPP
R429
R429
80D6R2F
80D6R2F
DMI_TXN[3..0]17
DMI_TXP[3..0]17
DMI_RXN[3..0]17
DMI_RXP[3..0]17
12
PM_EXTTS#0
PM_EXTTS#1
CLK_DDR011
CLK_DDR111
CLK_DDR311
CLK_DDR411
CLK_DDR0#11
CLK_DDR1#11
CLK_DDR3#11
CLK_DDR4#11
M_CKE0_R#11,12
M_CKE1_R#11,12
M_CKE2_R#11,12
M_CKE3_R#11,12
M_CS0_R#11,12
M_CS1_R#11,12
M_CS2_R#11,12
M_CS3_R#11,12
M_OCDCOMP0
M_OCDCOMP1
M_ODT011,12
M_ODT111,12
M_ODT211,12
M_ODT311,12
DDR_VREF_S3
12
C109
C109
A
R344
R344
10KR2
10KR2
4 4
3 3
Layout Note:
Route as short
as possible
12
R405
R405
40D2R2F
40D2R2F
2 2
2D5V_S0
1 2
1 2
1D8V_S3
12
1 1
12
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
M_RCOMPN
M_RCOMPP
SMXSLEW
SMYSLEW
VCCP_GMCH_S0
12
12
10KR2
10KR2
12
R48
R48
4K7R2
4K7R2
DY
DY
R49
R49
12
12
DY
DY
B
CFG/RSVD
CFG/RSVD
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
BM_BUSY#
EXT_TS0#
EXT_TS1#
THRMTRIP#
PM
PM
PWROK
DREF_CLKN
DREF_CLKP
DREF_SSCLKN
CLK
CLK
DREF_SSCLKP
NC
NC
B
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
RSTIN#
DMI
DMI
DDR MUXING
DDR MUXING
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
G16
H13
G14
F16
F15
G15
E16
D17
J16
D15
E15
D14
E14
H12
C14
H15
J15
H14
G22
G23
D23
G25
G24
J17
A31
A30
D26
D25
J23
J21
H22
F5
AD30
AE29
A24
A23
C37
D37
AP37
AN37
AP36
AP2
AP1
AN1
B1
A2
B37
A36
A37
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
C
Alviso will provide SDVO_CTRLCLK
and CTRLDATA pulldowns on-die
CFG0
CFG1
R534
R534
1 2
CFG3 PEG_COMP
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
PM_EXTTS#0
PM_EXTTS#1
RST1#
1 2
GMCH_TP3
GMCH_TP4
GMCH_TP5
GMCH_TP6
GMCH_TP7
GMCH_TP8
GMCH_TP9
GMCH_TP10
GMCH_TP11
GMCH_TP12
GMCH_TP13
When Low 2.2K Ohm
R350
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
DY
R350
DUMMY-R2
DUMMY-R2
R348
R348
DUMMY-R2
DUMMY-R2
R343
R343
DUMMY-R2
DUMMY-R2
R571
R571
2K2R2
2K2R2
R352
R352
DUMMY-R2
DUMMY-R2
R340
R340
DUMMY-R2
DUMMY-R2
R347
R347
DUMMY-R2
DUMMY-R2
R349
R349
DUMMY-R2
DUMMY-R2
R52
R52
DUMMY-R2
DUMMY-R2
R345
R345
DUMMY-R2
DUMMY-R2
R338
R338
DUMMY-R2
DUMMY-R2
R346
R346
DUMMY-R2
DUMMY-R2
R342
R342
DUMMY-R2
DUMMY-R2
R339
R339
DUMMY-R2
DUMMY-R2
R341
R341
DUMMY-R2
DUMMY-R2
CFG2
1KR2
1KR2
GMCH_DDCCLK15
GMCH_DDCDATA15
TP48TP48
TP44TP44
TP43TP43
TP11TP11
TP10TP10
TP47TP47
TP45TP45
PM_BMBUSY# 17
PM_THRMTRIP-A# 4,16
PWROK 20
100R2
100R2
R406
R406
DREFCLK# 3
DREFCLK 3
DREFSSCLK# 3
DREFSSCLK 3
TP20 TPAD30TP20 TPAD30
TP18 TPAD30TP18 TPAD30
TP19 TPAD30TP19 TPAD30
TP15 TPAD30TP15 TPAD30
TP16 TPAD30TP16 TPAD30
TP17 TPAD30TP17 TPAD30
TP7 TPAD30TP7 TPAD30
TP8 TPAD30TP8 TPAD30
TP14 TPAD30TP14 TPAD30
TP13 TPAD30TP13 TPAD30
TP12 TPAD30TP12 TPAD30
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
COMP_VGA13
LUMA_VGA13
CRMA_VGA13
VGA_BLUE15
VGA_GREEN15
VGA_RED15
DY
DY
1 2
DY
DY
1 2
DY
DY
1 2
VGA_VSYNC13
VGA_HSYNC13
PLT_RST1# 19,21
LCTLA_CLK
1
LCTLB_DATA
2
LDDC_CLK
3
LDDC_DATA
4 5
BL_ON
LBKLT_CRTL
LIBG
EDID_DAT14
Strapping
CFG[17:3] have internal pullup resistors.
Intel suggest NC Due to votusly DVO
TP46TPAD30 TP46TPAD30
TP49TPAD30 TP49TPAD30
CLK_MCH_3GPLL#3
CLK_MCH_3GPLL3
R53
R53
150R2F
150R2F
RN39
RN39
SRN2K2
SRN2K2
1 2
1 2
1 2
EDID_CLK14
12
R59 150R2F
R59 150R2F
R57 150R2F
R57 150R2F
R56 150R2F
R56 150R2F
8
7
6
R382
R382
100KR2
100KR2
R381
R381
100KR2
100KR2
R379
R379
1K5R2F
1K5R2F
RN38
RN38
SRN4D7KJ
SRN4D7KJ
12
150R2F
150R2F
LCDVDD_ON14
2D5V_S0
R54
R54
Less than 0.5", trace impendance 37.5ohmTrace impendance 50ohm
1 2
1 2
1 2
BL_ON31
TP41TPAD30 TP41TPAD30
TP51TPAD30 TP51TPAD30
TP50TPAD30 TP50TPAD30
3D3V_S0
2
14
3
12
R55
R55
150R2F
150R2F
R60 39R2JR60 39R2J
R58 39R2JR58 39R2J
R374 255R2FR374 255R2F
NO STUFF
LDDC_CLK
1 2
TXACLK-14
TXACLK+14
TXBCLK-14
TXBCLK+14
TXAOUT0-14
TXAOUT1-14
TXAOUT2-14
TXAOUT0+14
TXAOUT1+14
TXAOUT2+14
TXBOUT0-14
TXBOUT1-14
TXBOUT2-14
TXBOUT0+14
TXBOUT1+14
TXBOUT2+14
SD 0817
R373
R373
5
6
SDVO_DAT
SDVO_CLK
4K99R2F
4K99R2F
LBKLT_CRTL
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LIBG
2D5V_S0
U14
U14
2N7002S
2N7002S
TV_REFSET
VSYNC
HSYNC
CRTIREF
L_LVBG
L_VREFH
L_VREFL
34
2
1
CFG[19:18] have internal pulldown resistors
C
H24
H25
AB29
AC29
A15
C16
A17
B15
B16
B17
E24
E23
E21
D21
C20
B20
A19
B19
H21
G21
E25
F25
C23
C22
F23
F22
F26
C33
C31
F28
F27
B30
B29
C25
C24
B34
B33
B32
A34
A33
B31
C29
D28
C27
C28
D27
C26
J18
J20
LDDC_DATA
D
U17G
U17G
SDVOCTRL_DATA
SDVOCTRL_CLK
GCLKN
GCLKP
TVDAC_A
TVDAC_B
TVDAC_C
TV_REFSET
TV_IRTNA
TV_IRTNB
TV_IRTNC
DDCCLK
DDCDATA
BLUE
BLUE#
GREEN
GREEN#
RED
RED#
VSYNC
HSYNC
REFSET
LBKLT_CRTL
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
LIBG
LVBG
LVREFH
LVREFL
LACLKN
LACLKP
LBCLKN
LBCLKP
LADATAN0
LADATAN1
LADATAN2
LADATAP0
LADATAP1
LADATAP2
LBDATAN0
LBDATAN1
LBDATAN2
LBDATAP0
LBDATAP1
LBDATAP2
ALVISO-GM
ALVISO-GM
D
E
2D5V_S09,15,18,40
1D8V_S39,10,11,12,38,39,40,41
1D5V_S05,9,17,18,21,38,39,41
CORE_GMCH_S06,9,10,40,41
DDR_VREF_S311,40
EXP_COMPI
EXP_ICOMPO
MISCTVVGALVDS
MISCTVVGALVDS
EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8
EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15
EXP_RXP0
EXP_RXP1
EXP_RXP2
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15
EXP_TXN0
EXP_TXN1
EXP_TXN2
EXP_TXN3
EXP_TXN4
EXP_TXN5
PCI-EXPRESS GRAPHICS
PCI-EXPRESS GRAPHICS
EXP_TXN6
EXP_TXN7
EXP_TXN8
EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15
EXP_TXP0
EXP_TXP1
EXP_TXP2
EXP_TXP3
EXP_TXP4
EXP_TXP5
EXP_TXP6
EXP_TXP7
EXP_TXP8
EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
D36
D34
E30
F34
G30
H34
J30
K34
L30
M34
N30
P34
R30
T34
U30
V34
W30
Y34
D30
E34
F30
G34
H30
J34
K30
L34
M30
N34
P30
R34
T30
U34
V30
W34
E32
F36
G32
H36
J32
K36
L32
M36
N32
P36
R32
T36
U32
V36
W32
Y36
D32
E36
F32
G36
H32
J36
K32
L36
M32
N36
P32
R36
T32
U36
V32
W36
GMCH (2 of 5)
GMCH (2 of 5)
GMCH (2 of 5)
Leopard 3
Leopard 3
Leopard 3
2D5V_S0
When High 1K Ohm
1 2
DY
DY
1 2
DY
DY
1 2
DY
DY
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
E
R380
R380
DUMMY-R2
DUMMY-R2
R376
R376
DUMMY-R2
DUMMY-R2
R377
R377
DUMMY-R2
DUMMY-R2
741Monday, August 15, 2005
741Monday, August 15, 2005
741Monday, August 15, 2005
2D5V_S0
1D8V_S3
1D5V_S0
CORE_GMCH_S0
DDR_VREF_S3
1D5V_S0
R71
R71
12
24D9R2F
24D9R2F
of
of
of
CFG18
CFG19
CFG20
-1
-1
-1
A
4 4
U17C
M_A_DATA[63..0]11
3 3
2 2
M_A_DATA0
M_A_DATA1
M_A_DATA2
M_A_DATA3
M_A_DATA4
M_A_DATA5
M_A_DATA6
M_A_DATA7
M_A_DATA8
M_A_DATA9
M_A_DATA10
M_A_DATA11
M_A_DATA12
M_A_DATA13
M_A_DATA14
M_A_DATA15
M_A_DATA16
M_A_DATA17
M_A_DATA18
M_A_DATA19
M_A_DATA20
M_A_DATA21
M_A_DATA22
M_A_DATA23
M_A_DATA24
M_A_DATA25
M_A_DATA26
M_A_DATA27
M_A_DATA28
M_A_DATA29
M_A_DATA30
M_A_DATA31
M_A_DATA32
M_A_DATA33
M_A_DATA34
M_A_DATA35
M_A_DATA36
M_A_DATA37
M_A_DATA38
M_A_DATA39
M_A_DATA40
M_A_DATA41
M_A_DATA42
M_A_DATA43
M_A_DATA44
M_A_DATA45
M_A_DATA46
M_A_DATA47
M_A_DATA48
M_A_DATA49
M_A_DATA50
M_A_DATA51
M_A_DATA52
M_A_DATA53
M_A_DATA54
M_A_DATA55
M_A_DATA56
M_A_DATA57
M_A_DATA58
M_A_DATA59
M_A_DATA60
M_A_DATA61
M_A_DATA62
M_A_DATA63
AG35
AH35
AL35
AL37
AH36
AJ35
AK37
AL34
AM36
AN35
AP32
AM31
AM34
AM35
AL32
AM32
AN31
AP31
AN28
AP28
AL30
AM30
AM28
AL28
AP27
AM27
AM23
AM22
AL23
AM24
AN22
AP22
AM9
AL9
AL6
AP7
AP11
AP10
AL7
AM7
AN5
AN6
AN3
AP3
AP6
AM6
AL4
AM3
AK2
AK3
AG2
AG1
AL3
AM2
AH3
AG3
AF3
AE3
AD6
AC4
AF2
AF1
AD4
AD5
U17C
SADQ0
SADQ1
SADQ2
SADQ3
SADQ4
SADQ5
SADQ6
SADQ7
SADQ8
SADQ9
SADQ10
SADQ11
SADQ12
SADQ13
SADQ14
SADQ15
SADQ16
SADQ17
SADQ18
SADQ19
SADQ20
SADQ21
SADQ22
SADQ23
SADQ24
SADQ25
SADQ26
SADQ27
SADQ28
SADQ29
SADQ30
SADQ31
SADQ32
SADQ33
SADQ34
SADQ35
SADQ36
SADQ37
SADQ38
SADQ39
SADQ40
SADQ41
SADQ42
SADQ43
SADQ44
SADQ45
SADQ46
SADQ47
SADQ48
SADQ49
SADQ50
SADQ51
SADQ52
SADQ53
SADQ54
SADQ55
SADQ56
SADQ57
SADQ58
SADQ59
SADQ60
SADQ61
SADQ62
SADQ63
ALVISO-GM
ALVISO-GM
SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
SA_RCVENIN#
SA_RCVENOUT#
SA_BS0#
SA_BS1#
SA_BS2#
SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7
SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_CAS#
SA_RAS#
SA_WE#
B
AK15
AK16
AL21
AJ37
AP35
AL29
AP24
AP9
AP4
AJ2
AD3
AK36
AP33
AN29
AP23
AM8
AM4
AJ1
AE5
AK35
AP34
AN30
AN23
AN8
AM5
AH1
AE4
AL17
AP17
AP18
AM17
AN18
AM18
AL19
AP20
AM19
AL20
AM16
AN20
AM20
AM15
AN15
AP16
AF29
AF28
AP15
M_A_SDM0
M_A_SDM1
M_A_SDM2
M_A_SDM3
M_A_SDM4
M_A_SDM5
M_A_SDM6
M_A_SDM7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
GMCH_TP48
GMCH_TP49
TP55TP55
M_A_BS0# 11,12
M_A_BS1# 11,12
M_A_BS2# 11,12
M_A_SDM[7..0] 11
M_A_DQS[7..0] 11
M_A_DQS#[7..0] 11
M_A_A[13..0] 11,12
M_A_CAS# 11,12
M_A_RAS# 11,12
M_A_WE# 11,12
M_B_DATA[63..0]11
C
U17D
U17D
M_B_DATA0
M_B_DATA1
M_B_DATA2
M_B_DATA3
M_B_DATA4
M_B_DATA5
M_B_DATA6
M_B_DATA7
M_B_DATA8
M_B_DATA9
M_B_DATA10
M_B_DATA11
M_B_DATA12
M_B_DATA13
M_B_DATA14
M_B_DATA15
M_B_DATA16
M_B_DATA17
M_B_DATA18
M_B_DATA19
M_B_DATA20
M_B_DATA21
M_B_DATA22
M_B_DATA23
M_B_DATA24
M_B_DATA25
M_B_DATA26
M_B_DATA27
M_B_DATA28
M_B_DATA29
M_B_DATA30
M_B_DATA31
M_B_DATA32
M_B_DATA33
M_B_DATA34
M_B_DATA35
M_B_DATA36
M_B_DATA37
M_B_DATA38
M_B_DATA39
M_B_DATA40
M_B_DATA41
M_B_DATA42
M_B_DATA43
M_B_DATA44
M_B_DATA45
M_B_DATA46
M_B_DATA47
M_B_DATA48
M_B_DATA49
M_B_DATA50
M_B_DATA51
M_B_DATA52
M_B_DATA53
M_B_DATA54
M_B_DATA55
M_B_DATA56
M_B_DATA57
M_B_DATA58
M_B_DATA59
M_B_DATA60
M_B_DATA61
M_B_DATA62
M_B_DATA63
AE31
AE32
AG32
AG36
AE34
AE33
AF31
AF30
AH33
AH32
AK31
AG30
AG34
AG33
AH31
AJ31
AK30
AJ30
AH29
AH28
AK29
AH30
AH27
AG28
AF24
AG23
AJ22
AK22
AH24
AH23
AG22
AJ21
AG10
AG9
AG8
AH8
AH11
AH10
AK9
AK6
AH5
AK8
AK4
AG5
AG4
AD8
AD9
AH4
AG6
AE8
AD7
AC5
AB8
AB6
AA8
AC8
AC7
AA4
AA5
AJ9
AJ7
AJ4
AJ8
AJ5
SBDQ0
SBDQ1
SBDQ2
SBDQ3
SBDQ4
SBDQ5
SBDQ6
SBDQ7
SBDQ8
SBDQ9
SBDQ10
SBDQ11
SBDQ12
SBDQ13
SBDQ14
SBDQ15
SBDQ16
SBDQ17
SBDQ18
SBDQ19
SBDQ20
SBDQ21
SBDQ22
SBDQ23
SBDQ24
SBDQ25
SBDQ26
SBDQ27
SBDQ28
SBDQ29
SBDQ30
SBDQ31
SBDQ32
SBDQ33
SBDQ34
SBDQ35
SBDQ36
SBDQ37
SBDQ38
SBDQ39
SBDQ40
SBDQ41
SBDQ42
SBDQ43
SBDQ44
SBDQ45
SBDQ46
SBDQ47
SBDQ48
SBDQ49
SBDQ50
SBDQ51
SBDQ52
SBDQ53
SBDQ54
SBDQ55
SBDQ56
SBDQ57
SBDQ58
SBDQ59
SBDQ60
SBDQ61
SBDQ62
SBDQ63
ALVISO-GM
ALVISO-GM
D
AJ15
SB_BS0#
AG17
SB_BS1#
AG21
SB_BS2#
AF32
SB_DM0
AK34
SB_DM1
AK27
SB_DM2
AK24
SB_DM3
AJ10
SB_DM4
AK5
SB_DM5
AE7
SB_DM6
AB7
SB_DM7
AF34
SB_DQS0
AK32
SB_DQS1
AJ28
SB_DQS2
AK23
SB_DQS3
AM10
SB_DQS4
AH6
SB_DQS5
AF8
SB_DQS6
AB4
SB_DQS7
AF35
SB_DQS0#
AK33
SB_DQS1#
AK28
SB_DQS2#
AJ23
SB_DQS3#
AL10
SB_DQS4#
AH7
SB_DQS5#
AF7
SB_DQS6#
AB5
SB_DQS7#
AH17
SB_MA0
AK17
SB_MA1
AH18
SB_MA2
AJ18
SB_MA3
AK18
SB_MA4
AJ19
SB_MA5
AK19
SB_MA6
AH19
SB_MA7
AJ20
SB_MA8
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
SB_RCVENIN#
SB_RCVENOUT#
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_CAS#
SB_RAS#
SB_WE#
AH20
AJ16
AG18
AG20
AG15
AH14
AK14
AF15
AF14
AH16
M_B_SDM0
M_B_SDM1
M_B_SDM2
M_B_SDM3
M_B_SDM4
M_B_SDM5
M_B_SDM6
M_B_SDM7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
GMCH_TP50
GMCH_TP51
TP53TP53TP54TP54
TP52TP52
E
M_B_BS0# 11,12
M_B_BS1# 11,12
M_B_BS2# 11,12
M_B_SDM[7..0] 11
M_B_DQS[7..0] 11
M_B_DQS#[7..0] 11
M_B_A[13..0] 11,12
M_B_CAS# 11,12
M_B_RAS# 11,12
M_B_WE# 11,12
1 1
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
A
B
C
D
Date: Sheet
GMCH (3 of 5)
GMCH (3 of 5)
GMCH (3 of 5)
Leopard 3
Leopard 3
Leopard 3
E
-1
-1
841Tuesday, July 12, 2005
841Tuesday, July 12, 2005
841Tuesday, July 12, 2005
of
of
of
-1
A
hexainf@hotmail.com
1D5V_TVDAC_S0
3D3V_S0
4 4
SC10U6D3V5MX
SC10U6D3V5MX
3 3
C465
C465
SCD1U10V2MX-1
SCD1U10V2MX-1
3D3V_VGA_S0
R35
R35
1 2
0R3-U
0R3-U
3D3V_VGA_S0
12
C461
C461
3D3V_S0 2D5V_CRTDAC_S0
U66
U66
3
VIN
12
APL5308-25AC-TR
APL5308-25AC-TR
1 2
1 2
1 2
1 2
VOUT
GND
R36
R36
1 2
10R2
10R2
R313
R313
0R3-U
0R3-U
R312
R312
0R3-U
0R3-U
R355
R355
0R3-U
0R3-U
R356
R356
0R3-U
0R3-U
2
1
TVDAC_PWR
12
12
12
12
SC10U6D3V5MX
SC10U6D3V5MX
D2
D2
SSM5818SL
SSM5818SL
3D3V_ATVBG_S0
C310
C310
SCD1U10V2MX-1
SCD1U10V2MX-1
3D3V_TVDACC_S0
C309
C309
SCD1U10V2MX-1
SCD1U10V2MX-1
3D3V_TVDACB_S0
C311
C311
SCD1U10V2MX-1
SCD1U10V2MX-1
3D3V_TVDACA_S0
C314
C314
SCD1U10V2MX-1
SCD1U10V2MX-1
12
C466
C466
U17E
U17E
1D5V_S0
21
1D5V_QTVDAC_S0
1D5V_DLVDS_S0
F17
E17
D18
C18
F18
E18
D19
H17
G18
B26
VSSA_TVBG
B25
VCCD_LVDS0
VCCD_TVDAC
VCCDQ_TVDAC
H18
VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVBG
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1
B
1D5V_S0
R354
R354
0R3-U
0R3-U
Note: All VCCSM
pins shorted
internally
C125
C125
1 2
SCD1U10V2MX-1
SCD1U10V2MX-1
AK26
AC27
AP26
AN26
AM26
AL26
VCCSM5
VCCSM6
VCCSM7
VCCSM8
VCCSM9
VCCSM10
1 2
12
C54
C54
SCD1U10V2MX-1
SCD1U10V2MX-1
AJ26
AH26
AG26
AF26
VCCSM11
VCCSM12
VCCSM13
VCCSM14
0R3-U
0R3-U
AE26
VCCSM15
AP25
AN25
VCCSM16
VCCSM17
1 2
12
C55
C55
SC10U10V5ZY-L
SC10U10V5ZY-L
SC10U10V5ZY-L
SC10U10V5ZY-L
AM25
AL25
AK25
AJ25
VCCSM18
VCCSM19
VCCSM20
G9
G9
GAP-CLOSE-PWR
GAP-CLOSE-PWR
AH25
AG25
VCCSM21
VCCSM22
VCCSM23
POWER
POWER
12
C299
C299
SCD1U10V2MX-1
SCD1U10V2MX-1
R353
R353
1 2
12
C300
C300
SCD1U10V2MX-1
SCD1U10V2MX-1
12
C127
C127
SCD1U10V2MX-1
SCD1U10V2MX-1
12
C126
C126
SCD1U10V2MX-1
SCD1U10V2MX-1
V1.8_DDR_CAP1
V1.8_DDR_CAP2
V1.8_DDR_CAP5
A35
A25
VCCD_LVDS1
VCCD_LVDS2
AM37
AH37
AP29
AD28
B22
B21
A21
VCCHV0
VCCHV1
VCCA_LVDS
AD27
VCCHV2
VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
C351
C351
AF25
VCCSM24
C
1D5V_S0
G10
G10
1 2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
2D5V_S0 2D5V_ALVDS_S0
GAP-CLOSE-PWR
GAP-CLOSE-PWR
2D5V_S02D5V_TVDAC_S0
2D5V_S0 2D5V_TXLVDS_S0
GAP-CLOSE-PWR
GAP-CLOSE-PWR
C59
C59
SCD1U10V2MX-1
SCD1U10V2MX-1
G12
G12
1 2
C63
C63
SCD1U10V2MX-1
SCD1U10V2MX-1
G11
G11
1 2
C61
C61
SCD1U10V2MX-1
SCD1U10V2MX-1
12
12
12
1D5V_DLVDS_S0
12
C58
C58
SC10U10V5ZY-L
SC10U10V5ZY-L
12
C62
C62
SCD01U16V3KX
SCD01U16V3KX
12
C60
C60
SC4D7U10V5ZY
SC4D7U10V5ZY
FOR DDR2
1D8V_S3
Note: All VCCSM
AM12
VCCSM48
VCCSM49
AL12
AK12
AJ12
VCCSM50
VCCSM51
VCCSM52
pins shorted
internally
1 2
SCD1U10V2MX-1
SCD1U10V2MX-1
AH12
AG12
AF12
AE12
VCCSM53
VCCSM54
VCCSM55
TC7
TC7
12
12
C339
C339
SC10U10V5ZY-L
SC10U10V5ZY-L
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AE17
AE16
AE15
AE14
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
12
ST150U4VBM-L1
ST150U4VBM-L1
AP13
AN13
AM13
AL13
AK13
AJ13
AH13
AG13
AF13
AE13
AP12
AN12
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
VCCSM43
VCCSM44
VCCSM45
VCCSM46
VCCSM47
D
12
C131
C131
ST100U6D3VM-U
ST100U6D3VM-U
12
C92
C92
SC10U10V5ZY-L
SC10U10V5ZY-L
1D5V_3GPLL_S0
12
C342
C342
Y27
Y29
Y28
F37
VCCA_3GPLL2
VCCA_3GPLL0
VCCA_3GPLL1
1 2
G37
VSSA_3GBG
VCCA_3GBG
12
C340
C340
SCD1U10V2MX-1
SCD1U10V2MX-1
12
C343
C343
SC10U10V5ZY-L
SC10U10V5ZY-L
12
C123
C123
SCD1U10V2MX-1
SCD1U10V2MX-1
SCD1U10V2MX-1
VCCA_SM3
AE37
VCC3G0
W37
VCC3G1
SCD1U10V2MX-1
U37
R37
N37
L37
VCC3G2
VCC3G3
VCC3G4
VCC3G5
J37
VCC3G6
12
C122
C122
SCD1U10V2MX-1
SCD1U10V2MX-1
C124
C124
AD11
AC11
AB11
VCCSM56
VCCSM57
VCCSM58
2D5V_TXLVDS_S02D5V_ALVDS_S0
V1.8_DDR_CAP4
V1.8_DDR_CAP3
V1.8_DDR_CAP6
AB10
AB9
AP8
AM1
AE1
VCCSM59
VCCSM60
VCCSM61
VCCSM62
VCCSM63
AF20
AP19
AF19
B28
A28
VCCSM64
VCCTX_LVDS0
AF18
A27
VCCA_SM0
VCCA_SM1
VCCA_SM2
VCCTX_LVDS1
VCCTX_LVDS2
E
1D5V_S01D5V_DDRDLL_S0
G29
G29
GAP-CLOSE-PWR
GAP-CLOSE-PWR
1D5V_S01D5V_PCIE_S0
G51
G51
1 2
12
GAP-CLOSE-PWR
GAP-CLOSE-PWR
TC16
TC16
ST100U6D3VM-U
ST100U6D3VM-U
DY
DY
1D5V_S0
G50
G50
1 2
12
GAP-CLOSE-PWR
GAP-CLOSE-PWR
C330
C330
SC10U10V5ZY-L
SC10U10V5ZY-L
2D5V_3GBG_S0 2D5V_S0
1 2
12
C74
C74
SCD1U10V2MX-1
SCD1U10V2MX-1
G13
G13
GAP-CLOSE-PWR
GAP-CLOSE-PWR
VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCCH_MPLL1
VCCH_MPLL0
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL
VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC
VCC_SYNC
VTT0
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23Y9VTT24W9VTT25U9VTT26R9VTT27P9VTT28N9VTT29M9VTT30L9VTT31J9VTT32N8VTT33M8VTT34N7VTT35M7VTT36N6VTT37M6VTT38A6VTT39N5VTT40M5VTT41N4VTT42M4VTT43N3VTT44M3VTT45N2VTT46M2VTT47B2VTT48V1VTT49N1VTT50M1VTT51
J29
T29
R29
12
C329
C329
SCD1U10V2MX-1
SCD1U10V2MX-1
N29
2 2
CORE_GMCH_S0
12
1D5V_S0
2D5V_S0
1D8V_S3
1 1
VCCP_GMCH_S0
CORE_GMCH_S0
12
C341
C341
SC10U10V5ZY-L
SC10U10V5ZY-L
1D5V_S0 5,7,17,18,21,38,39,41
2D5V_S0 7,15,18,40
1D8V_S3 7,10,11,12,38,39,40,41
VCCP_GMCH_S0 4,5,6,7,10,16,18,36,40,41
CORE_GMCH_S0 6,10,40,41
12
C325
C325
SC10U10V5ZY-L
SC10U10V5ZY-L
A
C326
C326
SC10U10V5ZY-L
SC10U10V5ZY-L
K29
V28
U28
M29
12
C328
C328
SCD1U10V2MX-1
SCD1U10V2MX-1
GAP-CLOSE-PWR
GAP-CLOSE-PWR
T28
R28
GMCH_CORE_VCC
P28
N28
G43
G43
J28
L28
K28
M28
12
C327
C327
SCD1U10V2MX-1
SCD1U10V2MX-1
1D5V_S0
12
H28
G28
T27
V27
U27
B
L27
P27
R27
N27
M27
1 2
IND-D1UH
IND-D1UH
L4
L4
1 2
IND-D1UH
IND-D1UH
L22
L22
1 2
IND-D1UH
IND-D1UH
L14
L14
1 2
IND-D1UH
IND-D1UH
L13
L13
K27
J27
H27
J25
K26
K25
H26
12
C56
C56
SC10U6D3V5MX
SC10U6D3V5MX
DY
DY
12
C302
C302
SC10U6D3V5MX
SC10U6D3V5MX
DY
DY
12
C108
C108
SC10U6D3V5MX
SC10U6D3V5MX
DY
DY
12
C107
C107
SC10U6D3V5MX
SC10U6D3V5MX
DY
DY
K24
T20
K23
K22
K21
K20
U20
W20
12
12
12
12
V19
K19
V18
U19
W18
1D5V_HMPLL_S0
1D5V_DPLLA_S0
C57
C57
SCD1U10V2MX-1
SCD1U10V2MX-1
1D5V_DPLLB_S0
C315
C315
SCD1U10V2MX-1
SCD1U10V2MX-1
1D5V_HPLL_S0
C110
C110
SCD1U10V2MX-1
SCD1U10V2MX-1
1D5V_MPLL_S0
C111
C111
SCD1U10V2MX-1
SCD1U10V2MX-1
T18
K18
K17
AC2
AC1
F19
B23
C
C35
AA1
AA2
E19
G19
SCD1U10V2MX-1
SCD1U10V2MX-1
J13
K13
K12
H20
12
C312
C312
SCD022U16V
SCD022U16V
VCCP_GMCH_S0
12
C72
C72
V11
U11
W11
12
SC22U10V6MX
SC22U10V6MX
DY
DY
ST100U6D3VM-U
ST100U6D3VM-U
T11
C459
C459
12
R11
C88
C88
P11
N11
M11
L11
K11
V10
W10
1 2
12
C301
C301
SCD1U10V2MX-1
SCD1U10V2MX-1
12
C313
C313
SCD1U10V2MX-1
SCD1U10V2MX-1
12
C89
C89
SC10U10V6ZY-U
SC10U10V6ZY-U
U10
R357
R357
T10
J10
P10
K10
R10
N10
M10
2D5V_CRTDAC_S0
0R5J
0R5J
Layout Notes: VSSA_CRTDAC
Route caps within 250mil
of Alviso. Route FB
within 3" of Alviso.
R560
R560
1 2
DY
DY
0R3-U
0R3-U
R358
R358
1 2
10R2
10R2
Route VSSA_CRTDAC gnd from GMCH to
decoupling cap ground lead and then
connect to the gnd plane.
D
VCCP_GMCH_CAP1
12
12
C53
C53
SCD47U16V3ZY
SCD47U16V3ZY
2D5V_S0
VCCP_GMCH_S0
D22
D22
21
SC4D7U10V5ZY
SSM5818SL
SSM5818SL
SC4D7U10V5ZY
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
C52
C52
SCD47U16V3ZY
SCD47U16V3ZY
SCD22U16V3ZY
SCD22U16V3ZY
VCCP_GMCH_S0
C324
C324
C90
C90
12
G1
VCCP_GMCH_CAP2
VCCP_GMCH_CAP3
VCCP_GMCH_CAP4
12
12
C71
C71
SCD22U16V3ZY
SCD22U16V3ZY
12
C323
C323
SC4D7U10V5ZY
SC4D7U10V5ZY
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
GMCH (4 of 5)
GMCH (4 of 5)
GMCH (4 of 5)
Leopard 3
Leopard 3
Leopard 3
941Tuesday, August 16, 2005
941Tuesday, August 16, 2005
941Tuesday, August 16, 2005
E
-1
-1
of
of
of
-1
A
4 4
L29
H29
G29
F29
E29
D29
A29
AC28
AB28
AA28
W28
E28
AN27
AL27
AJ27
AG27
AF27
AB27
AA27
W27
G27
E27
B27
J26
G26
E26
A26
AN24
U17F
U17F
ALVISO-GM
ALVISO-GM
3 3
AL24
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS259P2VSS258T2VSS257V2VSS256
VSS255
VSS254
VSS253
VSS252
VSS251A3VSS250C3VSS249
VSS248
VSS247
VSS246
AA3
AB3
AC3
VSS245C4VSS244H4VSS243L4VSS242P4VSS241U4VSS240Y4VSS239
AJ3
AF4
AN4
VSSALVDS
B36
VSS260L2VSS268J2VSS269G2VSS270D2VSS271
Y1
AL2
AE2
AD2
AH2
AN2
B
W31
V31
U31
T31
R31
P31
N31
M31
L31
K31
J31
H31
G31
F31
E31
D31
AP30
AE30
AC30
AB30
AA30
Y30
C30
AM29
AJ29
AG29
AD29
AA29
W29
V29
U29
P29
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS238
VSS237E5VSS236W5VSS235
VSS234
AL5
AP5
VSS233B6VSS232J6VSS231L6VSS230P6VSS229T6VSS228
AA6
VSS227
VSS226
VSS225
VSS224G7VSS223V7VSS222
VSS221
VSS220
VSS219
VSS218C8VSS217E8VSS216L8VSS215P8VSS214Y8VSS213
AJ6
AE6
AA7
AC6
AK7
AN7
AG7
VSS212A9VSS211H9VSS210K9VSS209T9VSS208V9VSS207
AL8
AA9
VSS206
AC9
AD31
AE9
VSS75
VSS205
AG31
VSS74
VSS
VSS
VSS204
AH9
C
AA34
C34
AL33
AF33
AD33
W33
V33
U33
T33
R33
P33
N33
M33
L33
K33
J33
H33
G33
F33
E33
D33
AN32
AJ32
AD32
AC32
AB32
AA32
Y32
C32
A32
AL31
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS196
VSS195
VSS194
VSS193
VSS192
VSS191
VSS190
VSS189
VSS188
VSS187
VSS186
VSS185
VSS184
VSS183
VSS182
VSS181
VSS180
VSS179
VSS178
VSS177
VSS176
VSS175
VSS203
VSS202
VSS201
VSS200
VSS199
VSS198
VSS197
J12
L10
F11
Y11
Y10
D10
AN9
H11
AA11
AA10
B12
AJ11
AL11
AF11
AN11
AG11
D12
J14
F14
A14
B14
K14
AJ14
AG14
VSS174
K15
A16
C15
D16
AL14
H16
AN14
D
AJ36
AF36
AE36
AD36
AC36
AB36
AA36
C36
AE35
Y35
W35
V35
U35
T35
R35
P35
N35
M35
L35
K35
J35
H35
G35
F35
E35
D35
B35
AN34
AH34
AD34
AC34
AB34
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS173
VSS172
VSS171
VSS170
VSS169
VSS168
VSS167
VSS166
VSS165
VSS164
VSS163
VSS162
VSS161
VSS160
VSS159
VSS158
VSS157
VSS156
VSS155
VSS154
VSS153
VSS152
VSS151
VSS150
VSS149
VSS148
VSS147
VSS146
VSS145
VSS144
VSS143
VSS142
VSS141
J19
K16
A18
G17
B18
AJ17
AF17
AN17
C17
AL16
U18
T19
C19
H19
W19
AL18
F20
G20
F21
V20
A22
C21
AK20
E22
D22
AF21
AN21
A20
E20
D20
AN19
AG19
E
CORE_GMCH_S06,9,40,41
VCCP_GMCH_S04,5,6,7,9,16,18,36,40,41
1D8V_S37,9,11,12,38,39,40,41
AL36
AN36
VSS9
VSS10
VSS140
VSS139
J22
AH22
E37
AL22
H37
VSS8
VSS138
H23
K37
VSS7
VSS137
AF23
M37
VSS6
VSS136
B24
P37
VSS5
VSS135
D24
T37
VSS4
VSS134
F24
V37
VSS3
VSS133
J24
Y37
VSS2
VSS132
AG24
AG37
VSS1
VSS131
AJ24
VSS0
VSS130
CORE_GMCH_S0
VCCP_GMCH_S0
1D8V_S3
VCC_NCTF6
VSS_NCTF6
P26
VCC_NCTF5
VSS_NCTF5
Y25
R26
AA25
VCC_NCTF4
VSS_NCTF4
T26
VCC_NCTF3
VSS_NCTF3
AB25
CORE_GMCH_S0
W26
V26
U26
VCC_NCTF0
VCC_NCTF1
VCC_NCTF2
VSS_NCTF2
VSS_NCTF1
VSS_NCTF0
Y26
AA26
AB26
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
GMCH (5 of 5)
GMCH (5 of 5)
GMCH (5 of 5)
Leopard 3
Leopard 3
Leopard 3
10 41Tuesday, July 12, 2005
10 41Tuesday, July 12, 2005
10 41Tuesday, July 12, 2005
E
-1
-1
of
of
-1
AD14
AC14
AD13
VCCSM_NCTF24
VCCSM_NCTF25
VCCSM_NCTF26
VCCSM_NCTF27
VCCP_GMCH_S0
FOR DDR2
AC18
AD17
AC17
AD16
AC16
AD15
AC15
VCCSM_NCTF17
VCCSM_NCTF18
VCCSM_NCTF19
VCCSM_NCTF20
VCCSM_NCTF21
VCCSM_NCTF22
VCCSM_NCTF23
AD21
AC21
AD20
AC20
AD19
AC19
AD18
VCCSM_NCTF13
VCCSM_NCTF14
VCCSM_NCTF15
VCCSM_NCTF16
AD23
AC23
AD22
AC22
VCCSM_NCTF7
VCCSM_NCTF8
VCCSM_NCTF9
VCCSM_NCTF10
VCCSM_NCTF11
VCCSM_NCTF12
VTT_NCTF17
VTT_NCTF16
VTT_NCTF15
VTT_NCTF14
VTT_NCTF13
L12
T12
P12
N12
R12
M12
B
VCCSM_NCTF6
VTT_NCTF12
AC24
U12
VCCSM_NCTF5
VTT_NCTF11
AD24
V12
AC25
VCCSM_NCTF4
VTT_NCTF10
W12
VCCSM_NCTF3
VTT_NCTF9
AD26
AC26
AD25
VCCSM_NCTF0
VCCSM_NCTF1
VCCSM_NCTF2
VTT_NCTF8
VTT_NCTF7
VTT_NCTF6
L13
N13
M13
U17
T17
P17
N17
M17
L17
VCC_NCTF74
VCC_NCTF75
VCC_NCTF76
VCC_NCTF77
VCC_NCTF78
VTT_NCTF5
VTT_NCTF4
VTT_NCTF3
VTT_NCTF2
VTT_NCTF1
VTT_NCTF0
T13
P13
V13
R13
U13
W13
P18
N18
L18
W17
V17
M18
VCC_NTTF69
VCC_NCTF68
VCC_NCTF70
VCC_NCTF71
VCC_NCTF72
VCC_NCTF73
VSS_NCTF68
Y12
AA12
P19
N19
M19
L19
Y18
R18
VCC_NCTF62
VCC_NCTF63
VCC_NCTF64
VCC_NCTF65
VCC_NCTF66
VCC_NCTF67
VSS_NCTF67
VSS_NCTF66
VSS_NCTF65
VSS_NCTF64
VSS_NCTF63
VSS_NCTF62
L14
Y13
P14
N14
M14
AA13
P20
N20
M20
L20
Y19
R19
VCC_NCTF56
VCC_NCTF57
VCC_NCTF58
VCC_NCTF59
VCC_NCTF60
VCC_NCTF61
NCTF
NCTF
VSS_NCTF61
VSS_NCTF60
VSS_NCTF59
VSS_NCTF58
VSS_NCTF57
VSS_NCTF56
T14
V14
Y14
R14
U14
W14
P21
N21
M21
L21
Y20
R20
VCC_NCTF53
VCC_NCTF54
VCC_NCTF55
VSS_NCTF55
VSS_NCTF54
VSS_NCTF53
L15
AA14
AB14
C
V21
U21
T21
VCC_NCTF49
VCC_NCTF50
VCC_NCTF51
VCC_NCTF52
VCC_NCTF47
VCC_NCTF48
VSS_NCTF52
VSS_NCTF51
VSS_NCTF50
VSS_NCTF49
VSS_NCTF48
VSS_NCTF47
T15
P15
N15
R15
U15
M15
R22
P22
N22
M22
L22
W21
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
VCC_NCTF44
VCC_NCTF45
VCC_NCTF46
VSS_NCTF46
VSS_NCTF45
VSS_NCTF44
VSS_NCTF43
VSS_NCTF42
VSS_NCTF41
L16
V15
Y15
W15
AA15
AB15
M23
L23
W22
V22
U22
T22
VCC_NCTF35
VCC_NCTF36
VCC_NCTF37
VCC_NCTF38
VCC_NCTF39
VCC_NCTF40
VSS_NCTF40
VSS_NCTF39
VSS_NCTF38
VSS_NCTF37
VSS_NCTF36
VSS_NCTF35
T16
P16
N16
R16
U16
M16
V23
U23
T23
R23
P23
N23
VCC_NCTF29
VCC_NCTF30
VCC_NCTF31
VCC_NCTF32
VCC_NCTF33
VCC_NCTF34
VSS_NCTF34
VSS_NCTF33
VSS_NCTF32
VSS_NCTF31
VSS_NCTF30
VSS_NCTF29
V16
Y16
R17
W16
AA16
AB16
R24
P24
N24
M24
L24
W23
VCC_NCTF23
VCC_NCTF24
VCC_NCTF25
VCC_NCTF26
VCC_NCTF27
VCC_NCTF28
VSS_NCTF28
VSS_NCTF27
VSS_NCTF26
VSS_NCTF25
VSS_NCTF24
VSS_NCTF23
Y17
AA17
AB17
AA18
AB18
AA19
M25
L25
W24
V24
U24
T24
VCC_NCTF17
VCC_NCTF18
VCC_NCTF19
VCC_NCTF20
VCC_NCTF21
VCC_NCTF22
VSS_NCTF22
VSS_NCTF21
VSS_NCTF20
VSS_NCTF19
VSS_NCTF18
VSS_NCTF17
Y21
R21
AB19
AA20
AB20
AA21
D
V25
U25
T25
R25
P25
N25
VCC_NCTF13
VCC_NCTF14
VCC_NCTF15
VCC_NCTF16
VSS_NCTF16
VSS_NCTF15
VSS_NCTF14
VSS_NCTF13
Y22
AB21
AA22
AB22
N26
M26
L26
W25
VCC_NCTF7
VCC_NCTF8
VCC_NCTF9
VCC_NCTF10
VCC_NCTF11
VCC_NCTF12
VSS_NCTF12
VSS_NCTF11
VSS_NCTF10
VSS_NCTF9
VSS_NCTF8
VSS_NCTF7
Y23
Y24
AA23
AB23
AA24
AB24
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet of
1D8V_S3
AC13
AB13
AD12
AC12
U17H
U17H
2 2
ALVISO-GM
ALVISO-GM
1 1
A
AB12
VCCSM_NCTF28
VCCSM_NCTF29
VCCSM_NCTF30
VCCSM_NCTF31
M_B_A[13..0]8,12
hexainf@hotmail.com
M_B_BS2#8,12
M_B_BS0#8,12
M_B_BS1#8,12
M_B_DATA[63..0]8
M_B_DQS#[7..0]8
M_B_DQS[7..0]8
M_ODT27,12
M_ODT37,12
12
C386
C386
SCD1U16V
SCD1U16V
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_DATA0
M_B_DATA1
M_B_DATA2
M_B_DATA3
M_B_DATA4
M_B_DATA5
M_B_DATA6
M_B_DATA7
M_B_DATA8
M_B_DATA9
M_B_DATA10
M_B_DATA11
M_B_DATA12
M_B_DATA13
M_B_DATA14
M_B_DATA15
M_B_DATA16
M_B_DATA17
M_B_DATA18
M_B_DATA19
M_B_DATA20
M_B_DATA21
M_B_DATA22
M_B_DATA23
M_B_DATA24
M_B_DATA25
M_B_DATA26
M_B_DATA27
M_B_DATA28
M_B_DATA29
M_B_DATA30
M_B_DATA31
M_B_DATA32
M_B_DATA33
M_B_DATA34
M_B_DATA35
M_B_DATA36
M_B_DATA37
M_B_DATA38
M_B_DATA39
M_B_DATA40
M_B_DATA41
M_B_DATA42
M_B_DATA43
M_B_DATA44
M_B_DATA45
M_B_DATA46
M_B_DATA47
M_B_DATA48
M_B_DATA49
M_B_DATA50
M_B_DATA51
M_B_DATA52
M_B_DATA53
M_B_DATA54
M_B_DATA55
M_B_DATA56
M_B_DATA57
M_B_DATA58
M_B_DATA59
M_B_DATA60
M_B_DATA61
M_B_DATA62
M_B_DATA63
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
12
C473
C473
SC2D2U6D3V3MX-1
SC2D2U6D3V3MX-1
102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
84
85
107
106
5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194
11
29
49
68
129
146
167
186
13
31
51
70
131
148
169
188
114
119
1
2
202
DM2
DM2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2
BA0
BA1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
/DQS0
/DQS1
/DQS2
/DQS3
/DQS4
/DQS5
/DQS6
/DQS7
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
ODT0
ODT1
VREF
VSS
GND
DDR2-200P-4
DDR2-200P-4
108
/RAS
109
/WE
113
/CAS
110
/CS0
115
/CS1
79
CKE0
80
CKE1
30
CK0
32
/CK0
164
CK1
166
/CK1
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
SDA
SCL
VDDSPD
SA0
SA1
NC#50
NC#69
NC#83
NC#120
NC#163/TEST
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NORMAL TYPE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
High 9.2mm
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GND
M_B_SDM0
10
M_B_SDM1
26
M_B_SDM2
52
M_B_SDM3
67
M_B_SDM4
130
M_B_SDM5
147
M_B_SDM6
170
M_B_SDM7
185
195
197
199
R575 10KR2R575 10KR2
198
1 2
200
1 2
R574 10KR2R574 10KR2
50
69
83
120
163
81
82
87
88
95
96
103
104
111
112
117
118
3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
145
149
150
155
156
161
162
165
168
171
172
177
178
183
184
187
190
193
196
201
1D8V_S3
0329 SB
3D3V_S0
SCD1U16V
SCD1U16V
M_B_RAS# 8,12
M_B_WE# 8,12
M_B_CAS# 8,12
M_CS2_R# 7,12
M_CS3_R# 7,12
M_CKE2_R# 7,12
M_CKE3_R# 7,12
CLK_DDR3 7
CLK_DDR3# 7
CLK_DDR4 7
CLK_DDR4# 7
M_B_SDM[7..0] 8
SMBD_ICH 3,19
SMBC_ICH 3,19
C469
C469
Hi 9.2 mm
12
3D3V_S0
12
C471
C471
SC2D2U6D3V3MX-1
SC2D2U6D3V3MX-1
DY
DY
DM1
M_A_A[13..0]8,12
M_A_BS2#8,12
M_A_BS0#8,12
M_A_BS1#8,12
M_A_DATA[63..0]8
M_A_DQS#[7..0]8
M_A_DQS[7..0]8
M_ODT07,12
DDR_VREF_S3DDR_VREF_S3
M_ODT17,12
C182
C182
SCD1U16V
SCD1U16V
12
12
SC2D2U6D3V3MX-1
SC2D2U6D3V3MX-1
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_DATA0
M_A_DATA1
M_A_DATA2
M_A_DATA3
M_A_DATA4
M_A_DATA5
M_A_DATA6
M_A_DATA7
M_A_DATA8
M_A_DATA9
M_A_DATA10
M_A_DATA11
M_A_DATA12
M_A_DATA13
M_A_DATA14
M_A_DATA15
M_A_DATA16
M_A_DATA17
M_A_DATA18
M_A_DATA19
M_A_DATA20
M_A_DATA21
M_A_DATA22
M_A_DATA23
M_A_DATA24
M_A_DATA25
M_A_DATA26
M_A_DATA27
M_A_DATA28
M_A_DATA29
M_A_DATA30
M_A_DATA31
M_A_DATA32
M_A_DATA33
M_A_DATA34
M_A_DATA35
M_A_DATA36
M_A_DATA37
M_A_DATA38
M_A_DATA39
M_A_DATA40
M_A_DATA41
M_A_DATA42
M_A_DATA43
M_A_DATA44
M_A_DATA45
M_A_DATA46
M_A_DATA47
M_A_DATA48
M_A_DATA49
M_A_DATA50
M_A_DATA51
M_A_DATA52
M_A_DATA53
M_A_DATA54
M_A_DATA55
M_A_DATA56
M_A_DATA57
M_A_DATA58
M_A_DATA59
M_A_DATA60
M_A_DATA61
M_A_DATA62
M_A_DATA63
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
C474
C474
102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
84
85
107
106
5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194
11
29
49
68
129
146
167
186
13
31
51
70
131
148
169
188
114
119
1
2
202
DM1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2
BA0
BA1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
/DQS0
/DQS1
/DQS2
/DQS3
/DQS4
/DQS5
/DQS6
/DQS7
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
ODT0
ODT1
VREF
VSS
GND
DDR2-200P-5
DDR2-200P-5
108
/RAS
109
/WE
113
/CAS
110
/CS0
115
/CS1
79
CKE0
80
CKE1
30
CK0
32
/CK0
164
CK1
166
/CK1
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
SDA
SCL
VDDSPD
SA0
SA1
NC#50
NC#69
NC#83
NC#120
NC#163/TEST
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NORMAL TYPE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Low5.2 mm
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GND
10
26
52
67
130
147
170
185
195
197
199
198
200
50
69
83
120
163
81
82
87
88
95
96
103
104
111
112
117
118
3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
145
149
150
155
156
161
162
165
168
171
172
177
178
183
184
187
190
193
196
201
M_A_SDM0
M_A_SDM1
M_A_SDM2
M_A_SDM3
M_A_SDM4
M_A_SDM5
M_A_SDM6
M_A_SDM7
SMBD_ICH
SMBC_ICH
R573 10KR2R573 10KR2
1 2
1 2
R572 10KR2R572 10KR2
1D8V_S3
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
M_A_RAS# 8,12
M_A_WE# 8,12
M_A_CAS# 8,12
M_CS0_R# 7,12
M_CS1_R# 7,12
M_CKE0_R# 7,12
M_CKE1_R# 7,12
CLK_DDR0 7
CLK_DDR0# 7
CLK_DDR1 7
CLK_DDR1# 7
M_A_SDM[7..0] 8
0329 SB
SCD1U16V
SCD1U16V
DDR_VREF_S37,40
12
12
C470
C470
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
DDR Socket
DDR Socket
DDR Socket
Leopard 3
Leopard 3
Leopard 3
1D8V_S37,9,10,12,38,39,40,41
DDR_VREF_S3
3D3V_S03,5,7,9,13,14,16,17,18,19,20,21,22,23,24,25,27,29,30,31,32,36,38,40,41
3D3V_S0
C472
C472
SC2D2U6D3V3MX-1
SC2D2U6D3V3MX-1
DY
DY
11 41Tuesday, August 16, 2005
11 41Tuesday, August 16, 2005
11 41Tuesday, August 16, 2005
of
of
of
1D8V_S3
3D3V_S0
-1
-1
-1
PLACE CAPS BETWEEN AND NEAR DDR SKTS
PLACE EACH 0.1UF CAP CLOSE TO POWER
1D8V_S3
PIN
12
C200
C200
SC1U6D3V2KX
SC1U6D3V2KX
12
C146
C146
SC1U6D3V2KX
SC1U6D3V2KX
12
12
SC2D2U6D3V3MX-1
SC2D2U6D3V3MX-1
C203
C203
SCD1U16V
SCD1U16V
C355
C355
12
C175
C175
SC1U6D3V2KX
SC1U6D3V2KX
12
C365
C365
SC1U6D3V2KX
SC1U6D3V2KX
12
C375
C375
SC10U10V5ZY-L
SC10U10V5ZY-L
12
C366
C366
SC2D2U6D3V3MX-1
SC2D2U6D3V3MX-1
12
C164
C164
SC1U6D3V2KX
SC1U6D3V2KX
12
12
12
C157
C157
SC1U6D3V2KX
SC1U6D3V2KX
12
C147
C147
SCD1U16V
SCD1U16V
C383
C383
SC10U10V5ZY-L
SC10U10V5ZY-L
12
C384
C384
SC2D2U6D3V3MX-1
SC2D2U6D3V3MX-1
C170
C170
SCD1U16V
SCD1U16V
12
C165
C165
SC1U6D3V2KX
SC1U6D3V2KX
12
C174
C174
SCD1U16V
SCD1U16V
12
EC39
EC39
SCD1U16V
SCD1U16V
12
C392
C392
SC2D2U6D3V3MX-1
SC2D2U6D3V3MX-1
For 1GB Memory
12
C166
C166
SC1U6D3V2KX
SC1U6D3V2KX
12
C198
C198
SCD1U16V
SCD1U16V
12
EC36
EC36
SCD1U16V
SCD1U16V
12
C390
C390
SC2D2U6D3V3MX-1
SC2D2U6D3V3MX-1
12
C364
C364
SC1U6D3V2KX
SC1U6D3V2KX
12
C192
C192
SCD1U16V
SCD1U16V
12
EC42
EC42
SCD1U16V
SCD1U16V
12
SC2D2U6D3V3MX-1
SC2D2U6D3V3MX-1
C389
C389
12
12
12
C363
C363
SCD1U16V
SCD1U16V
C186
C186
SCD1U16V
SCD1U16V
EC44
EC44
SCD1U16V
SCD1U16V
12
TC23
TC23
ST100U4VBM-U
ST100U4VBM-U
M_CKE2_R#7,11
M_B_BS1#8,11
M_B_A08,11
M_B_A28,11
M_CS3_R#7,11
M_B_CAS#8,11
M_B_WE#8,11
M_B_BS0#8,11
M_B_A78,11
M_CKE3_R#7,11
Address / Command
M_A_BS1#8,11
M_A_RAS#8,11
M_CS0_R#7,11
M_A_A138,11
M_B_A98,11
M_B_BS2#8,11
M_B_A138,11
M_CS2_R#7,11
M_B_RAS#8,11
M_A_WE#8,11
M_A_BS0#8,11
M_A_CAS#8,11
M_CS1_R#7,11
M_CKE0_R#7,11
M_A_BS2#8,11
M_A_A128,11
M_A_A98,11
M_CKE1_R#7,11
M_A_A118,11
M_A_A88,11
M_A_A58,11
M_A_A18,11
M_A_A08,11
M_A_A38,11
M_A_A108,11
M_A_A78,11
M_A_A68,11
M_A_A48,11
M_A_A28,11
M_B_A48,11
M_B_A68,11
M_B_A88,11
M_B_A128,11
M_B_A118,11
M_B_A108,11
M_B_A18,11
M_B_A38,11
M_B_A58,11
Control
RN69
RN69
1
2
3
4 5
SRN56-1
SRN56-1
SRN56-1
SRN56-1
RN70
RN70
1
2
3
4 5
SRN56-1
SRN56-1
RN71
RN71
1
2
3
4 5
SRN56-1
SRN56-1
0D9V_S0
RN68
RN68
1
2
3
4 5
SRN56-1
SRN56-1
8
7
6
RN22
RN22
1
2
3
4 5
SRN56-1
SRN56-1
RN7
RN7
1
2
3
4 5
SRN56-1
SRN56-1
RN49
RN49
1
2
3
4 5
SRN56-1
SRN56-1
RN21
RN21
1
2
3
4 5
SRN56-1
SRN56-1
RN50
RN50
1
2
3
4 5
RN48
RN48
1
2
3
4 5
SRN56-1
SRN56-1
RN67
RN67
1
2
3
4 5
SRN56-1
SRN56-1
RN8
RN8
1
2
3
4 5
SRN56-1
SRN56-1
8
7
6
8
7
6
8
7
6
8
7
6
8
7
6
8
7
6
0D9V_S0
8
7
6
8
7
6
8
7
6
8
7
6
8
7
6
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
C180
C180
SCD01U16V2KX
SCD01U16V2KX
DY
DY
C404
C404
SCD1U16V
SCD1U16V
C358
C358
SCD01U16V2KX
SCD01U16V2KX
DY
DY
C196
C196
SCD1U16V
SCD1U16V
C356
C356
SCD01U16V2KX
SCD01U16V2KX
DY
DY
C399
C399
SCD1U16V
SCD1U16V
C197
C197
SCD01U16V2KX
SCD01U16V2KX
DY
DY
C202
C202
SCD1U16V
SCD1U16V
C396
C396
SCD1U16V
SCD1U16V
C403
C403
SCD01U16V2KX
SCD01U16V2KX
DY
DY
C194
C194
SCD1U16V
SCD1U16V
C357
C357
SCD01U16V2KX
SCD01U16V2KX
DY
DY
C161
C161
SCD1U16V
SCD1U16V
C388
C388
SCD01U16V2KX
SCD01U16V2KX
DY
DY
C181
C181
SCD1U16V
SCD1U16V
C385
C385
SCD01U16V2KX
SCD01U16V2KX
DY
DY
C405
C405
SCD1U16V
SCD1U16V
C177
C177
SCD01U16V2KX
SCD01U16V2KX
DY
DY
C401
C401
SCD1U16V
SCD1U16V
C187
C187
SCD01U16V2KX
SCD01U16V2KX
DY
DY
C193
C193
SCD1U16V
SCD1U16V
C387
C387
SCD1U16V
SCD1U16V
DY
DY
C395
C395
SCD1U16V
SCD1U16V
C171
C171
SCD01U16V2KX
SCD01U16V2KX
DY
DY
0D9V_S0
0D9V_S039
1D8V_S3
1D8V_S37,9,10,11,38,39,40,41
0D9V_S0
R585 56R2JR585 56R2J
M_ODT07,11
M_ODT17,11
M_ODT27,11
M_ODT37,11
1 2
R586 56R2JR586 56R2J
1 2
R587 56R2JR587 56R2J
1 2
R588 56R2JR588 56R2J
1 2
Wistron Corporation
Wistron Corporation
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
Date: Sheet
DDR Serial/Terminator Resistor
DDR Serial/Terminator Resistor
DDR Serial/Terminator Resistor
Leopard 3
Leopard 3
Leopard 3
12 41Thursday, August 18, 2005
12 41Thursday, August 18, 2005
12 41Thursday, August 18, 2005
of
of
of
-1
-1
-1
A
hexainf@hotmail.com
Digital Signal CONN
CN5
CN5
21
4 4
22
JST-CON20
JST-CON20
USB_PP1
1
USB_PN1
2
3
USB_PP3
4
USB_PN3
5
6
CRMA_CN5
7
LUMA_CN5
8
9
10
11
12
13
14
15
16
17
18
19
20
5V_S3
5V_S3
DDC_DATA 15
DDC_CLK 15
JVGA_HS 7
JVGA_VS 7
5V_S0
CRT_R 15
CRT_G 15
CRT_B 15
USB_PP1 17
USB_PN1 17
USB_PP3 17
USB_PN3 17
LINE-OUT
LUMA_CN5
CRMA_CN5
BC12
BC12
SC3P50V2CN
SC3P50V2CN
12
12
SC3P50V2CN
SC3P50V2CN
Analog Signal CONN
CN6
CN6
11
MIC_PR
1
2
3
4
5
3 3
2 2
1 1
6
7
8
9
10
12
MOLEX-CON10-1
MOLEX-CON10-1
AUD_AGND
BC0EX126
BC0EX226
DOCK_PRESENT
EXT_MIC_1 27
EXT_MIC_2 27
HP_OUT_R 27
HP_OUT_L 27
EARPHONE 28
LID_SW 14
3D3V_S0
12
R432
R432
47KR2
47KR2
63.47334.1D1
63.47334.1D1
1 2
DY
DY
1 2
DY
DY
Please close to ICH6
R63
R63
1 2
47R2
47R2
12
R64
R64
2K2R2
2K2R2
EARPHONE
DUMMY-R2
DUMMY-R2
DUMMY-R2
DUMMY-R2
5V_S0
1
MIC-IN
R495
R495
R225
R225
12
R309
R309
10KR2
10KR2
PR_INSERT#
3
Q17
Q17
S2N3904-U3
S2N3904-U3
2
PR_PRESENT#
ICH_PME# 17,25,29
PCI_AD24 17,22,25,29
PR_INSERT# 31
1 2
BLM11B750S
BLM11B750S
L12
L12
1 2
L15
L15
BC13
BC13
SC3P50V2CN
SC3P50V2CN
LID_SW
B
BLM11B750S
BLM11B750S
C99
C99
DY
DY
3
12
D31
D31
BAV99LT1
BAV99LT1
12
C102
C102
SC3P50V2CN
SC3P50V2CN
DY
DY
3D3V_S3
2
1
LUMA
CRMA
R94
R94
150R2F
150R2F
AUD_AGND
D29
D29
VOL_UP_DK# VOL_DWN_DK#
12
12
R91
R91
150R2F
150R2F
1 2
3
BAV99LT1
BAV99LT1
DY
DY
5V_S3 AD+
12
C337
C337
SCD1U16V
SCD1U16V
SPDIF_OUT27
EC124
EC124
SCD1U16V
SCD1U16V
DY
DY
C
5V_S0 5V_S0
D30
2
1
AUD_AGND
DK_SPKR_R+28
DK_SPKR_L+28
VOL_DWN_DK#31
12
R65
R65
1KR2
1KR2
5V_S0
12
C70
C70
SCD1U25V3KX
SCD1U25V3KX
SPDIF_OUT
VOL_UP_DK#31
DCBATOUT_BEAD
12
12
D30
2
3
1
BAV99LT1
BAV99LT1
DY
DY
PR_PRESENT#
RJ45-426
RJ45-526
RJ45-126
RJ45-226
USB_PN717
USB_PP717
TP40TPAD30 TP40TPAD30
R333
R333
1 2
0R2-0
0R2-0
5V_DOCK
DCBATOUT_BEAD
C458
C458
SCD1U16V
SCD1U16V
1 2
L19
L19
C464
C464
SC470P25V2KN
SC470P25V2KN
CRMA_PR
CIR_PR
AD+ AD+
12
C69
C69
SCD1U25V3KX
SCD1U25V3KX
SPDIF
BLM18PG600SN1
BLM18PG600SN1
D
Docking Connector
CN12
MIC_PR
USB_PN7
USB_PP7
IR_OUT
COMP_PR
LUMA_PR
5V_S0
12
12
SC470P25V2KN
SC470P25V2KN
CN12
MH1
MH2
C338
C338
SCD1U16V
SCD1U16V
C51
C51
Place near the DOCK
60
5556
12
34
56
78
910
1112
1314
1516
1718
1920
2122
2324
2526
2728
2930
3132
3334
3536
3738
3940
4142
4344
4546
4748
4950
5152
5354
5758
59
FOX-CONN58D-U3
FOX-CONN58D-U3
LUMA_PR
C296
C296
SC47P50V2JN
SC47P50V2JN
COMP_PR
12
C295
C295
SC47P50V2JN
SC47P50V2JN
SPDIF
5V_Dock_S0
1 2
DOCK_PRESENT
HIGH B1
1 2
L26
L26
12
SC47P50V2JN
SC47P50V2JN
CRMA_PR
1 2
L24
L24
12
C294
C294
SC47P50V2JN
SC47P50V2JN
1 2
IND-1D2UH
IND-1D2UH
L25
L25
C298
C298
SC47P50V2JN
SC47P50V2JN
IND-1D2UH
IND-1D2UH
C297
C297
IND-1D2UH
IND-1D2UH
12
R335
R335
150R2F
150R2F
0R2-0
0R2-0
FUNCTIONINPUT
R43
R43
5V_DOCK
B0LOW
LUMA_PR_1
12
R334
R334
150R2F
150R2F
CRMA_PR_1
12
C307
C307
SC47P50V2JN
SC47P50V2JN
12
12
RJ45-7 26
RJ45-8 26
RJ45-3 26
RJ45-6 26
JACK_DETECT# 28
5V_S0
MUTE_LED 14,31
1394_TPA1P_PR 26
1394_TPA1N_PR 26
1394_TPB1P_PR 26
1394_TPB1N_PR 26
LUMA
12
R372
R372
150R2F
150R2F
JACK_DETECT#
MUTE_LED
AUD_AGND
MIC_PR
DK_SPKR_R+
DK_SPKR_L+
COMP_PR
VOL_UP_DK#
VOL_DWN_DK#
DOCK_PRESENT
PR_PRESENT#
BT_LED
BT_LED 14,26
Place near the GMCH
U7
U7
1
B1
2
GND
B03A
U8
U8
1
B1
2
GND
B03A
VCC
NC7SB3157P6X-U
NC7SB3157P6X-U
VCC
NC7SB3157P6X-U
NC7SB3157P6X-U
R536
R536
1 2
0R2-0
0R2-0
6
S
5
4
6
S
5
4
E
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
5V_S0
3D3V_S03,5,7,9,11,14,16,17,18,19,20,21,22,23,24,25,27,29,30,31,32,36,38,40,41
5V_S014,18,19,20,21,23,24,27,28,29,32,36,39,40,41
5V_S314,26,28,30,32,37,38,40,41
DCBATOUT14,35,37,38,39,40,41
5V_AUX14,15,35,37,38,39
PR_INSERT#
PR_INSERT#CRMA
DCBATOUT
EC8
EC8
SCD1U16V
SCD1U16V
EC11
EC11
SCD1U16V
SCD1U16V
EC93
EC93
SCD1U16V
SCD1U16V
EC95
EC95
SC1000P16V2KX
SC1000P16V2KX
EC94
EC94
SC1000P16V2KX
SC1000P16V2KX
EC102
EC102
SC1000P16V2KX
SC1000P16V2KX
EC100
EC100
SC1000P16V2KX
SC1000P16V2KX
EC101
EC101
SC1000P16V2KX
SC1000P16V2KX
EC103
EC103
SC1000P16V2KX
SC1000P16V2KX
EC20
EC20
SC1000P16V2KX
SC1000P16V2KX
EC92
EC92
SC1000P16V2KX
SC1000P16V2KX
EC19
EC19
SC1000P16V2KX
SC1000P16V2KX
LUMA_VGA 7
CRMA_VGA 7
COMP_VGA 7
3D3V_S0
5V_S0
5V_S3
5V_AUX
5V_S3
F3
F3
1 2
FUSE-2A6V
FUSE-2A6V
12
A
5V_DOCK
12
C305
C305
C306
C306
SCD1U16V
SCD1U16V
SC4D7U10V5ZY
SC4D7U10V5ZY
100 mil
12
TC15
TC15
ST47U6D3V-U1
ST47U6D3V-U1
DY
DY
Wistron Corporation
Wistron Corporation
R259
R259
C
1 2
1 2
0R2-0
0R2-0
R371
R371
0R2-0
0R2-0
CIR_KBC 31
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
D
Date: Sheet
Board to board conn/ Docking
Board to board conn/ Docking
Board to board conn/ Docking
CIR15
CIR_PR
CIR,CIR_PR,CIR_KBC are connect togather. default setting 12/12
B
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Taipei Hsien 221, Taiwan, R.O.C.
Leopard 3
Leopard 3
Leopard 3
E
-1
-1
of
13 41Monday, August 15, 2005
13 41Monday, August 15, 2005
13 41Monday, August 15, 2005
-1
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