HP CQ40 Intel Schematics

A

www.kythuatvitinh.com

Digitally signed by dd
DN: cn=dd, o=dd, ou=dd,
email=[e-mail],
c=US
Date: 2009.11.12 09:03:29
+07'00'

1 1

2 2

B

C

D

E

Compal confidential

Schematics Document

Mobile Penryn uFCPGA with Intel
Cantiga_GM+ICH9-M core logic

3 3

2008-01-01

4 4

A

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Do cument Number Re v

Cu st om

D

Da te: Sheet

Compal Electronics, Inc.

Cover Sheet

Montev ina Blade UMA LA4101P

E

0.3

o f

1 46Sa turd ay, January 05, 200 8

A

www.kythuatvitinh.com

B

C

D

E

Compal confidential

1 1

LVDS Panel
Interface

CRT

Support V1.3

2 2

PCIE
CardReader
JMB385

P27

RTL8102EL
(10/100M)

HDMI

P25

P19

P18

P35

Mini-Card

WLAN

Thermal Sensor
EMC1402

Fan conn

Mini-Card

TV-tuner or
Robson

Montevina Consumer 14" UMA

Mobile Penryn

P06

P06

PCI-E BUS*5

New Card

P26P26

DMI X4

P26

uFCPGA-478 CPU

P6, 7, 8

H_A#(3..35)
H_D#(0..63)

FSB

667/800/1066 MHz 1.05V

Intel Cantiga MCH

FCBGA 1329

P9,10, 11, 12, 13, 14

C-Link

Intel ICH9-M

mBGA-676

P20,21,22,23

DDR2 667MHz 1.8V

Dual Channel

USB2.0 X12

Azalia
SATA Master-1

SATA Slave
SATA Slave

CK505

72QFN

Clock Generator
SLG8SP553V

P17

DDR2 SO-DIMM X2

BANK 0, 1, 2, 3

USB conn x1

BT Conn

USB Camera

Finger print

Codec_IDT9271B7

P15, 16

P30

P30

P19

P30

Audio CKT AMP & Audio Jack

P28 P29

TPA6017A2

5 in1 Slot

3 3

RJ45/11 CONN

P33

P25

LPC BUS

MDC

P29

SATA HDD Connector

P24

ENE

RTC CKT.

ACCELEROMETER-1
ST

ACCELEROMETER-2
BOSCH

4 4

K/B backlight Conn

P21

LED

P33

P24

P24

P33

Dock

USB2.0*1
RGB
RJ45
SPDIF
CIR
MIC*1
LINE-OUT*1

Touch Pad CONN.

P33

DC/DC Interface CKT.

P36

A

P34

B

KB926

SPI ROM
25LF080A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

P31

C

SPI

P32

Int.KBD

P32

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

SATA ODD Connector

e-SATA Connector

Title

Size Do cument Number Re v

Cu st om

D

Da te: Sheet o f

P24

P30

Capsense switch Conn

Compal Electronics, Inc.

Block Diagram

Montev ina Blade UMA LA4101P

USB Board Conn
USB conn x2

Audio board

、

CIR Conn

2 46Sa turd ay, January 05, 200 8

E

P30

P29

P33

0.3

A

www.kythuatvitinh.com

Symbol Note :

Voltage Rails

power
plane

State

S0

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

1 1

O MEANS ON X MEANS OFF

+B

O
O
O
O
O

+5VALW

+3VALW

O
O
O
O

X
XX

+1.8V

: means Digital Ground

: means Analog Ground

+5VS
+3VS
+1.5VS
+0.9V
+VCCP
+CPU_CORE
+2.5VS
+1.8VS

O
O
O

X
X
X

O
O

X
X
X
X

@ : means just reserve , no build

45@ : means need be mounted when 45 level assy or rework stage.

DEBUG@ : means just reserve for debug.

BATT @ : means need be mounted when 45 level assy or rework stage.
CONN@ : means ME part

ESATA @ : means just reserve for ESATA

GS @ : means just reserve for G sensor
FP @ : means just reserve for Finger Print

Multi @ : means just reserve for Multi Bay
NewC@ : means just reserve for New card
DOCK@ : means just reserve for Docking

Main@ : means just reserve for Main stream

OPP@ : means just reserve for OPP
2MiniC@ : means just reserve for 2nd Mini card slot

USB assignment:

USB-0 Right side
USB-1 Right side
USB-2 Left side(with ESATA)
USB-3 Dock
USB-4 Camera
USB-5 WLAN
USB-6 Bluetooth
USB-7 Finger Printer
USB-8 MiniCard(WWAN/TV)
USB-9 Express card
USB-10 X
USB-11 X

PCIe assignment:

PCIe-1 TV /WWAN/Robeson
PCIe-2 X
PCIe-3 WLAN

PCIe-4 GLAN (Realtek)

PCIe-5 Card reader

PCIe-6 New Card

SMBUS Control Table

SOURCE

SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
SMB_CK_CLK1
SMB_CK_DAT1
LCD_CLK
LCD_DAT

KB926

KB926

ICH9

Cantiga

43154432L01 Main@/DEBUG@/DOCK@/NewC@/FP
43154432L02 Main@/DEBUG@/DOCK@/NewC
43154432L03 Main@/DEBUG@/DOC
43154432L04 OP
43154432L05 OP

DA600007100 --->Main
DAZ03V00100 --->OPP

INVERTER BATT

：：：：
：：：：
：：：：
：：：：

P@/DEBUG@

：：：：

P@/DEBUG@

X V
X
X
X

SERIAL
EEPROM

X
X
X

Thermal
Sensor

V

X
X
X

X

V

X
X

SODIMM CLK CHIP

X
X

V V V

X

@/ESATA@/GS@/Multi@/2MiniC@

@/FP@/ESATA@/GS@/2MiniC@

K@/NewC@/FP@/2MiniC@

MINI CARD

X
X

X

X
X

X

Cap sensor

LCD

board

X
X
X

V

V

X
X
X

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

NEW CARD G sensor

X X
X

V V

X

2007/08/28 2006/03/10

A

X

X

Compal Secret Data

I2C / SMBUS ADDRESSING

DEVICE

DDR SO-DIMM 0
DDR SO-DIMM 1
CLOCK GENERATOR (EXT.)

43154432L01 UMA GM
43154432L02 UMA GM
43154432L03 UMA
43154432L04 UMA GM
43154432L05 U

：：：：
：：：：
：：：：
：：：：
：：：：

Cantiga GM45 B0(QR32) SA00001P930
ICH9M A2 ES2 Base

Deciphered Date

HEX

A0

D2

PA FF (SI-1)
PR FF (SI-1)

GL PR FF-

OPP (SI-1)

MA GL OPP

：：：：

：：：：

SA00002AN10

Title

Size Document Number Re v

Cu stom

Da te: Sheet o f

ADDRESS

1 0 1 0 0 0 0 0
1 0 1 0 0 1 0 0A4
1 1 0 1 0 0 1 0

Compal Electronics, Inc.

Montev ina Blade UMA LA4101P

Notes List

3 46Sa turday, January 05 , 20 08

0.3

5

www.kythuatvitinh.com

4

3

2

1

50mA

177mA

1A

D D

VIN

AC

C C

B+

7A

+V_BATTERY Dock con

0.3A

INVPWR_B+

2A

B++

LVDS CON

1.7A

+3VALW

+1.5VS

+5VALW

300mA

60mA

20mA

10mA

550mA

657mA

2.2A0.3A

1.3A0.58A

1.56A

ICH9

LAN +3VS_DVDD

+3VAUX_BT

+3VALW_EC

SPI ROM

3.39A5.89A

+3VS

50mA

25mA

35mA

1A

278mA

1.5A

JMB385

250mA

ICH_VCC1_5
ICH9

ICH9

+5VS

35mA

10mA

1A

1A

+VDDA
IDT 9271B7

+5VAMP

Finger printer

PC Camera

ALC268

MDC 1.5

New card

ICH9

+LCDVDD

LVDS CON

+3VS_CK505

Mini card (WLAN)

Mini card (TV tu/WWAN/Robeson)

1.8A

700mA

B B

3.7 X 3=11.1V

DC BATT

B+++

A A

CPU_B+ +VCC_CORE

12.11A1.9A

4.7A

10mA2A

+1.8V

1.05V_B+

34A/1.025V

5

4

3.7A

8 A

50mA

+VCCP

CPU

MCH

1.8A

DDR2 800Mhz 4G x2

+0.9V

1.17A

1.26A

2.3A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

ICH9

MCH

CPU

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

2

ODD

SATA

Muti Bay

Compal Electronics, Inc.

Title

Size Doc ume nt Number Re v

C

Mo ntevina Blade UMA LA4101P

Dat e: Sheet of

Power delivery

1

4 46Sat urd ay, Ja nuar y 05, 2008

0.3

A

www.kythuatvitinh.com

1 1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Re v

Cu stom

Da te: Sheet o f

Compal Electronics, Inc.

Power sequence

Montev ina Blade UMA LA4101P

5 46Sa turday, January 05 , 20 08

0.3

5

www.kythuatvitinh.com

4

3

2

1

R1

ITP-XDP Connector

XDP _DBRESE T#_R

@

1 2

Change value in 5/02

JP1

1

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

+3VS

FA N_PWM<32>

Deciphered Date

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A0
OBSDATA_A1
GND4
OBSDATA_A2
OBSDATA_A3
GND6
OBSFN_B0
OBSFN_B1
GND8
OBSDATA_B0
OBSDATA_B1
GND10
OBSDATA_B2
OBSDATA_B3
GND12
PWRGOOD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
GND14
SDA
SCL
TCK1
TCK0
GND16

SAMTE_BSH-030-01-L-D-A

C ONN@

+3VS

1

C2

2

0.1U_0402_16V4Z

C3

1 2

220 0P_ 0402_50V7K

R16

1 2

10K _0402_5%

RB751V_SOD323

OBSDATA_C0
OBSDATA_C1

OBSDATA_C2
OBSDATA_C3

OBSDATA_D0
OBSDATA_D1

OBSDATA_D2
OBSDATA_D3

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

H_ THERMDA
H_ TH ERMDC

THERM#

D1

1

G

3

2

D D

H_ A#[3..16]<9>

H_ADSTB#0<9>

H_REQ#0<9>
H_REQ#1<9>
H_REQ#2<9>
H_REQ#3<9>
H_REQ#4<9>

C C

B B

A A

H_A#[1 7..35]<9>

H_ADSTB#1<9>

H_A20M#<21>

H_ FE RR#<21>

H_ IGNNE#<21>
H_STPCLK#<21>

H_ INT R<21>
H_ NMI<21>
H_SMI#<21>

+V CCP

B

H_ P ROCHOT# OCP#

H_ IE RR#

E

3 1

Q1

@

MMBT3904_NL_SOT23-3

+V CCP

12

@

R17
56_ 0402_5%

2

C

R18
56_ 0402_5%

1 2

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0

H_ REQ#0
H_ REQ#1
H_ REQ#2
H_ REQ#3
H_ REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1

H_A20M#
H_ FERR#
H_ IG NNE#

H_STPCLK#
H_ INTR
H_ NMI
H_SMI#

5

J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1

K3
H2
K2
J3
L1

Y2
U5
R3

W6

U4
Y5
U1
R4
T5

T3
W2
W5

Y4

U2

V4
W3

AA4
AB2
AA3

V1

A6

A5

C4

D5

C6

B4

A3

M4

N5

T2

V3

B2

D2

D22

D3

F6

OCP # <22>

JC PU1A

A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#

REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#

A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#

A20M#
FERR#
IGNNE#

STPCLK#
LINT0
LINT1
SMI#

RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]

Pe nryn

ADDR GROUP_0

ADDR GROUP_1

ICH

ADS#
BNR#

BPRI#

DEFER#

DRDY#
DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

RESET#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HITM#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#
PREQ#

TRST#

DBR#

XDP/ITP SIGNALS

THERMAL

PROCHOT#

THERMDA
THERMDC

THERMTRIP#

H CLK

BCLK[0]
BCLK[1]

RESERVED

HIT#

TCK
TDO

TMS

H_ ADS #

H1

H_ B NR#

E2

H_ BP RI#

G5

H_ DE FER#

H5

H_ DRDY#

F21

H_ DBSY#

E1

H_ BR0#

F1

H_ IE RR#

D20

H_ INIT#

B3

H_ LOCK #

H4

H_RE SET#

C1

H_ RS#0

F3

H_ RS#1

F4

H_ RS#2

G3

H_ TRDY#

G2

H_ HIT#

G6

H_ HITM#

E4

XDP _BPM#0

AD4

XDP _BPM#1

AD3

XDP _BPM#2

AD1

XDP _BPM#3

AC4

XDP _BPM#4

AC2

XDP _BPM#5

AC1

XDP _TCK

AC5

XDP _TDI

AA6

TDI

XDP _TDO

AB3

XDP_TMS

AB5

XDP _TRST#

AB6

XDP _DBRESET#

C20

H_ P ROCHOT#

D21
A24

H_ TH ERMDC_R

B25

H_THERMTRIP#

C7

CL K_CPU_B CLK

A22

CL K_CPU_B CLK #

A21

For Merom, R14 and R15 are 0ohm
For Penryn, R14 and R15 are 100ohm.

H_ADS# <9>
H_ BNR# <9>

H_ BPRI# <9>

H_ DEFER# <9>
H_ DRDY# <9>
H_ DBS Y# <9>

H_BR0# <9>

H_ INIT# <21>
H_LOCK# <9>
H_RE SET# <9>

H_RS#0 <9>

H_RS#1 <9>

H_RS#2 <9>

H_ TRDY# <9>

H_HIT# <9>
H_HITM# <9>

R13 49.9_0402_1%

R14 100 _04 02_5%
R15 100 _04 02_5%

H_THERMTRIP # <9,21>

CLK_CP U_BCLK <17>
CLK_CPU_BCL K# <17>

T1

Place TP with a
GND 0.1" away

XDP _DBRESET# <22>

1 2
1 2

1 2

H_THERMDA, H_THERMDC routing together,
Trace w idth / Spacing = 10 / 10 mil

+V CCP

H_ THERMDAH_ THERMDA _R
H_ TH ERMDC

H_ PW RGOOD<7,2 1> CLK_CPU_XDP <17>

C1 0.1U_04 02_ 16V4Z

Removed at 5/30.(Follow
Chimay)

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

XDP _BPM#5
XDP _BPM#4

XDP _BPM#3
XDP _BPM#2

XDP _BPM#1
XDP _BPM#0

R9
1K_0402_5%

H_ PW RG OOD_R

12

XDP _HOOK1

12

XDP _TCK

PWM Fan Control circuit

2007/08/28 2006/03/10

Compal Secret Data

2

GND1

4

OBSFN_C0

6

OBSFN_C1

8

GND3

10
12
14

GND5

16
18
20

GND7

22

OBSFN_D0

24

OBSFN_D1

26

GND9

28
30
32

GND11

34
36
38

GND13

40
42
44
46
48
50

GND15

52

TD0

54

TRST#

56

TDI

58

TMS

60

GND17

U1

1

VDD

2

DP

3

DN

4

THERM#

EMC1402 -1-ACZL -TR_MSOP8

Address:100_1100

+5VS

2 1

6

2

D

Q2

S

SI3456BDV-T1-E3_TSOP6

4 5

1

C4

4.7U_0805_10V4Z

2

XDP _TDI
XDP_TMS
XDP _TDO
XDP _BPM#5
XDP _HOOK1
XDP _TRST#
XDP _TCK

CLK_CPU_XDP
CLK_CPU_XDP#

H_RE SET#_R

XDP _TDO
XDP _TRST#
XDP _TDI
XDP_TMS
XDP _PRE

R2 54.9_0402_1%

1 2

R3 54.9_0402_1%

1 2

R4 54.9_0402_1%

1 2

R5 54.9_0402_1%

1 2

R6 54.9_0402_1%@

1 2

R7 54.9_0402_1%

1 2

R8 54.9_0402_1%

1 2

Thi s shall place near CPU

+V CCP+VCCP

R10 1K_0402_1%

1 2

R11 200 _0402_1%

R12
0_0 402_5%

1 2

12

CLK_CPU_XDP# <17>

Place R191 within 200ps (~1") to CPU

SMB _EC_CK2

8

SMCLK

SMDATA

ALERT#

+FAN

Title

Size Do cument Number Re v

Cu st om

Da te: Sheet o f

SMB _EC_DA2

7
6
5

GND

1

C5

0.1U_0402_16V4Z

2

12

D2

@

RLZ5.1B _LL34

Change PCB Footprint from
ACES_85204-02001_2P to
ACES_88231-02001_2P

Compal Electronics, Inc.

Penryn(1/3)-AGTL+/ITP-XDP

Montev ina Blade UMA LA4101P

1

+3VS

1K_0402_5%

+VCCP

H_RE SET#
XDP _DBRESET#XDP _DBRESE T#_R

SMB _EC_CK2 <32>
SMB _EC_DA2 <32>

11/01 update

JP2

1

1

2

2

3

GND

4

GND

ACE S_8 8231-02001

C ONN@

6 46Sa turd ay, January 05, 200 8

0.3

5

www.kythuatvitinh.com

4

3

2

1

H_ D# [0..15]<9>

D D

H_DS TBN#0<9>
H_DS TBP#0<9>
H_ DINV#0<9>
H_ D#[16..31]<9>

C C

* Route the TEST3 and TEST5 signals through
a ground referenced Zo = 55-ohm trace that
ends in a via that is near a GND via and is
accessible through an oscilloscope
connection.

B B

CPU_BSEL CPU_BSEL2 CPU_BSEL1

R21 1K_0402_5%@
R22 1K_0402_5%@

166

H_DSTB N#1<9>
H_DS TBP#1<9>
H_ DINV#1<9>

1 2
1 2

CPU_ BSEL0<17>
CPU_ BSEL1<17>

T2
T3
T4
T5
T6

0 1

200

266

0 0

H_ D#0
H_ D#1
H_ D#2
H_ D#3
H_ D#4
H_ D#5
H_ D#6
H_ D#7
H_ D#8
H_ D#9
H_ D#10
H_ D#11
H_ D#12
H_ D#13
H_ D#14
H_ D#15
H_DS TBN#0
H_DS TBP#0
H_ DINV#0

H_ D#16
H_ D#17
H_ D#18
H_ D#19
H_ D#20
H_ D#21
H_ D#22
H_ D#23
H_ D#24
H_ D#25
H_ D#26
H_ D#27
H_ D#28
H_ D#29
H_ D#30
H_ D#31
H_DS TBN#1
H_DS TBP#1
H_ DINV#1

+V_CPU_GTLREF

TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
CPU_ BSEL0
CPU_ BSEL1
CPU_ BSEL2

10

JC PU1B

E22

D[0]#

F24

D[1]#

E26

D[2]#

G22

D[3]#

F23

D[4]#

G25

D[5]#

E25

D[6]#

E23

D[7]#

K24

D[8]#

G24

D[9]#

J24

D[10]#

J23

D[11]#

H22

D[12]#

F26

D[13]#

K22

D[14]#

H23

D[15]#

J26

DSTBN[0]#

H26

DSTBP[0]#

H25

DINV[0]#

N22

D[16]#

K25

D[17]#

P26

D[18]#

R23

D[19]#

L23

D[20]#

M24

D[21]#

L22

D[22]#

M23

D[23]#

P25

D[24]#

P23

D[25]#

P22

D[26]#

T24

D[27]#

R24

D[28]#

L25

D[29]#

T25

D[30]#

N25

D[31]#

L26

DSTBN[1]#

M26

DSTBP[1]#

N24

DINV[1]#

AD26

GTLREF

C23

TEST1

D25

TEST2

C24

TEST3

AF26

TEST4

AF1

TEST5

A26

TEST6

C3

TEST7

B22

BSEL[0]

B23

BSEL[1]

C21

BSEL[2]

Penryn

CPU_BSEL0

H_ D#32

Y22

MISC

D[32]#
D[33]#

DATA GRP 0

D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#

DATA GRP 2DATA GRP 3

D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#

D[47]#
DSTBN[2]#
DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

DATA GRP 1

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]#
DSTBN[3]#
DSTBP[3]#

DINV[3]#
COMP[0]

COMP[1]
COMP[2]
COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

R26
U26
AA1
Y1

E5
B5
D24
D6
D7
AE6

H_ D#33
H_ D#34
H_ D#35
H_ D#36
H_ D#37
H_ D#38
H_ D#39
H_ D#40
H_ D#41
H_ D#42
H_ D#43
H_ D#44
H_ D#45
H_ D#46
H_ D#47
H_DS TBN#2
H_DS TBP#2
H_ DINV#2

H_ D#48
H_ D#49
H_ D#50
H_ D#51
H_ D#52
H_ D#53
H_ D#54
H_ D#55
H_ D#56
H_ D#57
H_ D#58
H_ D#59
H_ D#60
H_ D#61
H_ D#62
H_ D#63
H_DS TBN#3
H_DS TBP#3
H_ DINV#3

COMP 0
COMP 1
COMP 2
COMP 3

H_DP RSTP#
H_DP SLP #
H_ DP WR#
H_ PW RGOOD
H_ CPUS LP#
H_PSI#

1

0

0

H_ D#[32..47] <9>

H_DS TBN#2 <9>
H_DS TBP#2 <9>
H_ DINV#2 <9>
H_ D#[48..63] <9>

H_DS TBN#3 <9>
H_DS TBP#3 <9>
H_ DINV#3 <9>

H_DP RSTP# <9,2 1,43>

H_DP SLP # <21>
H_ DP WR# <9>
H_ PW RGOOD <6,21>

H_CPUSLP# <9>
H_PSI# <43>CPU_ BSEL2<17>

R24

R23

12

54.9_0402_1%

Resistor placed within 0.5"
of CPU pin.Trace should be
at least 25 mils away from
any other toggling signal.
COMP[0,2] trace width is 18
mils. COMP[1,3] trace width
is 4 mils.

+V_CPU_GTLREF

27.4_0402_1%

12

+V CCP

R25

12

54.9_0402_1%

12

R27
1K_0402_1%

12

R29
2K_0402_1%

27.4_0402_1%

+V CC_ CORE +VCC_CORE

R26

12

AA10
AA12
AA13
AA15
AA17
AA18
AA20

AC10
AB10
AB12
AB14
AB15
AB17
AB18

JC PU 1C

A7

VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

VCCA[01]
VCCA[02]

VCCSENSE

VSSSENSE

A9
A10
A12
A13
A15
A17
A18
A20

B7

B9
B10
B12
B14
B15
B17
B18
B20

C9
C10
C12
C13
C15
C17
C18

D9
D10
D12
D14
D15
D17
D18

E7

E9
E10
E12
E13
E15
E17
E18
E20

F7

F9
F10
F12
F14
F15
F17
F18
F20

AA7
AA9

AB9

Penryn

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

AF20

+VCCPA

G21

+VCCPB

V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

AF7

AE7

.

1 2
1 2

V CCSE NSE

VSSSE NSE

R19

R20

0_0 402_5%
0_0 402_5%

CP U_VID0 <43>
CP U_VID1 <43>
CP U_VID2 <43>
CP U_VID3 <43>
CP U_VID4 <43>
CP U_VID5 <43>
CP U_VID6 <43>

VC CSE NSE <43>

VSSSE NSE <43>

Length match within 25 mils.
The trace width/space/other is 20/7/25.

+V CC _CORE

R28 100 _04 02_1%

1 2

R30 100 _04 02_1%

1 2

+VCCP

10U_0805_6.3V6M

V CCSE NSE

VSSSE NSE

1

+

C6
330 U_D2E_2.5VM_R7

2

1

C7

2

0.01U_0402_16V7K

+1.5VS

1

C8

2

Near pin B26

Close to CPU pin within

A A

Close to CPU pin AD26
within 500mils.

500mils.

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

5

4

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Do cument Number Re v

Cu st om

2

Da te: Sheet o f

Compal Electronics, Inc.

Penryn(2/3)-AGTL+/ITP-XDP

Montev ina Blade UMA LA4101P

1

7 46Sa turd ay, January 05, 200 8

0.3

5

www.kythuatvitinh.com

D D

C C

B B

JC PU 1D

A4

VSS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

AF2

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

VSS[025]

D1

VSS[026]

D4

VSS[027]

D8

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080]
VSS[081]P3VSS[162]

Pe nryn

VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]

VSS[163]

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

.

4

Place these capacitors on
L8 (North side,Secondary
Layer)

Place these capacitors on
L8 (North side,Secondary
Layer)

Place these capacitors on
L8 (North side,Secondary
Layer)

Place these capacitors on
L8 (North side,Secondary
Layer)

Mid Frequence Decoupling

Near CPU CORE regulator

+V CC_ CORE

C41

11/21 Change ESR=7m ohm

+V CCP

1

C45

0.1U_0402_10V6K

2

3

+V CC _CORE

1

2

+V CC _CORE

1

2

+V CC _CORE

1

2

+V CC _CORE

1

2

C9
10U_0805_6.3V6M

C17
10U_0805_6.3V6M

C25
10U_0805_6.3V6M

C33
10U_0805_6.3V6M

1

C10
10U_0805_6.3V6M

2

1

C18
10U_0805_6.3V6M

2

1

C26
10U_0805_6.3V6M

2

1

C34
10U_0805_6.3V6M

2

ESR <= 1.5m ohm
Capacitor > 1980uF

1

1

@

+

+

C42

2

2

330 U_D2_2VY_R7M

Inside CPU center cavity in 2 rows

1

C46

0.1U_0402_10V6K

2

330 U_D2_2VY_R7M

C43

1

2

1

+

C44

2

330 U_D2_2VY_R7M

C47

0.1U_0402_10V6K

1

+

2

330 U_D2_2VY_R7M

1

2

1

C11
10U_0805_6.3V6M

2

1

C19
10U_0805_6.3V6M

2

1

C27
10U_0805_6.3V6M

2

1

C35
10U_0805_6.3V6M

2

C48

0.1U_0402_10V6K

1

C1 2
10U_0805_6 .3V6M

2

1

C2 0
10U_0805_6 .3V6M

2

1

C2 8
10U_0805_6 .3V6M

2

1

C3 6
10U_0805_6 .3V6M

2

5

1

C49

0.1U_0402_10V6K

2

5

1

C13
10U_0805_6 .3V6M

2

5

1

C21
10U_0805_6 .3V6M

2

5

1

C29
10U_0805_6 .3V6M

2

5

1

C37
10U_0805_6 .3V6M

2

1

C50

0.1U_0402_10V6K

2

2

1

C14
10U_0805_6 .3V6M

2

1

C22
10U_0805_6 .3V6M

2

1

C30
10U_0805_6 .3V6M

2

1

C38
10U_0805_6 .3V6M

2

1

C15
10U_0805_6 .3V6M

2

1

C23
10U_0805_6 .3V6M

2

1

C31
10U_0805_6 .3V6M

2

1

C39
10U_0805_6 .3V6M

2

1

2

1

2

1

2

1

2

1

C16
10U_0805_6.3V6M

C24
10U_0805_6.3V6M

C32
10U_0805_6.3V6M

C40
10U_0805_6.3V6M

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

5

4

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Do cument Number Re v

Cu st om

2

Da te: Sheet o f

Compal Electronics, Inc.

Penryn(3/3)-AGTL+/ITP-XDP

Montev ina Blade UMA LA4101P

1

8 46Sa turd ay, January 05, 200 8

0.3

5

www.kythuatvitinh.com

H_ RCOMP

12

R54

AD14

AA13
AA11

AD11
AD10
AD13
AE12

AE14

AE11

U2A

F2

H_D#_0

G8

H_D#_1

F8

H_D#_2

E6

H_D#_3

G2

H_D#_4

H6

H_D#_5

H2

H_D#_6

F6

H_D#_7

D4

H_D#_8

H3

H_D#_9

M9

H_D#_10

M11

H_D#_11

J1

H_D#_12

J2

H_D#_13

N12

H_D#_14

J6

H_D#_15

P2

H_D#_16

L2

H_D#_17

R2

H_D#_18

N9

H_D#_19

L6

H_D#_20

M5

H_D#_21

J3

H_D#_22

N2

H_D#_23

R1

H_D#_24

N5

H_D#_25

N6

H_D#_26

P13

H_D#_27

N8

H_D#_28

L7

H_D#_29

N10

H_D#_30

M3

H_D#_31

Y3

H_D#_32
H_D#_33

Y6

H_D#_34

Y10

H_D#_35

Y12

H_D#_36

Y14

H_D#_37

Y7

H_D#_38

W2

H_D#_39

AA8

H_D#_40

Y9

H_D#_41
H_D#_42

AA9

H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48

AE9

H_D#_49

AA2

H_D#_50

AD8

H_D#_51

AA3

H_D#_52

AD3

H_D#_53

AD7

H_D#_54
H_D#_55

AF3

H_D#_56

AC1

H_D#_57

AE3

H_D#_58

AC3

H_D#_59
H_D#_60

AE8

H_D#_61

AG2

H_D#_62

AD6

H_D#_63

C5

H_SWING

E3

H_RCOMP

C12

H_CPURST#

E11

H_CPUSLP#

A11

H_AVREF

B11

H_DVREF

CANT IGA ES_ FCBGA1329

+VCCP

12

R47

221 _0603_1%

12

R55

100 _0402_1%

+H_SWNG

1

2

0.1U_0402_16V4Z

H_ADSTB#_0
H_ADSTB#_1

H_DEFER#

HPLL_CLK

HPLL_CLK#

H_DPWR#

HOST

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

C59

H_ D#[0..63]<7>

D D

C C

H_RE SET#<6>

H_CPUSLP#<7>

B B

Layout note:

Route H_SCOMP and H_SCOMP# with trace
width, spacing and impedance (55 ohm) same as
FSB data traces

Layout Note:
H_RCOMP / H_VREF / H_SWNG
trace width and spacing is 10/20

+V CCP

12

R46

1K_0402_1%

A A

12

R52

2K_0402_1%

0.1U_0402_16V4Z

+H_VREF

1

C58

2

H_ D#0
H_ D#1
H_ D#2
H_ D#3
H_ D#4
H_ D#5
H_ D#6
H_ D#7
H_ D#8
H_ D#9
H_ D#10
H_ D#11
H_ D#12
H_ D#13
H_ D#14
H_ D#15
H_ D#16
H_ D#17
H_ D#18
H_ D#19
H_ D#20
H_ D#21
H_ D#22
H_ D#23
H_ D#24
H_ D#25
H_ D#26
H_ D#27
H_ D#28
H_ D#29
H_ D#30
H_ D#31
H_ D#32
H_ D#33
H_ D#34
H_ D#35
H_ D#36
H_ D#37
H_ D#38
H_ D#39
H_ D#40
H_ D#41
H_ D#42
H_ D#43
H_ D#44
H_ D#45
H_ D#46
H_ D#47
H_ D#48
H_ D#49
H_ D#50
H_ D#51
H_ D#52
H_ D#53
H_ D#54
H_ D#55
H_ D#56
H_ D#57
H_ D#58
H_ D#59
H_ D#60
H_ D#61
H_ D#62
H_ D#63

+H_SWNG
H_ RCOMP

H_RE SET#
H_ CPUS LP#

+H_VREF

24.9_0402_1%

Near B3 pinwithin 100 mils from NB

5

4

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADS#

H_BNR#

H_BPRI#

H_BREQ#
H_DBSY#

H_DRDY#

H_HIT#

H_HITM#

H_LOCK#
H_TRDY#

H_RS#_0
H_RS#_1
H_RS#_2

H_A#4

C15

H_A#5

F16

H_A#6

H13

H_A#7

C18

H_A#8

M16

H_A#9

J13

H_A#10

P16

H_A#11

R16

H_A#12

N17

H_A#13

M13

H_A#14

E17

H_A#15

P17

H_A#16

F17

H_A#17

G20

H_A#18

B19

H_A#19

J16

H_A#20

E20

H_A#21

H16

H_A#22

J20

H_A#23

L17

H_A#24

A17

H_A#25

B17

H_A#26

L16

H_A#27

C21

H_A#28

J17

H_A#29

H20

H_A#30

B18

H_A#31

K17

H_A#32

B20

H_A#33

F21

H_A#34

K21

H_A#35

L20

H_ ADS #

H12

H_ADSTB#0

B16

H_ADSTB#1

G17

H_ B NR#

A9

H_ BP RI#

F11

H_ BR0#

G12

H_ DE FER#

E9

H_ DBSY#

B10

CL K_MCH_B CLK

AH7

CLK_MCH_ BCLK#

AH6

H_ DP WR#

J11

H_ DRDY#

F9

H_ HIT#

H9

H_ HITM#

E12

H_ LOCK #

H11

H_ TRDY#

C9

H_ DINV#0

J8

H_ DINV#1

L3

H_ DINV#2

Y13

H_ DINV#3

Y1

H_DS TBN#0

L10

H_DS TBN#1

M7

H_DS TBN#2

AA5

H_DS TBN#3

AE6

H_DS TBP#0

L9

H_DS TBP#1

M8

H_DS TBP#2

AA6

H_DS TBP#3

AE5

H_ REQ#0

B15

H_ REQ#1

K13

H_ REQ#2

F13

H_ REQ#3

B13

H_ REQ#4

B14

H_ RS#0

B6

H_ RS#1

F12

H_ RS#2

C8

Layout Note: V_DDR_MCH_REF
trace width and spacing is 20/20.

H_A#3

A14

H_ A#[3..35] <6>

H_ADS# <6>
H_ADSTB#0 <6>
H_ADSTB#1 <6>
H_ BNR# <6>
H_ BPRI# <6>
H_BR0# <6>
H_ DEFER# <6>
H_ DBSY# <6>
CLK_MCH_BCLK <17>
CLK_MCH_BCLK# <17>
H_ DP WR# <7>
H_ DRDY# <6>
H_ HIT# <6>
H_HITM# <6>
H_ LOCK # <6>
H_ TR DY# <6>

H_ DINV#0 <7>
H_ DINV#1 <7>
H_ DINV#2 <7>
H_ DINV#3 <7>

H_DS TBN#0 <7>
H_DS TBN#1 <7>
H_DS TBN#2 <7>
H_DS TBN#3 <7>

H_DS TBP#0 <7>
H_DS TBP#1 <7>
H_DS TBP#2 <7>
H_DS TBP#3 <7>

H_ REQ#0 <6>
H_ REQ#1 <6>
H_ REQ#2 <6>
H_ REQ#3 <6>
H_ REQ#4 <6>

H_RS#0 <6>
H_RS#1 <6>
H_RS#2 <6>

PLT_RST#<20,25,26,27>

H_THERMTRIP#<6,21>

+V_DDR_MCH_REF generated by DC-DC

V_ DD R_MCH_REF<15,16>

4

2.2U_0603_6.3V4Z

S MRCOMP_VOH

80% of 1.8V VCC_SM

20% of 1.8V VCC_SM

SMRCOMP_ VOL

2.2U_0603_6.3V4Z

DPRSLP VR<22,43>

V_ DD R_MCH_REF

1

C57

2

0.1U_0402_16V4Z

3

T7
T8
T9

+1.8V

1

1

C52

2

1

C5 4

2

12

R45
1K_0402_1%

12

R48
1K_0402_1%

12

0.01U_0402_25V7K

12

12

0.01U_0402_25V7K

PM_EXTTS#0

PM_EXTTS#1

CLKREQ#_7

R41
R42

R31
1K_0402_1%

R32

3.01K_0402_1%

R33
1K_0402_1%

R38 10K _04 02_5%

1 2

R39 10K _04 02_5%

1 2

R40 10K _04 02_5%

1 2

MCH_CLKS EL0<17>
MCH_CLKS EL1<17>
MCH_CLKS EL2<17>

CF G5<11>
CF G6<11>
CF G7<11>
CF G8<11>

CF G9<11>
CF G10<11>
CF G11<11>
CF G12<11>
CF G13<11>
CF G14<11>
CF G15<11>
CF G16<11>
CF G17<11>
CF G18<11>
CF G19<11>
CF G20<11>

PM_ BMBUSY#<22>

H_DP RSTP#<7,21 ,43>
PM_EXTTS#0<15>
PM_EXTTS#1<16>
PM_ PWROK<22,32>

1 2

100 _04 02_5%

1 2

0_0 402_5%

C51

2

1

C5 3

2

PLT_RST#

+1.8V

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20

T21
T22
T23

T24

T25
T26
T27
T28

MCH_CLKS EL0
MCH_CLKS EL1
MCH_CLKS EL2

CF G5
CF G6
CF G7
CF G8
CF G9
CF G10
CF G11
CF G12
CF G13
CF G14
CF G15
CF G16
CF G17
CF G18
CF G19
CF G20

PM_ BMBUSY#
H_DP RSTP#
PM_EXTTS#0
PM_EXTTS#1
PM_ PWROK

THERMTRIP#
DP RSLPV R

@

1

C55

2

0.1U_0402_16V4Z

2007/08/28 2006/03/10

U2B

M36

RESERVED

N36

RESERVED

R33

RESERVED

T33

RESERVED

AH9

RESERVED

AH10

RESERVED

AH12

RESERVED

AH13

RESERVED

K12

RESERVED

AL34

RESERVED

AK34

RESERVED

AN35

RESERVED

AM35

RESERVED

T24

RESERVED

B31

RESERVED

B2

RESERVED

M1

RESERVED

AY21

RESERVED

BG23

RESERVED

BF23

RESERVED

BH18

RESERVED

BF18

RESERVED

+3VS

T25

CFG_0

R25

CFG_1

P25

CFG_2

P20

CFG_3

P24

CFG_4

C25

CFG_5

N24

CFG_6

M24

CFG_7

E21

CFG_8

C23

CFG_9

C24

CFG_10

N21

CFG_11

P21

CFG_12

T21

CFG_13

R20

CFG_14

M20

CFG_15

L21

CFG_16

H21

CFG_17

P29

CFG_18

R28

CFG_19

T28

CFG_20

R29

PM_SYNC#

B7

PM_DPRSTP#

N33

PM_EXT_TS#_0

P32

PM_EXT_TS#_1

AT40

PWROK

AT11

RSTIN#

T20

THERMTRIP#

R32

DPRSLPVR

BG48

NC

BF48

NC

BD48

NC

BC48

NC

BH47

NC

BG47

NC

BE47

NC

BH46

NC

BF46

NC

BG45

NC

BH44

NC

BH43

NC

BH6

NC

BH5

NC

BG4

NC

BH3

NC

BF3

NC

BH2

NC

BG2

NC

BE2

NC

BG1

NC

BF1

NC

BD1

NC

BC1

NC

F1

NC

A47

NC

CANT IGA ES_ FCBGA1329

Compal Secret Data

Deciphered Date

2

RSVD

DDR CLK/ CONTROL/COMPENSATIONCLK

DPLL_REF_SSCLK#

CFG

DMI

PM

GRAPHICS VIDMEHDA

NC

MISC

2

SA_CK_0
SA_CK_1
SB_CK_0
SB_CK_1

SA_CK#_0
SA_CK#_1
SB_CK#_0
SB_CK#_1

SA_CKE_0
SA_CKE_1
SB_CKE_0
SB_CKE_1

SA_CS#_0
SA_CS#_1
SB_CS#_0
SB_CS#_1

SA_ODT_0
SA_ODT_1
SB_ODT_0
SB_ODT_1

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH
SM_RCOMP_VOL

SM_VREF

SM_PWROK

SM_REXT

SM_DRAMRST#

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

PEG_CLK

PEG_CLK#

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4

GFX_VR_EN

CL_CLK

CL_DATA

CL_PWROK

CL_RST#

CL_VREF

DDPC_CTRLCLK

DDPC_CTRLDATA

SDVO_CTRLCLK

SDVO_CTRLDATA

CLKREQ#

ICH_SYNC#

TSATN#

HDA_BCLK

HDA_RST#

HDA_SDI

HDA_SDO

HDA_SYNC

1

M_ CLK_DDR0

AP24

M_ CLK_DDR1

AT21

M_ CLK_DDR2

AV24

M_ CLK_DDR3

AU20

M_ CLK_DDR#0

AR24

M_ CLK_DDR#1

AR21

M_ CLK_DDR#2

AU24

M_ CLK_DDR#3

AV20

DDR_CKE0_DIMMA

BC28

DDR_CKE1_DIMMA

AY28

DDR_CKE2_DIMMB

AY36

DDR_CKE3_DIMMB

BB36

DDR_CS0_ DIMMA#

BA17

DDR_CS1_ DIMMA#

AY16

DDR_CS2_ DIMMB#

AV16

DDR_CS3_ DIMMB#

AR13

M_ODT0

BD17

M_ODT1

AY17

M_ODT2

BF15

M_ODT3

AY13

S MRCOMP

BG22

SMRCOMP#

BH21

S MRCOMP_VOH

BF28

SMRCOMP_ VOL

BH28

V_ DD R_MCH_REF

AV42

SM_ PWROK

AR36

SM_REXT

BF17

TP_SM_ DRAMRST#

BC36

CL K_ MCH_DRE FCLK

B38

CL K _MCH_DREFCLK #

A38

MCH_ SS CDREFCLK

E41

MCH_ SS CDREFCLK #

F41

CLK_MCH_ 3GPLL

F43

CLK_MCH_ 3GPLL#

E43

DMI_TXN0

AE41

DMI_TXN1

AE37

DMI_TXN2

AE47

DMI_TXN3

AH39

DMI_TXP0

AE40

DMI_TXP1

AE38

DMI_TXP2

AE48

DMI_TXP3

AH40

DMI_RXN0

AE35

DMI_RXN1

AE43

DMI_RXN2

AE46

DMI_RXN3

AH42

DMI_RXP0

AD35

DMI_RXP1

AE44

DMI_RXP2

AF46

DMI_RXP3

AH43

B33
B32
G33
F33
E33

C34

CL _CLK0

AH37

CL_DATA0

AH36

M_PWROK

AN36

CL_RST#

AJ35

+CL_VREF

AH34

06 21 a dd CLK and DAT for DVI

N28
M28

HDMICLK_NB

G36

HD MIDA T_NB

E36

CLKREQ#_7

K36

MCH_ICH_SYNC#

H36

TSATN#

B12

B28
B30

HDA_ SDIN2_NB

B29
C29
A28

R737 56_ 0402_5%

1 2

M_ CLK _DDR0 <15>
M_ CLK _DDR1 <15>
M_ CLK _DDR2 <16>
M_ CLK _DDR3 <16>

M_ CLK _DDR# 0 <15>
M_ CLK _DDR# 1 <15>
M_ CLK _DDR# 2 <16>
M_ CLK _DDR# 3 <16>

DDR_CKE0_DIMMA <15>
DDR_CKE1_DIMMA <15>
DDR_CKE2_DIMMB <16>
DDR_CKE3_DIMMB <16>

DDR_CS0_DIMMA# <15>
DDR_CS1_DIMMA# <15>
DDR_CS2_DIMMB# <16>
DDR_CS3_DIMMB# <16>

M_ODT0 <15>
M_ODT1 <15>
M_ODT2 <16>
M_ODT3 <16>

R34 80.6_0402_1%

1 2

R35 80.6_0402_1%

1 2

Follow Design Guide
For Cantiga: 80.6ohm

R36 0_0 402_5%

1 2

R37 499 _04 02_1%

1 2

T29 P AD

CL K_ MCH_DREFCLK <17>
CL K_ MCH_DREFCLK# <17>

MCH_SSCDREFCLK <17>

MCH_SSCDREFCLK# <17>

CLK_MCH_ 3GPLL <17>
CLK_MCH_ 3GPLL# <17>

DMI_TXN0 <22>
DMI_TXN1 <22>
DMI_TXN2 <22>
DMI_TXN3 <22>

DMI_TXP0 <22>
DMI_TXP1 <22>
DMI_TXP2 <22>
DMI_TXP3 <22>

DMI_RXN0 <22>
DMI_RXN1 <22>
DMI_RXN2 <22>
DMI_RXN3 <22>

DMI_RXP0 <22>
DMI_RXP1 <22>
DMI_RXP2 <22>
DMI_RXP3 <22>

T30
T31
T32
T33
T34

T35

CL_CLK0 <22>
CL_DATA0 <22>
M_PWROK <22,32>
CL_RST# <22>

0.1U_0402_16V4Z

T36
T37

HDMICL K_NB <35>
HDMIDAT_NB <35>

CLKREQ#_7 <17>
MCH_ICH_SYNC# <22>

+VCCP

TSATN# <32>

HDA _BITCLK _NB <21>
HDA _RST#_NB <21>

HDA_SDOUT _NB <21>
HDA_ SYNC_NB <21>

1 2

33_ 0402_5%

C5 6

R210

1

2

+V CCP

*R44*Follow Intel
feedback

08 30 A dd p ull-up and pull- down res isto r.

Title

Size Do cument Number Re v

Cu st om

Da te: Sheet o f

Compal Electronics, Inc.

Cantiga(1/6)-AGTL/DMI/DDR

Montev ina Blade UMA LA4101P

9 46Sa turd ay, January 05, 200 8

1

+1.8V

12

R43
1K_0402_1%

12

R44
499 _0402_1%

HDA_ SDIN2 <21>

0.3

5

www.kythuatvitinh.com

D D

DDR_A_D[0..63]<15>

C C

B B

DDR_ A_D0
DDR_ A_D1
DDR_ A_D2
DDR_ A_D3
DDR_ A_D4
DDR_ A_D5
DDR_ A_D6
DDR_ A_D7
DDR_ A_D8
DDR_ A_D9
DDR_A_D1 0
DDR_A_D1 1
DDR_A_D1 2
DDR_A_D1 3
DDR_A_D1 4
DDR_A_D1 5
DDR_A_D1 6
DDR_A_D1 7
DDR_A_D1 8
DDR_A_D1 9
DDR_A_D2 0
DDR_A_D2 1
DDR_A_D2 2
DDR_A_D2 3
DDR_A_D2 4
DDR_A_D2 5
DDR_A_D2 6
DDR_A_D2 7
DDR_A_D2 8
DDR_A_D2 9
DDR_A_D3 0
DDR_A_D3 1
DDR_A_D3 2
DDR_A_D3 3
DDR_A_D3 4
DDR_A_D3 5
DDR_A_D3 6
DDR_A_D3 7
DDR_A_D3 8
DDR_A_D3 9
DDR_A_D4 0
DDR_A_D4 1
DDR_A_D4 2
DDR_A_D4 3
DDR_A_D4 4
DDR_A_D4 5
DDR_A_D4 6
DDR_A_D4 7
DDR_A_D4 8
DDR_A_D4 9
DDR_A_D5 0
DDR_A_D5 1
DDR_A_D5 2
DDR_A_D5 3
DDR_A_D5 4
DDR_A_D5 5
DDR_A_D5 6
DDR_A_D5 7
DDR_A_D5 8
DDR_A_D5 9
DDR_A_D6 0
DDR_A_D6 1
DDR_A_D6 2
DDR_A_D6 3

U 2D

AJ38

SA_DQ_0

AJ41

SA_DQ_1

AN38

SA_DQ_2

AM38

SA_DQ_3

AJ36

SA_DQ_4

AJ40

SA_DQ_5

AM44

SA_DQ_6

AM42

SA_DQ_7

AN43

SA_DQ_8

AN44

SA_DQ_9

AU40

SA_DQ_10

AT38

SA_DQ_11

AN41

SA_DQ_12

AN39

SA_DQ_13

AU44

SA_DQ_14

AU42

SA_DQ_15

AV39

SA_DQ_16

AY44

SA_DQ_17

BA40

SA_DQ_18

BD43

SA_DQ_19

AV41

SA_DQ_20

AY43

SA_DQ_21

BB41

SA_DQ_22

BC40

SA_DQ_23

AY37

SA_DQ_24

BD38

SA_DQ_25

AV37

SA_DQ_26

AT36

SA_DQ_27

AY38

SA_DQ_28

BB38

SA_DQ_29

AV36

SA_DQ_30

AW36

SA_DQ_31

BD13

SA_DQ_32

AU11

SA_DQ_33

BC11

SA_DQ_34

BA12

SA_DQ_35

AU13

SA_DQ_36

AV13

SA_DQ_37

BD12

SA_DQ_38

BC12

SA_DQ_39

BB9

SA_DQ_40

BA9

SA_DQ_41

AU10

SA_DQ_42

AV9

SA_DQ_43

BA11

SA_DQ_44

BD9

SA_DQ_45

AY8

SA_DQ_46

BA6

SA_DQ_47

AV5

SA_DQ_48

AV7

SA_DQ_49

AT9

SA_DQ_50

AN8

SA_DQ_51

AU5

SA_DQ_52

AU6

SA_DQ_53

AT5

SA_DQ_54

AN10

SA_DQ_55

AM11

SA_DQ_56

AM5

SA_DQ_57

AJ9

SA_DQ_58

AJ8

SA_DQ_59

AN12

SA_DQ_60

AM13

SA_DQ_61

AJ11

SA_DQ_62

AJ12

SA_DQ_63

CANT IGA ES_ FCBGA1329

DDR SYSTEM MEMORY A

SA_BS_0
SA_BS_1
SA_BS_2

SA_RAS#
SA_CAS#

SA_WE#

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6

SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14

4

DDR_A_ BS0

BD21
BG18
AT25

BB20
BD20
AY20

AM37
AT41
AY41
AU39
BB12
AY6
AT7
AJ5

AJ44
AT44
BA43
BC37
AW12
BC8
AU8
AM7
AJ43
AT43
BA44
BD37
AY12
BD8
AU9
AM8

BA21
BC24
BG24
BH24
BG25
BA24
BD24
BG27
BF25
AW24
BC21
BG26
BH26
BH17
AY25

DDR_A_ BS1
DDR_A_ BS2

DD R_A _RAS#
DD R_A _CAS#
DDR_A_WE#

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2

DDR_A_DQS#3

DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_ MA0
DDR_A_ MA1
DDR_A_ MA2
DDR_A_ MA3
DDR_A_ MA4
DDR_A_ MA5
DDR_A_ MA6
DDR_A_ MA7
DDR_A_ MA8
DDR_A_ MA9
DDR_A_MA 10
DDR_A_MA 11
DDR_A_MA 12
DDR_A_MA 13
DDR_A_MA 14

DDR_A_BS0 <15>
DDR_A_BS1 <15>
DDR_A_BS2 <15>

DDR_A_ RAS # <15>
DDR_A_ CAS # <15>
DDR_A _WE # <15>

DDR_A_DM[0..7] <15>

DDR_A_DQS[0 ..7] <15>

DDR_A_DQS#[0..7 ] <15>

DDR_A _MA[0..1 4] <15>

3

DDR_B_D[0..63]<16>

DDR_ B_D0
DDR_ B_D1
DDR_ B_D2
DDR_ B_D3
DDR_ B_D4
DDR_ B_D5
DDR_ B_D6
DDR_ B_D7
DDR_ B_D8
DDR_ B_D9
DDR_B_D1 0
DDR_B_D1 1
DDR_B_D1 2
DDR_B_D1 3
DDR_B_D1 4
DDR_B_D1 5
DDR_B_D1 6
DDR_B_D1 7
DDR_B_D1 8
DDR_B_D1 9
DDR_B_D2 0
DDR_B_D2 1
DDR_B_D2 2
DDR_B_D2 3
DDR_B_D2 4
DDR_B_D2 5
DDR_B_D2 6
DDR_B_D2 7
DDR_B_D2 8
DDR_B_D2 9
DDR_B_D3 0
DDR_B_D3 1
DDR_B_D3 2
DDR_B_D3 3
DDR_B_D3 4
DDR_B_D3 5
DDR_B_D3 6
DDR_B_D3 7
DDR_B_D3 8
DDR_B_D3 9
DDR_B_D4 0
DDR_B_D4 1
DDR_B_D4 2
DDR_B_D4 3
DDR_B_D4 4
DDR_B_D4 5
DDR_B_D4 6
DDR_B_D4 7
DDR_B_D4 8
DDR_B_D4 9
DDR_B_D5 0
DDR_B_D5 1
DDR_B_D5 2
DDR_B_D5 3
DDR_B_D5 4
DDR_B_D5 5
DDR_B_D5 6
DDR_B_D5 7
DDR_B_D5 8
DDR_B_D5 9
DDR_B_D6 0
DDR_B_D6 1
DDR_B_D6 2
DDR_B_D6 3

U2E

AK47
AH46
AP47
AP46

AJ46

AJ48
AM48
AP48
AU47
AU46
BA48
AY48

AT47
AR47
BA47
BC47
BC46
BC44
BG43

BF43
BE45
BC41

BF40

BF41
BG38

BF38
BH35
BG35
BH40
BG39
BG34
BH34
BH14
BG12
BH11

BG8

BH12

BF11

BF8
BG7
BC5
BC6
AY3
AY1
BF6
BF5
BA1
BD3
AV2
AU3
AR3
AN2
AY2
AV1
AP3
AR1

AL1
AL2

AJ1
AH1
AM2
AM3
AH3

AJ3

CANT IGA ES_ FCBGA1329

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

2

DDR_B_BS0

BC16

SB_BS_0
SB_BS_1
SB_BS_2

SB_RAS#
SB_CAS#

SB_WE#

SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6

SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14

DDR SYSTEM MEMORY B

BB17
BB33

AU17
BG16
BF14

AM47
AY47
BD40
BF35
BG11
BA3
AP1
AK2

AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6
AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5

AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33

DDR_B_ BS1
DDR_B_ BS2

DD R_B _RAS#
DD R_B _CAS#
DDR_B_WE#

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_ MA0
DDR_B_ MA1
DDR_B_ MA2
DDR_B_ MA3
DDR_B_ MA4
DDR_B_ MA5
DDR_B_ MA6
DDR_B_ MA7
DDR_B_ MA8
DDR_B_ MA9
DDR_B_MA 10
DDR_B_MA 11
DDR_B_MA 12
DDR_B_MA 13
DDR_B_MA 14

1

DDR_B_BS0 <16>
DDR_B_BS1 <16>
DDR_B_BS2 <16>

DDR_B_ RAS # <16>
DDR_B_ CAS # <16>
DDR_B_ WE# <16>

DDR_B_DM[0..7] <16>

DDR_B_DQS[0 ..7] <16>

DDR_B_DQS#[0..7 ] <16>

DDR_B _MA[0..1 4] <16>

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

5

4

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Do cument Number Re v

Cu st om

2

Da te: Sheet o f

Compal Electronics, Inc.

Cantiga(2/6)-DDR2 A/B CH

Montev ina Blade UMA LA4101P

1

10 46Saturday, January 05, 2008

0.3

5

www.kythuatvitinh.com

R148

1 2

100 K_0 402_5%

D D

C C

11/10 Disable TV out

B B

ENB KL

ENB KL<32>

+3VS

DDC2_CLK<19>
DDC2_DATA<19>

Follow Intel DG &
Checklist

EN AVDD<19>

T48
T49
T50

Follow Intel DG &
Checklist

+3VS

M_B LUE<18>
M_GREEN<18>
M_ RED<18>

Follow Intel DG &
Checklist

3V DD CCL<18>
3V DD CDA<18>

CRT_ HS YNC<18>
CRT_ VSYNC<18>

ENB KL

R58 10K _0402_5%

1 2

R59 10K _0402_5%

1 2

DDC2 _CLK
DD C2_DATA

EN A VDD

R60 2.37K_0402_1%

1 2

LVDS_A CLK­LVDS_A CLK+
LVDS_B CLK-

T80

LVDS_B CLK+

T81

LVDS_A0­LVDS_A1­LVDS_A2­LVDS_A3-

T38

LVDS_A0+
LVDS_A1+
LVDS_A2+
LVDS_A3+

T39

LVDS_B0-

T72

LVDS_B1-

T73

LVDS_B2-

T74

LVDS_B3-

T40

LVDS_B0+

T75

LVDS_B1+

T77

LVDS_B2+

T79

LVDS_B3+

T41

TV_COMPS
TV_LUMA
TV_CRMA

12

75_ 0402_1%

R62

R61

R64 2.2K_0402_5%@

1 2

R406 0_0 402_5%

1 2

M_B LUE
M_GREEN
M_RED

3V DD CCL
3V DD CDA
CRT_ HS YNC

R65

R68

30.1_0402_1%

R69

30.1_0402_1%

150 _04 02_1%

12

1 2
1 2

R66

12

12

75_ 0402_1%

R63

150 _04 02_1%

12

12

R67

H SYN C
VS Y NCCRT_ VS YNC

R70

1.02K_0402_1%

4

U 2C

L32

L_BKLT_CTRL

G32

L_BKLT_EN

M32

L_CTRL_CLK

M33

L_CTRL_DATA

K33

L_DDC_CLK

J33

L_DDC_DATA

M29

L_VDD_EN

C44

LVDS_IBG

B43

LVDS_VBG

E37

LVDS_VREFH

E38

LVDS_VREFL

C41

LVDSA_CLK#

C40

LVDSA_CLK

B37

LVDSB_CLK#

A37

LVDSB_CLK

H47

LVDSA_DATA#_0

E46

LVDSA_DATA#_1

G40

LVDSA_DATA#_2

A40

LVDSA_DATA#_3

H48

LVDSA_DATA_0

D45

LVDSA_DATA_1

F40

LVDSA_DATA_2

B40

LVDSA_DATA_3

A41

LVDSB_DATA#_0

H38

LVDSB_DATA#_1

G37

LVDSB_DATA#_2

J37

LVDSB_DATA#_3

B42

LVDSB_DATA_0

G38

LVDSB_DATA_1

F37

LVDSB_DATA_2

K37

LVDSB_DATA_3

F25

TVA_DAC

H25

75_ 0402_1%

150 _04 02_1%

12

TVB_DAC

K25

TVC_DAC

H24

TV_RTN

C31

TV_DCONSEL_0

E32

TV_DCONSEL_1

E28

CRT_BLUE

G28

CRT_GREEN

J28

CRT_RED

G29

CRT_IRTN

H32

CRT_DDC_CLK

J32

CRT_DDC_DATA

J29

CRT_HSYNC

E29

CRT_TVO_IREF

L29

CRT_VSYNC

CANT IGA ES_ FCBGA1329

LVDS

TV VGA

PCI-EXPRESS GRAPHICS

PEG_COMPI

PEG_COMPO

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8

PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8

PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9

PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8

PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

T37
T36

H44
J46
L44
L40
N41
P48
N44
T43
U43
Y43
Y48
Y36
AA43
AD37
AC47
AD39

H43
J44
L43
L41
N40
P47
N43
T42
U42
Y42
W47
Y37
AA42
AD36
AC48
AD40

J41
M46
M47
M40
M42
R48
N38
T40
U37
U40
Y40
AA46
AA37
AA40
AD43
AC46

J42
L46
M48
M39
M43
R47
N37
T39
U36
U39
Y39
Y46
AA36
AA39
AD42
AD46

3

R57

1 2

49.9_0402_1%

PEGCOMP trace width
and spacing is 20/25 mils.

TMDS_B_HPD#

TMDS_BDATA2#
TMDS_BDATA1#
TMDS_BDATA0#
TMDS_BCLK#

TMDS_BDATA2
TMDS_BDATA1
TMDS_BDATA0
TMDS_BCLK

C274 0.1U_0402_10V7K
C275 0.1U_0402_10V7K
C276 0.1U_0402_10V7K
C277 0.1U_0402_10V7K

C278 0.1U_0402_10V7K
C279 0.1U_0402_10V7K
C280 0.1U_0402_10V7K
C281 0.1U_0402_10V7K

1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2

+VCC_PE G

TMDS_B_HPD# <35>

2

TMDS_B_DATA2# <35>
TMDS_B_DATA1# <35>
TMDS_B_DATA0# <35>
TMDS_B_CLK# <35>

TMDS_B_DATA2 <35>
TMDS_B_DATA1 <35>
TMDS_B_DATA0 <35>
TMDS_B_CLK <35>

Strap Pin Table

CFG[2:0] FSB Freq
select

CFG[4:3]
CFG5 (DMI select)

CFG6

(Intel Management

CFG7

Engine Crypto strap)

CFG8

CFG9 (PCIE Graphics

Lane Reversal)

CFG10

(PCIE
Lookback
enable)

CFG11

CFG[13:12] (XOR/ALLZ)

CFG[15:14]

CFG16 (FSB Dynamic ODT)

CFG[18:17]

CFG19 (DMI Lane Reversal)

(PCIE/SDVO

CFG20

concurrent)

+3VS

R71

4.02K_0402_1%

CF G5<9>

CF G5

@

R74

2.21K_0402_1%

1

000 = FSB 1066MHz
010 = FSB 800MHz
011 = FSB 667MHz
Others = Reserved

Reserved
0 = DMI x 2

1 = DMI x 4
0 = The iTPM Host Interface is enable

*

1 = The iTPM Host Interface is disable
0 =(TLS)chiper suite with no confidentiality
1 =(TLS)chiper suite with confidentiality

Reserved

0 = Reverse Lane,15->0, 14->1
1 = Normal Operation,Lane Number in

order
0 = Enable

1 = Disable
Reserved
00 = Reserved

01 = XOR Mode Enabled
10 = All Z Mode Enabled

*

Reserved

0 = Disabled
1 = Enabled

*

Reserved

0 = Normal Operation

(Lane number in Order)

1 = Reverse Lane

0 = Only PCIE or SDVO is operational.
1 = PCIE/SDVO are operating simu.

12

12

CF G16<9>

CF G19<9>

CF G20<9>

R72

R73

@

R75

@

(Default)11 = Normal Operation

*

*

*

*

1 2

4.02K_0402_1%

1 2

4.02K_0402_1%

1 2

4.02K_0402_1%

*

*

+3VS

R76

@

@

@

@

@

R77

R78

R80

R82

R85

R87

1 2

2.21K_0402_1%

1 2

2.21K_0402_1%

1 2

2.21K_0402_1%

1 2

2.21K_0402_1%

1 2

2.21K_0402_1%

1 2

2.21K_0402_1%

1 2

2.21K_0402_1%

11 46Saturday, January 05, 2008

0.3

Solve 3G WWAN issue

LVDS_A CLK+<19>

LVDS_A CLK-<19>
LVDS_A0+<19>

LVDS_A0-<19>
LVDS_A1+<19>

LVDS_A1-<19>
LVDS_A2+<19>

A A

LVDS_A2-<19>

LVDS_A CLK+

LVDS_A CLK­LVDS_A0+

LVDS_A0­LVDS_A1+

LVDS_A1­LVDS_A2+

LVDS_A2-

5

1

@

C60

0.1U_0402_10V6K

2
1

@

C61

0.1U_0402_10V6K

2
1

@

C62

0.1U_0402_10V6K

2
1

@

C63

0.1U_0402_10V6K

2

R79

@

CF G6<9>

CF G7<9>

CF G8<9>

CF G9<9>

CF G10<9>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

2

1 2

2.21K_0402_1%

R81

1 2

2.21K_0402_1%

R83

@

1 2

2.21K_0402_1%

R84

@

1 2

2.21K_0402_1%

R86

@

1 2

2.21K_0402_1%

Title

Cantiga(3/6)-VGA/LVDS/TV

Size Do cument Number Re v

Cu st om

Montev ina Blade UMA LA4101P

Da te: Sheet o f

CF G11<9>

CF G12<9>

CF G13<9>

CF G14<9>

CF G15<9>

CF G17<9>

CF G18<9>

Compal Electronics, Inc.

1

5

www.kythuatvitinh.com

+3VS_DAC_BG

0.022U_0402_16V7K

12

@

C68

0_0603_5%

R89

D D

C C

B B

12

@

R92

+3VS_DAC_CRT

C75

0_0603_5%

+1.5VS

+VCCP

C69

1

2

0.022U_0402_16V7K
C76

1

2

+3VS

220 U_D2_4VM

R103

1 2

0_0603_5%

1U_0603_10V4Z

0.1U_0402_16V4Z
C70

1

1

2

2

R91

1 2

BLM18PG181SN1D_0603

0.1U_0402_16V4Z

1

2

R96

@

1 2

0_0603_5%

R97

1 2

0_0603_5%

1

C94

+

2

C102

+3VS

R88

1 2

BLM18PG181SN1D_0603

10U_0805_10V4Z

+3VS

1

C89

0.1 U_0402_16V4Z

2

R100

1 2

0_0805_5%

C95

1

2

+1.05VS_A_SM_CK

C103

1

1

2

2

Check Again!!!

+1.8V_TXLVDS

+1.5VS_PEG_BG

+1.05VS_A_SM

10U_0805_10V4Z

C96

4.7 U_0805_10V4Z

1U_0603_10V4Z

10U_0805_10V4Z

C104

1

2

**RED Mark: Means UMA & dis@ Power select**
~It check by INTEL Graphics Disable
Guidelines~

+3VS_DAC_CRT

+3VS_DAC_BG

+1.05VS_DPLLA
+1.05VS_DPLLB

+1.05VS_HPLL
+1.05VS_MPLL

1

C88

1000P_0402_50V7K

2

+1.05VS_PEGPLL

1

1

C97

2

2

1U_0603_10V4Z

0.1U_0402_16V4Z

C105

1

2

+3VS_TVDAC

+1.5VS

+1.5VS_TVDAC
+1.5VS_Q DAC

+1.05VS_HPLL

+1.05VS_PEGPLL

+1.8V_LVDS

4

U2 H

73mA

B27

VCCA_CRT_DAC

A26

VCCA_CRT_DAC

2.68mA

A25

VCCA_DAC_BG

B25

VSSA_DAC_BG

F47

VCCA_DPLLA

L48

VCCA_DPLLB

AD1

VCCA_HPLL

AE1

VCCA_MPLL

13.2mA

J48

VCCA_LVDS

J47

VSSA_LVDS

414uA

AD48

VCCA_PEG_BG

50mA

AA48

VCCA_PEG_PLL

AR20

VCCA_SM

AP20

VCCA_SM

AN20

VCCA_SM

AR17

VCCA_SM

AP17

VCCA_SM

AN17

VCCA_SM

AT16

VCCA_SM

AR16

VCCA_SM

AP16

VCCA_SM

AP28

VCCA_SM_CK

AN28

VCCA_SM_CK

AP25

VCCA_SM_CK

AN25

VCCA_SM_CK

AN24

VCCA_SM_CK

AM28

VCCA_SM_CK_NCTF

AM26

VCCA_SM_CK_NCTF

AM25

VCCA_SM_CK_NCTF

AL25

VCCA_SM_CK_NCTF

AM24

VCCA_SM_CK_NCTF

AL24

VCCA_SM_CK_NCTF

AM23

VCCA_SM_CK_NCTF

AL23

VCCA_SM_CK_NCTF

B24

VCCA_TV_DAC

A24

VCCA_TV_DAC

A32

VCC_HDA

M25

VCCD_TVDAC

L28

VCCD_QDAC

AF1

VCCD_HPLL

AA47

VCCD_PEG_PLL

M38

VCCD_LVDS

L37

VCCD_LVDS

60.31mA

CANT IGA ES_FCBGA1329

CRTPLLA PEGA SMTV

64.8mA

64.8mA
24mA

139.2mA

A LVDSHDA

720mA

26mA
26mA

TVA 2 4.15mA
TVB 3 9.48mA
TVX 2 4.15mA

50mA

58.67mA

48.363mA

157.2mA
50mA

LVDS

852mA

POWER

A CK

105.3mA

1732mA

D TV/CRT

DMI

456mA

VTT

321.35mA

VCC_AXF
VCC_AXF
VCC_AXF

AXF

124mA

VCC_SM_CK
VCC_SM_CK
VCC_SM_CK
VCC_SM_CK

SM CK

118.8mA

VCC_TX_LVDS

VCC_HV
VCC_HV
VCC_HV

HV

VCC_PEG
VCC_PEG
VCC_PEG
VCC_PEG

PEG

VCC_PEG

VCC_DMI
VCC_DMI
VCC_DMI
VCC_DMI

VTTLF

VTTLF
VTTLF
VTTLF

3

+VCCP

U13

VTT

T13

VTT

U12

VTT

T12

VTT

U11

VTT

T11

VTT

U10

VTT

T10

VTT

U9

VTT

T9

VTT

U8

VTT

T8

VTT

U7

VTT

T7

VTT

U6

VTT

T6

VTT

U5

VTT

T5

VTT

V3

VTT

U3

VTT

V2

VTT

U2

VTT

T2

VTT

V1

VTT

U1

VTT

B22
B21
A21

BF21
BH20
BG20
BF20

K47
C35

B35
A35

V48
U48
V47
U47
U46

AH48
AF48
AH47
AG47

A8
L1
AB2

C110

0.47U_0603_10V7K

+V1.05VS_AXF

+1.8V_SM_CK

+1.8V_TXLVDS

+VCC_PEG

+1. 05VS_DMI

0.47U_0603_10V7K

C111

1

2

1

C71

+

2

1

C80

2

C112

1

2

4.7U_0805_10V4Z

220U_6.3V_M

C72

1

2

4.7U_0805_10V4Z

0.47U_0603_10V7K

C81

+3VS_HV

C107

0.47U_0603_10V7K

1

2

2.2U_0805_16V4Z

1

1

C82

2

2

0.1U_0402_16V4Z

1

2

+1.05VS_DPLLA

@

220U_D2_4VM

1

C77

+

2

0.1U_0402_16V4Z
C86

1

2

0.1 U_0402_16V4Z

C73

1

2

C87

1

2

+1.05VS_PEGPLL

2

1 2

R90

10U_0805_10V4Z

0.1U_0402_16V4Z

10U_0805_10V4Z

+1.05VS_HPLL

+1.05VS_MPLL

C99

10U_FLC-453232-100K_0.25A_10%

C74

1

2

R94

1 2

10U_FLC-453232-100K_0.25A_10%

0.1U_0402_16V4Z

C90

C91

1

1

2

2

1

2

10U_0805_10V4Z

0.1U_0402_16V4Z
C106

1

2

+VCCP+1.05VS_DPLLB

R98

1 2

MBK2012121YZF_0805

10U_0805_10V4Z

R101

1 2

MBK2012121YZF_0805

1

C100
10U_0805_10V4Z

2

L1

1 2

BLM18PG121SN1D_0603

C108

1

2

+VCCP

+3VS

+VCCP

+VCCP

+VCCP

+VCCP

+VCCP_D

D3

2 1

CH751H-40PT_SOD323-2

@

C83

R105

1 2

10_0402_5%

+V1.05VS_AXF

10U_0805_10V4Z

+1.8V_SM_CK

10U_0805_10V4Z

C84

1

2

+1.5VS_TVDAC

C92

+VCC_PEG

C98

+1.05VS_D MI

C78

1

2

10U_0805_10V4Z

1

2

0.022U_0402_16V7K

1

2

220U_D2_4VM

1

+

2

C109

1

2

R106

1 2

0_0402_5%

1

C93

C101

R104

1 2

0_0603_5%

0.1U_0402_16V4Z

+VCCP

R93

1 2

1U_0603_10V4Z

0_0603_5%

C79

1

2

+1.8V

R95

0.1U_0402_16V4Z

1 2

0_0805_5%

C85

1

2

+1.5VS

R99

1 2

0.1U_0402_16V4Z
0_0805_5%

R102

1 2

0_0805_5%

+VCCP

+3VS_HV

+VCCP

1

2

10U_0805_10V4Z

1

2

+1.8V_LVDS

R107

1 2

@

R109

12

0_0603_5%

2

@

R114

12

0_0603_5%

+1.5VS_Q DAC

0.022U_0402_16V7K

C119

1

2

0.1U_0402_16V4Z

@

220U_D2_4VM

C120

1

1

2

C121

+

2

+3VS_TVDAC

@

A A

R113

0.022U_0402_16V7K

12

0_0603_5%

C117

1

2

0.1U_0402_16V4Z

C118

1

2

R111

1 2

BLM18PG181SN1D_0603

+3VS

5

4

R112

1 2

100_0603_1%

+1.5VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

1U_0603_10V4Z

10U_0805_10V4Z

1

2

0_0603_5%

C114

C113

1

2

Title

Size Document Num ber Rev

Cus tom

Date: Sheet of

@

+1.8V

R110

12

Compal Electronics, Inc.

Cantiga(4/6)-PWR

Monte vina Bla de UMA LA4101P

40 mils

0_0603_5%

1000P_0402_50V7K

+1.8V_TXLVDS

C116

1

2

R108

1 2

0_0603_5%

@

220U_D2_4VM

1

C115

+

2

1

+1.8V

0.3

12 46Sat urday, January 05, 2008

5

www.kythuatvitinh.com

4

3

2

1

W28
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16

AV44
BA37
AM40
AV21
AY5
AM10
BB13

+V CCP

VCCS M_L F1
VCCS M_L F2
VCCS M_L F3
VCCS M_L F4
VCCS M_L F5
VCCS M_L F6
VCCS M_L F7

0.1U_0402_16V4Z

1

C127

2

0.22U_0402_10V4Z

C139 0.1 U_0402_16V4Z

1

2

4.7U_0603_6.3V6M

1

1

2

C140 0.1 U_0402_16V4Z

1

1

2

2

C129

C128

2

C141 0 .22U_0603_10V7K

1

2

C144 1 U_0603_ 10V4Z

C143 0 .47U_0402_6.3V6K

C142 0 .22U_0603_10V7K

1

2

C145 1 U_0603_ 10V4Z

1

1

2

2

U2 G

3000mA

Extnal Graphic: 1210.34mA
integrated Graphic: 1930.4mA

+VCCP

D D

0.22U_0402_10V4Z

0.22U_0402_10V4Z

10U_0805_10V4Z

220 U_D2_4VM

1

C124

C131

1

+

2

2

C C

B B

0.1U_0402_16V4Z

C133

C132

1

2

C125

1

1

2

2

U2 F

AG34

VCC

AC34

VCC

AB34

VCC

AA34

VCC

Y34

VCC

V34

VCC

U34

VCC

AM33

VCC

AK33

VCC

AJ33

VCC

AG33

VCC

AF33

VCC

AE33

VCC

AC33

VCC

AA33

VCC

Y33

VCC

W33

VCC

V33

VCC

U33

VCC

AH28

VCC

AF28

VCC

AC28

VCC

AA28

VCC

AJ26

VCC

AG26

VCC

AE26

VCC

AC26

VCC

AH25

VCC

AG25

VCC

AF25

VCC

AG24

VCC

AJ23

VCC

AH23

VCC

AF23

VCC

T32

VCC

CANT IGA ES_ FCBGA1329

VCC CORE

+V CCP

AM32

VCC_NCTF

AL32

VCC_NCTF

AK32

VCC_NCTF

AJ32

VCC_NCTF

AH32

VCC_NCTF

AG32

VCC_NCTF

AE32

VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF

AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23

POWER

VCC NCTF

1U_0603_10V4Z

+1.8 V

1

C134

2

330 U_D2E_2.5VM_R7

1

+

2

10U_0805_10V4Z

330 U_D2E_2.5VM_R7

1

+

C135

2

10U_0805_10V4Z

10U_0805_10V4Z

C126

C122

1

2

031 7 change value

1

C136

2

10U_0805_10V4Z

0.01U_0402_16V7K

C130

1

2

+VCCP

0.1U_0402_16V4Z

1

1

C138

C137

2

2

T42PA D
T43PA D

2

1

AP33

VCC_SM

AN33

VCC_SM

BH32

VCC_SM

BG32

VCC_SM

BF32

VCC_SM

BD32

VCC_SM

BC32

C123

BB32
BA32
AY32

AW32

AV32
AU32
AT32
AR32
AP32
AN32
BH31
BG31
BF31
BG30
BH29
BG29
BF29
BD29
BC29
BB29
BA29
AY29

AW29

AV29
AU29
AT29
AR29
AP29

BA36
BB24
BD16

BB21
AW16
AW13

AT13

AE25

AB25

AA25

AE24

AC24

AA24

AE23

AC23

AB23

AA23

AJ21

AG21

AE21

AC21

AA21

AH20

AF20

AE20

AC20

AB20

AA20

AM15

AL15

AE15

AJ15

AH15

AG15

AF15

AB15

AA15

AN14

AM14

AJ14

AH14

Y26

Y24

Y21

T17
T16

Y15
V15
U15

U14

T14

VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM

VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC

6326.84mA

VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG

VCC_AXG_SENSE
VSS_AXG_SENSE

VCC SMVCC GFX

VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF

POWER

VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF

VCC GFX NCTF

VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF

VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF

VCC SM LF

A A

CANT IGA ES_ FCBGA1329

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

5

4

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Do cument Number Re v

Cu st om

2

Da te: Sheet o f

Compal Electronics, Inc.

Cantiga(5/6)-PWR/GND

Montev ina Blade UMA LA4101P

1

13 46Saturday, January 05, 2008

0.3

5

www.kythuatvitinh.com

4

3

2

1

U2 I

AU48

VSS

AR48

VSS

AL48

VSS

BB47

VSS

AW47

VSS

AN47

VSS

AJ47

VSS

AF47

D D

C C

B B

A A

VSS

AD47

VSS

AB47

VSS

Y47

VSS

T47

VSS

N47

VSS

L47

VSS

G47

VSS

BD46

VSS

BA46

VSS

AY46

VSS

AV46

VSS

AR46

VSS

AM46

VSS

V46

VSS

R46

VSS

P46

VSS

H46

VSS

F46

VSS

BF44

VSS

AH44

VSS

AD44

VSS

AA44

VSS

Y44

VSS

U44

VSS

T44

VSS

M44

VSS

F44

VSS

BC43

VSS

AV43

VSS

AU43

VSS

AM43

VSS

J43

VSS

C43

VSS

BG42

VSS

AY42

VSS

AT42

VSS

AN42

VSS

AJ42

VSS

AE42

VSS

N42

VSS

L42

VSS

BD41

VSS

AU41

VSS

AM41

VSS

AH41

VSS

AD41

VSS

AA41

VSS

Y41

VSS

U41

VSS

T41

VSS

M41

VSS

G41

VSS

B41

VSS

BG40

VSS

BB40

VSS

AV40

VSS

AN40

VSS

H40

VSS

E40

VSS

AT39

VSS

AM39

VSS

AJ39

VSS

AE39

VSS

N39

VSS

L39

VSS

B39

VSS

BH38

VSS

BC38

VSS

BA38

VSS

AU38

VSS

AH38

VSS

AD38

VSS

AA38

VSS

Y38

VSS

U38

VSS

T38

VSS

J38

VSS

F38

VSS

C38

VSS

BF37

VSS

BB37

VSS

AW37

VSS

AT37

VSS

AN37

VSS

AJ37

VSS

H37

VSS

C37

VSS

BG36

VSS

BD36

VSS

AK15

VSS

AU36

VSS

CANT IGA ES_ FCBGA1329

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
AD12
AY24
AT24
AJ24
AH24
AF24
AB24
R24
L24
K24
J24
G24
F24
E24
BH23
AG23
Y23
B23
A23
AJ6

U2 J

BG21

VSS

L12

VSS

AW21

VSS

AU21

VSS

AP21

VSS

AN21

VSS

AH21

VSS

AF21

VSS

AB21

VSS

R21

VSS

M21

VSS

J21

VSS

G21

VSS

BC20

VSS

BA20

VSS

AW20

VSS

AT20

VSS

AJ20

VSS

AG20

VSS

Y20

VSS

N20

VSS

K20

VSS

F20

VSS

C20

VSS

A20

VSS

BG19

VSS

A18

VSS

BG17

VSS

BC17

VSS

AW17

VSS

AT17

VSS

R17

VSS

M17

VSS

H17

VSS

C17

VSS

BA16

VSS

AU16

VSS

AN16

VSS

N16

VSS

K16

VSS

G16

VSS

E16

VSS

BG15

VSS

AC15

VSS

W15

VSS

A15

VSS

BG14

VSS

AA14

VSS

C14

VSS

BG13

VSS

BC13

VSS

BA13

VSS

AN13

VSS

AJ13

VSS

AE13

VSS

N13

VSS

L13

VSS

G13

VSS

E13

VSS

BF12

VSS

AV12

VSS

AT12

VSS

AM12

VSS

AA12

VSS

J12

VSS

A12

VSS

BD11

VSS

BB11

VSS

AY11

VSS

AN11

VSS

AH11

VSS

Y11

VSS

N11

VSS

G11

VSS

C11

VSS

BG10

VSS

AV10

VSS

AT10

VSS

AJ10

VSS

AE10

VSS

AA10

VSS

M10

VSS

BF9

VSS

BC9

VSS

AN9

VSS

AM9

VSS

AD9

VSS

G9

VSS

B9

VSS

BH8

VSS

BB8

VSS

AV8

VSS

AT8

VSS

CANT IGA ES_ FCBGA1329

VSS

AH8

VSS

Y8

VSS

L8

VSS

E8

VSS

B8

VSS

AY7

VSS

AU7

VSS

AN7

VSS

AJ7

VSS

AE7

VSS

AA7

VSS

N7

VSS

J7

VSS

BG6

VSS

BD6

VSS

AV6

VSS

AT6

VSS

AM6

VSS

M6

VSS

C6

VSS

BA5

VSS

AH5

VSS

AD5

VSS

Y5

VSS

L5

VSS

J5

VSS

H5

VSS

F5

VSS

BE4

VSS

BC3

VSS

AV3

VSS

AL3

VSS

R3

VSS

P3

VSS

F3

VSS

BA2

VSS

AW2

VSS

AU2

VSS

AR2

VSS

AP2

VSS

AJ2

VSS

AH2

VSS

AF2

VSS

AE2

VSS

AD2

VSS

AC2

VSS

Y2

VSS

M2

VSS

K2

VSS

AM1

VSS

AA1

VSS

P1

VSS

H1

VSS

U24

VSS

U28

VSS

U25

VSS

U29

VSS

AF32

VSS_NCTF

AB32

VSS_NCTF

V32

VSS_NCTF

AJ30

VSS_NCTF

AM29

VSS_NCTF

AF29

VSS_NCTF

AB29

VSS_NCTF

U26

VSS_NCTF

U23

VSS_NCTF

AL20

VSS_NCTF

V20

VSS_NCTF

AC19

VSS_NCTF

AL17

VSS_NCTF

AJ17

VSS_NCTF

VSS NCTF

VSS SCB

NC

VSS_NCTF
VSS_NCTF

VSS_SCB
VSS_SCB
VSS_SCB
VSS_SCB
VSS_SCB

AA17
U17

BH48
BH1
A48
C1
A3

E1

NC

D2

NC

C3

NC

B4

NC

A5

NC

A6

NC

A43

NC

A44

NC

B45

NC

C46

NC

D47

NC

B47

NC

A46

NC

F48

NC

E48

NC

C48

NC

B48

NC

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

5

4

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Do cument Number Re v

Cu st om

2

Da te: Sheet o f

Compal Electronics, Inc.

Cantiga(6/6)-PWR/GND

Montev ina Blade UMA LA4101P

1

14 46Saturday, January 05, 2008

0.3

5

www.kythuatvitinh.com

DDR_A_DQS#[0..7]<10>
DDR_A_D[0..63]<10>
DDR_A_DM[0..7]<10>
DDR_A_DQS[0 ..7]<10>
DDR_A_ MA[0..14 ]<10>

D D

C C

B B

A A

Layout Note:
Place near
JP3

+1.8V

2.2U_0805_16V4Z

2.2U_0805_16V4Z
C147

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C159

R117 56_0402_5%

2.2U_0805_16V4Z

1

2

0.1U_0402_16V4Z

1

2

C160

RP156_ 040 4_4P2R_5%

1 4
2 3

RP356_ 040 4_4P2R_5%

1 4
2 3

RP556_ 040 4_4P2R_5%

1 4
2 3

RP756_ 040 4_4P2R_5%

1 4
2 3

RP956_ 040 4_4P2R_5%

1 4
2 3

RP1156_ 040 4_4P2R_5%

2 3
1 4

1 2

C153

1

2

C161

+0.9V

2.2U_0805_16V4Z
C152

1

2

Layout Note:
Place one cap close to every 2
pullup
resistors terminated to +0.9VS

+0.9V

0.1U_0402_16V4Z

1

2

C158

DDR_A_MA8
DDR_A_ MA5

DDR_A_ MA1
DDR_A_ MA3

DD R_A _RAS#
DDR_CS0_ DIMMA#

DDR_A_ BS0
DDR_A_MA 10

DD R_A _CAS#
DDR_A_WE#

DDR_CS1_ DIMMA#
M_ODT1

DDR_A_MA11

2.2U_0805_16V4Z

C154

1

2

5 10

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C162

RP2 56_ 040 4_4P2R_5%

RP4 56_ 040 4_4P2R_5%

RP6 56_ 040 4_4P2R_5%

RP8 56_ 040 4_4P2R_5%

RP10 56_04 04_ 4P2R_5%

RP12 56_04 04_ 4P2R_5%

RP13 56_04 04_ 4P2R_5%

C155

1

2

0.1U_0402_16V4Z

1

1

2

2

C164

C163

DDR_A_ BS2

14

DDR_CKE0_DIMMA

23

DDR_A_ MA7

14

DDR_A_MA6

23

DDR_A_MA 12

14

DDR_A_ MA9

23

DDR_A_ MA4

14

DDR_A_ MA2

23

DDR_A_ MA0

14

DDR_A_ BS1

23

M_ODT0

14

DDR_A_MA 13

23

DDR_CKE1_DIMMA

14

DDR_A_MA 14

23

0.1U_0402_16V4Z
C156

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C165

5

4

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C166

C149

C148

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C167

330 U_D2E_2.5VM_R7

0.1U_0402_16V4Z

1

2

C168

1

C157

1

+

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C170

C169

Layout Note:
Place these resistor
closely JP3,all
trace length Max=1.5"

C150

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+1.8V

V_ DD R_MCH_REF

JDIMM1

1

VREF

3

DDR_ A_D4
DDR_ A_D1

DDR_A_DQS#0
DDR_A_DQS0

DDR_ A_D2
DDR_ A_D3

DDR_ A_D8
DDR_ A_D9

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D1 1 DDR_A_D1 5
DDR_A_D1 0 DDR_A_D1 4

DDR_A_D1 6
DDR_A_D1 7

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D1 8
DDR_A_D1 9

DDR_A_DM3

DDR_A_D2 6
DDR_A_D2 7

DDR_CKE0_DIMMA<9>

DDR_A_BS2<10>

DDR_A_BS0<10>

DDR_A_ WE#<10>

DDR_A_ CAS #<10>

DDR_CS1_DIMMA#<9>

M_ODT1<9>

CLK_SMBDATA<16,17>
CLK_SMBCLK<16,1 7>

+3VS

3

DDR_CKE0_DIMMA

DDR_A_ BS2
DDR_A_MA 12

DDR_A_ MA9 DDR_A_ MA7
DDR_A_MA8

DDR_A_ MA5
DDR_A_ MA3
DDR_A_ MA1

DDR_A_MA 10
DDR_A_ BS0
DDR_A_WE#

DD R_A _CAS#
DDR_CS1_ DIMMA#

M_ODT1
DDR_A_D3 7

DDR_A_D3 6
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D3 9

DDR_A_D3 8
DDR_A_D4 5

DDR_A_D4 4
DDR_A_DM5
DDR_A_D4 7 DDR_A_D4 3

DDR_A_D4 6
DDR_A_D4 9

DDR_A_D4 8

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D5 0
DDR_A_D6 1 DDR_A_D5 7

DDR_A_D6 0
DDR_A_DM7
DDR_A_D5 9

DDR_A_D5 8
CLK_SMBDATA

CLK_SMBCLK

C172

C171

Compal Secret Data

1

2

1

2

2.2U_0603_6.3V4Z

2006/02/13 2006/03/10

5

7

9

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

0.1U_0402_16V4Z

Deciphered Date

VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

FOX _AS OA426-M4R-TR

C ONN@

SO-DIMM A

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0
CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD

BA1
RAS#

VDD
ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1
CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

SA1

2

+1.8 V

2

DDR_ A_D5

4

DDR_ A_D0

6
8

DDR_A_DM0

10
12

DDR_ A_D6

14

DDR_ A_D7

16
18

DDR_A_D1 3

20

DDR_A_D1 2

22
24

DDR_A_DM1

26
28

M_ CLK_DDR0

30

M_ CLK_DDR#0

32
34
36
38
40

42

DDR_A_D2 0

44

DDR_A_D2 1

46
48
50

NC

A11

A7
A6

A4
A2
A0

S0#

NC

2

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_A_DM2
DDR_A_D2 3

DDR_A_D2 2
DDR_A_D2 8DDR_A_D2 9

DDR_A_D2 5DDR_A_D2 4
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D3 1

DDR_A_D3 0
DDR_CKE1_DIMMA

DDR_A_MA 14
DDR_A_MA11
DDR_A_MA6
DDR_A_ MA4

DDR_A_ MA2
DDR_A_ MA0

DDR_A_ BS1
DD R_A _RAS#
DDR_CS0_ DIMMA#

M_ODT0
DDR_A_MA 13

DDR_A_D3 2
DDR_A_D3 3

DDR_A_DM4
DDR_A_D3 4

DDR_A_D3 5
DDR_A_D4 0

DDR_A_D4 1
DDR_A_DQS#5

DDR_A_DQS5

DDR_A_D4 2
DDR_A_D5 2

DDR_A_D5 3
M_ CLK_DDR1

M_ CLK_DDR#1
DDR_A_DM6
DDR_A_D5 1DDR_A_D5 4

DDR_A_D5 5

DDR_A_D5 6
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D6 2

DDR_A_D6 3

12

R116

R115

10K _04 02_5%

10K _04 02_5%

12

2.2U_0805_16V4Z
C146

1

2

M_ CLK _DDR0 <9>
M_CLK_ DDR#0 <9>

PM_EXTTS#0 <9>

DDR_CKE1_DIMMA <9>

DDR_A_BS1 <10>
DDR_A_ RAS # <10>
DDR_CS0_DIMMA# <9>

M_ODT0 <9>

M_ CLK _DDR1 <9>
M_CLK_ DDR#1 <9>

Title

Size Do cument Number Re v

Cu st om

Da te: Sheet o f

Compal Electronics, Inc.

DDRII-SODIMM SLOT1

Montev ina Blade UMA LA4101P

1

C151

1

V_ DD R_MCH_REF <9,1 6>

0.3

15 46Saturday, January 05, 2008

0.1U_0402_16V4Z

1

2

5

www.kythuatvitinh.com

DDR_B_DQS#[0..7 ]<10>
DDR_B_D[0..63]<10>
DDR_B_DM[0..7]<10>
DDR_B_DQS[0 ..7]<10>
DDR_B _MA[0..1 4]<10>

D D

C C

B B

A A

Layout Note:
Place near
JP10

+1.8 V

2.2U_0805_16V4Z

1

2

0.1U_0402_16V4Z

1

2

C186

RP1456_ 040 4_4P2R_5%

1 4
2 3

RP1656_ 040 4_4P2R_5%

1 4
2 3

RP1856_ 040 4_4P2R_5%

1 4
2 3

RP2056_ 040 4_4P2R_5%

1 4
2 3

RP2256_ 040 4_4P2R_5%

1 4
2 3

RP2456_ 040 4_4P2R_5%

2 3
1 4

1 2

2.2U_0805_16V4Z

C176

0.1U_0402_16V4Z

1

2

C187

+0.9V

2.2U_0805_16V4Z

2.2U_0805_16V4Z

Layout Note:
Place one cap close to every 2
pullup
resistors terminated to +0.9VS

+0.9 V

0.1U_0402_16V4Z

DDR_B_ MA3
DDR_B_ MA1

DDR_B_ BS0
DDR_B_MA 10

DDR_B_ MA0
DDR_B_ BS1

DDR_CS2_ DIMMB#
DD R_B _RAS#

DD R_B _CAS#
DDR_B_WE#

DDR_CS3_ DIMMB#
M_ODT3

DDR_CKE3_DIMMB

C174

1

2

0.1U_0402_16V4Z

1

2

C184

C175

1

2

0.1U_0402_16V4Z

1

2

C185

R120 56_0 402_5%

5

2.2U_0805_16V4Z

C183

C177

1

1

2

2

5 10

0.1U_0402_16V4Z

1

1

2

2

C189

C188

RP15 56_04 04_ 4P2R_5%

14
23

RP17 56_04 04_ 4P2R_5%

14
23

RP19 56_04 04_ 4P2R_5%

14
23

RP21 56_04 04_ 4P2R_5%

14
23

RP23 56_04 04_ 4P2R_5%

14
23

RP25 56_04 04_ 4P2R_5%

14
23

RP26 56_04 04_ 4P2R_5%

14
23

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C190

DDR_B_MA 12
DDR_B_ MA9

DDR_B_MA11
DDR_B_MA 14

DDR_B_ MA5
DDR_B_MA8

DDR_B_MA6
DDR_B_ MA7

DDR_B_ MA2
DDR_B_ MA4

DDR_B_MA 13
M_ODT2

DDR_CKE2_DIMMB
DDR_B_ BS2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C178

1

2

0.1U_0402_16V4Z

1

2

C192

C191

5

4

0.1U_0402_16V4Z
C180

C179

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C193

C194

Layout Note:
Place these resistor
closely JP3,all
trace length Max=1.5"

4

3

+1.8V

V_ DD R_MCH_REF

JDIMM2

1

VREF

3

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

0.1U_0402_16V4Z

Deciphered Date

5
7
9

VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

FOX _AS 0A4 26-N8RN-7F

C ONN@

SO-DIMM B

DDR_ B_D0
DDR_ B_D1

DDR_B_DQS#0
DDR_B_DQS0

DDR_ B_D2
DDR_ B_D3

DDR_ B_D8
DDR_ B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D1 0
DDR_B_D1 1

0.1U_0402_16V4Z
C181

1

2

DDR_CKE2_DIMMB<9>

DDR_B_BS2<10>

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C195

C196

DDR_B_BS0<10>

DDR_B_ WE#<10>

DDR_B_ CAS #<10>

DDR_CS3_DIMMB#<9>

M_ODT3<9>

CLK_SMBDATA<15,17>
CLK_SMBCLK<15,17>

+3VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

DDR_B_D2 0
DDR_B_DQS#2

DDR_B_DQS2
DDR_B_D1 9

DDR_B_D1 8
DDR_B_D2 8

DDR_B_DM3

DDR_B_D3 0
DDR_B_D3 1

DDR_CKE2_DIMMB

DDR_B_ BS2
DDR_B_MA 12

DDR_B_ MA9
DDR_B_MA8

DDR_B_ MA5
DDR_B_ MA3
DDR_B_ MA1

DDR_B_MA 10
DDR_B_ BS0
DDR_B_WE#

DD R_B _CAS#
DDR_CS3_ DIMMB#

M_ODT3
DDR_B_D3 2

DDR_B_D3 7
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D3 4

DDR_B_D3 5
DDR_B_D4 0

DDR_B_D4 1
DDR_B_DM5
DDR_B_D4 2

DDR_B_D4 3
DDR_B_D4 8

DDR_B_D4 9

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D5 4
DDR_B_D5 5

DDR_B_D6 0
DDR_B_D6 1 DDR _B_D57

DDR_B_DM7
DDR_B_D6 3

DDR_B_D5 8
CLK_SMBDATA

CLK_SMBCLK

1

C197

2

2.2U_0603_6.3V4Z

2006/02/13 2006/03/10

1

C198

2

Compal Secret Data

VSS
DQ4
DQ5
VSS

DM0

VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0
CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD
NC/A15
NC/A14

VDD

VDD

VDD

BA1

RAS#

VDD

ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1
CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SA0

SA1

2

+1.8V

2.2U_0805_16V4Z

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90

A11

92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110

S0#

112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

2

DDR_ B_D5
DDR_ B_D4

DDR_B_DM0
DDR_ B_D6

DDR_ B_D7
DDR_B_D1 2

DDR_B_D1 3
DDR_B_DM1
M_ CLK_DDR2

M_ CLK_DDR#2
DDR_B_D1 4

DDR_B_D1 5

DDR_B_D1 6DD R_B_D21
DDR_B_D1 7

DDR_B_DM2
DDR_B_D2 2

DDR_B_D2 3
DDR_B_D2 9

DDR_B_D2 4DD R_B_D25
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D2 6

DDR_B_D2 7
DDR_CKE3_DIMMB

DDR_B_MA 14
DDR_B_MA11

DDR_B_ MA7
DDR_B_MA6

DDR_B_ MA4
DDR_B_ MA2
DDR_B_ MA0

DDR_B_ BS1
DD R_B _RAS#
DDR_CS2_ DIMMB#

M_ODT2
DDR_B_MA 13

DDR_B_D3 6
DDR_B_D3 3

DDR_B_DM4
DDR_B_D3 9

DDR_B_D3 8
DDR_B_D4 4

DDR_B_D4 5
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D4 6

DDR_B_D4 7
DDR_B_D5 2

DDR_B_D5 3
M_ CLK_DDR3

M_ CLK_DDR#3
DDR_B_DM6
DDR_B_D5 0

DDR_B_D5 1
DDR_B_D5 6

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D5 9
DDR_B_D6 2

10K _0402_5%

12

R119

R118

1 2

10K _04 02_5%

Title

Size Do cument Number Re v

Da te: Sheet o f

0.1U_0402_16V4Z

1

1

C173

2

2

M_ CLK _DDR2 <9>
M_CLK_ DDR#2 <9>

PM_EXTTS#1 <9>

DDR_CKE3_DIMMB <9>

0612 add

DDR_B_BS1 <10>
DDR_B_ RAS # <10>
DDR_CS2_DIMMB# <9>

M_ODT2 <9>

M_ CLK _DDR3 <9>
M_CLK_ DDR#3 <9>

+3VS

Compal Electronics, Inc.

DDRII-SODIMM SLOT2

Montev ina Blade UMA LA4101P

1

V_ DD R_MCH_REF <9,15>

C182

1

16 46Saturday, January 05, 2008

0.3

5

www.kythuatvitinh.com

PCI

FSC

FSB

CLKSEL2

CLKSEL1

00

00

0

1

D D

0

1

0

1

0

1

1

1

1

1

FSA

CPU_ BSEL0<7>

C C

FSB

CPU_ BSEL1<7>

B B

FS C

CPU_ BSEL2<7>

FSA

CLKSEL0

0

1

0
1

0

1

0
1

R128

1 2

2.2K_0402_5%
R138

1 2

0_0 402_5%

R154

1 2

0_0 402_5%

R164

1 2

10K _0402_5%
R171

1 2

0_0 402_5%

CPU
MHz

266

133

200

166

333

100

400

+VCCP

+VCCP

12

1 2

R129
1K_0402_5%

12

@

R139
1K_0402_5%

@

R143
1K_0402_5%

1 2

1 2

R150
1K_0402_5%

12

@

R157
0_0 402_5%

12

@

R163
1K_0402_5%

1 2

R165
1K_0402_5%

12

@

R174
0_0 402_5%

MHz

100

100

100

100

100

100

100

R123

1 2

56_ 0402_5%

CL RP1
NO S HORT PADS

SRC

REF

MHz

MHz

33.3

14.318 96.0 48.0

14.318

33.3

14.318

33.3

14.318

33.3

14.318

33.3

14.318

33.3

14.318

33.3

Reserved

+V CCP

MCH_CLKS EL0 <9>

MCH_CLKS EL1 <9>

MCH_CLKS EL2 <9>

DOT_96
MHz

96.0

96.0

96.0

96.0

96.0

96.0

NB
CPU

CLK_ENA BLE#<43>

CK _P WRGD<22>

CLK_14M_ICH<22>

CLK_SMBDATA<15,16>

CLK_SMBCLK<15,1 6>

CLK_DEB UG_PORT_1<26>
CLK_DEB UG_PORT_0<31>

CL K_PCI_EC<32>
CL K_ PCI_ICH<20>

Change 33M and 48M damping to 39M by EMI request

NB (UMA)

4

USB
MHz

48.0

48.0

48.0

48.0

48.0

48.0

VGATE<22,43>

18P _04 02_50V8J

CLKREQ#_7<9>

CLK_MCH_BCLK<9>
CLK_CPU_BCL K#<6>
CLK_CP U_BCLK<6>

R141 0_0 402_5%@
R142 0_0 402_5%@
R140 0_0 402_5%

No Debug port anymore

R147 33_ 0402_1%

R393 39_0 402_1%
R155 39_0 402_1%

R158 33_ 0402_1%
R161 33_ 0402_1%

CLK_48M_ICH<22>

CL K_ MCH_DREFCLK<9>
CL K_ MCH_DREFCLK #<9>

+3VS

Routing the trace at least 10mil

Y1

1 2

C213

2

2

1

1

Vendor suggests 22pF

R126 475 _0402_1%

1 2

R130 0_0 402_5%

1 2

R132 0_0 402_5%

1 2

R134 0_0 402_5%

1 2

R136 0_0 402_5%

1 2

1 2
1 2
1 2

1 2

T44

1 2
1 2
1 2

1 2

R_ CK P WRGD
FSB

CLK_XTAL_OUT
CLK_XTAL_IN

FS C
RE F1
CLK_SMBDATA
CLK_SMBCLK

P CI2_1
PCI2 _TME
27_SEL
P CI_CL K3
ITP_EN

R167 39_0 402_1%

1 2

T76

R173 0_0 402_5%

1 2

R175 0_0 402_5%

1 2

+3VS_CK505

R121

1 2

0_0 805_5%

CLK_XTAL_OUT
CLK_XTAL_IN

14.318MHZ_16PF_7A14300083

C214
18P _04 02_50V8J

1

C199
10U_0805_10V4Z

2

R_ CLKREQ#_7
R_ MCH_BCL K#
R_ MCH_BCL K
R_ CPU_BCLK#
R_ CPU_BCLK

U3

+3VS_CK505

1

CKPWRGD/PD#

2

FS_B/TEST_MODE

3

VSS_REF

4

XTAL_OUT

5

XTAL_IN

6

VDD_REF

7

REF_0/FS_C/TEST_

8

REF_1

9

SDA

10

SCL

11

NC

12

VDD_PCI

13

PCI_1

14

PCI_2

15

PCI_3

16

PCI_4/SEL_LCDCL

17

PCIF_5/ITP_EN

18

VSS_PCI

+3VS_CK505

FSA
R_ CLK_48M_CRUSB

+1.0 5VS _CK505

R_ MCH_DREF CLK
R_ MC H_DREFCLK# SS C DREF CLK#

3

1

C200

0.1U_0402_16V4Z

2

+V CCP

R122

1 2

0_0 805_5%

+3VS_CK505

72

71

70

69

68

67

66

65

CPU_0

CPU_1

CPU_0#

CPU_1#

VSS_CPU

VDD_CPU

VDD_CPU_IO

VDD_4819USB_0/FS_A20USB_1/CLKREQ_A#21VSS_4822VDD_IO23SRC_0/DOT_9624SRC_0#/DOT_96#25VSS_IO26VDD_PLL327LCDCLK/27M28LCDCLK#/27M_SS29VSS_PLL330VDD_PLL3_IO31SRC_232SRC_2#33VSS_SRC34SRC_335SRC_3#

10U_0805_10V4Z

+1.0 5VS _CK505

64

63

62

61

SRC_7

CLKREQ_7#

VDD_SRC_IO

SRC_8/CPU_ITP

SRC_8#/CPU_ITP#

1

C201

0.1U_0402_16V4Z

2

+1.0 5VS _CK505

1

2

60

59

58

57

SRC_6

SRC_7#

VSS_SRC

CLKREQ_6#

1

C202

0.1U_0402_16V4Z

2

Place close to U51

0.1U_0402_16V4Z

1

C207

C206

2

0.1U_0402_16V4Z

R_ CPU_ XDP
R_CP U_XDP#
R_ MCH_3GPLL
R_MCH_3GPLL#
R_ CLKREQ#_6
R_ CL K_PCIE_MCARD2
R_ CLK_PCIE_MCARD2#

+3VS_CK505

56

55

SRC_6#

VDD_SRC

PCI_STOP#

CPU_STOP#

VDD_SRC_IO

SRC_10#

SRC_10

CLKREQ_10#

SRC_11

SRC_11#

CLKREQ_11#

SRC_9#

SRC_9

CLKREQ_9#

VSS_SRC

CLKREQ_4#

SRC_4#

SRC_4

VDD_SRC_IO

CLKREQ_3#

SLG8SP 553 VTR_QFN72_10x10

36

R_PCIE_SATA#
R_PCIE_SATA

R_ PC IE_ICH#
R_ PC IE_ICH

+1.0 5VS _CK505

SS C DREF CLK

2

1

54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37

2

10U_0805_10V4Z

1

1

C208

2

2

R124 0_0 402_5%
R125 0_0 402_5%
R127 0_0 402_5%
R131 0_0 402_5%
R133 475 _0402_1%
R135 0_0 402_5%
R137 0_0 402_5%

+1.0 5VS _CK505

H_STP_PCI#

H_STP_CPU#

R_ CLK_PCIE_MCARD0#
R_ CL K_PCIE_MCARD0

R_CL KREQ#_1 0
R_ CLK_SRC11
R_ CLK_SRC11#

R_ CLK_PCIE_LAN#
R_ CLK_PCIE_LAN
R_ CLKREQ#_9

R_ CLKREQ#_4
R_ CL K _PCIE_NCARD#
R_ CL K _PCIE_NCARD

R_ CL KRE Q#_C

R166 0_0 402_5%
R168 0_0 402_5%

R170 0_0 402_5%
R172 0_0 402_5%

R176 0_0 402_5%
R177 0_0 402_5%

C203

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C210

C209

2

0.1U_0402_16V4Z

1 2
1 2
1 2
1 2
1 2
1 2
1 2

R725 0_0 402_5%

1 2

R726 0_0 402_5%

1 2

1 2
1 2

1 2
1 2

1 2
1 2

1

C204

0.1U_0402_16V4Z

2

1

C211

2

R144 0_0 402_5%
R145 0_0 402_5%
R146 475 _0402_1%

R152 0_0 402_5%
R153 0_0 402_5%
R738 475 _0402_1%

R156 475 _0402_1%
R159 0_0 402_5%
R160 0_0 402_5%

R162 475 _0402_1%

1

2

1

C212

2

0.1U_0402_16V4Z

CLK_CPU_XDP <6>
CLK_CPU_XDP# <6>
CLK_MCH_ 3GPLL <9>
CLK_MCH_ 3GPLL# <9>CLK_MCH_ BCLK#<9>

CLKREQ#_6 <26>

CL K_PCIE_MCARD2 <26>
CLK_PCIE_MCARD2# <26>

H_STP_PCI# <22>
H_STP_CPU# <22>

1 2
1 2
1 2

1 2
1 2
1 2

1 2
1 2
1 2

1 2

Ne wC@
Ne wC@
Ne wC@

CLK_PCIE_S ATA# <21>
CLK_PCIE_SATA <21>

CL K_ PCIE_ICH# <22>
CL K_ PCIE_ICH <22>

MCH_SSCDREFCLK# <9>
MCH_SS CDREFCLK <9>

C205

0.1U_0402_16V4Z

2Mi niC@
2Mi niC@
2Mi niC@

CLK_PCIE_MCARD0# <26>
CL K_PCIE_MCARD0 <26>

CLKREQ#_10 <26>
CLK_SRC11 <27>
CLK_SRC11# <27>

CLK_PCIE_LAN# <25>
CLK_PCIE_LAN <25>

CLKREQ#_9 <25>

CLKREQ#_4 <26>

CL K_ PCIE_NCARD# <26>
CL K_ PCIE_NCARD <26>

CL KRE Q#_C <22>

1

XDP/ITP

3G_PLL

MiniCard_2(WLAN)

MiniCard_0

LAN

New Card

SATA

ICH

NB_SSC (UMA)

+3VS

R178

2.2K_0402_5%

2007/08/28 2006/03/10

R179

2.2K_0402_5%

CLK_SMBDATA

CLK_SMBCLK

Compal Secret Data

Deciphered Date

C215

@

5P_040 2_50V8C

C216

@

4.7P_0402_50V8C
C217

@

4.7P_0402_50V8C
C218

@

4.7P_0402_50V8C
C219

@

5P_040 2_50V8C

Title

Size Do cument Number Re v

2

Da te: Sheet

Compal Electronics, Inc.

Clock Generator CK505

Montev ina Blade UMA LA4101P

CL K_48M_ICH

12

CL K_14M_ICH

12

CL K_ PCI_ICH

12

CL K_ PCI_ EC

12

CLK_DEB UG_PORT_0

12

1

0.3

o f

17 46Saturday, January 05, 2008

Q3A

6 1

5

2N7002DW-7-F_S OT363-6

4

<BOM Structu re>

+3VS

2

3

ITP_EN

PCI_CLK3

A A

0 = SRC8/SRC8#
1 = ITP/ITP#
0 = Enable DOT96 & SRC1(UMA)
1 = Enable SRC0 & 27MHz(DIS)

+3VS +3VS

12

R180
10K _0402_5%

ITP_EN P CI_CL K3

12

@

R182
10K _0402_5%

5

12

@

R181
10K _0402_5%

12

R183
10K _0402_5%

+3VS

ICH_SMBDATA<22,24,26>

SB, MINI PCI

ICH_SMB CLK<22,24,26>

Q3B

3

2N7002DW-7-F_S OT363-6

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

www.kythuatvitinh.com

1 1

CRT Connector

+5VS +5VS

C221

0.1U_0402_16V4Z

1 2

1

5

U4
SN74AHCT1G1 25GW_SOT353-5

2 2

CRT_ HSYNC<11>

CRT_VSY NC<11>

CRT_ HS YNC

CRT_ VS YNC

P

A2Y

G

3

4

OE#

B

C222

0.1U_0402_16V4Z

1 2

HS YNC_G_A

1

5

P

A2Y

G

3

VS Y NC_G_A D_ VS Y NC

4

OE#

U5
SN74AHCT1G1 25GW_SOT353-5

R184

1 2

R189

1 2

D_ HS YNC<34>

D_ VS YNC<34>

R ED<34>

GREEN<34>

BLUE<34>

0_0 603_5%

0_0 603_5%

R ED

GR EEN

BLUE

D_ HS YNC

@

1

C223
5P_040 2_50V8C

2

C

D4

2 1

RB491D_ SC59-3

@

1

C224
5P_040 2_50V8C

2

F1

1.1A_6VDC_FUS E

2.2K_0402_5%

D_ DD CDATA

D_ DDCCL K

21

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

SUY IN_070546FR015S263ZR

C ONN@

12

R185

2.2K_0402_5%

D_ DDCDATA <34>
D_ DDCCL K <34>

W=40mils

0.1U_0402_16V4Z
C220

JC RT1

16
17

R186

D

+CRT VDD+RCRT_VCC+5VS

1

2

+3VS+CRT VDD +CRT VDD

12

2

6 1

Q5A

2N7002DW-7-F_S OT363-6

BLUE
GR EEN
R ED

2.2K_0402_5%

5

3

4

Q5B

2N7002DW-7-F_S OT363-6

R187

D5

@

+3VS

12

1

2

3

12

R188

2.2K_0402_5%

@

DAN2 17T 146 _SC59-3

3V DD CDA

3V DD CCL

E

Place close to

D6

1

2

3

D7

@

2

DAN2 17T 146 _SC59-3

3V DD CDA <11>

3V DD CCL <11>

1

3

JCRT1

+CRTV DD

DAN2 17T 146 _SC59-3

CRT Termination/EMI Filter

3 3

M_ RED<11>

M_GREEN<11>

M_B LUE<11>

4 4

12

12

R196

R195

150 _04 02_1%

A

B

C_ RE D

C_ GRN

22P _04 02_50V8J

12

R197

150 _04 02_1%

150 _04 02_1%

22P _04 02_50V8J

1

1

1

2

2

2

C227

@

C226

@

C225

@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

11/07 Change CRT lounting NB-->Docking-->CRT connector

L2

1 2

HLC0 603CSCCR11JT_0603

L3

1 2

HLC0 603CSCCR11JT_0603

L4

1 2

HLC0 603CSCCR11JT_0603

22P _04 02_50V8J

2007/08/28 2006/07/26

10P _04 02_50V8J

1

1

2

2

C229

C228

Compal Secret Data

Deciphered Date

R ED

GR EEN

BLUEC_ BL U

10P _04 02_50V8J

10P _04 02_50V8J

1

2

C230

Title

Size Do cument Number Re v

D

Da te: Sheet o f

Compal Electronics, Inc.

CRT Connector

Montev ina Blade UMA LA4101P

18 46Saturday, January 05, 2008

E

0.3

5

www.kythuatvitinh.com

INVPWR_B ++ LC DVDD+3VS

4

3

2

1

D D

C C

C235

12

680 P_0 402_50V7K

USB 20_P4<22>
USB 20_N4<22>

LVDS_A CLK+
LVDS_A CLK­DDC2 _CLK
DD C2_DATA

C237

C236

1

12

2

680 P_0 402_50V7K

680 P_0 402_50V7K

USB 20_P4
USB 20_N4

11/17 Delete LVDS B

C1399 100 P_0 402_50V8J@

1 2

C1400 100 P_0 402_50V8J@

1 2

C1401 100 P_0 402_50V8J@

1 2

C1402 100 P_0 402_50V8J@

1 2

0831 EMI request

LVDS CONN & USB Camera + Dig Mic

+3VS

JLVDS1

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39
GND41GND

ACE S_8 8242-4001

C ONN@

10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

LVDS_A2-

2

2

LVDS_A2+

4

4

LVDS_A1-

6

6

LVDS_A1+

8

8

LVDS_A0-

10

LVDS_A0+

12

LVDS_A CLK-

14

LVDS_A CLK+

16
18
20
22
24
26
28
30
32
34
36
38
40
42

11/07 Change R727 to 0805 size

DM IC_DAT
DMIC_CLK
+3V_LOGO

R727

INV_P WM
BKOFF#
DA C_ BRIG

DDC2 _CLK
DD C2_DATA

680 P_0 402_50V7K

1 2

470 _0805_5%

+USB_CAM

1

C435

2

0308_Install all cap for EMI
request.

+3VS

R202

2.2K_0402_5%

DDC2 _CLK
DD C2_DATA

1 2

1 2

1

C434
680 P_0 402_50V7K

2

R203

2.2K_0402_5%

LVDS_A2- <11>
LVDS_A2+ <11>
LVDS_A1- <11>
LVDS_A1+ <11>
LVDS_A0- <11>
LVDS_A0+ <11>
LVDS_A CLK- <11>
LVDS_A CLK+ <11>

DMIC_DA T <28>

DMIC_CLK <28>

+5VS

INV _PW M <32>

BKOFF# <32>

DA C_ BRIG <32>
DDC2_CLK <11>

DDC2_DATA <11>

0.1U_0402_16V4Z

Must close JLVDS1pin 24、、、、26

DMIC_CLK
DM IC_DAT

1

1

C302

@

220 P_0 402_25V8J

2

C303

@

220 P_0 402_25V8J

2

C231

1

2

1

C232

0.1U_0402_16V4Z

2

12

R198

100 _04 02_5%

61

1M_0402_5%

2

2N7002DW-7-F_S OT363-6
Q8A

Limited Current < 1A

EN AVDD<11>

100 K_0402_5%

R201

12

Avoid Panel display garbage after power on.

@

L5 0_0 805_5%

1 2

L6

1 2

FBMA-L11-2 012 09-221LMA30T_0805

0308_Reserve L10 and install L11.

+5VALW+LCDVDD+L CDVDD

12

R199

3

Q8B
2N7002DW-7-F_S OT363-6

5

4

R200

100 K_0 402_5%

INVPWR_B+B+

C233

4.7U_0805_10V4Z

12

+L CDVDD

Q7

SI2301BDS-T1-E3_SOT23-3

1 3

1

2

D

C238

0.047U_0402_16V7K

01/03 Change to 0.047u to meet T1 timing

+3VS

S

G

C234

1

2

2

4.7U_0805_10V4Z

11/09 EMI reserver

B B

USB Camera

+5VALW +USB_CA M

PJP 6

@

PA D-OPEN 2x2m

10U_0805_6.3V6M

GPIO20<22>

A A

11/07 Change U42 to 3.9V LDO(Adjustable)
11/07 Change R1091 to 215K，，，，R1093 to 100K

C1392

R441 0_0402_5% @

PA D-OPEN 2x2m

2 1
1

2

1 2

11/08 Change C1391、、、、C1392 to 0805 size

+USB_CAM is +3.9VS, R1091:215K; R1093:100Kohm

5

PJP 5

R440

0_0 402_5%

+5VS

U42

1

IN

2

2 1

1 2

GND

3

SHDN

G916-39 0T1 UF_SOT23-5

BYP

OUT

5

4

+USB_CAM=1.25(1+R1091/R1093)

12

R1091
215 K_0 603_1%

1

R1093
100 K_0 402_1%

C1391
10U_0805_6.3V6M

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/07/26

Compal Secret Data

Deciphered Date

2

Title

Size Do cument Number Re v

Da te: Sheet o f

Compal Electronics, Inc.

LCD CONN.

Montev ina Blade UMA LA4101P

19 46Saturday, January 05, 2008

1

0.3

12

4

5

www.kythuatvitinh.com

+3VS

R272 8.2K_ 0402_5%

1 2

R273 8.2K_ 0402_5%

1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2

12

R274 8.2K_ 0402_5%
R275 8.2K_ 0402_5%

D D

C C

R276 8.2K_ 0402_5%
R277 8.2K_ 0402_5%
R278 8.2K_ 0402_5%
R279 8.2K_ 0402_5%

+3VS

R281 8.2K_ 0402_5%
R282 8.2K_ 0402_5%
R283 8.2K_ 0402_5%
R284 8.2K_ 0402_5%
R285 8.2K_ 0402_5%
R286 8.2K_ 0402_5%
R287 8.2K_ 0402_5%
R288 8.2K_ 0402_5%

R289 8.2K_ 0402_5%
R290 8.2K_ 0402_5%
R292 8.2K_ 0402_5%
R293 8.2K_ 0402_5%

PCI_ DEV SEL#
PCI_ STOP#
PC I_TRDY#
P CI_FRAME #
P CI_P LOCK #
PC I_ IR DY#
PC I_SERR#
PC I_PERR#

PC I_PIRQA #
PC I_PIRQB #
PC I_ PIRQC#
PC I_ PIRQD#
PC I_PIRQE #
PC I_PIRQF#
PC I_PIRQG#
PC I_ PIRQH#

P CI_RE Q0#
P CI_RE Q1#
P CI_RE Q2#
P CI_RE Q3#

4

U12B

D11

AD0

C8

AD1

PC I_PIRQA #
PC I_PIRQB #
PC I_ PIRQC#
PC I_ PIRQD#

D9

E12

E9
C9

E10

B7
C7
C5

G11

F8

F11

E7
A3
D2

F10

D5

D10

B3
F7
C3
F3
F4
C1
G7
H7
D1
G5
H6
G1
H3

J5

E1

J6

C4

ICH9-M ES_FCBGA676

PCI

AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

Interrupt I/F

PIRQA#
PIRQB#
PIRQC#
PIRQD#

REQ0#

GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55

C/BE0#
C/BE1#
C/BE2#
C/BE3#

IRDY#

PAR

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR#
STOP#
TRDY#

FRAME#

PLTRST#

PCICLK

PME#

PIRQE#/GPIO2

PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5

3

P CI_RE Q0#

F1

P CI_GNT0#

G4

P CI_RE Q1#

B6
A7

P CI_RE Q2#

F13
F12

P CI_RE Q3#

E6

P CI_GNT3#

F6
D8

B4
D6
A5

PC I_ IR DY#

D3
E3

PCI_ RST#

R1

PCI_ DEV SEL#

C6

PC I_PERR#

E4

P CI_P LOCK #

C2

PC I_SERR#

J4

PCI_ STOP#

A4

PC I_TRDY#

F5

P CI_FRAME #

D7

PLT_RST#

C14

CL K_ PCI_ICH

D4

PCI_ PME#

R2

PCI_RST# <31,32>

PC I_SERR# <32>

PLT_RST# <9,25,2 6,27>
CL K_ PCI_ICH <17>
PCI_ PME# <32>

3/28 PCI_PME# Remvoe 8.2k pull high +3VALW resistance.

PC I_PIRQE #

H4

PC I_PIRQF#

K6

PC I_PIRQG#

F2

PC I_ PIRQH#

G2

1 2

R291 0_0 402_5%

GS@

AC CEL _INT <24>

2

Place closely pin D4

CL K_ PCI_ICH

12

@

R280
10_ 0402_5%

1

@

C425

8.2P_0402_50V

2

1

B B

PCI_GNT3#

P CI_GNT3#

A A

Low= A16 swap override Enble
High= Default

R294

@

1 2

*

1K_0402_5%

5

A16 swap override Strap

Boot BIOS Strap

PCI_GNT0# SPI_CS#1

0

1

SPI_CS1#_R<22>

4

1

01

1

SPI_CS1#_R

P CI_GNT0#

Boot BIOS Location

SPI

PCI

LPC

*

+3VALW

@

R295

1 2

1K_0402_5%

R296

@

1 2

1K_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Do cument Number Re v

2

Da te: Sheet o f

Compal Electronics, Inc.

ICH9(1/4)-PCI/INT

Montev ina Blade UMA LA4101P

20 46Saturday, January 05, 2008

1

0.3

5

www.kythuatvitinh.com

4

3

2

1

+RTCV CC

HDA_ BIT CLK_CODE C<28>
HDA_B ITCLK_MDC<29>
HDA _BITCLK _NB<9>
HDA_ SYNC_CODEC<28>
HDA_ SYNC_MDC<29>

HDA_ SYNC_NB<9>
HDA_ RST #_CODEC<28,32>
HDA_RS T#_MDC<29>
HDA _RST#_NB<9>

SM _ INTRUDER#
LAN100_SLP
ICH_ INTVRMEN
IC H_S RTCRST#

C426

0.1U_0402_16V4Z

+RTC VCC

HDA_ SDIN0<28>
HDA_ SDIN1<29>
HDA_ SDIN2<9>

R307

1 2

20K _04 02_5%

HDA_ SDOUT_MDC<29>
HDA_ SDOUT_CODE C<28>
HDA_SDOUT _NB<9>

12

1

2

0_0 402_5%

1U_0603_10V4Z

R312 3 3_0402_5%
R313 3 3_0402_5%
R207 3 3_0402_5%
R316 3 3_0402_5%
R314 3 3_0402_5%
R208 3 3_0402_5%
R317 3 3_0402_5%
R318 3 3_0402_5%
R209 3 3_0402_5%

SATA_LED#<33>
SATA_RXN0_C<24>

SATA_RXP0_C<24>
SATA_TXN0<24>
SATA_TXP0<24>

SATA_RXP1_C<24>
SATA_TXN1<24>
SATA_TXP1<24>

@

R303

C427

12

@

R304

0_0 402_5%

1

2

SATA_TXN0
SATA_TXP0

SATA_TXN1
SATA_TXP1

1 2

R297 1M_0402_5%

1 2

R299 330K _0402_5%

1 2

R300 330K _0402_5%

1 2

D D

C C

R302 180K _0402_5%

P- HDD

B B

ICH8M Internal VR Enable Strap
(Internal VR for VccSus1.05, VccSus1.5,
VccCL1.5)

ICH_INTVRMEN

ICH8M LAN100 SLP Strap
(Internal VR for VccLAN1.05 and VccCL1.05)

ICH_LAN100_SLP Low = Internal VR Disabled

12

CLRP2
SHORT P ADS

+1.5VS

0.01U_0402_50V7K

C431

1 2

C433

1 2

0.01U_0402_50V7K

0.01U_0402_50V7K

C820

1 2

C821

1 2

0.01U_0402_50V7K

24.9_0402_1%

1 2

1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

R320 3 3_0402_5%
R321 3 3_0402_5%
R204 3 3_0402_5%

Low = Internal VR Disabled
High = Internal VR Enabled(Default)

High = Internal VR Enabled(Default)

ICH_RTCX1
ICH_RTCX2

ICH_RTCRS T#
IC H_S RTCRST#
SM _ INTRUDER#

ICH_ INTVRMEN
LAN100_SLP

R311

GLAN_COMP

HDA_B ITCLK
HDA_ S YNC

HDARST#
HDA_ SDIN0

HDA_ SDIN1
HDA_ SDIN2

HDA_SDOUT

T55PA D
T56PA D

SATA_LED#

SATA_TXN0_C
SATA_TXP0_C

SATA_TXN1_C

Mul ti@

SATA_TXP1_C

Mul ti@

U12A

C23

RTCX1

C24

RTCX2

A25

RTCRST#

F20

SRTCRST#

C22

INTRUDER#

B22

INTVRMEN

A22

LAN100_SLP

E25

GLAN_CLK

C13

LAN_RSTSYNC

F14

LAN_RXD0

G13

LAN_RXD1

D14

LAN_RXD2

D13

LAN_TXD_0

D12

LAN_TXD_1

E13

LAN_TXD_2

B10

GPIO56

B28

GLAN_COMPI

B27

GLAN_COMPO

AF6

HDA_BIT_CLK

AH4

HDA_SYNC

AE7

HDA_RST#

AF4

HDA_SDIN0

AG4

HDA_SDIN1

AH3

HDA_SDIN2

AE5

HDA_SDIN3

AG5

HDA_SDOUT

AG7

HDA_DOCK_EN#/GPIO33

AE8

HDA_DOCK_RST#/GPIO34

AG8

SATALED#

AJ16

SATA0RXN

AH16

SATA0RXP

AF17

SATA0TXN

AG17

SATA0TXP

AH13

SATA1RXN

AJ13

SATA1RXP

AG14

SATA1TXN

AF14

SATA1TXP

ICH9-M ES_FCBGA676

+3VS

GAT EA20

KB_RST#

H_DP RSTP#

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

FWH4/LFRAME#

RTC

LPCCPU

LAN / GLAN

IHDA

SATA

LDRQ0#

LDRQ1#/GPIO23

A20GATE

A20M#

DPRSTP#

DPSLP#

FERR#

CPUPWRGD

IGNNE#

INIT#

INTR

RCIN#

SMI#

STPCLK#

THRMTRIP#

TP12

SATA4RXN
SATA4RXP

SATA4TXN
SATA4TXP

SATA5RXN
SATA5RXP

SATA5TXN
SATA5TXP

SATA_CLKN
SATA_CLKP

SATARBIAS#

SATARBIAS

LPC_AD1

K4

LPC_AD2

L6

LPC_AD3

K2

LPC_FRA ME#

K3
J3

J1

GAT EA20

N7

H_A20M#

AJ27
AJ25

H_DP SLP #

AE23

R_ H_ FE RR#

AJ26

H_ PW RGOOD

AD22

H_ IG NNE#

AF25

H_ INIT#

AE22

H_ INTR

AG25

KB_RST#

L3

H_ NMI

AF23

NMI

H_SMI#

AF24

H_STPCLK#

AH27

TH RMTRIP _ICH#

AG26
AG27

AH11
AJ11

SATA_TXN4_C

AG12

SATA_TXP4_C

AF12

AH9
AJ9

SATA_TXN5_C

AE10

SATA_TXP5_C

AF10

CLK_PCIE_SATA#

AH18

CLK_PCIE_SATA

AJ18
AJ7

R322

AH7

1 2

24.9_0402_1%

LPC_AD0

K5

Within 500 mils

LP C_ AD[0 ..3] <26,31,32>

LPC_FRA ME# <2 6,31,32>

T54 PAD

GATEA20 <32>
H_A20M# <6>

R309

1 2

1 2

H_ PW RGOOD <6,7>
H_ IGNNE# <6>
H_ INIT# <6>

H_ INT R <6>

KB_RST# <32>

H_ NMI <6>
H_SMI# <6>

H_STPCLK# <6>
1 2

C428

12

C429

12

0.01U_0402_50V7K
C430

12

C432

12

0.01U_0402_50V7K

0_0 402_5%

56_ 0402_5%

R310

R319 54.9_0402_1%

0.01U_0402_50V7K

0.01U_0402_50V7K

ESATA@
ESATA@

SATA_TXN4
SATA_TXP4

SATA_TXN5
SATA_TXP5

H_DP SLP #

H_DP RSTP#H_DPRSTP _R#

H_ FERR#

3/28 add 56ohm

+V CCP

R298

1 2

10K _0402_5%
R301

1 2

10K _0402_5%

R305

@

1 2

56_ 0402_5%
R306

@

1 2

56_ 0402_5%

H_DP RSTP# <7,9,43>
H_DP SLP # <7>

wi th in 2" from R379

12

R315
56_ 0402_5%

H_THERMTRIP# <6,9>

placed within 2"
from ICH9M

SATA_RXN4_C <24>
SATA_RXP4_C <24>

SATA_TXN4 <24>

SATA_TXP4 <24>

SATA_RXN5_C <30>
SATA_RXP5_C <30>

SATA_TXN5 <30>

SATA_TXP5 <30>

CLK_PCIE_SATA# <17>
CLK_PCIE_SATA <17>SATA_RXN1_C<24>

+VCCP

+V CCP

R308
56_ 0402_5%

1 2

ODD

e-SATA

De -f eature disable

H_ FE RR# <6>

Add 12p on HDA_SDOUT and HDA_SDOUT

XOR CHAIN ENTRANCE STRAP:RSVD

+3VS

R325

@

1 2

R326

@

1 2

1K_0402_5%

1K_0402_5%

HDA_ S DOUT_CODE C

ICH_RS VD

ICH_RSV D <22>

ICH_RSVD HDA_SDOUT_CODEC

A A

0
0
1

0
1
0

1 1

5

C436

15P _04 02_50V8J

4

HDA_ SDOUT_MDC
HDA_ S DOUT_CODE C

C311 12P_0402_50V8J

1 2

C312 12P_0402_50V8J

1 2

0821 Change C528 and C516 to 15PF

R328

1 2

10M_0402_5%

1

2

Y 2

1 4
2 3

32.768KHZ_ 12.5P_MC-146

ICH_RTCX1

ICH_RTCX2

1

C437
15P _04 02_50V8J

2

HDA_B ITCLK

12

@

R327
10_ 0402_5%

1

1

@

C439
10P _04 02_25V8K

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

C438

2.2U_0603_6.3V4Z

2

R329

1 2

W=2 0mils

0_0 402_5%

Pl ac e near ICH9

2

W=20mils

D8

1

DAN202U_SC70

BATT1

@

+3VL+RTCV CC

2
3

W=2 0mils

Title

Size Do cument Number Re v

Cu st om

Da te: Sheet o f

BATT1.1

R330

1 2

1K_0402_5%

W= 20mils

Compal Electronics, Inc.

ICH9(2/4)_LAN,HD,IDE,LPC

Montev ina Blade UMA LA4101P

CR2032 RTC BATTERY

JBATT1

1

1

2

2

3

GND

4

GND

ACE S_8 5205-02001

C ONN@

21 46Saturday, January 05, 2008

1

0.3

5

www.kythuatvitinh.com

+3VS

1 2

R333 10K_0402_5%

1 2

R334 8.2K _0402_5%

1 2

R335 10K_0402_5%

1 2

R336 8.2 K_0 402_5%@

1 2

D D

C C

B B

A A

R337 10K_0402_5%@

1 2

R338 8.2 K_0 402_5%@

1 2

R341 8.2K _0402_5%

1 2

R344 8.2K _0402_5%

1 2

R356 8.2K _0402_5%

1 2

R349 8.2K _0402_5%

1 2

R350 8.2K _0402_5%

1 2

R351 8.2K _0402_5%

1 2

R352 8.2K _0402_5%

1 2

R357 8.2K _0402_5%

1 2

R358 8.2K _0402_5%

1 2

R359 10K_0402_5%

1 2

R361 8.2K _0402_5%

1 2

R362 8.2K _0402_5%

1 2

R365 10K_0402_5%@

+3VALW

1 2

R369 10K_0402_5%

1 2

R371 8.2K _0402_5%

1 2

R372 1K_0402_5%

1 2

R374 10K_0402_5%

1 2

R375 10K_0402_5%

1 2

R376 10K_0402_5%

1 2

R377 10K_0402_5%

1 2

R378 10K_0402_5%

1 2

R379 10K_0402_5%

1 2

R373 10K_0402_5%

1 2

R380 8.2K _0402_5%

1 2

R381 8.2K _0402_5%

+3VS +3VS

R745

@

10K _04 02_5%

1 2

DIS/UMA 17/14

R746
10K _04 02_5%

1 2

US B_OC#6
US B_OC#1
US B_OC#2
US B_OC#4

US B_OC#7
US B_OC#8
US B_OC#9
US B_OC#0

WXMIT_OFF#
US B_OC#5

USB _OC#10
USB _OC#11

SI RQ
PM _CLKRUN#
OCP#
THERM_SCI#
CL KREQ#_ C
PM_ BMBUSY#
EC _S CI#
CR _CP PE#
CR_WAKE#
GPIO18
HD DHALT_LED#
GPIO20
GPIO21
GPIO36
GPIO37
GPIO39
GPIO48
GPIO57

GPIO49

LINK ALERT#
ICH_LOW_BAT #
IC H_P CIE_ WAK E#
ICH_RI#
XDP _DBRESET#
S4_STATE#
ME_ EC_CLK1
ME_ EC_DATA1
GPIO10
E C_LID_OUT #
EC_SMI#
GPIO14

@

10K _04 02_5%

1 2

R748
10K _04 02_5%

1 2

RP27

4 5
3 6
2 7
1 8

10K _12 06_ 8P4R_5%

RP28

4 5
3 6
2 7
1 8

10K _12 06_ 8P4R_5%

RP29

4 5
3 6
2 7
1 8

10K _12 06_ 8P4R_5%

5

Board ID

R747

+3VALW

+3VS

01/03 Change HDCP ROM to +3VS

+3VALW

10K _0402_5%

H_STP_PCI#<17>
H_STP_CPU#<17>

CR_CPP E#<27>

EC _SCI#<32>
EC_SMI#<32>

+3VS

TV Tuner

11/17 Swap PCIE LAN and New card

WLAN

LAN

Card Reader

New Card

11/20 Add HDCP ROM for ICH9M

SPI_SB _CS#

1 2

R399 10 K_0 402_5%

1 2

R429 10 K_0 402_5%

1 2

R430 10 K_0 402_5%

R331 2.2K_ 0402_5%
R332 2.2K_ 0402_5%

ICH_SMB CLK<17,24,26>

ICH_SMBDATA<17,24,26>

+3VS

12

12

R340

@

R339

@

VGATE<17,43>

R366
Low -->default
High -->No boot

SPI_SI

SPI_SO_R

10K _0402_5%

R345 0_0 402_5%

R353

100 K_0402_5%

CR_WAK E#<27>

1 2

R364 8.2K_ 0402_5%

EXP_CPPE#<26>

+3VS

SB_SPKR<28>

SPI_CLK<3 1,32>

SPI_SB _CS#<31>

SPI_CS1#_R<20>

SPI_SI<31>

SPI_SO_R<31>

4

1 2
1 2

T57PA D

XDP _DBRESET#<6>

PM_ BMBUSY#<9>

EC_LID_OUT#<32>

1 2

ICH_PCIE_W AKE#<25,26>
SI RQ<32>
THERM_SCI#<32>

1 2

R225 0_0 402_5%

1 2

R226 0_0 402_5%@

1 2

R366 1K_0402_5% @

PCIE _RX N1<26>
PCIE _RXP1<26>
PCIE _TXN1<26>

PCIE_TXP1<26>

PCIE _RX N3<26>
PCIE _RXP3<26>
PCIE _TXN3<26>

PCIE_TXP3<26>

GLAN_RXN<25>
GLAN_RXP<25>
GLAN_TXN<25>

GLAN_TXP<25>

PCIE _RX N5<27>
PCIE _RXP5<27>
PCIE _TXN5<27>

PCIE_TXP5<27>

PCIE _RX N4<26>
PCIE _RXP4<26>
PCIE _TXN4<26>

PCIE_TXP4<26>

SPI_CLK
SPI_SB _CS#

SPI_SI
SPI_SO_R

BT_OFF<30>
WXMIT_OFF#<26>

T59PA D

OCP #<6>

GPIO20<19>

CL KRE Q#_C<17>

R739

1 2

0_0 402_5%

1 2

MCH_ICH_SYNC#<9>

ICH_RSV D<21>

C445 0.1U_0402_16V4Z
C444 0.1U_0402_16V4Z

2Mi niC@
2Mi niC@

C448 0.1U_0402_16V4Z
C449 0.1U_0402_16V4Z

C452 0.1U_0 402_16V4Z
C453 0.1U_0 402_16V4Z

C816 0.1U_0402_16V4Z
C817 0.1U_0402_16V4Z

C450 0.1U_0402_16V4Z
C451 0.1U_0402_16V4Z

Ne wC@
Ne wC@

R383 0_04 02_5%

4

IC H_S MBCLK
ICH_SMBDATA
LINK ALERT#
ME_ EC_CLK1
ME_ EC_DATA1

ICH_RI#
SUS _STAT#

XDP _DBRESET#
PM_ BMBUSY#
E C_LID_OUT #
H_STP_PCI#

R_STP_CPU#
PM _CLKRUN#
IC H_P CIE_ WAK E#

SI RQ
THERM_SCI#

VGATE

OCP#
CR _CP PE#
EC_SCI#_SB
EC_SMI#
E C_SCI#_GPIO1 2

T46PA D

17/14
GPIO18
GPIO20
CR_WAKE#
DIS/UMA

T47PA D

CL KREQ#_ C
GPIO38
GPIO39
GPIO48
GPIO49
GPIO57

SB_SPKR
MCH_ICH_SYNC#
ICH_RS VD

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

R417 15_0402_5%

1 2

R416 15_0402_5%

1 2

1 2

12

Within 500 mils

R384

22.6_0402_1%

3

U1 2C

G16

SMBCLK

A13

SMBDATA

E17

LINKALERT#/GPIO60/CLGPIO4

C17

SMLINK0

B18

SMLINK1

F19

RI#

R4

SUS_STAT#/LPCPD#

G19

SYS_RESET#

M6

PMSYNC#/GPIO0

A17

SMBALERT#/GPIO11

A14

STP_PCI#

E19

STP_CPU#

L4

CLKRUN#

E20

WAKE#

M5

SERIRQ

AJ23

THRM#

D21

VRMPWRGD

A20

TP11

AG19

GPIO1

AH21

GPIO6

AG21

GPIO7

A21

GPIO8

C12

GPIO12

C21

GPIO13

AE18

GPIO17

K1

GPIO18

AF8

GPIO20

AJ22

SCLOCK/GPIO22

A9

GPIO27

D19

GPIO28

L1

SATACLKREQ#/GPIO35

AE19

SLOAD/GPIO38

AG22

SDATAOUT0/GPIO39

AF21

SDATAOUT1/GPIO48

AH24

GPIO49

A8

GPIO57/CLGPIO5

M7

SPKR

AJ24

MCH_SYNC#

B21

TP3

AH20

TP8

AJ20

TP9

AJ21

TP10

ICH9-M ES_FCBGA676

PCIE _RX N1
PCIE _RX P1
PCIE _C_TXN1
PCIE _C_TXP1

PCIE _RX N3
PCIE _RX P3
PCIE _C_TXN3
PCIE _C_TXP3

GLAN_RXN
GLAN_RXP
GLAN_TX N_C
GLAN_TXP_C

PCIE _RX N5
PCIE _RX P5
PCIE _C_TXN5
PCIE _C_TXP5

PCIE _RX N4
PCIE _RX P4
PCIE _C_TXN4
PCIE _C_TXP4

SPI_CS1#_R

US B_OC#0
US B_OC#1
US B_OC#2
WXMIT_OFF#
US B_OC#4
US B_OC#5
US B_OC#6
US B_OC#7
US B_OC#8
US B_OC#9
USB _OC#10
USB _OC#11

US BRB IAS

SMB

U1 2D

N29

PERN1

N28

PERP1

P27

PETN1

P26

PETP1

L29

PERN2

L28

PERP2

M27

PETN2

M26

PETP2

J29

PERN3

J28

PERP3

K27

PETN3

K26

PETP3

G29

PERN4

G28

PERP4

H27

PETN4

H26

PETP4

E29

PERN5

E28

PERP5

F27

PETN5

F26

PETP5

C29

PERN6/GLAN_RXN

C28

PERP6/GLAN_RXP

D27

PETN6/GLAN_TXN

D26

PETP6/GLAN_TXP

D23

SPI_CLK

D24

SPI_CS0#

F23

SPI_CS1#GPIO58/CLGPIO6

D25

SPI_MOSI

E23

SPI_MISO

N4

OC0#/GPIO59

N5

OC1#/GPIO40

N6

OC2#/GPIO41

P6

OC3#/GPIO42

M1

OC4#/GPIO43

N2

OC5#/GPIO29

M4

OC6#/GPIO30

M3

OC7#/GPIO31

N3

OC8#/GPIO44

N1

OC9#/GPIO45

P5

OC10#/GPIO46

P3

OC11#/GPIO47

AG2

USBRBIAS

AG1

USBRBIAS#

ICH9-M ES_FCBGA676

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

SATA0GP/GPIO21
SATA1GP/GPIO19
SATA4GP/GPIO36
SATA5GP/GPIO37

SATA

GPIO

clocks

SYS / GPIOGPIOMISC

Power MGT

GPIO10/SUS_PWR_ACK

Controller Link

PCI - Express

SPI

USB

CLK14

CLK48
SUSCLK
SLP_S3#

SLP_S4#
SLP_S5#

S4_STATE#/GPIO26

PWROK

DPRSLPVR/GPIO16

BATLOW#
PWRBTN#
LAN_RST#

RSMRST#

CK_PWRGD

CLPWROK

SLP_M#

CL_CLK0
CL_CLK1

CL_DATA0
CL_DATA1

CL_VREF0
CL_VREF1

CL_RST0#
CL_RST1#

MEM_LED/GPIO24

GPIO14/AC_PRESENT

WOL_EN/GPIO9

DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP

DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP

DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP

DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP

DMI_CLKN
DMI_CLKP

DMI_ZCOMP

Direct Media Interface

DMI_IRCOMP

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N

USBP9P
USBP10N
USBP10P
USBP11N
USBP11P

2007/08/28 2006/03/10

GPIO21

AH23

HD DHALT_LED#

AF19

GPIO36

AE21

GPIO37

AD20

CL K_14M_ICH

H1

CL K_48M_ICH

AF3

ICH_ SUS CLK

P1

SLP_S3#

C16

SLP_S4#

E16

SLP_S5#

G17

S4_STATE#

C10

PM_ PWROK

G20

R348 0_04 02_5%

M2

ICH_LOW_BAT #

B13

PWRBTN_ OUT#

R3
D20

R_EC_RSMRST #

D22

CK _P WRGD

R5

M_PWROK

R6
B16

CL _CLK0

F24
B19

CL_DATA0

F22
C19

CL _VREF0_ICH

C25

CL _VREF1_ICH

A19

CL_RST#

F21
D18

XMIT_OFF

A16

GPIO10

C18

GPIO14

C11

LAN_WOL_EN

C20

DMI_RXN0

V27

DMI_RXP0

V26

DMI_TXN0

U29

DMI_TXP0

U28

DMI_RXN1

Y27

DMI_RXP1

Y26

DMI_TXN1

W29

DMI_TXP1

W28

DMI_RXN2

AB27

DMI_RXP2

AB26

DMI_TXN2

AA29

DMI_TXP2

AA28

DMI_RXN3

AD27

DMI_RXP3

AD26

DMI_TXN3

AC29

DMI_TXP3

AC28

CL K _PCIE_ICH#

T26

CL K_ PCIE_ICH

T25
AF29

DMI_ IRCOMP

AF28

USB 20_N0

AC5

USB 20_P0

AC4

USB 20_N1

AD3

USB 20_P1

AD2

USB 20_N2

AC1

USB 20_P2

AC2

USB 20_N3

AA5

USB 20_P3

AA4

USB 20_N4

AB2

USB 20_P4

AB3

USB 20_N5

AA1

USB 20_P5

AA2

USB 20_N6

W5

USB 20_P6

W4

USB 20_N7

Y3

USB 20_P7

Y2

USB 20_N8

W1

USB 20_P8

W2

USB 20_N9

V2

USB 20_P9

V3
U5
U4
U1
U2

Compal Secret Data

1 2

Deciphered Date

11/09 Change Gsensor control from SB

T58 P AD

R370

12

100 K_0 402_5%

DMI_RXN0 <9>
DMI_RXP0 <9>
DMI_TXN0 <9>
DMI_TXP0 <9>

DMI_RXN1 <9>
DMI_RXP1 <9>
DMI_TXN1 <9>
DMI_TXP1 <9>

DMI_RXN2 <9>
DMI_RXP2 <9>
DMI_TXN2 <9>
DMI_TXP2 <9>

DMI_RXN3 <9>
DMI_RXP3 <9>
DMI_TXN3 <9>
DMI_TXP3 <9>

CL K_ PCIE _ICH# <17>
CL K_ PCIE_ICH <17>

R382 24.9_0402_1%

1 2

USB 20_N0 <30>
USB 20_P0 <30>
USB 20_N1 <30>
USB 20_P1 <30>
USB 20_N2 <30>
USB 20_P2 <30>
USB 20_N3 <34>
USB 20_P3 <34>
USB 20_N4 <19>
USB 20_P4 <19>
USB 20_N5 <26>
USB 20_P5 <26>
USB 20_N6 <30>
USB 20_P6 <30>
USB 20_N7 <30>
USB 20_P7 <30>
USB 20_N8 <26>
USB 20_P8 <26>
USB 20_N9 <26>
USB 20_P9 <26>

2

HDDHALT_LED# <33>

CLK_14M_ICH <17>
CLK_48M_ICH <17>

SLP_S3# <32>
SLP_S4# <32>
SLP_S5# <32>

PM_ PWROK <9,32>

PWRBTN_ OUT# <32>

CK _P WRGD <17>
M_PWROK <9,32>

CL_CLK0 <9>

CL_DATA0 <9>

CL_RST# <9>

XMIT_OFF <26>

DP RSL PVR <9,43>

R_EC_RSMRST # <39>

R354 100_0402_5%

1 2

R355 10K_0402_5%

1 2

+3VALW

2

Place closely pin
AF3

R346 10 K_0 402_5%

1 2

11/17 Add +3VALW GD to EC_RSMRST#
to fix Battery mode can't boot issue

EC_RSMRST# <32>

12

1

C442

2

0.1U_0402_16V4Z

12

1

C443

2

0.1U_0402_16V4Z

Within 500 mils

+1.5 VS

USB-0 Right side
USB-1 Right side
USB-2 Left side(with ESATA)
USB-3 Dock
USB-4 Camera
USB-5 WLAN
USB-6 Bluetooth
USB-7 Finger Printer
USB-8 MiniCard(WWAN/TV)
USB-9 Express card

Title

ICH9(3/4)_DMI,USB,GPIO,PCIE

Size Do cument Number Re v

Cu st om

Montev ina Blade UMA LA4101P

Da te: Sheet o f

1

Place closely pin

+3VS

+3VALW

H1

12

@

10_ 0402_5%

1

@

4.7P_0402_50V8C

2

CL K_48M_ICH

12

R342

@

10_ 0402_5%

1

C440

@

4.7P_0402_50V8C

2

1 2

3.24K_0402_1%

R363
453 _0402_1%

NA lead free

R368
453 _0402_1%

R360

R367

1 2

3.24K_0402_1%

Compal Electronics, Inc.

1

CL K_14M_ICH

R343

C441

0.3

22 46Saturday, January 05, 2008

5

www.kythuatvitinh.com

+RTC VCC

20 mils

1

C454

2

0.1U_0402_16V4Z

40 mils

1

+

C459

2

10U_0805_10V4Z

220 U_D2_4VM

1

C477

2

1U_0603_10V4Z

1

C483

2

1

C487

2

10U_0805_10V4Z

2.2U_0603_6.3V4Z

1

2

0.1U_0402_16V4Z

1

2

10U_0805_10V4Z

+1.5 VS

1

C488

2

C462

R387

1 2

+5VS +3VS

R386

100 _0402_5%

R388

10_ 0402_5%

+1.5 VS

031 6 change design

+1.5 VS

12

+3VALW+5V ALW

12

R389

1 2

CHB1 608 U301_0603

+3VS

C485

0.1U_0402_16V4Z

CHB1 608 U301_0603

21

D9
CH75 1H-4 0_S C76

ICH_V5 REF_RUN

20 mils

1

C465

0.1U_0402_10V6K

2

21

D10
CH75 1H-4 0_S C76

ICH_V5RE F_SUS

20 mils

1

C472

0.1U_0402_10V6K

2

C476

+1.5 VS

0.1U_0402_16V4Z

1

R390 CHB 1608U30 1_0603

1 2

+1.5VS

2

C458

1

2

D D

C C

B B

A A

ICH_V5 REF_RUN

ICH_V5RE F_SUS

10U_0805_10V4Z

1

C460

C456

2

2.2U_0603_6.3V4Z

+1.5 VS

C478

1U_0603_10V4Z

+1.5 VS

C481

1U_0603_10V4Z

C484

0.1U_0402_16V4Z

V CC_LAN1_ 05_ INT_ ICH_1

T69

V CC_LAN1_ 05_ INT_ ICH_2

T70

R391

1 2

+1.5 VS

CHB1 608 U301_0603

031 6 change design

1

2

1

2

1

2

1

2

C489

4.7U_0805_10V4Z

1

+3VS

2

5

4

U12F

A23

VCCRTC

A6

V5REF

AE1

V5REF_SUS

AA24

VCC1_5_B[01]

AA25

VCC1_5_B[02]

AB24

VCC1_5_B[03]

AB25

VCC1_5_B[04]

AC24

VCC1_5_B[05]

AC25

VCC1_5_B[06]

AD24

VCC1_5_B[07]

AD25

VCC1_5_B[08]

AE25

VCC1_5_B[09]

AE26

VCC1_5_B[10]

AE27

VCC1_5_B[11]

AE28

VCC1_5_B[12]

AE29

VCC1_5_B[13]

F25

VCC1_5_B[14]

G25

VCC1_5_B[15]

H24

VCC1_5_B[16]

H25

VCC1_5_B[17]

J24

VCC1_5_B[18]

J25

VCC1_5_B[19]

K24

VCC1_5_B[20]

K25

VCC1_5_B[21]

L23

VCC1_5_B[22]

L24

VCC1_5_B[23]

L25

VCC1_5_B[24]

M24

VCC1_5_B[25]

M25

VCC1_5_B[26]

N23

VCC1_5_B[27]

N24

VCC1_5_B[28]

N25

VCC1_5_B[29]

P24

VCC1_5_B[30]

P25

VCC1_5_B[31]

R24

VCC1_5_B[32]

R25

VCC1_5_B[33]

R26

VCC1_5_B[34]

R27

VCC1_5_B[35]

T24

VCC1_5_B[36]

T27

VCC1_5_B[37]

T28

VCC1_5_B[38]

T29

VCC1_5_B[39]

U24

VCC1_5_B[40]

U25

VCC1_5_B[41]

V24

VCC1_5_B[42]

V25

VCC1_5_B[43]

U23

VCC1_5_B[44]

W24

VCC1_5_B[45]

W25

VCC1_5_B[46]

K23

VCC1_5_B[47]

Y24

VCC1_5_B[48]

Y25

VCC1_5_B[49]

AJ19

VCCSATAPLL

AC16

VCC1_5_A[01]

AD15

VCC1_5_A[02]

AD16

VCC1_5_A[03]

AE15

VCC1_5_A[04]

AF15

VCC1_5_A[05]

AG15

VCC1_5_A[06]

AH15

VCC1_5_A[07]

AJ15

VCC1_5_A[08]

AC11

VCC1_5_A[09]

AD11

VCC1_5_A[10]

AE11

VCC1_5_A[11]

AF11

VCC1_5_A[12]

AG10

VCC1_5_A[13]

AG11

VCC1_5_A[14]

AH10

VCC1_5_A[15]

AJ10

VCC1_5_A[16]

AC9

VCC1_5_A[17]

AC18

VCC1_5_A[18]

AC19

VCC1_5_A[19]

AC21

VCC1_5_A[20]

G10

VCC1_5_A[21]

G9

VCC1_5_A[22]

11mA

AC12

VCC1_5_A[23]

AC13

VCC1_5_A[24]

AC14

VCC1_5_A[25]

AJ5

VCCUSBPLL

AA7

VCC1_5_A[26]

AB6

VCC1_5_A[27]

AB7

VCC1_5_A[28]

AC6

VCC1_5_A[29]

AC7

VCC1_5_A[30]

A10

VCCLAN1_05[1]

A11

VCCLAN1_05[2]

A12

VCCLAN3_3[1]

B12

VCCLAN3_3[2]

23mA

A27

VCCGLANPLL

80mA

D28

VCCGLAN1_5[1]

D29

VCCGLAN1_5[2]

E26

VCCGLAN1_5[3]

E27

VCCGLAN1_5[4]

1mA

A26

VCCGLAN3_3

ICH9-M ES_FCBGA676

4

11mA

G3 : 6uA
2mA

2mA
64 6mA

47mA

1342mA

ARX

212mA

ATX

USB CORE

16 34mA

VCCA3GP

GLAN POWER

CORE

23mA

48mA

2mA

VCCP_CORE

PCI

11mA

VC CPSUS

VCCPUSB

VCC1_05[01]
VCC1_05[02]
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]
VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC1_05[20]
VCC1_05[21]
VCC1_05[22]
VCC1_05[23]
VCC1_05[24]
VCC1_05[25]
VCC1_05[26]

VCCDMIPLL
VCC_DMI[1]

VCC_DMI[2]

V_CPU_IO[1]
V_CPU_IO[2]

VCC3_3[01]
VCC3_3[02]
VCC3_3[07]

VCC3_3[03]
VCC3_3[04]
VCC3_3[05]
VCC3_3[06]

308mA

VCC3_3[08]
VCC3_3[09]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]
VCC3_3[14]

11mA

VCCSUSHDA

VCCSUS1_05[1]
VCCSUS1_05[2]

VCCSUS1_5[1]
VCCSUS1_5[2]

VCCSUS3_3[01]
VCCSUS3_3[02]
VCCSUS3_3[03]
VCCSUS3_3[04]

VCCSUS3_3[05]

VCCSUS3_3[06]
VCCSUS3_3[07]
VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]

VCCCL1_05

VCCCL1_5

19 /73/73mA19 /78/78mA

VCCCL3_3[1]
VCCCL3_3[2]

3

+V CCP

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

VC CSUS1 _5_ ICH_1
VC CSUS1 _5_ ICH_2

0.1U_0402_16V4Z

VC CC L1_05_ICH

+3VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

0.1U_0402_16V4Z

1

1

C457

C455

2

2

1

C464

2

+3VS

0.1U_0402_16V4Z

1 2

12

0.1U_0402_16V4Z

R385

1 2

CHB1 608 U301_0603

1

C463
10U_0805_10V4Z

2

+VCCP

0.1U_0402_16V4Z

1

C470

2

R212

@

0_0 402_5%

1 2

R741
150 _04 02_1%

Compal Secret Data

1

C471

2

R740
180 _04 02_1%

+1.5VALW

Deciphered Date

+1.5VS

0.01U_0402_16V7K

1

C461

2

22U_0805_6 .3VAM

0.1U_0402_16V4Z

1

C469

2

+3VS

C473

1

C475

T65

2

T66

T67
T68

+3VALW

1

C479

2

+3VALW

1

2

T71

@

C486
1U_0603_10V4Z

+1.5 VS

C480

C482

4.7U_0603_6.3V6M

1

2

1

2

1

2

2007/08/28 2006/03/10

+V CCP

4.7U_0603_6.3V6M

+3VALW

C466

1

2

VCCHDA

A15
B15
C15
D15
E15
F15
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

R29
W23

Y23
AB23

AC23
AG29

AJ6
AC10

AD19
AF20
AG24
AC20

B9
F9
G3
G6
J2
J7
K7

AJ4
AJ3

AC8
F17

AD8
F18

A18
D16
D17
E22

AF1

T1
T2
T3
T4
T5
T6
U6
U7
V6
V7
W6
W7
Y6
Y7
T7

G22
G23

A24
B24

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C467

1

2

(D MI)

0.1U_0402_16V4Z

2

U12E

AA26

VSS[001]

AA27

VSS[002]

AA3

VSS[003]

AA6

VSS[004]

AB1

VSS[005]

AA23

VSS[006]

AB28

VSS[007]

AB29

VSS[008]

AB4

VSS[009]

AB5

VSS[010]

AC17

VSS[011]

AC26

VSS[012]

AC27

VSS[013]

AC3

VSS[014]

AD1

VSS[015]

AD10

VSS[016]

AD12

VSS[017]

AD13

VSS[018]

AD14

VSS[019]

AD17

VSS[020]

AD18

VSS[021]

AD21

VSS[022]

AD28

VSS[023]

AD29

VSS[024]

AD4

VSS[025]

AD5

VSS[026]

AD6

VSS[027]

AD7

VSS[028]

AD9

VSS[029]

AE12

VSS[030]

AE13

VSS[031]

AE14

VSS[032]

AE16

VSS[033]

AE17

VSS[034]

AE2

VSS[035]

AE20

VSS[036]

AE24

VSS[037]

AE3

VSS[038]

C468

1

2

+1.5 VS

1

C474

2

Cu st om

AE4

VSS[039]

AE6

VSS[040]

AE9

VSS[041]

AF13

VSS[042]

AF16

VSS[043]

AF18

VSS[044]

AF22

VSS[045]

AH26

VSS[046]

AF26

VSS[047]

AF27

VSS[048]

AF5

VSS[049]

AF7

VSS[050]

AF9

VSS[051]

AG13

VSS[052]

AG16

VSS[053]

AG18

VSS[054]

AG20

VSS[055]

AG23

VSS[056]

AG3

VSS[057]

AG6

VSS[058]

AG9

VSS[059]

AH12

VSS[060]

AH14

VSS[061]

AH17

VSS[062]

AH19

VSS[063]

AH2

VSS[064]

AH22

VSS[065]

AH25

VSS[066]

AH28

VSS[067]

AH5

VSS[068]

AH8

VSS[069]

AJ12

VSS[070]

AJ14

VSS[071]

AJ17

VSS[072]

AJ8

VSS[073]

B11

VSS[074]

B14

VSS[075]

B17

VSS[076]

B2

VSS[077]

B20

VSS[078]

B23

VSS[079]

B5

VSS[080]

B8

VSS[081]

C26

VSS[082]

C27

VSS[083]

E11

VSS[084]

E14

VSS[085]

E18

VSS[086]

E2

VSS[087]

E21

VSS[088]

E24

VSS[089]

E5

VSS[090]

E8

VSS[091]

F16

VSS[092]

F28

VSS[093]

F29

VSS[094]

G12

VSS[095]

G14

VSS[096]

G18

VSS[097]

G21

VSS[098]

G24

VSS[099]

G26

VSS[100]

G27

VSS[101]

G8

VSS[102]

H2

VSS[103]

H23

VSS[104]

H28

VSS[105]

H29

VSS[106]

ICH9-M E S_F CBGA676

Title

Size Do cument Number Re v

Da te: Sheet o f

Compal Electronics, Inc.

ICH9(4/4)_POWER&GND

Montev ina Blade UMA LA4101P

1

VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]

VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]
VSS_NCTF[05]
VSS_NCTF[06]
VSS_NCTF[07]
VSS_NCTF[08]
VSS_NCTF[09]
VSS_NCTF[10]
VSS_NCTF[11]
VSS_NCTF[12]

1

H5
J23
J26
J27
AC22
K28
K29
L13
L15
L2
L26
L27
L5
L7
M12
M13
M14
M15
M16
M17
M23
M28
M29
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
P12
P13
P14
P15
P16
P17
P2
P23
P28
P29
P4
P7
R11
R12
R13
R14
R15
R16
R17
R18
R28
T12
T13
T14
T15
T16
T17
T23
B26
U12
U13
U14
U15
U16
U17
AD23
U26
U27
U3
V1
V13
V15
V23
V28
V29
V4
V5
W26
W27
W3
Y1
Y28
Y29
Y4
Y5
AG28
AH6
AF2
B25

A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29

23 46Saturday, January 05, 2008

0.3

5

www.kythuatvitinh.com

4

3

2

1

C713

GS@

ICH_SMBDATA

R570

GS@

0_0 402_5%

1 2

+3VS_ACL

1

1

C714

2

2

0.1U_0402_16V4Z

10U_0805_6 .3V6M

GS@

ICH_SMBCLK <17,22,26>

0011101b

ICH_SMBDATA <1 7,22,26>

ACCEL_ INT <20>

Pleace near HDD CONN (JP3)

HDD Connector

JP 3

1

GND

2

A+

3

A-

D D

C C

GND

B-

B+

GND

V33
V33

V33
GND
GND
GND

V5
V5
V5

GND

Reserved

GND

V12

V12

V12

SUY IN_127072FR022G523 _RV

C ONN@

CD-ROM Connector

JP 5

GND

A+

A-

GND

B-

B+

GND

DP

V5
V5

MD
GND
GND

SUY IN_127382FR013GX09ZR

C ONN@

0.01U_0402_16V7K

4

SATA_RXN0

5

SATA_RXP0 SATA_RXP0_C

6

0.01U_0402_16V7K

7

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

13
12
11
10
9
8
7

6
5
4
3
2
1

+3VS_HDD1

+5VS

0.01U_0402_16V7K

SATA_RXN4
SATA_RXP4

0.01U_0402_16V7K

+5VS

SATA_TXP0
SATA_TXN0

SATA_RXN0_C

C494

12

C495

12

Near CONN side.

SATA_TXP4
SATA_TXN4

SATA_RXN4_C

C510

12

SATA_RXP4_C

C511

12

Near CONN side.

SATA_TXP0 <21>
SATA_TXN0 <21>

SATA_RXN0_C <21>

SATA_RXP0_C <21>

SATA_TXP4 <21>

SATA_TXN4 <21>

SATA_RXN4_C <21>

SATA_RXP4_C <21>

+5VS

1

C490

2

Pleace near HDD CONN

R392

@

1 2

+3VS

0_0 805_5%

+5VS

1

C512

2

1

C491

C492

2

10U_0805_10V4Z

0.1U_0402_16V4Z

1

C497

@

C496

@

2

100 0P_ 0402_50V7K

1

1

C493

2

2

0.1U_0402_16V4Z

+3VS_HDD1

1

1

C498

@

2

2

0.1U_0402_16V4Z

Placea caps. near ODD CONN.

1

C513

C514

2

1U_0603_10V4Z

0.1U_0402_16V4Z

1

1

C515

2

2

10U_0805_10V4Z

D23

GS@

0.1U_0402_16V4Z

2 1

CH75 1H-4 0PT _SOD323-2

VDDIO absolute man
rating is VDD+0.1

1U_0603_10V4Z

10U_0805_10V4Z

+3VS_A CL_IO

GS@

+3VS_ACL

+3VS_ACL+3VS +3VS_A CL_IO

GS@

1 2

U29

1

R568

0_0 402_5%

1 2

Vdd_IO

2

GND

3

Reserved

4

GND

5

GND

6

Vdd

R569 10K _0402_5%GS@

Must be placed in the center of the system.

R564

0_0 603_5%

14

GS@

LIS302DLTR_LGA 14_3x5

7

12

IC H_S MBCLK

SCL / SPC

SDA / SDI / SDO

Reserved

CS

SDO

GND
INT 2
INT 1

13
12
11
10
9
8

ACCELEROMETER (Bosch)

ACCELEROMETER (ST)

B B

U14

@

Multi Bay

+5VS

A A

16

VCC5

15

VCC5

14

VCC5

13

VCC3

12

VCC3

11

VCC3

10

GND

9

GND

18

GND

TYCO_20 23087

C ONN@

GND

GND
RX+

GND
GND

GND

JP12

TX+

RX-

1

SATA_TXP1

2

SATA_TXN1

3

TX-

4

SATA_RXN1 SATA _RXN1_C

5

SATA_RXP1 SATA_RXP1_C

6
7
8

17

SATA_TXP1 <21>

SATA_TXN1 <21>

C822 0.01U_0402_16V7K

12

C823 0.01U_0402_16V7K

12
Mul ti@
Mul ti@

SATA_RXN1_C <21>
SATA_RXP1_C <21>

5

4

+5VS

Placea caps. near Multi Bay CONN.

C297

Mul ti@

1

2

1

C298

Mul ti@

0.1U_0402_16V4Z

ZZ Z2

PCB-MB

1

C299

Mul ti@

2

2

1U_0603_10V4Z

10U_0805_10V4Z

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C300

Mul ti@

1

2

10U_0805_10V4Z

2007/08/28 2006/03/10

3

+3VS_ACL

Compal Secret Data

R571 1 0K_ 0402_5%@

Deciphered Date

1 2

ICH_SMBDATA

IC H_S MBCLK

A CCEL _INT

G_CS#

2

BMA150

4

INT

5

CSB

6

SCK

7

SDO

8

SDI

BMA 150 _LGA12

9

VDDIO

VDD

GND

RSVD
RSVD

RSVD
RSVD

Title

Size Do cument Number Re v

Cu st om

Da te: Sheet o f

+3VS_A CL_IO

2

+3VS_ACL

3
1

10

11
12

Compal Electronics, Inc.

HDD & CDROM

Montev ina Blade UMA LA4101P

24 46Saturday, January 05, 2008

1

0.3

5

www.kythuatvitinh.com

4

3

2

1

LAN Conn.

JR J45

13

Yellow LED+

14

Yellow LED-

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

11

Green LED+

12

Green LED-

FOX _JM3611 3-P1122-7F

C ONN@

1

C271

0.1U_0402_16V4Z

2

RJ45_MIDI0+ <34>

1 2
1 2

2

1

RJ45_MIDI0- <34>

RJ45_MIDI1+ <34>
RJ45_MIDI1- <34>

C256

0.1U_0402_16V4Z

C257 0 .01U_0603_100V7-M
C258 0 .01U_0603_100V7-M

+3V_LAN

SHLD1

DETECT PIN1

DETCET PIN2

SHLD1

1

C272

4.7U_0805_10V4Z

2

RJ 45_ CT0_C
RJ 45_ CT1_C

+3V_LAN

16
9

10
15

LA NG ND

R693

75_ 0402_1%

1 2
1 2

R694

75_ 0402_1%

RJ 45 _GND

C259

100 0P_ 1206_2KV7K

1

2

RJ 45_MIDI0+
RJ 45_MIDI0-

RJ45_CT0

RJ45_CT1
RJ 45_MIDI1+
RJ 45_MIDI1-

12

12

RJ 45_MIDI1-

RJ 45_MIDI1+

RJ 45_MIDI0-

RJ 45_MIDI0+

12

GND

NC
NC

VCC

+3V_LAN

+3V_LAN

5
6
7
8

Place Close to Chip

C240 0.1U_0402_16V7K

12

C241 0.1U_0402_16V7K

12

GLAN_TXP<22>

GLAN_TXN<22>

CLK_PCIE_LAN<17>

CLK_PCIE_LAN#<17>

CLKREQ#_9<17>

PLT_RST#<9,20,26,27>

R688 2.49K _0402_1%

ICH_PCIE_W AKE#<2 2,26>

+LAN_V DD12

2

C251

C252

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+3VS

12

R215
1K_0402_1%

R216
15K _0402_5%

GLAN_RXP<22>
GLAN_RXN<22>

ISOLATEB

Check??

LA N_POWE R_OF F<32>

D D

C C

B B

Close to Pin10,13,30,36

2

2

C250

C249

1

1

0.1U_0402_16V4Z

PCIE _PTX_IRX_P2
PCIE _PTX_IRX_N2

1 2

ISOLATEB
LAN_X1

LAN_X2

1 2

R218 10K _04 02_5%

2

1

0.1U_0402_16V4Z

U44

20

HSOP

21

HSON

15

HSIP

16

HSIN

17

REFCLK_P

18

REFCLK_M

25

CLKREQB

27

PERSTB

46

RSET

26

LANWAKEB

28

ISOLATEB

41

CKXTAL1

42

CKXTAL2

23

NC

24

NC

7

GND

14

GND

31

GND

47

GND

22

GNDTX

RTL8102EL-GR_LQFP48_7X7

PJP 4

C255

1 2

PA D-OP EN 4 x4m

S

2

G

@

2

1

+3VALW

0.1U_0402_16V4Z

Close to Pin1,37,29

2

C253

1

0.1U_0402_16V4Z

RTL8102EL

D

Q19
SI2301BDS-T1-E3_SOT23-3

C254

40 mils

13

+3V_LAN

2

C261

1

0.1U_0402_16V4Z

LED3/EEDO

LED2/EEDI/AUX

LED1/EESK

EECS

LED0

MDIP0
MDIN0
MDIP1
MDIN1

VCTRL12A

VDDTX
DVDD12
DVDD12
DVDD12
DVDD12

VCTRL12D

VDD33

VDD33

AVDD33

+3V_LAN

2

1

0.1U_0402_16V4Z

NC
NC
NC
NC

NC

NC
NC

NC
NC

LA N_ DO

33

LA N_ DI

34

LAN_SK _LA N_LINK#

35

LAN_CS

32

LAN_ACT IVITY#

38

LAN_MDI0+

2

LAN_MDI0-

3

LAN_MDI1+

5

LAN_MDI1-

6
8
9
11
12

4

VCTRL12

48
19

30
36
13
10

39
44

45
29

37
1

40
43

+EVDD12
+LAN_V DD12

+LAN_V DD12
+3V_LAN

10/29 update

C247 0.01U_0402_16V7K

1 2

C248 0.01U_0402_16V7K

1 2

LAN_MDI0+
LAN_MDI0­LAN_CT0

LAN_CT1
LAN_MDI1+
LAN_MDI1-

LAN_ACT IVITY#

LAN_SK _LA N_LINK#

U46

1

RD+

2

RD-

3

CT

4

NC

5

NC

6

CT

7

TD+
TD-8TX-

LEF842 3A-R

LA N_ DO
LA N_ DI
LAN_SK _LA N_LINK#
LAN_CS

R697 300 _04 02_5%

1

C268
68P _04 02_50V8K

@

2

2

C269

@

68P _04 02_50V8K

1

R698 300 _04 02_5%

16

RX+

15

RX-

14

CT

13

NC

12

NC

11

CT

10

TX+

9

1 2

R695 3.6K_0402_5%

U45

4

DO

3

DI

2

SK

1

CS

AT93C46-10 SI-2.7_SO8

R696 10K_0402_5%

Y3

LAN_X2LAN_X1

+EV DD12

2

A A

C266

2

C267

1

1

1U_0402_6.3V4Z

0.1U_0402_16V4Z

Close to Pin45Close to Pin19

C264

2

1

+LAN_VDD12

@

C265

0.1U_0402_16V4Z

1

2

10U_0805_10V4Z

5

Close to Pin48

4

VCTRL12

@

C262

25MHz_20pF_6X25000017

1

C244

1

2

C263

2

1

10U_0805_10V4Z

0.1U_0402_16V4Z

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28

2

27P _04 02_50V8J

Compal Secret Data

Deciphered Date

12

27P _04 02_50V8J

2

10/09 update

1

C245

Change the PCB Footprint from
Y_KDS_1BX25000CK1A_2P to

2

Y_6X25000017_2P

2007/06/30

Compal Electronics, Inc.

Title

RTL8102EL LAN

Size Document Number Re v

Montevi na Blade UMA LA4101P 0.3

Cu stom

Saturday, January 05, 2008

Da te: Sheet o f

25 46

1

A

www.kythuatvitinh.com

B

C

D

E

Mini Card 0--TV tuner/WWAN/Robson

+3VALW +3VS_WWAN

1

C573

2Mi niC@

2

0.1U_0402_16V4Z

IC H_P CIE_ WAK E#
CH_DAT A
CH_CLK
CLKREQ#_10

0_0 402_5%

P CIE_ C_RX N1
PCIE _C_RXP1

PCIE _TXN1
PCIE _TXP1

R427 0 _0603_5%

1 2
1 2

R428 0 _0603_5%

M_WXMIT _OFF#

21

4.7U_0805_10V4Z

1

C574

2Mi niC@

2

1

C575

2Mi niC@

2

JP 6

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

GND1

FOX _AS 0B2 26-S40N-7F

C ONN@

WW AN_POWER_OFF<32>

GND2

+3VS_WWAN

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

0.01U_0402_16V7K

1

C572

CLK_PCIE_MCARD0#<17>
CL K_PCIE_MCARD0<17>

0.1U_0402_16V4Z

CLKREQ#_10<17>

PCIE _TXN1<22>
PCIE_TXP1<22>

+3VS_WWAN

2Mi niC@

2

2Mi niC@
2Mi niC@

R419

1 2
1 2

R421 0_0 402_5%

2Mi niC@
2Mi niC@

1 1

PCIE _RX N1<22>
PCIE _RXP1<22>

2 2

0821 Change +3VS to +3VS_WWAN
0811 Pins 37 and 43 connect to GND and remove +1.5VS

WXMIT_OFF#<22>

D1 1

CH751H-40_SC76

2Mi niC@

SIM card Connector

UIM_ PWR

UIM_DATA
UI M_CLK
UIM_RST

UIM_VPP

+1.5 VS_WLAN

UIM_ PWR
UIM_DATA
UI M_CLK
UIM_RST
UIM_VPP

M_WXMIT _OFF#
PLT_RST#

R420 0_0 402_5% @

1 2

R422 0_0 402_5%

1 2

2Mi niC@

IC H_S MBCLK
ICH_SMBDATA

+1.5 VS_WLAN
+3VS_WWAN

R418

@

1 2

0_1 206_5%

1 3

D

+1.5 VS_WLAN

USB 20_N8 <22>

WW _LED# <33>

11/17 Reserve UIM_DATA
PU to UIM_PWR

+3VALW+3VS_WWAN

Q52A P2305GN

2Mi niC@

S

G

2

UIM_ PWR

JP4

1

1

2

2

3

3

4

4

5

5

6

6

G1

7

7

G2

ACE S_8 8266-07001

C ONN@

+3VALW
+3VS_WWAN

R750

@

1 2

47K _04 02_5%

UI M_CLK

1

C824
18P _04 02_50V8J

2

8
9

@

UIM_DATA

Mini Card 2---WLAN

0.1U_0402_16V4Z

1

C566

2

4.7U_0805_10V4Z

PCIE _RX N3<22>
PCIE _RX P3<22>

+3VS_WLAN

+3VALW

1

C567

2

CLK_PCIE_MCARD2#<17>
CL K_PCIE_MCARD2<17>

CLK_DEB UG_PORT_1<17>

1

2

0.1U_0402_16V4Z

CH_DATA<30>

CH_CLK<30>

CLKREQ#_6<17>

R423 0_0402_5%

1 2

R425 0_0402_5%

1 2

PCIE _TXN3<22>

PCIE _TXP3<22>

C568

0.01U_0402_16V7K

IC H_P CIE_ WAK E#
CH_DAT A
CH_CLK

CLKREQ#_6

CL K_ PCIE _MCARD2#
CL K_ PCIE _MCARD2

PCIE _TXN3
PCIE _TXP3

+3VS_WLAN

+1.5 VS_WLAN

4.7U_0805_10V4Z

1

1

C569

2

0.1U_0402_16V4Z

PLT_RST#

P CIE_ C_RX N3
PCIE _C_RXP3

1

C570

C571

2

2

JP 7

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

GND1

FOX _AS 0B2 26-S40N-7F

C ONN@

XMIT_OFF<22>

01/03 Prevent WLAN leakage

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

GND2

10K _0402_5%

D19

21

CH751H-40_SC76

R431 0_0 805_5%

+1.5 VS

+3VS +3VS _WLAN

R699 0_0 402_5%DEBUG@
R700 0_0 402_5%DEBUG@
R701 0_0 402_5%DEBUG@
R702 0_0 402_5%DEBUG@
R703 0_0 402_5%DEBUG@

R433

@

1 2

R432 0_0 805_5%

1 2

+3VS_WLAN
+1.5 VS_WLAN

1 2
1 2
1 2
1 2
1 2

XMIT_OFF#
PLT_RST#

R424 0_0402_5%

1 2

R426 0_0402_5%@

1 2

IC H_S MBCLK
ICH_SMBDATA

USB 20_N5 <22>USB 20_P8 <22>
USB 20_P5 <22>

WL_ LED# <33>
+1.5 VS_WLAN
+3VS_WLAN

+3VALW

12

12

@

R434
100 K_0 402_5%

13

D

@

Q10

2

2N7002_SOT23-3

G

S

R435

1 2

0_0 402_5%

XMIT_OFF#

+3VALW
+3VS_WLAN
+1.5 VS_WLAN

+1.5 VS_WLAN

LPC_FRA ME# <21 ,31,32>
LPC_AD3 <2 1,31,32>
LPC_AD2 <2 1,31,32>
LPC_AD1 <2 1,31,32>
LPC_AD0 <2 1,31,32>

3 3

C576

1 2

C579 0 .1U_ 0402_16V4Z

1 2

C580 0 .1U_ 0402_16V4Z

+3VALW

PLT_RST#<9 ,20,25,27>

SY S ON<32,33,3 6,41>
SUS P#<28 ,32,36,3 8,40,41>

+3VALW

EXP_CPPE#<22>

4 4

internal pull high to 3.3Vaux-in
EC need setting at Hi-Z & output Low

1 2

PLT_RST#
SY S ON
SUS P#

R439 100K _0402_5%

1 2

EXP_CPPE#

New Card

Ne wC@

0.1U_0402_16V4Z

Ne wC@
Ne wC@

+3VS

Express Card Power Switch

+1.5VS

U16

Ne wC@

12

1.5Vin

14

1.5Vin

2

3.3Vin

4

3.3Vin
AUX_IN17AUX_OUT

6

SYSRST#

20

SHDN#

1

STBY#

10

CPPE#

9

CPUSB#

18

RCLKEN

R5538D001-TR-F_QFN20_4X4~D

1.5Vout

1.5Vout

3.3Vout

3.3Vout

PERST#

OC#

GND

USB 20_N9<22>

11
13

3
5

15
19
8
16

NC

7

+1.5 VS_PEC

+3VS_PEC

+3V_PEC

PERST#

USB 20_P9<22>

ICH_SMB CLK<17,22,24>

ICH_SMBDATA<17,22,24>

ICH_PCIE_W AKE#<2 2,25>

CLKREQ#_4<17>

CL K_ PCIE_NCARD#<17>
CL K_ PCIE_NCARD<17>

PCIE _RX N4<22>
PCIE _RX P4<22>

PCIE _TXN4<22>
PCIE _TXP4<22>

Close to
JEXP

Ne wC@

R436 0_0 402_5%

1 2

R437 0_0 402_5%

1 2

Ne wC@

R438

1 2

0_0 402_5%

Ne wC@

+1.5 VS_PEC
+1.5 VS_PEC

+3V_PEC
+3VS_PEC

USB 9­USB 9+
EXP_CPPE#

IC H_S MBCLK
ICH_SMBDATA

PCIE _PME#_R
PERST#

CLKREQ#_4
EXP_CPPE#

JEXP1

1

GND

2

USB_D-

3

USB_D+

4

CPUSB#

5

RSV

6

RSV

7

SMB_CLK

8

SMB_DATA

9

+1.5V

10

+1.5V

11

WAKE#

12

+3.3VAUX

13

PERST#

14

+3.3V

15

+3.3V

16

CLKREQ#

17

CPPE#

18

REFCLK-

19

REFCLK+

20

GND

21

PERn0

22

PERp0

23

GND

24

PETn0

25

PETp0

26

GND

27

GND

28

GND

SANTA_ 130801-5_LT

C ONN@

GND
GND

29
30

Near to Express Card slot.

+3VS_PEC

1

C577

0.1U_0402_16V4Z

Ne wC@

C581

0.1U_0402_16V4Z

Ne wC@

C583

0.1U_0402_16V4Z

Ne wC@

+1.5 VS_PEC

+3V_PEC

1

C578

4.7U_0805_10V4Z

2

2

Ne wC@

1

1

C582

4.7U_0805_10V4Z

2

2

Ne wC@

1

1

C584

4.7U_0805_10V4Z

Ne wC@

2

2

01/03 New card PTH connector GND

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

A

B

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/28 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Do cument Number Re v

D

Da te: Sheet o f

Compal Electronics, Inc.

WLAN, WWAN, New Card

Montev ina Blade UMA LA4101P

26 46Saturday, January 05, 2008

E

0.3

5

www.kythuatvitinh.com

4

3

2

1

09/26 (JMicron)recommend C1328/1000pF close to U36 pin5
09/26 (JMicron)recommend place C1329/0.1uF near by C1328
09/26 (JMicron)recommend (APVDD, 20 mil width, less than 120mil long)

GND
GND
GND
GND

NC
NC
NC

+1 . 8VS_CR

10 U_ 080 5_10V 4Z

5
10
30

19
20
44
18
37

XD _ SD_ MS_ D0

48

XD _ SD_ MS_ D1

47

XD _ SD_ MS_ D2

46

XD _ SD_ MS_ D3

45

SD CMD _M SBS_X DWE #

43

SD CLK _ MSCL K_XDCE #

42

XD WP# _ SDWP#

41

XD _ CLE

40

X D_D 4

29

X D_D 5

28

X D_D 6

27

X D_D 7

26

XD _ RE#

25

XD _ RB#

23

X D_ALE

22
34

35
36

6
24

31
32
33

C1 32 6

+3 VS

1

2

1

2

0. 1U_04 02_16 V4Z

C1 33 6

0. 1U_04 02_16 V4Z

0. 1U_04 02_16 V4Z

1

2

C1 32 7

+3 VS

0. 1U_04 02_16 V4Z

+1 . 8VS_CR

C1 33 2

1

2

C1 32 8
10 00P _04 02 _50 V7K

C1 33 4

1

2

1

C1 32 9

0. 1U_04 02_16 V4Z

2

1

2

1

C1 33 3

0. 1U_04 02_16 V4Z

2

1

C1 33 5

0. 1U_04 02_16 V4Z

2

11/07 Stuff for JMB385 internal LDO

R7 04

0_ 060 3_5%

1 2

C1 32 4

10 U_0 805_1 0V4 Z

Use 0603 type and over 20
mils trace width on both side

1

2

+V CC_4IN1+V CC_ OUT

12

C1 32 5

0.1U_ 080 5_ 50V 7M

09/26 (JMicron)recommend change to 0805 Size
09/26 (JMicron)recommend +VCC_OUT >30mil

+V CC_4IN1+ VC C_ OUT

C1 33 0

0. 1U_04 02_16 V4Z

+3 VS

1

2

U3 7

@

3

IN

OUT

4

EN

OUT

2

GND

G5250 C2T1U_ SOT 23- 5

1U _0 603 _10V4 Z

1
5

1

2

C1 33 1

reserved power circuit

11/07 Change U37 correct PCBFootprint SOT23
11/07 BOM delete for JMB385 internal LDO

09/26 Must change P mos FET

+1 . 8VS_CR +1 .8VS

40mil

12

R1 05 0

@

15 0K_ 040 2_ 5%

+3 VS

1 2

1 2

1 2
1 2
1 2

2
3

XD CD0 # _SD CD#
XD CD1 #_ MSC D#

XD WP# _ SDWP#

XD _ CLE
X D_ALE

12

C7 88

@

10 0P_ 040 2_ 25V 8K

C7 89

@

10 0P_ 040 2_ 25V 8K

C7 90

@

10 0P_ 040 2_ 25V 8K

D4 1

1

DA N20 2U _SC70

09/26 (JMicron)recommend
width/length: 12mil /
<250mil for PREXT signal

XD _ RB#

11/07 Change to 8.2K(vender)

09/26 (JMicron)recommend add a
test point for pin 13 1

(pin 7)

PC IE_TXN 5< 22>
PC IE_ TXP5<22>

PC IE_RXN5<22 >
PC IE_RXP5<2 2>

CR _ CP PE#<22 >

CR _ WA KE#<22>

11/09 Add D18 for cardreader wake up

SD CLKSD CLK _ MSCL K_XDCE #
MS C LK
XD CE#

XD _ CD#

1

C1 04 7
27 0P_ 040 2_ 50V 7K

2

CL K _SRC11#<17>
CL K _SRC11<17>

C1 32 1 0.1U_ 040 2_ 16V 4Z

12

C1 32 2 0.1U_ 040 2_ 16V 4Z

12

R4 02 8 .2K_04 02_5%

1 2

R9 72 10 K_0 402 _5%

1 2

+3 VS

、、、、

4

PL T_ RST#<9,2 0,2 5,26>

R4 04 0_ 040 2_5%

1 2

D1 8

21

CH 75 1H-40 PT_SOD323 -2

PC IE_ C_ RXN 5
PC IE_ C_R XP5

T78R7 07

XD CD1 #_ MSC D#
XD CD0 # _SD CD#

+V CC_OUT

use for PWR_EN#

CR _ L ED#

8mA sink current

P REXT

3
4

9
8

11
12

7

X IN

38
39

1
2

13
14

15
16

17

21

U3 6

APCLKN
APCLKP

APRXN
APRXP

APTXN
APTXP

APREXT

PCIES_EN
PCIES

JMB385

XRSTN
XTEST

SEEDAT
SEECLK

CR1_CD1N
CR1_CD0N

CR1_PCTLN

CR1_LEDN

JM B3 8 5- LGE Z0 A _L QFP 48 _7X 7

APVDD

APV18
TAV33

DV33
DV33
DV33
DV18
DV18

MDIO0
MDIO1
MDIO2
MDIO3
MDIO4
MDIO5
MDIO6
MDIO7
MDIO8

MDIO9
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14

APGND

R1 04 2 4.7K_ 040 2_ 5%

1 2

R1 04 1 4.7K_ 040 2_ 5%

1 2

D D

C C

+V CC_4IN1

R1 04 4 10K_0 402 _5 %
R1 04 3 10K_0 402 _5 %

+3 VS

R7 09 1 0K_ 060 3_ 5%
R1 04 8 10 K_0 603 _5 %

XD _ RE#

XD CE#

SD CLK

MS C LK

12
12

11/07 Change to 10K(vender)

1 2
1 2

01/03 Change Cardreader LED control

R1 04 6 200K_ 040 2_ 5%

1 2

12

R7 06

@

10 0_0 402_5%

1 2

@

10 0_0 402_5%

1 2

R7 08

@

10 0_0 402_5%

R7 10 22 _04 02_5%
R7 11 22 _04 02_5%
R7 12 22 _04 02_5%

XDCD 1#_MSCD#
XD CD0 # _SD CD#

Card Reader Connector

R7 05

JR EAD 1

B B

White LED: VF=3V, IF = 5mA, Res = 56ohm

11/09 don't support DIM function

+5 VS

12

R7 19
47 0_0 402_5%

21

D1 5

White

HT -F1 96B P5_ WHI TE

13

D

Q101

2N700 2_SOT2 3-3

S

CR _ L ED#

2

G

R1 94

4.7K_040 2_5%

1 2

+V CC_4IN1

XD _ SD_ MS_ D0
XD _ SD_ MS_ D1
XD _ SD_ MS_ D2
XD _ SD_ MS_ D3
X D_D 4
X D_D 5
X D_D 6
X D_D 7

SD CMD _M SBS_X DWE #
XD WP# _ SDWP#
X D_ALE
XD _ CD#
XD _ RB#
XD _ RE#
XD CE#
XD _ CLE

3

XD-VCC

32

XD-D0

10

XD-D1

9

XD-D2

8

XD-D3

7

XD-D4

6

XD-D5

5

XD-D6

4

XD-D7

34

XD-WE

33

XD-WP

35

XD-ALE

40

XD-CD

39

XD-R/B

38

XD-RE

37

XD-CE

36

XD-CLE

11

7IN1 GND

31

7IN1 GND

41

7IN1 GND

42

7IN1 GND

TAITW _R 0 15 -B 1 0- LM

CONN@

7 IN 1 CONN

SD-VCC
MS-VCC

SD_CLK
SD-DAT0
SD-DAT1
SD-DAT2
SD-DAT3
SD-DAT4
SD-DAT5
SD-DAT6
SD-DAT7

SD-CMD

SD-CD-SW

SD-WP-SW

MS-SCLK
MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3

MS-INS

MS-BS

21
28

SD CLK

20

XD _ SD_ MS_ D0

14

XD _ SD_ MS_ D1

12

XD _ SD_ MS_ D2

30

XD _ SD_ MS_ D3

29

X D_D 4

27

X D_D 5

23

X D_D 6

18

X D_D 7

16

SD CMD _M SBS_X DWE #

25

XD CD0 # _SD CD#

1

XD WP# _ SDWP#

2

MS C LK

26

XD _ SD_ MS_ D0

17

XD _ SD_ MS_ D1

15

XD _ SD_ MS_ D2

19

XD _ SD_ MS_ D3

24

XD CD1 #_ MSC D#

22

SD CMD _M SBS_X DWE #

13

+V CC_4IN1

11/07 Don't stuff for JMB385 internal LDO

11/17 Update CIS library

A A

01/03 Change Cardreader LED control

@

1 2

0_ 080 5_5%

Security Classification

Issued Date

THIS S HEET OF ENGINE ERING DRA WING IS THE P ROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRA DE SE CRET INFO RMATION. THIS SHE ET MA Y NOT B E TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPA RTMENT EXCEP T AS AUTHORIZED B Y COM PAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE US ED BY OR DI SCLOSED TO ANY THIRD P ARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/10/06

Compal Secret Data

Deciphered Date

2

Tit le

Size Do c um en t N umb er Re v

Cu s to m

Da te : She et o f

Compal Electronics, Inc.

USB CardReader&CONN

Mo ntevina Blad e U MA LA41 01P

1

27 46Sa tu rday, Ja nua ry 05 , 2 00 8

0. 3

A

www.kythuatvitinh.com

B

C

D

E

CODEC POWER

+1.5 VS_HDA

R1051

1 2

BLM18B D601SN1D_0603

0.1U_0402_16V4Z

C1342

1 1

1

2

+1.5 VS

R1052

1 2

+3VS +V DD A_CODEC

BLM18B D601SN1D_0603

+3 VDD_CODEC +5VALW

1

2

C1337

1U_0603_10V4Z

C1338

0.1U_0402_16V4Z

+V DD A_ CODEC_R

1

2

R1053

1 2

0_0 603_5%

1

1

2

2

1U_0603_10V4Z

C1340

C1339

0.1U_0402_16V4Z

W=40Mil

C1341

1 2

0.1U_0402_16V4Z

SUS P#<26 ,32,36,3 8,40,41>

11/07 Change to 4.75V LDO

U39

1

IN

OUT

2

GND

3

SHDN

BYP

G9191-4 75T 1U_SOT23-5

5

4

(4.75V(4.56~4.94V))

+V DD A_CODEC

2.2U_0805_16V4Z

1

2

C1343

1

C1344

0.1U_0402_16V4Z

2

300mA

U38

12

1U_0603_10V4Z

9

DVDD_CORE*

1

DVDD_CORE

25

AVDD1*

38

AVDD2**

3

DVDD_IO

32

MONO_OUT

6

BITCLK

5

SDO

8

SDI_CODEC

10

SYNC

11

RESET#

46

DMIC_CLK

33

CAP2

12

PCBEEP

40

NC / OTP

34

SENSE_B / NC

37

NC

18

NC

19

NC

20

NC

27

VREFFILT

26

AVSS1*

42

AVSS2**

7

DVSS**

92HD71B 7X5 NLGXA1X8_QFN48_7X7

EAPD/ SPDIF OUT 0 or 1 / GPIO 0

VOL_UP/DMIC_0/GPIO 1
VOL_DN/DMIC_1/GPIO 2

GPIO 3

VREFOUT-E / GPIO 4

GPIO 5
GPIO 6

SPDIF OUT1 / GPIO 7

SPDIF OUT0

VREFOUT-B
VREFOUT-C

SENSE_A

PORTA_R
PORTA_L

PORTB_R
PORTB_L

PORTC_R

PORTC_L

PORTD_R

PORTD_L

PORTE_R
PORTE_L

PORTF_R
PORTF_L

+3 VDD_CODEC

+V DD A_ CODEC_R

HDA_BIT CLK_CODE C

12

@

R1054

47_ 0402_5%

2 2

33P _04 02_50V8K

3 3

@

C1345

@

1 2

@

1 2

@

1 2

@

1 2

C1358

C1359

C1360

C1361

C1362

R1065

R596

1 2

1 2

1 2

1

2

11/09 reserve EC_BEEP

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0_0 402_5%

0_1 206_5%

0_1 206_5%

R445

@

47K _0402_5%

EC_BEEP

EC_BEEP<32>

1 2

SB_SPKR<22>

GNDA <29,34>

HDA_ BIT CLK_CODE C<21>
HDA_ SDOUT_CODE C<21>

HDA_ SDIN0<21>

HDA_ SYNC_CODEC<21>
HDA_RST# _CODEC<21,32>

DMIC_CLK<19>

R1060 47 K_0402_5%

1 2

R1061 10K _0402_5%

1 2

C1349 0.1U_04 02_ 16V4Z

1 2

+V DD A_ CODEC_R

SENSE_B#<34>

R1062 5.1K_0402_1%

1 2

R1063 39.2K_0402_1%

1 2

+1.5 VS_HDA

HDA_BIT CLK_CODE C
HDA_ S DOUT_CODE C

R1055

HDA_ SDIN0_CODEC

1 2

HDA_ SYNC_CODEC
HDA_RST #_CODEC

R1058 22 _04 02_5%

1 2

C1347

1 2

C1348 0.1U_0 402_16V4Z

C1353

0.1U_0402_16V4Z

C1355
10U_0805_10V4Z

1 2

33_ 0402_5%

1

2

V C_RE FA

MO NO_INR

SENSEB#

EA P D_CODEC

47
2
4
30
31
43
44

S PDIF _OUT

45
48

VRE FOUT _B

28
29

SENSE

13

HP _OUTR

41

HP_OUTL

39

MIC_EXTR

22

MIC_EXTL

21

MI C_ INR

24

MI C_ INL

23

LI NE_OUT_R

36

LINE _OUT _L

35

DOCK _MICR DOCK _ MICR_C

15

DOCK _MICL

14

17
16

R1056 5.1K_0402_1%
R1057 20 K_0402_1%
R1059 39 .2K_0402_1%
R683 10K _0402_1%
C1346 0.1U_0402_16V4Z

1 2

C1350 1U_0 603_10V6K

1 2

C1351 1U_0 603_10V6K

LI NE_OUT_R <29>

LINE _OUT _L <29>

1 2

C1356 1U_0 603_10V6K

1 2

C1357 1U_0 603_10V6K

EA P D_CODEC <32>
DMIC_DA T <19>

SP DIF_ OUT <34>

01/03 Change SPDIF to SPDIF1

VRE FOUT _B <29>

1 2
1 2
1 2
1 2
1 2

HP _OUTR <29>
HP_OUTL <29>

DOCK _MICL_C

1.21K_0402_1%

+V DD A_ CODEC_R

HP Jack & Dock

MIC_EXT_R <29>
MIC_EXT_L <29>

1 2

C1352 0.022U_0402_16V7K

12

R1064

@

0_0 603_5%

1 2

C1354 0.022U_0402_16V7K

Internal SPKR.

12

12

R735

Jack MIC

R733 10K_0402_5%

1 2

R734 10K_0402_5%

1 2

R736

1.21K_0402_1%

1/10*Vin
need close to
Codec

EXTMIC_DET# <29>
JACK_DE T# <29,34>
INTMIC_DE T# <29>

11/07 Change R1059 39.2K

MI C_ IN_R <29>

11/08 Change C1352 C135、、、、 4 (recommend)

Internal MIC

MI C_IN_L <29>

DOCK _MIC_R <34>
DOCK_MIC_L <34>

DOCK MIC

GNDAGND

11/07 Stuff 0 Ohm for AGND and GND

SENSE A SENSE B

Port Resistor Port Resistor

A 39.2K

4 4

B 20K

C 10K

D 5.11K

A

E

F

G

H

39.2K

20K

10K

5.11K

Security Classification

Issued Date

THIS S HEET OF E NGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEP T AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/28 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Do cument Number Re v

Cu st om

D

Da te: Sheet o f

Codec_IDT9271B7

Montevina Blade UMA LA4101P

28 46Saturday, January 05, 2008

E

0.3

A

www.kythuatvitinh.com

B

C

D

E

GAIN0 GAIN1 Av(inv)

+5VS+5VAMP

0.1U_0402_16V4Z

1

1

C283

2

2

0.1U_0402_16V4Z

2
3

SPKR+

18

SPKR-

14

SPKL+

4

SPKL-

8

12

NC

10

12/18 Shut down pop noise

1 2

1U_0603_10V4Z

R686

4.7K_0402_5%

EXTMIC IN

1 1

U40

C285 0.022U_0603_25V7K

1 2
1 2

C286 0.022U_0402_16V7K

C287 0 .022U_0603_25V7K

LINE_OUT_R<28>

LINE _OUT _L<28>

2 2

3 3

EC_MUTE#<32>

1 2
1 2

C288 0 .022U_0402_16V7K

C289 0.022U_0603_25V7K

1 2
1 2

C290 0.022U_0402_16V7K

C291 0 .022U_0603_25V7K

1 2
1 2

C292 0 .022U_0402_16V7K

EC_MUTE#

VRE FOUT _B<28>

MIC_EXT_R<28>

7

RIN+

17

RIN-

9

LIN+

5

LIN-

19

SHUTDOWN

20

R684

0_0 402_5%

4.7K_0402_5%

MIC_EXT_R

MIC_EXT_L<28>

MIC_EXT_L

10U_0805_10V4Z

16

15

6

VDD

PVDD1

PVDD2

ROUT+

ROUT-

LOUT+

BYPASS

GND41GND311GND213GND1

THERMAL PAD

21

TPA6017A2_TSSOP20

12

12

12

R685

C282

GAIN0
GAIN1

LOUT-

C787

R394

1 2

0_1 206_5%

1

C284

2

R395

@

100 K_0 402_5%

R397

100 K_0 402_5%

Keep 10 mil width

1

C293
1U_0805_25V6K

2

15.6 dB

12

12

+5VS

12

12

0

0

1

1

11/17 Change to15.6 dB

R396
100 K_0402_5%

R398

@

100 K_0402_5%

+3VALW

R401

10K _04 02_5%

1 2

HP_DET#

11/07 Add 10K PU

HP _OUTR<28>

HP_OUTL<28>

MDC 1.5 Conn.

JP8

1

GND1

3

IAC_SDATA_OUT

5

GND2

7

IAC_SYNC

9

IAC_SDATA_IN

11

IAC_RESET#

GND13GND14GND15GND16GND17GND

Connector for MDC Rev1.5

C ONN@

1 2

HDA_ SDOUT_MDC
HDA_ SYNC_MDC

HDA_ S DIN1_MDC

HDA_ SDOUT_MDC<21>
HDA_ SYNC_MDC<21>

HDA_ SDIN1<21>
HDA_RS T#_MDC<21>

H12

H14

HOLE A

HOL EA

4 4

1

1

R477 33_ 0402_5%

RES0
RES1

3.3V
GND3
GND4

IAC_BITCLK

18

2
4
6
8
10
12

ACE S_8 8018-124G

R475 0 _0603_5%

@

R476 0 _0603_5%

+3VS

R478

@

10_ 0402_5%

1 2
1 2

12

@

+1.5VS
+3VS

HDA_B ITCLK_MDC <21>

1 2

C618
10P _04 02_25V8K

1

C619

2

0

1

0

1

JACK_DE T#<28,34>

+3VALW

R676

10K _0402_5%

DOCK@

1 2

61

Q16A

DOCK@

2

2N7002DW-7-F_S OT363-6

JACK_DE T# HP_DE T#

+3VS

1

1

C621

C620

@

2

2

4.7U_0805_10V4Z

0.1U_0402_16V4Z

100 0P_ 0402_50V7K

MDC Standoff

Security Classification

Issued Date

THIS S HEET OF E NGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

A

B

DEPARTMENT EXCEP T AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/28 2006/07/26

Q16B

DOCK@

5

2

G

OPP @

R192

1 2

0_0 402_5%

6dB

10dB

15.6dB

21.6dB

3

4

2N7002DW-7-F_S OT363-6

Q46

13

D

2N7002_SOT23-3

DOCK@

S

Q17B

DOCK@

2

6 1

C785

1 2

C786

1 2

3

2N7002DW-7-F_S OT363-6

+

+

Q17A

DOCK@

2N7002DW-7-F_S OT363-6

Compal Secret Data

Deciphered Date

SPKR-

SPKR+
SPKL­SPKL+

1

2

C1378

B+

12

R678
330 K_0 402_5%

DOCK@

1

2

5

4

150 U_B_6.3 VM_R40M

150 U_B_6.3 VM_R40M

INT MIC_DET#<28>

R1105 0_0 603_5%

1 2

R1104 0_0 603_5%

1 2

R1103 0_0 603_5%

1 2

R1102 0_0 603_5%

1 2

1

2

C1377

100 P_0 402_50V8J

100 P_0 402_50V8J

1

1

2

2

C1375

C1376

100 P_0 402_50V8J

100 P_0 402_50V8J

PSOT24 C_SOT23-3

3

D55

@

8/31EMI request

PSOT24 C_SOT23-3

EXTMIC_DET#<28>

C270

0.01U_0402_25V7K

DOCK@

CIR_IN<32,34>

HP OUT

C295

+

1 2

150 U_B_6.3 VM_R40MDOCK@

C296

+

1 2

150 U_B_6.3 VM_R40MDOCK@

11/07 Add Capacitor avoid DC lever to Docking audio

HP _OUT_R

HP_OUT_L

ANA _MIC_DET<32>

HP OUT For M/B

+V DD A_ CODEC

D

MI C_IN_L<28>

MI C_ IN_R<28>

R409 47_0402_5%

R410 47_0402_5%

R1077

0_0 402_5%

4.7K_0402_5%

+3VS

R681 1 0K_ 0402_5%

61

Q18A

2

2N7002DW-7-F_S OT363-6

1 2

DOCK@

1 2

DOCK@

C1379

1U_0603_10V4Z

12

12

1 2

12

R1079

4.7K_0402_5%

Main@

3

Q18B

4

2N7002DW-7-F_S OT363-6

AMP & Audio Jack

12

R1078

Title

Size Do cument Number Re v

Cu st om

Da te: Sheet o f

2

3

2

1

1

D56

@

Audio/B & CIR

MIC_EXT_R
MIC_EXT_L

HP _OUT_R
HP_OUT_L

EXTMIC_DET#
HP_DET#

+5VL

+V DD A_CODEC

R951
10K _0402_5%

1 2

5

Montevina Blade UMA LA4101P

SPEAKER

JP60

1

1

2

2

3

3

4

4

5

GND1

6

GND2

E&T_3806-F04N-02R

C ONN@

11/07Change JP60 PCB
Footprint from
ACES_85204-04001_4P to
ACES_88231-04001_4P

JP49

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

CIR_IN

DOCK_LOUT_R <34>

HP OUT For Docking

DOCK_LOUT_L <34>

10

11

11

12

12

13

13

14

14

ACE S_8 7213-1400G

C ONN@

INTMIC IN

JP5 1

1

1

2

2

3

3

4

4

5

GND1

6

GND2

ACE S_8 8231-04001

C ONN@

29 46Saturday, January 05, 2008

E

0.3

www.kythuatvitinh.com

A

www.kythuatvitinh.com

White

CAP S_L ED#<32>

1 1

BAT_LED#<32>

SATA_LED#<21>

HDDHALT_LED#<22>

AMBER

ON /OFFBTN_LE D#

HT-F 196 BP5_WHITE

HT-F 196 BP5_WHITE

White

HT-F 196 BP5_WHITE

D50

White

D52

D53

White

Amber

QSMF-C16E_AMBER-WHITE

White

D17

21

21

21

43

21

R1095

1 2

470 _04 02_5%

R1097

1 2

470 _04 02_5%

R1098
470 _04 02_5%

1 2

GS@

1 2

R728
470 _04 02_5%

R980

1 2

470 _04 02_5%

B

+5VS_LED

+5VALW_LED

Cap lock

Battery
Charge LED

+5VS_LED

+3VS

+5VALW_LED

HDD LED

System
Power LED

C

+5V_TP

TP ON/OFF

SW 1
TJG-533 -V-T/R_6P

3
4

5

12

R611
10K _0402_5%

1
2

11/07 Change part number

6

@

T/P Board (Inculde T/P_ON/OFF)System LED

TP_BTN# <32>

D

TouchPAD ON/OFF LED

+5VS_LED

12

R610

820 _0402_5%

43

Amber

13

D

2

G

Q4

S

R718

10K _0402_5%

+5VS

AMBER White

12

2N7002_SOT23-3

E

12

R609
200 _0402_5%

21

White

D1 2
QSMF-C16E_AMBER-WHITE

TP_LED#

On (TP_LED#=L)-> White
Off (TP_LED#=H)-> Amber

TP_LED# <32>

1

C729

@

0.1U_0402_16V4Z

2

C730

@

100 P_0 402_50V8J

61

Q11A

2

12

Q11B

12

TP_DATA
TP_CLK

5

1

1

2

2

+3VS

12

2N7002DW-7-F_S OT363-6

3

4

2

3

D28
PSOT24 C_SOT23-3

@

1

EMI request

TP_CLK <32>
TP_DATA <32>

C731

@

100 P_0 402_50V8J

R193
10K _04 02_5%

WL_ BLUE_LED# <32>

2N7002DW-7-F_S OT363-6

Compal Electronics, Inc.

KBD, ON/OFF, SW, CIR

Montev ina Blade UMA LA4101P

33 46Saturday, January 05, 2008

E

0.3

2 2

Capacitor Sensor Conn

R151 0_0 402_5%OPP@

WL_ BLUE_BTN<32>

ENE

Cypress

3 3

WL_ BLUE_LED#

SMB _EC_CK1<31,32,37>

ESB_CLK<32>
ESB_DAT<32>

I2 C_INT<32>

NUM_LED#<32>

SMB _EC_DA1<31,32,37>

R234

@

ESB_CLK

33_ 0402_5%

01/03 EMI request

SMB _EC_CK1
ESB_CLK
ESB_DAT

SMB _EC_DA1

12

@

C310

15P _04 02_50V8J

1 2

R169 0_0 402_5%OPP@

1 2

R729 0_0 402_5%

1 2

R56 0_0 402_5%Main@

1 2

R149 0_0 402_5%Main@

1 2

R730 0_0 402_5%

1 2

12

ON/OFF Button Connector

+5VALW_LED

JP1 0

1

ON/OFFBTN<32>

ON/OFFBTN_LED#<31,32>

ON/OFFBTN
ON /OFFBTN_LE D#

1

2

2

3

3

G1

4

4

G2

ACE S_8 5201-04051

C ONN@

5
6

Lid Switch Connector

4 4

LI D_SW#<32>

+3VALW

JP11

1

1

2

2

3

5

3

G1

4

6

4

G2

ACE S_8 5201-04051

CONN@

A

01/03 Change Lid switch connector type

+5VS_LED

+3VL +5VAL W_LED

12

12

R51

R53

0_0 805_5%

0_0 805_5%

Main@

OPP @

JP5 9

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

12

R1101
10K _0402_5%

1

4.7U_0603_6.3V6K
C313

2

10

10

11

GND

12

GND

ACE S_8 5201-1005N

C ONN@

Keyboard backlight Conn

R205

+5VS_LED

1 2

0_0 805_5%

01/03 Keyboard backlight reserve a 0805 size resistor

B

JP9

1

1

2

2

3

3

G1

4

4

G2

ACE S_8 5201-04051

C ONN@

5
6

Security Classification

T/P Board Conn

+5VALW +5V_TP

R691 0_0603_5%

1 2

S

D

13

12

R612

@

10K _0402_5%

13

SY S ON<26 ,32,36,41>

SY S ON

D

2

G

S

Q23

G

SI2301BDS-T1-E3_SOT23-3

2

Q24

@

2N7002_SOT23-3

JP2 3

5
6

ACE S_8 5201-04051

C ONN@

Mini card LED

+3VS

Q14

47K

DTA114YKA T146_SOT23-3

10K

WL_ LED#<26>

+3VS

Q20

47K

DTA114YKA T146_SOT23-3

2Mi niC@

10K

WW _LED#<26>

2

1 3

11/20 Reserve WW_LED function

Issued Date

THIS S HEET OF E NGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEP T AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/28 2006/07/26

Compal Secret Data

Deciphered Date

2

1 3

D

BT_LED<30>

G1
G2

WL_LED

100 K_0 402_5%

+5V_TP

1

1

TP_CLK

2

2

TP_DATA

3

3

4

4

R716

100 K_0 402_5%

R717

Title

Size Do cument Number Re v

Da te: Sheet o f

DOCK_PWR_ON Spec

www.kythuatvitinh.com

0V = Notebook S4/S5, Dock off

2.5V = Notebook S3, Dock on
4V = Notebook S0, Dock on

R974 1K_0402_5%

+5VS

R975 1K_0402_5%

+3VALW

SY SON#<36,4 2>

1 2
1 2

Q58

2N7002_SOT23-3

DOCK@

DOCK@
DOCK@

2

G

13

D

S

Dock PRESENT

CONA#<32>

DOCK_PRES ENT

R979

1 2

22_ 0402_5%

DOCK@

12

R623
2K_0402_5%

DOCK@

2
3

12

R976
10K _04 02_5%

DOCK@

2

D57

DAN202U_SC70

DOCK@

+3VL

G

DOCK _P WRON

1

11/12 Change to +3VL

R621
10K _0402_5%

1 2

13

D

Q27
2N7002_SOT23-3

S

DOCK@

Atlas/ Saturn Dock

R ED<18>
GREEN<18>
BLUE<18>
D_ DDCDATA<18>
D_ DDCCLK<18>

D_ HS YNC<18>

D_ VS YNC<18>

USB 20_N3<22>
USB 20_P3<22>

RJ 45_ MIDI1 -<25>
RJ 45_ MIDI1 +<25>
RJ 45_ MIDI0 -<25>
RJ 45_ MIDI0 +<25>

B+

PJP3

PA D-OP EN 2 x2m

R ED
GR EEN
BLUE
D_ DD CDATA
D_ DDCCL K
D_ HS YNC
D_ VS Y NC
USB 20_N3
USB 20_P3

12/18 Correct GND

RJ 45_MIDI1­RJ 45_MIDI1+
RJ 45_MIDI0­RJ 45_MIDI0+

+V_BAT TERY

21

MIC_Dock

DOCK _MIC_R<28>
DOCK_ MIC_L<28>

38
40
34
36
30
32
26
28
22
24
18
20
14
16
10
12

6
8
2
4

45
46

Need 600 Ohm 500 mA

L36

DOCK@

FBM-11-160 808-601-T_0603

1 2
1 2

L37

DOCK@

FBM-11-160 808-601-T_0603

220 P_0 402_50V7K

+3VS

JD OCK 1

CRT_Red
CRT_Green
CRT_Blue
DDC_DATA
DDC_Clock
Hsync
Vsync
USB­USB+
Digital gnd
MDI3­MDI3+
MD2I­MDI2+
MDI1­MDI1+
MDI0­MDI0+
Battery out
Battery out

GND
GND

C ONN@

C754

DOCK@

GNDA GNDA

Digital gnd

TV Luma

TV chroma

TV composite

TV ground

CIR input
PWR_ON

Mute_LED

Sleep Botton

Jack Detect

VOL_up

VOL_down

SPDIF

Audio Output gnd

Right headphone

Left headphone

Mic_Right

Mic_Left

Mic gnd

Dock_present

FOX _QL1122 L-H2 12AR-7F

DOCK _MIC_R_C
DOCK _MIC_L_C

1

1

C755
220 P_0 402_50V7K

2

2

DOCK@

GND
GND
GND
GND

39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1

41
42
43
44

12/18 Correct GND

11/07 Delete TVout function from Docking

VG A_GND
CIR_IN
DOCK _P WRON
MUTE_LED
DOCK_SLP_B TN#
JACK_DE T#
R_VOL_UP#
R_ V OL_DWN#
S PDIF O_L
AU DI O_ OGND
DOCK _LOUT_R
DOCK_LOUT_L
DOCK _MIC_R_C
DOCK _MIC_L_C
AU DI O_ IGND
DOCK_PRES ENT

CIR_IN <29,32>

MUTE_LED <32>

DOCK_SLP_B TN# <32>

R617 200_0402_5%

1 2

R618 200_0402_5%

1 2

DOCK@

GNDA

DOCK@

DOCK_LOUT_R <29>
DOCK_LOUT_L <29>

GNDA

R620 2K_0402_5%

1 2

+DOCKVIN

C305

1 2

C306

1 2

11/17 Reserve

1

C744

2

DOCK@

100 0P_ 0402_50V7K

JACK_DE T# <28,29>

DOCK_VOL_UP# <32>
DOCK _VOL_DWN# <32>

+DOCKVIN

100 0P_ 0402_50V7K@

100 0P_ 0402_50V7K@

1

C734
100 0P_ 0402_50V7K

2

DOCK@

GNDA

DOCK _LOUT_RR_VOL_UP#

DOCK_LOUT_LR_ V OL_ DWN#

1

1

C745

2

DOCK@

100 0P_ 0402_50V7K

1

C740

2

DOCK@

GNDA GNDA

C741

2

DOCK@

0.01U_0402_16V7K

0.01U_0402_16V7K

11/17 Recommend

13

D

Q29
2N7002_SOT23-3

DOCK@

S

SENSE_B# <28>

Compal Secret Data

Deciphered Date

R625

R626

10K _04 02_5%

DOCK@

1 2

1 2

Q32

DOCK@

2

B

E

2

C757

1

1U_0603_10V6K

DOCK@

C

3 1

DOCK _MIC_L_C

R632

1 2

10K _04 02_5%

DOCK@

47K _04 02_5%

MMBT3904_NL_SOT23-3

R633

DOCK@

Security Classification

Issued Date

THIS S HEET OF E NGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEP T AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

10K _0402_5%

DOCK@

1 2

C

2

B

E

3 1

Q30
MMBT3904_NL_SOT23-3

DOCK@

2

G

2007/08/28 2006/03/10

+1.5 VS_HDA

Q55

@

2N7002_SOT23-3

S PDIF O_L

1 2
13

D

S

R722

@

33_ 0402_5%

2

G

R723

DOCK@

1 2

0_0 603_5%

C64

DOCK@

1 2

0.1U_0402_16V7K

12

1

C819

220 P_0 402_25V8J

DOCK@

Title

Size Do cument Number Re v

Cu st om

Da te: Sheet o f

R978
110 _04 02_5%

2

DOCK@

Compal Electronics, Inc.

DOCK CONN.

Montev ina Blade UMA LA4101P

R977

DOCK@

1 2

220 _0402_5%

34 46Saturday, January 05, 2008

SP DIF_ OUT <28>

0.3

5

www.kythuatvitinh.com

D D

Follow Intel
Feedback putting

2.2K ohm

HDMIDAT_NB<9>
HDMICL K_NB<9>

+3VS_LS

12

R742

12

2

G

20K _04 02_5%

TMDS_B_HPD#

13

D

Q28

S

2N7002_SOT23-3

12

R744

7.5K_0402_1%

TMDS_B_HPD# <11>

C C

TMDS_B_HPD

R743

20K _04 02_5%

R649

2.2K_0402_5%

+3VS_LS

12

Follow Vendor Feedback

12

R650

2.2K_0402_5%

HDMICLK-

HDMI_ TX_2+
HDMI_ TX_2-

4

R653

TMDS_B_DATA2#<11>
TMDS_B_DATA2<11>

TMDS_B_CLK#<11>
TMDS_B_CLK<11>

+3VS_LS

1K_0402_5%

12

TMDS_B_HPD

+3VS_LS

C769

@

0.5P_0402_50V8B

C771

@

0.5P_0402_50V8B

U43

1

GND

2

VCC3V

3

FUNCTION1

4

FUCNTION2

5

GND

6

ANALOG1(REXT)

7

HPD_SOURCE

8

SDA_SOURCE

9

SCL_SOURCE

10

ANALOG2

11

VCC3V

12

GND

R656

@

1 2

68_ 040 2_5%

R658

@

1 2

68_ 040 2_5%

3

+3VS_LS +3VS_LS

48

47

46

45

44

43

42

41

40

39

38

IN_D4-

IN_D4+

OUT_D4+13OUT_D4-14VCC3V15OUT_D3+16OUT_D3-17GND18OUT_D2+19OUT_D2-20VCC3V21OUT_D1+22OUT_D1-23GND

GND

IN_D3-

VCC3V

IN_D3+

IN_D2-

VCC3V

IN_D2+

IN_D1+

+3VS_LS+3VS_LS

37

GND

IN_D1-

GND
FUNCTION4
FUNCTION3

VCC3V

DDC_EN

GND

HPD_SINK
SDA_SINK
SCL_SINK

GND

VCC3V

OE*

24

CH73 18A -BF-TR_QFN48_7X7

R657

@

1 2

68_ 0402_5%

R659

@

1 2

68_ 040 2_5%

36
35
34
33
32
31
30
29
28
27
26
25

0.5P_0402_50V8B

0.5P_0402_50V8B

TMDS_B_DATA1 <11>
TMDS_B_DATA1# <11>

TMDS_B_DATA0 <11>
TMDS_B_DATA0# <11>

11/07 Enable DDC_EN pin

+3VS_LS

HDMI_DE TECT
HD MIDA T
HDMICLK

@

@

R651 0_0 402_5%
R652 0_0 402_5%@

R654 0_0 402_5% @
R655 0_0 402_5%

C770

C772

HDMI_ TX_0­HDMI_ TX_0+HDMICLK+

HDMI_ TX_1­HDMI_ TX_1+

2

R648 0_0603_5%

1 2

12
12

12
12

+3VS_LS

+3VS_LS+3VS_LS

+3VS_LS+3VS

1

11/07 correct TMDS_B_HPD# connection to North bridge

R206 0_0402_5%

1 2

L38

@

HDMICLK-

B B

A A

HDMICLK+

HDMI_ TX_0-

HDMI_ TX_0+

HDMI_ TX_1-

HDMI_ TX_1+

HDMI_ TX_2-

HDMI_ TX_2+

01/03 Reserver 0 ohm co lay with common choke

1

1

4

4

R211 0_0402_5%

1 2
1 2

R214 0_0402_5%

L39

1

1

4

4

R217 0_0402_5%

1 2
1 2

R219 0_0402_5%

L41

1

1

4

4

R220 0_0402_5%

1 2
1 2

R221 0_0402_5%

L42

1

1

4

4

1 2

R222 0 _04 02_5%

2

2

WCM-2012-900T_0805

3

3

@

2

2

WCM-2012-900T_0805

3

3

@

2

2

WCM-2012-900T_0805

3

3

@

2

2

WCM-2012-900T_0805

3

3

HDMI_CLK-

HD MI_CLK+

HDMI_ TX0-

HDMI_ TX0+

HDMI_ TX1-

HDMI_ TX1+

HDMI_ TX2-

HDMI_ TX2+

5

4

HDMI Connector

11/07 Follow recommend change to 3.9K

2 1

R665

1 2

1K_0402_1%

12

R666
10K _0402_1%

Compal Secret Data

Deciphered Date

HDMI_DE TECT

D32

SKS10-04AT_TSMA

Security Classification

Issued Date

THIS S HEET OF E NGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEP T AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/03/10

Vendor suggests 4K PU

L40

1 2

FBML10160808121LMT_0603

C774

330 P_0 402_50V7K

2

1

2

+5VS

21

RB411D T146 _S OT23-3
D31

+5VS_HDMI

1

12

12

R49

R50

3.9K_0402_1%

3.9K_0402_1%

HD MIDA T
HDMICLK

HDMI_CLK­HD MI_CLK+
HDMI_ TX0­HDMI_ TX0+
HDMI_ TX1­HDMI_ TX1+
HDMI_ TX2­HDMI_ TX2+

Title

Size Do cument Number Re v

Cu st om

Montev ina Blade UMA LA4101P

Da te: Sheet o f

0.1U_0402_16V4Z
C773

2

JH DMI1

18

+5V

16

SDA

15

SCL

19

HP_DET

12

CK-

10

CK+

9

D0-

7

D0+

6

D1-

4

D1+

3

D2-

1

D2+

SUY IN_100042MR019S153ZL

C ONN@

CEC

Reserved

GND
GND
GND
GND
GND
GND
GND
GND

DDC/CEC_GND

Compal Electronics, Inc.

HDMI LS & Conn.

1

13
14

2
5
8
11
20
21
22
23
17

35 46Saturday, January 05, 2008

0.3

5

www.kythuatvitinh.com

4

3

2

1

+5VALW to +5VS Transfer +3VALW to +3VS Transfer

B+

Q34A

C760

1

2

61

2

D D

12

R223

330 K_0 402_5%

SUS P

2N7002DW-7-F_S OT363-6

U32

8

D

7

D

6

D

5

D

AO4466_SO8

10U_0805_10V4Z

RU NON

12

1

2

+5VS+5VALW +3VS+3VALWB+

1

S

2

S

3

S

4

G

C761

R224

@

470 _0402_5%

C65

@

0.01U_0402_16V7K

1

2

1

C762

2

0.1U_0402_16V4Z

10U_0805_10V4Z

01/03 Sparate+5VS
and +3VS power
timing

12

R636

330 K_0 402_5%

SUS P

5

Q34B

2N7002DW-7-F_S OT363-6

1

C759
10U_0805_10V4Z

2

RUNO N_3VS

3

4

U33

8

D

7

D

6

D

5

D

AO4466_SO8

12

R638
470 _0402_5%

1

C765

0.01U_0402_16V7K

2

1

S

2

S

3

S

4

G

10U_0805_10V4Z

1

C763

2

0.1U_0402_16V4Z

1

C764

2

+1.8V to +1.8VS Transfer

+1.8VS+1.8V

U34

@

S

D

S

D

S

D

G

D

AO4466_SO8

1
2
3
4

1

C767

@

2

1

C768

@

2

0.1U_0402_16V4Z

10U_0805_10V4Z

SY SON#<34,4 2> SUS P <42>

SY S ON<26,32,3 3,41>

100 K_0 402_5%

SY S ON#

SY S ON

R639

Q13A

2

8

C C

1

C766

@

2

7
6
5

10U_0805_10V4Z

RU NON

11/07 BOM Delete +1.8VS for Cardreader internal LDO

+3VL

+3VL

12

12

R640
100 K_0 402_5%

SUS P

61

3

Q13B

SUS P#

2N7002DW-7-F_S OT363-6

5

4

2N7002DW-7-F_S OT363-6

SUS P# <26,28,32,3 8,40,41>

DIM LED

DIM_LED<32>

DI M_L ED

+5VALW +5VA LW_ LED

12

R637

10K _04 02_5%

13

D

2

G

S

Q33

SI2301BDS-T1-E3_SOT23-3

S

G

DIM_LE D#

Q35
2N7002_SOT23-3

Q15

SI2301BDS-T1-E3_SOT23-3

S

G

2

DIM_LE D#

D

13

1

2

D

C758

0.1U_0402_16V4Z

2

+5VS_LED+5VS

13

1

C294

0.1U_0402_16V4Z

2

H2

H3

H4

H1

HOLE A

HOL EA

1

1

H16

H17

HOLE A

HOL EA

1

1

FM2

FM31FM4

1

Title

Size Do cument Number Re v

Da te: Sheet o f

1

HOL EA

1

H15
HOL EA

1

FM1

Discharge circuit

+VCCP +0.9V

12

R645

470 _0402_5%

3

Q9B

5

4

2N7002DW-7-F_S OT363-6

470 _04 02_5%

Q9A

SUS P

R644

2

+1.5 VS

12

61

2N7002DW-7-F_S OT363-6

B B

A A

+5VS +3VS

12

R641

470 _04 02_5%

61

Q6A

SUS P SY S ON#SUS P

2

SUS P SUS P

2N7002DW-7-F_S OT363-6

R642

470 _0402_5%

Q6B

5

12

3

4

2N7002DW-7-F_S OT363-6

5

4

+1.8V

12

R643

470 _04 02_5%

61

Q12A

2

2N7002DW-7-F_S OT363-6

Security Classification

Issued Date

THIS S HEET OF E NGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEP T AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

12

R646
470 _04 02_5%

3

Q12B

5

4

2N7002DW-7-F_S OT363-6

2007/08/28 2006/07/26

+1.8 VS

12

R647

@

470 _04 02_5%

13

D

2

G

@

S

2N7002_SOT23-3

SUS P

Compal Secret Data

Deciphered Date

Q44

2

H5

HOLE A

HOL EA

1

1

H1 9

H18

HOLEC

HOLE A

1

1

1

Compal Electronics, Inc.

H7
HOLE A

1

H8
HOL EA

1

H9
HOLE A

1

H6
HOL EA

1

H20
HOLEC

1

DC/DC Interface

Montev ina Blade UMA LA4101P

36 46Saturday, January 05, 2008

1

H1 0
HOL EA

1

0.3

A

www.kythuatvitinh.com

B

C

D

+3VALW

PQ3
TP0610K-T1-E3_SOT23-3

1 1

2

AC_LED <38>

ADP_ID <32>

1 3

PR8
100_0402_5%

ACES_88334-057N

PJP1

2 2

1 2

ADP_SIGNAL

5

5

4

4

3

3

2

2

1

1

ADPINAD PIN

1 2

PR3
10K_0402_5%

2

3

PD1

@PJSOT24C_SOT23-3

1

12

100P_0402_50V8J

PC2

12

PR2
10K_0402_5%

12

PC3
1000P_0402_50V7K

12

PD4

RLZ3.6B_LL34

PL1

SMB3025500YA_2P

1 2

12

12

PC4

100P_0402_50V8J

PC12
@1000P_0402_50V7K

VIN +DOCKVIN

PL2

PC5

SMB3025500YA_2P

12

1000P_0402_50V7K

12

12

PC6

0.01U_0402_25V7K

BATT

340K_0402_1%

499K_0402_1%

105K_0402_1%

12

PR1

12

PR4

12

PR6

+5VALW

12

PC1

0.01U_0402_25V7K

3
2

PU1A

LM358ADT_SO8

8

P

+

1

0

-

G

4

PR5

10K_0402_5%

12

BATT_OVP <32>

VMB

PJP2

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

9

GND

10

GND

3 3

SUYIN_200275MR008GXOLZR

PR16

6.49K_0402_1%

1 2

12

PR17
1K_0402_5%

4 4

EC_SMD
EC_SMC

PR13

100_0402_5%

BAT_ID <38>

+3VL

12

PD2
@SM05_SOT23

3
2

12

PR14
100_0402_5%

BATT_TEMP <32>

1

2

3

PD3

1

@SM24.TC_SOT23-3

SMB_EC_DA1

SMB_EC_CK1

PL3

HCB2012KF-121T50_0805

1 2

PL4

HCB2012KF-121T50_0805

1 2

12

PC8
1000P_0402_50V7K

12

A

B

BATT

PH1 under CPU botten side :

CPU thermal protection at 90 +-3 degree C

PC9

0.01U_0402_50V4Z

SMB_EC_DA1 <31,32,33>

SMB_EC_CK1 <31,32,33>

0.22U_0603_10V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Recovery at 47 +-3 degree C

+5VS

CPU

12

PH1
10K_TH11-3H103FT_0603_1%

PR10

15K_0402_1%

1 2
1 2

+5VALW

12

12

PC10

2007/05/29 2008/05/29

PR12

2.55K_0402_1%

Compal Secret Data

PR11

150K_0402_1%

PR15

150K_0402_1%

Deciphered Date

C

12

12

PC11
1000P_0402_50V7K

PR7

47K_0402_1%

1 2

8

5

+

6

-

4

P

G

LM358ADT_SO8

0

PU1B

ENTRIP1 <39>

13

D

7

2

G

PQ1
SSM3K7002FU_SC70-3

S

ENTRIP2 <39>

13

D

2

G

Title

Size Document Number R ev

Date: Sheet of

Compal Electronics, Inc.

DC Connector/CPU_OTP

PQ2
SSM3K7002FU_SC70-3

S

Montevina Blade UMA LA4101P

D

37 46Saturday, January 05, 2008

0.3

A

www.kythuatvitinh.com

V IN

1 1

PR101

47 K_0402_5 %

1 2

12

PC101

47 P_0402_50V8J

PR107
47K_0402 _1%

1 2

SSM3 K70 02FU_SC70-3

2 2

PQ107

2

13

D

2

G

S

PA C IN

ACO FF#

13

PQ105
DT C11 5EUA_SC70 -3

PR1 11

3K_0402_ 1%

1 2

PD1 01

1 2

1SS 355_SOD323-2

2

PQ101
AM4 835EP-T1 -PF_SO8

8
7

5

PQ104

DT A144EUA_SC70-3

1 3

PQ109

13

D

SSM3 K70 02 FU_SC70-3

2

G

S

VCT RL<3 2>

1
2
36

4

PC1 06

1 2

1U_ 0603 _10V6K

P2

12

0.2 2U_0603_16V7 K

PR114
@0_0402_5%

PC117

AM4 835EP-T1-PF_SO8

1
2
3 6

12

PR1 06

20 0K_0402_ 5%

12

PR1 09
15 0K_0402_ 5%

14 3K_0402_ 1%

12

PR113

4

PQ103

AC_ SET<32>

SUS P#<2 6,2 8,32,36,4 0,41>

12

12

PR115
100K_040 2_1%

8
7

5

@0. 01U_0402_16V7K

PC128

1 2

@18 0P_ 0402_50V8J

PC1 12

1 2

1U_ 0603 _6.3V6M

Charge Detector

ADP_I<32>

PR123

3
2

P2

12

8

+

-

4

1M_0402_5%

1 2

PR1 25
47_1206 _5%

12

P

1

O

G

PU10 2A
LM3 93DG_SO8

PC125

0.1 U_0603_25V7K

+3VL

12

PR129

10 K_0402_1 %

STD_ADP <32>

+3VL

PR1 28

2

G

12

10K_0402 _5%

CH GEN#

13

D

S

FST CHG<32>

PQ112
SSM3 K70 02 FU_SC70-3

FST CHG#

1 2

PR137
20K_0402 _1%

+3VL

PR1 32

100K_040 2_5%

2

G

ACD ET

12

3 3

V IN

12

PR131
13 3K_0402_ 1%

12

PR135
10 K_0603_0.1%

1.2 4VREF

4 4

PR104
0_0402_ 5%

1 2

PC1 07

PR110
0_0402_ 5%

1 2

BQ2 4740VREF

PR1 16

39K_0402 _5%

12

PC1 20

0.2 2U_0603_10V7 K

12

13

D

PQ113
SSM3 K70 02 FU_SC70-3

S

PR138

10 0K_0402_ 1%

B

12

+3VL

12

PR118

10K_0402 _5%

1 2

0.1 U_0 402_10V7K

47 0P_0402_ 50V7K

ACS ET

ACS ET

12

PR1 40
10 0K_0402_ 5%

8

IADSLP

9

AGND

10

VREF

11

VDAC

12

VADJ

13

EXTPWR

14

ISYNSET

PC1 21

10 0P_0402_50V8J

PC123

PC133

ACD ET

6

7

LPREF

ACSET

PU10 1
BQ2 4740R HDR_ QFN28_5X5

IADAPT

SRSET

15

16

IAD APT

12

12

5

ACDET

BAT

17

BATT

12

PC1 08

0.1 U_0603_25V7K

4

18

P4

PR102

0.0 12_2512_1%

1 2

1 2

PC102

1U_ 0603 _6.3V6M

12

3

ACP

LPMD

SRP

SRN

19

133K_040 2_1%

12

PR121
200K_040 2_1%

B+

1 2

12

PC1 09
@0. 1U_ 0603_25V7K

CH GEN#

1

2

ACN

CHGEN

PVCC

BTST

HIDRV

REGN

LODRV

PGND

DPMDET

CELLS

21

20

SSM3 K70 02 FU_SC70-3

PR1 20

12

PL101
HCB2 012KF-121T50_0805

29

TP

PC110
1U_ 0805 _25V6K

1 2

28

BST _CHG

27

DH _ CHG

26

LX_CHG

25

PH

RE GNVAD J

24

D L_C HG

23

22

12

PC119
1U_ 0603 _10V6K

D

PQ111

S

IRE F <32>

12

PC1 03

4.7 U_0805_25V6-K

PR1 08
10_1206 _5%

1 2

PD1 02

RLS 4148_LL34-2

PR117

100K_040 2_5%

1 2

13

2

G

12

PC1 04

4.7 U_0805_25V6-K

12

PC134

PC111

1 2

0.1 U_0402_10V7K

12

12

PC129

12

10 00P_0402 _50V7K

AO4 466_SO8

BQ2 4740VREF

12

PC124

0.1 U_0603_25V7K

C

PC1 05

4.7 U_0805_25V6-K

PC130

12

27 0P_0402_50V7K

47 0P_0402_ 50V7K

PQ110

47 K_0402_5 %
PR119

12

CHG_B+

578

3 6

578

3 6

CHG_B+

PQ108
AO4 466_SO8

241

241

BAT _ID <37 >

12

PC1 22

0.0 47 U_0402_16 V7K

PL102
10 U_LF 919AS-100M-P3_ 4.5A_20%

1 2

12

PR1 41

4.7 _1206_5%

12

PC135
47 0P_0603_50V8J

1 2

@0. 1U_ 0603_25V7K

PR1 26

100K_040 2_1%

12

PC1 26

AC_LED<37>

12

PC114

PC113

4.7 U_0805_25V6- K

V IN

12

PR130

2.1 5K_0402_1%

1 2

12

PR133
10 K_0603_0 .1%

PC127

22 P_0402_50V8J

PR112

0.0 15_1206_1%

1 2

1 2

4.7 U_0805_25V6- K
PC118

0.1 U_0 402_10V7K

12

PQ102
AM4 835EP-T1-PF_SO8

1
2
3 6

4

ACO FF#

PR1 39

+3VLP

10 0K_0402_ 5%

1 2

PA C IN

BATT

12

PR122
68 1K_0402_ 1%

1 2

8

PU10 2B

5

P

+

O

6

-

G

LM3 93DG_SO8

4

49 .9K_0402_1%

4

5

8
7

12

5

13

D

2

G

PQ114

S

SSM3 K70 02FU_SC70-3

12

12

PC116

PC115

4.7 U_0805_25V6- K

4.7 U_0805_25V6- K

7

PD103

RLZ 4.3 B_LL34

PR1 36

1 2

PU10 4

REF

CATHODE

NC
NC

ANODE

LMV 431ACM5X_SOT23-5

BATT

PC1 32

@10 00P_0 402_50V7K

PC131

@10 00P_0 402_50V7K

V IN

12

PR127

10 K_0402_1 %

12

P2

3
2
1

D

PR103

47 K_0402_5 %

1 2

12

PR1 05
10 K_0402_5 %

13

2

PQ106
DT C11 5EUA_SC70 -3

PR1 24
1K_ 0402_5%

1 2

PA C IN

12

PR134
10K_0402 _5%

1.2 4VREF

V IN

ACO FF <32,39>

ACIN <32>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

A

B

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/05/29 2008/05/29

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Doc ume nt Number R ev

Dat e: Sheet o f

Charger

Mo ntevina Blade UMA LA4101P

D

38 46Sat urd ay, Ja nua ry 05, 200 8

0.3

A

www.kythuatvitinh.com

B

C

D

E

2VREF_51125

1 1

PR301

13.7K_0402_1%

1 2

B+

2 2

3 3

PL301

HCB2012KF-121T50_0805

1 2

PC316

B++

+3VLP

12

PC301

2200P_0402_50V7K

@0.1U_0402_25V4K

+3VALWP

12

12

PC303

4.7U_0805_25V6-K

PL302

4.7UH_SIQB74B-4R7PF_4A_20%

1

+

PC309

2

220U_6.3VM_R15

12

ENTRIP2<37>ENTRIP1<37>

PQ301

1

D1

2

D1

1S/2D

3

G2

1S/2D

4

1S/2D

S2

SP8K10S-FD5_SO8

1G

LG_3V

8
7
6
5

UG1_3V

12

PC306

10U_0805_6.3V6M

PR307

1 2

1 2

0_0402_5%

PC307

0.1U_0402_10V7K

LX_3V

12

PR315

@4.7_1206_5%

12

PC314

@680P_0603_50V7K

PR303

20K_0402_1%

1 2

PR305

174K_0402_1%

1 2

PU301

25

P PAD

7

VO2

8

BST_3V BST_5V

UG_3V

PR311

VREG3

9

VBST2

10

DRVH2

11

LL2

12

DRVL2

12

620K_0402_5%

2VREF_51125

13

D

SSM3K7002FU_SC70-3

1 2

4

PR317

604K_0402_1%

PQ305

SSM3K7002FU_SC70-3

+3VL

ACOFF

4 4

PU302

74LVC1G14GW_SOT353-5

5NC1

P

A2Y

G

3

12

S

PQ308

PC318

2

G

13

D

2

G

0.022U_0402_25V7K

D

S

S

A

13

D

2

G

S

1 2

PR313

100K_0402_5%

13

PQ307

2

G

SSM3K7002FU_SC70-3

PQ306
SSM3K7002FU_SC70-3

VL

12

100K_0402_5%
PR314

B

EC_ON <32>

PJP302

+5VALWP

+3VALWP

1 2

PAD-OPEN 4x4m
PJP303

1 2

PAD-OPEN 4x4m

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/05/29 2008/05/29

C

12

PC302

0.22U_0603_10V7K

PR302

30.9K_0402_1%

1 2

PR304

20K_0402_1%

1 2

PR306

ENTRIP2

3

4

5

6

VFB2

VREF

TONSEL

ENTRIP2

GND

VIN

SKIPSEL

EN0

15

16

14

13

147K_0402_1%

ENTRIP1

1 2

1

2

VFB1

ENTRIP1

VO1

PGOOD

VBST1
DRVH1

LL1

DRVL1

VREG5

VCLK

17

18

TPS51125RGER_QFN24_4X4

VL

12

PC311

12

B++

(4.5A,180mils ,Via NO.= 9)

+5VALW

+3VALW

(3A,120mils ,Via NO.= 6)

10U_0805_10V6K

PC312

0.1U_0603_25V7K

Compal Secret Data

Deciphered Date

B++

12

PC304

24
23
22

UG_5V

21

LX_5V

20

LG_5V

19

1 2

0_0805_5%

PR308

0_0402_5%

1 2

PR318

2200P_0402_50V7K

PC308

0.1U_0402_10V7K

1 2

VL

+3VLP

D

12

12

PR316

@4.7_1206_5%

12

R_EC_RSMRST# <22>

PJP304

2 1

PAD-OPEN 2x2m

PJP301

2 1

PAD-OPEN 2x2m

12

PC317

PC305

10U_1206_25V6M

PC315

@680P_0603_50V7K

578

@0.1U_0402_25V4K

UG1_5V

578

PQ302

AO4466_SO8

3 6

241

PL303
10U_LF919AS-100M-P3_4.5A_20%

1 2

3 6

241

PQ304

FDS6690AS_NL_SO8

+5VALWP

1

+

PC310

150U_D_6.3VM

2

+5VL

+3VL

Title

Size Document Number R ev

Date: Sheet of

Compal Electronics, Inc.

3.3VALWP/5VALWP

Montevina Blade UMA LA4101P

39 46Saturday, January 05, 2008

E

0.3

A

www.kythuatvitinh.com

1 1

PR401

0_0402_5%

SUSP#

PR410

@10K_0402_5%

2 2

1 2

12

@1000P_0402_50V7K

+1.05V_VCCP

PC401

12

PR405

0_0402_5%

+5VALW

PR403

316_0402_1%

12

12

12

PC409
1U_0603_10V6K

+1.05V_VCCP

PR408

1 2

10.5K_0402_1%

PR404
255K_0402_1%

1 2

2
3
4
5
6

PU401

TON
VOUT
V5FILT
VFB
PGOOD

1

EN_PSV

B

14TP15

VBST

DRVH

LL

TRIP

V5DRV

DRVL

GND7PGND

TPS51117RGYR_QFN14_3.5x3.5

8

1 2

PR402

0_0402_5%

DH_1.05V

13

LX_1.05V

12
11
10
9

BST1_1.05VBST_1.05V

0.1U_0402_10V7K

+5VALW

12

4.7U_0805_10V6K

1 2

PC402

1 2

PR406

18.7K_0402_1%

PC415

PR411

1 2

0_0402_5%

DL_1.05V

578

3 6

578

3 6

241

241

C

12

PC414

@0.1U_0402_25V4K

PQ401
AO4466_SO8

PQ402
FDS6690AS_NL_SO8

12

PC404

4.7U_0805_25V6-K

PL402

1 2

HCB1608KF-121T30_0603

1 2

PC405

2200P_0402_50V7K

1.05V_B+

12

12

PC403

4.7U_0805_25V6-K

2.2UH_PCMC063T-2R2MN_8A_20%

12

PR407

4.7_1206_5%

PC412
220P_0603_50V8J

1 2

PL401

D

B+

12

PC406
@680P_0402_50V7K

+1.05V_VCCP

1

+

PC408

220U_6.3VM_R15

2

12

PR409

25.5K_0402_1%

3 3

PJP401

+1.05V_VCCP

4 4

1 2

PAD-OPEN 4x4m

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

A

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

(6A,240mils ,Via NO.=12)

+VCCP

2007/05/29 2008/05/29

Compal Secret Data

Deciphered Date

C

Title

Size Document Number R ev

Date: Sheet of

Compal Electronics, Inc.

1.05V_VCCP

Montevina Blade UMA LA4101P

D

40 46Saturday, January 05, 2008

0.3

5

www.kythuatvitinh.com

4

3

2

1

D D

B+++

12

PC501

4.7U_0805_25V6-K

C C

PC502

2200P_0402_50V7K

+1.5VSP

3.3UH_PCMC063T-3R3MN_6A_20%

1

12

+

2

220U_B2_2.5VM

PJP501

1 2

PAD-OPEN 4x4m
PJP502

1 2

PAD-OPEN 4x4m

4.7U_0805_6.3V6K

PC517

B B

+1.5VSP

+1.8VP

PL503

PC509

+1.5VS

+1.8V

12

12

PC520

@0.1U_0402_25V4K

578

3 6

241

12

578

PQ504

AO4466_SO8

3 6

241

SUSP#<26,28,32,36,38,40>

(4A,160mils ,Via NO.=8)

(7A,280mils ,Via NO.= 14)

+1.5VSP

PQ502

AO4466_SO8

0.1U_0402_10V7K

PC506

12

12

PR515
@4.7_1206_5%

12

PC518

@680P_0603_50V7K

PR513

10K_0402_5%

73.2K_0402_1%

PR506
0_0402_5%

12

PR5080_0402_5%

12

PR501

1 2

12

12

PC513

0.1U_0402_16V7K

BST_1.5V
UG_1.5VUG1_1.5V

LX_1.5V

LG_1.5V

1U_0603_10V6K

PU501

25

7
8

9
10
11
12

PR510

17.8K_0402_1%

1 2

PC514

PR502

75K_0402_1%

1 2

PR505

0_0402_5%

6

P PAD

PGOOD2
EN2
VBST2
DR VH2
LL2
DR VL2

13

1 2

PR514

3.3_0402_5%

12

PR503

10.2K_0603_0.1%

1 2

1 2

3

4

5

VO2

VFB2

TRIP2

PGND2

15

14

GND

TONSEL

V5FILT

V5IN

16

12

PC515

4.7U_0805_10V6K

2

VFB1

PGOOD1

TRIP1

17

PR511

16.5K_0402_1%

1 2

1

VO1

24
23

EN1

BST_1.8V

22

VBST1

DR VH1

DR VL1

PGND1

TPS51124RGER_QFN24_4x4

18

+5VALW

UG_1.8V

21

LX_1.8V

20

LL1

LG_1.8V

19

PR504

14.3K_0603_0.1%

1 2

0_0402_5%

12

PC512
@0.1U_0402_16V7K

+1.8VP

PR507

12

PR509

0_0402_5%

PR512

0_0402_5%

1 2

12

PC507

0.1U_0402_10V7K

1 2

UG1_1.8V

12

PR516
@4.7_1206_5%

12

PC519

@680P_0603_50V7K

12

PR517

100K_0402_5%

B+++

578

PQ501

AO4466_SO8

3 6

578

3 6

SYSON <26,32,33,36>

PL502

HCB2012KF-121T50_0805

PC516

4.7U_0805_25V6-K

241

3.3UH_PCMC063T-3R3MN_6A_20%

1 2

4.7U_0805_6.3V6K

PQ503

FDS6690AS_NL_SO8

241

12

PL501

12

12

PC504

4.7U_0805_25V6-K

PC510

B+

12

12

PC521

PC505

2200P_0402_50V7K

@0.1U_0402_25V4K

+1.8VP

1

+

PC508

1 2

2

220U_D2_4VY_R25M

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

5

4

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/05/29 2008/05/29

3

Compal Secret Data

Deciphered Date

Title

Size Document Number R ev

2

Date: Sheet of

Compal Electronics, Inc.

1.5VSP/1.8VP

Montevina Blade UMA LA4101P

41 46Saturday, January 05, 2008

1

0.3

5

www.kythuatvitinh.com

D D

C C

PJ P60 1

+0 .9VP

1 2

PA D- O PE N 3 x3m

(2A,80mils ,Via NO.= 4)

+0 .9V

4

+1. 8V

12

12

PC 60 1

10 U_ 080 5_10V 4Z

SYSON#<34,36>

SUSP<36>

1 2

PR 60 2

@0 _0 402 _5%

SS M3 K70 02FU_S C70 -3

1 2

PR 60 4

0_ 040 2_5%

PQ 601

12

PC 60 6
@0 .1U_0 402 _1 6V7 K

12

PC 60 2

PR 60 1
1K_ 04 02_ 1%

@1 0U _0 805 _10V4 Z

12

PR 60 3

13

D

2

G

1K_ 04 02_ 1%

S

3

PU 60 1

VIN1VCNTL

2

GND

3

VREF

4

VOUT

G2 9 92 F1U_SO8

6
5

NC

7

NC

8

NC

9

TP

+5VALW

12

PC 60 3
1U_06 03_16 V6K

2

1

+0.9VP

12

12

PC 60 5
10 U_0 805_6 .3V 6M

0.1U_ 040 2_ 16V 7K

PC 604

B B

A A

Security Classification

Issued Date

THIS S HEET OF ENGINE ERING DRA WING IS THE P ROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRA DE SE CRET INFO RMATION. THIS SHE ET MA Y NOT B E TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPA RTMENT EXCEP T AS AUTHORIZED B Y COM PAL E LECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE US ED BY OR DI SCLOSED TO ANY THIRD P ARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/11/23 2007/11/23

Compal Secret Data

Deciphered Date

2

Tit le

Size Do c um en t N umb er Re v

Da te : She et o f

Compal Electronics, Inc.

0.9VP/1.1V_PCIE

Mo ntevina Blad e U MA LA41 01P

1

42 46Sa tu rday, Ja nua ry 05 , 2 00 8

0. 3

5

www.kythuatvitinh.com

4

3

2

1

+5VS

PC205

4.7U_0805_25V6-K

PR220

10K _04 02_ 1%

12

PC 214

PR231

CPU_B+

12

12

PC206

4.7U_0805_25V6-K

PL202

12

PR 224

@0_0603_5%

1 2

PC 211

1 2

IS E N1

0.22U_0603_10V7K

12

12

PC235

PC236

220 0P_ 040 2_50V7K

4.7U_0805_25V6-K

PL203

12

10K _04 02_ 1%

PR 233 @0_ 060 3_5%

1 2

PC 223

1 2

0.22U_0603_10V7K

IS E N2

12

PC 207

220 0P_ 040 2_50V7K

12

12

12

4.7U_0805_25V6-K

12

PL201

SMB 302 5500YA _2P

12

PC237

PR 223

1_0 402 _5%

VC C_ P RM

12

PC238

@0.1U_0402_25V4K

12

PR 232

1_0 402 _5%

VC C_ P RM

12

1

1

+

+

PC 241

PC 239

2

2

@0.1U_0402_25 V4K

68 U_2 5V_ M_R0 .44

68 U_2 5V_ M_R0 .44

+V CC_CORE

CPU_B+

1 2

12

12

0.22U_0603_10V7K
PC209

1 2

1 2

0_0 603 _5%

PR217

FDS6676AS_SO8

1 2

PC 217

PR 202
1_0 603 _5%

PC203

2.2U_0603_6.3V6K

UGAT E_CPU1-2

578

PQ202

UGAT E_CPU2-2

PQ205

FDS6676AS_SO8

3 6

241

578

3 6

1

12

12

+

PC 204

PC 242

5

PQ201

D8D7D6D

AO4474_SO8

S1S2S3G

4

578

3 6

241

PQ203

FDS6676AS_SO8

5

PQ204

D8D7D6D

AO4474_SO8

S1S2S3G

4

578

241

3 6

241

PQ206
FDS6676AS_SO8

2

470 P_0 402 _50V7K

68 U_2 5V_ M_R0 .44

12

PR218

4.7_1206_5 %

12

PC210

470 P_0 603 _50V7K

12

PR 229

4.7_1206_5 %

12

12

PC233

PC234

4.7U_0805_25V6-K

4.7U_0805_25V6-K

0. 36 UH _P CMC104T-R36MN1R17_30A_20%

12

PR219

3.65K_0805_1%

VS UM

12

PC213

PC212

4.7U_0805_25V6-K

4.7U_0805_25V6-K

0. 36 UH _P CMC104T-R36MN1R17_30A_20%

12

PR 230

3.65K_0805_1%

PC 219

VS UM

470 P_0 603 _50V7K

<7>

<7>

<7>

<7>

<32>

CP U_ VID5

CP U_ VID3

CP U_ VID4

CP U_ VID6

VR _O N

D D

PR215

@499_0402_1%

VGA TE<17,2 2>

H_ PS I#<7>

PR 221

1 2

@0_0402_5%

PR 222147K_0402_1%

1 2

C C

PR226 13K _0402_1%

1 2
1 2

PR 2286.81 K_0 402_1%

1 2

1 2

PC218 1000P_0402_50V7K

PR235 97.6K _04 02_ 1%

1 2

470 P_0 402 _50V7K

1 2

PC 222 220P_0402_50V7K
255 _04 02_1%

B B

VC CS ENSE<7>

1 2

PR238

PR 2401K_0402_1%

VS SSENSE<7>

DP RS LPVR<9,22>

H_ DPRSTP #< 7,9,21>

CL K_ENAB LE#<1 7>

+3VS

+3VS

1 2

VR_TT#

PC2150.022U_0603_25V7K

1 2

PC216100 0P_ 0402_50V7K

PC220

12

PC224 1000P_0402_50V7K

1 2

1 2

VC C_ P RM

PR201 499_0402_1%

PR 204 0_0402 _5%

PR206 0_0402_5%

1 2

12

PC201

PR216

1U_0603_6.3V6M

1.91K_0402_1%

10
11
12

PR236

1 2

@0_0402_5%

PC226 820P_0603_50V7K

1 2

12

PC227
@0.022U_0603_50V7K

PC229 180P_0402_50V8J

1 2

PR243 1K_0402_1%

PC231

0.22U_0603_10V7K

1 2

PR 203 0_0402 _5%

1 2

1 2

12

48

49

3V3

GND

1

PGOOD

2

PSI#

3

PMON

4

RBIAS

5

VR_TT#

6

NTC

7

SOFT

8

OCSET

9

VW
COMP
FB
FB2

VDIFF13VSEN14RTN15DROOP16DFB17VO18VSUM19VIN20GND21VDD22ISEN223ISEN1

12

PR 237

1K_040 2_1%

1 2

1 2

PR244 3.57K _04 02_ 1%

PR207

12

0_0 402 _5%

44

45

46

47

VR_ON

CLK_EN#

DPRSTP#

DPRSLPVR

IS L6262A CRZ-T_QFN48_7X7

12

PC 228

0.01U_0603_50V7K

PC230 0.1U_0402_16V7K

1 2

PC 2320.22 U_0402_ 6.3V6K

12

PR210

PR208

PR209

12

12

12

0_0 402 _5%

0_0 402 _5%

43

12

PR 242

12

CP U_ VID2

PR212

PR211

12

12

0_0 402 _5%

0_0 402 _5%

0_0 402 _5%

12

10_ 060 3_5%

1 2

PC225

0.1U_0603_25V7K

12

PR241

12

11K _04 02_ 1%

1 2

CP U_ VID1

PR205

12

0_0 402 _5%

BOOT1
UGATE1
PHASE1

PGND1
LGATE1

LGATE2

PGND2
PHASE2
UGATE2

BOOT2

1 2

PC221
1U_0402_6.3V6K

PR239

VS UM

2.61K_0402_1%

PH201

<7>

<7>

<7>

CP U_ VID0

0.022U_0402_16V7K

PR213

12

0_0 402 _5%

BO OT_CP U1

VID037VID138VID239VID340VID441VID542VID6

36

UGAT E_CPU1-1

35

PH ASE _CPU1

34
33
32
31

PVCC

30
29
28
27
26
25

NC

PU 201

24

IS E N1
IS E N2

PR234 1_0603_5%

10K B_0603 _5%_ERTJ1V R103J

LG AT E_CPU1

LG AT E_CPU2

PH ASE _CPU2
UGAT E_CPU2-1
BO OT_CP U2

1 2

PR 227

2.2_0603_5 %

+5VS

CPU_B+

PC 202

2.2_0603_5 %
PR 214

1 2

PR 225

1 2

0_0 603 _5%

0.22U_0603_10V7K

B+

12

12

PC 240

PC 208

220 0P_ 040 2_50V7K

100 0P_ 040 2_50V7K

A A

Compal Electronics, Inc.

Title

THIS S HEET OF E NGINEERING DRAW ING IS THE PROPR IETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

5

4

AND TRADE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEP T AS AUTHORIZE D BY COMPAL ELEC TRONIC S, INC . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISC LOSE D TO ANY THIR D PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

+CPU_CORE

Size Do cu me nt Number Rev

Cu st om

Da te: Sheet o f

43 46S at ur da y, Jan uary 05, 2008

1

0.3

5

www.kythuatvitinh.com

4

3

2

1

Item (Reason for change)Fixed Issue PAGE Modify List Date

Phase

1 11/21C41、C42、C43、C44 Change ESR=7m ohmTransation Fail 08

2

Disable TV out function from Docking 11、34 R61 R62、 、R63 change to 75 Ohm、TV_DCONSEL_0、TV_DCONSEL_1 connect to GND

3

D D

C C

Update Connetor Library

4

Delete LVDS B channel 11、19 Schematic Delete

5

USB camera Footprint error 19 Change U42 to G916-390T1UF SOT23, it adjustable mode, R1091=215K，R1093=100K 11/07

6

Reserve Card reader D3E function 22、27 GPIO6= CR_CPPE#，GPIO22=CR_WAKE#

7

Swap PCIE LAN and New card 22 Swap PCIE4 and PICE6

8

Add HDCP ROM for ICH9M 22、31 Add HDCP ROM for ICH9M

9

Change G sensor control from SB、LED drive by +5VS 22、33 Change G sensor control from SB

10

Avoid Battery mode can't boot issue 22、39 Add +3VALW GD to EC_RSMRST# to fix Battery mode can't boot issue 11/17

11

12

Change LAN solution (Marvell to Realtek) 25

13

LAN can't work 25 U46 Change to correct transformer type

14

Cardreader schematic review and update, add D3E function 27 R709-->10K R402、 -->8.2K、R704-->Stuff、R705-->@、U37-->@、Cardreader LED-->+5VS、add D3E function 11/17

15

Jack can't detect normal 28 R1059 change from 39.2 to 39.2K

16

Speaker work un normal 28 Add and Stuff C1362、R1065、R596

CRT(JCRT1)、HDMI(JHDMI1)、ESATA(JP53)、Finger print(JJP24)、FAN(JP2)、Speaker(JP60)、Multi
bay(JP12)、Dual LED(D53、D12)

Change LAN solution (Marvell to Realtek) 11/17

11/07

11/17

11/17

11/17

11/17

11/17

11/17

11/17Add G sensor ST and Bosch 24 Add G sensor ST and Bosch

11/17

11/17

11/17

SI-1

SI-1

SI-1

SI-1

SI-1

SI-1

SI-1

SI-1

SI-1

SI-1

SI-1

SI-1

SI-1

SI-1

SI-1

SI-1

17

HP audio team recommend 28、29 C285~C292、C1352、C1354 change to 0.022U、Amp output setup to 15.6 dB、Reserve C305、C306 for GNDA and GND

18

Audio jack can't detect normal 29 Add Pull up resistor R401 to +3VALW

19

B B

A A

Docking HP audio test fail 29 Add C295BC296 to avoid DC level, and add R409、R410 to reduce HP out level

20

Leakage problem 32 Correct direction pretect leakage 11/07

21

EC pin define update 32

22

Can't Hibernation(SLP_S4#) 32 Connect SLP_S4# to SB

23

EC can't receive docking present CONA# change +3VL34

24

HDMI can't detect 35 DDC _EN must enable 、TMDS_B_HPD# inverse 11/07

25

LVDS power on timing 19 C238 change to 0.047u to meet TI timing

26

Prevent WWAN nosie 21 Add 12p on HDA_SDOUT and HDA_SDOUT

27

Power leakage 21、31 Change HDCP ROM to +3VS power plane

28

Prevent WLAN leakage 26 Add Diode prevent WLAN leakage

5

4

Delete EC_PME#、SYSON PU、SUSP# PU、LID_SW# change to +3VALW、Delete CLKRUN#、R582->@ for C0 chip、CIR
PU+5VL、add 100P to BATT_OVP(EC recommend)

Security Classification

Issued Date

THIS S HEET OF E NGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEP T AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Do cument Number Re v

2

Da te: Sheet o f

Compal Electronics, Inc.

PIR

Montev ina Blade UMA LA4101P

11/17

11/17

11/17

SI-1

SI-1

SI-1

SI-1

11/07

11/17

11/12

SI-1

SI-1

SI-1

SI-1

01/03

01/03

01/03

01/03

1

SI-2

SI-2

SI-2

SI-2

0.3

44 46Saturday, January 05, 2008

5

www.kythuatvitinh.com

4

3

2

1

Item (Reason for change)Fixed Issue PAGE Modify List Date

Phase

29 01/03New card PTH connector GNDNew card PTH connector GND 26

30

Change Cardreader LED control 27 Change Cardreader LED control

31

D D

C C

Change SPDIF to SPDIF1 Change to SPDIF1

32

Shut down pop noise 29 Change C293 to 1U

33

Change BT power to +3VS 30 Change BT power to +3VS

34

EMI Request 31 SPI_FSEL#、SPI_CLK_R、SPI_FWR# reserver RC

35

Reserver 0 ohm co lay with common choke 35 Reserver 0 ohm co lay with common choke

36

Sparate+5VS and +3VS power timing 36 Sparate+5VS and +3VS power timing

37

Keyboard backlight reserve a 0805 size resistor 33 Keyboard backlight reserve a 0805 size resistor

38

Change Lid switch connector type 33 Change Lid switch connector type

39

28

01/03

01/03

01/03

01/03

01/03

01/03

01/03

01/03

01/03

SI-2

SI-2

SI-2

SI-2

SI-2

SI-2

SI-2

SI-2

SI-2

SI-2

40

41

42

43

44

45

46

47

B B

48

49

50

51

52

53

54

55

A A

56

Security Classification

Issued Date

THIS S HEET OF E NGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

5

4

DEPARTMENT EXCEP T AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Do cument Number Re v

2

Da te: Sheet o f

Compal Electronics, Inc.

PIR 2

Montev ina Blade UMA LA4101P

1

45 46Saturday, January 05, 2008

0.3

A

www.kythuatvitinh.com

B

C

Version Change List ( P. I. R. List ) for Power Circuit

D

E

Page#

1 1

1

37

2

3

38

4

43

5

39 3.3VALWP/5VALWP 11/14 Compal for Layout Change PL303 and PC310

6

2 2

38 Charger 12/31 Compal EMI solution Add PC129, PC130, PC131, PC132, PC133

7

8

39 3.3VALWP/5VALWP 12/31 Compal PWR request Add PU302, control signal changed to ACOFF

9

10

Title

DC Connector
/CPU_OTP

3.3VALWP/5VALWP Compal

Charger 11/06 Compal EMI solution

+CPU_CORE 11/06 Compal EMI solution

+CPU_CORE43 12/31 Compal EMI solution Add PC242

Date

11/06

11/0639

Request
Owner

Compal

Add PD4 & PC12

for Layout

Solution Description

Add PD4 & PC12

Change PQ301 cancel PQ303

Add pc128

Add PC240

Rev.Issue DescriptionItem

11

3 3

12

13

14

4 4

Security Classification

Issued Date

THIS S HEET OF E NGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

A

B

DEPARTMENT EXCEP T AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Do cument Number Re v

Cu st om

D

Da te: Sheet

Compal Electronics, Inc.

Power Changed-List History-1

Montev ina Blade UMA LA4101P

E

o f

46 46Saturday, January 05, 2008

0.3