HP CQ40-AMD Schematics
A
B
C
D
E
1 1
2 2
Compal confidential
Schematics Document
Mobile AMD S1G2 CPU with ATI
RX781(NB) & SB700(SB) core logic
3 3
2008-05-14
REV:1.0
4 4
A
B
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2007/10/11 200810/11
2007/10/11 200810/11
2007/10/11 200810/11
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC MB A4112
SCHEMATIC MB A4112
SCHEMATIC MB A4112
401568
401568
401568
154Friday, February 13, 2009
154Friday, February 13, 2009
154Friday, February 13, 2009
E
of
of
of
F
F
F
A
Compal Confidential
B
C
D
E
1 1
Accelerometer
LIS3LV02DL-TR
VRAM
256MB
page 19, 20
DDR2 400MHz
Page 37
Discrete
OPP Rachman AMD 14" Discrete - LA-4112P
Thermal Sensor
ADM1032ARMZ
Page 6
Fan conn
Page 4
PCI-E Lane*16
AMD S1G2 CPU
638-PIN uFCPGA 638
Page 4, 5, 6, 7
Hyper Transport Link
16X16
DDR2 800MHz 1.8V
Dual Channel
DDR2-SO-DIMM X2
BANK 0, 1, 2, 3
PC2-5300 (DDR2/667)
PC2-6400 (DDR2/800)
Page 8, 9
72QFN
Clock Generator
SLG8SP626VTR
Page 22
ATI M82-SCE
Page 15,16,17,18,21
ATI RS780, RX781
LVDS Panel
Interface
2 2
CRT
HDMI
Page 24
Page 23
1600x1200 max resolution at 75Hz
Page 25
A-Link Express II
4X PCI-E
PCI-E BUS*5
CardReader-JM385
5 in 1
Page 34
CardReader CONN
3 3
5 in 1:SD/MMC/MS/MSPro/XS
Support for RS-MMC, Memory Stick Duo and Memory Stick
Duo Pro, Micro-M2, Mini-SD, and MicroSD
Page 34
Realtek
8102EL(10/100M)
Page 32
RJ45/11 CONN
Page 32
Mini-Card* 1
WLAN Card
802.11a/b/g/n
Page 34
LED
Page 41
Touch Pad CONN. Int.KBD
RS780MN/CE
Page 10, 11, 12, 13, 14
ATI SB700
Page 26,27,28,29,30
KBC
ENE KB926
Page 41
LPC BUS
Page 40
Azalia (HDA I/F)
SATA Master-1
SATA Master-2
SATA Slave
SATA Slave
Page 40
USB2.0 X12
USB conn x3
BT Conn
USB WebCam
Chicony CNF7047
MDC V1.5
Page 38
Page 38
Page 24
Page 41
Audio CKT
Codec_IDT9271B7
SATA HDD Connector
SATA ODD Connector
Page 35 Page 36
Page 31
Page 31
daughter board
daughter board
daughter board
AMP & Audio Jack
TPA6017A2
RTC CKT.
SPI ROM
C
SPI
25LF080A
Page 39
Compal Secret Data
Compal Secret Data
2007/10/11 200810/11
2007/10/11 200810/11
2007/10/11 200810/11
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
e-SATA Connector
D
Page 38
Vista 32&64 bit supporttive
Energy star 4.0/EPEAT request compliant
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC MB A4112
SCHEMATIC MB A4112
SCHEMATIC MB A4112
401568
401568
401568
254Friday, February 13, 2009
254Friday, February 13, 2009
254Friday, February 13, 2009
E
of
of
of
F
F
F
Page 26
4 4
Consumer IR
Page 36/42
Power On/Off CKT.
P41
DC/DC Interface CKT.
Page 43
A
B
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
D
E
Voltage Rails
1 1
State
2 2
S0
S1
S3
S5 S4/AC
S5 S4/ Battery only
S5 S4/AC & Battery
don't exist
3 3
4 4
I2C / SMBUS ADDRESSING
DEVICE
DDR SO-DIMM 0
DDR SO-DIMM 1
CLOCK GENERATOR (EXT.)
ACCELEROMETER 3A 0 0 1 1 1 0 1 0
EC SM Bus1 address
Device
Smart Battery
24C16
CPU SIC interface
A
O MEANS ON X MEANS OFF
power
plane
HEX
A0
D2
+B
+3VL
+5VL
O
O
O
O
O
X
+5VALW
+3VALW
+1.2VALW
O
O
O
O
X
XX X
ADDRESS
1 0 1 0 0 0 0 0
1 0 1 0 0 1 0 0A4
1 1 0 1 0 0 1 0
+1.8V
+0.9V
EC SM Bus2 address
HEX HEX
Address Address
0001 011X b
16H
1010 000X b
A0H
1001 100X b
98H
Device
ADI1032-2 CPU
ADI1032-1 VGA
B
9AH
98H
+5VS
+3VS
+2.5VS
+1.8VS
+1.5VS
+1.1VS
+VGA_CORE
+1.2V_HT
+CPU_CORE_0
+CPU_CORE_1
+CPU_CORE_NB
OO
OO
O
X
XX
X
1001 101X b
1001 100X b
X
SMBUS Control Table
SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
SCL
SDA
DDC4CLK
DDC4DATA
DDC3CLK
DDC3DATA
SCL0
SDA0
SCL1
SDA1
SCL2
SDA2
SCL3
SDA3
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
SOURCE
KB926
KB926
VGA
M82-SE
VGA
M82-SE
VGA
M82-SE
SB700
SB700
SB700
SB700
Symbol Note :
: means Digital Ground
: means Analog Ground
@ : means just reserve , no build
DEBUG@ : means just reserve for debug.
THERMAL
SENSOR
VGA M82-SE
ADM1032
X
V
SERIAL SENSOR
BATT EEPROM
X
V
XX
XXX X X X X
XXX X X
XXX X X
XXX X X
XXXX
XXXX
XXXX
Compal Secret Data
Compal Secret Data
2007/10/11 200810/11
2007/10/11 200810/11
2007/10/11 200810/11
C
Compal Secret Data
THERMAL
CPU &
ADM1032
XX
V
Deciphered Date
Deciphered Date
Deciphered Date
SODIMM CLK CHIP
I / II
WL
MINI CARD
Slot 1
XX
XXXX
XXX
LCD
X
V
HDMI
X
X
X
V
XXX X
VV
XX
D
V
X
X
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
XX
XXXX
XXXX
XX
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
SCHEMATIC MB A4112
SCHEMATIC MB A4112
SCHEMATIC MB A4112
401568
401568
401568
E
CRT
X
X
X
X
V
X
X
X
X
G-Sensor
X
X
X
X
X
V
X
X
X
of
of
of
354Friday, February 13, 2009
354Friday, February 13, 2009
354Friday, February 13, 2009
F
F
F
A
B
C
D
E
1 1
+VLDT_B
AE2
AE3
AE4
AE5
AD1
AC1
AC2
AC3
AB1
AA1
AA2
AA3
W2
W3
V1
U1
U2
U3
T1
R1
AD4
AD3
AD5
AC5
AB4
AB3
AB5
AA5
Y5
W5
V4
V3
V5
U5
T4
T3
Y1
W1
Y4
Y3
R2
R3
T5
R5
H_CADOP[0..15]
H_CADON[0..15]
1 2
C7 4.7U_0805_10V4ZC7 4.7U_0805_10V4Z
If VLDT is connected only on one side, one
4.7uF cap should be added to the island
H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7
H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15
side.
H_CADOP[0..15] <10>
H_CADON[0..15] <10>H_CADIN[0..15]<10>
H_CLKOP0 <10>
H_CLKON0 <10>
H_CLKOP1 <10>
H_CLKON1 <10>
H_CTLOP0 <10>
H_CTLON0 <10>H_CTLIN0<10>
H_CTLON1 <10>
PWM Fan Control circuit
H_CADIP[0..15]<10>
2 2
H_CLKIP0<10>
H_CLKIN0<10>
H_CLKIP1<10>
3 3
H_CLKIN1<10>
H_CTLIP0<10>
H_CTLIP1<10> H_CTLOP1 <10>
H_CTLIN1<10>
H_CADIP[0..15]
H_CADIN[0..15]
1.5A(+-60mV_dc,
+-75mV_ac)
+1.2V_HT
H_CADIP0
H_CADIN0
H_CADIP1
H_CADIN1
H_CADIP2
H_CADIN2
H_CADIP3
H_CADIN3
H_CADIP4
H_CADIN4
H_CADIP5
H_CADIN5
H_CADIP6
H_CADIN6
H_CADIP7
H_CADIN7
H_CADIP8
H_CADIN8
H_CADIP9
H_CADIN9
H_CADIP10
H_CADIN10
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIP13
H_CADIN13
H_CADIP14
H_CADIN14
H_CADIP15
H_CADIN15
JCPUA
JCPUA
HT LINK
D1
D2
D3
D4
E3
E2
E1
F1
G3
G2
G1
H1
J1
K1
L3
L2
L1
M1
N3
N2
E5
F5
F3
F4
G5
H5
H3
H4
K3
K4
L5
M5
M3
M4
N5
P5
J3
J2
J5
K5
N1
P1
P3
P4
HT LINK
VLDT_A0
VLDT_A1
VLDT_A2
VLDT_A3
L0_CADIN_H0
L0_CADIN_L0
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H15
L0_CADIN_L15
L0_CLKIN_H0
L0_CLKIN_L0
L0_CLKIN_H1
L0_CLKIN_L1
L0_CTLIN_H0
L0_CTLIN_L0
L0_CTLIN_H1
L0_CTLIN_L1
FOX_PZ6382A-284S-41F_GRIFFIN
FOX_PZ6382A-284S-41F_GRIFFIN
CONN@
CONN@
Athlon 64 S1
Processor Socket
VLDT_B0
VLDT_B1
VLDT_B2
VLDT_B3
L0_CADOUT_H0
L0_CADOUT_L0
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H15
L0_CADOUT_L15
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
+1.2V_HT
250 mil
1
C1
C1
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
FAN_PWM<40>
1
C2
C2
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
CH751H-40PT_SOD323-2
CH751H-40PT_SOD323-2
VLDT CAP.
1
C3
C3
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
Near CPU Socket
+5VS
D1
D1
2 1
6
2
1
D
D
Q1
Q1
G
G
3
S
S
SI3456BDV-T1-E3_TSOP6
SI3456BDV-T1-E3_TSOP6
4 5
1
C4
C4
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C8
C8
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
+VCC_FAN
1
C5
C5
180P_0402_50V8J
180P_0402_50V8J
2
1
C9
@C9
@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
12
D2
@D2
@
RLZ5.1B_LL34
RLZ5.1B_LL34
1
C6
C6
180P_0402_50V8J
180P_0402_50V8J
2
JP2
JP2
1
1
2
2
3
GND
4
GND
ACES_88231-02001
ACES_88231-02001
CONN@
CONN@
4 4
A
B
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2007/10/11 200810/11
2007/10/11 200810/11
2007/10/11 200810/11
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC MB A4112
SCHEMATIC MB A4112
SCHEMATIC MB A4112
401568
401568
401568
454Friday, February 13, 2009
454Friday, February 13, 2009
454Friday, February 13, 2009
E
of
of
of
F
F
F
A
B
C
D
E
Processor DDR2 Memory Interface
PLACE CLOSE TO PROCESSOR
1 1
2 2
D10
C10
Place them close to CPU within 1"
MEMZP/N=W/S=5mil/10mil
DDR_CS0_DIMMA#<8>
DDR_CS1_DIMMA#<8> DDR_CS0_DIMMB# <9>
DDR_CKE0_DIMMA<8>
DDR_CKE1_DIMMA<8>
3 3
4 4
DDR_A_CLK#0<8>
DDR_A_CLK#1<8>
DDR_A_MA[15..0]<8> DDR_B_MA[15..0] <9>
+1.8V
DDR_A_ODT0<8>
DDR_A_ODT1<8>
DDR_A_CLK0<8>
DDR_A_CLK1<8>
DDR_A_BS#0<8>
DDR_A_BS#1<8>
DDR_A_BS#2<8>
DDR_A_RAS#<8>
DDR_A_CAS#<8>
DDR_A_WE#<8>
R4 39.2_0402_1%
R4 39.2_0402_1%
1 2
1 2
R3 39.2_0402_1%
R3 39.2_0402_1%
T2 PADT2 PAD
DDR_A_ODT0
DDR_A_ODT1
DDR_CS0_DIMMA#
DDR_CS1_DIMMA# DDR_CS0_DIMMB#
DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK1
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
A
B10
AD10
MEMZP
AF10
MEMZN VTT_SENSE
AE10
H16
T19
V22
U21
V19
T20
U19
U20
V20
J22
J20
N19
N20
E16
F16
Y16
AA16
P19
P20
N21
M20
N22
M19
M22
L20
M24
L21
L19
K22
R21
L22
K20
V24
K24
K19
R20
R23
J21
R19
T22
T24
WITHIN 1.5 INCH
DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK1
DDR_A_CLK#1
DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK1
DDR_B_CLK#1
JCPUB
JCPUB
VTT1
MEM:CMD/CTRL/CLK
MEM:CMD/CTRL/CLK
VTT2
VTT3
VTT4
MEMZP
MEMZN
RSVD_M1
MA0_ODT0
MA0_ODT1
MA1_ODT0
MA1_ODT1
MA0_CS_L0
MA0_CS_L1
MA1_CS_L0
MA1_CS_L1
MA_CKE0
MA_CKE1
MA_CLK_H5
MA_CLK_L5
MA_CLK_H1
MA_CLK_L1
MA_CLK_H7
MA_CLK_L7
MA_CLK_H4
MA_CLK_L4
MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14
MA_ADD15
MA_BANK0
MA_BANK1
MA_BANK2
MA_RAS_L
MA_CAS_L
MA_WE_L
FOX_PZ6382A-284S-41F_GRIFFIN
FOX_PZ6382A-284S-41F_GRIFFIN
Athlon 64 S1
Processor
Socket
CONN@
CONN@
B
1
2
1
2
1
2
1
2
VTT_SENSE
MEMVREF
RSVD_M2
MB0_ODT0
MB0_ODT1
MB1_ODT0
MB0_CS_L0
MB0_CS_L1
MB1_CS_L0
MB_CKE0
MB_CKE1
MB_CLK_H5
MB_CLK_L5
MB_CLK_H1
MB_CLK_L1
MB_CLK_H7
MB_CLK_L7
MB_CLK_H4
MB_CLK_L4
MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8
MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15
MB_BANK0
MB_BANK1
MB_BANK2
MB_RAS_L
MB_CAS_L
MB_WE_L
C10
C10
1.5P_0402_50V9C
1.5P_0402_50V9C
C11
C11
1.5P_0402_50V9C
1.5P_0402_50V9C
C14
C14
1.5P_0402_50V9C
1.5P_0402_50V9C
C15
C15
1.5P_0402_50V9C
1.5P_0402_50V9C
W10
VTT5
AC10
VTT6
AB10
VTT7
AA10
VTT8
A10
VTT9
Y10
W17
B18
W26
W23
Y26
V26
W25
U22
J25
H26
P22
R22
A17
A18
AF18
AF17
R26
R25
P24
N24
P26
N23
N26
L23
N25
L24
M26
K26
T26
L26
L25
W24
J23
J24
R24
U26
J26
U25
U24
U23
+0.9V+0.9V
750mA(+-50mV_dc,
+-75mV_ac)
+MCH_REF
DDR_B_ODT0
DDR_B_ODT1
DDR_CS1_DIMMB#
DDR_CKE0_DIMMB
DDR_CKE1_DIMMB
DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK1
DDR_B_CLK#1DDR_A_CLK#1
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2
DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#
JCPUC
DDR_B_D[63..0]<9>
+1.8V
R1
R1
1K_0402_1%
1K_0402_1%
1 2
+MCH_REF
1
R2
R2
C12
1K_0402_1%
1K_0402_1%
C12
1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
VTT_SENSE=W/S=10mil/10mil
T1PAD T1PAD
T3PAD T3PAD
DDR_B_ODT0 <9>
DDR_B_ODT1 <9>
DDR_CS1_DIMMB# <9>
DDR_CKE0_DIMMB <9>
DDR_CKE1_DIMMB <9>
DDR_B_CLK0 <9>
DDR_B_CLK#0 <9>
DDR_B_CLK1 <9>
DDR_B_CLK#1 <9>
DDR_B_BS#0 <9>
DDR_B_BS#1 <9>
DDR_B_BS#2 <9>
DDR_B_RAS# <9>
DDR_B_CAS# <9>
DDR_B_WE# <9>
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C13
C13
2
1000P_0402_25V8J
1000P_0402_25V8J
C
1
2
DDR_B_DM[7..0]<9> DDR_A_DM[7..0] <8>
DDR_B_DQS0<9>
DDR_B_DQS#0<9>
DDR_B_DQS1<9>
DDR_B_DQS#1<9>
DDR_B_DQS2<9>
DDR_B_DQS#2<9>
DDR_B_DQS3<9>
DDR_B_DQS#3<9>
DDR_B_DQS4<9>
DDR_B_DQS#4<9>
DDR_B_DQS5<9>
DDR_B_DQS#5<9>
DDR_B_DQS6<9>
DDR_B_DQS#6<9>
DDR_B_DQS7<9>
DDR_B_DQS#7<9>
2007/10/11 200810/11
2007/10/11 200810/11
2007/10/11 200810/11
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
DDR_B_DQS0
DDR_B_DQS#0
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS7
DDR_B_DQS#7
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
JCPUC
C11
MB_DATA0
A11
MB_DATA1
A14
MB_DATA2
B14
MB_DATA3
G11
MB_DATA4
E11
MB_DATA5
D12
MB_DATA6
A13
MB_DATA7
A15
MB_DATA8
A16
MB_DATA9
A19
MB_DATA10
A20
MB_DATA11
C14
MB_DATA12
D14
MB_DATA13
C18
MB_DATA14
D18
MB_DATA15
D20
MB_DATA16
A21
MB_DATA17
D24
MB_DATA18
C25
MB_DATA19
B20
MB_DATA20
C20
MB_DATA21
B24
MB_DATA22
C24
MB_DATA23
E23
MB_DATA24
E24
MB_DATA25
G25
MB_DATA26
G26
MB_DATA27
C26
MB_DATA28
D26
MB_DATA29
G23
MB_DATA30
G24
MB_DATA31
AA24
MB_DATA32
AA23
MB_DATA33
AD24
MB_DATA34
AE24
MB_DATA35
AA26
MB_DATA36
AA25
MB_DATA37
AD26
MB_DATA38
AE25
MB_DATA39
AC22
MB_DATA40
AD22
MB_DATA41
AE20
MB_DATA42
AF20
MB_DATA43
AF24
MB_DATA44
AF23
MB_DATA45
AC20
MB_DATA46
AD20
MB_DATA47
AD18
MB_DATA48
AE18
MB_DATA49
AC14
MB_DATA50
AD14
MB_DATA51
AF19
MB_DATA52
AC18
MB_DATA53
AF16
MB_DATA54
AF15
MB_DATA55
AF13
MB_DATA56
AC12
MB_DATA57
AB11
MB_DATA58
Y11
MB_DATA59
AE14
MB_DATA60
AF14
MB_DATA61
AF11
MB_DATA62
AD11
MB_DATA63
A12
MB_DM0
B16
MB_DM1
A22
MB_DM2
E25
MB_DM3
AB26
MB_DM4
AE22
MB_DM5
AC16
MB_DM6
AD12
MB_DM7
C12
MB_DQS_H0
B12
MB_DQS_L0
D16
MB_DQS_H1
C16
MB_DQS_L1
A24
MB_DQS_H2
A23
MB_DQS_L2
F26
MB_DQS_H3
E26
MB_DQS_L3
AC25
MB_DQS_H4
AC26
MB_DQS_L4
AF21
MB_DQS_H5
AF22
MB_DQS_L5
AE16
MB_DQS_H6
AD16
MB_DQS_L6
AF12
MB_DQS_H7
AE12
MB_DQS_L7
FOX_PZ6382A-284S-41F_GRIFFIN
FOX_PZ6382A-284S-41F_GRIFFIN
Athlon 64 S1
Processor Socket
CONN@
CONN@
D
MEM:DATA
MEM:DATA
MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63
MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7
MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
DDR_A_D1
F12
DDR_A_D2
H14
DDR_A_D3
G14
DDR_A_D4
H11
DDR_A_D5
H12
DDR_A_D6
C13
DDR_A_D7
E13
DDR_A_D8
H15
DDR_A_D9
E15
DDR_A_D10
E17
DDR_A_D11
H17
DDR_A_D12
E14
DDR_A_D13
F14
DDR_A_D14
C17
DDR_A_D15
G17
DDR_A_D16
G18
DDR_A_D17
C19
DDR_A_D18
D22
DDR_A_D19
E20
DDR_A_D20
E18
DDR_A_D21
F18
DDR_A_D22
B22
DDR_A_D23
C23
DDR_A_D24
F20
DDR_A_D25
F22
DDR_A_D26
H24
DDR_A_D27
J19
DDR_A_D28
E21
DDR_A_D29
E22
DDR_A_D30
H20
DDR_A_D31
H22
DDR_A_D32
Y24
DDR_A_D33
AB24
DDR_A_D34
AB22
DDR_A_D35
AA21
DDR_A_D36
W22
DDR_A_D37
W21
DDR_A_D38
Y22
DDR_A_D39
AA22
DDR_A_D40
Y20
DDR_A_D41
AA20
DDR_A_D42
AA18
DDR_A_D43
AB18
DDR_A_D44
AB21
DDR_A_D45
AD21
DDR_A_D46
AD19
DDR_A_D47
Y18
DDR_A_D48
AD17
DDR_A_D49
W16
DDR_A_D50
W14
DDR_A_D51
Y14
DDR_A_D52
Y17
DDR_A_D53
AB17
DDR_A_D54
AB15
DDR_A_D55
AD15
DDR_A_D56
AB13
DDR_A_D57
AD13
DDR_A_D58
Y12
DDR_A_D59
W11
DDR_A_D60
AB14
DDR_A_D61
AA14
DDR_A_D62
AB12
DDR_A_D63
AA12
DDR_A_DM0
E12
DDR_A_DM1
C15
DDR_A_DM2
E19
DDR_A_DM3
F24
DDR_A_DM4
AC24
DDR_A_DM5
Y19
DDR_A_DM6
AB16
DDR_A_DM7
Y13
DDR_A_DQS0
G13
DDR_A_DQS#0
H13
DDR_A_DQS1
G16
DDR_A_DQS#1
G15
DDR_A_DQS2
C22
DDR_A_DQS#2
C21
DDR_A_DQS3
G22
DDR_A_DQS#3
G21
DDR_A_DQS4
AD23
DDR_A_DQS#4
AC23
DDR_A_DQS5
AB19
DDR_A_DQS#5
AB20
DDR_A_DQS6
Y15
DDR_A_DQS#6
W15
DDR_A_DQS7
W12
DDR_A_DQS#7
W13
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
SCHEMATIC MB A4112
SCHEMATIC MB A4112
SCHEMATIC MB A4112
401568
401568
401568
DDR_A_D0
G12
DDR_A_D[63..0] <8>
DDR_A_DQS0 <8>
DDR_A_DQS#0 <8>
DDR_A_DQS1 <8>
DDR_A_DQS#1 <8>
DDR_A_DQS2 <8>
DDR_A_DQS#2 <8>
DDR_A_DQS3 <8>
DDR_A_DQS#3 <8>
DDR_A_DQS4 <8>
DDR_A_DQS#4 <8>
DDR_A_DQS5 <8>
DDR_A_DQS#5 <8>
DDR_A_DQS6 <8>
DDR_A_DQS#6 <8>
DDR_A_DQS7 <8>
DDR_A_DQS#7 <8>
E
F
F
F
of
of
of
554Friday, February 13, 2009
554Friday, February 13, 2009
554Friday, February 13, 2009
A
250mA(+-100mV_dc,
+-150mV_ac)
1 1
CLK_CPU_BCLK<22>
LDT_RST#=4mil/12mil
2 2
LDT_RST#<26>
H_PWRGD_CPU=4mil/12mil
H_PWRGD_CPU<26,50>
3 3
LDT_STOP#=4mil/12mil
LDT_STOP#<11,26>
0718 AMD , need check with AMD
+1.8VS
4 4
CPU_LDT_REQ#=4mil/12mil
R30
R30
300_0402_5%
300_0402_5%
1 2
CPU_LDT_REQ#
1
C24
C24
0.01U_0402_25V4Z
0.01U_0402_25V4Z
@
@
2
+1.8VS
R15
R15
300_0402_5%
300_0402_5%
1 2
LDT_RST#
1
C22
C22
0.01U_0402_25V4Z
0.01U_0402_25V4Z
@
@
2
+1.8VS
R21
R21
300_0402_5%
300_0402_5%
1 2
H_PWRGD_CPU
1
C23
C23
0.01U_0402_25V4Z
0.01U_0402_25V4Z
@
@
2
+1.8VS
R36
R36
300_0402_5%
300_0402_5%
1 2
LDT_STOP#
1
C25
C25
0.01U_0402_25V4Z
0.01U_0402_25V4Z
@
@
2
CPU_LDT_REQ# <11,26>
A
0718 Silego -- 216 ohm
CLK_CPU_BCLK#<22>
+CPU_CORE_0
+CPU_CORE_1
+1.8V
+1.8V
C27
C27
1 2
2200p change to
1000p for ADT7421
+2.5VS
100U_D2_10VM
100U_D2_10VM
R487 10_0402_5%
R487 10_0402_5%
1 2
1 2
R486 10_0402_5% R486 10_0402_5%
R489 10_0402_5%
R489 10_0402_5%
1 2
1 2
R488 10_0402_5%
R488 10_0402_5%
@R175
@
+3VS
20K_0402_5%
20K_0402_5%
R18
R18
2.2K_0402_5%
2.2K_0402_5%
R19
R19
2.2K_0402_5%
2.2K_0402_5%
CPU_SIC
+3VS
1
C26
C26
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2200P_0402_50V7K
2200P_0402_50V7K
C16
@+C16
@
Place close to CPU wihtin 1.5"
C20
C20
C21 3900P_0402_50V7K
C21 3900P_0402_50V7K
CPU_VDD0_FB_H/L(Differential
pair)=10/5/5/5/10
CPU_VDD1_FB_H/L(Differential
pair)=10/5/5/5/10
CPU_VDD0_FB_H
CPU_VDD0_FB_L
Close to CPU
CPU_VDD1_FB_H
CPU_VDD1_FB_L
R175
12
G
G
S
S
Q127
@
Q127
@
12
FDV301N_NL_SOT23-3
FDV301N_NL_SOT23-3
12
FDV301N_NL_SOT23-3
FDV301N_NL_SOT23-3
Q129
@
Q129
@
THERMDA_CPU
THERMDC_CPU
B
L1
L1
1 2
FBM_L11_201209_300L_0805
FBM_L11_201209_300L_0805
1
+
2
3900P_0402_50V7K
3900P_0402_50V7K
1 2
12
R8
R8
169_0402_1%
169_0402_1%
1 2
1 2
C939 0.1U_0402_16V4Z@C939 0.1U_0402_16V4Z@
R814
@R814
@
12
34.8K_0402_1%~N
34.8K_0402_1%~N
2
SMB_EC_DA1CPU_SID
13
D
D
G
G
2
SMB_EC_CK1
13
D
S
D
S
EC is PU to 5VALW
FDV301N, the Vgs is:
min = 0.65V
Typ = 0.85V
Max = 1.5V
U2
U2
1
VDD
D+
SDATA
ALERT#
DÂTHERM#4GND
B
SCLK
2
3
ADM1032ARMZ-2REEL_MSOP8
ADM1032ARMZ-2REEL_MSOP8
Address:100_1101
+2.5VDDA
VDDA=300mA
3300P_0402_50V7K
3300P_0402_50V7K
1
1
C174.7U_0805_10V4Z C174.7U_0805_10V4Z
2
2
Address:100_1100
R13 44.2_0402_1%R13 44.2_0402_1%
R14 44.2_0402_1%R14 44.2_0402_1%
+1.2V_HT
2.09V for Gate
SMB_EC_DA1 <39,40,44>
SMB_EC_CK1 <39,40,44>
8
7
6
5
1
C19
C19
C18
C18
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
CPU_CLKIN_SC_P
CPU_CLKIN_SC_N
LDT_RST#
H_PWRGD_CPU
LDT_STOP#
CPU_LDT_REQ#
CPU_SIC
CPU_SID
1 2
1 2
CPU_VDD0_FB_H<50>
CPU_VDD0_FB_L<50>
CPU_VDD1_FB_H<50>
CPU_VDD1_FB_L<50>
CPU_DBRDY
CPU_TMS
CPU_TCK
CPU_TRST#
CPU_TDI
CPU_TEST23_TSTUPD
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1
CPU_TEST25_H_BYPASSCLK_H
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST21_SCANEN
CPU_TEST20_SCANCLK2
CPU_TEST24_SCANCLK1
CPU_TEST22_SCANSHIFTEN
CPU_TEST12_SCANSHIFTENB
CPU_TEST27_SINGLECHAIN
R25 0_0402_5%R25 0_0402_5%
1 2
SMB_EC_CK2 <21,40>
SMB_EC_DA2 <21,40>
C
D
CPU_THERMTRIP#_R/ENTRIP2/H_THERMTRIP#=4mil/12mil
+1.8V
JCPUD
JCPUD
F8
VDDA1
F9
VDDA2
A9
CLKIN_H
A8
CLKIN_L
B7
RESET_L
A7
PWROK
F10
LDTSTOP_L
C6
LDTREQ_L
AF4
SIC
AF5
SID
AE6
CPU_HTREF0
CPU_HTREF1
CPU_VDD0_FB_H
CPU_VDD0_FB_L
CPU_VDD1_FB_H
CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO
NOTE: HDT TERMINATION IS REQUIRED
FOR REV. Ax SILICON ONLY.
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ALERT_L
R6
HT_REF0
P6
HT_REF1
F6
VDD0_FB_H
E6
VDD0_FB_L
Y6
VDD1_FB_H
AB6
VDD1_FB_L
G10
DBRDY
AA9
TMS
AC9
TCK
AD9
TRST_L
AF9
TDI
AD7
TEST23
H10
TEST18
G9
TEST19
E9
TEST25_H
E8
TEST25_L
AB8
TEST21
AF7
TEST20
AE7
TEST24
AE8
TEST22
AC8
TEST12
AF8
TEST27
C2
TEST9
AA6
TEST6
A3
RSVD1
A5
RSVD2
B3
RSVD3
B5
RSVD4
C1
RSVD5
FOX_PZ6382A-284S-41F_GRIFFIN
FOX_PZ6382A-284S-41F_GRIFFIN
CONN@
CONN@
12
C
THERMTRIP_L
PROCHOT_L
VDDIO_FB_H
VDDIO_FB_L
VDDNB_FB_H
VDDNB_FB_L
+1.8V
R39220_0402_5%@ R39220_0402_5%@
R37220_0402_5%@ R37220_0402_5%@
R38220_0402_5%@ R38220_0402_5%@
R40220_0402_5%@ R40220_0402_5%@
12
12
12
12
2007/10/11 200810/11
2007/10/11 200810/11
2007/10/11 200810/11
M11
KEY1
W18
KEY2
CPU_SVC
A6
SVC
CPU_SVD
A4
SVD
CPU_THERMTRIP#_R
AF6
CPU_PROCHOT#_1.8
AC7
CPU_MEMHOT#_1.8V
AA8
MEMHOT_L
THERMDC_CPU
W7
THERMDC
THERMDA
DBREQ_L
TEST28_H
TEST28_L
TEST17
TEST16
TEST15
TEST14
TEST10
TEST29_H
TEST29_L
RSVD10
RSVD9
RSVD8
RSVD7
RSVD6
R41300_0402_5% R41300_0402_5%
THERMDA_CPU
W8
VDDIO_FB_H
W9
VDDIO_FB_L
Y9
VDD_NB_FB_H
H6
VDD_NB_FB_LCPU_VDD1_FB_L
G6
CPU_DBREQ#
E10
CPU_TDO
AE9
TDO
CPU_TEST28_H_PLLCHRZ_P
J7
CPU_TEST28_L_PLLCHRZ_N
H8
CPU_TEST17_BP3
D7
CPU_TEST16_BP2
E7
CPU_TEST15_BP1
F7
CPU_TEST14_BP0
C7
C3
TEST7
K8
C4
TEST8
CPU_TEST29_H_FBCLKOUT_P
C9
CPU_TEST29_L_FBCLKOUT_N
C8
H18
H19
AA7
D5
C5
HDT Connector
@SAMTEC_ASP-68200-07
@
9/20 SP020016900
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
CPU_SVC <50>
CPU_SVD <50>
VDD_NB_FB_H <50>
VDD_NB_FB_L <50>
JP3
JP3
2
1
4
3
6
5
8
7
10
9
12
11
14
13
16
15
18
17
20
19
22
21
2423
26
SAMTEC_ASP-68200-07
R17
R17
12
300_0402_5%@
300_0402_5%@
+1.8V sense no support
T42PAD T42PAD
VDDIO_FB_H/L=10mil/10mil
T43PAD T43PAD
D
+1.8V
VDD_NB_FB_H/L(Differential
pair)=10/5/5/5/10
T5PAD T5PAD
T6PAD T6PAD
testpoint under package
T7PAD T7PAD
T8PAD T8PAD
T10PAD T10PAD
T12PAD T12PAD
CPU_TEST29_H_FBCLKOUT_P
/CPU_TEST29_L_FBCLKOUT_N (85ohm
T13PAD T13PAD
T14PAD T14PAD
Differential pair)
U1
HDT_RST#
4
1 2
R10 10K_0402_5%
R10 10K_0402_5%
1 2
R5 300_0402_5%
R5 300_0402_5%
CPU_THERMTRIP#_R
B
B
2
Q3
Q3
E
E
3 1
C
C
MMBT3904_NL_SOT23-3
+1.8V
MMBT3904_NL_SOT23-3
1 2
R9 300_0402_5% R9 300_0402_5%
CPU_PROCHOT#_1.8
CPU_PROCHOT#_1.8/H_PROCHOT#=4mil/12mil
route as differential
as short as possible
+3VS
5
P
B
Y
A
G
NC7SZ08P5X_NL_SC70-5@U1NC7SZ08P5X_NL_SC70-5@
3
CPU_TEST28_H_PLLCHRZ_P
/CPU_TEST28_L_PLLCHRZ_N (85ohm
Differential pair)
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST27_SINGLECHAIN
CPU_TEST21_SCANEN
CPU_TEST20_SCANCLK2
CPU_TEST24_SCANCLK1
CPU_TEST22_SCANSHIFTEN
CPU_TEST12_SCANSHIFTENB
CPU_TEST15_BP1
CPU_TEST14_BP0
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1
CPU_TEST23_TSTUPD
CPU_TEST25_H_BYPASSCLK_H
LDT_RST#
2
1
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
SB_PWRGD <27,40,50>
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
SCHEMATIC MB A4112
SCHEMATIC MB A4112
SCHEMATIC MB A4112
401568
401568
401568
E
R6 0_0402_5%@R6 0_0402_5%@
1 2
1 2
R7 0_0402_5%R7 0_0402_5%
1 2
R11 0_0402_5%@R11 0_0402_5%@
R22 1K_0402_5%R22 1K_0402_5%
CPU_SVC
1 2
CPU_SVD
1 2
R23 1K_0402_5%R23 1K_0402_5%
0718 AMD --> 1K ohm
R484 10_0402_5%
VDD_NB_FB_H
VDD_NB_FB_L
R484 10_0402_5%
1 2
1 2
R485 10_0402_5% R485 10_0402_5%
Close to CPU
R59 300_0402_5%@R59 300_0402_5%@
1 2
R24 300_0402_5%@R24 300_0402_5%@
1 2
R26 300_0402_5%R26 300_0402_5%
1 2
R27 300_0402_5%@R27 300_0402_5%@
R28 300_0402_5%R28 300_0402_5%
R29 300_0402_5%@R29 300_0402_5%@
R31 300_0402_5%@R31 300_0402_5%@
R32 300_0402_5%@R32 300_0402_5%@
R33 300_0402_5%@R33 300_0402_5%@
R34 300_0402_5%@R34 300_0402_5%@
R35 300_0402_5%@R35 300_0402_5%@
R60 300_0402_5%@R60 300_0402_5%@
R61 300_0402_5%@R61 300_0402_5%@
E
EN0 <44,46>
H_THERMTRIP# <27,40>
H_PROCHOT# <26>
+1.8V
+CPU_CORE_NB
+1.8V
12
12
12
12
12
12
12
12
12
12
of
of
of
654Friday, February 13, 2009
654Friday, February 13, 2009
654Friday, February 13, 2009
F
F
F
A
VDD(+CPU_CORE) decoupling.
+CPU_CORE_0
1
+
+
C30
1 1
C30
330U_X_2VM_R6M
330U_X_2VM_R6M
2
+CPU_CORE_0
1
C32
C32
22U_0805_6.3V6M
22U_0805_6.3V6M
2
+CPU_CORE_0
1
C40
C40
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
2 2
1
C33
C33
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C41
C41
0.01U_0402_25V4Z
0.01U_0402_25V4Z
2
1
+
+
2
1
C34
C34
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C42
C42
180P_0402_50V8J
180P_0402_50V8J
2
C28
C28
330U_X_2VM_R6M
330U_X_2VM_R6M
Near CPU Socket
1
C35
C35
22U_0805_6.3V6M
22U_0805_6.3V6M
2
Under CPU Socket
VDDIO decoupling.
+1.8V
1
C46
C46
22U_0805_6.3V6M
22U_0805_6.3V6M
2
3 3
+1.8V
1
C55
C55
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
+1.8V +1.8V
1
C60
C60
0.01U_0402_25V4Z
0.01U_0402_25V4Z
2
4 4
+1.8V
1
2
C74
C74
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
C47
C47
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C48
C48
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
Under CPU Socket
Between CPU Socket and DIMM
1
C57
C57
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
2
1
2
1
C56
C56
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C61
C61
0.01U_0402_25V4Z
0.01U_0402_25V4Z
2
1
C75
C75
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
A
1
C49
C49
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
2
180PF Qt'y follow the distance between
CPU socket and DIMM0. <2.5inch>
C62
C62
180P_0402_50V8J
180P_0402_50V8J
C76
C76
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
2
1
180P_0402_50V8J
180P_0402_50V8J
2
C58
C58
0.22U_0603_16V4Z
0.22U_0603_16V4Z
1
C63
C63
180P_0402_50V8J
180P_0402_50V8J
2
A: Add C165 and C176
to follow AMD Layout
review recommand for
EMI
C77
C77
4.7U_0805_10V4Z
4.7U_0805_10V4Z
B
+CPU_CORE_1
1
+
+
2
+CPU_CORE_1
1
C36
C36
22U_0805_6.3V6M
22U_0805_6.3V6M
2
C50
C50
1
C51
C51
180P_0402_50V8J
180P_0402_50V8J
2
1
C64
C64
180P_0402_50V8J
180P_0402_50V8J
2
1
C: Change to NBO CAP
+
+
C78
C78
220U_Y_4VM
220U_Y_4VM
@
@
2
B
C31
C31
330U_X_2VM_R6M
330U_X_2VM_R6M
1
2
+CPU_CORE_1
1
C43
C43
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C65
C65
180P_0402_50V8J
180P_0402_50V8J
2
C37
C37
22U_0805_6.3V6M
22U_0805_6.3V6M
1
+
+
C29
C29
330U_X_2VM_R6M
330U_X_2VM_R6M
2
1
C38
C38
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C44
C44
0.01U_0402_25V4Z
0.01U_0402_25V4Z
2
1
C39
C39
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C45
C45
180P_0402_50V8J
180P_0402_50V8J
2
C
VDD_dc & VDDNB_dc
transient < 5us
0.8V~1.1V, 3A(+-25mV_dc,
+-125mV_ac)
2A(+-100mV_dc,
+-150mV_ac)
0.7V~1.2V, 18A/35W,
18A/7200mil/36vias 18A/7200mil/36vias
+CPU_CORE_NB
+1.8V
10A/20W(+-25mV_dc,
+-125mV_ac)
JCPUE
JCPUE
G4
H2
J9
J11
J13
J15
K6
K10
K12
K14
L4
L7
L9
L11
L13
L15
M2
M6
M8
M10
N7
N9
N11
K16
M16
P16
T16
V16
H25
J17
K18
K21
K23
K25
L17
M18
M21
M23
M25
N17
FOX_PZ6382A-284S-41F_GRIFFIN
FOX_PZ6382A-284S-41F_GRIFFIN
Athlon 64 S1
Processor Socket
CONN@
CONN@
VDD0_1
VDD0_2
VDD0_3
VDD0_4
VDD0_5
VDD0_6
VDD0_7
VDD0_8
VDD0_9
VDD0_10
VDD0_11
VDD0_12
VDD0_13
VDD0_14
VDD0_15
VDD0_16
VDD0_17
VDD0_18
VDD0_19
VDD0_20
VDD0_21
VDD0_22
VDD0_23
VDDNB_1
VDDNB_2
VDDNB_3
VDDNB_4
VDDNB_5
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
D
VDD1_1
VDD1_2
VDD1_3
VDD1_4
VDD1_5
VDD1_6
VDD1_7
VDD1_8
VDD1_9
VDD1_10
VDD1_11
VDD1_12
VDD1_13
VDD1_14
VDD1_15
VDD1_16
VDD1_17
VDD1_18
VDD1_19
VDD1_20
VDD1_21
VDD1_22
VDD1_23
VDD1_24
VDD1_25
VDD1_26
VDDIO27
VDDIO26
VDDIO25
VDDIO24
VDDIO23
VDDIO22
VDDIO21
VDDIO20
VDDIO19
VDDIO18
VDDIO17
VDDIO16
VDDIO15
VDDIO14
VDDIO13
+CPU_CORE_NB decoupling.
+CPU_CORE_NB
1
C52
C52
22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C53
C53
22U_0805_6.3V6M
22U_0805_6.3V6M
2
VTT decoupling.
+0.9V
1
C66
C66
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
+0.9V
1
C79
C79
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
C67
C67
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
Near CPU Socket Right side.
1
C80
C80
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
Near CPU Socket Left side.
C
2007/10/11 200810/11
2007/10/11 200810/11
2007/10/11 200810/11
1
@C54
@
2
1
C68
C68
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C81
C81
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
C54
22U_0805_6.3V6M
22U_0805_6.3V6M
+0.9V
Near Power Supply
1
C: Change to NBO CAP
+
+
C59
C59
220U_Y_4VM
220U_Y_4VM
2
1
C69
C69
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C82
C82
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
1
C70
C70
1000P_0402_25V8J
1000P_0402_25V8J
2
1
C83
C83
1000P_0402_25V8J
1000P_0402_25V8J
2
D
P8
P10
R4
R7
R9
R11
T2
T6
T8
T10
T12
T14
U7
U9
U11
U13
U15
V6
V8
V10
V12
V14
W4
Y2
AC4
AD2
Y25
V25
V23
V21
V18
U17
T25
T23
T21
T18
R17
P25
P23
P21
P18
1
C71
C71
1000P_0402_25V8J
1000P_0402_25V8J
2
1
C84
C84
1000P_0402_25V8J
1000P_0402_25V8J
2
E
JCPUF
JCPUF
AA4
+CPU_CORE_1+CPU_CORE_0
+1.8V
1
C72
C72
180P_0402_50V8J
180P_0402_50V8J
2
1
C85
C85
180P_0402_50V8J
180P_0402_50V8J
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
VSS1
AA11
VSS2
AA13
VSS3
AA15
VSS4
AA17
VSS5
AA19
VSS6
AB2
VSS7
AB7
VSS8
AB9
VSS9
AB23
VSS10
AB25
VSS11
AC11
VSS12
AC13
VSS13
AC15
VSS14
AC17
VSS15
AC19
VSS16
AC21
VSS17
AD6
VSS18
AD8
VSS19
AD25
VSS20
AE11
VSS21
AE13
VSS22
AE15
VSS23
AE17
VSS24
AE19
VSS25
AE21
VSS26
AE23
VSS27
B4
VSS28
B6
VSS29
B8
VSS30
B9
VSS31
B11
VSS32
B13
VSS33
B15
VSS34
B17
VSS35
B19
VSS36
B21
VSS37
B23
VSS38
B25
VSS39
D6
VSS40
D8
VSS41
D9
VSS42
D11
VSS43
D13
VSS44
D15
VSS45
D17
VSS46
D19
VSS47
D21
VSS48
D23
VSS49
D25
VSS50
E4
VSS51
F2
VSS52
F11
VSS53
F13
VSS54
F15
VSS55
F17
VSS56
F19
VSS57
F21
VSS58
F23
VSS59
F25
VSS60
H7
VSS61
H9
VSS62
H21
VSS63
H23
VSS64
J4
VSS65
FOX_PZ6382A-284S-41F_GRIFFIN
FOX_PZ6382A-284S-41F_GRIFFIN
Athlon 64 S1
Processor Socket
CONN@
CONN@
1
C73
C73
180P_0402_50V8J
180P_0402_50V8J
2
1
C86
C86
180P_0402_50V8J
180P_0402_50V8J
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
SCHEMATIC MB A4112
SCHEMATIC MB A4112
SCHEMATIC MB A4112
401568
401568
401568
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
E
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
AC6
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6
F
F
F
of
of
of
754Friday, February 13, 2009
754Friday, February 13, 2009
754Friday, February 13, 2009
A
DDR_A_D0
DDR_A_D1
1 1
2 2
DDR_CKE0_DIMMA<5>
DDR_A_BS#2<5>
DDR_A_BS#0<5>
DDR_A_WE#<5>
DDR_A_CAS#<5>
DDR_CS1_DIMMA#<5>
DDR_A_ODT1<5>
3 3
SMB_CK_DAT0<9,22,27,37>
SMB_CK_CLK0<9,22,27,37>
4 4
+3VS
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D16 DDR_A_D20
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27
DDR_CKE0_DIMMA
DDR_A_BS#2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1 DDR_A_MA0
DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#
DDR_A_CAS# DDR_A_ODT0
DDR_CS1_DIMMA#
DDR_A_ODT1
DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_DM7
DDR_A_D58
DDR_A_D59
1
C103
C103
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
A
B
+V_DDR_MCH_REF
JP4
JP4
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
201
GND
TYCO_292527-4
TYCO_292527-4
CONN@
CONN@
DQ12
DQ13
CK0#
DQ14
DQ15
DQ20
DQ21
DQ22
DQ23
DQ28
DQ29
DQS3#
DQS3
DQ30
DQ31
NC/CKE1
NC/A15
NC/A14
RAS#
ODT0
NC/A13
DQ36
DQ37
DQ38
DQ39
DQ44
DQ45
DQS5#
DQS5
DQ46
DQ47
DQ52
DQ53
CK1#
DQ54
DQ55
DQ60
DQ61
DQS7#
DQS7
DQ62
DQ63
GND
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
VSS
DM1
VSS
CK0
VSS
VSS
VSS
VSS
DM2
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
BA1
VDD
VDD
VSS
VSS
DM4
VSS
VSS
VSS
VSS
VSS
VSS
CK1
VSS
DM6
VSS
VSS
VSS
VSS
VSS
SAO
SA1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
NC
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
A11
92
A7
94
A6
96
98
A4
100
A2
102
A0
104
106
108
110
S0#
112
114
116
118
120
NC
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
9/20 SP07000ET00/SP07000GN00
B
+1.8V+1.8V
C
DDR_A_D4
DDR_A_D5
DDR_A_DM0
DDR_A_D6
DDR_A_D7
DDR_A_D12
DDR_A_D13
DDR_A_DM1
DDR_A_D14
DDR_A_D15
DDR_A_D21
DDR_A_DM2
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDR_CKE1_DIMMA
DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#
DDR_A_MA13
DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DDR_A_D[0..63]
DDR_A_DM[0..7]
DDR_A_DQS[0..7]
DDR_A_MA[0..15]
DDR_A_DQS#[0..7]
DDR_A_CLK0 <5>
DDR_A_CLK#0 <5>
+V_DDR_MCH_REF
1
C95
C95
2
1000P_0402_25V8J
1000P_0402_25V8J
0.1U_0402_16V4Z
0.1U_0402_16V4Z
DDR_CKE1_DIMMA <5>
DDR_A_BS#1 <5>
DDR_A_RAS# <5>
DDR_CS0_DIMMA# <5>
DDR_A_ODT0 <5>
DDR_A_CLK1 <5>
DDR_A_CLK#1 <5>
C
DDR_A_D[0..63] <5>
DDR_A_DM[0..7] <5>
DDR_A_DQS[0..7] <5>
DDR_A_MA[0..15] <5>
DDR_A_DQS#[0..7] <5>
+1.8V
R43
R43
1K_0402_1%
1K_0402_1%
1 2
1
C96
C96
2
2007/10/11 200810/11
2007/10/11 200810/11
2007/10/11 200810/11
+V_DDR_MCH_REF <9>
R44
R44
1K_0402_1%
1K_0402_1%
1 2
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
+0.9V
RP1
DDR_A_MA11
DDR_A_MA14
DDR_A_MA7
DDR_A_MA6
DDR_A_MA15
DDR_CKE1_DIMMA
DDR_CKE0_DIMMA
DDR_A_BS#2
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS#1
DDR_A_MA5
DDR_A_MA8
DDR_A_MA9
DDR_A_MA12
DDR_A_BS#0
DDR_A_MA10
DDR_A_MA1
DDR_A_MA3
DDR_CS1_DIMMA#
DDR_A_ODT1
DDR_A_CAS#
DDR_A_WE#
DDR_A_RAS#
DDR_A_ODT0
DDR_A_MA13
DDR_CS0_DIMMA#
D
RP1
18
27
36
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
Cross between +1.8V and +0.9V power plan
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
45
RP2
RP2
18
27
36
45
RP3
RP3
18
27
36
45
RP4
RP4
18
27
36
45
RP5
RP5
18
27
36
45
RP6
RP6
18
27
36
45
RP7
RP7
18
27
36
45
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
SCHEMATIC MB A4112
SCHEMATIC MB A4112
SCHEMATIC MB A4112
401568
401568
401568
E
1 2
C87 0.1U_0402_16V4Z
C87 0.1U_0402_16V4Z
1 2
C88 0.1U_0402_16V4Z
C88 0.1U_0402_16V4Z
1 2
C90 0.1U_0402_16V4Z
C90 0.1U_0402_16V4Z
1 2
C89 0.1U_0402_16V4Z
C89 0.1U_0402_16V4Z
1 2
C91 0.1U_0402_16V4Z
C91 0.1U_0402_16V4Z
1 2
C92 0.1U_0402_16V4Z
C92 0.1U_0402_16V4Z
1 2
C93 0.1U_0402_16V4Z
C93 0.1U_0402_16V4Z
1 2
C94 0.1U_0402_16V4Z
C94 0.1U_0402_16V4Z
1 2
C98 0.1U_0402_16V4Z
C98 0.1U_0402_16V4Z
1 2
C97 0.1U_0402_16V4Z
C97 0.1U_0402_16V4Z
1 2
C100 0.1U_0402_16V4Z
C100 0.1U_0402_16V4Z
1 2
C99 0.1U_0402_16V4Z
C99 0.1U_0402_16V4Z
1 2
C102 0.1U_0402_16V4Z
C102 0.1U_0402_16V4Z
1 2
C101 0.1U_0402_16V4Z
C101 0.1U_0402_16V4Z
E
+1.8V
F
F
F
of
of
of
854Friday, February 13, 2009
854Friday, February 13, 2009
854Friday, February 13, 2009
A
B
C
D
E
JP5
JP5
+V_DDR_MCH_REF<8>
1
C104
C104
1 1
2
1000P_0402_25V8J
1000P_0402_25V8J
2 2
3 3
4 4
DDR_CKE0_DIMMB<5>
DDR_B_BS#2<5>
DDR_B_BS#0<5>
DDR_B_CAS#<5>
DDR_CS1_DIMMB#<5>
DDR_B_ODT1<5>
SMB_CK_DAT0<8,22,27,37>
SMB_CK_CLK0<8,22,27,37>
DDR_B_D0
DDR_B_D1
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D13
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D21
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_DM3
DDR_B_D26
DDR_B_D27
DDR_CKE0_DIMMB
DDR_B_BS#2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#
DDR_B_CAS#
DDR_CS1_DIMMB#
DDR_B_ODT1
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_DM7
DDR_B_D58
DDR_B_D59
+3VS
C119
C119
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
FOX_AS0A426-N8RN-7F
FOX_AS0A426-N8RN-7F
CONN@
CONN@
9/20 SP07000BZ00/SP07000EU00
DDR2 SOCKET H9.2 (REV)
VSS
201
NC/CKE1
NC/A15
NC/A14
NC/A13
VSS
202
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0#
VSS
DQ14
DQ15
VSS
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
VDD
VDD
VDD
VDD
RAS#
VDD
ODT0
VDD
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
VSS
DQ4
DQ5
VSS
CK0
A11
BA1
S0#
CK1
SA0
SA1
NC
A7
A6
A4
A2
A0
NC
A
B
+1.8V+1.8V
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DDR_B_D4
DDR_B_D5
DDR_B_DM0
DDR_B_D6
DDR_B_D7
DDR_B_D12
DDR_B_D9
DDR_B_DM1
DDR_B_D14
DDR_B_D15
DDR_B_D20
DDR_B_D16
DDR_B_DM2
DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31
DDR_CKE1_DIMMB
DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_BS#1
DDR_B_RAS#
DDR_CS0_DIMMB#
DDR_B_ODT0
DDR_B_MA13
DDR_B_D36
DDR_B_D37
DDR_B_DM4
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
+3VS
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
DDR_B_D[0..63]
DDR_B_DM[0..7]
DDR_B_DQS[0..7]
DDR_B_MA[0..15]
DDR_B_DQS#[0..7]
DDR_B_CLK0 <5>
DDR_B_CLK#0 <5>
DDR_CKE1_DIMMB <5>
DDR_B_BS#1 <5>
DDR_B_RAS# <5>
DDR_CS0_DIMMB# <5>DDR_B_WE#<5>
DDR_B_ODT0 <5>
DDR_B_CLK1 <5>
DDR_B_CLK#1 <5>
2007/10/11 200810/11
2007/10/11 200810/11
2007/10/11 200810/11
DDR_B_D[0..63] <5>
DDR_B_DM[0..7] <5>
DDR_B_DQS[0..7] <5>
DDR_B_MA[0..15] <5>
DDR_B_DQS#[0..7] <5>
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
DDR_B_MA6
DDR_B_MA2
DDR_B_MA0
DDR_CS0_DIMMB#
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA4
DDR_CKE1_DIMMB
DDR_B_MA15
DDR_CKE0_DIMMB
DDR_B_BS#2
DDR_B_MA5
DDR_B_MA8
DDR_B_MA9
DDR_B_MA12
DDR_B_MA10
DDR_B_BS#0
DDR_B_MA1
DDR_B_MA3
DDR_B_ODT1
DDR_CS1_DIMMB#
DDR_B_CAS#
DDR_B_WE#
DDR_B_RAS#
DDR_B_BS#1
DDR_B_ODT0
DDR_B_MA13
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
Cross between +1.8V and +0.9V power plan
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
+0.9V
RP8
RP8
18
27
36
45
RP9
RP9
18
27
36
45
RP10
RP10
18
27
36
45
RP11
RP11
18
27
36
45
RP12
RP12
18
27
36
45
RP13
RP13
18
27
36
45
RP14
RP14
18
27
36
45
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
12
C105 0.1U_0402_16V4Z
C105 0.1U_0402_16V4Z
1 2
C106 0.1U_0402_16V4Z
C106 0.1U_0402_16V4Z
12
C108 0.1U_0402_16V4Z
C108 0.1U_0402_16V4Z
1 2
C107 0.1U_0402_16V4Z
C107 0.1U_0402_16V4Z
12
C109 0.1U_0402_16V4Z
C109 0.1U_0402_16V4Z
1 2
C110 0.1U_0402_16V4Z
C110 0.1U_0402_16V4Z
12
C111 0.1U_0402_16V4Z
C111 0.1U_0402_16V4Z
1 2
C112 0.1U_0402_16V4Z
C112 0.1U_0402_16V4Z
12
C114 0.1U_0402_16V4Z
C114 0.1U_0402_16V4Z
1 2
C113 0.1U_0402_16V4Z
C113 0.1U_0402_16V4Z
12
C116 0.1U_0402_16V4Z
C116 0.1U_0402_16V4Z
1 2
C115 0.1U_0402_16V4Z
C115 0.1U_0402_16V4Z
12
C118 0.1U_0402_16V4Z
C118 0.1U_0402_16V4Z
1 2
C117 0.1U_0402_16V4Z
C117 0.1U_0402_16V4Z
SCHEMATIC MB A4112
SCHEMATIC MB A4112
SCHEMATIC MB A4112
401568
401568
401568
E
+1.8V
F
F
F
of
of
of
954Friday, February 13, 2009
954Friday, February 13, 2009
954Friday, February 13, 2009
A
SB_RX0P<26>
SB_RX0N<26>
SB_RX1P<26>
SB_RX1N<26>
SB_RX2P<26>
SB_RX2N<26>
SB_RX3P<26>
SB_RX3N<26>
PCIE_GTX_C_MRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_P15
PCIE_GTX_C_MRX_N15
U3B
U3B
D4
GFX_RX0P
C4
GFX_RX0N
A3
GFX_RX1P
B3
GFX_RX1N
C2
GFX_RX2P
C1
GFX_RX2N
E5
GFX_RX3P
F5
GFX_RX3N
G5
GFX_RX4P
G6
GFX_RX4N
H5
GFX_RX5P
H6
GFX_RX5N
J6
GFX_RX6P
J5
GFX_RX6N
J7
GFX_RX7P
J8
GFX_RX7N
L5
GFX_RX8P
L6
GFX_RX8N
M8
GFX_RX9P
L8
GFX_RX9N
P7
GFX_RX10P
M7
GFX_RX10N
P5
GFX_RX11P
M5
GFX_RX11N
R8
GFX_RX12P
P8
GFX_RX12N
R6
GFX_RX13P
R5
GFX_RX13N
P4
GFX_RX14P
P3
GFX_RX14N
T4
GFX_RX15P
T3
GFX_RX15N
AE3
GPP_RX0P
AD4
GPP_RX0N
AE2
GPP_RX1P
AD3
GPP_RX1N
AD1
GPP_RX2P
AD2
GPP_RX2N
V5
GPP_RX3P
W6
GPP_RX3N
U5
GPP_RX4P
U6
GPP_RX4N
U8
GPP_RX5P
U7
GPP_RX5N
AA8
SB_RX0P
Y8
SB_RX0N
AA7
SB_RX1P
Y7
SB_RX1N
AA5
SB_RX2P
AA6
SB_RX2N
W5
SB_RX3P
Y5
SB_RX3N
RS780M_FCBGA528
RS780M_FCBGA528
PART 2 OF 6
PART 2 OF 6
PCIE I/F GFX
PCIE I/F GFX
PCIE I/F GPP
PCIE I/F GPP
PCIE I/F SB
PCIE I/F SB
PCE_CALRP(PCE_BCALRP)
PCE_CALRN(PCE_BCALRN)
PCIE_GTX_C_MRX_P[0..15]<15>
PCIE_GTX_C_MRX_N[0..15]<15>
1 1
PCIE_PTX_C_IRX_P1<34>
PCIE_PTX_C_IRX_N1<34>
PCIE_PTX_C_IRX_P2<33>
PCIE_PTX_C_IRX_N2<33>
PCIE_PTX_C_IRX_P3<32>
2 2
PCIE_PTX_C_IRX_N3<32>
RS780M Display Port Support (muxed on GFX)
DP0
DP1
3 3
SA00001ZG00(A11) S IC 216-0674001-00/RS780M FCBGA528P 0FH
SA00001ZG20(A12) S IC 216-0674008-00 A12 RS780M FCBGA 0FH
GFX_TX0,TX1,TX2 and TX3
AUX0 and HPD0
GFX_TX4,TX5,TX6 and TX7
AUX1 and HPD1
SA00002DT10(A12) S IC 215-0674024 A12 RX781 FCBGA528P 0FH
B
GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N
GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_TX4P
GPP_TX4N
GPP_TX5P
GPP_TX5N
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
A5
PCIE_MTX_GRX_N0
B5
PCIE_MTX_GRX_P1
A4
B4
PCIE_MTX_GRX_P2
C3
PCIE_MTX_GRX_N2
B2
PCIE_MTX_GRX_P3
D1
D2
PCIE_MTX_GRX_P4
E2
PCIE_MTX_GRX_N4
E1
PCIE_MTX_GRX_P5
F4
F3
PCIE_MTX_GRX_P6
F1
F2
PCIE_MTX_GRX_P7
H4
H3
PCIE_MTX_GRX_P8
H1
H2
PCIE_MTX_GRX_P9
J2
PCIE_MTX_GRX_N9
J1
K4
PCIE_MTX_GRX_N10
K3
PCIE_MTX_GRX_P11
K1
PCIE_MTX_GRX_N11
K2
PCIE_MTX_GRX_P12
M4
PCIE_MTX_GRX_N12
M3
PCIE_MTX_GRX_P13
M1
M2
PCIE_MTX_GRX_P14
N2
PCIE_MTX_GRX_N14
N1
PCIE_MTX_GRX_P15
P1
P2
AC1
AC2
PCIE_ITX_PRX_P1
AB4
PCIE_ITX_PRX_N1
AB3
PCIE_ITX_PRX_P2
AA2
PCIE_ITX_PRX_N2
AA1
PCIE_ITX_PRX_P3
Y1
PCIE_ITX_PRX_N3
Y2
Y4
Y3
V1
V2
SB_TX0P_C
AD7
SB_TX0N_C
AE7
SB_TX1P_C
AE6
SB_TX1N_C
AD6
SB_TX2P_C
AB6
SB_TX2N_C
AC6
SB_TX3P_C
AD5
SB_TX3N_C
AE5
CALRP
AC8
CALRN
AB8
Place them close to NB within 1"
C121 0.1U_0402_16V7KC121 0.1U_0402_16V7K
C123 0.1U_0402_16V7KC123 0.1U_0402_16V7K
C125 0.1U_0402_16V7KC125 0.1U_0402_16V7K
C127 0.1U_0402_16V7KC127 0.1U_0402_16V7K
C129 0.1U_0402_16V7KC129 0.1U_0402_16V7K
C131 0.1U_0402_16V7KC131 0.1U_0402_16V7K
C133 0.1U_0402_16V7KC133 0.1U_0402_16V7K
C135 0.1U_0402_16V7KC135 0.1U_0402_16V7K
C137 0.1U_0402_16V7KC137 0.1U_0402_16V7K
C139 0.1U_0402_16V7KC139 0.1U_0402_16V7K
C141 0.1U_0402_16V7KC141 0.1U_0402_16V7K
C143 0.1U_0402_16V7KC143 0.1U_0402_16V7K
C145 0.1U_0402_16V7KC145 0.1U_0402_16V7K
C147 0.1U_0402_16V7KC147 0.1U_0402_16V7K
C149 0.1U_0402_16V7KC149 0.1U_0402_16V7K
C151 0.1U_0402_16V7KC151 0.1U_0402_16V7K
C162 0.1U_0402_16V7K C162 0.1U_0402_16V7K
C163 0.1U_0402_16V7K C163 0.1U_0402_16V7K
C164 0.1U_0402_16V7K C164 0.1U_0402_16V7K
C165 0.1U_0402_16V7K C165 0.1U_0402_16V7K
C166 0.1U_0402_16V7K C166 0.1U_0402_16V7K
C168 0.1U_0402_16V7K C168 0.1U_0402_16V7K
C169 0.1U_0402_16V7K C169 0.1U_0402_16V7K
C167 0.1U_0402_16V7K C167 0.1U_0402_16V7K
R55 1.27K_0402_1% R55 1.27K_0402_1%
1 2
R56 2K_0402_1% R56 2K_0402_1%
1 2
CALRP/N=W/S=5mil/10mil
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
C154 0.1U_0402_16V7K C154 0.1U_0402_16V7K
1 2
C155 0.1U_0402_16V7K C155 0.1U_0402_16V7K
1 2
C156 0.1U_0402_16V7K C156 0.1U_0402_16V7K
1 2
C157 0.1U_0402_16V7K C157 0.1U_0402_16V7K
1 2
C158 0.1U_0402_16V7K C158 0.1U_0402_16V7K
1 2
C159 0.1U_0402_16V7K C159 0.1U_0402_16V7K
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
C
C120 0.1U_0402_16V7KC120 0.1U_0402_16V7K
1 2
C122 0.1U_0402_16V7KC122 0.1U_0402_16V7K
1 2
C124 0.1U_0402_16V7KC124 0.1U_0402_16V7K
1 2
C126 0.1U_0402_16V7KC126 0.1U_0402_16V7K
1 2
C128 0.1U_0402_16V7KC128 0.1U_0402_16V7K
1 2
C130 0.1U_0402_16V7KC130 0.1U_0402_16V7K
1 2
C132 0.1U_0402_16V7KC132 0.1U_0402_16V7K
1 2
C134 0.1U_0402_16V7KC134 0.1U_0402_16V7K
1 2
C136 0.1U_0402_16V7KC136 0.1U_0402_16V7K
1 2
C138 0.1U_0402_16V7KC138 0.1U_0402_16V7K
1 2
C140 0.1U_0402_16V7KC140 0.1U_0402_16V7K
1 2
C142 0.1U_0402_16V7KC142 0.1U_0402_16V7K
1 2
C144 0.1U_0402_16V7KC144 0.1U_0402_16V7K
1 2
C146 0.1U_0402_16V7KC146 0.1U_0402_16V7K
1 2
C148 0.1U_0402_16V7KC148 0.1U_0402_16V7K
1 2
C150 0.1U_0402_16V7KC150 0.1U_0402_16V7K
1 2
PCIE_ITX_C_PRX_P1 <34>
PCIE_ITX_C_PRX_N1 <34>
PCIE_ITX_C_PRX_P2 <33>
PCIE_ITX_C_PRX_N2 <33>
PCIE_ITX_C_PRX_P3 <32>
PCIE_ITX_C_PRX_N3 <32>
SB_TX0P <26>
SB_TX0N <26>
SB_TX1P <26>
SB_TX1N <26>
SB_TX2P <26>
SB_TX2N <26>
SB_TX3P <26>
SB_TX3N <26>
+1.1VS
PCIE_MTX_C_GRX_P[0..15]
PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P0PCIE_MTX_GRX_P0
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1PCIE_MTX_GRX_N1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P3PCIE_MTX_GRX_N3
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5PCIE_MTX_GRX_N5
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P6PCIE_MTX_GRX_N6
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_P7PCIE_MTX_GRX_N7
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8PCIE_MTX_GRX_N8
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_P10PCIE_MTX_GRX_P10
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N13PCIE_MTX_GRX_N13
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N15PCIE_MTX_GRX_N15
D
PCIE_MTX_C_GRX_P[0..15] <15>
PCIE_MTX_C_GRX_N[0..15] <15>
Polarity inversion
Polarity inversion
Polarity inversion
E
New Card(delete)
CardReader
WLAN
LAN10/100
TV Tuner(delete)
H_CLKOP0<4>
H_CLKON0<4>
H_CLKOP1<4>
H_CLKON1<4>
H_CTLOP0<4>
H_CTLON0<4>
H_CTLON1<4>
Place them close to NB within 1" Place them close to NB within 1"
RXCALRP/N=W/S=5mil/10mil
H_CADOP[0..15]<4>
H_CADON[0..15]<4> H_CADIN[0..15] <4>
H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7
H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15
H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1
RXCALRP
R57301_0402_1% R57301_0402_1%
1 2
RXCALRN
H_CADON[0..15]
U3A
U3A
Y25
HT_RXCAD0P
Y24
HT_RXCAD0N
V22
HT_RXCAD1P
V23
HT_RXCAD1N
V25
HT_RXCAD2P
V24
HT_RXCAD2N
U24
HT_RXCAD3P
U25
HT_RXCAD3N
T25
HT_RXCAD4P
T24
HT_RXCAD4N
P22
HT_RXCAD5P
P23
HT_RXCAD5N
P25
HT_RXCAD6P
P24
HT_RXCAD6N
N24
HT_RXCAD7P
N25
HT_RXCAD7N
AC24
HT_RXCAD8P
AC25
HT_RXCAD8N
AB25
HT_RXCAD9P
AB24
HT_RXCAD9N
AA24
HT_RXCAD10P
AA25
HT_RXCAD10N
Y22
HT_RXCAD11P
Y23
HT_RXCAD11N
W21
HT_RXCAD12P
W20
HT_RXCAD12N
V21
HT_RXCAD13P
V20
HT_RXCAD13N
U20
HT_RXCAD14P
U21
HT_RXCAD14N
U19
HT_RXCAD15P
U18
HT_RXCAD15N
T22
HT_RXCLK0P
T23
HT_RXCLK0N
AB23
HT_RXCLK1P
AA22
HT_RXCLK1N
M22
HT_RXCTL0P
M23
HT_RXCTL0N
R21
HT_RXCTL1P
R20
HT_RXCTL1N
C23
HT_RXCALP
A24
HT_RXCALN
RS780M_FCBGA528
RS780M_FCBGA528
H_CADIP[0..15]H_CADOP[0..15]
H_CADIN[0..15]
PART 1 OF 6
PART 1 OF 6
HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N
HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N
HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N
HYPER TRANSPORT CPU I/F
HYPER TRANSPORT CPU I/F
HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N
HT_TXCALP
HT_TXCALN
H_CADIP[0..15] <4>
H_CADIP0
D24
H_CADIN0
D25
H_CADIP1
E24
H_CADIN1
E25
H_CADIP2
F24
H_CADIN2
F25
H_CADIP3
F23
H_CADIN3
F22
H_CADIP4
H23
H_CADIN4
H22
H_CADIP5
J25
H_CADIN5
J24
H_CADIP6
K24
H_CADIN6
K25
H_CADIP7
K23
H_CADIN7
K22
H_CADIP8
F21
H_CADIN8
G21
H_CADIP9
G20
H_CADIN9
H21
H_CADIP10
J20
H_CADIN10
J21
H_CADIP11
J18
H_CADIN11
K17
H_CADIP12
L19
H_CADIN12
J19
H_CADIP13
M19
H_CADIN13
L18
H_CADIP14
M21
H_CADIN14
P21
H_CADIP15
P18
H_CADIN15
M18
H24
H25
L21
L20
H_CTLIP0
M24
H_CTLIN0
M25
H_CTLIP1
P19
H_CTLIN1
R18
TXCALRP
B24
TXCALRN
B25
TXCALRP/N=W/S=5mil/10mil
H_CLKIP0 <4>
H_CLKIN0 <4>
H_CLKIP1 <4>
H_CLKIN1 <4>
H_CTLIP0 <4>
H_CTLIN0 <4>
H_CTLIP1 <4>H_CTLOP1<4>
H_CTLIN1 <4>
R58 301_0402_1%R58 301_0402_1%
1 2
4 4
A
B
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2007/10/11 200810/11
2007/10/11 200810/11
2007/10/11 200810/11
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC MB A4112
SCHEMATIC MB A4112
SCHEMATIC MB A4112
401568
401568
401568
10 54Friday, February 13, 2009
10 54Friday, February 13, 2009
10 54Friday, February 13, 2009
E
of
of
of
F
F
F
A
+3VS
B
C
D
E
LDT_STOP#<6,26>
1 1
R1170 0_0402_5%
R1170 0_0402_5%
CPU_LDT_REQ#<6,26>
2 2
3 3
R1171 0_0402_5%
R1171 0_0402_5%
+1.8VS
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
R87
@R87
@
4.7K_0402_5%
4.7K_0402_5%
12
1 2
+3VS
@R84
@
NB_ALLOW_LDTSTOP
12
1 2
+1.8VS
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
L11
L11
1 2
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
+1.1VS
NB_LDTSTOP#
R84
4.7K_0402_5%
4.7K_0402_5%
L10
L10
1 2
C180
C180
C179
C179
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
1
2
1
2
Install when SB700 A12 use
1 2
R71
R71
150_0402_1%
150_0402_1%
1 2
R72
R72
150_0402_1%
150_0402_1%
NB_PWRGD<27>
PLT_RST#<14,15,26,32,33,34,39,40>
+1.8VS
NB_OSC_14.318M<22>
CLK_SBLINK_BCLK<22>
CLK_SBLINK_BCLK#<22>
+VDDA18HTPLL
+VDDA18PCIEPLL
1 2
R371 300_0402_5%R371 300_0402_5%
CLK_NBHT<22>
CLK_NBHT#<22>
NBGFX_CLK<22>
NBGFX_CLK#<22>
+VDDA18HTPLL=W/S=20/10mil
+VDDA18PCIEPLL=W/S=20/10mil
R66 0_0402_5% R66 0_0402_5%
+3VS
1 2
AUX_CAL<14>
NB_RESET#
NB_PWRGD
NB_LDTSTOP#
NB_ALLOW_LDTSTOP
12
R88 10K_0402_5%
R88 10K_0402_5%
Strap pin
U3C
U3C
F12
AVDD1(NC)
E12
AVDD2(NC)
F14
AVDDDI(NC)
G15
AVSSDI(NC)
H15
AVDDQ(NC)
H14
AVSSQ(NC)
E17
C_Pr(DFT_GPIO5)
F17
Y(DFT_GPIO2)
F15
COMP_Pb(DFT_GPIO4)
G18
RED(DFT_GPIO0)
G17
REDb(NC)
E18
GREEN(DFT_GPIO1)
F18
GREENb(NC)
E19
BLUE(DFT_GPIO3)
F19
BLUEb(NC)
A11
DAC_HSYNC(PWM_GPIO4)
B11
DAC_VSYNC(PWM_GPIO6)
F8
DAC_SCL(PCE_RCALRN)
E8
DAC_SDA(PCE_TCALRN)
G14
DAC_RSET(PWM_GPIO1)
A12
PLLVDD(NC)
D14
PLLVDD18(NC)
B12
PLLVSS(NC)
H17
VDDA18HTPLL
D7
VDDA18PCIEPLL1
E7
VDDA18PCIEPLL2
D8
SYSRESETb
A10
POWERGOOD
C10
LDTSTOPb
C12
ALLOW_LDTSTOP
C25
HT_REFCLKP
C24
HT_REFCLKN
E11
REFCLK_P/OSCIN(OSCIN)
F11
REFCLK_N(PWM_GPIO3)
T2
GFX_REFCLKP
T1
GFX_REFCLKN
U1
GPP_REFCLKP
U2
GPP_REFCLKN
V4
GPPSB_REFCLKP(SB_REFCLKP)
V3
GPPSB_REFCLKN(SB_REFCLKN)
B9
I2C_CLK
A9
I2C_DATA
B8
DDC_DATA0/AUX0N(NC)
A8
DDC_CLK0/AUX0P(NC)
B7
DDC_CLK1/AUX1P(NC)
A7
DDC_DATA1/AUX1N(NC)
B10
STRP_DATA
G11
RSVD
C8
AUX_CAL(NC)
RS780M_FCBGA528
RS780M_FCBGA528
PART 3 OF 6
PART 3 OF 6
TXOUT_U1P(PCIE_RESET_GPIO3)
TXOUT_U1N(PCIE_RESET_GPIO2)
TXOUT_U3P(PCIE_RESET_GPIO5)
CRT/TVOUT
CRT/TVOUT
TXCLK_UP(PCIE_RESET_GPIO4)
TXCLK_UN(PCIE_RESET_GPIO1)
LVTM
LVTM
PM
PM
LVDS_DIGON(PCE_TCALRP)
LVDS_BLON(PCE_RCALRP)
LVDS_ENA_BL(PWM_GPIO2)
CLOCKs PLL PWR
CLOCKs PLL PWR
MIS.
MIS.
SUS_STAT#(PWM_GPIO5)
TXOUT_L0P(NC)
TXOUT_L0N(NC)
TXOUT_L1P(NC)
TXOUT_L1N(NC)
TXOUT_L2P(NC)
TXOUT_L2N(DBG_GPIO0)
TXOUT_L3P(NC)
TXOUT_L3N(DBG_GPIO2)
TXOUT_U0P(NC)
TXOUT_U0N(NC)
TXOUT_U2P(NC)
TXOUT_U2N(NC)
TXOUT_U3N(NC)
TXCLK_LP(DBG_GPIO1)
TXCLK_LN(DBG_GPIO3)
VDDLTP18(NC)
VSSLTP18(NC)
VDDLT18_1(NC)
VDDLT18_2(NC)
VDDLT33_1(NC)
VDDLT33_2(NC)
VSSLT1(VSS)
VSSLT2(VSS)
VSSLT3(VSS)
VSSLT4(VSS)
VSSLT5(VSS)
VSSLT6(VSS)
VSSLT7(VSS)
TMDS_HPD(NC)
HPD(NC)
THERMALDIODE_P
THERMALDIODE_N
TESTMODE
A22
B22
A21
B21
B20
A20
A19
B19
B18
A18
A17
B17
D20
D21
D18
D19
B16
A16
D16
D17
A13
B13
A15
B15
A14
B14
C14
D15
C16
C18
C20
E20
C22
E9
F7
G12
flash issue check IALAA
D9
D10
D12
AE8
AD8
D13
1 2
R77 0_0402_5%
R77 0_0402_5%
1 2
R80
R80
1.8K_0402_5%
1.8K_0402_5%
SUS_STAT# <27>
SUS_STAT_R# <14>
Strap pin
NB temp to SB
4 4
A
B
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2007/10/11 200810/11
2007/10/11 200810/11
2007/10/11 200810/11
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC MB A4112
SCHEMATIC MB A4112
SCHEMATIC MB A4112
401568
401568
401568
11 54Friday, February 13, 2009
11 54Friday, February 13, 2009
11 54Friday, February 13, 2009
E
of
of
of
F
F
F
A
1 1
2 2
B
C
AB12
MEM_A0(NC)
AE16
MEM_A1(NC)
V11
MEM_A2(NC)
AE15
MEM_A3(NC)
AA12
MEM_A4(NC)
AB16
MEM_A5(NC)
AB14
MEM_A6(NC)
AD14
MEM_A7(NC)
AD13
MEM_A8(NC)
AD15
MEM_A9(NC)
AC16
MEM_A10(NC)
AE13
MEM_A11(NC)
AC14
MEM_A12(NC)
Y14
MEM_A13(NC)
AD16
MEM_BA0(NC)
AE17
MEM_BA1(NC)
AD17
MEM_BA2(NC)
W12
MEM_RASb(NC)
Y12
MEM_CASb(NC)
AD18
MEM_WEb(NC)
AB13
MEM_CSb(NC)
AB18
MEM_CKE(NC)
V14
MEM_ODT(NC)
V15
MEM_CKP(NC)
W14
MEM_CKN(NC)
AE12
MEM_COMPP(NC)
AD12
MEM_COMPN(NC)
RS780M_FCBGA528
RS780M_FCBGA528
U3D
U3D
PAR 4 OF 6
PAR 4 OF 6
MEM_DQ0/DVO_VSYNC(NC)
MEM_DQ1/DVO_HSYNC(NC)
MEM_DQ2/DVO_DE(NC)
MEM_DQ3/DVO_D0(NC)
MEM_DQ4(NC)
MEM_DQ5/DVO_D1(NC)
MEM_DQ6/DVO_D2(NC)
MEM_DQ7/DVO_D4(NC)
MEM_DQ8/DVO_D3(NC)
MEM_DQ9/DVO_D5(NC)
MEM_DQ10/DVO_D6(NC)
MEM_DQ11/DVO_D7(NC)
MEM_DQ12(NC)
MEM_DQ13/DVO_D9(NC)
MEM_DQ14/DVO_D10(NC)
MEM_DQ15/DVO_D11(NC)
MEM_DQS0P/DVO_IDCKP(NC)
MEM_DQS0N/DVO_IDCKN(NC)
MEM_DQS1P(NC)
MEM_DQS1N(NC)
MEM_DM0(NC)
MEM_DM1/DVO_D8(NC)
SBD_MEM/DVO_I/F
SBD_MEM/DVO_I/F
IOPLLVDD18(NC)
IOPLLVDD(NC)
IOPLLVSS(NC)
MEM_VREF(NC)
AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21
Y17
W18
AD20
AE21
W17
AE19
AE23
AE24
AD23
AE18
D
+1.8VS=W/S=20/10mil For Memory PLL power
+1.8VS
+1.1VS=W/S=20/10mil For Memory PLL power
+1.1VS
E
3 3
4 4
A
B
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2007/10/11 200810/11
2007/10/11 200810/11
2007/10/11 200810/11
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC MB A4112
SCHEMATIC MB A4112
SCHEMATIC MB A4112
401568
401568
401568
E
of
of
of
12 54Friday, February 13, 2009
12 54Friday, February 13, 2009
12 54Friday, February 13, 2009
F
F
F
A
B
C
D
E
U3F
1 1
+VDDHT >120mil
(power plan)
C208
C208
1
1
2
2
+VDDHTRX >70mil
(power plan)
+VDDHTRX
1
1
C218
C218
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
+VDDHTTX >45mil
(power plan)
1
C228
C228
C238
C238
1
C229
C229
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+VDDA18PCIE >20mil
(power plan)
1
1
C239
C239
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.8VS >20mil
+1.8VS
1
C251
C251
2
+VDDHT
C210
C210
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+VDDHTTX
+VDDA18PCIE
J17
VDDHT_1
K16
VDDHT_2
L16
VDDHT_3
M16
VDDHT_4
P16
VDDHT_5
R16
VDDHT_6
T16
VDDHT_7
H18
VDDHTRX_1
G19
VDDHTRX_2
F20
VDDHTRX_3
E21
VDDHTRX_4
D22
VDDHTRX_5
B23
VDDHTRX_6
A23
VDDHTRX_7
AE25
VDDHTTX_1
AD24
VDDHTTX_2
AC23
VDDHTTX_3
AB22
VDDHTTX_4
AA21
VDDHTTX_5
Y20
VDDHTTX_6
W19
VDDHTTX_7
V18
VDDHTTX_8
U17
VDDHTTX_9
T17
VDDHTTX_10
R17
VDDHTTX_11
P17
VDDHTTX_12
M17
VDDHTTX_13
J10
VDDA18PCIE_1
P10
VDDA18PCIE_2
K10
VDDA18PCIE_3
M10
VDDA18PCIE_4
L10
VDDA18PCIE_5
W9
VDDA18PCIE_6
H9
VDDA18PCIE_7
T10
VDDA18PCIE_8
R10
VDDA18PCIE_9
Y9
VDDA18PCIE_10
AA9
VDDA18PCIE_11
AB9
VDDA18PCIE_12
AD9
VDDA18PCIE_13
AE9
VDDA18PCIE_14
U10
VDDA18PCIE_15
F9
VDD18_1
G9
VDD18_2
AE11
VDD18_MEM1(NC)
AD11
VDD18_MEM2(NC)
RS780M_FCBGA528
RS780M_FCBGA528
+VDDA11PCIE >300mil
(power plan)
0.7A/4vias
U3E
U3E
PART 5/6
PART 5/6
VDDPCIE_1
VDDPCIE_2
VDDPCIE_3
VDDPCIE_4
VDDPCIE_5
VDDPCIE_6
VDDPCIE_7
VDDPCIE_8
VDDPCIE_9
VDDPCIE_10
VDDPCIE_11
VDDPCIE_12
VDDPCIE_13
VDDPCIE_14
VDDPCIE_15
VDDPCIE_16
VDDPCIE_17
VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
POWER
POWER
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
VDD_MEM1(NC)
VDD_MEM2(NC)
VDD_MEM3(NC)
VDD_MEM4(NC)
VDD_MEM5(NC)
VDD_MEM6(NC)
VDD33_1(NC)
VDD33_2(NC)
VDDA_12=2.5A
A6
B6
C6
D6
E6
F6
G7
H8
J9
K9
M9
L9
P9
R9
T9
V9
U9
K12
J14
U16
J11
K15
M12
L14
L11
M13
M15
N12
N14
P11
P13
P14
R12
R15
T11
T15
U12
T14
J16
AE10
AA11
Y11
AD10
AB10
AC10
H11
H12
+VDDA11PCIE
+1.1VS +NB_VDDC
7A/16vias
1
1
1
C2470.1U_0402_16V4Z C2470.1U_0402_16V4Z
C2400.1U_0402_16V4Z C2400.1U_0402_16V4Z
C2410.1U_0402_16V4Z C2410.1U_0402_16V4Z
2
2
2
0.15A/2vias
+3VS
+3VS >20mil
L17
L17
1 2
FBMA-L11-201209-221LMA30T_0805
FBMA-L11-201209-221LMA30T_0805
C211
C211
C212
C212
C220 1U_0402_6.3V4Z
C220 1U_0402_6.3V4Z
C219 1U_0402_6.3V4Z
C219 1U_0402_6.3V4Z
C222 1U_0402_6.3V4Z
C222 1U_0402_6.3V4Z
C221 1U_0402_6.3V4Z
C221 1U_0402_6.3V4Z
C224 0.1U_0402_16V4Z C224 0.1U_0402_16V4Z
C223 0.1U_0402_16V4Z C223 0.1U_0402_16V4Z
1
1
C2420.1U_0402_16V4Z C2420.1U_0402_16V4Z
C2430.1U_0402_16V4Z C2430.1U_0402_16V4Z
2
2
1 2
1 2
1 2
1 2
PJP604
PJP604
1 2
PAD-OPEN 4x4m
PAD-OPEN 4x4m
VDD_CORE=5A
1
1
C2300.1U_0402_16V4Z C2300.1U_0402_16V4Z
C2310.1U_0402_16V4Z C2310.1U_0402_16V4Z
2
2
1 2
1 2
10U_0805_10V4Z
10U_0805_10V4Z
10U_0805_10V4Z
10U_0805_10V4Z
12
12
1
1
C2320.1U_0402_16V4Z C2320.1U_0402_16V4Z
C2440.1U_0402_16V4Z C2440.1U_0402_16V4Z
2
2
C2500.1U_0402_16V4Z @C2500.1U_0402_16V4Z @
C2530.1U_0402_16V4Z @C2530.1U_0402_16V4Z @
+1.1VS
+NB_VDDC >300mil
(power plan)
330U_D2E_2.5VM_R15
330U_D2E_2.5VM_R15
1
C234
C234
1
1
C24510U_0805_10V4Z C24510U_0805_10V4Z
C23310U_0805_10V4Z C23310U_0805_10V4Z
+
+
2
2
2
C209
C209
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C214
C214
2
C225
C225
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C246
C246
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.6A/4vias
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C206
C206
1
1
C207
C207
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.45A/3vias
1
C216
C216
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.5A/4vias
1
1
C227
C227
C226
C226
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.25A/2vias
1
1
C237
C237
C236
C236
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C217
C217
1
2
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
+1.1VS
2 2
+1.2V_HT
L19
L19
0_0805_5%
0_0805_5%
L16
L16
0_0805_5%
0_0805_5%
4.7U_0805_10V4Z
4.7U_0805_10V4Z
L18
L18
12
0_0805_5%
0_0805_5%
4.7U_0805_10V4Z
4.7U_0805_10V4Z
12
12
C215
C215
+1.35VS for A11
4.7U_0805_10V4Z
4.7U_0805_10V4Z
L22
L22
+1.8VS
3 3
12
0_0805_5%
0_0805_5%
4.7U_0805_10V4Z
4.7U_0805_10V4Z
C235
C235
4.7U_0805_10V4Z
4.7U_0805_10V4Z
U3F
A25
VSSAHT1
D23
VSSAHT2
E22
VSSAHT3
G22
VSSAHT4
G24
VSSAHT5
G25
VSSAHT6
H19
VSSAHT7
J22
VSSAHT8
L17
VSSAHT9
L22
VSSAHT10
L24
VSSAHT11
L25
VSSAHT12
M20
VSSAHT13
N22
VSSAHT14
P20
VSSAHT15
R19
VSSAHT16
R22
VSSAHT17
R24
VSSAHT18
R25
VSSAHT19
H20
VSSAHT20
U22
VSSAHT21
V19
VSSAHT22
W22
VSSAHT23
W24
VSSAHT24
W25
VSSAHT25
Y21
VSSAHT26
AD25
VSSAHT27
L12
VSS11
M14
VSS12
N13
VSS13
P12
VSS14
P15
VSS15
R11
VSS16
R14
VSS17
T12
VSS18
U14
VSS19
U11
VSS20
U15
VSS21
V12
VSS22
W11
VSS23
W15
VSS24
AC12
VSS25
AA14
VSS26
Y18
VSS27
AB11
VSS28
AB15
VSS29
AB17
VSS30
AB19
VSS31
AE20
VSS32
AB21
VSS33
K11
VSS34
RS780M_FCBGA528
RS780M_FCBGA528
PART 6/6
PART 6/6
VSSAPCIE1
VSSAPCIE2
VSSAPCIE3
VSSAPCIE4
VSSAPCIE5
VSSAPCIE6
VSSAPCIE7
VSSAPCIE8
VSSAPCIE9
VSSAPCIE10
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30
GROUND
GROUND
VSSAPCIE31
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
A2
B1
D3
D5
E4
G1
G2
G4
H7
J4
R7
L1
L2
L4
L7
M6
N4
P6
R1
R2
R4
V7
U4
V8
V6
W1
W2
W4
W7
W8
Y6
AA4
AB5
AB1
AB7
AC3
AC4
AE1
AE4
AB2
AE14
D11
G8
E14
E15
J15
J12
K14
M11
L15
+1.8VS
1
C1064
@C1064
@
2
10U_0805_10V4Z
10U_0805_10V4Z
4 4
@
@
2N7002_SOT23-3
2N7002_SOT23-3
VLDT_EN#<43>
1 2
R1017 0_0402_5%@ R1017 0_0402_5%@
2
@C1068
@
1
A
Just for RS780M A11 version boot issue
12
R1015
@R1015
@
1K_0402_1%
1K_0402_1%
+VREF1.35V
12
R1016
@R1016
Q163
Q163
2
G
G
C1068
0.1U_0402_16V7K
0.1U_0402_16V7K
@
13
D
D
3K_0402_5%
3K_0402_5%
S
S
0.1U_0402_16V7K
0.1U_0402_16V7K
2
C1066
@C1066
@
1
U64
@U64
@
VIN1VCNTL
2
GND
3
VREF
4
VOUT
G2992F1U_SO8
G2992F1U_SO8
1
C1067
@C1067
@
10U_0805_10V4Z
10U_0805_10V4Z
2
B
+1.35VS
6
5
NC
7
NC
8
NC
9
TP
+3VS
1
C1065
@C1065
@
1U_0603_10V6K
1U_0603_10V6K
2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2007/10/11 200810/11
2007/10/11 200810/11
2007/10/11 200810/11
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC MB A4112
SCHEMATIC MB A4112
SCHEMATIC MB A4112
401568
401568
401568
13 54Friday, February 13, 2009
13 54Friday, February 13, 2009
13 54Friday, February 13, 2009
E
of
of
of
F
F
F
A
B
C
D
E
1 1
2 2
RS780 DFT_GPIO5 mux at CRT_VSYNC pull low to 1K
CRT_VSYNC<16,23>
12
R101 1K_0402_5%R101 1K_0402_5%
12
R102 1K_0402_5%@R102 1K_0402_5%@
+3VS
DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb
Enables the Test Debug Bus using GPIO.
1 : Disable (RS740) Enable (RX780, RS780)
0 : Enable (Rs740) Disable (RX780, RS780)
PIN: RS740-->RS780_AUX_CAL; RX780-->NB_TV_C; RS780--> VSYNC#
DFT_GPIO1: LOAD_EEPROM_STRAPS
1 2
R104 150_0402_1%@R104 150_0402_1%@
D4 CH751H-40PT_SOD323-2@D4 CH751H-40PT_SOD323-2@
2 1
Selects Loading of STRAPS from EPROM
1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 : I2C Master can load strap values from EEPROM if connected, or use
default values if not connected
RS740/RX780: DFT_GPIO1 RS780:SUS_STAT
RS780 DFT_GPIO1
AUX_CAL<11>
SUS_STAT_R#<11> PLT_RST# <11,15,26,32,33,34,39,40>
RX780 DFT_GPIO1 mux at GREEN(Ball E18) and change pull low form 150 to 3K.
3 3
DFT_GPIO0: STRAP_DEBUG_BUS_PCIE_ENABLEb
RX780: Enables the Test Debug Bus using PCIE bus
1 : Disable ( Can still be enabled using nbcfg register access )
RS780 use HSYNC to enable SIDE PORT (internal pull high)
CRT_HSYNC<16,21,23>
4 4
A
B
R107 3K_0402_5%@R107 3K_0402_5%@
12
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
0 : Enable
RS740/RS780: Enables Side port memory ( RS780 use HSYNC#)
1. Disable (RS740/RS780)
0 : Enable (RS740/RS780)
Compal Secret Data
Compal Secret Data
2007/10/11 200810/11
2007/10/11 200810/11
2007/10/11 200810/11
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC MB A4112
SCHEMATIC MB A4112
SCHEMATIC MB A4112
401568
401568
401568
14 54Friday, February 13, 2009
14 54Friday, February 13, 2009
14 54Friday, February 13, 2009
E
of
of
of
F
F
F
5
4
3
2
1
PCIE_GTX_C_MRX_P[0..15]<10>
PCIE_GTX_C_MRX_N[0..15]<10>
D D
C C
B B
CLK_PCIE_VGA<22>
CLK_PCIE_VGA#<22>
PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N15
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N0 PEG_M_RXN0
PLT_RST#<11,14,26,32,33,34,39,40>
PCIE_MTX_C_GRX_P[0..15]<10>
PCIE_MTX_C_GRX_N[0..15]<10>
U5A
U5A
AC30
PCIE_RX0P
AC31
PCIE_RX0N
AC29
PCIE_RX1P
AB29
PCIE_RX1N
AB31
PCIE_RX2P
AB30
PCIE_RX2N
AA31
PCIE_RX3P
AA30
PCIE_RX3N
W30
PCIE_RX4P
W31
PCIE_RX4N
W29
PCIE_RX5P
V29
PCIE_RX5N
V31
PCIE_RX6P
V30
PCIE_RX6N
U31
PCIE_RX7P
U30
PCIE_RX7N
P30
PCIE_RX8P
P31
PCIE_RX8N
P29
PCIE_RX9P
N29
PCIE_RX9N
N31
PCIE_RX10P
N30
PCIE_RX10N
M31
PCIE_RX11P
M30
PCIE_RX11N
K30
PCIE_RX12P
K31
PCIE_RX12N
K29
PCIE_RX13P
J29
PCIE_RX13N
J31
PCIE_RX14P
J30
PCIE_RX14N
H31
PCIE_RX15P
H30
PCIE_RX15N
Clock
Clock
AD29
PCIE_REFCLKP
AD30
PCIE_REFCLKN
SM BUS
SM BUS
AC28
NC_SMBCLK
AC27
NC_SMBDATA
AG25
PERSTB
216-0707001-00/M82-S_BGA632
216-0707001-00/M82-S_BGA632
PCIE_GTX_C_MRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
PCIE_MTX_C_GRX_N[0..15]
PART 1 OF 6
PART 1 OF 6
P
P
C
C
I
I
-
ÂE
E
X
X
P
P
R
R
E
E
S
S
S
S
I
I
N
N
T
T
E
E
R
R
F
F
A
A
C
C
E
E
PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P
PCIE_TX3N
PCIE_TX4P
PCIE_TX4N
PCIE_TX5P
PCIE_TX5N
PCIE_TX6P
PCIE_TX6N
PCIE_TX7P
PCIE_TX7N
PCIE_TX8P
PCIE_TX8N
PCIE_TX9P
PCIE_TX9N
PCIE_TX10P
PCIE_TX10N
PCIE_TX11P
PCIE_TX11N
PCIE_TX12P
PCIE_TX12N
PCIE_TX13P
PCIE_TX13N
PCIE_TX14P
PCIE_TX14N
PCIE_TX15P
PCIE_TX15N
Calibration
Calibration
PCIE_CALRN
PCIE_CALRP
PEG_M_RXP15
AA28
PEG_M_RXN15
AA27
PEG_M_RXP14
AA25
PEG_M_RXN14
AA24
PEG_M_RXP13
Y28
PEG_M_RXN13
Y27
PEG_M_RXP12
Y25
PEG_M_RXN12
Y24
PEG_M_RXP11
V28
PEG_M_RXN11
V27
PEG_M_RXP10
V25
PEG_M_RXN10
V24
PEG_M_RXP9
T28
PEG_M_RXN9 PCIE_GTX_C_MRX_N9
T27
PEG_M_RXP8
T25
PEG_M_RXN8 PCIE_GTX_C_MRX_N8
T24
PEG_M_RXP7
P28
PEG_M_RXN7
P27
PEG_M_RXP6
P25
PEG_M_RXN6
P24
PEG_M_RXP5
M28
PEG_M_RXN5
M27
PEG_M_RXP4 PCIE_GTX_C_MRX_P4
M25
PEG_M_RXN4
M24
PEG_M_RXP3
L28
PEG_M_RXN3
L27
PEG_M_RXP2 PCIE_GTX_C_MRX_P2
L25
PEG_M_RXN2
L24
PEG_M_RXP1 PCIE_GTX_C_MRX_P1
J28
PEG_M_RXN1
J27
PEG_M_RXP0
G28
G27
PCIE_CALRN
AF25
PCIE_CALRP
AE25
AE23
NC
AH30
NC
C1077 0.1U_0402_16V7KC1077 0.1U_0402_16V7K
1 2
C1078 0.1U_0402_16V7KC1078 0.1U_0402_16V7K
1 2
C1079 0.1U_0402_16V7KC1079 0.1U_0402_16V7K
1 2
C1080 0.1U_0402_16V7KC1080 0.1U_0402_16V7K
1 2
C1081 0.1U_0402_16V7KC1081 0.1U_0402_16V7K
1 2
C1082 0.1U_0402_16V7KC1082 0.1U_0402_16V7K
1 2
C1083 0.1U_0402_16V7KC1083 0.1U_0402_16V7K
1 2
C1084 0.1U_0402_16V7KC1084 0.1U_0402_16V7K
1 2
C1085 0.1U_0402_16V7KC1085 0.1U_0402_16V7K
1 2
C1086 0.1U_0402_16V7KC1086 0.1U_0402_16V7K
1 2
C1087 0.1U_0402_16V7KC1087 0.1U_0402_16V7K
1 2
C1088 0.1U_0402_16V7KC1088 0.1U_0402_16V7K
1 2
C1089 0.1U_0402_16V7KC1089 0.1U_0402_16V7K
1 2
C1090 0.1U_0402_16V7KC1090 0.1U_0402_16V7K
1 2
C1091 0.1U_0402_16V7KC1091 0.1U_0402_16V7K
1 2
C1092 0.1U_0402_16V7KC1092 0.1U_0402_16V7K
1 2
C1093 0.1U_0402_16V7KC1093 0.1U_0402_16V7K
1 2
C1094 0.1U_0402_16V7KC1094 0.1U_0402_16V7K
1 2
C1095 0.1U_0402_16V7KC1095 0.1U_0402_16V7K
1 2
C1096 0.1U_0402_16V7KC1096 0.1U_0402_16V7K
1 2
C1097 0.1U_0402_16V7KC1097 0.1U_0402_16V7K
1 2
C1098 0.1U_0402_16V7KC1098 0.1U_0402_16V7K
1 2
C1099 0.1U_0402_16V7KC1099 0.1U_0402_16V7K
1 2
C1100 0.1U_0402_16V7KC1100 0.1U_0402_16V7K
1 2
C1101 0.1U_0402_16V7KC1101 0.1U_0402_16V7K
1 2
C1102 0.1U_0402_16V7KC1102 0.1U_0402_16V7K
1 2
C1103 0.1U_0402_16V7KC1103 0.1U_0402_16V7K
1 2
C1104 0.1U_0402_16V7KC1104 0.1U_0402_16V7K
1 2
C1105 0.1U_0402_16V7KC1105 0.1U_0402_16V7K
1 2
C1106 0.1U_0402_16V7KC1106 0.1U_0402_16V7K
1 2
C1107 0.1U_0402_16V7KC1107 0.1U_0402_16V7K
1 2
C1108 0.1U_0402_16V7KC1108 0.1U_0402_16V7K
1 2
R1057 2K_0402_1%R1057 2K_0402_1%
1 2
R1058
R1058
1 2
1.27K_0402_1%
1.27K_0402_1%
PCIE_CALRN/P==W/S=5mil/10mil
+1.1VS
PCIE_GTX_C_MRX_P15
PCIE_GTX_C_MRX_N15
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_N0
PCIE LANE REVERSALPCIE LANE REVERSAL
A A
5
4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2007/10/11 200810/11
2007/10/11 200810/11
2007/10/11 200810/11
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC MB A4112
SCHEMATIC MB A4112
SCHEMATIC MB A4112
401568
401568
401568
15 54Friday, February 13, 2009
15 54Friday, February 13, 2009
15 54Friday, February 13, 2009
1
of
of
of
F
F
F
5
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
+VGA_CORE
D D
+1.8VS
C C
+1.1VS
+1.8VS
12
R1071
R1071
499_0402_1%
499_0402_1%
12
R1072
R1072
249_0402_1%
249_0402_1%
B B
L97
L97
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
L100
L100
10U_0603_6.3V6M
10U_0603_6.3V6M
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
+1.8VS
10U_0603_6.3V6M
10U_0603_6.3V6M
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
R1063
R1063
10U_0603_6.3V6M
10U_0603_6.3V6M
+VGA_VREF
1
C1151
C1151
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
+3.3V_DELAY
R1059
R1059
SI: Per EMI request add SSC chip
Spread spectrum
27M_OUT
R1164
R1164
0_0402_5%
0_0402_5%
1 2
27M_CLK<22>
A A
27MCLK
@ Y8
@
4
GND
1
IN
1
27MHz_16PF_6P27000126
27MHz_16PF_6P27000126
CV2
@ CV2
@
2
22P_0402_50V8J
22P_0402_50V8J
OUT
GND
Y8
12
C1112
C1112
10U_0603_4V6M
10U_0603_4V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
12
1
C1124
C1124
2
12
1
C1133
C1133
2
12
1
C1136
C1136
2
ENBKL<40>
+3.3V_DELAY
VGA_PWRSEL<51>
27M_SSC<22>
U4
@U4
@
1
REFOUT
2
XOUT
XIN3VDD
ASM3P2872A
ASM3P2872A
3
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
1
C1113
C1113
2
2
1
C1125
C1125
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C1134
C1134
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C1137
C1137
2
VSS
MODOUT
@C1273
@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
27M_OUT
XTALOUT
1
CV1
@ CV1
@
22P_0402_50V8J
22P_0402_50V8J
2
5
+MPVDD
1
C1114
C1114
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+DPLL_PVDD
1
C1126
C1126
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
+PCIE_PVDD
1
C1135
C1135
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
+DPLL_VDDC
1
C1138
C1138
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
R1066
R1066
12
10K_0402_5%
10K_0402_5%
R1067
@R1067
@
12
10K_0402_5%
10K_0402_5%
1 2
R11620_0402_5%R11620_0402_5%
SCS#_GPIO22<21>
12
R106910K_0402_5% R106910K_0402_5%
6
5
R1163 33_0402_5%@R1163 33_0402_5%@
4
C1273
VGA input level is 1.8V
1 2
1
1
@C1274
@
2
2
R1074
27M_SSC_R
C1274
1U_0402_6.3V4Z
1U_0402_6.3V4Z
75_0402_1%
75_0402_1%
1 2
R1074
THM_ALERT#<21>
12
R106810K_0402_5%@ R106810K_0402_5%@
R1070 1K_0402_5%R1070 1K_0402_5%
+3VS
1 2
PSYNC<21>
VRAM_ID0<21>
VRAM_ID1<21>
VRAM_ID2<21>
VRAM_ID3<21>
GPIO0<21>
GPIO1<21>
GPIO4<21>
GPIO5<21>
GPIO6<21>
SOUT_GPIO8<21>
SIN_GPIO9<21>
SCLK<21>
GPIO11<21>
GPIO12<21>
GPIO13<21>
12
52mA
68mA
230mA
80mA
27MCLK
R1075
R1075
100_0402_5%
100_0402_5%
27M_SSC_R
VGA_CTF
VGA_CLKREQ#
T47 PADT47 PAD
T48 PADT48 PAD
T49 PADT49 PAD
T50 PADT50 PAD
T51 PADT51 PAD
T52 PADT52 PAD
+DPLL_PVDD
+PCIE_PVDD
+MPVDD
+DPLL_VDDC
R1076
1K_0402_5%
1K_0402_5%
+VGA_VREF
XTALOUT
12
R1076
4
U5B
U5B
AJ4
TXCM_DPA0P
AJ5
TXCP_DPA0N
AL5
TX0M_DPA1P
AK5
TX0P_DPA1N
AL6
TX1M_DPA2P
AK6
TX1P_DPA2N
AK8
TX2M_DPA3P
AL8
TX2P_DPA3N
AD9
DVALID
AE7
PSYNC_NEW
AK4
DVPCNTL_MVP_0
AL3
DVPCNTL_MVP_1
V2
DVPCNTL_0
V1
DVPCNTL_1
W3
DVPCNTL_2
W1
DVPCLK
Y1
DVPDATA_0
Y2
DVPDATA_1
Y3
DVPDATA_2
AA2
DVPDATA_3
AA3
DVPDATA_4
AB1
DVPDATA_5
AB2
DVPDATA_6
AB3
DVPDATA_7
AC1
DVPDATA_8
AC3
DVPDATA_9
AD1
DVPDATA_10
AD2
DVPDATA_11
AD3
DVPDATA_12
AF3
DVPDATA_13
AG3
DVPDATA_14
AH3
DVPDATA_15
AG1
DVPDATA_16
AH2
DVPDATA_17
AH1
DVPDATA_18
AJ3
DVPDATA_19
AJ1
DVPDATA_20
AJ2
DVPDATA_21
AK2
DVPDATA_22
AK3
DVPDATA_23
Y4
GPIO_0
V3
GPIO_1
V4
GPIO_2
V5
GPIO_3
U3
GPIO_4
U2
GPIO_5
T4
GPIO_6
T5
GPIO_7_BLON
T7
GPIO_8_ROMSO
T8
GPIO_9_ROMSI
R1
GPIO_10_ROMSCK
R2
GPIO_11
R3
GPIO_12
P1
GPIO_13
P3
GPIO_14_HPD2
N1
GPIO_15_PWRCNTL_0
N2
GPIO_16_SSIN
P4
GPIO_17_THERMAL_INT
P7
GPIO_18_HPD3
P8
GPIO_19_CTF
P5
GPIO_20_PWRCNTL_1
V7
GPIO_21_BB_EN
N3
GPIO_22_ROMCSB
Y5
GPIO_23_CLKREQB
M4
GPIO_24_JMODE
M5
GPIO_25_TDI
M7
GPIO_26_TCK
M8
GPIO_27_TMS
L8
GPIO_28_TDO
Y8
GEN_A
Y7
GEN_B
V8
GEN_C
AH6
GEN_D_HPD4
AG6
GEN_E
AC11
VREFG
AH12
DPLL_PVDD
AG12
DPLL_PVSS
AH31
PCIE_PVDD
A9
MPVDD
B9
MPVSS
AE12
DPLL_VDDC
AJ31
XTALIN
AJ30
XTALOUT
AH26
TESTEN
AD12
PLLTEST
216-0707001-00/M82-S_BGA632
216-0707001-00/M82-S_BGA632
4
PART 2 OF 6
PART 2 OF 6
INTEGRATED
INTEGRATED
TMDS/DP PORT
TMDS/DP PORT
EXT TMDS
EXT TMDS
DVO
DVO
GENERAL
GENERAL
PURPOSE
PURPOSE
I/O
I/O
PLL &
PLL &
XTAL
XTAL
TEST
TEST
3
polarity swap for ATI commond
DPA_PVDD
DPA_PVSS
DPB_PVDD
DPB_PVSS
DPA_VDDR
DPA_VDDR
DPB_VDDR
DPB_VDDR
DPB_VSSR
DPB_VSSR
DPB_VSSR
DPB_VSSR
DPB_VSSR
DPA_VSSR
DPA_VSSR
DPA_VSSR
DPA_VSSR
DPA_VSSR
DP_CALR
HPD1
HSYNC
VSYNC
RSET
AVDD
AVSSQ
VDD1DI
VSS1DI
COMP
V2SYNC
H2SYNC
A2VDD
A2VDDQ
A2VSSQ
VDD2DI
VSS2DI
R2SET
DDC1DATA
DDC1CLK
DDC2DATA
DDC2CLK
TS_FDO
DPLUS
DMINUS
AK9
AL9
AJ9
AJ10
AL10
AK10
AL11
AK11
40mA
+1.8VS_DPA
AL7
AK7
+1.8VS_DPB
AE11
AF11
AJ12
AJ13
AK13
AL13
AL12
AK12
AJ11
AH9
AH11
AJ8
AF7
AG7
AJ7
AH7
AG11
AA8
AL28
R
AK28
RB
AL27
G
AK27
GB
AL26
B
AK26
BB
AK29
AK30
AJ28
1 2
R1065 499_0402_1%R1065 499_0402_1%
AL29
AH28
AJ27
AJ26
AL17
R2
AK17
R2B
AL15
G2
AK15
G2B
AL14
B2
AK14
B2B
AJ17
C
AJ15
Y
AJ14
AE16
AF16
AH14
AH16
AG16
AF18
AE18
AG14
1 2
R1073 715_0402_1%R1073 715_0402_1%
AA5
SCL
AA4
SDA
AJ29
AH29
AC5
AC4
AF4
AH4
AF9
AG9
AE14
AE5
AE4
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
R1060 150_0402_1% R1060 150_0402_1%
1 2
RED
GREEN
BLUE
+A2VDD
+A2VDDQ
Issued Date
Issued Date
Issued Date
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
CRT_HSYNC <14,21,23>
CRT_VSYNC <14,23>
LCD_DDC_CLK <24>
VGA_DDC_DAT <23>
VGA_DDC_CLK <23>
HDMIDAT_VGA <25>
HDMICLK_VGA <25>
D+ <21>
D- <21>
3
TXCM_DPB0P
TXCP_DPB0N
TX0M_DPB1P
TX0P_DPB1N
TX1M_DPB2P
TX1P_DPB2N
TX2M_DPB3P
TX2P_DPB3N
DAC1 / CRT
DAC1 / CRT
DAC2 (TV/CRT2)
DAC2 (TV/CRT2)
SERIAL
SERIAL
BUSES
BUSES
DDC3DATA_DP3_AUXN
DDC3CLK_DP3_AUXP
DDC4DATA_DP4_AUXN
DDC4CLK_DP4_AUXP
THERMAL
THERMAL
+1.8VS
1 2
L96
L96
BLM18PG121SN1D_0603
+1.8VS
L99
L99
12
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
C11210.1U_0402_16V4Z C11210.1U_0402_16V4Z
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
C11270.1U_0402_16V4Z C11270.1U_0402_16V4Z
2
RED
GREEN
BLUE
1
C1148
C1148
2
BLM18PG121SN1D_0603
10U_0603_6.3V6M
10U_0603_6.3V6M
1 2
L98
L98
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
10U_0603_6.3V6M
10U_0603_6.3V6M
+1.8VS
200mA
1
1
C1123
C1123
C1122
C1122
2
2
10U_0603_6.3V6M
10U_0603_6.3V6M
200mA
1
1
C1128
C1128
C1129
C1129
2
2
10U_0603_6.3V6M
10U_0603_6.3V6M
1 2
R1061 150_0402_1%@R1061 150_0402_1%@
1 2
R1062 150_0402_1%@R1062 150_0402_1%@
1 2
R1064 150_0402_1%@R1064 150_0402_1%@
100mA
100mA
1
1
C1142
C1142
C1143
C1143
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
100mA
L107 0_0603_5%
L107 0_0603_5%
1
C1150
C1150
C1149
C1149
2
1U_0402_6.3V4Z@
1U_0402_6.3V4Z@
0.1U_0402_16V4Z@
0.1U_0402_16V4Z@
TMDS_B_CLK# <25>
TMDS_B_CLK <25>
TMDS_B_DATA0# <25>
TMDS_B_DATA0 <25>
TMDS_B_DATA1# <25>
TMDS_B_DATA1 <25>
TMDS_B_DATA2# <25>
TMDS_B_DATA2 <25>
1
1
C1119
C1119
C1118
C1118
LCD_DDC_DAT <24>
2
2
HPD <25>
RED <23>
GREEN <23>
BLUE <23>
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
C1120
C1120
10U_0603_6.3V6M
10U_0603_6.3V6M
+DPA_VDDR
+DPB_VDDR
+AVDD
+VDD1DI
1U_0402_6.3V4Z
1U_0402_6.3V4Z
48mA
1
2
10U_0603_6.3V6M@
10U_0603_6.3V6M@
LCD
CRT
HDMI
thermal
D+/D-=others 20mil/10mil/10mil/10mil/others 20mil
Compal Secret Data
Compal Secret Data
2007/10/11 200810/11
2007/10/11 200810/11
2007/10/11 200810/11
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
C1109
C1109
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
C1115
C1115
2
L101
L101
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
L102
L102
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
1
C1144
C1144
10U_0603_6.3V6M
10U_0603_6.3V6M
2
12
+1.8VS
2
1
1
C1110
C1110
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
C1116
C1116
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
12
+1.1VS
12
+1.1VS
L105
L105
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
10U_0603_6.3V6M@
10U_0603_6.3V6M@
1
C1145
C1145
2
0.1U_0402_16V4Z@
0.1U_0402_16V4Z@
+LVDDR
C1111
C1111
+LVDDC
C1117
C1117
12
1
C1146
C1146
2
1
U5F
U5F
PART 6 OF 6
PART 6 OF 6
AF20
LVDDR
AG20
LVDDR
AJ18
LVDDC
AH20
LVDDC
AF23
LVSSR
AF21
LVSSR
AL18
LVSSR
AJ22
LVSSR
AJ25
LVSSR
AK18
LVSSR
AK23
LVSSR
AK25
LVSSR
AJ21
LVSSR
AL23
LVSSR
AL25
LVSSR
AG18
LPVDD
AH18
LPVSS
216-0707001-00/M82-S_BGA632
216-0707001-00/M82-S_BGA632
1
C1130
C1130
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
C1147
C1147
1U_0402_6.3V4Z@
1U_0402_6.3V4Z@
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Control
Control
LVDS channel
LVDS channel
10U_0603_6.3V6M
10U_0603_6.3V6M
1
C1131
C1131
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
1
C256
C256
2
2
1
C1139
C1139
2
L106 0_0603_5%
L106 0_0603_5%
12
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
SCHEMATIC MB A4112
SCHEMATIC MB A4112
SCHEMATIC MB A4112
401568
401568
401568
VARY_BL
DIGON
TXCLK_UP
TXCLK_UN
TXOUT_U0P
TXOUT_U0N
TXOUT_U1P
TXOUT_U1N
TXOUT_U2P
TXOUT_U2N
TXOUT_U3P
TXOUT_U3N
TXCLK_LP
TXCLK_LN
TXOUT_L0P
TXOUT_L0N
TXOUT_L1P
TXOUT_L1N
TXOUT_L2P
TXOUT_L2N
TXOUT_L3P
TXOUT_L3N
+LPVDD
1
C1132
C1132
2
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
C255
C255
1
1
C1140
C1140
10U_0603_6.3V6M
10U_0603_6.3V6M
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+3.3V_DELAY
AA7
AC6
AD21
AE21
AJ24
AJ23
AK24
AL24
AG21
AH21
AG23
AH23
AL19
AK19
AJ20
AJ19
AK20
AL20
AK21
AL21
AK22
AL22
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
L114
L114
C1141
C1141
1
40mA
+1.8VS
320mA
80mA
1U_0402_6.3V4Z
1U_0402_6.3V4Z
+1.8VS_DPB
1
2
R299 10K_0402_5%R299 10K_0402_5%
12
VGA_PWM <24>
VGA_ENVDD <24>
LVDS_BCLK+ <24>
LVDS_BCLK- <24>
LVDS_B0+ <24>
LVDS_B0- <24>
LVDS_B1+ <24>
LVDS_B1- <24>
LVDS_B2+ <24>
LVDS_B2- <24>
LVDS_ACLK+ <24>
LVDS_ACLK- <24>
LVDS_A0+ <24>
LVDS_A0- <24>
LVDS_A1+ <24>
LVDS_A1- <24>
LVDS_A2+ <24>
LVDS_A2- <24>
12
+1.8VS
L103
L103
12
+1.8VS
12
L104
L104
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
of
16 54Friday, February 13, 2009
of
16 54Friday, February 13, 2009
of
16 54Friday, February 13, 2009
+1.8VS
F
F
F
5
MDA[63..32]<20>
D D
MDA[31..0]<19>
MDA[63..32]
MDA[31..0]
C C
+1.8VS
12
R1077
R1077
100_0402_1%
100_0402_1%
+VDD_MEM18_REFD
1
12
C1152
C1152
0.1U_0402_16V4Z
R1078
R1078
100_0402_1%
100_0402_1%
B B
0.1U_0402_16V4Z
2
100_0402_1%
100_0402_1%
R1082
R1082
+1.8VS
12
+VDD_MEM18_REFS
R1079
R1079
4.7K_0402_5%
4.7K_0402_5%
12
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63
12
R1081
R1081
4.7K_0402_5%
4.7K_0402_5%
4
U5C
U5C
E29
E30
E31
D31
C29
B29
B30
A29
E26
D26
E25
D25
G23
G21
E21
D21
C28
B28
B27
A27
C25
A25
C24
B24
C23
B23
A23
B22
C20
B20
A20
C19
C8
C7
B7
A7
A5
C4
B4
A3
G9
E9
D9
G7
G5
F5
G4
F4
B3
B2
C2
C1
E3
F3
F2
F1
G2
G1
H3
H2
K2
L3
L2
L1
F30
F31
L5
L7
J7
216-0707001-00/M82-S_BGA632
216-0707001-00/M82-S_BGA632
12
R1083
R1083
240_0402_1%
240_0402_1%
DQ_0
DQ_1
DQ_2
DQ_3
DQ_4
MEMORY
MEMORY
DQ_5
INTERFACE
INTERFACE
DQ_6
DQ_7
DQ_8
DQ_9
DQ_10
DQ_11
DQ_12
DQ_13
DQ_14
DQ_15
DQ_16
DQ_17
DQ_18
DQ_19
DQ_20
DQ_21
DQ_22
DQ_23
DQ_24
DQ_25
DQ_26
DQ_27
DQ_28
DQ_29
DQ_30
DQ_31
DQ_32
DQ_33
DQ_34
DQ_35
DQ_36
DQ_37
DQ_38
DQ_39
DQ_40
DQ_41
DQ_42
DQ_43
DQ_44
DQ_45
DQ_46
DQ_47
DQ_48
DQ_49
DQ_50
DQ_51
DQ_52
DQ_53
DQ_54
DQ_55
DQ_56
DQ_57
DQ_58
DQ_59
DQ_60
DQ_61
DQ_62
DQ_63
MVREFD
MVREFS
TEST_MCLK
TEST_YCLK
MEMTEST
Part 3 of 6
Part 3 of 6
MA_0
MA_1
MA_2
MA_3
MA_4
MA_5
MA_6
MA_7
MA_8
MA_9
MA_10
MA_11
MA_BA0
MA_BA1
MA_A12
MA_BA2
DQMB_0
DQMB_1
DQMB_2
DQMB_3
DQMB_4
DQMB_5
DQMB_6
DQMB_7
QS_0
QS_1
QS_2
QS_3
QS_4
QS_5
QS_6
QS_7
QS_0B
QS_1B
QS_2B
QS_3B
QS_4B
QS_5B
QS_6B
write strobe read strobe
write strobe read strobe
QS_7B
ODT0
ODT1
CLK0
CLK1
CLK0B
CLK1B
RAS0B
RAS1B
CAS0B
CAS1B
CS0B_0
CS0B_1
CS1B_0
CS1B_1
CKE0
CKE1
WE0B
WE1B
DRAM_RST
B14
A14
B13
E14
B17
A17
C15
G16
E16
C14
A12
B12
C12
D14
B15
G14
D30
G25
C26
C21
C5
D6
D2
K3
C30
D23
B26
B21
B6
E7
E2
J2
C31
E23
A26
A21
A6
D7
E1
J1
E20
C11
A18
A11
B18
B11
G20
D12
D20
E12
E18
G18
G11
E11
D18
G12
D16
C10
J5
R1080
R1080
4.7K_0402_5%
4.7K_0402_5%
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
BA0
BA1
MAA12
BA2
DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7
QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7
QSA#0
QSA#1
QSA#2
QSA#3
QSA#4
QSA#5
QSA#6
QSA#7
ODTA0
ODTA1
CLKA0
CLKA1
CLKA0#
CLKA1#
RASA#0
RASA#1
CASA#0
CASA#1
CSA0#
CSA1#
CKEA0
CKEA1
WEA#0
WEA#1
12
3
MAA[12..0]
BA[2..0]
DQMA#[3..0] <19>
DQMA#[7..4] <20>
QSA[3..0] <19>
QSA[7..4] <20>
QSA#[3..0] <19>
QSA#[7..4] <20>
ODTA0 <19>
ODTA1 <20>
CLKA0 <19>
CLKA1 <20>
CLKA0# <19>
CLKA1# <20>
RASA#0 <19>
RASA#1 <20>
CASA#0 <19>
CASA#1 <20>
CSA0# <19>
CSA1# <20>
CKEA0 <19>
CKEA1 <20>
WEA#0 <19>
WEA#1 <20>
MAA[12..0] <19,20>
BA[2..0] <19,20>
2
1
12
R1084
R1084
100_0402_1%
100_0402_1%
A A
5
1
C1153
C1153
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2007/10/11 200810/11
2007/10/11 200810/11
2007/10/11 200810/11
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
SCHEMATIC MB A4112
SCHEMATIC MB A4112
SCHEMATIC MB A4112
401568
401568
401568
17 54Friday, February 13, 2009
17 54Friday, February 13, 2009
17 54Friday, February 13, 2009
1
F
F
F
of
of
of
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