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CQ40
Schematics
56 pgs900.74 Kb0
Schematics
55 pgs1.05 Mb0
Schematics REV 0.4
54 pgs1.24 Mb0
Schematics
46 pgs1.72 Mb0

HP CQ40 Schematics REV 0.2 14NOV2007

A
hexainf@hotmail.com
1 1
2 2
B
C
D
E
Compal confidential
Schematics Document
Mobile AMD S1G2 CPU with ATI RS780M(NB) & SB700(SB) core logic
3 3
2007-11-14
REV:0.2
4 4
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2007/08/02 2008/08/02
Deciphered Date
Title
Size Document Number Rev
Custom
D
Date: Sheet
Compal Electronics, Inc.
Cover Sheet
LA-4111P
147Thursday, November 15, 2007
E
0.2
of
A
Compal Confidential
B
C
D
Consumer AMD 14" UMA - Ripley (JBL20)
E
1 1
Accelerometer ST LIS302DLTR
Page 30
Thermal Sensor ADM1032ARMZ
Page 6
Fan conn
Page 4
AMD S1G2 CPU
638-PIN uFCPGA 638
Page 4, 5, 6, 7
DDR2 800MHz 1.8V
Dual Channel
DDR2-SO-DIMM X2
BANK 0, 1, 2, 3
Page 8, 9
72QFN
Clock Generator SLG8SP626VTR
Page 15
Side-Port DDR2 SDRAM
Hyper Transport Link
16X16
LVDS Panel
Page 16
Page 18
Page 17
A-Link Express II
Interface
2 2
CRT
HDMI
PCI-E BUS*5
CardReader JMicron JMB385-LGEZ0A
3 3
CardReade r Socket
Page 27
Page 27
Realtek 8102E(10/100M)
Page 25
RJ45/11 CONN
Page 25
Mini-Card*2
WLAN & WWAN
Page 26
Express Card
Page 26
ATI RS780M
4X PCI-E
ATI SB700
DDR2 400MHz
Page 10, 11, 12, 13, 14
USB2.0 X12
Azalia (HDA I/F) SATA Master-1 SATA Master-2 SATA Slave SATA Slave
Page 19, 20, 21, 22, 23
LPC BUS
256Mbits(16Mbx16)
USB conn x2
BT Conn
Mini-Card WWAN
14" Only
USB conn x1
Page 12
Page 31
Page 31
Page 26
Page 31
USB WebCam
Page 17
FingerPrinter AES1610 USBx1
MDC V1.5
page 35
Page 34
Audio CKT
Codec_IDT9271B7
Page 28 Page 29
daughter board
daughter board
daughter board
daughter board
daughter board
AMP & Audio Jack
TPA6017A2
KBC
ENE KB926
Page 33
Docking CONN.
*RJ-45(LED*2) *RJ-11(Pass Through) *CRT *COMPOSITE Video Out *S-VIDEO OUT *SPDIF *Headphone/Line Out L/R *Stereo Mic L/R
4 4
*Volume Control
LED
P41
RTC CKT.
Page 19
Power OK CKT.
P35
Touch Pad CONN. Int.KBD
Consumer IR
Page 34
SPI
Page 34
Page 33
SPI ROM SST25VF080B
Page 32
SATA HDD Connector
SATA ODD Connector
Multi-Bay HDD/ODD Option Connector
14" UMA PA Only
Page 24
Page 24
Page 24
e-SATA Con nector
Page 31
*Consumer IR *USB x1 *DC JACK
Page 35
A
Power On/Off CKT.
P35
DC/DC Int erface CKT.
Page 36
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2007/08/02 2008/08/02
Deciphered Date
Title
Size Document Number Rev
Custom
D
Date: Sheet
Compal Electronics, Inc.
Block Diagram
LA-4111P
247Thursday, No vember 15, 2007
E
0.2
of
A
hexainf@hotmail.com
B
C
D
E
Voltage Rails
1 1
State
2 2
S0
S1
S3
S5 S4/AC
S5 S4/ Battery only
S5 S4/AC & Battery don't exist
3 3
I2C / SMBUS ADDRESSING
DEVICE
DDR SO-DIMM 0 DDR SO-DIMM 1 CLOCK GENERATOR (EXT.)
EC SM Bus1 address
Device
Smart Battery
24C16
4 4
O MEANS ON X MEANS OFF
power plane
HEX
A0
D2
+B
O O O O O
X
+5VALW
+3VALW
O O O O
X XX X
ADDRESS
1 0 1 0 0 0 0 0 1 0 1 0 0 1 0 0A4 1 1 0 1 0 0 1 0
+1.8V
EC SM Bus2 address
HEX
Address Address
16H
1010 000X b
A0H
Device
CPU
ADI1032-2 CPU
HEX
98H 9AH
+5VS +3VS +1.5VS +0.9V +VCCP +CPU_CORE
+VGA_CORE +2.5VS +1.8VS +1.2VS +0.9VGA
OO OO
O
X XX X
1001 100X b0001 011X b 1001 101X b
X
SMBUS Control Table
SMB_EC_CK1 SMB_EC_DA1 SMB_EC_CK2 SMB_EC_DA2 I2C_CLK I2C_DATA DDC_CLK0 DDC_DATA0 DDC_CLK1 DDC_DATA1 SCL0 SDA0 SCL1 SDA1 SCL2 SDA2 SCL3 SDA3
Symbol Note :
: means Digital Ground
: means Analog Ground
@ : means just reserve , no build DEBUG@ : means jus t r e s e r v e for debug.
Layout Notes
L
UMA@ : means for RS780M. Please see VGA@ as no install. No support RX780M.
11/14 update
: Question Ar ea Mark.(Wait check)
SOURCE
KB926
KB926
RS780M
RS780M
RS780M
SB700
SB700
SB700
SB700
INVERTER BATT EEPROM
X
SERIAL SENSOR
VV
XXX XXX X X X X XXX X X XXX X X XXX X X
THERMAL
CPU & ADM1032
SODIMM CLK CHIP
XX
V
XXXX
XXX XXX X
VV
XXXX XXXX XXXX
XX
MINI CARD
Slot 2I / II
LCD
XX
X
V
V
X X
HDMI
X X X
V
XX XXXX XXXX XX
G-Sensor
X X X X X X X
V
X
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2007/08/02 2008/08/02
Deciphered Date
Title
Size Document Number Rev
Custom
D
Date: Sheet
Compal Electronics, Inc.
Notes List
LA-4111P
347Thursday, November 15, 2007
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0.2
of
A
1 1
H_CADIP[0..15]<10>
H_CADIP[0..15] H_CADIN[0..15]
B
H_CADOP[0..15] H_CADON[0..15]
H_CADOP[0..15] <10> H_CADON[0..15] <10>H_CADIN[0..15]<10>
C
+1.2V_HT
250 mil
1
C1
4.7U_0805_10V4Z
2
1
C2
4.7U_0805_10V4Z
2
D
VLDT CAP.
1
C3
0.22U_0603_16V4Z
2
1
C4
0.22U_0603_16V4Z
2
1
C5 180P_0402_50V8J
2
E
1
C6 180P_0402_50V8J
2
Near CPU Socket
+1.2V_HT
VLDT=500mA
H_CADIP0 H_CADIN0 H_CADIP1 H_CADIN1 H_CADIP2
2 2
H_CLKIP0<10> H_CLKIN0<10> H_CLKIP1<10>
3 3
H_CLKIN1<10> H_CTLIP0<10> H_CTLIP1<10> H_CTLOP1 <10>
H_CTLIN1<10>
H_CADIN2 H_CADIP3 H_CADIN3 H_CADIP4 H_CADIN4 H_CADIP5 H_CADIN5 H_CADIP6 H_CADIN6 H_CADIP7 H_CADIN7 H_CADIP8 H_CADIN8 H_CADIP9 H_CADIN9 H_CADIP10 H_CADIN10 H_CADIP11 H_CADIN11 H_CADIP12 H_CADIN12 H_CADIP13 H_CADIN13 H_CADIP14 H_CADIN14 H_CADIP15 H_CADIN15
JCPUA
D1 D2 D3 D4
E3 E2 E1
F1 G3 G2 G1 H1
J1
K1
L3
L2
L1 M1 N3 N2
E5
F5
F3
F4 G5 H5 H3 H4
K3
K4
L5 M5 M3 M4 N5
P5
J3
J2
J5
K5 N1
P1
P3
P4
9/20 SP07000DM00/SP07000EQ00
HT LINK
VLDT_A0 VLDT_A1 VLDT_A2 VLDT_A3
L0_CADIN_H0 L0_CADIN_L0 L0_CADIN_H1 L0_CADIN_L1 L0_CADIN_H2 L0_CADIN_L2 L0_CADIN_H3 L0_CADIN_L3 L0_CADIN_H4 L0_CADIN_L4 L0_CADIN_H5 L0_CADIN_L5 L0_CADIN_H6 L0_CADIN_L6 L0_CADIN_H7 L0_CADIN_L7 L0_CADIN_H8 L0_CADIN_L8 L0_CADIN_H9 L0_CADIN_L9 L0_CADIN_H10 L0_CADIN_L10 L0_CADIN_H11 L0_CADIN_L11 L0_CADIN_H12 L0_CADIN_L12 L0_CADIN_H13 L0_CADIN_L13 L0_CADIN_H14 L0_CADIN_L14 L0_CADIN_H15 L0_CADIN_L15
L0_CLKIN_H0 L0_CLKIN_L0 L0_CLKIN_H1 L0_CLKIN_L1
L0_CTLIN_H0 L0_CTLIN_L0 L0_CTLIN_H1 L0_CTLIN_L1
FOX_PZ6382A-284S-41F_GRIFFIN
CONN@
Athlon 64 S1 Processor Socket
VLDT_B0 VLDT_B1 VLDT_B2 VLDT_B3
L0_CADOUT_H0 L0_CADOUT_L0 L0_CADOUT_H1 L0_CADOUT_L1 L0_CADOUT_H2 L0_CADOUT_L2 L0_CADOUT_H3 L0_CADOUT_L3 L0_CADOUT_H4 L0_CADOUT_L4 L0_CADOUT_H5 L0_CADOUT_L5 L0_CADOUT_H6 L0_CADOUT_L6 L0_CADOUT_H7 L0_CADOUT_L7 L0_CADOUT_H8 L0_CADOUT_L8 L0_CADOUT_H9
L0_CADOUT_L9 L0_CADOUT_H10 L0_CADOUT_L10 L0_CADOUT_H11 L0_CADOUT_L11 L0_CADOUT_H12 L0_CADOUT_L12 L0_CADOUT_H13 L0_CADOUT_L13 L0_CADOUT_H14 L0_CADOUT_L14 L0_CADOUT_H15 L0_CADOUT_L15
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1 L0_CTLOUT_H0
L0_CTLOUT_L0 L0_CTLOUT_H1 L0_CTLOUT_L1
+VLDT_B
AE2 AE3 AE4 AE5
AD1 AC1 AC2 AC3 AB1 AA1 AA2 AA3 W2 W3 V1 U1 U2 U3 T1 R1 AD4 AD3 AD5 AC5 AB4 AB3 AB5 AA5 Y5 W5 V4 V3 V5 U5 T4 T3
Y1 W1 Y4 Y3
R2 R3 T5 R5
1 2
C7 4.7U_0805_10V4Z
If VLDT is connected only on one side, one
4.7uF cap should be added to the island
H_CADOP0 H_CADON0 H_CADOP1 H_CADON1 H_CADOP2 H_CADON2 H_CADOP3 H_CADON3 H_CADOP4 H_CADON4 H_CADOP5 H_CADON5 H_CADOP6 H_CADON6 H_CADOP7 H_CADON7 H_CADOP8 H_CADON8 H_CADOP9 H_CADON9 H_CADOP10 H_CADON10 H_CADOP11 H_CADON11 H_CADOP12 H_CADON12 H_CADOP13 H_CADON13 H_CADOP14 H_CADON14 H_CADOP15 H_CADON15
side.
H_CLKOP0 <10> H_CLKON0 <10> H_CLKOP1 <10> H_CLKON1 <10>
H_CTLOP0 <10> H_CTLON0 <10>H_CTLIN0<10>
H_CTLON1 <10>
PWM Fan Control circuit
CH751H-40PT_SOD323-2
FAN_PWM<33>
+5VS
1
D1
2 1
6
2
1
D
Q1
G
3
S
SI3456BDV-T1-E3_TSOP6
4 5
C8
4.7U_0805_10V4Z
2
+VCC_FAN
1
C9
0.1U_0402_16V4Z
2
12
D2
@
RLZ5.1B_LL34
11/14 update
JP2
1
1
2
2
3
GND
4
GND
ACES_88231-02001
CONN@
Change PCB Footprint from ACES_85204-02001_2P to ACES_88231-02001_2P
4 4
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2007/08/02 2008/08/02
Deciphered Date
Title
Size Document Number Rev
Custom
D
Date: Sheet
Compal Electronics, Inc.
AMD CPU S1G2 HT I/F
LA-4111P
447Thursday, No vember 15, 2007
E
0.2
of
A
hexainf@hotmail.com
B
C
D
E
Processor DDR2 Memory Interface
PLACE CLOSE TO P ROCESSOR
1 1
2 2
Place them close to CPU within 1"
R4 39.2_0402_1%
1 2
DDR_A_BS#0<8> DDR_A_BS#1<8> DDR_A_BS#2<8>
DDR_A_RAS#<8> DDR_A_CAS#<8> DDR_A_WE#<8>
1 2
R3 39.2_0402_1%
T2 PA D
DDR_A_ODT0 DDR_A_ODT1
DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS0_DIMMB#
DDR_CKE0_DIMMA DDR_CKE1_DIMMA
DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK1
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15
DDR_A_BS#0 DDR_A_BS#1 DDR_A_BS#2
DDR_A_RAS# DDR_A_CAS# DDR_A_WE#
+1.8V
DDR_A_ODT0<8> DDR_A_ODT1<8>
DDR_CS0_DIMMA#<8> DDR_CS1_DIMMA#<8> DDR_CS0_DIMMB# <9>
DDR_CKE0_DIMMA<8> DDR_CKE1_DIMMA<8>
DDR_A_CLK0<8>
DDR_A_CLK#0<8>
3 3
4 4
DDR_A_CLK1<8>
DDR_A_CLK#1<8>
DDR_A_MA[15..0]<8> DDR_B_MA[15..0] <9>
AD10 AF10
AE10
AA16
D10 C10 B10
H16 T19
V22 U21 V19
T20 U19 U20 V20
J22 J20
N19 N20 E16 F16 Y16
P19 P20
N21 M20 N22 M19 M22 L20 M24 L21 L19 K22 R21 L22 K20 V24 K24 K19
R20 R23
J21
R19 T22 T24
WITHIN 1.5 INCH
DDR_A_CLK0
DDR_A_CLK#0 DDR_A_CLK1
DDR_A_CLK#1
DDR_B_CLK0
DDR_B_CLK#0 DDR_B_CLK1
DDR_B_CLK#1
JCPUB
VTT1
MEM:CMD/CTRL/CLK
VTT2 VTT3 VTT4
MEMZP MEMZN
RSVD_M1 MA0_ODT0
MA0_ODT1 MA1_ODT0 MA1_ODT1
MA0_CS_L0 MA0_CS_L1 MA1_CS_L0 MA1_CS_L1
MA_CKE0 MA_CKE1
MA_CLK_H5 MA_CLK_L5 MA_CLK_H1 MA_CLK_L1 MA_CLK_H7 MA_CLK_L7 MA_CLK_H4 MA_CLK_L4
MA_ADD0 MA_ADD1 MA_ADD2 MA_ADD3 MA_ADD4 MA_ADD5 MA_ADD6 MA_ADD7 MA_ADD8 MA_ADD9 MA_ADD10 MA_ADD11 MA_ADD12 MA_ADD13 MA_ADD14 MA_ADD15
MA_BANK0 MA_BANK1 MA_BANK2
MA_RAS_L MA_CAS_L MA_WE_L
FOX_PZ6382A-284S-41F_GRIFFIN
Athlon 64 S1 Processor Socket
CONN@
1
2
1
2
1
2
1
2
VTT_SENSE
MEMVREF
RSVD_M2
MB0_ODT0 MB0_ODT1 MB1_ODT0
MB0_CS_L0 MB0_CS_L1 MB1_CS_L0
MB_CKE0 MB_CKE1
MB_CLK_H5
MB_CLK_L5
MB_CLK_H1
MB_CLK_L1
MB_CLK_H7
MB_CLK_L7
MB_CLK_H4
MB_CLK_L4
MB_ADD0 MB_ADD1 MB_ADD2 MB_ADD3 MB_ADD4 MB_ADD5 MB_ADD6 MB_ADD7 MB_ADD8
MB_ADD9 MB_ADD10 MB_ADD11 MB_ADD12 MB_ADD13 MB_ADD14 MB_ADD15
MB_BANK0 MB_BANK1 MB_BANK2
MB_RAS_L MB_CAS_L
MB_WE_L
C10
1.5P_0402_50V9C
C11
1.5P_0402_50V9C
C14
1.5P_0402_50V9C
C15
1.5P_0402_50V9C
W10
VTT5
AC10
VTT6
AB10
VTT7
AA10
VTT8
A10
VTT9
Y10 W17 B18 W26
W23 Y26
V26 W25 U22
J25 H26
P22 R22 A17 A18 AF18 AF17 R26 R25
P24 N24 P26 N23 N26 L23 N25 L24 M26 K26 T26 L26 L25 W24 J23 J24
R24 U26 J26
U25 U24 U23
+0.9V+0.9V
VTT_SENSE
+MCH_REF
DDR_B_ODT0 DDR_B_ODT1
DDR_CS1_DIMMB#
DDR_CKE0_DIMMB DDR_CKE1_DIMMB
DDR_B_CLK0 DDR_B_CLK#0 DDR_B_CLK1 DDR_B_CLK#1DDR_A_CLK#1
DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15
DDR_B_BS#0 DDR_B_BS#1 DDR_B_BS#2
DDR_B_RAS# DDR_B_CAS# DDR_B_WE#
+1.8V
R1
1K_0402_1%
R2
1K_0402_1%
T1PAD
09/13 update
T3PAD
DDR_B_ODT0 <9> DDR_B_ODT1 <9>
DDR_CS1_DIMMB# <9>
DDR_CKE0_DIMMB <9> DDR_CKE1_DIMMB <9>
DDR_B_CLK0 <9> DDR_B_CLK#0 <9> DDR_B_CLK1 <9> DDR_B_CLK#1 <9>
DDR_B_BS#0 <9> DDR_B_BS#1 <9> DDR_B_BS#2 <9>
DDR_B_RAS# <9> DDR_B_CAS# <9> DDR_B_WE# <9>
09/13 update
1 2
+MCH_REF
1
C12
2
1 2
0.1U_0402_16V4Z
DDR_B_D[63..0]<9>
1
C13
2
1000P_0402_25V8J
DDR_B_DM[7..0]<9> DDR_A_DM[7..0] <8>
DDR_B_DQS0<9> DDR_B_DQS#0<9> DDR_B_DQS1<9> DDR_B_DQS#1<9> DDR_B_DQS2<9> DDR_B_DQS#2<9> DDR_B_DQS3<9> DDR_B_DQS#3<9> DDR_B_DQS4<9> DDR_B_DQS#4<9> DDR_B_DQS5<9> DDR_B_DQS#5<9> DDR_B_DQS6<9> DDR_B_DQS#6<9> DDR_B_DQS7<9> DDR_B_DQS#7<9>
DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63
DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7
DDR_B_DQS0 DDR_B_DQS#0 DDR_B_DQS1 DDR_B_DQS#1 DDR_B_DQS2 DDR_B_DQS#2 DDR_B_DQS3 DDR_B_DQS#3 DDR_B_DQS4 DDR_B_DQS#4 DDR_B_DQS5 DDR_B_DQS#5 DDR_B_DQS6 DDR_B_DQS#6 DDR_B_DQS7 DDR_B_DQS#7
JCPUC
C11 A11 A14 B14 G11 E11 D12 A13 A15 A16 A19 A20 C14 D14 C18 D18 D20 A21 D24 C25 B20 C20 B24 C24 E23 E24 G25 G26 C26 D26 G23
G24 AA24 AA23 AD24 AE24 AA26 AA25 AD26 AE25 AC22 AD22 AE20 AF20 AF24 AF23 AC20 AD20 AD18 AE18 AC14 AD14 AF19 AC18 AF16 AF15 AF13 AC12 AB11
Y11 AE14 AF14 AF11 AD11
A12
B16
A22
E25 AB26 AE22 AC16 AD12
C12
B12
D16
C16
A24
A23
F26
E26 AC25 AC26 AF21 AF22 AE16 AD16 AF12 AE12
FOX_PZ6382A-284S-41F_GRIFFIN
Athlon 64 S1 Processor Socket
CONN@
MB_DATA0 MB_DATA1 MB_DATA2 MB_DATA3 MB_DATA4 MB_DATA5 MB_DATA6 MB_DATA7 MB_DATA8 MB_DATA9 MB_DATA10 MB_DATA11 MB_DATA12 MB_DATA13 MB_DATA14 MB_DATA15 MB_DATA16 MB_DATA17 MB_DATA18 MB_DATA19 MB_DATA20 MB_DATA21 MB_DATA22 MB_DATA23 MB_DATA24 MB_DATA25 MB_DATA26 MB_DATA27 MB_DATA28 MB_DATA29 MB_DATA30 MB_DATA31 MB_DATA32 MB_DATA33 MB_DATA34 MB_DATA35 MB_DATA36 MB_DATA37 MB_DATA38 MB_DATA39 MB_DATA40 MB_DATA41 MB_DATA42 MB_DATA43 MB_DATA44 MB_DATA45 MB_DATA46 MB_DATA47 MB_DATA48 MB_DATA49 MB_DATA50 MB_DATA51 MB_DATA52 MB_DATA53 MB_DATA54 MB_DATA55 MB_DATA56 MB_DATA57 MB_DATA58 MB_DATA59 MB_DATA60 MB_DATA61 MB_DATA62 MB_DATA63
MB_DM0 MB_DM1 MB_DM2 MB_DM3 MB_DM4 MB_DM5 MB_DM6 MB_DM7
MB_DQS_H0 MB_DQS_L0 MB_DQS_H1 MB_DQS_L1 MB_DQS_H2 MB_DQS_L2 MB_DQS_H3 MB_DQS_L3 MB_DQS_H4 MB_DQS_L4 MB_DQS_H5 MB_DQS_L5 MB_DQS_H6 MB_DQS_L6 MB_DQS_H7 MB_DQS_L7
MEM:DATA
MA_DATA0 MA_DATA1 MA_DATA2 MA_DATA3 MA_DATA4 MA_DATA5 MA_DATA6 MA_DATA7 MA_DATA8
MA_DATA9 MA_DATA10 MA_DATA11 MA_DATA12 MA_DATA13 MA_DATA14 MA_DATA15 MA_DATA16 MA_DATA17 MA_DATA18 MA_DATA19 MA_DATA20 MA_DATA21 MA_DATA22 MA_DATA23 MA_DATA24 MA_DATA25 MA_DATA26 MA_DATA27 MA_DATA28 MA_DATA29 MA_DATA30 MA_DATA31 MA_DATA32 MA_DATA33 MA_DATA34 MA_DATA35 MA_DATA36 MA_DATA37 MA_DATA38 MA_DATA39 MA_DATA40 MA_DATA41 MA_DATA42 MA_DATA43 MA_DATA44 MA_DATA45 MA_DATA46 MA_DATA47 MA_DATA48 MA_DATA49 MA_DATA50 MA_DATA51 MA_DATA52 MA_DATA53 MA_DATA54 MA_DATA55 MA_DATA56 MA_DATA57 MA_DATA58 MA_DATA59 MA_DATA60 MA_DATA61 MA_DATA62 MA_DATA63
MA_DM0 MA_DM1 MA_DM2 MA_DM3 MA_DM4 MA_DM5 MA_DM6 MA_DM7
MA_DQS_H0 MA_DQS_L0 MA_DQS_H1 MA_DQS_L1 MA_DQS_H2 MA_DQS_L2 MA_DQS_H3 MA_DQS_L3 MA_DQS_H4 MA_DQS_L4 MA_DQS_H5 MA_DQS_L5 MA_DQS_H6 MA_DQS_L6 MA_DQS_H7 MA_DQS_L7
G12 F12 H14 G14 H11 H12 C13 E13 H15 E15 E17 H17 E14 F14 C17 G17 G18 C19 D22 E20 E18 F18 B22 C23 F20 F22 H24 J19 E21 E22 H20 H22 Y24 AB24 AB22 AA21 W22 W21 Y22 AA22 Y20 AA20 AA18 AB18 AB21 AD21 AD19 Y18 AD17 W16 W14 Y14 Y17 AB17 AB15 AD15 AB13 AD13 Y12 W11 AB14 AA14 AB12 AA12
E12 C15 E19 F24 AC24 Y19 AB16 Y13
G13 H13 G16 G15 C22 C21 G22 G21 AD23 AC23 AB19 AB20 Y15 W15 W12 W13
DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63
DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7
DDR_A_DQS0 DDR_A_DQS#0 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS7 DDR_A_DQS#7
DDR_A_D[63..0] <8>
DDR_A_DQS0 <8> DDR_A_DQS#0 <8> DDR_A_DQS1 <8> DDR_A_DQS#1 <8> DDR_A_DQS2 <8> DDR_A_DQS#2 <8> DDR_A_DQS3 <8> DDR_A_DQS#3 <8> DDR_A_DQS4 <8> DDR_A_DQS#4 <8> DDR_A_DQS5 <8> DDR_A_DQS#5 <8> DDR_A_DQS6 <8> DDR_A_DQS#6 <8> DDR_A_DQS7 <8> DDR_A_DQS#7 <8>
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2007/08/02 2008/08/02
Deciphered Date
Title
Size Document Number Rev
Custom
D
Date: Sheet
Compal Electronics, Inc.
AMD CPU S1G2 DDRII I/F
LA-4111P
547Thursday, No vember 15, 2007
E
0.2
of
A
A:Need to re-Link "SGN00000200"
1 1
CLK_CPU_BCLK<15>
+2.5VS
C16
100U_D2_10VM
Place close to CPU wihtin 1.5"
C20
0718 Silego -- 216 ohm
CLK_CPU_BCLK#<15>
+1.8V
2 2
LDT_RST#<19>
09/13 update
H_PWRGD_CPU<19>
3 3
LDT_STOP#<11,19>
R15 300_0402_5%
1 2
LDT_RST#
1
C22
0.01U_0402_25V4Z
@
2
+1.8V
R21 300_0402_5%
1 2
H_PWRGD_CPU
1
C23
0.01U_0402_25V4Z
@
2
+1.8V
R36 300_0402_5%
1 2
LDT_STOP#
1
C25
0.01U_0402_25V4Z
@
2
0718 AMD , need check with AMD
+1.8V
R30 300_0402_5%
1 2
4 4
CPU_LDT_REQ#
1
C24
0.01U_0402_25V4Z
@
2
CPU_LDT_REQ# <11,19>
A
+CPU_CORE_0
R487 10_0402_5%
1 2 1 2
R486 10_0402_5%
+CPU_CORE_1
R489 10_0402_5%
1 2 1 2
R488 10_0402_5%
+3VS
20K_0402_5%
390_0402_5%
390_0402_5%
CPU_SIC
+3VS
0.1U_0402_16V4Z
C27
1 2
2200P_0402_50V7K
R18
R19
1
C26
2
+1.8V
+1.8V
2200p change to 1000p for ADT7421
CPU_VDD0_FB_H CPU_VDD0_FB_L
Close to CPU
CPU_VDD1_FB_H CPU_VDD1_FB_L
R175
12
S
Q127
12
FDV301N_NL_SOT23-3
12
FDV301N_NL_SOT23-3 Q129
THERMDA_CPU THERMDC_CPU
C21 3900P_0402_50V7K
G
B
L1
1 2
FBM_L11_201209_300L_0805
1
+
2
3900P_0402_50V7K
1 2
12
R8 169_0402_1%
1 2
1 2
C939 0.1U_0402_16V4Z
R814
12
34.8K_0402_1%~N
2
SMB_EC_DA2CPU_SID
13
D
G
2
SMB_EC_CK2
13
D
S
EC is PU to 5VALW
FDV301N, the Vgs is: min = 0.65V Typ = 0.85V Max = 1.5V
U2
1
VDD D+
SDATA
ALERT#
D­THERM#4GND
B
SCLK
2 3
ADM1032ARMZ-2REEL_MSOP8
Address:100_1101
+2.5VDDA
VDDA=300mA
3300P_0402_50V7K
1
1
C174.7U_0805_10V4Z
C18
2
2
Address:100_1100
R13 44.2_0402_1%
1 2
R14 44.2_0402_1%
T4 PAD
T9 PAD T11 PAD
1 2
CPU_VDD0_FB_H<43> CPU_VDD0_FB_L<43>
CPU_VDD1_FB_H<43> CPU_VDD1_FB_L<43>
+1.2V_HT
2.09V for Gate
SMB_EC_DA2 <33>
SMB_EC_CK2 <33>
SMB_EC_CK2
8
SMB_EC_DA2
7 6 5
1
C19
0.22U_0603_16V4Z
2
CPU_CLKIN_SC_P CPU_CLKIN_SC_N
LDT_RST# H_PWRGD_CPU LDT_STOP# CPU_LDT_REQ#
CPU_SIC CPU_SID
CPU_HTREF0 CPU_HTREF1
CPU_VDD0_FB_H CPU_VDD0_FB_L
CPU_VDD1_FB_H
CPU_DBRDY CPU_TMS CPU_TCK CPU_TRST# CPU_TDI
CPU_TEST23_TSTUPD
CPU_TEST19_PLLTEST0 CPU_TEST18_PLLTEST1
CPU_TEST25_H_BYPASSCLK_H CPU_TEST25_L_BYPASSCLK_L
CPU_TEST21_SCANEN CPU_TEST20_SCANCLK2 CPU_TEST24_SCANCLK1 CPU_TEST22_SCANSHIFTEN CPU_TEST12_SCANSHIFTENB CPU_TEST27_SINGLECHAIN
R25 0_0402_5%
1 2
CPU_DBREQ# CPU_DBRDY CPU_TCK CPU_TMS CPU_TDI CPU_TRST# CPU_TDO
NOTE: HDT TERMINATION IS REQUIRED FOR REV. Ax SILICON ONLY.
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
JCPUD
F8
VDDA1
F9
VDDA2
A9
CLKIN_H
A8
CLKIN_L
B7
RESET_L
A7
PWROK
F10
LDTSTOP_L
C6
LDTREQ_L
AF4
SIC
AF5
SID
AE6
ALERT_L
R6
HT_REF0
P6
HT_REF1
F6
VDD0_FB_H
E6
VDD0_FB_L
Y6
VDD1_FB_H
AB6
VDD1_FB_L
G10
DBRDY
AA9
TMS
AC9
TCK
AD9
TRST_L
AF9
TDI
AD7
TEST23
H10
TEST18
G9
TEST19
E9
TEST25_H
E8
TEST25_L
AB8
TEST21
AF7
TEST20
AE7
TEST24
AE8
TEST22
AC8
TEST12
AF8
TEST27
C2
TEST9
AA6
TEST6
A3
RSVD1
A5
RSVD2
B3
RSVD3
B5
RSVD4
C1
RSVD5
FOX_PZ6382A-284S-41F_GRIFFIN
CONN@
12
+1.8V
R37220_0402_5%@
THERMTRIP_L
PROCHOT_L
VDDIO_FB_H VDDIO_FB_L
VDDNB_FB_H VDDNB_FB_L
R38220_0402_5%@
R39220_0402_5%@
R40220_0402_5%@
12
12
12
12
2007/08/02 2008/08/02
C
M11
KEY1
W18
KEY2
CPU_SVC
A6
SVC
CPU_SVD
A4
SVD
CPU_THERMTRIP#_R
AF6
CPU_PROCHOT#_1.8
AC7
CPU_MEMHOT#_1.8V
AA8
MEMHOT_L
THERMDC_CPU
W7
THERMDC
THERMDA
DBREQ_L
TEST28_H TEST28_L
TEST17 TEST16 TEST15 TEST14
TEST10
TEST29_H TEST29_L
RSVD10
RSVD9 RSVD8 RSVD7 RSVD6
R41220_0402_5%@
THERMDA_CPU
W8
09/19 update
W9 Y9
VDD_NB_FB_H
H6
VDD_NB_FB_LCPU_VDD1_FB_L
G6
CPU_DBREQ#
E10
CPU_TDO
AE9
TDO
CPU_TEST28_H_PLLCHRZ_P
J7
CPU_TEST28_L_PLLCHRZ_N
H8
CPU_TEST17_BP3
D7
CPU_TEST16_BP2
E7
CPU_TEST15_BP1
F7
CPU_TEST14_BP0
C7 C3
TEST7
K8 C4
TEST8
CPU_TEST29_H_FBCLKOUT_P
C9
CPU_TEST29_L_FBCLKOUT_N
C8
H18 H19 AA7 D5 C5
HDT Connector
JP3
1 3 5 7 9 11 13 15 17 19 21
SAMTEC_ASP-68200-07
@
9/20 SP020016900
Deciphered Date
CPU_SVC <43> CPU_SVD <43>
T42PAD T43PAD
VDD_NB_FB_H <43> VDD_NB_FB_L <43>
2 4 6
8 10 12 14 16 18 20 22 2423 26
D
+1.8V
R17
300_0402_5%@
1 2
R10 10K_0402_5%
1 2
R5 300_0402_5%
CPU_THERMTRIP#_R
12
+1.8V
09/11 update
B
2
Q3
E
3 1
+1.8V
C
R11 10K_0402_5%@
1 2
R9 300_0402_5%
CPU_PROCHOT#_1.8
MMBT3904_NL_SOT23-3
+1.8V sense no support
route as differential
T5PAD
as short as possible
T6PAD
testpoint under package
T7PAD T8PAD T10PAD T12PAD
T13PAD T14PAD
CPU_TEST27_SINGLECHAIN
CPU_TEST21_SCANEN CPU_TEST20_SCANCLK2 CPU_TEST24_SCANCLK1 CPU_TEST22_SCANSHIFTEN CPU_TEST12_SCANSHIFTENB CPU_TEST15_BP1 CPU_TEST14_BP0 CPU_TEST19_PLLTEST0 CPU_TEST18_PLLTEST1
+3VS
5
HDT_RST#
D
U1
4
Y
LDT_RST#
2
P
B
1
A
G
NC7SZ08P5X_NL_SC70-5@
3
Title
Size Document Number Rev
Custom
Date: Sheet
E
MMBT3904_NL_SOT23-3@
CPU_SVC CPU_SVD
E
3 1
11/13 update
ENTRIP2 <37,39> H_THERMTRIP#_EC <33> H_THERMTRIP# <20>
B
2
Q2
C
R22 1K_0402_5%
1 2 1 2
R23 1K_0402_5%
H_PROCHOT# <19>
R6 0_0402_5%@
1 2 1 2
R16 0_0402_5%
1 2
R7 0_0402_5%
12
0718 AMD --> 1K ohm
VDD_NB_FB_H VDD_NB_FB_L
R484 10_0402_5%
1 2 1 2
R485 10_0402_5%
Close to CPU
R24 300_0402_5%@
1 2
09/11 update
R26 300_0402_5%@
1 2
R27 300_0402_5%@ R28 300_0402_5%@ R29 300_0402_5%@ R31 300_0402_5%@ R32 300_0402_5%@ R33 300_0402_5%@ R34 300_0402_5%@ R35 300_0402_5%@
SB_PWRGD <20,33,43>
12 12 12 12 12 12 12 12
Compal Electronics, Inc.
AMD CPU S1G2 CTRL
LA-4111P
647Thursday, No vember 15, 2007
E
+1.8V
+CPU_CORE_NB
+1.8V
0.2
of
A
hexainf@hotmail.com
B
C
D
E
18A/720mil/36vias
VDD(+CPU_CORE) decoupling.
+CPU_CORE_0
1
+
1 1
C30 330U_X_2VM_R6M
2
1
+
C28 330U_X_2VM_R6M
2
Near CPU Socket
+CPU_CORE_0
1
C32 22U_0805_6.3V6M
2
+CPU_CORE_0
1
C40
0.22U_0603_16V4Z
2
2 2
1
C33 22U_0805_6.3V6M
2
1
C41
0.01U_0402_25V4Z
2
1
C34 22U_0805_6.3V6M
2
1
2
C42 180P_0402_50V8J
1
C35 22U_0805_6.3V6M
2
Under CPU Socket
+CPU_CORE_1
+CPU_CORE_1
1
C36 22U_0805_6.3V6M
2
1
+
C31 330U_X_2VM_R6M
2
+CPU_CORE_1
1
C37 22U_0805_6.3V6M
2
1
C43
0.22U_0603_16V4Z
2
1
+
C29 330U_X_2VM_R6M
2
1
C38 22U_0805_6.3V6M
2
1
C44
0.01U_0402_25V4Z
2
1
C39 22U_0805_6.3V6M
2
1
C45 180P_0402_50V8J
2
L
?A/?mil/?vias
L
L
+CPU_CORE_NB
+1.8V
?A/?mil/?vias
JCPUE
G4
VDD0_1
H2
VDD0_2
J9
VDD0_3
J11
VDD0_4
J13
VDD0_5
J15
VDD0_6
K6
VDD0_7
K10
VDD0_8
K12
VDD0_9
K14
VDD0_10
L4
VDD0_11
L7
VDD0_12
L9
VDD0_13
L11
VDD0_14
L13
VDD0_15
L15
VDD0_16
M2
VDD0_17
M6
VDD0_18
M8
VDD0_19
M10
VDD0_20
N7
VDD0_21
N9
VDD0_22
N11
VDD0_23
K16
VDDNB_1
M16
VDDNB_2
P16
VDDNB_3
T16
VDDNB_4
V16
VDDNB_5
H25
VDDIO1
J17
VDDIO2
K18
VDDIO3
K21
VDDIO4
K23
VDDIO5
K25
VDDIO6
L17
VDDIO7
M18
VDDIO8
M21
VDDIO9
M23
VDDIO10
M25
VDDIO11
N17
VDDIO12
FOX_PZ6382A-284S-41F_GRIFFIN
Athlon 64 S1 Processor Socket
CONN@
VDD1_1 VDD1_2 VDD1_3 VDD1_4 VDD1_5 VDD1_6 VDD1_7 VDD1_8
VDD1_9 VDD1_10 VDD1_11 VDD1_12 VDD1_13 VDD1_14 VDD1_15 VDD1_16 VDD1_17 VDD1_18 VDD1_19 VDD1_20 VDD1_21 VDD1_22 VDD1_23 VDD1_24 VDD1_25 VDD1_26
VDDIO27 VDDIO26 VDDIO25 VDDIO24 VDDIO23 VDDIO22 VDDIO21 VDDIO20 VDDIO19 VDDIO18 VDDIO17 VDDIO16 VDDIO15 VDDIO14 VDDIO13
18A/720mil/36vias
L
+CPU_CORE_1+CPU_CORE_0
P8 P10 R4 R7 R9 R11 T2 T6 T8 T10 T12 T14 U7 U9 U11 U13 U15 V6 V8 V10 V12 V14 W4 Y2 AC4 AD2
Y25 V25 V23 V21 V18 U17 T25 T23 T21 T18 R17 P25 P23 P21 P18
+1.8V
+CPU_CORE_NB decoupling.
VDDIO decoupling.
+1.8V
1
C46 22U_0805_6.3V6M
2
3 3
+1.8V
1
C55
0.22U_0603_16V4Z
2
+1.8V +1.8V
1
C60
0.01U_0402_25V4Z
2
4 4
+1.8V
1
C74
4.7U_0805_10V4Z
2
1
C47 22U_0805_6.3V6M
2
Under CPU Socket
Between CPU Socket and DIMM
1
C56
0.22U_0603_16V4Z
2
1
C61
0.01U_0402_25V4Z
2
1
C75
4.7U_0805_10V4Z
2
A
1
C48
0.22U_0603_16V4Z
2
1
C57
0.22U_0603_16V4Z
2
1
2
1
2
1
C49
0.22U_0603_16V4Z
2
1
2
180PF Qt'y follow the distance between CPU socket and DIMM0. <2.5inch>
C62 180P_0402_50V8J
C76
4.7U_0805_10V4Z
1
2
1
C50
180P_0402_50V8J
2
C58
0.22U_0603_16V4Z
1
C63 180P_0402_50V8J
2
A: Add C165 and C176 to follow AMD Layout review recommand for EMI
C77
4.7U_0805_10V4Z
1
2
1
C64 180P_0402_50V8J
2
1
C: Change to NBO CAP
+
C78 220U_Y_4VM
@
2
B
C51 180P_0402_50V8J
1
C65 180P_0402_50V8J
2
+CPU_CORE_NB
1
C52 22U_0805_6.3V6M
2
VTT decoupling.
+0.9V
1
C66
4.7U_0805_10V4Z
2
+0.9V
1
C79
4.7U_0805_10V4Z
2
Security Classification
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Near CPU Socket Right side.
Near CPU Socket Left side.
Issued Date
1
C67
4.7U_0805_10V4Z
2
1
C80
4.7U_0805_10V4Z
2
C
1
C53 22U_0805_6.3V6M
2
2007/08/02 2008/08/02
1
2
1
C68
0.22U_0603_16V4Z
2
1
C81
0.22U_0603_16V4Z
2
C54 22U_0805_6.3V6M
+0.9V
Near Power Supply
1
C: Change to NBO CAP
+
C59 220U_Y_4VM
2
1
C69
0.22U_0603_16V4Z
2
1
C82
0.22U_0603_16V4Z
2
Deciphered Date
1
C70 1000P_0402_25V8J
2
1
C83 1000P_0402_25V8J
2
D
1
C71 1000P_0402_25V8J
2
1
C84 1000P_0402_25V8J
2
1
C72 180P_0402_50V8J
2
1
C85 180P_0402_50V8J
2
Title
Size Document Number Rev
Custom
Date: Sheet
JCPUF
AA4
VSS1
AA11
VSS2
AA13
VSS3
AA15
VSS4
AA17
VSS5
AA19
VSS6
AB2
VSS7
AB7
VSS8
AB9
VSS9
AB23
VSS10
AB25
VSS11
AC11
VSS12
AC13
VSS13
AC15
VSS14
AC17
VSS15
AC19
VSS16
AC21
VSS17
AD6
VSS18
AD8
VSS19
AD25
VSS20
AE11
VSS21
AE13
VSS22
AE15
VSS23
AE17
VSS24
AE19
VSS25
AE21
VSS26
AE23
VSS27
B4
VSS28
B6
VSS29
B8
VSS30
B9
VSS31
B11
VSS32
B13
VSS33
B15
VSS34
B17
VSS35
B19
VSS36
B21
VSS37
B23
VSS38
B25
VSS39
D6
VSS40
D8
VSS41
D9
VSS42
D11
VSS43
D13
VSS44
D15
VSS45
D17
VSS46
D19
VSS47
D21
VSS48
D23
VSS49
D25
VSS50
E4
VSS51
F2
VSS52
F11
VSS53
F13
VSS54
F15
VSS55
F17
VSS56
F19
VSS57
F21
VSS58
F23
VSS59
F25
VSS60
H7
VSS61
H9
VSS62
H21
VSS63
H23
VSS64
J4
VSS65
FOX_PZ6382A-284S-41F_GRIFFIN
Athlon 64 S1 Processor Socket
CONN@
1
C73 180P_0402_50V8J
2
1
C86 180P_0402_50V8J
2
VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98
VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129
J6 J8 J10 J12 J14 J16 J18 K2 K7 K9 K11 K13 K15 K17 L6 L8 L10 L12 L14 L16 L18 M7 M9 AC6 M17 N4 N8 N10 N16 N18 P2 P7 P9 P11 P17 R8 R10 R16 R18 T7 T9 T11 T13 T15 T17 U4 U6 U8 U10 U12 U14 U16 U18 V2 V7 V9 V11 V13 V15 V17 W6 Y21 Y23 N6
Compal Electronics, Inc.
AMD CPU S1G2 PWR & GND
LA-4111P
747Thursday, No vember 15, 2007
E
of
0.2
A
DDR_A_D0 DDR_A_D1
1 1
2 2
DDR_CKE0_DIMMA<5>
DDR_A_BS#2<5>
DDR_A_BS#0<5> DDR_A_WE#<5>
DDR_A_CAS#<5> DDR_CS1_DIMMA#<5>
DDR_A_ODT1<5>
3 3
SMB_CK_DAT0<9,15,20,30> SMB_CK_CLK0<9,15,20,30>
4 4
A
+3VS
DDR_A_DQS#0 DDR_A_DQS0
DDR_A_D2 DDR_A_D3
DDR_A_D8 DDR_A_D9
DDR_A_DQS#1 DDR_A_DQS1
DDR_A_D10 DDR_A_D11
DDR_A_D16 DDR_A_D20 DDR_A_D17
DDR_A_DQS#2 DDR_A_DQS2
DDR_A_D18 DDR_A_D19
DDR_A_D24 DDR_A_D25
DDR_A_DM3
DDR_A_D26 DDR_A_D27
DDR_CKE0_DIMMA
DDR_A_BS#2 DDR_A_MA12
DDR_A_MA9 DDR_A_MA8
DDR_A_MA5 DDR_A_MA3 DDR_A_MA1 DDR_A_MA0
DDR_A_MA10 DDR_A_BS#0 DDR_A_WE#
DDR_A_CAS# DDR_A_ODT0 DDR_CS1_DIMMA#
DDR_A_ODT1 DDR_A_D32
DDR_A_D33 DDR_A_DQS#4
DDR_A_DQS4 DDR_A_D34
DDR_A_D35 DDR_A_D40
DDR_A_D41 DDR_A_DM5 DDR_A_D42
DDR_A_D43 DDR_A_D48
DDR_A_D49
DDR_A_DQS#6 DDR_A_DQS6
DDR_A_D50 DDR_A_D51
DDR_A_D56 DDR_A_D57
DDR_A_DM7 DDR_A_D58
DDR_A_D59
1
C103
0.1U_0402_16V4Z
2
B
+V_DDR_MCH_REF
JP4
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
FOX_AS0A426-N8RN-7F
CONN@
9/20 SP07000BZ00/SP07000EU00 DDR2 SOCKET H9.2 (REV)
B
DQ12 DQ13
CK0#
DQ14 DQ15
DQ20 DQ21
DQ22 DQ23
DQ28 DQ29
DQS3#
DQS3 DQ30
DQ31
NC/CKE1
NC/A15 NC/A14
RAS#
ODT0
NC/A13
DQ36 DQ37
DQ38 DQ39
DQ44 DQ45
DQS5#
DQS5 DQ46
DQ47 DQ52
DQ53
CK1#
DQ54 DQ55
DQ60 DQ61
DQS7#
DQS7 DQ62
DQ63
VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS
VSS DM1 VSS CK0
VSS
VSS
VSS
VSS DM2
VSS
VSS
VSS
VSS
VSS VDD
VDD
VDD
VDD BA1
VDD
VDD VSS
VSS DM4 VSS
VSS
VSS
VSS
VSS
VSS CK1
VSS DM6 VSS
VSS
VSS
VSS
VSS SA0 SA1
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
42 44 46 48 50
NC
52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90
A11
92
A7
94
A6
96 98
A4
100
A2
102
A0
104 106 108 110
S0#
112 114 116 118 120
NC
122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200
+1.8V+1.8V
C
DDR_A_D4 DDR_A_D5
DDR_A_DM0 DDR_A_D6
DDR_A_D7 DDR_A_D12
DDR_A_D13 DDR_A_DM1
DDR_A_D14 DDR_A_D15
DDR_A_D21
DDR_A_DM2 DDR_A_D22
DDR_A_D23 DDR_A_D28
DDR_A_D29 DDR_A_DQS#3
DDR_A_DQS3 DDR_A_D30
DDR_A_D31 DDR_CKE1_DIMMA DDR_A_MA15
DDR_A_MA14 DDR_A_MA11
DDR_A_MA7 DDR_A_MA6
DDR_A_MA4 DDR_A_MA2
DDR_A_BS#1 DDR_A_RAS# DDR_CS0_DIMMA#
DDR_A_MA13
DDR_A_D36 DDR_A_D37
DDR_A_DM4 DDR_A_D38
DDR_A_D39 DDR_A_D44
DDR_A_D45 DDR_A_DQS#5
DDR_A_DQS5 DDR_A_D46
DDR_A_D47 DDR_A_D52
DDR_A_D53
DDR_A_DM6 DDR_A_D54
DDR_A_D55 DDR_A_D60
DDR_A_D61 DDR_A_DQS#7
DDR_A_DQS7 DDR_A_D62
DDR_A_D63
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DDR_A_D[0..63]
DDR_A_DM[0..7]
DDR_A_DQS[0..7]
DDR_A_MA[0..15]
DDR_A_DQS#[0..7]
DDR_A_CLK0 <5> DDR_A_CLK#0 <5>
+V_DDR_MCH_REF
1
C95
2
1000P_0402_25V8J
0.1U_0402_16V4Z
DDR_CKE1_DIMMA <5>
DDR_A_BS#1 <5> DDR_A_RAS# <5> DDR_CS0_DIMMA# <5>
DDR_A_ODT0 <5>
DDR_A_CLK1 <5> DDR_A_CLK#1 <5>
C
DDR_A_D[0..63] <5> DDR_A_DM[0..7] <5>
DDR_A_DQS[0..7] <5>
DDR_A_MA[0..15] <5>
DDR_A_DQS#[0..7] <5>
+1.8V
R43 1K_0402_1%
1 2
R44 1K_0402_1%
1 2
+V_DDR_MCH_REF <9>
1
C96
2
09/13 update
2007/08/02 2008/08/02
Deciphered Date
D
+0.9V
DDR_A_MA14 DDR_A_MA11 DDR_A_MA7 DDR_A_MA6
DDR_CKE0_DIMMA DDR_A_BS#2 DDR_CKE1_DIMMA DDR_A_MA15
DDR_A_MA4 DDR_A_MA2 DDR_A_BS#1 DDR_A_MA0
DDR_A_MA5 DDR_A_MA8 DDR_A_MA9 DDR_A_MA12
DDR_A_BS#0 DDR_A_MA10 DDR_A_MA1 DDR_A_MA3
DDR_A_ODT1 DDR_CS1_DIMMA# DDR_A_WE# DDR_A_CAS#
DDR_CS0_DIMMA# DDR_A_RAS# DDR_A_MA13 DDR_A_ODT0
D
RP1
18 27 36
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
Cross between +1.8V and +0.9V power plan
Title
Size Document Number Rev
Custom
Date: Sheet
45
RP2
18 27 36 45
RP3
18 27 36 45
RP4
18 27 36 45
RP5
18 27 36 45
RP6
18 27 36 45
RP7
18 27 36 45
Compal Electronics, Inc.
DDRII SO-DIMM 0
LA-4111P
E
1 2
C87 0.1U_0402_16V4Z
1 2
C88 0.1U_0402_16V4Z
1 2
C90 0.1U_0402_16V4Z
1 2
C89 0.1U_0402_16V4Z
1 2
C91 0.1U_0402_16V4Z
1 2
C92 0.1U_0402_16V4Z
1 2
C93 0.1U_0402_16V4Z
1 2
C94 0.1U_0402_16V4Z
1 2
C98 0.1U_0402_16V4Z
1 2
C97 0.1U_0402_16V4Z
1 2
C100 0.1U_0402_16V4Z
1 2
C99 0.1U_0402_16V4Z
1 2
C102 0.1U_0402_16V4Z
1 2
C101 0.1U_0402_16V4Z
E
+1.8V
0.2
of
847Thursday, No vember 15, 2007
A
hexainf@hotmail.com
B
C
D
E
JP5
+V_DDR_MCH_REF<8>
1
C104
1 1
2 2
3 3
4 4
1000P_0402_25V8J
DDR_CKE0_DIMMB<5>
DDR_B_BS#2<5>
DDR_B_BS#0<5> DDR_B_WE#<5>
DDR_B_CAS#<5> DDR_CS1_DIMMB#<5>
DDR_B_ODT1<5>
SMB_CK_DAT0<8,15,20,30> SMB_CK_CLK0<8,15,20,30>
2
DDR_B_D0 DDR_B_D1
DDR_B_DQS#0 DDR_B_DQS0
DDR_B_D2 DDR_B_D3
DDR_B_D8 DDR_B_D13
DDR_B_DQS#1 DDR_B_DQS1
DDR_B_D10 DDR_B_D11
DDR_B_D21 DDR_B_D17
DDR_B_DQS#2 DDR_B_DQS2
DDR_B_D18 DDR_B_D22 DDR_B_D19
DDR_B_D24 DDR_B_D25
DDR_B_DM3
DDR_B_D26 DDR_B_D27
DDR_CKE0_DIMMB
DDR_B_BS#2 DDR_B_MA12
DDR_B_MA9
DDR_B_MA5 DDR_B_MA3 DDR_B_MA1
DDR_B_MA10 DDR_B_BS#0 DDR_B_WE#
DDR_B_CAS# DDR_B_ODT0 DDR_CS1_DIMMB#
DDR_B_ODT1 DDR_B_D32
DDR_B_D33 DDR_B_DQS#4
DDR_B_DQS4 DDR_B_D34
DDR_B_D35 DDR_B_D40
DDR_B_D41 DDR_B_DM5 DDR_B_D42
DDR_B_D43 DDR_B_D47 DDR_B_D48
DDR_B_D49 DDR_B_D53
DDR_B_DQS#6 DDR_B_DQS6
DDR_B_D50 DDR_B_D51 DDR_B_D55
DDR_B_D56 DDR_B_D57
DDR_B_DM7 DDR_B_D58
DDR_B_D59
+3VS
0.1U_0402_16V4Z
C119
1
2
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VSS
11
DQS0#
13
DQS0
15
VSS
17
DQ2
19
DQ3
21
VSS
23
DQ8
25
DQ9
27
VSS
29
DQS1#
31
DQS1
33
VSS
35
DQ10
37
DQ11
39
VSS
41
VSS
43
DQ16
45
DQ17
47
VSS
49
DQS2#
51
DQS2
53
VSS
55
DQ18
57
DQ19
59
VSS
61
DQ24
63
DQ25
65
VSS
67
DM3
69
NC
71
VSS
73
DQ26
75
DQ27
77
VSS
79
CKE0
81
VDD
83
NC
85
BA2
87
VDD
89
A12
91
A9
93
A8
95
VDD
97
A5
99
A3
101
A1
103
VDD
105
A10/AP
107
BA0
109
WE#
111
VDD
113
CAS#
115
NC/S1#
117
VDD
119
NC/ODT1
121
VSS
123
DQ32
125
DQ33
127
VSS
129
DQS4#
131
DQS4
133
VSS
135
DQ34
137
DQ35
139
VSS
141
DQ40
143
DQ41
145
VSS
147
DM5
149
VSS
151
DQ42
153
DQ43
155
VSS
157
DQ48
159
DQ49
161
VSS
163
NC,TEST
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SDA
197
SCL
199
VDDSPD
201
GND
TYCO_292527-4
CONN@
VSS DQ4 DQ5
VSS DM0 VSS DQ6 DQ7 VSS
DQ12 DQ13
VSS DM1 VSS
CK0
CK0#
VSS
DQ14 DQ15
VSS
VSS
DQ20 DQ21
VSS DM2
VSS
DQ22 DQ23
VSS
DQ28 DQ29
VSS
DQS3#
DQS3
VSS
DQ30 DQ31
VSS
NC/CKE1
VDD
NC/A15 NC/A14
VDD
A11
VDD
VDD
BA1
RAS#
S0# VDD
ODT0
NC/A13
VDD VSS
DQ36 DQ37
VSS DM4 VSS
DQ38 DQ39
VSS
DQ44 DQ45
VSS
DQS5#
DQS5
VSS
DQ46 DQ47
VSS
DQ52 DQ53
VSS
CK1
CK1#
VSS DM6 VSS
DQ54 DQ55
VSS
DQ60 DQ61
VSS
DQS7#
DQS7
VSS
DQ62 DQ63
VSS SAO
SA1 GND
NC
A7 A6
A4 A2 A0
NC
9/20 SP07000ET00/SP07000GN00
+1.8V+1.8V
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202
DDR_B_D4 DDR_B_D5
DDR_B_DM0 DDR_B_D6
DDR_B_D7 DDR_B_D12
DDR_B_D9 DDR_B_DM1
DDR_B_D14 DDR_B_D15
DDR_B_D20 DDR_B_D16
DDR_B_DM2
DDR_B_D23 DDR_B_D28
DDR_B_D29 DDR_B_DQS#3
DDR_B_DQS3 DDR_B_D30
DDR_B_D31 DDR_CKE1_DIMMB DDR_B_MA15
DDR_B_MA14 DDR_B_MA11
DDR_B_MA7 DDR_B_MA6DDR_B_MA8
DDR_B_MA4 DDR_B_MA2 DDR_B_MA0
DDR_B_BS#1 DDR_B_RAS# DDR_CS0_DIMMB#
DDR_B_MA13
DDR_B_D36 DDR_B_D37
DDR_B_DM4 DDR_B_D38
DDR_B_D39 DDR_B_D44
DDR_B_D45 DDR_B_DQS#5
DDR_B_DQS5 DDR_B_D46
DDR_B_D52
DDR_B_DM6 DDR_B_D54
DDR_B_D60 DDR_B_D61
DDR_B_DQS#7 DDR_B_DQS7
DDR_B_D62 DDR_B_D63
+3VS
DDR_B_D[0..63]
DDR_B_DM[0..7]
DDR_B_DQS[0..7]
DDR_B_MA[0..15]
DDR_B_DQS#[0..7]
DDR_B_CLK0 <5> DDR_B_CLK#0 <5>
DDR_CKE1_DIMMB <5>
DDR_B_BS#1 <5> DDR_B_RAS# <5> DDR_CS0_DIMMB# <5>
DDR_B_ODT0 <5>
DDR_B_CLK1 <5> DDR_B_CLK#1 <5>
DDR_B_D[0..63] <5>
DDR_B_DM[0..7] <5>
DDR_B_DQS[0..7] <5>
DDR_B_MA[0..15] <5>
DDR_B_DQS#[0..7] <5>
DDR_B_MA6 DDR_B_MA2 DDR_B_MA0 DDR_CS0_DIMMB#
DDR_B_MA14 DDR_B_MA11 DDR_B_MA7 DDR_B_MA4
DDR_B_BS#2 DDR_CKE0_DIMMB DDR_B_MA15 DDR_CKE1_DIMMB
DDR_B_MA5 DDR_B_MA8 DDR_B_MA9 DDR_B_MA12
DDR_B_MA10 DDR_B_BS#0 DDR_B_MA1 DDR_B_MA3
DDR_B_ODT1 DDR_CS1_DIMMB# DDR_B_CAS# DDR_B_WE#
DDR_B_RAS# DDR_B_BS#1 DDR_B_ODT0 DDR_B_MA13
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
47_0804_8P4R_5%
Cross between +1.8V and +0.9V power plan
09/26 update DDR_B_D21 swap with DDR_B_D16
DDR_B_D13 swap with DDR_B_D9
RP8
RP9
RP10
RP11
RP12
RP13
RP14
+0.9V
18
C105 0.1U_0402_16V4Z
27
1 2
36
C106 0.1U_0402_16V4Z
45
18
C108 0.1U_0402_16V4Z
27 36
1 2
C107 0.1U_0402_16V4Z
45
18
C109 0.1U_0402_16V4Z
27 36
1 2
C110 0.1U_0402_16V4Z
45
18
C111 0.1U_0402_16V4Z
27 36
1 2
C112 0.1U_0402_16V4Z
45
18
C114 0.1U_0402_16V4Z
27
1 2
36
C113 0.1U_0402_16V4Z
45
18
C116 0.1U_0402_16V4Z
27 36
1 2
C115 0.1U_0402_16V4Z
45
18
C118 0.1U_0402_16V4Z
27 36
1 2
C117 0.1U_0402_16V4Z
45
12
12
12
12
12
12
12
+1.8V
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2007/08/02 2008/08/02
Deciphered Date
Title
Size Document Number Rev
Custom
D
Date: Sheet
Compal Electronics, Inc.
DDRII SO-DIMM 1
LA-4111P
947Thursday, No vember 15, 2007
E
0.2
of
A
U3B
D4
GFX_RX0P
C4
GFX_RX0N
A3
GFX_RX1P
B3
GFX_RX1N
C2
GFX_RX2P
C1
GFX_RX2N
E5
GFX_RX3P
F5
GFX_RX3N
G5
GFX_RX4P
G6
AE3 AD4 AE2 AD3 AD1 AD2
W6
AA8 AA7 AA5
AA6
W5
H5 H6
J6 J5 J7 J8 L5 L6
M8
L8 P7
M7
P5 M5 R8
P8 R6 R5
P4
P3
T4
T3
V5 U5
U6 U8 U7
Y8
Y7
Y5
GFX_RX4N GFX_RX5P GFX_RX5N GFX_RX6P GFX_RX6N GFX_RX7P GFX_RX7N GFX_RX8P GFX_RX8N GFX_RX9P GFX_RX9N GFX_RX10P GFX_RX10N GFX_RX11P GFX_RX11N GFX_RX12P GFX_RX12N GFX_RX13P GFX_RX13N GFX_RX14P GFX_RX14N GFX_RX15P GFX_RX15N
GPP_RX0P GPP_RX0N GPP_RX1P GPP_RX1N GPP_RX2P GPP_RX2N GPP_RX3P GPP_RX3N GPP_RX4P GPP_RX4N GPP_RX5P GPP_RX5N
SB_RX0P SB_RX0N SB_RX1P SB_RX1N SB_RX2P SB_RX2N SB_RX3P SB_RX3N
1 1
PCIE_PTX_C_IRX_P0<26> PCIE_PTX_C_IRX_N0<26> PCIE_PTX_C_IRX_P1<27> PCIE_PTX_C_IRX_N1<27> PCIE_PTX_C_IRX_P2<26> PCIE_PTX_C_IRX_N2<26> PCIE_PTX_C_IRX_P3<25>
2 2
PCIE_PTX_C_IRX_N3<25>
PCIE_PTX_C_IRX_P5<26> PCIE_PTX_C_IRX_N5<26>
SB_RX0P<19> SB_RX0N<19> SB_RX1P<19> SB_RX1N<19> SB_RX2P<19> SB_RX2N<19> SB_RX3P<19> SB_RX3N<19>
RS780M_FCBGA528
PART 2 OF 6
PCIE I/F GFX
PCIE I/F GPP
PCIE I/F SB
PCE_CALRP(PCE_BCALRP)
PCE_CALRN(PCE_BCALRN)
RS780M Display Port Support (muxed on GFX)
DP0
DP1
3 3
9/20 SA00001ZG00(A11) S IC 216-0674001-00/RS780M FCBGA528P 0FH
GFX_TX0,TX1,TX2 and TX3 AUX0 and HPD0
GFX_TX4,TX5,TX6 and TX7 AUX1 and HPD1
UMA@
B
GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N
GPP_TX0P GPP_TX0N GPP_TX1P GPP_TX1N GPP_TX2P GPP_TX2N GPP_TX3P GPP_TX3N GPP_TX4P GPP_TX4N GPP_TX5P GPP_TX5N
SB_TX0P SB_TX0N SB_TX1P SB_TX1N SB_TX2P SB_TX2N SB_TX3P SB_TX3N
A5 B5 A4 B4 C3 B2 D1 D2 E2 E1 F4 F3 F1 F2 H4 H3 H1 H2 J2 J1 K4 K3 K1 K2 M4 M3 M1 M2 N2 N1 P1 P2
PCIE_ITX_PRX_P0
AC1
PCIE_ITX_PRX_N0
AC2
PCIE_ITX_PRX_P1
AB4
PCIE_ITX_PRX_N1
AB3
PCIE_ITX_PRX_P2
AA2
PCIE_ITX_PRX_N2
AA1
PCIE_ITX_PRX_P3
Y1
PCIE_ITX_PRX_N3
Y2 Y4 Y3
PCIE_ITX_PRX_P5
V1
PCIE_ITX_PRX_N5
V2
SB_TX0P_C
AD7
SB_TX0N_C
AE7
SB_TX1P_C
AE6
SB_TX1N_C
AD6
SB_TX2P_C
AB6
SB_TX2N_C
AC6
SB_TX3P_C
AD5
SB_TX3N_C
AE5 AC8
AB8
TMDS_B_DATA2 <18> TMDS_B_DATA2# <18> TMDS_B_DATA1 <18> TMDS_B_DATA1# <18> TMDS_B_DATA0 <18> TMDS_B_DATA0# <18> TMDS_B_CLK <18> TMDS_B_CLK# <18>
C152 0.1U_0402_16V7K C153 0.1U_0402_16V7K C154 0.1U_0402_16V7K C155 0.1U_0402_16V7K C156 0.1U_0402_16V7K C157 0.1U_0402_16V7K C158 0.1U_0402_16V7K C159 0.1U_0402_16V7K
C160 0.1U_0402_16V7K C161 0.1U_0402_16V7K
C162 0.1U_0402_16V7K C163 0.1U_0402_16V7K C164 0.1U_0402_16V7K C165 0.1U_0402_16V7K C166 0.1U_0402_16V7K C168 0.1U_0402_16V7K C169 0.1U_0402_16V7K C167 0.1U_0402_16V7K
R55 1.27K_0402_1%
1 2
R56 2K_0402_1%
1 2
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
+1.1VS
C
PCIE_ITX_C_PRX_P0 <26> PCIE_ITX_C_PRX_N0 <26> PCIE_ITX_C_PRX_P1 <27> PCIE_ITX_C_PRX_N1 <27> PCIE_ITX_C_PRX_P2 <26> PCIE_ITX_C_PRX_N2 <26> PCIE_ITX_C_PRX_P3 <25> PCIE_ITX_C_PRX_N3 <25>
PCIE_ITX_C_PRX_P5 <26> PCIE_ITX_C_PRX_N5 <26>
SB_TX0P <19> SB_TX0N <19> SB_TX1P <19> SB_TX1N <19> SB_TX2P <19> SB_TX2N <19> SB_TX3P <19> SB_TX3N <19>
New Card CardReader
WLAN LAN10/100
TV Tuner
H_CLKOP0<4> H_CLKON0<4> H_CLKOP1<4> H_CLKON1<4>
H_CTLOP0<4> H_CTLON0<4>
H_CTLON1<4>
0718 Place within 1" layout 1:2
H_CADOP[0..15]<4> H_CADON[0..15]<4> H_CADIN[0..15] <4>
H_CADOP10 H_CADON10 H_CADOP11 H_CADON11 H_CADOP12 H_CADON12 H_CADOP13 H_CADON13 H_CADOP14 H_CADON14 H_CADOP15 H_CADON15
H_CTLOP0 H_CTLON0 H_CTLOP1 H_CTLON1
R57 301_0402_1%
1 2
H_CADOP0 H_CADON0 H_CADOP1 H_CADON1 H_CADOP2 H_CADON2 H_CADOP3 H_CADON3 H_CADOP4 H_CADON4 H_CADOP5 H_CADON5 H_CADOP6 H_CADON6 H_CADOP7 H_CADON7
H_CADOP8 H_CADON8 H_CADOP9 H_CADON9
D
Y25 Y24 V22 V23 V25 V24 U24 U25 T25 T24 P22 P23 P25 P24 N24 N25
AC24 AC25 AB25 AB24 AA24 AA25
Y22
Y23 W21 W20
V21
V20
U20
U21
U19
U18
T22
T23
AB23 AA22
M22 M23
R21
R20
C23
A24
H_CADON[0..15]
U3A
HT_RXCAD0P HT_RXCAD0N HT_RXCAD1P HT_RXCAD1N HT_RXCAD2P HT_RXCAD2N HT_RXCAD3P HT_RXCAD3N HT_RXCAD4P HT_RXCAD4N HT_RXCAD5P HT_RXCAD5N HT_RXCAD6P HT_RXCAD6N HT_RXCAD7P HT_RXCAD7N
HT_RXCAD8P HT_RXCAD8N HT_RXCAD9P HT_RXCAD9N HT_RXCAD10P HT_RXCAD10N HT_RXCAD11P HT_RXCAD11N HT_RXCAD12P HT_RXCAD12N HT_RXCAD13P HT_RXCAD13N HT_RXCAD14P HT_RXCAD14N HT_RXCAD15P HT_RXCAD15N
HT_RXCLK0P HT_RXCLK0N HT_RXCLK1P HT_RXCLK1N
HT_RXCTL0P HT_RXCTL0N HT_RXCTL1P HT_RXCTL1N
HT_RXCALP HT_RXCALN
RS780M_FCBGA528
UMA@
PART 1 OF 6
HYPER TRANSPORT CPU I/F
H_CADIP[0..15]H_CADOP[0..15] H_CADIN[0..15]
HT_TXCAD0P HT_TXCAD0N HT_TXCAD1P HT_TXCAD1N HT_TXCAD2P HT_TXCAD2N HT_TXCAD3P HT_TXCAD3N HT_TXCAD4P HT_TXCAD4N HT_TXCAD5P HT_TXCAD5N HT_TXCAD6P HT_TXCAD6N HT_TXCAD7P HT_TXCAD7N
HT_TXCAD8P HT_TXCAD8N HT_TXCAD9P
HT_TXCAD9N HT_TXCAD10P HT_TXCAD10N HT_TXCAD11P HT_TXCAD11N HT_TXCAD12P HT_TXCAD12N HT_TXCAD13P HT_TXCAD13N HT_TXCAD14P HT_TXCAD14N HT_TXCAD15P HT_TXCAD15N
HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N
HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N
HT_TXCALP HT_TXCALN
E
H_CADIP[0..15] <4>
H_CADIP0
D24
H_CADIN0
D25
H_CADIP1
E24
H_CADIN1
E25
H_CADIP2
F24
H_CADIN2
F25
H_CADIP3
F23
H_CADIN3
F22
H_CADIP4
H23
H_CADIN4
H22
H_CADIP5
J25
H_CADIN5
J24
H_CADIP6
K24
H_CADIN6
K25
H_CADIP7
K23
H_CADIN7
K22
H_CADIP8
F21
H_CADIN8
G21
H_CADIP9
G20
H_CADIN9
H21
H_CADIP10
J20
H_CADIN10
J21
H_CADIP11
J18
H_CADIN11
K17
H_CADIP12
L19
H_CADIN12
J19
H_CADIP13
M19
H_CADIN13
L18
H_CADIP14
M21
H_CADIN14
P21
H_CADIP15
P18
H_CADIN15
M18 H24
H25 L21 L20
H_CTLIP0
M24
H_CTLIN0
M25
H_CTLIP1
P19
H_CTLIN1
R18 B24
B25
0718 Place within 1" layout 1:2
H_CLKIP0 <4> H_CLKIN0 <4> H_CLKIP1 <4> H_CLKIN1 <4>
H_CTLIP0 <4>
H_CTLIN0 <4>
H_CTLIP1 <4>H_CTLOP1<4>
H_CTLIN1 <4>
R58 301_0402_1%
1 2
NEED CHECK R68 & R69 WITH AMD
4 4
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2007/08/02 2008/08/02
Deciphered Date
Title
Size Document Number Rev
Custom
D
Date: Sheet
Compal Electronics, Inc.
RS780-HT/PCIE
LA-4111P
10 47Thursday, No vember 15, 2007
E
0.2
of
A
hexainf@hotmail.com
1 1
11/13 update
LDT_STOP#<6,19>
CPU_LDT_REQ#<6,19>
2 2
Install when SB700 A12 use
L
3 3
R67
1 2
0_0402_5%
R68
1 2
0_0402_5%
+1.8VS
BLM18PG121SN1D_0603
+1.8VS
1 2
BLM18PG121SN1D_0603
2.2U_0603_6.3V4Z
+1.1VS
NB_LDTSTOP#
NB_ALLOW_LDTSTOP
+1.1VS
+1.8VS
BLM18PG121SN1D_0603
L10
1 2
L11
1
C180
2
1 2
R71
4.7K_0402_5%
1 2
R62 150_0402_1%
1 2
R63 150_0402_1%
1 2
R64 150_0402_1%
1 2
BLM18PG121SN1D_0603
L7
1 2
C176
2.2U_0603_6.3V4Z
1
C179
2.2U_0603_6.3V4Z
2
11/13 update
1 2
R72
4.7K_0402_5%
+1.8VS
L9
1
2
B
+1.8VS
L6
1 2
BLM18PG121SN1D_0603
2.2U_0603_6.3V4Z
RED
GREEN
BLUE
1
C178
2.2U_0603_6.3V4Z
2
+NB_PLLVDD +NB_HTPVDD
+VDDA18HTPLL +VDDA18PCIEPLL
PLT_RST#<14,19,25,26,27,32,33>
NB_PWRGD<20>
+1.8VS
CLK_NBHT<15> CLK_NBHT#<15>
NB_OSC_14.318M<15>
NBGFX_CLK<15> NBGFX_CLK#<15>
CLK_SBLINK_BCLK<15> CLK_SBLINK_BCLK#<15>
LCD_DDC_CLK<17>
LCD_DDC_DAT<17> HDMIDAT_UMA<18> HDMICLK_UMA<18>
+3VS
1 2
BLM18PG121SN1D_0603
L4
0_0603_5%
+AVDDQ
1
C175
2
T46 PAD T47 PAD T48 PAD
11/05 update
RED<16> GREEN<16> BLUE<16>
CRT_HSYNC<14,16>
CRT_VSYNC<14,16> UMA_CRT_CLK<16> UMA_CRT_DAT<16>
R65 715_0402_1%
R66 0_0402_5%
1 2
1 2
R371 10K_0402_5%
RS780_DFT_GPIO_0<14>
+3VS
L2
+AVDD1
+AVDD2
1
C172
2.2U_0603_6.3V4Z
2
RED GREEN BLUE
1 2
NB_RESET# NB_PWRGD NB_LDTSTOP#
NB_ALLOW_LDTSTOP
Strap pin
R88 10K_0402_5%
AUX_CAL<14>
Strap pin
AVDD=100mA
1
2
TV_CRMA TV_LUMA TV_COMPS
CRT_HSYNC CRT_VSYNC
12
C170
2.2U_0603_6.3V4Z
U3C
F12
AVDD1(NC)
E12
AVDD2(NC)
F14
AVDDDI(NC)
G15
AVSSDI(NC)
H15
AVDDQ(NC)
H14
AVSSQ(NC)
E17
C_Pr(DFT_GPIO5)
F17
Y(DFT_GPIO2)
F15
COMP_Pb(DFT_GPIO4)
G18
RED(DFT_GPIO0)
G17
REDb(NC)
E18
GREEN(DFT_GPIO1)
F18
GREENb(NC)
E19
BLUE(DFT_GPIO3)
F19
BLUEb(NC)
A11
DAC_HSYNC(PWM_GPIO4)
B11
DAC_VSYNC(PWM_GPIO6)
F8
DAC_SCL(PCE_RCALRN)
E8
DAC_SDA(PCE_TCALRN)
G14
DAC_RSET(PWM_GPIO1)
A12
PLLVDD(NC)
D14
PLLVDD18(NC)
B12
PLLVSS(NC)
H17
VDDA18HTPLL
D7
VDDA18PCIEPLL1
E7
VDDA18PCIEPLL2
D8
SYSRESETb
A10
POWERGOOD
C10
LDTSTOPb
C12
ALLOW_LDTSTOP
C25
HT_REFCLKP
C24
HT_REFCLKN
E11
REFCLK_P/OSCIN(OSCIN)
F11
REFCLK_N(PWM_GPIO3)
T2
GFX_REFCLKP
T1
GFX_REFCLKN
U1
GPP_REFCLKP
U2
GPP_REFCLKN
V4
GPPSB_REFCLKP(SB_REFCLKP)
V3
GPPSB_REFCLKN(SB_REFCLKN)
B9
I2C_CLK
A9
I2C_DATA
B8
DDC_DATA0/AUX0N(NC)
A8
DDC_CLK0/AUX0P(NC)
B7
DDC_CLK1/AUX1P(NC)
A7
DDC_DATA1/AUX1N(NC)
B10
STRP_DATA
G11
RSVD
C8
AUX_CAL(NC)
RS780M_FCBGA528
UMA@
C
PART 3 OF 6
TXOUT_U1P(PCIE_RESET_GPIO3)
TXOUT_U1N(PCIE_RESET_GPIO2)
TXOUT_U3P(PCIE_RESET_GPIO5)
CRT/TVOUT
TXCLK_UP(PCIE_RESET_GPIO4)
TXCLK_UN(PCIE_RESET_GPIO1)
LVTM
PM
TXOUT_L0P(NC)
TXOUT_L0N(NC)
TXOUT_L1P(NC)
TXOUT_L1N(NC)
TXOUT_L2P(NC)
TXOUT_L2N(DBG_GPIO0)
TXOUT_L3P(NC)
TXOUT_L3N(DBG_GPIO2)
TXOUT_U0P(NC) TXOUT_U0N(NC)
TXOUT_U2P(NC) TXOUT_U2N(NC)
TXOUT_U3N(NC)
TXCLK_LP(DBG_GPIO1) TXCLK_LN(DBG_GPIO3)
VDDLTP18(NC) VSSLTP18(NC)
VDDLT18_1(NC) VDDLT18_2(NC) VDDLT33_1(NC) VDDLT33_2(NC)
VSSLT1(VSS) VSSLT2(VSS) VSSLT3(VSS) VSSLT4(VSS) VSSLT5(VSS) VSSLT6(VSS) VSSLT7(VSS)
LVDS_DIGON(PCE_TCALRP)
LVDS_BLON(PCE_RCALRP)
LVDS_ENA_BL(PWM_GPIO2)
CLOCKs PLL PWR
A22 B22 A21 B21 B20 A20 A19 B19
B18 A18 A17 B17 D20 D21 D18 D19
B16 A16 D16 D17
A13 B13
A15 B15 A14 B14
C14 D15 C16 C18 C20 E20 C22
E9 F7 G12
0.1U_0402_16V4Z
D
LVDS_A0+ <17> LVDS_A0- <17> LVDS_A1+ <17> LVDS_A1- <17> LVDS_A2+ <17> LVDS_A2- <17>
LVDS_B0+ <17> LVDS_B0- <17> LVDS_B1+ <17> LVDS_B1- <17> LVDS_B2+ <17> LVDS_B2- <17>
LVDS_ACLK+ <17> LVDS_ACLK- <17> LVDS_BCLK+ <17> LVDS_BCLK- <17>
+VDDLTP18
+VDDLT18
1 2
R69 0_0402_5%
1 2
R70 0_0402_5%
C173
1
2
1
2
L3
1 2
BLM18PG121SN1D_0603
C171
2.2U_0603_6.3V4Z L5
1 2
BLM18PG121SN1D_0603
1
C174
4.7U_0805_10V4Z
2
0.08A/10mil/1vias
L
E
+1.8VS
+1.8VS
UMA_ENVDD <17> ENBKL <33>
PA_RS780A4 placement close to NB ball
flash issue check IALAA
MIS.
TMDS_HPD(NC)
SUS_STAT#(PWM_GPIO5)
HPD(NC)
THERMALDIODE_P THERMALDIODE_N
TESTMODE
D9 D10
D12
NB_THERMAL_DA
AE8
NB_THERMAL_DC
AD8
1 2
D13
R80
1.8K_0402_5%
1 2
R77 0_0402_5%
HPD <18> SUS_STAT_R# <14>
SUS_STAT# <20>
T49PAD T50PAD
NB temp to SB
Strap pin
4 4
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2007/08/02 2008/08/02
Deciphered Date
Title
Size Document Number Rev
Custom
D
Date: Sheet
Compal Electronics, Inc.
RS780 VEDIO/CLK GEN
LA-4111P
11 47Thursday, November 15, 2007
E
0.2
of
A
B
C
D
E
MEM_BA0 MEM_BA1
MEM_A12 MEM_A11
1 1
12
R91
100_0402_1%
SIDE@
2 2
MEM_A10 MEM_A9 MEM_A8 MEM_A7 MEM_A6 MEM_A5 MEM_A4 MEM_A3 MEM_A2 MEM_A12 MEM_A1 MEM_A0
MEM_CLKN MEM_CLKP
MEM_CKE
MEM_CS# MEM_WE# MEM_RAS# MEM_CAS# MEM_DM0
MEM_DM1
MEM_ODT
MEM_DQS_P0 MEM_DQS_N0
MEM_DQS_P1 MEM_DQS_N1
+MEM_VREF
MEM_BA2
U61
L2
BA0
L3
BA1
R2
A12
P7
A11
M2
A10/AP
P3
A9
P8
A8
P2
A7
N7
A6
N3
A5
N8
A4
N2
A3
M7
A2
M3
A1
M8
A0
K8
CK
J8
CK
K2
CKE
L8
CS
K3
WE
K7
RAS
L7
CAS
F3
LDM
B3
UDM
K9
ODT
F7
LDQS
E8
LDQS
B7
UDQS
A8
UDQS
J2
VREF
A2
NC
E2
NC
L1
NC
R3
NC
R7
NC
R8
NC
HY5PS561621AFP-25_FBGA84
SIDE@
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10
DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VDD VDD VDD VDD VDD
VDDL
VSSDL
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
VSS VSS VSS VSS VSS
MEM_DQ15
B9
MEM_DQ11
B1
MEM_DQ13 MEM_A1
D9
MEM_DQ12 MEM_A2
D1
MEM_DQ8
D3
MEM_DQ10
D7
MEM_DQ9
C2
MEM_DQ14
C8
MEM_DQ3
F9
MEM_DQ7
F1
MEM_DQ1
H9
MEM_DQ6
H1
MEM_DQ5
H3
MEM_DQ0
H7
MEM_DQ4
G2
MEM_DQ2
G8
A9 C1 C3 C7 C9 E9 G1 G3 G7 G9
A1 E1 J9 M9 R1
J1 J7
A7 B2 B8 D2 D8 E7 F2 F8 H2 H8
A3 E3 J3 N1 P9
+VDDL
+1.8V_MEM_VDDQ
+1.8V_MEM_VDDQ
L96
1 2
0_0603_5%SIDE@
1
C184
1U_0603_10V6KSIDE@
2
Layout Note: 50 mil for VSSDL
+1.8V_MEM_VDDQ
R92 40.2_0402_1%SIDE@ R93 40.2_0402_1%SIDE@
09/19 update
12 12
MEM_A0
MEM_A3 MEM_A4 MEM_A5 MEM_A6 MEM_A7 MEM_A8 MEM_A9 MEM_A10 MEM_A11
MEM_BA0 MEM_BA1 MEM_BA2
MEM_RAS# MEM_CAS# MEM_WE# MEM_CS# MEM_CKE MEM_ODT
MEM_CLKP MEM_CLKN
MEM_COMP_P MEM_COMP_N
U3D
AB12
MEM_A0(NC)
AE16
MEM_A1(NC)
V11
MEM_A2(NC)
AE15
MEM_A3(NC)
AA12
MEM_A4(NC)
AB16
MEM_A5(NC)
AB14
MEM_A6(NC)
AD14
MEM_A7(NC)
AD13
MEM_A8(NC)
AD15
MEM_A9(NC)
AC16
MEM_A10(NC)
AE13
MEM_A11(NC)
AC14
MEM_A12(NC)
Y14
MEM_A13(NC)
AD16
MEM_BA0(NC)
AE17
MEM_BA1(NC)
AD17
MEM_BA2(NC)
W12
MEM_RASb(NC)
Y12
MEM_CASb(NC)
AD18
MEM_WEb(NC)
AB13
MEM_CSb(NC)
AB18
MEM_CKE(NC)
V14
MEM_ODT(NC)
V15
MEM_CKP(NC)
W14
MEM_CKN(NC)
AE12
MEM_COMPP(NC)
AD12
MEM_COMPN(NC)
RS780M_FCBGA528
UMA@
PAR 4 OF 6
MEM_DQ0/DVO_VSYNC(NC) MEM_DQ1/DVO_HSYNC(NC)
MEM_DQ2/DVO_DE(NC) MEM_DQ3/DVO_D0(NC)
MEM_DQ5/DVO_D1(NC) MEM_DQ6/DVO_D2(NC) MEM_DQ7/DVO_D4(NC) MEM_DQ8/DVO_D3(NC)
MEM_DQ9/DVO_D5(NC) MEM_DQ10/DVO_D6(NC) MEM_DQ11/DVO_D7(NC)
MEM_DQ12(NC)
MEM_DQ13/DVO_D9(NC)
MEM_DQ14/DVO_D10(NC) MEM_DQ15/DVO_D11(NC)
MEM_DQS0P/DVO_IDCKP(NC)
MEM_DQS0N/DVO_IDCKN(NC)
MEM_DQS1P(NC) MEM_DQS1N(NC)
MEM_DM1/DVO_D8(NC)
SBD_MEM/DVO_I/F
IOPLLVDD18(NC)
MEM_VREF(NC)
MEM_DQ4(NC)
MEM_DM0(NC)
IOPLLVDD(NC)
IOPLLVSS(NC)
AA18 AA20 AA19 Y19 V17 AA17 AA15 Y15 AC20 AD19 AE22 AC18 AB20 AD22 AC22 AD21
Y17 W18 AD20 AE21
W17 AE19
AE23 AE24
AD23 AE18
MEM_DQ0 MEM_DQ1 MEM_DQ2 MEM_DQ3 MEM_DQ4 MEM_DQ5 MEM_DQ6 MEM_DQ7 MEM_DQ8 MEM_DQ9 MEM_DQ10 MEM_DQ11 MEM_DQ12 MEM_DQ13 MEM_DQ14 MEM_DQ15
MEM_DQS_P0 MEM_DQS_N0 MEM_DQS_P1 MEM_DQS_N1
MEM_DM0 MEM_DM1
+NB_IOPLLVDD
+MEM_VREF1
MEM_COMP_P and MEM_COMP_N trace width >=10mils and 10mils spacing from other Signals in X,Y,Z directions
L13
1 2
BLM18PG121SN1D_0603
1
C181
2.2U_0603_6.3V4Z
2
SIDE@
+1.8V_IOPLLVDD
+1.1VS
1
C182
0.1U_0402_16V4Z
2
SIDE@
09/19 update Del SI3456 and MEM related Pull-high.
L12
1 2
BLM18PG121SN1D_0603
1
C183
2.2U_0603_6.3V4Z
2
SIDE@
+1.8VS
9/20 SA000012G20 S IC D2 32M16 HY5PS121621CFP-25 FBGA 84P
3 3
1
SIDE@
C195
2
1
SIDE@
C199
2
4 4
A
SIDE@
R96
1 2
1K_0402_1%
0.1U_0402_16V4Z
+MEM_VREF
SIDE@
R98
0.1U_0402_16V4Z
1 2
1K_0402_1%
Side Port disable,VREF need connect to +1.8VS for DDR2
+1.8V_MEM_VDDQ+1.8V_MEM_VDDQ
SIDE@
SIDE@
1
C196
2
0.1U_0402_16V4Z
1
C200
2
0.1U_0402_16V4Z
R97
1 2
R99
1 2
10/8 update
SIDE@
1K_0402_1%
+MEM_VREF1
SIDE@
1K_0402_1%
B
SIDE@
+1.8V_MEM_VDDQ
2
C608
1
SIDE@
1U_0402_6.3V4Z
2
C607
1
SIDE@
1U_0402_6.3V4Z
1
C201
2
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
1
SIDE@
0.1U_0402_16V4Z
C202
1
C203
SIDE@
2
2
0.1U_0402_16V4Z
2007/08/02 2008/08/02
10/8 update
L15
1 2
0_0805_5%SIDE@
220 ohm @ 100MHz,2A
22U_0805_6.3V6M
Deciphered Date
+1.8VS
Title
Size Document Number Rev
Custom
D
Date: Sheet
Compal Electronics, Inc.
RS780 Side-Port DDR2 SDRAM
LA-4111P
E
of
12 47Thursday, No vember 15, 2007
0.2
A
hexainf@hotmail.com
B
C
D
E
1 1
0.6A/50mil/4vias
+1.1VS
FBMA-L11-201209-221LMA30T_0805
FBMA-L11-201209-221LMA30T_0805
+1.2V_HT
2 2
09/19 update
3 3
FBMA-L11-201209-221LMA30T_0805@
+1.35VS
FBMA-L11-201209-221LMA30T_0805
+1.8VS
FBMA-L11-201209-221LMA30T_0805
L18
L19
12
L95
12
L22
4.7U_0805_10V4Z
L16
4.7U_0805_10V4Z
4.7U_0805_10V4Z
12
12
2A
C215
4.7U_0805_10V4Z
2A
12
1
C235
2
4.7U_0805_10V4Z
L
2A
0.1U_0402_16V4Z C206
1
C209
2
0.45A/40mil/3vias
L
0.1U_0402_16V4Z
1
1
C214
2
2
0.1U_0402_16V4Z
0.5A/50mil/4vias
L
2A
1
C225
C226
2
0.1U_0402_16V4Z
0.25A/30mil/2vias
L
1
C236
C246
2
0.1U_0402_16V4Z
+1.8VS
C251
1U_0402_6.3V4Z
1
C207
2
0.1U_0402_16V4Z
1
C216
2
1
C227
2
0.1U_0402_16V4Z
1
C237
2
0.1U_0402_16V4Z
+1.8VS
1
2
0.1U_0402_16V4Z C208
1
1
2
2
0.1U_0402_16V4Z C217
1
2
1
1
C229
C228
2
2
0.1U_0402_16V4Z
1
1
C239
C238
2
2
0.1U_0402_16V4Z
1 2
R1051 0_0603_5%SIDE@
11/13 update
+VDDHT
1
C210
0.1U_0402_16V4Z
2
+VDDHTRX
1
C218
0.1U_0402_16V4Z
2
+VDDHTTX
1
2
0.1U_0402_16V4Z
+VDDA18PCIE
1
2
0.1U_0402_16V4Z
+1.8V_VDD_SP
J17
K16
L16 M16 P16 R16
T16 H18
G19
F20 E21 D22 B23 A23
AE25 AD24 AC23 AB22 AA21
Y20
W19
V18 U17
T17 R17 P17 M17
J10 P10 K10 M10
L10
W9
T10 R10
AA9 AB9 AD9 AE9 U10
AE11 AD11
1
C252 1U_0402_6.3V4Z
2
SIDE@
U3E
VDDHT_1 VDDHT_2 VDDHT_3 VDDHT_4 VDDHT_5 VDDHT_6 VDDHT_7
VDDHTRX_1 VDDHTRX_2 VDDHTRX_3 VDDHTRX_4 VDDHTRX_5 VDDHTRX_6 VDDHTRX_7
VDDHTTX_1 VDDHTTX_2 VDDHTTX_3 VDDHTTX_4 VDDHTTX_5 VDDHTTX_6 VDDHTTX_7 VDDHTTX_8 VDDHTTX_9 VDDHTTX_10 VDDHTTX_11 VDDHTTX_12 VDDHTTX_13
VDDA18PCIE_1 VDDA18PCIE_2 VDDA18PCIE_3 VDDA18PCIE_4 VDDA18PCIE_5 VDDA18PCIE_6
H9
VDDA18PCIE_7 VDDA18PCIE_8 VDDA18PCIE_9
Y9
VDDA18PCIE_10 VDDA18PCIE_11 VDDA18PCIE_12 VDDA18PCIE_13 VDDA18PCIE_14 VDDA18PCIE_15
F9
VDD18_1
G9
VDD18_2 VDD18_MEM1(NC) VDD18_MEM2(NC)
RS780M_FCBGA528
UMA@
PART 5/6
VDDPCIE_1 VDDPCIE_2 VDDPCIE_3 VDDPCIE_4 VDDPCIE_5 VDDPCIE_6 VDDPCIE_7 VDDPCIE_8
VDDPCIE_9 VDDPCIE_10 VDDPCIE_11 VDDPCIE_12 VDDPCIE_13 VDDPCIE_14 VDDPCIE_15 VDDPCIE_16 VDDPCIE_17
VDDC_1 VDDC_2 VDDC_3 VDDC_4 VDDC_5 VDDC_6 VDDC_7 VDDC_8
VDDC_9 VDDC_10 VDDC_11 VDDC_12
POWER
VDDC_13 VDDC_14 VDDC_15 VDDC_16 VDDC_17 VDDC_18 VDDC_19 VDDC_20 VDDC_21 VDDC_22
VDD_MEM1(NC) VDD_MEM2(NC) VDD_MEM3(NC) VDD_MEM4(NC) VDD_MEM5(NC) VDD_MEM6(NC)
VDD33_1(NC) VDD33_2(NC)
0.7A/60mil/4vias
L
VDDA_12=2.5A
A6 B6 C6 D6 E6 F6 G7 H8 J9 K9 M9 L9 P9 R9 T9 V9 U9
K12 J14 U16 J11 K15 M12 L14 L11 M13 M15 N12 N14 P11 P13 P14 R12 R15 T11 T15 U12 T14 J16
AE10 AA11 Y11 AD10 AB10
+1.8V_VDD_MEM
AC10 H11
H12
L17
1 2
FBMA-L11-201209-221LMA30T_0805
+VDDA11PCIE
10/04 update
L
C211 C212
C220 1U_0402_6.3V4Z C219 1U_0402_6.3V4Z C222 1U_0402_6.3V4Z C221 1U_0402_6.3V4Z C224 0.1U_0402_16V4Z C223 0.1U_0402_16V4Z
+1.1VS +NB_VDDC
L
1
C2470.1U_0402_16V4Z
2
0.15A/30mil/2vias
+3VS
L20 FBMA-L11-201209-221LMA30T_0805 L21
FBMA-L11-201209-221LMA30T_0805
7A/280mil/16vias
1
1
1
1
C2410.1U_0402_16V4Z
C2430.1U_0402_16V4Z
C2400.1U_0402_16V4Z
C2420.1U_0402_16V4Z
2
2
2
2
+1.8VS
SIDE@
0_0603_5%
1 2
R1054
1 2 1 2 1 2 1 2
1 2 1 2
VDD_CORE=5A
1
1
C2310.1U_0402_16V4Z
C2300.1U_0402_16V4Z
2
2
1 2 1 2
10U_0805_10V4Z 10U_0805_10V4Z
12 12
1
1
C2320.1U_0402_16V4Z
C2440.1U_0402_16V4Z
2
2
C2500.1U_0402_16V4Z C2530.1U_0402_16V4Z
330U_D2E_2.5VM_R15
1
1
C24510U_0805_10V4Z
C23310U_0805_10V4Z
2
2
12 12 12 12 12
+1.1VS
1
C234
+
2
C2494.7U_0805_10V4Z SIDE@ C2480.1U_0402_16V4Z SIDE@ C5970.1U_0402_16V4Z SIDE@ C5980.1U_0402_16V4Z SIDE@ C5990.1U_0402_16V4Z SIDE@
U3F
A25
VSSAHT1
D23
VSSAHT2
E22
VSSAHT3
G22
VSSAHT4
G24
VSSAHT5
G25
VSSAHT6
H19
VSSAHT7
J22
VSSAHT8
L17
VSSAHT9
L22
VSSAHT10
L24
VSSAHT11
L25
VSSAHT12
M20
VSSAHT13
N22
VSSAHT14
P20
VSSAHT15
R19
VSSAHT16
R22
VSSAHT17
R24
VSSAHT18
R25
VSSAHT19
H20
VSSAHT20
U22
VSSAHT21
V19
VSSAHT22
W22
VSSAHT23
W24
VSSAHT24
W25
VSSAHT25
Y21
VSSAHT26
AD25
VSSAHT27
L12
VSS11
M14
VSS12
N13
VSS13
P12
VSS14
P15
VSS15
R11
VSS16
R14
VSS17
T12
VSS18
U14
VSS19
U11
VSS20
U15
VSS21
V12
VSS22
W11
VSS23
W15
VSS24
AC12
VSS25
AA14
VSS26
Y18
VSS27
AB11
VSS28
AB15
VSS29
AB17
VSS30
AB19
VSS31
AE20
VSS32
AB21
VSS33
K11
VSS34
RS780M_FCBGA528
UMA@
PART 6/6
GROUND
VSSAPCIE1 VSSAPCIE2 VSSAPCIE3 VSSAPCIE4 VSSAPCIE5 VSSAPCIE6 VSSAPCIE7 VSSAPCIE8
VSSAPCIE9 VSSAPCIE10 VSSAPCIE11 VSSAPCIE12 VSSAPCIE13 VSSAPCIE14 VSSAPCIE15 VSSAPCIE16 VSSAPCIE17 VSSAPCIE18 VSSAPCIE19 VSSAPCIE20 VSSAPCIE21 VSSAPCIE22 VSSAPCIE23 VSSAPCIE24 VSSAPCIE25 VSSAPCIE26 VSSAPCIE27 VSSAPCIE28 VSSAPCIE29 VSSAPCIE30 VSSAPCIE31 VSSAPCIE32 VSSAPCIE33 VSSAPCIE34 VSSAPCIE35 VSSAPCIE36 VSSAPCIE37 VSSAPCIE38 VSSAPCIE39 VSSAPCIE40
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9
VSS10
A2 B1 D3 D5 E4 G1 G2 G4 H7 J4 R7 L1 L2 L4 L7 M6 N4 P6 R1 R2 R4 V7 U4 V8 V6 W1 W2 W4 W7 W8 Y6 AA4 AB5 AB1 AB7 AC3 AC4 AE1 AE4 AB2
AE14 D11 G8 E14 E15 J15 J12 K14 M11 L15
+1.8VS
1
C1064
2
10U_0805_10V4Z
4 4
VLDT_EN#<36>
10/8 update
R1017 0_0402_5%
A
2N7002_SOT23-3
1 2
2
1
Just for RS780M A11 version boot issue
L
12
R1015 1K_0402_1%
+VREF1.35V
12
Q163
C1068
0.1U_0402_16V7K@
2
G
R1016
13
D
3K_0402_5%
S
0.1U_0402_16V7K
U64
VIN1VCNTL
2
GND
3
VREF
4
VOUT
G2992F1U_SO8
1
2
C1067
C1066
10U_0805_10V4Z
2
1
B
+1.35VS
NC NC NC TP
6 5 7 8 9
09/19 update
+3VS
1
C1065 1U_0603_10V6K
2
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2007/08/02 2008/08/02
Deciphered Date
Title
Size Document Number Rev
Custom
D
Date: Sheet
Compal Electronics, Inc.
RS780 PWR/GND
LA-4111P
13 47Thursday, No vember 15, 2007
E
0.2
of
A
B
C
D
E
1 1
2 2
RS780 DFT_GPIO5 mux at CRT_VSYNC pull low to 3K
CRT_VSYNC<11,16>
12
R101 1K_0402_5%@
12
R102 1K_0402_5%
+3VS
DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb
Enables the Test Debug Bus using GPIO. 1 : Disable (RS740) Enable (RX780, RS780) 0 : Enable (Rs740) Disable (RX780, RS780) PIN: RS740-->RS780_AUX_CAL; RX780-->NB_TV_C; RS780--> VSYNC#
DFT_GPIO1: LOA D_ EE PROM_STRAPS
1 2
R104 150_0402_1%@ D4 CH751H-40PT_SOD323-2@
2 1
Selects Loading of STRAPS from EPROM 1 : Bypass the loading of EEPROM straps and use Hardware Default Values 0 : I2C Master can load strap values from EEPROM if connected, or use default values if not connected RS740/RX780: DFT_GPIO1 RS780:SUS_STAT
RS780 DFT_GPIO1
AUX_CAL<11>
SUS_STAT_R#<11> PLT_RST# <11,19,25,26,27,32,33>
RX780 DFT_GPIO1 mux at GREEN(Ball E18) and change pull low form 150 to 3K.
3 3
DFT_GPIO0: STR A P_DEBUG_BUS_PCIE_E NABLEb
RS780_DFT_GPIO_0<11>
RS780 use HSYNC to enable SIDE PORT (internal pull high)
CRT_HSYNC<11,16>
R105 1K_0402_5%@
R107 3K_0402_5%SIDE@
12
12
RX780: Enables the Test Debug Bus using PCIE bus 1 : Disable ( Can still be enabled using nbcfg register access ) 0 : Enable
RS740/RS780: Enables Side port memory ( RS780 use HSYNC#)
1. Disable (RS740/RS780) 0 : Enable (RS740/RS780)
10/09 update
4 4
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2007/08/02 2008/08/02
Deciphered Date
Title
Size Document Number Rev
Custom
D
Date: Sheet
Compal Electronics, Inc.
RS780 STRAPS
LA-4111P
14 47Thursday, No vember 15, 2007
E
0.2
of
A
hexainf@hotmail.com
B
C
D
E
R167
1 2
0_0805_5%
+3VS_CLK
1
C444 10U_0805_10V4Z
2
1
C445
0.1U_0402_16V4Z
2
1
C458
0.1U_0402_16V4Z
2
1
C446
0.1U_0402_16V4Z
2
1
C459
0.1U_0402_16V4Z
2
1
C447
0.1U_0402_16V4Z
2
1
C460
0.1U_0402_16V4Z
2
1
C448
0.1U_0402_16V4Z
2
1
C461
0.1U_0402_16V4Z
2
1
C449
0.1U_0402_16V4Z
2
1
C450
0.1U_0402_16V4Z
2
1
C451
@
1U_0402_6.3V4Z
2
+3VS
R168
1 2
0_0805_5%
+VDDCLK_IO
1
2
0.1U_0402_16V4Z
1
C452
2
C453
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C454
2
1
C455
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C456
2
1
C457
2
+1.2V_HT
10U_0805_10V4Z
1 1
EMI Caps for single end clock.
CLK_48M_USB
R170 33_0402_5%
1 2
1 2
CLK_48M_USB_R
71
VSS_48
48MHz_0
+3VS_CLK
69
70
VDD_48
48MHz_1
CLK_XTAL_OUT
68
CLK_XTAL_IN
67
XTAL_OUT
R379 200_0402_1%
NB_OSC_14.318M_R
65
66
XTAL_IN
VSS_REF
REF_0/SEL_HTT66
+3VS_CLK
SEL_SATA
27M_SEL
64
63
62
REF_2/SEL_27
REF_1/SEL_SATA
R220 33_0402_5%
1 2
+3VS_CLK
61
60
59
58
57
VSS_HTT
VDD_HTT
VDD_REF
HTT_0/66M_0
HTT_0#/66M_1
1 2
R380 100_0402_1%
1 2
R174 8.2K_0402_5%
CLK_CPU_BCLK_R CLK_CPU_BCLK#_R
09/21 update
56
55
PD#
CPU_K8_0
CPU_K8_0#
VDD_CPU
VDD_CPU_I/O
VSS_CPU CLKREQ_1# CLKREQ_2#
VDD_A
VSS_A
VSS_SATA
SRC_6/SATA
SRC_6#/SATA#
VDD_SATA CLKREQ_3# CLKREQ_4#
SB_SRC_SLOW#
SB_SRC_0
SB_SRC_0#
VDD_SB_SRC
VDD_SB_SRC_IO
CLK_XTAL_OUT CLK_XTAL_IN
Y2
12
14.31818MHZ_20P_6X1430004201
+3VS_CLK
+VDDCLK_IO
+VDDCLK_IO
1
C465 22P_0402_50V8J
2
+3VS_CLK
09/29 update
U10
1
SCL
2
SDA
3
VDD_DOT
4
SRC_7#/27M
5
SRC_7/27M_SS
6
VSS_DOT
7
SRC_5#
8
SRC_5
9
SRC_4#
10
SRC_4
11
VSS_SRC
12
VDD_SRC_IO
13
SRC_3#
14
SRC_3
15
SRC_2#
16
SRC_2
17
VDD_SRC
18
VDD_SRC_IO
72
73
GND
2 2
22P_0402_50V8J
C464
1
2
Routing the t race at least 10mil
SMB_CK_CLK0<8,9,20,30> SMB_CK_DAT0<8,9,20,30>
PA_RS7X0A1
SB LINK SB SRC
MiniCard_1 MiniCard_2
3 3
CLK_SBLINK_BCLK#<11>
CLK_SBLINK_BCLK<11>
CLK_PCIE_MCARD1#<26>
CLK_PCIE_MCARD1<26>
CLK_PCIE_MCARD2#<26>
CLK_PCIE_MCARD2<26>
CLK_48M_USB <20> NB_OSC_14.318M <11>
CLK_14M_SIO <32> CLK_NBHT <11> CLK_NBHT# <11>
+3VS_CLK
1 2
R946 0_0402_1%
1 2
R945 0_0402_1%
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
+3VS_CLK +VDDCLK_IO
CLKREQ_NCARD# CLKREQ_MCARD2#
+3VS_CLK
CLKREQ_MCARD1# CLKREQ4
1 2
R372 10K_0402_5%
+3VS_CLK +VDDCLK_IO
NB
R186 261_0402_1%@
10/03 update
1 2
+3VS_CLK
RS780
CLK_SBSRC_BCLK <19> CLK_SBSRC_BCLK# <19>
CLKREQ_MCARD1# <26>
+3VS_CLK
OSC_14M_NB
1.8V 75R/100RRX780
1.1V 200R/100R
CLK_CPU_BCLK <6>
CPU
CLK_CPU_BCLK# <6>
CLKREQ_NCARD# <26> CLKREQ_MCARD2# <26>
For ICS need to pull high. For SLG is NC
PA_RS7X0A1
NB_OSC_14.318M
CLK_14M_SIO
C1076
@
5P_0402_50V8C
1
2
1
@
1
5P_0402_50V8C
2
C1075
@ 2
5P_0402_50V8C
C1074
VSS_SRC19SRC_1#20SRC_121SRC_0#22SRC_023CLKREQ_0#24ATIGCLK_2#25ATIGCLK_226VSS_ATIG27VDD_ATIG_IO28VDD_ATIG29ATIGCLK_1#30ATIGCLK_131ATIGCLK_0#32VSS_SB_SRC36SB_SRC_135SB_SRC_1#34ATIGCLK_0
33
+3VS_CLK
R179
@
8.2K_0402_5%
1 2
SEL_SATA
R181
8.2K_0402_5%
4 4
SEL_SATA
* default
1 2
1
configure as SATA output
*
configure as normal SRC(SRC_6) output
0
+3VS_CLK
1 2
27M_SEL
R180
8.2K_0402_5%
27M_SEL
1* 0
configure as 27M and 27M_SS output configure as SRC_7 output
* default
+3VS_CLK
+VDDCLK_IO
CLKREQ_LAN#
SLG8SP626VTR_QFN72_10x10
9/20 SA00001Z300 S IC SLG8SP626VTR QFN 72P CLK GEN 9/20 SA000025B00 S IC RTM880N-795-GRT QFN 72P CLK GEN
NBGFX_CLK <11> NBGFX_CLK# <11>
CLK_PCIE_MCARD0 <27> CLK_PCIE_MCARD0# <27> CLKREQ_LAN# <25> CLK_PCIE_LAN <25> CLK_PCIE_LAN# <25>
CLK_PCIE_NCARD <26> CLK_PCIE_NCARD# <26>
NB GFX
Card Reader
GLAN
New Card
CLKREQ_NCARD# CLKREQ_MCARD2# CLKREQ_MCARD1# CLKREQ_LAN# CLKREQ4
NB CLOCK INPUT TABLE
NB CLOCKS HT_REFCLKP HT_REFCLKN REFCLK_P REFCLK_N GFX_REFCLK 100M DIFF
1 2
R324 8.2K_0402_5%
1 2
R325 8.2K_0402_5%
1 2
R326 8.2K_0402_5%
1 2
R1039 8.2K_0402_5%
1 2
R1045 8.2K_0402_5%
RX780 RS780
100M DIFF 100M DIFF
14M SE (1.8V) 14M SE (1.1V) NC vref
+3VS_CLK
100M DIFF 100M DIFF
100M DIFF(IN/OUT)*
Use voltage divider resistor R379 & R380 to pull low
NB_OSC_14.318M
*0 confi gu re as di ff er en tial 100MHz output
* default
configure as single-ended 66MHz output1
A
B
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2007/08/02 2008/08/02
Deciphered Date
Title
Size Document Number Rev
Custom
D
Date: Sheet
Compal Electronics, Inc.
Clock generator
LA-4111P
15 47Thursday, November 15, 2007
E
0.2
of
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