HP CQ40 Schematics REV 0.2 14NOV2007

A

[e-mail]

1 1

2 2

B

C

D

E

Compal confidential

Schematics Document

Mobile AMD S1G2 CPU with ATI
RS780M(NB) & SB700(SB) core logic

3 3

2007-11-14

REV:0.2

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Cover Sheet

LA-4111P

147Thursday, November 15, 2007

E

0.2

of

A

Compal Confidential

B

C

D

Consumer AMD 14" UMA - Ripley (JBL20)

E

1 1

Accelerometer
ST LIS302DLTR

Page 30

Thermal Sensor
ADM1032ARMZ

Page 6

Fan conn

Page 4

AMD S1G2 CPU

638-PIN uFCPGA 638

Page 4, 5, 6, 7

DDR2 800MHz 1.8V

Dual Channel

DDR2-SO-DIMM X2

BANK 0, 1, 2, 3

Page 8, 9

72QFN

Clock Generator
SLG8SP626VTR

Page 15

Side-Port DDR2 SDRAM

Hyper Transport Link

16X16

LVDS Panel

Page 16

Page 18

Page 17

A-Link Express II

Interface

2 2

CRT

HDMI

PCI-E BUS*5

CardReader
JMicron
JMB385-LGEZ0A

3 3

CardReade r Socket

Page 27

Page 27

Realtek
8102E(10/100M)

Page 25

RJ45/11 CONN

Page 25

Mini-Card*2

WLAN & WWAN

Page 26

Express Card

Page 26

ATI RS780M

4X PCI-E

ATI SB700

DDR2 400MHz

Page 10, 11, 12, 13, 14

USB2.0 X12

Azalia (HDA I/F)
SATA Master-1
SATA Master-2
SATA Slave
SATA Slave

Page 19, 20, 21, 22, 23

LPC BUS

256Mbits(16Mbx16)

USB conn x2

BT Conn

Mini-Card WWAN

14" Only

USB conn x1

Page 12

Page 31

Page 31

Page 26

Page 31

USB WebCam

Page 17

FingerPrinter AES1610
USBx1

MDC V1.5

page 35

Page 34

Audio CKT

Codec_IDT9271B7

Page 28 Page 29

daughter board

daughter board

daughter board

daughter board

daughter board

AMP & Audio Jack

TPA6017A2

KBC

ENE KB926

Page 33

Docking CONN.

*RJ-45(LED*2)
*RJ-11(Pass Through)
*CRT
*COMPOSITE Video Out
*S-VIDEO OUT
*SPDIF
*Headphone/Line Out L/R
*Stereo Mic L/R

4 4

*Volume Control

LED

P41

RTC CKT.

Page 19

Power OK CKT.

P35

Touch Pad CONN. Int.KBD

Consumer IR

Page 34

SPI

Page 34

Page 33

SPI ROM
SST25VF080B

Page 32

SATA HDD Connector

SATA ODD Connector

Multi-Bay HDD/ODD Option Connector

14" UMA PA Only

Page 24

Page 24

Page 24

e-SATA Con nector

Page 31

*Consumer IR
*USB x1
*DC JACK

Page 35

A

Power On/Off CKT.

P35

DC/DC Int erface CKT.

Page 36

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Block Diagram

LA-4111P

247Thursday, No vember 15, 2007

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of

A

[e-mail]

B

C

D

E

Voltage Rails

1 1

State

2 2

S0

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

3 3

I2C / SMBUS ADDRESSING

DEVICE

DDR SO-DIMM 0
DDR SO-DIMM 1
CLOCK GENERATOR (EXT.)

EC SM Bus1 address

Device

Smart Battery

24C16

4 4

O MEANS ON X MEANS OFF

power
plane

HEX

A0

D2

+B

O
O
O
O
O

X

+5VALW

+3VALW

O
O
O
O

X
XX X

ADDRESS

1 0 1 0 0 0 0 0
1 0 1 0 0 1 0 0A4
1 1 0 1 0 0 1 0

+1.8V

EC SM Bus2 address

HEX

Address Address

16H

1010 000X b

A0H

Device

CPU

ADI1032-2 CPU

HEX

98H
9AH

+5VS
+3VS
+1.5VS
+0.9V
+VCCP
+CPU_CORE

+VGA_CORE
+2.5VS
+1.8VS
+1.2VS
+0.9VGA

OO
OO

O

X
XX
X

1001 100X b0001 011X b
1001 101X b

X

SMBUS Control Table

SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
I2C_CLK
I2C_DATA
DDC_CLK0
DDC_DATA0
DDC_CLK1
DDC_DATA1
SCL0
SDA0
SCL1
SDA1
SCL2
SDA2
SCL3
SDA3

Symbol Note :

: means Digital Ground

: means Analog Ground

@ : means just reserve , no build
DEBUG@ : means jus t r e s e r v e for debug.

Layout Notes

L

UMA@ : means for RS780M.
Please see VGA@ as no install. No support RX780M.

11/14 update

: Question Ar ea Mark.(Wait check)

SOURCE

KB926

KB926

RS780M

RS780M

RS780M

SB700

SB700

SB700

SB700

INVERTER BATT EEPROM

X

SERIAL SENSOR

VV

XXX
XXX X X X X
XXX X X
XXX X X
XXX X X

THERMAL

CPU &
ADM1032

SODIMM CLK CHIP

XX

V

XXXX

XXX
XXX X

VV

XXXX
XXXX
XXXX

XX

MINI CARD

Slot 2I / II

LCD

XX

X

V

V

X
X

HDMI

X
X
X

V

XX
XXXX
XXXX
XX

G-Sensor

X
X
X
X
X
X
X

V

X

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Notes List

LA-4111P

347Thursday, November 15, 2007

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of

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1 1

H_CADIP[0..15]<10>

H_CADIP[0..15]
H_CADIN[0..15]

B

H_CADOP[0..15]
H_CADON[0..15]

H_CADOP[0..15] <10>
H_CADON[0..15] <10>H_CADIN[0..15]<10>

C

+1.2V_HT

250 mil

1

C1

4.7U_0805_10V4Z

2

1

C2

4.7U_0805_10V4Z

2

D

VLDT CAP.

1

C3

0.22U_0603_16V4Z

2

1

C4

0.22U_0603_16V4Z

2

1

C5
180P_0402_50V8J

2

E

1

C6
180P_0402_50V8J

2

Near CPU Socket

+1.2V_HT

VLDT=500mA

H_CADIP0
H_CADIN0
H_CADIP1
H_CADIN1
H_CADIP2

2 2

H_CLKIP0<10>
H_CLKIN0<10>
H_CLKIP1<10>

3 3

H_CLKIN1<10>
H_CTLIP0<10>
H_CTLIP1<10> H_CTLOP1 <10>

H_CTLIN1<10>

H_CADIN2
H_CADIP3
H_CADIN3
H_CADIP4
H_CADIN4
H_CADIP5
H_CADIN5
H_CADIP6
H_CADIN6
H_CADIP7
H_CADIN7
H_CADIP8
H_CADIN8
H_CADIP9
H_CADIN9
H_CADIP10
H_CADIN10
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIP13
H_CADIN13
H_CADIP14
H_CADIN14
H_CADIP15
H_CADIN15

JCPUA

D1
D2
D3
D4

E3
E2
E1

F1
G3
G2
G1
H1

J1

K1

L3

L2

L1
M1
N3
N2

E5

F5

F3

F4
G5
H5
H3
H4

K3

K4

L5
M5
M3
M4
N5

P5

J3

J2

J5

K5
N1

P1

P3

P4

9/20 SP07000DM00/SP07000EQ00

HT LINK

VLDT_A0
VLDT_A1
VLDT_A2
VLDT_A3

L0_CADIN_H0
L0_CADIN_L0
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H15
L0_CADIN_L15

L0_CLKIN_H0
L0_CLKIN_L0
L0_CLKIN_H1
L0_CLKIN_L1

L0_CTLIN_H0
L0_CTLIN_L0
L0_CTLIN_H1
L0_CTLIN_L1

FOX_PZ6382A-284S-41F_GRIFFIN

CONN@

Athlon 64 S1
Processor Socket

VLDT_B0
VLDT_B1
VLDT_B2
VLDT_B3

L0_CADOUT_H0
L0_CADOUT_L0
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H9

L0_CADOUT_L9
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H15
L0_CADOUT_L15

L0_CLKOUT_H0

L0_CLKOUT_L0

L0_CLKOUT_H1

L0_CLKOUT_L1
L0_CTLOUT_H0

L0_CTLOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1

+VLDT_B

AE2
AE3
AE4
AE5

AD1
AC1
AC2
AC3
AB1
AA1
AA2
AA3
W2
W3
V1
U1
U2
U3
T1
R1
AD4
AD3
AD5
AC5
AB4
AB3
AB5
AA5
Y5
W5
V4
V3
V5
U5
T4
T3

Y1
W1
Y4
Y3

R2
R3
T5
R5

1 2

C7 4.7U_0805_10V4Z

If VLDT is connected only on one side, one

4.7uF cap should be added to the island

H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7
H_CADOP8
H_CADON8
H_CADOP9
H_CADON9
H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15

side.

H_CLKOP0 <10>
H_CLKON0 <10>
H_CLKOP1 <10>
H_CLKON1 <10>

H_CTLOP0 <10>
H_CTLON0 <10>H_CTLIN0<10>

H_CTLON1 <10>

PWM Fan Control circuit

CH751H-40PT_SOD323-2

FAN_PWM<33>

+5VS

1

D1

2 1

6

2

1

D

Q1

G

3

S

SI3456BDV-T1-E3_TSOP6

4 5

C8

4.7U_0805_10V4Z

2

+VCC_FAN

1

C9

0.1U_0402_16V4Z

2

12

D2

@

RLZ5.1B_LL34

11/14 update

JP2

1

1

2

2

3

GND

4

GND

ACES_88231-02001

CONN@

Change PCB Footprint from
ACES_85204-02001_2P to
ACES_88231-02001_2P

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

AMD CPU S1G2 HT I/F

LA-4111P

447Thursday, No vember 15, 2007

E

0.2

of

A

[e-mail]

B

C

D

E

Processor DDR2 Memory Interface

PLACE CLOSE TO P ROCESSOR

1 1

2 2

Place them close to CPU within 1"

R4 39.2_0402_1%

1 2

DDR_A_BS#0<8>
DDR_A_BS#1<8>
DDR_A_BS#2<8>

DDR_A_RAS#<8>
DDR_A_CAS#<8>
DDR_A_WE#<8>

1 2

R3 39.2_0402_1%

T2 PA D

DDR_A_ODT0
DDR_A_ODT1

DDR_CS0_DIMMA#
DDR_CS1_DIMMA# DDR_CS0_DIMMB#

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA

DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK1

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

+1.8V

DDR_A_ODT0<8>
DDR_A_ODT1<8>

DDR_CS0_DIMMA#<8>
DDR_CS1_DIMMA#<8> DDR_CS0_DIMMB# <9>

DDR_CKE0_DIMMA<8>
DDR_CKE1_DIMMA<8>

DDR_A_CLK0<8>

DDR_A_CLK#0<8>

3 3

4 4

DDR_A_CLK1<8>

DDR_A_CLK#1<8>

DDR_A_MA[15..0]<8> DDR_B_MA[15..0] <9>

AD10
AF10

AE10

AA16

D10
C10
B10

H16
T19

V22
U21
V19

T20
U19
U20
V20

J22
J20

N19
N20
E16
F16
Y16

P19
P20

N21
M20
N22
M19
M22
L20
M24
L21
L19
K22
R21
L22
K20
V24
K24
K19

R20
R23

J21

R19
T22
T24

WITHIN 1.5 INCH

DDR_A_CLK0

DDR_A_CLK#0
DDR_A_CLK1

DDR_A_CLK#1

DDR_B_CLK0

DDR_B_CLK#0
DDR_B_CLK1

DDR_B_CLK#1

JCPUB

VTT1

MEM:CMD/CTRL/CLK

VTT2
VTT3
VTT4

MEMZP
MEMZN

RSVD_M1
MA0_ODT0

MA0_ODT1
MA1_ODT0
MA1_ODT1

MA0_CS_L0
MA0_CS_L1
MA1_CS_L0
MA1_CS_L1

MA_CKE0
MA_CKE1

MA_CLK_H5
MA_CLK_L5
MA_CLK_H1
MA_CLK_L1
MA_CLK_H7
MA_CLK_L7
MA_CLK_H4
MA_CLK_L4

MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14
MA_ADD15

MA_BANK0
MA_BANK1
MA_BANK2

MA_RAS_L
MA_CAS_L
MA_WE_L

FOX_PZ6382A-284S-41F_GRIFFIN

Athlon 64 S1
Processor
Socket

CONN@

1

2

1

2

1

2

1

2

VTT_SENSE

MEMVREF

RSVD_M2

MB0_ODT0
MB0_ODT1
MB1_ODT0

MB0_CS_L0
MB0_CS_L1
MB1_CS_L0

MB_CKE0
MB_CKE1

MB_CLK_H5

MB_CLK_L5

MB_CLK_H1

MB_CLK_L1

MB_CLK_H7

MB_CLK_L7

MB_CLK_H4

MB_CLK_L4

MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8

MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15

MB_BANK0
MB_BANK1
MB_BANK2

MB_RAS_L
MB_CAS_L

MB_WE_L

C10

1.5P_0402_50V9C

C11

1.5P_0402_50V9C

C14

1.5P_0402_50V9C

C15

1.5P_0402_50V9C

W10

VTT5

AC10

VTT6

AB10

VTT7

AA10

VTT8

A10

VTT9

Y10
W17
B18
W26

W23
Y26

V26
W25
U22

J25
H26

P22
R22
A17
A18
AF18
AF17
R26
R25

P24
N24
P26
N23
N26
L23
N25
L24
M26
K26
T26
L26
L25
W24
J23
J24

R24
U26
J26

U25
U24
U23

+0.9V+0.9V

VTT_SENSE

+MCH_REF

DDR_B_ODT0
DDR_B_ODT1

DDR_CS1_DIMMB#

DDR_CKE0_DIMMB
DDR_CKE1_DIMMB

DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK1
DDR_B_CLK#1DDR_A_CLK#1

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2

DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#

+1.8V

R1

1K_0402_1%

R2

1K_0402_1%

T1PAD

09/13 update

T3PAD

DDR_B_ODT0 <9>
DDR_B_ODT1 <9>

DDR_CS1_DIMMB# <9>

DDR_CKE0_DIMMB <9>
DDR_CKE1_DIMMB <9>

DDR_B_CLK0 <9>
DDR_B_CLK#0 <9>
DDR_B_CLK1 <9>
DDR_B_CLK#1 <9>

DDR_B_BS#0 <9>
DDR_B_BS#1 <9>
DDR_B_BS#2 <9>

DDR_B_RAS# <9>
DDR_B_CAS# <9>
DDR_B_WE# <9>

09/13 update

1 2

+MCH_REF

1

C12

2

1 2

0.1U_0402_16V4Z

DDR_B_D[63..0]<9>

1

C13

2

1000P_0402_25V8J

DDR_B_DM[7..0]<9> DDR_A_DM[7..0] <8>

DDR_B_DQS0<9>
DDR_B_DQS#0<9>
DDR_B_DQS1<9>
DDR_B_DQS#1<9>
DDR_B_DQS2<9>
DDR_B_DQS#2<9>
DDR_B_DQS3<9>
DDR_B_DQS#3<9>
DDR_B_DQS4<9>
DDR_B_DQS#4<9>
DDR_B_DQS5<9>
DDR_B_DQS#5<9>
DDR_B_DQS6<9>
DDR_B_DQS#6<9>
DDR_B_DQS7<9>
DDR_B_DQS#7<9>

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS#0
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS7
DDR_B_DQS#7

JCPUC

C11
A11
A14
B14
G11
E11
D12
A13
A15
A16
A19
A20
C14
D14
C18
D18
D20
A21
D24
C25
B20
C20
B24
C24
E23
E24
G25
G26
C26
D26
G23

G24
AA24
AA23
AD24
AE24
AA26
AA25
AD26
AE25
AC22
AD22
AE20
AF20
AF24
AF23
AC20
AD20
AD18
AE18
AC14
AD14
AF19
AC18
AF16
AF15
AF13
AC12
AB11

Y11
AE14
AF14
AF11
AD11

A12

B16

A22

E25
AB26
AE22
AC16
AD12

C12

B12

D16

C16

A24

A23

F26

E26
AC25
AC26
AF21
AF22
AE16
AD16
AF12
AE12

FOX_PZ6382A-284S-41F_GRIFFIN

Athlon 64 S1
Processor Socket

CONN@

MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63

MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7

MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7

MEM:DATA

MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8

MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63

MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7

MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7

G12
F12
H14
G14
H11
H12
C13
E13
H15
E15
E17
H17
E14
F14
C17
G17
G18
C19
D22
E20
E18
F18
B22
C23
F20
F22
H24
J19
E21
E22
H20
H22
Y24
AB24
AB22
AA21
W22
W21
Y22
AA22
Y20
AA20
AA18
AB18
AB21
AD21
AD19
Y18
AD17
W16
W14
Y14
Y17
AB17
AB15
AD15
AB13
AD13
Y12
W11
AB14
AA14
AB12
AA12

E12
C15
E19
F24
AC24
Y19
AB16
Y13

G13
H13
G16
G15
C22
C21
G22
G21
AD23
AC23
AB19
AB20
Y15
W15
W12
W13

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS7
DDR_A_DQS#7

DDR_A_D[63..0] <8>

DDR_A_DQS0 <8>
DDR_A_DQS#0 <8>
DDR_A_DQS1 <8>
DDR_A_DQS#1 <8>
DDR_A_DQS2 <8>
DDR_A_DQS#2 <8>
DDR_A_DQS3 <8>
DDR_A_DQS#3 <8>
DDR_A_DQS4 <8>
DDR_A_DQS#4 <8>
DDR_A_DQS5 <8>
DDR_A_DQS#5 <8>
DDR_A_DQS6 <8>
DDR_A_DQS#6 <8>
DDR_A_DQS7 <8>
DDR_A_DQS#7 <8>

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

AMD CPU S1G2 DDRII I/F

LA-4111P

547Thursday, No vember 15, 2007

E

0.2

of

A

A:Need to re-Link "SGN00000200"

1 1

CLK_CPU_BCLK<15>

+2.5VS

C16

100U_D2_10VM

Place close to CPU wihtin 1.5"

C20

0718 Silego -- 216 ohm

CLK_CPU_BCLK#<15>

+1.8V

2 2

LDT_RST#<19>

09/13 update

H_PWRGD_CPU<19>

3 3

LDT_STOP#<11,19>

R15
300_0402_5%

1 2

LDT_RST#

1

C22

0.01U_0402_25V4Z

@

2

+1.8V

R21
300_0402_5%

1 2

H_PWRGD_CPU

1

C23

0.01U_0402_25V4Z

@

2

+1.8V

R36
300_0402_5%

1 2

LDT_STOP#

1

C25

0.01U_0402_25V4Z

@

2

0718 AMD , need check with AMD

+1.8V

R30
300_0402_5%

1 2

4 4

CPU_LDT_REQ#

1

C24

0.01U_0402_25V4Z

@

2

CPU_LDT_REQ# <11,19>

A

+CPU_CORE_0

R487 10_0402_5%

1 2
1 2

R486 10_0402_5%

+CPU_CORE_1

R489 10_0402_5%

1 2
1 2

R488 10_0402_5%

+3VS

20K_0402_5%

390_0402_5%

390_0402_5%

CPU_SIC

+3VS

0.1U_0402_16V4Z

C27

1 2

2200P_0402_50V7K

R18

R19

1

C26

2

+1.8V

+1.8V

2200p change to
1000p for ADT7421

CPU_VDD0_FB_H
CPU_VDD0_FB_L

Close to CPU

CPU_VDD1_FB_H
CPU_VDD1_FB_L

R175

12

S

Q127

12

FDV301N_NL_SOT23-3

12

FDV301N_NL_SOT23-3
Q129

THERMDA_CPU
THERMDC_CPU

C21 3900P_0402_50V7K

G

B

L1

1 2

FBM_L11_201209_300L_0805

1

+

2

3900P_0402_50V7K

1 2

12

R8
169_0402_1%

1 2

1 2

C939 0.1U_0402_16V4Z

R814

12

34.8K_0402_1%~N

2

SMB_EC_DA2CPU_SID

13

D

G

2

SMB_EC_CK2

13

D

S

EC is PU to 5VALW

FDV301N, the Vgs is:
min = 0.65V
Typ = 0.85V
Max = 1.5V

U2

1

VDD
D+

SDATA

ALERT#

D­THERM#4GND

B

SCLK

2
3

ADM1032ARMZ-2REEL_MSOP8

Address:100_1101

+2.5VDDA

VDDA=300mA

3300P_0402_50V7K

1

1

C174.7U_0805_10V4Z

C18

2

2

Address:100_1100

R13 44.2_0402_1%

1 2

R14 44.2_0402_1%

T4 PAD

T9 PAD
T11 PAD

1 2

CPU_VDD0_FB_H<43>
CPU_VDD0_FB_L<43>

CPU_VDD1_FB_H<43>
CPU_VDD1_FB_L<43>

+1.2V_HT

2.09V for Gate

SMB_EC_DA2 <33>

SMB_EC_CK2 <33>

SMB_EC_CK2

8

SMB_EC_DA2

7
6
5

1

C19

0.22U_0603_16V4Z

2

CPU_CLKIN_SC_P
CPU_CLKIN_SC_N

LDT_RST#
H_PWRGD_CPU
LDT_STOP#
CPU_LDT_REQ#

CPU_SIC
CPU_SID

CPU_HTREF0
CPU_HTREF1

CPU_VDD0_FB_H
CPU_VDD0_FB_L

CPU_VDD1_FB_H

CPU_DBRDY
CPU_TMS
CPU_TCK
CPU_TRST#
CPU_TDI

CPU_TEST23_TSTUPD

CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1

CPU_TEST25_H_BYPASSCLK_H
CPU_TEST25_L_BYPASSCLK_L

CPU_TEST21_SCANEN
CPU_TEST20_SCANCLK2
CPU_TEST24_SCANCLK1
CPU_TEST22_SCANSHIFTEN
CPU_TEST12_SCANSHIFTENB
CPU_TEST27_SINGLECHAIN

R25 0_0402_5%

1 2

CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO

NOTE: HDT TERMINATION IS REQUIRED
FOR REV. Ax SILICON ONLY.

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

JCPUD

F8

VDDA1

F9

VDDA2

A9

CLKIN_H

A8

CLKIN_L

B7

RESET_L

A7

PWROK

F10

LDTSTOP_L

C6

LDTREQ_L

AF4

SIC

AF5

SID

AE6

ALERT_L

R6

HT_REF0

P6

HT_REF1

F6

VDD0_FB_H

E6

VDD0_FB_L

Y6

VDD1_FB_H

AB6

VDD1_FB_L

G10

DBRDY

AA9

TMS

AC9

TCK

AD9

TRST_L

AF9

TDI

AD7

TEST23

H10

TEST18

G9

TEST19

E9

TEST25_H

E8

TEST25_L

AB8

TEST21

AF7

TEST20

AE7

TEST24

AE8

TEST22

AC8

TEST12

AF8

TEST27

C2

TEST9

AA6

TEST6

A3

RSVD1

A5

RSVD2

B3

RSVD3

B5

RSVD4

C1

RSVD5

FOX_PZ6382A-284S-41F_GRIFFIN

CONN@

12

+1.8V

R37220_0402_5%@

THERMTRIP_L

PROCHOT_L

VDDIO_FB_H
VDDIO_FB_L

VDDNB_FB_H
VDDNB_FB_L

R38220_0402_5%@

R39220_0402_5%@

R40220_0402_5%@

12

12

12

12

2007/08/02 2008/08/02

C

M11

KEY1

W18

KEY2

CPU_SVC

A6

SVC

CPU_SVD

A4

SVD

CPU_THERMTRIP#_R

AF6

CPU_PROCHOT#_1.8

AC7

CPU_MEMHOT#_1.8V

AA8

MEMHOT_L

THERMDC_CPU

W7

THERMDC

THERMDA

DBREQ_L

TEST28_H
TEST28_L

TEST17
TEST16
TEST15
TEST14

TEST10

TEST29_H
TEST29_L

RSVD10

RSVD9
RSVD8
RSVD7
RSVD6

R41220_0402_5%@

THERMDA_CPU

W8

09/19 update

W9
Y9

VDD_NB_FB_H

H6

VDD_NB_FB_LCPU_VDD1_FB_L

G6

CPU_DBREQ#

E10

CPU_TDO

AE9

TDO

CPU_TEST28_H_PLLCHRZ_P

J7

CPU_TEST28_L_PLLCHRZ_N

H8

CPU_TEST17_BP3

D7

CPU_TEST16_BP2

E7

CPU_TEST15_BP1

F7

CPU_TEST14_BP0

C7
C3

TEST7

K8
C4

TEST8

CPU_TEST29_H_FBCLKOUT_P

C9

CPU_TEST29_L_FBCLKOUT_N

C8

H18
H19
AA7
D5
C5

HDT Connector

JP3

1
3
5
7
9
11
13
15
17
19
21

SAMTEC_ASP-68200-07

@

9/20 SP020016900

Compal Secret Data

Deciphered Date

CPU_SVC <43>
CPU_SVD <43>

T42PAD
T43PAD

VDD_NB_FB_H <43>
VDD_NB_FB_L <43>

2
4
6

8
10
12
14
16
18
20
22
2423
26

D

+1.8V

R17

300_0402_5%@

1 2

R10 10K_0402_5%

1 2

R5 300_0402_5%

CPU_THERMTRIP#_R

12

+1.8V

09/11 update

B

2

Q3

E

3 1

+1.8V

C

R11 10K_0402_5%@

1 2

R9 300_0402_5%

CPU_PROCHOT#_1.8

MMBT3904_NL_SOT23-3

+1.8V sense no support

route as differential

T5PAD

as short as possible

T6PAD

testpoint under package

T7PAD
T8PAD
T10PAD
T12PAD

T13PAD
T14PAD

CPU_TEST27_SINGLECHAIN

CPU_TEST21_SCANEN
CPU_TEST20_SCANCLK2
CPU_TEST24_SCANCLK1
CPU_TEST22_SCANSHIFTEN
CPU_TEST12_SCANSHIFTENB
CPU_TEST15_BP1
CPU_TEST14_BP0
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1

+3VS

5

HDT_RST#

D

U1

4

Y

LDT_RST#

2

P

B

1

A

G

NC7SZ08P5X_NL_SC70-5@

3

Title

Size Document Number Rev

Custom

Date: Sheet

E

MMBT3904_NL_SOT23-3@

CPU_SVC
CPU_SVD

E

3 1

11/13 update

ENTRIP2 <37,39>
H_THERMTRIP#_EC <33>
H_THERMTRIP# <20>

B

2

Q2

C

R22 1K_0402_5%

1 2
1 2

R23 1K_0402_5%

H_PROCHOT# <19>

R6 0_0402_5%@

1 2
1 2

R16 0_0402_5%

1 2

R7 0_0402_5%

12

0718 AMD --> 1K ohm

VDD_NB_FB_H
VDD_NB_FB_L

R484 10_0402_5%

1 2
1 2

R485 10_0402_5%

Close to CPU

R24 300_0402_5%@

1 2

09/11 update

R26 300_0402_5%@

1 2

R27 300_0402_5%@
R28 300_0402_5%@
R29 300_0402_5%@
R31 300_0402_5%@
R32 300_0402_5%@
R33 300_0402_5%@
R34 300_0402_5%@
R35 300_0402_5%@

SB_PWRGD <20,33,43>

12
12
12
12
12
12
12
12

Compal Electronics, Inc.

AMD CPU S1G2 CTRL

LA-4111P

647Thursday, No vember 15, 2007

E

+1.8V

+CPU_CORE_NB

+1.8V

0.2

of

A

[e-mail]

B

C

D

E

18A/720mil/36vias

VDD(+CPU_CORE) decoupling.

+CPU_CORE_0

1

+

1 1

C30
330U_X_2VM_R6M

2

1

+

C28
330U_X_2VM_R6M

2

Near CPU Socket

+CPU_CORE_0

1

C32
22U_0805_6.3V6M

2

+CPU_CORE_0

1

C40

0.22U_0603_16V4Z

2

2 2

1

C33
22U_0805_6.3V6M

2

1

C41

0.01U_0402_25V4Z

2

1

C34
22U_0805_6.3V6M

2

1

2

C42
180P_0402_50V8J

1

C35
22U_0805_6.3V6M

2

Under CPU Socket

+CPU_CORE_1

+CPU_CORE_1

1

C36
22U_0805_6.3V6M

2

1

+

C31
330U_X_2VM_R6M

2

+CPU_CORE_1

1

C37
22U_0805_6.3V6M

2

1

C43

0.22U_0603_16V4Z

2

1

+

C29
330U_X_2VM_R6M

2

1

C38
22U_0805_6.3V6M

2

1

C44

0.01U_0402_25V4Z

2

1

C39
22U_0805_6.3V6M

2

1

C45
180P_0402_50V8J

2

L

?A/?mil/?vias

L

L

+CPU_CORE_NB

+1.8V

?A/?mil/?vias

JCPUE

G4

VDD0_1

H2

VDD0_2

J9

VDD0_3

J11

VDD0_4

J13

VDD0_5

J15

VDD0_6

K6

VDD0_7

K10

VDD0_8

K12

VDD0_9

K14

VDD0_10

L4

VDD0_11

L7

VDD0_12

L9

VDD0_13

L11

VDD0_14

L13

VDD0_15

L15

VDD0_16

M2

VDD0_17

M6

VDD0_18

M8

VDD0_19

M10

VDD0_20

N7

VDD0_21

N9

VDD0_22

N11

VDD0_23

K16

VDDNB_1

M16

VDDNB_2

P16

VDDNB_3

T16

VDDNB_4

V16

VDDNB_5

H25

VDDIO1

J17

VDDIO2

K18

VDDIO3

K21

VDDIO4

K23

VDDIO5

K25

VDDIO6

L17

VDDIO7

M18

VDDIO8

M21

VDDIO9

M23

VDDIO10

M25

VDDIO11

N17

VDDIO12

FOX_PZ6382A-284S-41F_GRIFFIN

Athlon 64 S1
Processor Socket

CONN@

VDD1_1
VDD1_2
VDD1_3
VDD1_4
VDD1_5
VDD1_6
VDD1_7
VDD1_8

VDD1_9
VDD1_10
VDD1_11
VDD1_12
VDD1_13
VDD1_14
VDD1_15
VDD1_16
VDD1_17
VDD1_18
VDD1_19
VDD1_20
VDD1_21
VDD1_22
VDD1_23
VDD1_24
VDD1_25
VDD1_26

VDDIO27
VDDIO26
VDDIO25
VDDIO24
VDDIO23
VDDIO22
VDDIO21
VDDIO20
VDDIO19
VDDIO18
VDDIO17
VDDIO16
VDDIO15
VDDIO14
VDDIO13

18A/720mil/36vias

L

+CPU_CORE_1+CPU_CORE_0

P8
P10
R4
R7
R9
R11
T2
T6
T8
T10
T12
T14
U7
U9
U11
U13
U15
V6
V8
V10
V12
V14
W4
Y2
AC4
AD2

Y25
V25
V23
V21
V18
U17
T25
T23
T21
T18
R17
P25
P23
P21
P18

+1.8V

+CPU_CORE_NB decoupling.

VDDIO decoupling.

+1.8V

1

C46
22U_0805_6.3V6M

2

3 3

+1.8V

1

C55

0.22U_0603_16V4Z

2

+1.8V +1.8V

1

C60

0.01U_0402_25V4Z

2

4 4

+1.8V

1

C74

4.7U_0805_10V4Z

2

1

C47
22U_0805_6.3V6M

2

Under CPU Socket

Between CPU Socket and DIMM

1

C56

0.22U_0603_16V4Z

2

1

C61

0.01U_0402_25V4Z

2

1

C75

4.7U_0805_10V4Z

2

A

1

C48

0.22U_0603_16V4Z

2

1

C57

0.22U_0603_16V4Z

2

1

2

1

2

1

C49

0.22U_0603_16V4Z

2

1

2

180PF Qt'y follow the distance between
CPU socket and DIMM0. <2.5inch>

C62
180P_0402_50V8J

C76

4.7U_0805_10V4Z

1

2

1

C50

180P_0402_50V8J

2

C58

0.22U_0603_16V4Z

1

C63
180P_0402_50V8J

2

A: Add C165 and C176
to follow AMD Layout
review recommand for
EMI

C77

4.7U_0805_10V4Z

1

2

1

C64
180P_0402_50V8J

2

1

C: Change to NBO CAP

+

C78
220U_Y_4VM

@

2

B

C51
180P_0402_50V8J

1

C65
180P_0402_50V8J

2

+CPU_CORE_NB

1

C52
22U_0805_6.3V6M

2

VTT decoupling.

+0.9V

1

C66

4.7U_0805_10V4Z

2

+0.9V

1

C79

4.7U_0805_10V4Z

2

Security Classification

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Near CPU Socket Right side.

Near CPU Socket Left side.

Issued Date

1

C67

4.7U_0805_10V4Z

2

1

C80

4.7U_0805_10V4Z

2

C

1

C53
22U_0805_6.3V6M

2

2007/08/02 2008/08/02

1

2

1

C68

0.22U_0603_16V4Z

2

1

C81

0.22U_0603_16V4Z

2

C54
22U_0805_6.3V6M

+0.9V

Near Power Supply

1

C: Change to NBO CAP

+

C59
220U_Y_4VM

2

1

C69

0.22U_0603_16V4Z

2

1

C82

0.22U_0603_16V4Z

2

Compal Secret Data

Deciphered Date

1

C70
1000P_0402_25V8J

2

1

C83
1000P_0402_25V8J

2

D

1

C71
1000P_0402_25V8J

2

1

C84
1000P_0402_25V8J

2

1

C72
180P_0402_50V8J

2

1

C85
180P_0402_50V8J

2

Title

Size Document Number Rev

Custom

Date: Sheet

JCPUF

AA4

VSS1

AA11

VSS2

AA13

VSS3

AA15

VSS4

AA17

VSS5

AA19

VSS6

AB2

VSS7

AB7

VSS8

AB9

VSS9

AB23

VSS10

AB25

VSS11

AC11

VSS12

AC13

VSS13

AC15

VSS14

AC17

VSS15

AC19

VSS16

AC21

VSS17

AD6

VSS18

AD8

VSS19

AD25

VSS20

AE11

VSS21

AE13

VSS22

AE15

VSS23

AE17

VSS24

AE19

VSS25

AE21

VSS26

AE23

VSS27

B4

VSS28

B6

VSS29

B8

VSS30

B9

VSS31

B11

VSS32

B13

VSS33

B15

VSS34

B17

VSS35

B19

VSS36

B21

VSS37

B23

VSS38

B25

VSS39

D6

VSS40

D8

VSS41

D9

VSS42

D11

VSS43

D13

VSS44

D15

VSS45

D17

VSS46

D19

VSS47

D21

VSS48

D23

VSS49

D25

VSS50

E4

VSS51

F2

VSS52

F11

VSS53

F13

VSS54

F15

VSS55

F17

VSS56

F19

VSS57

F21

VSS58

F23

VSS59

F25

VSS60

H7

VSS61

H9

VSS62

H21

VSS63

H23

VSS64

J4

VSS65

FOX_PZ6382A-284S-41F_GRIFFIN

Athlon 64 S1
Processor Socket

CONN@

1

C73
180P_0402_50V8J

2

1

C86
180P_0402_50V8J

2

VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129

J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
AC6
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6

Compal Electronics, Inc.

AMD CPU S1G2 PWR & GND

LA-4111P

747Thursday, No vember 15, 2007

E

of

0.2

A

DDR_A_D0
DDR_A_D1

1 1

2 2

DDR_CKE0_DIMMA<5>

DDR_A_BS#2<5>

DDR_A_BS#0<5>
DDR_A_WE#<5>

DDR_A_CAS#<5>
DDR_CS1_DIMMA#<5>

DDR_A_ODT1<5>

3 3

SMB_CK_DAT0<9,15,20,30>
SMB_CK_CLK0<9,15,20,30>

4 4

A

+3VS

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D9

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D16 DDR_A_D20
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS#2
DDR_A_MA12

DDR_A_MA9
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1 DDR_A_MA0

DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

DDR_A_CAS# DDR_A_ODT0
DDR_CS1_DIMMA#

DDR_A_ODT1
DDR_A_D32

DDR_A_D33
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D34

DDR_A_D35
DDR_A_D40

DDR_A_D41
DDR_A_DM5
DDR_A_D42

DDR_A_D43
DDR_A_D48

DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_DM7
DDR_A_D58

DDR_A_D59

1

C103

0.1U_0402_16V4Z

2

B

+V_DDR_MCH_REF

JP4

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

FOX_AS0A426-N8RN-7F

CONN@

9/20 SP07000BZ00/SP07000EU00
DDR2 SOCKET H9.2 (REV)

B

DQ12
DQ13

CK0#

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3
DQ30

DQ31

NC/CKE1

NC/A15
NC/A14

RAS#

ODT0

NC/A13

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5
DQ46

DQ47
DQ52

DQ53

CK1#

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7
DQ62

DQ63

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS

VSS
DM1
VSS
CK0

VSS

VSS

VSS

VSS
DM2

VSS

VSS

VSS

VSS

VSS
VDD

VDD

VDD

VDD
BA1

VDD

VDD
VSS

VSS
DM4
VSS

VSS

VSS

VSS

VSS

VSS
CK1

VSS
DM6
VSS

VSS

VSS

VSS

VSS
SA0
SA1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90

A11

92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110

S0#

112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

+1.8V+1.8V

C

DDR_A_D4
DDR_A_D5

DDR_A_DM0
DDR_A_D6

DDR_A_D7
DDR_A_D12

DDR_A_D13
DDR_A_DM1

DDR_A_D14
DDR_A_D15

DDR_A_D21

DDR_A_DM2
DDR_A_D22

DDR_A_D23
DDR_A_D28

DDR_A_D29
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D30

DDR_A_D31
DDR_CKE1_DIMMA
DDR_A_MA15

DDR_A_MA14
DDR_A_MA11

DDR_A_MA7
DDR_A_MA6

DDR_A_MA4
DDR_A_MA2

DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#

DDR_A_MA13

DDR_A_D36
DDR_A_D37

DDR_A_DM4
DDR_A_D38

DDR_A_D39
DDR_A_D44

DDR_A_D45
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D46

DDR_A_D47
DDR_A_D52

DDR_A_D53

DDR_A_DM6
DDR_A_D54

DDR_A_D55
DDR_A_D60

DDR_A_D61
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62

DDR_A_D63

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DDR_A_D[0..63]

DDR_A_DM[0..7]

DDR_A_DQS[0..7]

DDR_A_MA[0..15]

DDR_A_DQS#[0..7]

DDR_A_CLK0 <5>
DDR_A_CLK#0 <5>

+V_DDR_MCH_REF

1

C95

2

1000P_0402_25V8J

0.1U_0402_16V4Z

DDR_CKE1_DIMMA <5>

DDR_A_BS#1 <5>
DDR_A_RAS# <5>
DDR_CS0_DIMMA# <5>

DDR_A_ODT0 <5>

DDR_A_CLK1 <5>
DDR_A_CLK#1 <5>

C

DDR_A_D[0..63] <5>
DDR_A_DM[0..7] <5>

DDR_A_DQS[0..7] <5>

DDR_A_MA[0..15] <5>

DDR_A_DQS#[0..7] <5>

+1.8V

R43
1K_0402_1%

1 2

R44
1K_0402_1%

1 2

+V_DDR_MCH_REF <9>

1

C96

2

09/13 update

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

D

+0.9V

DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6

DDR_CKE0_DIMMA
DDR_A_BS#2
DDR_CKE1_DIMMA
DDR_A_MA15

DDR_A_MA4
DDR_A_MA2
DDR_A_BS#1
DDR_A_MA0

DDR_A_MA5
DDR_A_MA8
DDR_A_MA9
DDR_A_MA12

DDR_A_BS#0
DDR_A_MA10
DDR_A_MA1
DDR_A_MA3

DDR_A_ODT1
DDR_CS1_DIMMA#
DDR_A_WE#
DDR_A_CAS#

DDR_CS0_DIMMA#
DDR_A_RAS#
DDR_A_MA13
DDR_A_ODT0

D

RP1

18
27
36

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

Cross between +1.8V and +0.9V power plan

Title

Size Document Number Rev

Custom

Date: Sheet

45

RP2

18
27
36
45

RP3

18
27
36
45

RP4

18
27
36
45

RP5

18
27
36
45

RP6

18
27
36
45

RP7

18
27
36
45

Compal Electronics, Inc.

DDRII SO-DIMM 0

LA-4111P

E

1 2

C87 0.1U_0402_16V4Z

1 2

C88 0.1U_0402_16V4Z

1 2

C90 0.1U_0402_16V4Z

1 2

C89 0.1U_0402_16V4Z

1 2

C91 0.1U_0402_16V4Z

1 2

C92 0.1U_0402_16V4Z

1 2

C93 0.1U_0402_16V4Z

1 2

C94 0.1U_0402_16V4Z

1 2

C98 0.1U_0402_16V4Z

1 2

C97 0.1U_0402_16V4Z

1 2

C100 0.1U_0402_16V4Z

1 2

C99 0.1U_0402_16V4Z

1 2

C102 0.1U_0402_16V4Z

1 2

C101 0.1U_0402_16V4Z

E

+1.8V

0.2

of

847Thursday, No vember 15, 2007

A

[e-mail]

B

C

D

E

JP5

+V_DDR_MCH_REF<8>

1

C104

1 1

2 2

3 3

4 4

1000P_0402_25V8J

DDR_CKE0_DIMMB<5>

DDR_B_BS#2<5>

DDR_B_BS#0<5>
DDR_B_WE#<5>

DDR_B_CAS#<5>
DDR_CS1_DIMMB#<5>

DDR_B_ODT1<5>

SMB_CK_DAT0<8,15,20,30>
SMB_CK_CLK0<8,15,20,30>

2

DDR_B_D0
DDR_B_D1

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D13

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D21
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18 DDR_B_D22
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_DM3

DDR_B_D26
DDR_B_D27

DDR_CKE0_DIMMB

DDR_B_BS#2
DDR_B_MA12

DDR_B_MA9

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#

DDR_B_CAS# DDR_B_ODT0
DDR_CS1_DIMMB#

DDR_B_ODT1
DDR_B_D32

DDR_B_D33
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D34

DDR_B_D35
DDR_B_D40

DDR_B_D41
DDR_B_DM5
DDR_B_D42

DDR_B_D43 DDR_B_D47
DDR_B_D48

DDR_B_D49 DDR_B_D53

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51 DDR_B_D55

DDR_B_D56
DDR_B_D57

DDR_B_DM7
DDR_B_D58

DDR_B_D59

+3VS

0.1U_0402_16V4Z

C119

1

2

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

201

GND

TYCO_292527-4

CONN@

VSS
DQ4
DQ5

VSS
DM0
VSS
DQ6
DQ7
VSS

DQ12
DQ13

VSS
DM1
VSS

CK0

CK0#

VSS

DQ14
DQ15

VSS

VSS

DQ20
DQ21

VSS
DM2

VSS

DQ22
DQ23

VSS

DQ28
DQ29

VSS

DQS3#

DQS3

VSS

DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

A11

VDD

VDD

BA1

RAS#

S0#
VDD

ODT0

NC/A13

VDD
VSS

DQ36
DQ37

VSS
DM4
VSS

DQ38
DQ39

VSS

DQ44
DQ45

VSS

DQS5#

DQS5

VSS

DQ46
DQ47

VSS

DQ52
DQ53

VSS

CK1

CK1#

VSS
DM6
VSS

DQ54
DQ55

VSS

DQ60
DQ61

VSS

DQS7#

DQS7

VSS

DQ62
DQ63

VSS
SAO

SA1
GND

NC

A7
A6

A4
A2
A0

NC

9/20 SP07000ET00/SP07000GN00

+1.8V+1.8V

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202

DDR_B_D4
DDR_B_D5

DDR_B_DM0
DDR_B_D6

DDR_B_D7
DDR_B_D12

DDR_B_D9
DDR_B_DM1

DDR_B_D14
DDR_B_D15

DDR_B_D20
DDR_B_D16

DDR_B_DM2

DDR_B_D23
DDR_B_D28

DDR_B_D29
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D30

DDR_B_D31
DDR_CKE1_DIMMB
DDR_B_MA15

DDR_B_MA14
DDR_B_MA11

DDR_B_MA7
DDR_B_MA6DDR_B_MA8

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS#1
DDR_B_RAS#
DDR_CS0_DIMMB#

DDR_B_MA13

DDR_B_D36
DDR_B_D37

DDR_B_DM4
DDR_B_D38

DDR_B_D39
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D52

DDR_B_DM6
DDR_B_D54

DDR_B_D60
DDR_B_D61

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D62
DDR_B_D63

+3VS

DDR_B_D[0..63]

DDR_B_DM[0..7]

DDR_B_DQS[0..7]

DDR_B_MA[0..15]

DDR_B_DQS#[0..7]

DDR_B_CLK0 <5>
DDR_B_CLK#0 <5>

DDR_CKE1_DIMMB <5>

DDR_B_BS#1 <5>
DDR_B_RAS# <5>
DDR_CS0_DIMMB# <5>

DDR_B_ODT0 <5>

DDR_B_CLK1 <5>
DDR_B_CLK#1 <5>

DDR_B_D[0..63] <5>

DDR_B_DM[0..7] <5>

DDR_B_DQS[0..7] <5>

DDR_B_MA[0..15] <5>

DDR_B_DQS#[0..7] <5>

DDR_B_MA6
DDR_B_MA2
DDR_B_MA0
DDR_CS0_DIMMB#

DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA4

DDR_B_BS#2
DDR_CKE0_DIMMB
DDR_B_MA15
DDR_CKE1_DIMMB

DDR_B_MA5
DDR_B_MA8
DDR_B_MA9
DDR_B_MA12

DDR_B_MA10
DDR_B_BS#0
DDR_B_MA1
DDR_B_MA3

DDR_B_ODT1
DDR_CS1_DIMMB#
DDR_B_CAS#
DDR_B_WE#

DDR_B_RAS#
DDR_B_BS#1
DDR_B_ODT0
DDR_B_MA13

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

Cross between +1.8V and +0.9V power plan

09/26 update
DDR_B_D21 swap with DDR_B_D16

DDR_B_D13 swap with DDR_B_D9

RP8

RP9

RP10

RP11

RP12

RP13

RP14

+0.9V

18

C105 0.1U_0402_16V4Z

27

1 2

36

C106 0.1U_0402_16V4Z

45

18

C108 0.1U_0402_16V4Z

27
36

1 2

C107 0.1U_0402_16V4Z

45

18

C109 0.1U_0402_16V4Z

27
36

1 2

C110 0.1U_0402_16V4Z

45

18

C111 0.1U_0402_16V4Z

27
36

1 2

C112 0.1U_0402_16V4Z

45

18

C114 0.1U_0402_16V4Z

27

1 2

36

C113 0.1U_0402_16V4Z

45

18

C116 0.1U_0402_16V4Z

27
36

1 2

C115 0.1U_0402_16V4Z

45

18

C118 0.1U_0402_16V4Z

27
36

1 2

C117 0.1U_0402_16V4Z

45

12

12

12

12

12

12

12

+1.8V

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

DDRII SO-DIMM 1

LA-4111P

947Thursday, No vember 15, 2007

E

0.2

of

A

U3B

D4

GFX_RX0P

C4

GFX_RX0N

A3

GFX_RX1P

B3

GFX_RX1N

C2

GFX_RX2P

C1

GFX_RX2N

E5

GFX_RX3P

F5

GFX_RX3N

G5

GFX_RX4P

G6

AE3
AD4
AE2
AD3
AD1
AD2

W6

AA8
AA7
AA5

AA6

W5

H5
H6

J6
J5
J7
J8
L5
L6

M8

L8
P7

M7

P5
M5
R8

P8
R6
R5

P4

P3

T4

T3

V5
U5

U6
U8
U7

Y8

Y7

Y5

GFX_RX4N
GFX_RX5P
GFX_RX5N
GFX_RX6P
GFX_RX6N
GFX_RX7P
GFX_RX7N
GFX_RX8P
GFX_RX8N
GFX_RX9P
GFX_RX9N
GFX_RX10P
GFX_RX10N
GFX_RX11P
GFX_RX11N
GFX_RX12P
GFX_RX12N
GFX_RX13P
GFX_RX13N
GFX_RX14P
GFX_RX14N
GFX_RX15P
GFX_RX15N

GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
GPP_RX4P
GPP_RX4N
GPP_RX5P
GPP_RX5N

SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N

1 1

PCIE_PTX_C_IRX_P0<26>
PCIE_PTX_C_IRX_N0<26>
PCIE_PTX_C_IRX_P1<27>
PCIE_PTX_C_IRX_N1<27>
PCIE_PTX_C_IRX_P2<26>
PCIE_PTX_C_IRX_N2<26>
PCIE_PTX_C_IRX_P3<25>

2 2

PCIE_PTX_C_IRX_N3<25>

PCIE_PTX_C_IRX_P5<26>
PCIE_PTX_C_IRX_N5<26>

SB_RX0P<19>
SB_RX0N<19>
SB_RX1P<19>
SB_RX1N<19>
SB_RX2P<19>
SB_RX2N<19>
SB_RX3P<19>
SB_RX3N<19>

RS780M_FCBGA528

PART 2 OF 6

PCIE I/F GFX

PCIE I/F GPP

PCIE I/F SB

PCE_CALRP(PCE_BCALRP)

PCE_CALRN(PCE_BCALRN)

RS780M Display Port Support (muxed on GFX)

DP0

DP1

3 3

9/20 SA00001ZG00(A11) S IC 216-0674001-00/RS780M FCBGA528P 0FH

GFX_TX0,TX1,TX2 and TX3
AUX0 and HPD0

GFX_TX4,TX5,TX6 and TX7
AUX1 and HPD1

UMA@

B

GFX_TX0P

GFX_TX0N

GFX_TX1P

GFX_TX1N

GFX_TX2P

GFX_TX2N

GFX_TX3P

GFX_TX3N

GFX_TX4P

GFX_TX4N

GFX_TX5P

GFX_TX5N

GFX_TX6P

GFX_TX6N

GFX_TX7P

GFX_TX7N

GFX_TX8P

GFX_TX8N

GFX_TX9P

GFX_TX9N

GFX_TX10P

GFX_TX10N

GFX_TX11P

GFX_TX11N

GFX_TX12P

GFX_TX12N

GFX_TX13P

GFX_TX13N

GFX_TX14P

GFX_TX14N

GFX_TX15P

GFX_TX15N

GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_TX4P
GPP_TX4N
GPP_TX5P
GPP_TX5N

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

A5
B5
A4
B4
C3
B2
D1
D2
E2
E1
F4
F3
F1
F2
H4
H3
H1
H2
J2
J1
K4
K3
K1
K2
M4
M3
M1
M2
N2
N1
P1
P2

PCIE_ITX_PRX_P0

AC1

PCIE_ITX_PRX_N0

AC2

PCIE_ITX_PRX_P1

AB4

PCIE_ITX_PRX_N1

AB3

PCIE_ITX_PRX_P2

AA2

PCIE_ITX_PRX_N2

AA1

PCIE_ITX_PRX_P3

Y1

PCIE_ITX_PRX_N3

Y2
Y4
Y3

PCIE_ITX_PRX_P5

V1

PCIE_ITX_PRX_N5

V2

SB_TX0P_C

AD7

SB_TX0N_C

AE7

SB_TX1P_C

AE6

SB_TX1N_C

AD6

SB_TX2P_C

AB6

SB_TX2N_C

AC6

SB_TX3P_C

AD5

SB_TX3N_C

AE5
AC8

AB8

TMDS_B_DATA2 <18>
TMDS_B_DATA2# <18>
TMDS_B_DATA1 <18>
TMDS_B_DATA1# <18>
TMDS_B_DATA0 <18>
TMDS_B_DATA0# <18>
TMDS_B_CLK <18>
TMDS_B_CLK# <18>

C152 0.1U_0402_16V7K
C153 0.1U_0402_16V7K
C154 0.1U_0402_16V7K
C155 0.1U_0402_16V7K
C156 0.1U_0402_16V7K
C157 0.1U_0402_16V7K
C158 0.1U_0402_16V7K
C159 0.1U_0402_16V7K

C160 0.1U_0402_16V7K
C161 0.1U_0402_16V7K

C162 0.1U_0402_16V7K
C163 0.1U_0402_16V7K
C164 0.1U_0402_16V7K
C165 0.1U_0402_16V7K
C166 0.1U_0402_16V7K
C168 0.1U_0402_16V7K
C169 0.1U_0402_16V7K
C167 0.1U_0402_16V7K

R55 1.27K_0402_1%

1 2

R56 2K_0402_1%

1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

+1.1VS

C

PCIE_ITX_C_PRX_P0 <26>
PCIE_ITX_C_PRX_N0 <26>
PCIE_ITX_C_PRX_P1 <27>
PCIE_ITX_C_PRX_N1 <27>
PCIE_ITX_C_PRX_P2 <26>
PCIE_ITX_C_PRX_N2 <26>
PCIE_ITX_C_PRX_P3 <25>
PCIE_ITX_C_PRX_N3 <25>

PCIE_ITX_C_PRX_P5 <26>
PCIE_ITX_C_PRX_N5 <26>

SB_TX0P <19>
SB_TX0N <19>
SB_TX1P <19>
SB_TX1N <19>
SB_TX2P <19>
SB_TX2N <19>
SB_TX3P <19>
SB_TX3N <19>

New Card
CardReader

WLAN
LAN10/100

TV Tuner

H_CLKOP0<4>
H_CLKON0<4>
H_CLKOP1<4>
H_CLKON1<4>

H_CTLOP0<4>
H_CTLON0<4>

H_CTLON1<4>

0718 Place within 1"
layout 1:2

H_CADOP[0..15]<4>
H_CADON[0..15]<4> H_CADIN[0..15] <4>

H_CADOP10
H_CADON10
H_CADOP11
H_CADON11
H_CADOP12
H_CADON12
H_CADOP13
H_CADON13
H_CADOP14
H_CADON14
H_CADOP15
H_CADON15

H_CTLOP0
H_CTLON0
H_CTLOP1
H_CTLON1

R57 301_0402_1%

1 2

H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADOP2
H_CADON2
H_CADOP3
H_CADON3
H_CADOP4
H_CADON4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7

H_CADOP8
H_CADON8
H_CADOP9
H_CADON9

D

Y25
Y24
V22
V23
V25
V24
U24
U25
T25
T24
P22
P23
P25
P24
N24
N25

AC24
AC25
AB25
AB24
AA24
AA25

Y22

Y23
W21
W20

V21

V20

U20

U21

U19

U18

T22

T23

AB23
AA22

M22
M23

R21

R20

C23

A24

H_CADON[0..15]

U3A

HT_RXCAD0P
HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD7P
HT_RXCAD7N

HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD15P
HT_RXCAD15N

HT_RXCLK0P
HT_RXCLK0N
HT_RXCLK1P
HT_RXCLK1N

HT_RXCTL0P
HT_RXCTL0N
HT_RXCTL1P
HT_RXCTL1N

HT_RXCALP
HT_RXCALN

RS780M_FCBGA528

UMA@

PART 1 OF 6

HYPER TRANSPORT CPU I/F

H_CADIP[0..15]H_CADOP[0..15]
H_CADIN[0..15]

HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N

HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P

HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N

HT_TXCLK0P

HT_TXCLK0N

HT_TXCLK1P

HT_TXCLK1N

HT_TXCTL0P

HT_TXCTL0N

HT_TXCTL1P

HT_TXCTL1N

HT_TXCALP
HT_TXCALN

E

H_CADIP[0..15] <4>

H_CADIP0

D24

H_CADIN0

D25

H_CADIP1

E24

H_CADIN1

E25

H_CADIP2

F24

H_CADIN2

F25

H_CADIP3

F23

H_CADIN3

F22

H_CADIP4

H23

H_CADIN4

H22

H_CADIP5

J25

H_CADIN5

J24

H_CADIP6

K24

H_CADIN6

K25

H_CADIP7

K23

H_CADIN7

K22

H_CADIP8

F21

H_CADIN8

G21

H_CADIP9

G20

H_CADIN9

H21

H_CADIP10

J20

H_CADIN10

J21

H_CADIP11

J18

H_CADIN11

K17

H_CADIP12

L19

H_CADIN12

J19

H_CADIP13

M19

H_CADIN13

L18

H_CADIP14

M21

H_CADIN14

P21

H_CADIP15

P18

H_CADIN15

M18
H24

H25
L21
L20

H_CTLIP0

M24

H_CTLIN0

M25

H_CTLIP1

P19

H_CTLIN1

R18
B24

B25

0718 Place within 1"
layout 1:2

H_CLKIP0 <4>
H_CLKIN0 <4>
H_CLKIP1 <4>
H_CLKIN1 <4>

H_CTLIP0 <4>

H_CTLIN0 <4>

H_CTLIP1 <4>H_CTLOP1<4>

H_CTLIN1 <4>

R58 301_0402_1%

1 2

NEED CHECK R68 & R69 WITH AMD

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

RS780-HT/PCIE

LA-4111P

10 47Thursday, No vember 15, 2007

E

0.2

of

A

[e-mail]

1 1

11/13 update

LDT_STOP#<6,19>

CPU_LDT_REQ#<6,19>

2 2

Install when SB700 A12 use

L

3 3

R67

1 2

0_0402_5%

R68

1 2

0_0402_5%

+1.8VS

BLM18PG121SN1D_0603

+1.8VS

1 2

BLM18PG121SN1D_0603

2.2U_0603_6.3V4Z

+1.1VS

NB_LDTSTOP#

NB_ALLOW_LDTSTOP

+1.1VS

+1.8VS

BLM18PG121SN1D_0603

L10

1 2

L11

1

C180

2

1 2

R71

4.7K_0402_5%

1 2

R62 150_0402_1%

1 2

R63 150_0402_1%

1 2

R64 150_0402_1%

1 2

BLM18PG121SN1D_0603

L7

1 2

C176

2.2U_0603_6.3V4Z

1

C179

2.2U_0603_6.3V4Z

2

11/13 update

1 2

R72

4.7K_0402_5%

+1.8VS

L9

1

2

B

+1.8VS

L6

1 2

BLM18PG121SN1D_0603

2.2U_0603_6.3V4Z

RED

GREEN

BLUE

1

C178

2.2U_0603_6.3V4Z

2

+NB_PLLVDD
+NB_HTPVDD

+VDDA18HTPLL
+VDDA18PCIEPLL

PLT_RST#<14,19,25,26,27,32,33>

NB_PWRGD<20>

+1.8VS

CLK_NBHT<15>
CLK_NBHT#<15>

NB_OSC_14.318M<15>

NBGFX_CLK<15>
NBGFX_CLK#<15>

CLK_SBLINK_BCLK<15>
CLK_SBLINK_BCLK#<15>

LCD_DDC_CLK<17>

LCD_DDC_DAT<17>
HDMIDAT_UMA<18>
HDMICLK_UMA<18>

+3VS

1 2

BLM18PG121SN1D_0603

L4

0_0603_5%

+AVDDQ

1

C175

2

T46 PAD
T47 PAD
T48 PAD

11/05 update

RED<16>
GREEN<16>
BLUE<16>

CRT_HSYNC<14,16>

CRT_VSYNC<14,16>
UMA_CRT_CLK<16>
UMA_CRT_DAT<16>

R65 715_0402_1%

R66 0_0402_5%

1 2

1 2

R371 10K_0402_5%

RS780_DFT_GPIO_0<14>

+3VS

L2

+AVDD1

+AVDD2

1

C172

2.2U_0603_6.3V4Z

2

RED
GREEN
BLUE

1 2

NB_RESET#
NB_PWRGD
NB_LDTSTOP#

NB_ALLOW_LDTSTOP

Strap pin

R88 10K_0402_5%

AUX_CAL<14>

Strap pin

AVDD=100mA

1

2

TV_CRMA
TV_LUMA
TV_COMPS

CRT_HSYNC
CRT_VSYNC

12

C170

2.2U_0603_6.3V4Z

U3C

F12

AVDD1(NC)

E12

AVDD2(NC)

F14

AVDDDI(NC)

G15

AVSSDI(NC)

H15

AVDDQ(NC)

H14

AVSSQ(NC)

E17

C_Pr(DFT_GPIO5)

F17

Y(DFT_GPIO2)

F15

COMP_Pb(DFT_GPIO4)

G18

RED(DFT_GPIO0)

G17

REDb(NC)

E18

GREEN(DFT_GPIO1)

F18

GREENb(NC)

E19

BLUE(DFT_GPIO3)

F19

BLUEb(NC)

A11

DAC_HSYNC(PWM_GPIO4)

B11

DAC_VSYNC(PWM_GPIO6)

F8

DAC_SCL(PCE_RCALRN)

E8

DAC_SDA(PCE_TCALRN)

G14

DAC_RSET(PWM_GPIO1)

A12

PLLVDD(NC)

D14

PLLVDD18(NC)

B12

PLLVSS(NC)

H17

VDDA18HTPLL

D7

VDDA18PCIEPLL1

E7

VDDA18PCIEPLL2

D8

SYSRESETb

A10

POWERGOOD

C10

LDTSTOPb

C12

ALLOW_LDTSTOP

C25

HT_REFCLKP

C24

HT_REFCLKN

E11

REFCLK_P/OSCIN(OSCIN)

F11

REFCLK_N(PWM_GPIO3)

T2

GFX_REFCLKP

T1

GFX_REFCLKN

U1

GPP_REFCLKP

U2

GPP_REFCLKN

V4

GPPSB_REFCLKP(SB_REFCLKP)

V3

GPPSB_REFCLKN(SB_REFCLKN)

B9

I2C_CLK

A9

I2C_DATA

B8

DDC_DATA0/AUX0N(NC)

A8

DDC_CLK0/AUX0P(NC)

B7

DDC_CLK1/AUX1P(NC)

A7

DDC_DATA1/AUX1N(NC)

B10

STRP_DATA

G11

RSVD

C8

AUX_CAL(NC)

RS780M_FCBGA528

UMA@

C

PART 3 OF 6

TXOUT_U1P(PCIE_RESET_GPIO3)

TXOUT_U1N(PCIE_RESET_GPIO2)

TXOUT_U3P(PCIE_RESET_GPIO5)

CRT/TVOUT

TXCLK_UP(PCIE_RESET_GPIO4)

TXCLK_UN(PCIE_RESET_GPIO1)

LVTM

PM

TXOUT_L0P(NC)

TXOUT_L0N(NC)

TXOUT_L1P(NC)

TXOUT_L1N(NC)

TXOUT_L2P(NC)

TXOUT_L2N(DBG_GPIO0)

TXOUT_L3P(NC)

TXOUT_L3N(DBG_GPIO2)

TXOUT_U0P(NC)
TXOUT_U0N(NC)

TXOUT_U2P(NC)
TXOUT_U2N(NC)

TXOUT_U3N(NC)

TXCLK_LP(DBG_GPIO1)
TXCLK_LN(DBG_GPIO3)

VDDLTP18(NC)
VSSLTP18(NC)

VDDLT18_1(NC)
VDDLT18_2(NC)
VDDLT33_1(NC)
VDDLT33_2(NC)

VSSLT1(VSS)
VSSLT2(VSS)
VSSLT3(VSS)
VSSLT4(VSS)
VSSLT5(VSS)
VSSLT6(VSS)
VSSLT7(VSS)

LVDS_DIGON(PCE_TCALRP)

LVDS_BLON(PCE_RCALRP)

LVDS_ENA_BL(PWM_GPIO2)

CLOCKs PLL PWR

A22
B22
A21
B21
B20
A20
A19
B19

B18
A18
A17
B17
D20
D21
D18
D19

B16
A16
D16
D17

A13
B13

A15
B15
A14
B14

C14
D15
C16
C18
C20
E20
C22

E9
F7
G12

0.1U_0402_16V4Z

D

LVDS_A0+ <17>
LVDS_A0- <17>
LVDS_A1+ <17>
LVDS_A1- <17>
LVDS_A2+ <17>
LVDS_A2- <17>

LVDS_B0+ <17>
LVDS_B0- <17>
LVDS_B1+ <17>
LVDS_B1- <17>
LVDS_B2+ <17>
LVDS_B2- <17>

LVDS_ACLK+ <17>
LVDS_ACLK- <17>
LVDS_BCLK+ <17>
LVDS_BCLK- <17>

+VDDLTP18

+VDDLT18

1 2

R69 0_0402_5%

1 2

R70 0_0402_5%

C173

1

2

1

2

L3

1 2

BLM18PG121SN1D_0603

C171

2.2U_0603_6.3V4Z
L5

1 2

BLM18PG121SN1D_0603

1

C174

4.7U_0805_10V4Z

2

0.08A/10mil/1vias

L

E

+1.8VS

+1.8VS

UMA_ENVDD <17>
ENBKL <33>

PA_RS780A4
placement close to NB ball

flash issue check IALAA

MIS.

TMDS_HPD(NC)

SUS_STAT#(PWM_GPIO5)

HPD(NC)

THERMALDIODE_P
THERMALDIODE_N

TESTMODE

D9
D10

D12

NB_THERMAL_DA

AE8

NB_THERMAL_DC

AD8

1 2

D13

R80

1.8K_0402_5%

1 2

R77 0_0402_5%

HPD <18>
SUS_STAT_R# <14>

SUS_STAT# <20>

T49PAD
T50PAD

NB temp to SB

Strap pin

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

RS780 VEDIO/CLK GEN

LA-4111P

11 47Thursday, November 15, 2007

E

0.2

of

A

B

C

D

E

MEM_BA0
MEM_BA1

MEM_A12
MEM_A11

1 1

12

R91

100_0402_1%

SIDE@

2 2

MEM_A10
MEM_A9
MEM_A8
MEM_A7
MEM_A6
MEM_A5
MEM_A4
MEM_A3
MEM_A2 MEM_A12
MEM_A1
MEM_A0

MEM_CLKN
MEM_CLKP

MEM_CKE

MEM_CS#
MEM_WE#
MEM_RAS#
MEM_CAS#
MEM_DM0

MEM_DM1

MEM_ODT

MEM_DQS_P0
MEM_DQS_N0

MEM_DQS_P1
MEM_DQS_N1

+MEM_VREF

MEM_BA2

U61

L2

BA0

L3

BA1

R2

A12

P7

A11

M2

A10/AP

P3

A9

P8

A8

P2

A7

N7

A6

N3

A5

N8

A4

N2

A3

M7

A2

M3

A1

M8

A0

K8

CK

J8

CK

K2

CKE

L8

CS

K3

WE

K7

RAS

L7

CAS

F3

LDM

B3

UDM

K9

ODT

F7

LDQS

E8

LDQS

B7

UDQS

A8

UDQS

J2

VREF

A2

NC

E2

NC

L1

NC

R3

NC

R7

NC

R8

NC

HY5PS561621AFP-25_FBGA84

SIDE@

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VDD
VDD
VDD
VDD
VDD

VDDL

VSSDL

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VSS
VSS
VSS
VSS
VSS

MEM_DQ15

B9

MEM_DQ11

B1

MEM_DQ13 MEM_A1

D9

MEM_DQ12 MEM_A2

D1

MEM_DQ8

D3

MEM_DQ10

D7

MEM_DQ9

C2

MEM_DQ14

C8

MEM_DQ3

F9

MEM_DQ7

F1

MEM_DQ1

H9

MEM_DQ6

H1

MEM_DQ5

H3

MEM_DQ0

H7

MEM_DQ4

G2

MEM_DQ2

G8

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

A1
E1
J9
M9
R1

J1
J7

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

A3
E3
J3
N1
P9

+VDDL

+1.8V_MEM_VDDQ

+1.8V_MEM_VDDQ

L96

1 2

0_0603_5%SIDE@

1

C184

1U_0603_10V6KSIDE@

2

Layout Note: 50 mil for VSSDL

+1.8V_MEM_VDDQ

R92 40.2_0402_1%SIDE@
R93 40.2_0402_1%SIDE@

09/19 update

12
12

MEM_A0

MEM_A3
MEM_A4
MEM_A5
MEM_A6
MEM_A7
MEM_A8
MEM_A9
MEM_A10
MEM_A11

MEM_BA0
MEM_BA1
MEM_BA2

MEM_RAS#
MEM_CAS#
MEM_WE#
MEM_CS#
MEM_CKE
MEM_ODT

MEM_CLKP
MEM_CLKN

MEM_COMP_P
MEM_COMP_N

U3D

AB12

MEM_A0(NC)

AE16

MEM_A1(NC)

V11

MEM_A2(NC)

AE15

MEM_A3(NC)

AA12

MEM_A4(NC)

AB16

MEM_A5(NC)

AB14

MEM_A6(NC)

AD14

MEM_A7(NC)

AD13

MEM_A8(NC)

AD15

MEM_A9(NC)

AC16

MEM_A10(NC)

AE13

MEM_A11(NC)

AC14

MEM_A12(NC)

Y14

MEM_A13(NC)

AD16

MEM_BA0(NC)

AE17

MEM_BA1(NC)

AD17

MEM_BA2(NC)

W12

MEM_RASb(NC)

Y12

MEM_CASb(NC)

AD18

MEM_WEb(NC)

AB13

MEM_CSb(NC)

AB18

MEM_CKE(NC)

V14

MEM_ODT(NC)

V15

MEM_CKP(NC)

W14

MEM_CKN(NC)

AE12

MEM_COMPP(NC)

AD12

MEM_COMPN(NC)

RS780M_FCBGA528

UMA@

PAR 4 OF 6

MEM_DQ0/DVO_VSYNC(NC)
MEM_DQ1/DVO_HSYNC(NC)

MEM_DQ2/DVO_DE(NC)
MEM_DQ3/DVO_D0(NC)

MEM_DQ5/DVO_D1(NC)
MEM_DQ6/DVO_D2(NC)
MEM_DQ7/DVO_D4(NC)
MEM_DQ8/DVO_D3(NC)

MEM_DQ9/DVO_D5(NC)
MEM_DQ10/DVO_D6(NC)
MEM_DQ11/DVO_D7(NC)

MEM_DQ12(NC)

MEM_DQ13/DVO_D9(NC)

MEM_DQ14/DVO_D10(NC)
MEM_DQ15/DVO_D11(NC)

MEM_DQS0P/DVO_IDCKP(NC)

MEM_DQS0N/DVO_IDCKN(NC)

MEM_DQS1P(NC)
MEM_DQS1N(NC)

MEM_DM1/DVO_D8(NC)

SBD_MEM/DVO_I/F

IOPLLVDD18(NC)

MEM_VREF(NC)

MEM_DQ4(NC)

MEM_DM0(NC)

IOPLLVDD(NC)

IOPLLVSS(NC)

AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21

Y17
W18
AD20
AE21

W17
AE19

AE23
AE24

AD23
AE18

MEM_DQ0
MEM_DQ1
MEM_DQ2
MEM_DQ3
MEM_DQ4
MEM_DQ5
MEM_DQ6
MEM_DQ7
MEM_DQ8
MEM_DQ9
MEM_DQ10
MEM_DQ11
MEM_DQ12
MEM_DQ13
MEM_DQ14
MEM_DQ15

MEM_DQS_P0
MEM_DQS_N0
MEM_DQS_P1
MEM_DQS_N1

MEM_DM0
MEM_DM1

+NB_IOPLLVDD

+MEM_VREF1

MEM_COMP_P and MEM_COMP_N trace
width >=10mils and 10mils spacing from
other Signals in X,Y,Z directions

L13

1 2

BLM18PG121SN1D_0603

1

C181

2.2U_0603_6.3V4Z

2

SIDE@

+1.8V_IOPLLVDD

+1.1VS

1

C182

0.1U_0402_16V4Z

2

SIDE@

09/19 update
Del SI3456 and MEM related Pull-high.

L12

1 2

BLM18PG121SN1D_0603

1

C183

2.2U_0603_6.3V4Z

2

SIDE@

+1.8VS

9/20 SA000012G20 S IC D2 32M16 HY5PS121621CFP-25 FBGA 84P

3 3

1

SIDE@

C195

2

1

SIDE@

C199

2

4 4

A

SIDE@

R96

1 2

1K_0402_1%

0.1U_0402_16V4Z

+MEM_VREF

SIDE@

R98

0.1U_0402_16V4Z

1 2

1K_0402_1%

Side Port disable,VREF need
connect to +1.8VS for DDR2

+1.8V_MEM_VDDQ+1.8V_MEM_VDDQ

SIDE@

SIDE@

1

C196

2

0.1U_0402_16V4Z

1

C200

2

0.1U_0402_16V4Z

R97

1 2

R99

1 2

10/8 update

SIDE@

1K_0402_1%

+MEM_VREF1

SIDE@

1K_0402_1%

B

SIDE@

+1.8V_MEM_VDDQ

2

C608

1

SIDE@

1U_0402_6.3V4Z

2

C607

1

SIDE@

1U_0402_6.3V4Z

1

C201

2

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

1

SIDE@

0.1U_0402_16V4Z

C202

1

C203

SIDE@

2

2

0.1U_0402_16V4Z

2007/08/02 2008/08/02

10/8 update

L15

1 2

0_0805_5%SIDE@

220 ohm @ 100MHz,2A

22U_0805_6.3V6M

Compal Secret Data

Deciphered Date

+1.8VS

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

RS780 Side-Port DDR2 SDRAM

LA-4111P

E

of

12 47Thursday, No vember 15, 2007

0.2

A

[e-mail]

B

C

D

E

1 1

0.6A/50mil/4vias

+1.1VS

FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

+1.2V_HT

2 2

09/19 update

3 3

FBMA-L11-201209-221LMA30T_0805@

+1.35VS

FBMA-L11-201209-221LMA30T_0805

+1.8VS

FBMA-L11-201209-221LMA30T_0805

L18

L19

12

L95

12

L22

4.7U_0805_10V4Z

L16

4.7U_0805_10V4Z

4.7U_0805_10V4Z

12

12

2A

C215

4.7U_0805_10V4Z

2A

12

1

C235

2

4.7U_0805_10V4Z

L

2A

0.1U_0402_16V4Z
C206

1

C209

2

0.45A/40mil/3vias

L

0.1U_0402_16V4Z

1

1

C214

2

2

0.1U_0402_16V4Z

0.5A/50mil/4vias

L

2A

1

C225

C226

2

0.1U_0402_16V4Z

0.25A/30mil/2vias

L

1

C236

C246

2

0.1U_0402_16V4Z

+1.8VS

C251

1U_0402_6.3V4Z

1

C207

2

0.1U_0402_16V4Z

1

C216

2

1

C227

2

0.1U_0402_16V4Z

1

C237

2

0.1U_0402_16V4Z

+1.8VS

1

2

0.1U_0402_16V4Z
C208

1

1

2

2

0.1U_0402_16V4Z
C217

1

2

1

1

C229

C228

2

2

0.1U_0402_16V4Z

1

1

C239

C238

2

2

0.1U_0402_16V4Z

1 2

R1051 0_0603_5%SIDE@

11/13 update

+VDDHT

1

C210

0.1U_0402_16V4Z

2

+VDDHTRX

1

C218

0.1U_0402_16V4Z

2

+VDDHTTX

1

2

0.1U_0402_16V4Z

+VDDA18PCIE

1

2

0.1U_0402_16V4Z

+1.8V_VDD_SP

J17

K16

L16
M16
P16
R16

T16
H18

G19

F20
E21
D22
B23
A23

AE25
AD24
AC23
AB22
AA21

Y20

W19

V18
U17

T17
R17
P17
M17

J10
P10
K10
M10

L10

W9

T10
R10

AA9
AB9
AD9
AE9
U10

AE11
AD11

1

C252
1U_0402_6.3V4Z

2

SIDE@

U3E

VDDHT_1
VDDHT_2
VDDHT_3
VDDHT_4
VDDHT_5
VDDHT_6
VDDHT_7

VDDHTRX_1
VDDHTRX_2
VDDHTRX_3
VDDHTRX_4
VDDHTRX_5
VDDHTRX_6
VDDHTRX_7

VDDHTTX_1
VDDHTTX_2
VDDHTTX_3
VDDHTTX_4
VDDHTTX_5
VDDHTTX_6
VDDHTTX_7
VDDHTTX_8
VDDHTTX_9
VDDHTTX_10
VDDHTTX_11
VDDHTTX_12
VDDHTTX_13

VDDA18PCIE_1
VDDA18PCIE_2
VDDA18PCIE_3
VDDA18PCIE_4
VDDA18PCIE_5
VDDA18PCIE_6

H9

VDDA18PCIE_7
VDDA18PCIE_8
VDDA18PCIE_9

Y9

VDDA18PCIE_10
VDDA18PCIE_11
VDDA18PCIE_12
VDDA18PCIE_13
VDDA18PCIE_14
VDDA18PCIE_15

F9

VDD18_1

G9

VDD18_2
VDD18_MEM1(NC)
VDD18_MEM2(NC)

RS780M_FCBGA528

UMA@

PART 5/6

VDDPCIE_1
VDDPCIE_2
VDDPCIE_3
VDDPCIE_4
VDDPCIE_5
VDDPCIE_6
VDDPCIE_7
VDDPCIE_8

VDDPCIE_9
VDDPCIE_10
VDDPCIE_11
VDDPCIE_12
VDDPCIE_13
VDDPCIE_14
VDDPCIE_15
VDDPCIE_16
VDDPCIE_17

VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8

VDDC_9
VDDC_10
VDDC_11
VDDC_12

POWER

VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22

VDD_MEM1(NC)
VDD_MEM2(NC)
VDD_MEM3(NC)
VDD_MEM4(NC)
VDD_MEM5(NC)
VDD_MEM6(NC)

VDD33_1(NC)
VDD33_2(NC)

0.7A/60mil/4vias

L

VDDA_12=2.5A

A6
B6
C6
D6
E6
F6
G7
H8
J9
K9
M9
L9
P9
R9
T9
V9
U9

K12
J14
U16
J11
K15
M12
L14
L11
M13
M15
N12
N14
P11
P13
P14
R12
R15
T11
T15
U12
T14
J16

AE10
AA11
Y11
AD10
AB10

+1.8V_VDD_MEM

AC10
H11

H12

L17

1 2

FBMA-L11-201209-221LMA30T_0805

+VDDA11PCIE

10/04 update

L

C211
C212

C220 1U_0402_6.3V4Z
C219 1U_0402_6.3V4Z
C222 1U_0402_6.3V4Z
C221 1U_0402_6.3V4Z
C224 0.1U_0402_16V4Z
C223 0.1U_0402_16V4Z

+1.1VS +NB_VDDC

L

1

C2470.1U_0402_16V4Z

2

0.15A/30mil/2vias

+3VS

L20
FBMA-L11-201209-221LMA30T_0805
L21

FBMA-L11-201209-221LMA30T_0805

7A/280mil/16vias

1

1

1

1

C2410.1U_0402_16V4Z

C2430.1U_0402_16V4Z

C2400.1U_0402_16V4Z

C2420.1U_0402_16V4Z

2

2

2

2

+1.8VS

SIDE@

0_0603_5%

1 2

R1054

1 2
1 2
1 2
1 2

1 2
1 2

VDD_CORE=5A

1

1

C2310.1U_0402_16V4Z

C2300.1U_0402_16V4Z

2

2

1 2
1 2

10U_0805_10V4Z
10U_0805_10V4Z

12
12

1

1

C2320.1U_0402_16V4Z

C2440.1U_0402_16V4Z

2

2

C2500.1U_0402_16V4Z
C2530.1U_0402_16V4Z

330U_D2E_2.5VM_R15

1

1

C24510U_0805_10V4Z

C23310U_0805_10V4Z

2

2

12
12
12
12
12

+1.1VS

1

C234

+

2

C2494.7U_0805_10V4Z SIDE@
C2480.1U_0402_16V4Z SIDE@
C5970.1U_0402_16V4Z SIDE@
C5980.1U_0402_16V4Z SIDE@
C5990.1U_0402_16V4Z SIDE@

U3F

A25

VSSAHT1

D23

VSSAHT2

E22

VSSAHT3

G22

VSSAHT4

G24

VSSAHT5

G25

VSSAHT6

H19

VSSAHT7

J22

VSSAHT8

L17

VSSAHT9

L22

VSSAHT10

L24

VSSAHT11

L25

VSSAHT12

M20

VSSAHT13

N22

VSSAHT14

P20

VSSAHT15

R19

VSSAHT16

R22

VSSAHT17

R24

VSSAHT18

R25

VSSAHT19

H20

VSSAHT20

U22

VSSAHT21

V19

VSSAHT22

W22

VSSAHT23

W24

VSSAHT24

W25

VSSAHT25

Y21

VSSAHT26

AD25

VSSAHT27

L12

VSS11

M14

VSS12

N13

VSS13

P12

VSS14

P15

VSS15

R11

VSS16

R14

VSS17

T12

VSS18

U14

VSS19

U11

VSS20

U15

VSS21

V12

VSS22

W11

VSS23

W15

VSS24

AC12

VSS25

AA14

VSS26

Y18

VSS27

AB11

VSS28

AB15

VSS29

AB17

VSS30

AB19

VSS31

AE20

VSS32

AB21

VSS33

K11

VSS34

RS780M_FCBGA528

UMA@

PART 6/6

GROUND

VSSAPCIE1
VSSAPCIE2
VSSAPCIE3
VSSAPCIE4
VSSAPCIE5
VSSAPCIE6
VSSAPCIE7
VSSAPCIE8

VSSAPCIE9
VSSAPCIE10
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30
VSSAPCIE31
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9

VSS10

A2
B1
D3
D5
E4
G1
G2
G4
H7
J4
R7
L1
L2
L4
L7
M6
N4
P6
R1
R2
R4
V7
U4
V8
V6
W1
W2
W4
W7
W8
Y6
AA4
AB5
AB1
AB7
AC3
AC4
AE1
AE4
AB2

AE14
D11
G8
E14
E15
J15
J12
K14
M11
L15

+1.8VS

1

C1064

2

10U_0805_10V4Z

4 4

VLDT_EN#<36>

10/8 update

R1017 0_0402_5%

A

2N7002_SOT23-3

1 2

2

1

Just for RS780M A11 version boot issue

L

12

R1015
1K_0402_1%

+VREF1.35V

12

Q163

C1068

0.1U_0402_16V7K@

2

G

R1016

13

D

3K_0402_5%

S

0.1U_0402_16V7K

U64

VIN1VCNTL

2

GND

3

VREF

4

VOUT

G2992F1U_SO8

1

2

C1067

C1066

10U_0805_10V4Z

2

1

B

+1.35VS

NC
NC
NC
TP

6
5
7
8
9

09/19 update

+3VS

1

C1065
1U_0603_10V6K

2

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

RS780 PWR/GND

LA-4111P

13 47Thursday, No vember 15, 2007

E

0.2

of

A

B

C

D

E

1 1

2 2

RS780 DFT_GPIO5 mux at CRT_VSYNC pull low to 3K

CRT_VSYNC<11,16>

12

R101 1K_0402_5%@

12

R102 1K_0402_5%

+3VS

DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb

Enables the Test Debug Bus using GPIO.
1 : Disable (RS740) Enable (RX780, RS780)
0 : Enable (Rs740) Disable (RX780, RS780)
PIN: RS740-->RS780_AUX_CAL; RX780-->NB_TV_C; RS780--> VSYNC#

DFT_GPIO1: LOA D_ EE PROM_STRAPS

1 2

R104 150_0402_1%@
D4 CH751H-40PT_SOD323-2@

2 1

Selects Loading of STRAPS from EPROM
1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 : I2C Master can load strap values from EEPROM if connected, or use
default values if not connected
RS740/RX780: DFT_GPIO1 RS780:SUS_STAT

RS780 DFT_GPIO1

AUX_CAL<11>

SUS_STAT_R#<11> PLT_RST# <11,19,25,26,27,32,33>

RX780 DFT_GPIO1 mux at GREEN(Ball E18) and change pull low form 150 to 3K.

3 3

DFT_GPIO0: STR A P_DEBUG_BUS_PCIE_E NABLEb

RS780_DFT_GPIO_0<11>

RS780 use HSYNC to enable SIDE PORT (internal pull high)

CRT_HSYNC<11,16>

R105 1K_0402_5%@

R107 3K_0402_5%SIDE@

12

12

RX780: Enables the Test Debug Bus using PCIE bus
1 : Disable ( Can still be enabled using nbcfg register access )
0 : Enable

RS740/RS780: Enables Side port memory ( RS780 use HSYNC#)

1. Disable (RS740/RS780)
0 : Enable (RS740/RS780)

10/09 update

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

RS780 STRAPS

LA-4111P

14 47Thursday, No vember 15, 2007

E

0.2

of

A

[e-mail]

B

C

D

E

R167

1 2

0_0805_5%

+3VS_CLK

1

C444
10U_0805_10V4Z

2

1

C445

0.1U_0402_16V4Z

2

1

C458

0.1U_0402_16V4Z

2

1

C446

0.1U_0402_16V4Z

2

1

C459

0.1U_0402_16V4Z

2

1

C447

0.1U_0402_16V4Z

2

1

C460

0.1U_0402_16V4Z

2

1

C448

0.1U_0402_16V4Z

2

1

C461

0.1U_0402_16V4Z

2

1

C449

0.1U_0402_16V4Z

2

1

C450

0.1U_0402_16V4Z

2

1

C451

@

1U_0402_6.3V4Z

2

+3VS

R168

1 2

0_0805_5%

+VDDCLK_IO

1

2

0.1U_0402_16V4Z

1

C452

2

C453

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C454

2

1

C455

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C456

2

1

C457

2

+1.2V_HT

10U_0805_10V4Z

1 1

EMI Caps for single end clock.

CLK_48M_USB

R170 33_0402_5%

1 2

1 2

CLK_48M_USB_R

71

VSS_48

48MHz_0

+3VS_CLK

69

70

VDD_48

48MHz_1

CLK_XTAL_OUT

68

CLK_XTAL_IN

67

XTAL_OUT

R379 200_0402_1%

NB_OSC_14.318M_R

65

66

XTAL_IN

VSS_REF

REF_0/SEL_HTT66

+3VS_CLK

SEL_SATA

27M_SEL

64

63

62

REF_2/SEL_27

REF_1/SEL_SATA

R220 33_0402_5%

1 2

+3VS_CLK

61

60

59

58

57

VSS_HTT

VDD_HTT

VDD_REF

HTT_0/66M_0

HTT_0#/66M_1

1 2

R380 100_0402_1%

1 2

R174 8.2K_0402_5%

CLK_CPU_BCLK_R
CLK_CPU_BCLK#_R

09/21 update

56

55

PD#

CPU_K8_0

CPU_K8_0#

VDD_CPU

VDD_CPU_I/O

VSS_CPU
CLKREQ_1#
CLKREQ_2#

VDD_A

VSS_A

VSS_SATA

SRC_6/SATA

SRC_6#/SATA#

VDD_SATA
CLKREQ_3#
CLKREQ_4#

SB_SRC_SLOW#

SB_SRC_0

SB_SRC_0#

VDD_SB_SRC

VDD_SB_SRC_IO

CLK_XTAL_OUT
CLK_XTAL_IN

Y2

12

14.31818MHZ_20P_6X1430004201

+3VS_CLK

+VDDCLK_IO

+VDDCLK_IO

1

C465
22P_0402_50V8J

2

+3VS_CLK

09/29 update

U10

1

SCL

2

SDA

3

VDD_DOT

4

SRC_7#/27M

5

SRC_7/27M_SS

6

VSS_DOT

7

SRC_5#

8

SRC_5

9

SRC_4#

10

SRC_4

11

VSS_SRC

12

VDD_SRC_IO

13

SRC_3#

14

SRC_3

15

SRC_2#

16

SRC_2

17

VDD_SRC

18

VDD_SRC_IO

72

73

GND

2 2

22P_0402_50V8J

C464

1

2

Routing the t race at least 10mil

SMB_CK_CLK0<8,9,20,30>
SMB_CK_DAT0<8,9,20,30>

PA_RS7X0A1

SB LINK SB SRC

MiniCard_1
MiniCard_2

3 3

CLK_SBLINK_BCLK#<11>

CLK_SBLINK_BCLK<11>

CLK_PCIE_MCARD1#<26>

CLK_PCIE_MCARD1<26>

CLK_PCIE_MCARD2#<26>

CLK_PCIE_MCARD2<26>

CLK_48M_USB <20>
NB_OSC_14.318M <11>

CLK_14M_SIO <32>
CLK_NBHT <11>
CLK_NBHT# <11>

+3VS_CLK

1 2

R946 0_0402_1%

1 2

R945 0_0402_1%

54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37

+3VS_CLK
+VDDCLK_IO

CLKREQ_NCARD#
CLKREQ_MCARD2#

+3VS_CLK

CLKREQ_MCARD1#
CLKREQ4

1 2

R372 10K_0402_5%

+3VS_CLK
+VDDCLK_IO

NB

R186
261_0402_1%@

10/03 update

1 2

+3VS_CLK

RS780

CLK_SBSRC_BCLK <19>
CLK_SBSRC_BCLK# <19>

CLKREQ_MCARD1# <26>

+3VS_CLK

OSC_14M_NB

1.8V 75R/100RRX780

1.1V 200R/100R

CLK_CPU_BCLK <6>

CPU

CLK_CPU_BCLK# <6>

CLKREQ_NCARD# <26>
CLKREQ_MCARD2# <26>

For ICS need to pull high.
For SLG is NC

PA_RS7X0A1

NB_OSC_14.318M

CLK_14M_SIO

C1076

@

5P_0402_50V8C

1

2

1

@

1

5P_0402_50V8C

2

C1075

@
2

5P_0402_50V8C

C1074

VSS_SRC19SRC_1#20SRC_121SRC_0#22SRC_023CLKREQ_0#24ATIGCLK_2#25ATIGCLK_226VSS_ATIG27VDD_ATIG_IO28VDD_ATIG29ATIGCLK_1#30ATIGCLK_131ATIGCLK_0#32VSS_SB_SRC36SB_SRC_135SB_SRC_1#34ATIGCLK_0

33

+3VS_CLK

R179

@

8.2K_0402_5%

1 2

SEL_SATA

R181

8.2K_0402_5%

4 4

SEL_SATA

* default

1 2

1

configure as SATA output

*

configure as normal SRC(SRC_6) output

0

+3VS_CLK

1 2

27M_SEL

R180

8.2K_0402_5%

27M_SEL

1*
0

configure as 27M and 27M_SS output
configure as SRC_7 output

* default

+3VS_CLK

+VDDCLK_IO

CLKREQ_LAN#

SLG8SP626VTR_QFN72_10x10

9/20 SA00001Z300 S IC SLG8SP626VTR QFN 72P CLK GEN
9/20 SA000025B00 S IC RTM880N-795-GRT QFN 72P CLK GEN

NBGFX_CLK <11>
NBGFX_CLK# <11>

CLK_PCIE_MCARD0 <27>
CLK_PCIE_MCARD0# <27>
CLKREQ_LAN# <25>
CLK_PCIE_LAN <25>
CLK_PCIE_LAN# <25>

CLK_PCIE_NCARD <26>
CLK_PCIE_NCARD# <26>

NB GFX

Card Reader

GLAN

New Card

CLKREQ_NCARD#
CLKREQ_MCARD2#
CLKREQ_MCARD1#
CLKREQ_LAN#
CLKREQ4

NB CLOCK INPUT TABLE

NB CLOCKS
HT_REFCLKP
HT_REFCLKN
REFCLK_P
REFCLK_N
GFX_REFCLK 100M DIFF

1 2

R324 8.2K_0402_5%

1 2

R325 8.2K_0402_5%

1 2

R326 8.2K_0402_5%

1 2

R1039 8.2K_0402_5%

1 2

R1045 8.2K_0402_5%

RX780 RS780

100M DIFF
100M DIFF

14M SE (1.8V) 14M SE (1.1V)
NC vref

+3VS_CLK

100M DIFF
100M DIFF

100M DIFF(IN/OUT)*

Use voltage divider resistor R379 & R380 to pull low

NB_OSC_14.318M

*0 confi gu re as di ff er en tial 100MHz output

* default

configure as single-ended 66MHz output1

A

B

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Clock generator

LA-4111P

15 47Thursday, November 15, 2007

E

0.2

of

A

B

C

D

E

1 1

C476

22P_0402_50V8J

1

D37

@

DAN217_SC59

2

RED_L

GREEN_L

BLUE_L

1

2

22P_0402_50V8J

3

C472

@

1

2

1

D35

@

DAN217_SC59

2

3

L47

1 2

BLM15AG121SN1D_0402

L48

1 2

BLM15AG121SN1D_0402

L49

1 2

BLM15AG121SN1D_0402

1

2

6P_0402_50V8K

C858

1

2

CRT_HSYNC<11,14>

CRT_VSYNC<11,14>

R217

150_0402_1%

+CRT_VCC

R218

D_DDCDATA

D_DDCCLK

1

@

2

470P_0402_50V8J

RED

GREEN

BLUE

12

C471

150_0402_1%

6.8K_0402_5%

C856

1

2

C859

6P_0402_50V8K

D_DDCCLK <35>

1

C469

2

6P_0402_50V8K

D_DDCDATA <35>

RED<11>

GREEN<11>

BLUE<11>

12

12

R211

R214

+3VS

2

3

Q10B

6.8K_0402_5%

61

Q10A

470P_0402_50V8J

150_0402_1%

R100

C857

@

1

2

2 2

12

R237

4.7K_0402_5%

UMA_CRT_DAT<11>

UMA_CRT_CLK<11>

3 3

R238

4.7K_0402_5%

1 2

2N7002DW-7-F_SOT363-6

5

4

2N7002DW-7-F_SOT363-6

CRT CONNECTOR

+R_CRT_VCC

D36

1

D34

DAN217_SC59

2

3

22P_0402_50V8J

@

2 1

+CRT_VCC

1 2

C473

0.1U_0402_16V4Z

1 2

C477

0.1U_0402_16V4Z

RB491D_SOT23

+3VS

D_DDCDATA

HSYNC

VSYNC

D_DDCCLK

+CRT_VCC

1

5

P

OE#

A2Y

G

U14
SN74AHCT1G125GW_SOT353-5

3

1

5

P

OE#

A2Y

G

U13

SN74AHCT1G125GW_SOT353-5

3

F2

21

1A_6VDC_MINISMDC110

0.1U_0402_16V4Z

JCRT

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5
16

17

SUYIN_070546FR015S263ZRCONN@

D_HSYNC

4

D_VSYNC

4

+CRT_VCC+5VS

1

C475

2

11/14 update

RGND
ID0
Red
GGND
SDA
Green
BGND
Hsync
Blue
+5V
Vsync
res
SGND
SCL
GND

GND
GND

R240 0_0603_5%

1 2

11/07 update

R241 0_0603_5%

1 2

Update PCB
Footprint SUYIN_070546FR015S263ZR_15P-T
: Change back
JCRT.5<->JCRT.15 ;
JCRT.14<->JCRT.4 ;
JCRT.13<->JCRT.3 ;
JCRT.12<->JCRT.2 ;
JCRT.11<->JCRT.1

RED_L <35>
GREEN_L <35>
BLUE_L <35>

D_VSYNC <35>
D_HSYNC <35>

HSYNC

VSYNC

1

1

C470

@

C474

@

2

2

10P_0402_50V8J

10P_0402_50V8J

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

CRT Connector

LA-4111P

16 47Thursday, No vember 15, 2007

E

0.2

of

A

[e-mail]

B

C

D

E

USB_VCCA is +3.9V, R892:100K;
R891:215KKohm
G916 Vref=1.25V when U54 install
G916-390T1UF

C718 install when U54 is

L

RT9193-39GB

Close to JLVDS

L

D22

+USB_CAM

R222

680P_0402_50V7K

USB20_N5

4
3

PRTR5V0U2X_SOT143-4@

2

C863
1000P_0402_50V7K

1

4.7U_0805_10V4Z

INV_PWM <33>
BKOFF# <33>
DAC_BRIG <33>

10/08 update

BKOFF#

LCD_DDC_CLK

LCD_DDC_DAT

IO1

VIN

GND

IO2

G

2

C487

USB20_P5

2
1

11/09 update

+3VS

80mil

S

SI2301BDS-T1-E3_SOT23-3
Q43

D

1 3

80mil

1

C491

0.1U_0402_16V4Z

2

1 2

R4834.7K_0402_5%@

1 2

R2744.7K_0402_5%

1 2

R2754.7K_0402_5%

11/07 update

+LCDVDD

+3VS

1

2

+LCDVDD

R225

12

R891

215K_0402_1%@

12

R892

100K_0402_1%@

12

61

R276

1 2

200_0805_5%

C482

2

5

@

680P_0402_50V7K

+USB_CAM

2

C719
10U_0805_10V4Z

1

+5VALW

R224
1M_0402_5%

1 2

1 2

100K_0402_5%

3

Q45B
2N7002DW-7-F_SOT363-6

4

+5VS

1

1

C483

2

2

@

WebCam+Digital Mic Reserve

11/13 update

IO1

GND

JP7

1

1

2

2

3

3

4

4

5

5

6

6

ACES_88231-06001

CONN@

USB20P5

2
1

7

G1

8

G2

680P_0402_50V7K

L

USB20_N5

DMIC_DAT
DMIC_CLK

680P_0402_50V7K

C479

1

2

+3VS

12

C481

Place R1027~R1030
close to JLVDS

R1027 0_0402_5%@

R1028 0_0402_5%@

R1029 0_0402_5%@

R1030 0_0402_5%@

USB20_P5<20>
USB20_N5<20>

LVDS_BCLK+<11>

LVDS_BCLK-<11>

1 2
1 2

1 2
1 2

INVPWR_B++L CDVDD

12

C480
680P_0402_50V7K

LVDS_B0+<11>

LVDS_B0-<11>

LVDS_B1+<11>

LVDS_B1-<11>

LVDS_B2+<11>

LVDS_B2-<11>

USB20P5USB20_P5
USB20N5

DMICDAT
DMICCLK

FBMA-L11-201209-221LMA30T_0805

USB20_P5
USB20_N5

LVDS_BCLK+
LVDS_BCLK-

LVDS_B0+
LVDS_B0­LVDS_B1+
LVDS_B1­LVDS_B2+
LVDS_B2-

PAD-OPEN 2x2m

10U_0805_10V4Z

L44

1 2

B+

LVDS CONN

JLVDS

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

GND41GND

ACES_88242-4001

CONN@

9/20 SP02000EA00/SP02000BW00

1 1

+USB_CAM

Close to JP7

L

C1072

@

10U_0805_10V4Z

+USB_CAM

USB20N5

09/26 update

2 2

LVDS_A2-

C1056 10P_0402_50V8J@

1 2

C1057 10P_0402_50V8J@

3 3

LVDS_ACLK- LVDS_ACLK+
LVDS_B2- LVDS_B2+
LVDS_B1- LVDS_B1+
LVDS_B0- LVDS_B0+
LVDS_BCLK- LVDS_BCLK+

1 2

C1058 10P_0402_50V8J@

1 2

C1059 10P_0402_50V8J@

1 2

C1060 10P_0402_50V8J@

1 2

C1061 10P_0402_50V8J@

1 2

C1062 10P_0402_50V8J@

1 2

C1063 10P_0402_50V8J@

1 2

2

1

LVDS_A2+
LVDS_A1+LVDS_A1­LVDS_A0+LVDS_A0-

USB20P5
USB20N5

DMICCLK
DMICDAT

D52

4
3

PRTR5V0U2X_SOT143-4@

VIN
IO2

09/19 update

+5VALW

PJP4

2 1

2

C720

12

1

R1013
0_0402_5%

LVDS_A2-

2

2

LVDS_A2+

4

4

LVDS_A1-

6

6

LVDS_A1+

8

8

LVDS_A0-

10

10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42

LVDS_A0+
LVDS_ACLK­LVDS_ACLK+

DMIC_DAT
DMIC_CLK

INV_PWM
BKOFF#
DAC_BRIG

LCD_DDC_CLK
LCD_DDC_DAT

1

VIN

2

GND

3

EN

RT9193-39GB_SOT23-5

@

1 2

0_0402_5%

UMA_ENVDD<11>

+USB_CAM

12

C866

C867

@

680P_0402_50V7K

U54

680P_0402_50V7K

5

VOUT

4

BP

0.1U_0402_16V4Z

R1014

2N7002DW-7-F_SOT363-6

LVDS_A2- <11>
LVDS_A2+ <11>
LVDS_A1- <11>
LVDS_A1+ <11>
LVDS_A0- <11>
LVDS_A0+ <11>
LVDS_ACLK- <11>
LVDS_ACLK+ <11>

DMIC_DAT <28>
DMIC_CLK <28>

LCD_DDC_CLK <11>
LCD_DDC_DAT <11>

12

@

C718

CAM_SHDN# <21>

470_0805_5%

Q45A

2.2K_0402_5%

11/07 update

R491

1 2

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

LCD CONN. / WebCam

LA-4111P

17 47Thursday, No vember 15, 2007

E

0.2

of

A

1 1

0.1U_0402_16V4Z

2 2

3 3

Just change P/N to SD034750080

11/13 update

4 4

+HDMI_5V_OUT

C851

2

TMDS_B_CLK#<10>
TMDS_B_CLK<10>

TMDS_B_DATA0#<10>

TMDS_B_DATA0<10>

TMDS_B_DATA1#<10>

TMDS_B_DATA1<10>

TMDS_B_DATA2#<10>
TMDS_B_DATA2<10>

HDMI_CLK­HDMI_CLK+

750_0402_1%

+5VS +5VS +5VS +5VS

1

5

1

P

OE#

A2Y

G

U39
SN74AHCT1G125GW_SOT353-5

3

12

R315

R307
750_0402_1%

1 2

61

2

Q136A

2N7002DW-7-F_SOT363-6

2.2K_0402_5%

4

C507 0.1U_0402_16V7K

1 2

C508 0.1U_0402_16V7K

1 2

C655 0.1U_0402_16V7K

1 2

C675 0.1U_0402_16V7K

1 2

C804 0.1U_0402_16V7K

1 2

C827 0.1U_0402_16V7K

1 2

C852 0.1U_0402_16V7K

1 2

C853 0.1U_0402_16V7K

1 2

HDMI_TX0­HDMI_TX0+

R173

750_0402_1%

R297
750_0402_1%

1 2

1 2
3

5

Q136B

4

2N7002DW-7-F_SOT363-6

HDMI_TX1­HDMI_TX1+

750_0402_1%

B

12

+3VS

R615

HPD <11>

HDMI_CLK­HDMI_CLK+

HDMI_TX0­HDMI_TX0+

HDMI_TX1­HDMI_TX1+

HDMI_TX2­HDMI_TX2+

HDMI_TX2­HDMI_TX2+

R172

R304
750_0402_1%

750_0402_1%

1 2

1 2

61

2

Q162A

2N7002DW-7-F_SOT363-6

R628

100K_0402_5%

R139

5

HDMI_HPD

2

C850

0.1U_0402_16V4Z

1

1 2

UMA use 750 ohm

R141
750_0402_1%

1 2

1 2
3

Q162B

4

2N7002DW-7-F_SOT363-6

VGA u se 499 ohm

C

12

R176

4.7K_0402_5%

HDMIDAT_UMA<11>

HDMICLK_UMA<11>

R209

4.7K_0402_5%

1 2

2N7002DW-7-F_SOT363-6

D

2

6.8K_0402_5%

61

3

Q134B

Q134A

2N7002DW-7-F_SOT363-6

5

4

C:Chg. PN to SB770020010.

11/13 update

HDMI_CLK+

HDMI_CLK-

HDMI_TX0+

HDMI_TX0-

HDMI_TX1+

HDMI_TX1-

HDMI_TX2-

Change PCB Footprint from SW_WCM2012F2S_4P to KING_WCM-2012-900T_4P

L

1 2

R112 0_0402_5%

L85

1

1

2

4

4

1 2

1 2

1

4

1 2

1 2

1

4

1 2

1 2

1

4

1 2

3

2

3

2

3

2

3

WCM-2012-900T_4P@

R113 0_0402_5%

R115 0_0402_5%

L86

1

4

WCM-2012-900T_4P@

R116 0_0402_5%

R117 0_0402_5%

L87

1

4

WCM-2012-900T_4P@

R118 0_0402_5%

R119 0_0402_5%

L88

1

4

WCM-2012-900T_4P@

R120 0_0402_5%

2

3

2

3

2

3

2

3

HDMI_R_CK+

HDMI_R_CK-

HDMI_R_D0+

HDMI_R_D0-

HDMI_R_D1+

HDMI_R_D1-

HDMI_R_D2+HDMI_TX2+

HDMI_R_D2-

R210

+HDMI_5V_OUT+3VS

E

R236

6.8K_0402_5%

HDMI_SDATA

HDMI_SCLK

MP:Update D10 to meet HDMI.

+5VS +HDMI_5V_OUT

RB491D_SOT23

1

C468

0.1U_0402_16V4Z

2

D10

2 1

HDMI Connector

+HDMI_5V_OUT

JHDMI

18

HDMI_SDATA
HDMI_SCLK
HDMI_HPD

HDMI_R_CK­HDMI_R_CK+
HDMI_R_D0­HDMI_R_D0+
HDMI_R_D1­HDMI_R_D1+
HDMI_R_D2­HDMI_R_D2+

11/14 update

+5V

16

SDA

15

SCL

19

HP_DET

12

CK-

10

CK+

9

D0-

7

D0+

6

D1-

4

D1+

3

D2-

1

D2+

SUYIN_100042MR019S153ZLCONN@

CEC

Reserved

GND
GND
GND
GND
GND
GND
GND
GND

DDC/CEC_GND

13
14

2
5
8
11
20
21
22
23
17

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

HDMI

LA-4111P

18 47Thursday, No vember 15, 2007

E

0.2

of

A

[e-mail]

+3VALW

C506

12

5

0.1U_0402_16V4Z@

NB_RST#_R

+1.8VS

+3VS

R312 0_0402_5%

18P_0402_50V8J

20M_0603_5%

18P_0402_50V8J

1 1

2 2

3 3

11/13 update

H_PWRGD_CPU<6>

4 4

U16

2

P

B

Y

1

A

G

3

12

R314 20M_0402_5%@

1 2

C643

1 2

12

R389

C652

1 2

Close to SB

09/11 update

R318 10K_0402_5%@

R319 10K_0402_5%

PLT_RST#

4

NC7SZ08P5X_NL_SC70-5@

12

12

PLT_RST# <11,14,25,26,27,32,33>

Y3

4

OUT

1

IN

32.768KHZ_12.5PF_1TJS125BJ4A421P

CPU_LDT_REQ#

H_PROCHOT#

R311

1 2

0_0402_5%

3

NC

2

NC

Check AMD need pull low or not

SB_RX0P<10>
SB_RX0N<10>
SB_RX1P<10>
SB_RX1N<10>
SB_RX2P<10>
SB_RX2N<10>
SB_RX3P<10>
SB_RX3N<10>

SB_TX0P<10>
SB_TX0N<10>
SB_TX1P<10>
SB_TX1N<10>
SB_TX2P<10>
SB_TX2N<10>
SB_TX3P<10>
SB_TX3N<10>

+PCIE_VDDR

+1.2V_HT

SB_32KHI

SB_32KHO

H_PWRGD

1 2

BLM18PG121SN1D_0603

1 2

R300 8.2K_0402_5%@

C492 0.1U_0402_16V7K

1 2

C493 0.1U_0402_16V7K

1 2

C494 0.1U_0402_16V7K

1 2

C495 0.1U_0402_16V7K

1 2

C496 0.1U_0402_16V7K

1 2

C497 0.1U_0402_16V7K

1 2

C498 0.1U_0402_16V7K

1 2

C499 0.1U_0402_16V7K

1 2

L53

C504

10U_0805_10V4Z

Close to SB

CLK_SBSRC_BCLK<15>
CLK_SBSRC_BCLK#<15>

CPU_LDT_REQ#<6,11>

H_PROCHOT#<6>

LDT_STOP#<6,11>

B

NB_RST#_R

R305 562_0402_1%
R306 2.05K_0402_1%

1

1

2

2

H_PWRGD

LDT_RST#<6>

C

NB_RST#_R
SB_RX0P_C

SB_RX0N_C
SB_RX1P_C
SB_RX1N_C
SB_RX2P_C
SB_RX2N_C
SB_RX3P_C
SB_RX3N_C

12
12

+SB_PCIEVDD

C505

1U_0402_6.3V4Z

CPU_LDT_REQ#
H_PROCHOT#
H_PWRGD

SB_32KHI

SB_32KHO

U15A

N2

A_RST#

V23

PCIE_TX0P

V22

PCIE_TX0N

V24

PCIE_TX1P

V25

PCIE_TX1N

U25

PCIE_TX2P

U24

PCIE_TX2N

T23

PCIE_TX3P

T22

PCIE_TX3N

U22

PCIE_RX0P

U21

PCIE_RX0N

U19

PCIE_RX1P

V19

PCIE_RX1N

R20

PCIE_RX2P

R21

PCIE_RX2N

R18

PCIE_RX3P

R17

PCIE_RX3N

T25

PCIE_CALRP

T24

PCIE_CALRN

P24

PCIE_PVDD

P25

PCIE_PVSS

N25

PCIE_RCLKP/NB_LNK_CLKP

N24

PCIE_RCLKN/NB_LNK_CLKN

K23

NB_DISP_CLKP

K22

NB_DISP_CLKN

M24

NB_HT_CLKP

M25

NB_HT_CLKN

P17

CPU_HT_CLKP

M18

CPU_HT_CLKN

M23

SLT_GFX_CLKP

M22

SLT_GFX_CLKN

J19

GPP_CLK0P

J18

GPP_CLK0N

L20

GPP_CLK1P

L19

GPP_CLK1N

M19

GPP_CLK2P

M20

GPP_CLK2N

N22

GPP_CLK3P

P22

GPP_CLK3N

L18

25M_48M_66M_OSC

J21

25M_X1

J20

25M_X2

A3

X1

B3

X2

F23

ALLOW_LDTSTP

F24

PROCHOT#

F22

LDT_PG

G25

LDT_STP#

G24

LDT_RST#

218S7EALA11FG_BGA528_SB700

RTC XTAL

SB700

Part 1 of 5

PCI EXPRESS INTERFACE

LPC

CPU

RTC

PCI CLKS

PCI INTERFACE

CLOCK GENERATOR

LDRQ1#/GNT5#/GPIO68

BMREQ#/REQ5#/GPIO65

INTRUDER_ALERT#

9/20 SA00001S510 S IC 218S7EALA11FG SB700 BGA 528P SB 0FH

PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4

PCICLK5/GPIO41

PCIRST#

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8

AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

CBE0#
CBE1#
CBE2#
CBE3#

FRAME#

DEVSEL#

IRDY#

TRDY#

PAR

STOP#
PERR#
SERR#
REQ0#
REQ1#

REQ2#
REQ3#/GPIO70
REQ4#/GPIO71

GNT0#

GNT1#

GNT2#

GNT3#/GPIO72
GNT4#/GPIO73

CLKRUN#

LOCK#

INTE#/GPIO33
INTF#/GPIO34

INTG#/GPIO35

INTH#/GPIO36

LPCCLK0
LPCCLK1

LAD0
LAD1
LAD2
LAD3

LFRAME#

LDRQ0#

SERIRQ

RTCCLK

VBAT

D

P4
P3
P1

CLK_PCI_SIO_R CLK_PCI_SIO

P2
T4
T3

N1

U2
P7
V4
T1
V3
U1
V1
V2
T2
W1
T9
R6
R7
R5
U8
U5
Y7
W8
V9
Y8
AA8
Y4
Y3

PCI_AD23

Y2

PCI_AD24

AA2

PCI_AD25

AB4

PCI_AD26

AA1

PCI_AD27

AB3

PCI_AD28

AB2
AC1
AC2
AD1
W2
U7
AA7
Y1
AA6
W5
AA5
Y5
U6
W6
W4
V7
AC3
AD4
AB7
AE6
AB6
AD2
AE4
AD5
AC6
AE5
AD6
V5

AD3
AC4
AE2

PCI_PIRQH#

AE3

CLK_PCI_EC_R

G22
E22
H24
H23
J25
J24
H25
H22
AB8
AD7
V15

C3
C2
B2

+SB_VBAT

R303 22_0402_5%@

1 2

R301 22_0402_5%

1 2

PCI_AD23 <23>
PCI_AD24 <23>
PCI_AD25 <23>
PCI_AD26 <23>
PCI_AD27 <23>
PCI_AD28 <23>

PCI_SERR# <33>

T15PAD

T16PAD
T17PAD

R967 0_0402_5%

22_0402_5%

R302

1 2

LPCCLK1 <23>
LPC_AD0 <32,33>
LPC_AD1 <32,33>
LPC_AD2 <32,33>
LPC_AD3 <32,33>

1

2

LPC_FRAME# <32,33>

LPC_DRQ# <32>

SIRQ <32,33>

RTC_CLK <23>

+SB_VBAT

C510

1U_0402_6.3V4Z

T18PAD

C509

0.1U_0402_16V4Z

12

CLK_PCI_EC

1

2

STRAP PIN
EC & Debug

11/13 update

STRAP PIN

09/29 update

+RTCVCC_R

R316
120_0402_5%

1 2

W=20mils

CLK_PCI_SIO2

ACCEL_INT <30>

CLK_PCI_EC <23,33>

R317
120_0402_5%

1 2

2

J1

2

JUMP_43X39@

1

1

PCICLK2 <23>

CLK_PCI_SIO2 <32>
CLK_PCI_SIO <23,32>

PCI_CLK4 <23>
PCI_CLK5 <23>

09/29 update

+RTCVCC

1

DAN202U_SC70

11/09 update

D42

2
3

W=20mils

+RTCBATT_R

09/29 update

+3VL

1 2

ZZZ

PCB-MB

R876

1K_0402_5%

E

+RTCBATT

1
2
3
4

JBATT1

1
2
GND
GND

ACES_85205-02001CONN@

W=20mils

9/20 SP020008T00

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

SB700-PCIE/PCI/ACPI/LPC/RTC

LA-4111P

19 47Thursday, November 15, 2007

E

of

0.2

A

B

C

D

E

NB_PWRGD<11>

R1053

For SB700 A11 divider to

100_0402_5%@

R1052

12

1.8V for RS & RX780

1 1

2 2

3 3

+3VS

1 2

R388 4.7K_0402_5%

+3VALW

1 2

R320 2.2K_0402_5%@

1 2

R321 2.2K_0402_5%@

1 2

R322 2.2K_0402_5%@

+3VS

R328 2.2K_0402_5%

1 2

R329 2.2K_0402_5%

1 2

+3VALW

R331 2.2K_0402_5%

1 2

R332 2.2K_0402_5%

1 2

LAN_PCIE_WAKE#<25>
MINI_PCIE_WAKE#<26>

SUS_STAT#

SB_TEST2
SB_TEST1
SB_TEST0

SMB_CK_CLK0
SMB_CK_DAT0

SMB_CK_CLK1
SMB_CK_DAT1

12

R993 0_0402_5%

12

R994 0_0402_5%@

HDA_BITCLK_CODEC<28>
HDA_BITCLK_MDC<34>
HDA_SDOUT_MDC<34>

HDA_SDOUT_CODEC<28>
HDA_SDIN0<28>
HDA_SDIN1<34>

HDA_SYNC_MDC<34>

HDA_SYNC_CODEC<28>

HDA_RST#_CODEC<28>
HDA_RST#_MDC<34>

HDARST#<23,33>

+3VALW

R540
10K_0402_5%

1 2

PCIE_WAKE#

11/13 update

NBPWRGD

12

0_0402_5%

STRAP PIN

11/13 update

R333 33_0402_5%
R334 33_0402_5%
R335 33_0402_5%
R336 33_0402_5%

R337 33_0402_5%
R338 33_0402_5%

R339 33_0402_5%
R340 33_0402_5%

demo circuit LID use RI#

SLP_S3#<33>
SLP_S5#<33>

PWRBTN_OUT#<33>

SB_PWRGD<6,33,43>
SUS_STAT#<11>

GATEA20<33>
KB_RST#<33>
EC_SCI#<33>
EC_SMI#<33>

11/13 update

10/08 update

H_THERMTRIP#<6>

EC_RSMRST#<33>

SB700 has internal PD

EC_LID_OUT#<33>

EXP_CPPE#<26>

CR_CPPE#<27>

1 2
1 2
1 2
1 2

1 2
1 2

1 2
1 2

2.2K_0402_5%

SB_SPKR<28>
SMB_CK_CLK0<8,9,15,30>
SMB_CK_DAT0<8,9,15,30>

SMB_CK_CLK1<26>

SMB_CK_DAT1<26>

EXP_CPPE#
CR_CPPE#

HDA_BITCLK
HDA_SDOUT

HDA_SDIN0
HDA_SDIN1

SUS_STAT#
SB_TEST2
SB_TEST1
SB_TEST0

T19PAD

PCIE_WAKE#
H_THERMTRIP#

NBPWRGD
EC_RSMRST#

R327

1 2

SMB_CK_CLK0
SMB_CK_DAT0
SMB_CK_CLK1
SMB_CK_DAT1

11/13 update

R82 0_0402_5%

1 2
1 2

R81 0_0402_5%

HDA_SYNC

HDARST#

T41PAD

U15D

E1

PCI_PME#/GEVENT4#

E2

RI#/EXTEVNT0#

H7

SLP_S2/GPM9#

F5

SLP_S3#

G1

SLP_S5#

H2

PWR_BTN#

H1

PWR_GOOD

K3

SUS_STAT#

H5

TEST2

H4

TEST1

H3

TEST0

Y15

GA20IN/GEVENT0#

W15

KBRST#/GEVENT1#

K4

LPC_PME#/GEVENT3#

K24

LPC_SMI#/EXTEVNT1#

F1

S3_STATE/GEVENT5#

J2

SYS_RESET#/GPM7#

H6

WAKE#/GEVENT8#

F2

BLINK/GPM6#

J6

SMBALERT#/THRMTRIP#/GEVENT2#

W14

NB_PWRGD

D3

RSMRST#

AE18

SATA_IS0#/GPIO10

AD18

CLK_REQ3#/SATA_IS1#/GPIO6

AA19

SMARTVOLT1/SATA_IS2#/GPIO4

W17

CLK_REQ0#/SATA_IS3#/GPIO0

V17

CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39

W20

CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40

W21

SPKR/GPIO2

AA18

SCL0/GPOC0#

W18

SDA0/GPOC1#

K1

SCL1/GPOC2#

K2

SDA1/GPOC3#

AA20

DDC1_SCL/GPIO9

Y18

DDC1_SDA/GPIO8

C1

LLB#/GPIO66

Y19

SMARTVOLT2/SHUTDOWN#/GPIO5

G5

DDR3_RST#/GEVENT7#

B9

USB_OC6#/IR_TX1/GEVENT6#

B8

USB_OC5#/IR_TX0/GPM5#

A8

USB_OC4#/IR_RX0/GPM4#

A9

USB_OC3#/IR_RX1/GPM3#

E5

USB_OC2#/GPM2#

F8

USB_OC1#/GPM1#

E4

USB_OC0#/GPM0#

M1

AZ_BITCLK

M2

AZ_SDOUT

J7

AZ_SDIN0/GPIO42

J8

AZ_SDIN1/GPIO43

L8

AZ_SDIN2/GPIO44

M3

AZ_SDIN3/GPIO46

L6

AZ_SYNC

M4

AZ_RST#

L5

AZ_DOCK_RST#/GPM8#

H19

IMC_GPIO0

H20

IMC_GPIO1

H21

SPI_CS2#/IMC_GPIO2

F25

IDE_RST#/F_RST#/IMC_GPO3

D22

IMC_GPIO4

E24

IMC_GPIO5

E25

IMC_GPIO6

D23

IMC_GPIO7

218S7EALA11FG_BGA528_SB700

SB700

USB OC

HD AUDIO

INTEGRATED uC

Part 4 of 5

USBCLK/14M_25M_48M_OSC

ACPI / WAKE UP EVENTS

INTEGRATED uC

USB_RCOMP

USB_FSD13P
USB_FSD13N

USB MISC

USB_FSD12P
USB_FSD12N

USB 1.1

USB_HSD11P

USB_HSD11N

USB_HSD10P

USB_HSD10N

USB_HSD9P

USB_HSD9N

USB_HSD8P

USB_HSD8N

USB_HSD7P

USB_HSD7N

USB_HSD6P

USB_HSD6N

USB_HSD5P

USB_HSD5N

USB_HSD4P

USB 2.0

USB_HSD4N

USB_HSD3P

USB_HSD3N

GPIO

USB_HSD2P

USB_HSD2N

USB_HSD1P

USB_HSD1N

USB_HSD0P

USB_HSD0N

IMC_PWM0/IMC_GPIO10

SCL2/IMC_GPIO11

SDA2/IMC_GPIO12
SCL3_LV/IMC_GPIO13
SDA3_LV/IMC_GPIO14

IMC_PWM1/IMC_GPIO15

IMC_PWM2/IMC_GPO16
IMC_PWM3/IMC_GPO17

IMC_GPIO18
IMC_GPIO19
IMC_GPIO20
IMC_GPIO21
IMC_GPIO22
IMC_GPIO23
IMC_GPIO24
IMC_GPIO25

IMC_GPIO26
IMC_GPIO27
IMC_GPIO28
IMC_GPIO29
IMC_GPIO30
IMC_GPIO31
IMC_GPIO32
IMC_GPIO33
IMC_GPIO34
IMC_GPIO35
IMC_GPIO36
IMC_GPIO37
IMC_GPIO38
IMC_GPIO39
IMC_GPIO40
IMC_GPIO41

IMC_GPIO8
IMC_GPIO9

C8

USB_RCOMP

G8

E6
E7

F7
E8

USB20_P11

H11

USB20_N11

J10

USB20_P10

E11

USB20_N10

F11
A11

B11

USB20_P8

C10

USB20_N8

D10

USB20_P7

G11

USB20_N7

H12

USB20_P6

E12

USB20_N6

E14

USB20_P5

C12

USB20_N5

D12
B12

A12

USB20_P3

G12

USB20_N3

G14

USB20_P2

H14

USB20_N2

H15

USB20_P1

A13

USB20_N1

B13

USB20_P0

B14

USB20_N0

A14
A18

B18
F21
D21
F19
E20
E21
E19
D19
E18

G20
G21
D25
D24
C25
C24
B25
C23

B24
B23
A23
C22
A22
B22
B21
A21
D20
C20
A20
B20
B19
A19
D18
C18

1 2

09/04 update

R32311.8K_0402_1%

USB20_P11 <26>
USB20_N11 <26>

USB20_P10 <26>
USB20_N10 <26>

USB20_P8 <26>
USB20_N8 <26>

USB20_P7 <31>
USB20_N7 <31>

USB20_P6 <31>
USB20_N6 <31>

USB20_P5 <17>
USB20_N5 <17>

USB20_P3 <35>
USB20_N3 <35>

USB20_P2 <31>
USB20_N2 <31>

USB20_P1 <31>
USB20_N1 <31>

USB20_P0 <31>
USB20_N0 <31>

GPIO16 <23>
GPIO17 <23>

CLK_48M_USB <15>

Touch Screen (delete)

USB-11 New Card
USB-10 MiniCard(TV)
USB-9 Card Reader (delete)
USB-8 MiniCard(WWAN)
USB-7 Fingerprint
USB-6 Bluetooth
USB-5 USB Ca mera
USB-4 Left side
USB-3 Dock
USB-2 Left Side
USB-1 Right side
USB-0 Right side (S/W Debug Port)

STRAP PIN
STRAP PIN

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

SB700 USB/AC97

LA-4111P

20 47Thursday, November 15, 2007

E

0.2

of

A

[e-mail]

B

C

D

E

C51610P_0402_50V8J

12

12

Y4

25MHz_20pF_6X25000017

1 1

SATA_TXP0<24>
SATA_TXN0<24>

SATA_TXP1<24>
SATA_TXN1<24>

SATA_TXP2<31>
SATA_TXN2<31>

11/05 update

SATA_TXP3<24>
SATA_TXN3<24>

C51710P_0402_50V8J

12

10/09 update

C512 0.01U_0402_25V7K

1 2

C513 0.01U_0402_25V7K

1 2

C514 0.01U_0402_25V7K

1 2

C515 0.01U_0402_25V7K

1 2

C520 0.01U_0402_25V7K

1 2

C521 0.01U_0402_25V7K

1 2

C518 0.01U_0402_25V7K

1 2

C519 0.01U_0402_25V7K

1 2

11/06 update

2 2

11/05 update

+3VS

+1.2V_HT

3 3

BLM18PG121SN1D_0603

+3VS

L54

12

1U_0402_6.3V4Z

L55

BLM18PG121SN1D_0603

1U_0402_6.3V4Z

C522

12

12

R341

10M_0402_5%

R343 10K_0402_5%

1 2

SATA_LED#<34>

2

2

1

1

2

C524

1

SATA_X1

Change the PCB Footpr int from
Y_KDS_1BX25000CK1A_2P to

L

Y_6X25000017_2P

SATA_X2

SATA_STX_DRX_P0
SATA_STX_DRX_N0

SATA_RXN0_C<24>

SATA_RXP0_C<24>

SATA_STX_DRX_P1
SATA_STX_DRX_N1

SATA_RXN1_C<24>

SATA_RXP1_C<24>

SATA_STX_DRX_P2
SATA_STX_DRX_N2

SATA_RXN2_C<31>

SATA_RXP2_C<31>

SATA_STX_DRX_P3
SATA_STX_DRX_N3

SATA_RXN3_C<24>

SATA_RXP3_C<24>

SATA_CAL

R342 1K_0402_1%

+PLLVDD_SATA

C523
1U_0402_6.3V4Z

+XTLVDD_SATA

12

SATA_X1
SATA_X2

U15B

AD9

SATA_TX0P

AE9

SATA_TX0N

AB10

SATA_RX0N

AC10

SATA_RX0P

AE10

SATA_TX1P

AD10

SATA_TX1N

AD11

SATA_RX1N

AE11

SATA_RX1P

AB12

SATA_TX2P

AC12

SATA_TX2N

AE12

SATA_RX2N

AD12

SATA_RX2P

AD13

SATA_TX3P

AE13

SATA_TX3N

AB14

SATA_RX3N

AC14

SATA_RX3P

AE14

SATA_TX4P

AD14

SATA_TX4N

AD15

SATA_RX4N

AE15

SATA_RX4P

AB16

SATA_TX5P

AC16

SATA_TX5N

AE16

SATA_RX5N

AD16

SATA_RX5P

V12

SATA_CAL

Y12

SATA_X1

AA12

SATA_X2

W11

SATA_ACT#/GPIO67

AA11

PLLVDD_SATA

W12

XTLVDD_SATA

218S7EALA11FG_BGA528_SB700

SB700

Part 2 of 5

SATA PWR SERIAL ATA

HW MONITOR

IDE_IORDY

IDE_IRQ

IDE_A0
IDE_A1
IDE_A2

IDE_DACK#

IDE_DRQ

IDE_IOR#
IDE_IOW#
IDE_CS1#
IDE_CS3#

IDE_D0/GPIO15
IDE_D1/GPIO16
IDE_D2/GPIO17
IDE_D3/GPIO18
IDE_D4/GPIO19
IDE_D5/GPIO20
IDE_D6/GPIO21
IDE_D7/GPIO22
IDE_D8/GPIO23

ATA 66/100/133

IDE_D9/GPIO24
IDE_D10/GPIO25
IDE_D11/GPIO26
IDE_D12/GPIO27
IDE_D13/GPIO28
IDE_D14/GPIO29
IDE_D15/GPIO30

SPI_DI/GPIO12

SPI_DO/GPIO11
SPI_CLK/GPIO47

SPI_HOLD#/GPIO31

SPI_CS1#/GPIO32

LAN_RST#/GPIO13

SPI ROM

ROM_RST#/GPIO14

FANOUT0/GPIO3

FANOUT1/GPIO48
FANOUT2/GPIO49

FANIN0/GPIO50

FANIN1/GPIO51

FANIN2/GPIO52

TEMP_COMM
TEMPIN0/GPIO61
TEMPIN1/GPIO62
TEMPIN2/GPIO63

TEMPIN3/TALERT#/GPIO64

VIN0/GPIO53
VIN1/GPIO54
VIN2/GPIO55
VIN3/GPIO56
VIN4/GPIO57
VIN5/GPIO58
VIN6/GPIO59
VIN7/GPIO60

AVDD
AVSS

AA24
AA25
Y22
AB23
Y23
AB24
AD25
AC25
AC24
Y25
Y24

AD24
AD23
AE22
AC22
AD21
AE20
AB20
AD19
AE19
AC20
AD20
AE21
AB22
AD22
AE23
AC23

G6
D2
D1
F4
F3

U15
J1

M8
M5
M7

P5

11/13 update

P8
R8

THERMAL_DC

C6
B6
A6
A5
B5

A4
B4
C4
D4

LFB_ID0

D5

LFB_ID1

D6

LFB_ID2

A7
B7

F6
G7

C525

0.1U_0402_16V4Z

11/13 update

R1062 0_0402_5%

1 2

+SB_AVDD

1

2

BLM18PG121SN1D_0603

1

C526

2.2U_0603_6.3V4Z

2

+3VALW
+3VALW

CR_WAKE# <27>

HDD_HALTLED# <34>
SB_INT_FLASH_SEL <32>

WLOFF# <26>
BT_COMBO_EN# <26>
WWOFF# <26>

EC_THERM# <33>
AC_IN_D <33>

BT_OFF <31>
CAM_SHDN# <17>

L56

+3VALW

12

Local Frame B u f f er Strapping List
Copy from Becks.

LFB_ID0LFB_ID1LFB_ID2

Hynix

Qimonda

Samsung

000

001

001

LFB_ID0 to LFB_ID2 got internal PU 10K to S5.

LFB_ID2

R344 1K_0402_5%

R1032

1 2

10K_0402_5%@

1 2

10K_0402_5%@

R1033

11/05 update

11/13 update

LFB_ID1
LFB_ID0

1 2

R367 1K_0402_5%

1 2

R345 1K_0402_5%

1 2

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

SB700 SATA/IDE/SPI

LA-4111P

21 47Thursday, November 15, 2007

E

0.2

of

A

B

C

D

E

0.6A/50mil/4vias

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9

V5_VREF

AVDDC

L

L15
M12
M14
N13
P12
P14
R11
R15
T16

0.3A/30mil/2vias

L

L21
L22
L24
L25

0.1A/30mil/2vias ?

L

A17
A24
B17
J4
J5
L1
L2

G2
G4

A10
B10

+V5_VREF

AE7

+AVDDCK_3.3V

J16

+AVDDCK_1.2V

K17

+AVDDC

E9

+1.2V_SB_CORE

+1.2V_CKVDD

+S5_3V

R564 0_0805_5%

+S5_1.2V

+1.2_USB

1 2

R592 0_0805_5%

1 2

R593 0_0805_5%@

1 2

BLM18PG121SN1D_0603
C546 1U_0402_6.3V4Z

C545 1U_0402_6.3V4Z
C548 0.1U_0402_16V4Z
C551 0.1U_0402_16V4Z

C550 10U_0805_10V4Z

1 2

+

1 2

L65 0_0603_5%

+

1 2

C578

0.1U_0402_16V4Z

BLM18PG121SN1D_0603

+

L60

1 2
1 2

1 2

C55622U_A_4VM
C5591U_0402_6.3V4Z

12

C5611U_0402_6.3V4Z

12

C5621U_0402_6.3V4Z

12

C5630.1U_0402_16V4Z

12

C5640.1U_0402_16V4Z

12

C5650.1U_0402_16V4Z

12

+1.2VALW

C5741U_0402_6.3V4Z

12

C5751U_0402_6.3V4Z

12

2

2

1U_0603_10V4Z

1

1

L67

12
12
12
12
12
12

12
12

C57322U_A_4VM

C579

12

12

+3VALW

C52922U_A_4VM
C5321U_0402_6.3V4Z
C5341U_0402_6.3V4Z
C5381U_0402_6.3V4Z
C5371U_0402_6.3V4Z
C5270.1U_0402_16V4Z
C5400.1U_0402_16V4Z

12
12

+1.2VALW
+1.2V_HT

+1.2V_HT

L64 0_0603_5%

D14

CH751H-40PT_SOD323-2

+3VALW

C5852.2U_0603_6.3V4Z
C5860.1U_0402_16V4Z

+1.2VALW

C5691U_0402_6.3V4Z

12

C5700.1U_0402_16V4Z

12

R3461K_0402_5%

12

+5VS

21

+3VS

+3VS

1 1

10/03 update

L

2 2

L

L

3 3

C528 22U_A_4VM
C531 1U_0402_6.3V4Z

1 2

C530 1U_0402_6.3V4Z

1 2

C533 1U_0402_6.3V4Z

1 2

C549 1U_0402_6.3V4Z

1 2

C535 1U_0402_6.3V4Z

1 2

C539 1U_0402_6.3V4Z

1 2

C541 0.1U_0402_16V4Z

1 2

C542 0.1U_0402_16V4Z

1 2

0_0603_5%

R12

+3VS

+1.2V_HT

0.8A/50mil/4vias

+1.2V_HT

<1.25A/50mil/4vias

<1.25A/50mil/4vias?

+3VALW

1 2

C543 22U_A_4VM
C544 1U_0402_6.3V4Z

1 2

C547 1U_0402_6.3V4Z

1 2

C536 1U_0402_6.3V4Z

1 2

FBMA-L11-201209-221LMA30T_0805

C552 22U_A_4VM
C553 1U_0402_6.3V4Z
C555 1U_0402_6.3V4Z
C554 1U_0402_6.3V4Z
C558 1U_0402_6.3V4Z
C557 0.1U_0402_16V4Z
C560 0.1U_0402_16V4Z

FBMA-L11-201209-221LMA30T_0805

C566 22U_A_4VM
C567 10U_0805_10V4Z
C568 10U_0805_10V4Z
C571 0.1U_0402_16V4Z
C572 0.1U_0402_16V4Z

FBMA-L11-201209-221LMA30T_0805

C576 10U_0805_10V4Z
C577 10U_0805_10V4Z
C580 1U_0402_6.3V4Z
C581 1U_0402_6.3V4Z
C583 0.1U_0402_16V4Z
C582 0.1U_0402_16V4Z
C584 0.1U_0402_16V4Z

+

1 2
1 2
1 2
1 2
1 2
1 2

12

+

1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2

12

L61

+

12

L63

+

L66

L

0.45A/30mil/3vias

L

+3.3V_SB_IDE

+PCIE_VDDR

12

+1.2V_SATA

12

12

+AVDD_USB

12

0.45A/40mil/3vias ?

U15C

L9

VDDQ_1

M9

VDDQ_2

T15

VDDQ_3

U9

VDDQ_4

U16

VDDQ_5

U17

VDDQ_6

V8

VDDQ_7

W7

VDDQ_8

Y6

VDDQ_9

AA4

VDDQ_10

AB5

VDDQ_11

AB21

VDDQ_12

Y20

VDD33_18_1

AA21

VDD33_18_2

AA22

VDD33_18_3

AE25

VDD33_18_4

P18

PCIE_VDDR_1

P19

PCIE_VDDR_2

P20

PCIE_VDDR_3

P21

PCIE_VDDR_4

R22

PCIE_VDDR_5

R24

PCIE_VDDR_6

R25

PCIE_VDDR_7

AA14

AVDD_SATA_1

AB18

AVDD_SATA_4

AA15

AVDD_SATA_2

AA17

AVDD_SATA_3

AC18

AVDD_SATA_5

AD17

AVDD_SATA_6

AE17

AVDD_SATA_7

A16

AVDDTX_0

B16

AVDDTX_1

C16

AVDDTX_2

D16

AVDDTX_3

D17

AVDDTX_4

E17

AVDDTX_5

F15

AVDDRX_0

F17

AVDDRX_1

F18

AVDDRX_2

G15

AVDDRX_3

G17

AVDDRX_4

G18

AVDDRX_5

218S7EALA11FG_BGA528_SB700

SB700

Part 3 of 5

PCI/GPIO I/O

IDE/FLSH I/O

POWER

A-LINK I/O

3.3V_S5 I/OCORE S5

SATA I/O

USB_PHY_1.2V_1
USB_PHY_1.2V_2

PLL CLKGEN I/O

USB I/O

CORE S0

CKVDD_1.2V_1
CKVDD_1.2V_2
CKVDD_1.2V_3
CKVDD_1.2V_4

S5_3.3V_1
S5_3.3V_2
S5_3.3V_3
S5_3.3V_4
S5_3.3V_5
S5_3.3V_6
S5_3.3V_7

S5_1.2V_1
S5_1.2V_2

AVDDCK_3.3V
AVDDCK_1.2V

U15E

SB700

T10

AVSS_SATA_1

U10

AVSS_SATA_2

U11

AVSS_SATA_3

U12

AVSS_SATA_4

V11

AVSS_SATA_5

V14

AVSS_SATA_6

W9

AVSS_SATA_7

Y9

AVSS_SATA_8

Y11

AVSS_SATA_9

Y14

AVSS_SATA_10

Y17

AVSS_SATA_11

AA9

AVSS_SATA_12

AB9

AVSS_SATA_13

AB11

AVSS_SATA_14

AB13

AVSS_SATA_15

AB15

AVSS_SATA_16

AB17

AVSS_SATA_17

AC8

AVSS_SATA_18

AD8

AVSS_SATA_19

AE8

AVSS_SATA_20

A15

AVSS_USB_1

B15

AVSS_USB_2

C14

AVSS_USB_3

D8

AVSS_USB_4

D9

AVSS_USB_5

D11

AVSS_USB_6

D13

AVSS_USB_7

D14

AVSS_USB_8

D15

AVSS_USB_9

E15

AVSS_USB_10

F12

AVSS_USB_11

F14

AVSS_USB_12

G9

AVSS_USB_13

H9

AVSS_USB_14

H17

AVSS_USB_15

J9

AVSS_USB_16

J11

AVSS_USB_17

J12

AVSS_USB_18

J14

AVSS_USB_19

J15

AVSS_USB_20

K10

AVSS_USB_21

K12

AVSS_USB_22

K14

AVSS_USB_23

K15

AVSS_USB_24

H18

PCIE_CK_VSS_1

J17

PCIE_CK_VSS_2

J22

PCIE_CK_VSS_3

K25

PCIE_CK_VSS_4

M16

PCIE_CK_VSS_5

M17

PCIE_CK_VSS_6

M21

PCIE_CK_VSS_7

P16

PCIE_CK_VSS_8

F9

AVSSC

Part 5 of 5

218S7EALA11FG_BGA528_SB700

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8

VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42

GROUND

VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50

PCIE_CK_VSS_9
PCIE_CK_VSS_10
PCIE_CK_VSS_11
PCIE_CK_VSS_12
PCIE_CK_VSS_13
PCIE_CK_VSS_14
PCIE_CK_VSS_15
PCIE_CK_VSS_16
PCIE_CK_VSS_17
PCIE_CK_VSS_18
PCIE_CK_VSS_19
PCIE_CK_VSS_20
PCIE_CK_VSS_21

AVSSCK

A2
A25
B1
D7
F20
G19
H8
K9
K11
K16
L4
L7
L10
L11
L12
L14
L16
M6
M10
M11
M13
M15
N4
N12
N14
P6
P9
P10
P11
P13
P15
R1
R2
R4
R9
R10
R12
R14
T11
T12
T14
U4
U14
V6
Y21
AB1
AB19
AB25
AE1
AE24

P23
R16
R19
T17
U18
U20
V18
V20
V21
W19
W22
W24
W25

L17

+AVDDCK_1.2V

+AVDDCK_3.3V

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

L68

12

BLM18PG121SN1D_0603

L69

BLM18PG121SN1D_0603

2007/08/02 2008/08/02

+1.2V_HT

C5872.2U_0603_6.3V4Z

12

C5880.1U_0402_16V4Z

12

12

+3VS

C5892.2U_0603_6.3V4Z

12

C5900.1U_0402_16V4Z

12

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

SB700 PWR/GND

LA-4111P

22 47Thursday, Novemb e r 15, 2007

E

0.2

A

[e-mail]

B

C

D

E

REQUIRED STRAPS

PCI_CLK3

PULL

1 1

09/29 update

2 2

HIGH

PULL
LOW

PCICLK2<19>

CLK_PCI_SIO<19,32>

PCI_CLK4<19>
PCI_CLK5<19>

CLK_PCI_EC<19,33>

LPCCLK1<19>
RTC_CLK<19>
HDARST#<20,33>

GPIO17<20>
GPIO16<20>

BOOTFAIL
TIMER
ENABLED

BOOTFAIL
TIMER
DISABLED

DEFAULT

+3VS +3VS +3VS +3VS +3VALW +3VALW +3VALW +3VALW +3VALW +3VALW

R347

10K_0402_5%

@

R357

10K_0402_5%

USE
DEBUG
STRAPS

IGNORE
DEBUG
STRAPS

DEFAULT

12

R348

@

12

R358

12

10K_0402_5%

12

10K_0402_5%

PCI_CLK4 PCI_CLK5

RESERVED

R349

@

R359

@

RESERVED

12

10K_0402_5%

12

10K_0402_5%

NOTE: SB700 HAS INTERNAL 15K PULL UP RESISTOR FOR RTC_CLK

RTC_CLKLPC_CLK1

INTERNAL
RTC

DEFAULT

EXT. RTC

(PD on X1,
apply
32KHz to
RTC_CLK)

12

R353

@

12

R363

@

R350

10K_0402_5%

@

R360

10K_0402_5%

@

12

12

AZ_RST_CD#

ENABLE PCI
MEM BOOT

DISABLE PCI
MEM BOOT

DEFAULT

12

R351

10K_0402_5%

@

12

R361

10K_0402_5%

CLKGEN
ENABLED

CLKGEN
DISABLED

DEFAULT

R352

10K_0402_5%

@

R362

10K_0402_5%

12

10K_0402_5%

12

2.2K_0402_5%

LPC_CLK0

EC

ENABLED

EC

DISABLED

DEFAULT

12

R354

10K_0402_5%

@

12

R364

10K_0402_5%

GP17

GP16PCI_CLK2

Interna l pull up

H,H = Reserved

H,L = SPI ROM

L,H = LPC ROM (Default)

L,L = FWH ROM

12

12

R356

R355

10K_0402_5%

10K_0402_5%

@

@

12

12

R365

R366

2.2K_0402_5%

2.2K_0402_5%

@

DEBUG STRAPS

SB700 HAS 15K IN T E RN AL PU FOR PCI_AD[28:23]

12

2.2K_0402_5%

PCI_AD27 PCI_AD26

USE PCI
PLL

DEFAULT

BYPASS
PCI PLL

R374

@

12

2.2K_0402_5%

USE ACPI
BCLK

DEFAULT

BYPASS
ACPI
BCLK

R375

@

PCI_AD28

3 3

PCI_AD28<19>
PCI_AD27<19>
PCI_AD26<19>
PCI_AD25<19>
PCI_AD24<19>
PCI_AD23<19>

4 4

PULL
HIGH

PULL
LOW

USE
LONG
RESET

DEFAULT

USE
SHORT
RESET

R373

@

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

12

2.2K_0402_5%

C

PCI_AD25 PCI_AD24

12

2.2K_0402_5%

USE DEFAULT
PCIE STRAPS

DEFAULT

USE EEPROM
PCIE STRAPS

R377

@

USE IDE
PLL

DEFAULT

BYPASS IDE
PLL

R376

@

2007/08/02 2008/08/02

PCI_AD23

RESERVED

12

R378

2.2K_0402_5%

@

Compal Secret Data

Deciphered Date

12

2.2K_0402_5%

D

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

SB700 STRAPS

LA-4111P

23 47Thursday, Novemb e r 15, 2007

E

of

0.2

A

B

C

D

E

HDD Connector

+5VS

1

1 1

C593

10U_0805_10V4Z

2

0.1U_0402_16V4Z

1

C594

2

1

C591

2

0.1U_0402_16V4Z

1

C595

2

Pleace near HD CONN (JP23)

+3VS +3VS_HDD1

R1009

@

1 2

0_0805_5%

C1032

@

10U_0805_10V4Z

1

2

0.1U_0402_16V4Z

1

1

C1034

@

2

0.1U_0402_16V4Z

1

C1035

2

@

C1033

@

2

Pleace near HD CONN (JP23)

JP9

0.1U_0402_16V4Z

0.1U_0402_16V4Z

GND

GND

GND

GND
GND
GND

GND

Reserved

GND

SUYIN_127072FR022G523_RVCONN@

11/14 update

1
2

A+

3

A-

4
5

B-

6

B+

7

8

V33

9

V33

10

V33

11
12
13
14

V5

15

V5

16

V5

17
18
19
20

V12

21

V12

22

V12

SATA_TXP0

0.01U_0402_16V7K

SATA_RXN0 SATA_RXN0_C

0.01U_0402_16V7K

Near CONN side.

+3VS_HDD1

+5VS

SATA_TXN0

C592

12

SATA_RXP0_CSATA_RXP0

C596

12

SATA_TXP0 <21>
SATA_TXN0 <21>

SATA_RXN0_C <21>
SATA_RXP0_C <21>

2 2

+5VS

Max 3A

C601

10U_0805_10V4Z

1

2

0.1U_0402_16V4Z

1

1

2

C602

C603

2

0.1U_0402_16V4Z

Pleace near HD CONN (JP23)

+3VS +3VS_HDD2

R1010

@

1 2

0_0805_5%

C1036

@

10U_0805_10V4Z

3 3

Pleace near HD CONN (JP23)

1

2

0.1U_0402_16V4Z

1

1

C1037

@

2

C1038

@

2

0.1U_0402_16V4Z

1

C604

2

0.1U_0402_16V4Z

1

C1039

2

@

0.1U_0402_16V4Z

+5VS+3VS_HDD2

JP10

VCC5
VCC5
VCC5
VCC3
VCC3
VCC3
GND
GND

GND

1

GND

2

TX+

3

TX-

GND

RX-

RX+
GND
GND

GND

TYCO_2023087CONN@

0.01U_0402_16V7K

4

SATA_RXN1 SATA_RXN1_C

5

SATA_RXP1 SATA_RXP1_C

6

0.01U_0402_16V7K

7
8

17

Near CONN side.

SATA_TXP1
SATA_TXN1

C605

12

C606

12

SATA_TXP1 <21>
SATA_TXN1 <21>

SATA_RXN1_C <21>
SATA_RXP1_C <21>

16
15
14
13
12
11
10

9

18

11/14 update

CD-ROM Connector

Multi-Bay Connector-option

+5VS

Placea caps. near ODD CONN.

0.1U_0402_16V4Z

1U_0603_10V4Z

C613

1

C614

2

4 4

10U_0805_10V4Z

1

1

C615

2

1

C616
10U_0805_10V4Z

2

2

JP11

1

GND

2

A+

3

A-

GND

B-

B+

GND

DP

V5
V5

MD
GND
GND

SUYIN_127382FR013G509ZRCONN@

0.01U_0402_16V7K

4

SATA_RXN3 SATA_RXN3_C

5

SATA_RXP3

6

0.01U_0402_16V7K

7

R970 0_0402_5%

8

1 2
9
10
11
12
13

+5VS

SATA_TXP3
SATA_TXN3

C612

12

SATA_RXP3_C

C611

12

Near CONN side.

11/14 update

SATA_TXP3 <21>
SATA_TXN3 <21>

SATA_RXN3_C <21>
SATA_RXP3_C <21>

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

HDD/CDROM

LA-4111P

24 47Thursday, November 15, 2007

E

0.2

of

A

[e-mail]

LAN_DO
LAN_DI
LAN_SK_LAN_LINK#
LAN_CS

1 1

Place Close to Chip

1 2

PCIE_PTX_IRX_P3
PCIE_PTX_IRX_N3

ISOLATEB
LAN_X1

LAN_X2

C485 0.1U_0402_16V7K

PCIE_PTX_C_IRX_P3<10>
PCIE_PTX_C_IRX_N3<10>

+3VS

12

R1060
1K_0402_1%

2 2

1

2

ISOLATEB

R1061
15K_0402_5%

10/09 update Change the PCB Footprint from

Y5

LAN_X1 LAN_X2

12

25MHz_20pF_6X25000017

C653

27P_0402_50V8J

27P_0402_50V8J

12

C488 0.1U_0402_16V7K

12

PCIE_ITX_C_PRX_P3<10>
PCIE_ITX_C_PRX_N3<10>

CLK_PCIE_LAN<15>

CLK_PCIE_LAN#<15>

CLKREQ_LAN#<15>

PLT_RST#<11,14,19,26,27,32,33>

R1059 2.49K_0402_1%

LAN_PCIE_WAKE#<20>

Y_KDS_1BX25000CK1A_2P to

L

Y_6X25000017_2P

1

C654

2

B

1 2

R1055 3.6K_0402_5%

U17

4

DO

3

DI

2

SK

1

CS

AT93C46-10SI-2.7_SO8

R1058 10K_0402_5%

U20

20

HSOP

21

HSON

15

HSIP

16

HSIN

17

REFCLK_P

18

REFCLK_M

25

CLKREQB

27

PERSTB

46

RSET

26

LANWAKEB

28

ISOLATEB

41

CKXTAL1

42

CKXTAL2

23

NC

24

NC

7

GND

14

GND

31

GND

47

GND

22

GNDTX

RTL8102EL-GR_LQFP48_7X7

5

GND

6

NC

7

NC

8

VCC

12

RTL8102EL

+3V_LAN

2

C1078

1

0.1U_0402_16V4Z

LED3/EEDO

LED2/EEDI/AUX

LED1/EESK

EECS

LED0

MDIP0
MDIN0
MDIP1
MDIN1

VCTRL12A

VDDTX
DVDD12
DVDD12
DVDD12
DVDD12

VCTRL12D

VDD33
VDD33

AVDD33

11/13 update

NC
NC
NC
NC

NC

NC
NC

NC
NC

+3V_LAN

LAN_DO

33

LAN_DI

34

LAN_SK_LAN_LINK#

35

LAN_CS

32

LAN_ACTIVITY#

38

LAN_MDI0+

2

LAN_MDI0-

3

LAN_MDI1+

5

LAN_MDI1-

6
8
9
11
12

4

VCTRL12

48
19

30
36
13
10

39
44

45
29

37
1

40
43

C

+EVDD12
+LAN_VDD12

+LAN_VDD12
+3V_LAN

LAN_POWER_OFF<33>

Close to Pin10,13,30,36

2

C628

0.1U_0402_16V4Z

1

D

+3VALW

R1056

100K_0402_5%

1 2

R1057 10K_0402_5%

2

C629

0.1U_0402_16V4Z

1

Close to Pin19

2

1

C1077

1 2

0.1U_0402_16V4Z

2

C630

0.1U_0402_16V4Z

1

VCTRL12

C1081
1U_0402_6.3V4Z

PJP605

1 2

PAD-OPEN 4x4m

S

2

G

2

Q144
SI2301BDS-T1-E3_SOT23-3

1

+LAN_VDD12

2

C631

0.1U_0402_16V4Z

1

Close to Pin48

0.1U_0402_16V4Z

1

C1079

2

10U_0805_10V4Z@

+EVDD12

2

C1082

0.1U_0402_16V4Z

1

E

D

40 mils

13

+3V_LAN

Close to Pin1,37,29

2

C620

0.1U_0402_16V4Z

1

2

C621

0.1U_0402_16V4Z

1

+3V_LAN

2

C622

0.1U_0402_16V4Z

1

Close to Pin45

+LAN_VDD12

2

C1080

1

2

C632

0.1U_0402_16V4Z

1

1

C633

10U_0805_10V4Z@

2

3 3

10/29 update

C648 0.01U_0402_16V7K

1 2

C647 0.01U_0402_16V7K

1 2

LAN_MDI0+
LAN_MDI0­LAN_CT0

LAN_CT1
LAN_MDI1+
LAN_MDI1-

U19

1

RD+

2

RD-

3

CT

4

NC

5

NC

6

CT

7

TD+
TD-8TX-

LEF8423A-R

RX+

RJ45_MIDI0+

16

RJ45_MIDI0-

15

RX-

RJ45_CT0

14

CT

13

NC

12

NC

RJ45_CT1

11

CT

RJ45_MIDI1+

10

TX+

RJ45_MIDI1-

9

C1083 0.01U_0603_100V7-M
C1084 0.01U_0603_100V7-M

1 2
1 2

RJ45_MIDI0+ <35>
RJ45_MIDI0- <35>

RJ45_MIDI1+ <35>
RJ45_MIDI1- <35>

RJ45_CT0_C
RJ45_CT1_C

75_0402_1%
R394

1 2
1 2

R396
75_0402_1%

RJ45_GND

C658

1000P_1206_2KV7K

LAN_ACTIVITY#

1

2

11/05 update

LAN_SK_LAN_LINK#

4 4

11/09 update

R391 300_0402_5%

1

C656
68P_0402_50V8K

@

2

2

C657

@

68P_0402_50V8K

1

R395 300_0402_5%

+3V_LAN

12

RJ45_MIDI1-

RJ45_MIDI1+

RJ45_MIDI0-

RJ45_MIDI0+

11/09 update

+3V_LAN

12

LAN Conn.

JRJ45

13

Yellow LED+

14

Yellow LED-

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

11

Green LED+

12

Green LED-

FOX_JM36113-P1122-7F

CONN@

1

C661

0.1U_0402_16V4Z

2

SHLD1

DETECT PIN1

DETCET PIN2

SHLD1

1

C662

4.7U_0805_10V4Z

2

16
9

10
15

LANGND

9/20 DC234001G00

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

RTL8111C/8102E 10/100/1000 LAN

LA-4111P

25 47Thursday, November 15, 2007

E

of

0.2

A

Mini Card Slot 1---WLAN

+3VS +1.5VS+3VS_WLAN +1.5VS_WLAN +3VALW_WLAN

Max 1A Max 0.5A

R407

12

0_0805_5%

C665

0.1U_0402_16V4Z

1 1

CH_DATA<31>

CH_CLK<31>

CLKREQ_MCARD2#<15>

CLK_PCIE_MCARD2#<15>

CLK_PCIE_MCARD2<15>

PCIE_PTX_C_IRX_N2<10>
PCIE_PTX_C_IRX_P2<10>

PCIE_ITX_C_PRX_N2<10>
PCIE_ITX_C_PRX_P2<10>

+3VS_WLAN

1

1

2

R47 0_0603_5%

C666

4.7U_0805_10V4Z

2

MINI_PCIE_WAKE#
CH_DATA
CH_CLK

1 2

11/09 update

CH_CLK

R49

BT_COMBO_EN#<21>

2 2

1 2

0_0402_5%

4.7K_0402_5%

12

R48

09/29 update

R406

1 2

0_0805_5%

C668

0.01U_0402_16V7K

JP14

1

1

3

3

5

5

7

7

9

9
111112
131314
151516

171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
515152

G153G254G355G3

1

2

0.1U_0402_16V4Z

2

2

4

4

6

6

8

8

10

10

12
14
16

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

CONN@

56

FOX_AS0B226-S99N-7F

9/20 SP01000HS00/SP01000LX00
9/20 STANDOFF (H=7.5 mm) ES000000D00

1

C669

2

WL_OFF#
PLT_RST#

SMB_CK_CLK1
SMB_CK_DAT1

WL_LED#

B

1

C670

4.7U_0805_10V4Z

2

+3VS_WLAN
+1.5VS_WLAN

+3VALW_WLAN

Max 0.3A

1

2

R52

1 2

0_0402_5%

USB20_N8 <20>
USB20_P8 <20>

WL_LED# <34>

R1043 0_0603_5%@

1 2

R1042 0_0603_5%

1 2

C667

0.1U_0402_16V4Z

WLOFF# <21>

+3VALW

+3VS_WLAN

C

+3VALW +3VS +1.5VS

Mini Card Slot 2---TV tuner / WWAN / Robson

R971 0_0603_5%

12

R972 0_0603_5%@

12

1

C671

MINI_PCIE_WAKE#<20>

CLKREQ_MCARD1#<15>

CLK_PCIE_MCARD1#<15>

CLK_PCIE_MCARD1<15>

PCIE_PTX_C_IRX_N5<10>

PCIE_PTX_C_IRX_P5<10>

PCIE_ITX_C_PRX_N5<10>

PCIE_ITX_C_PRX_P5<10>

+3VS_MINI

11/09 update

0.1U_0402_16V4Z

R401 0_0603_5%

1 2

C738

@

39P_0402_50V8J

2

1

2

1

2

D

Max 2.7A

L78

1 2

0_1206_5%

C784

@

0.1U_0402_16V7K

JP13

1

1

3

3

5

5

7

7

9

9
111112
131314
151516

171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
515152

0.01U_0402_16V7K

1

C785

2

0.1U_0402_16V4Z

2
4
6
8

10

G153G254G355G3

CONN@

56

FOX_AS0B226-S99N-7F

C786

2
4
6
8
10
12
14
16

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

9/20 SP01000HS00/SP01000LX00

+3VS_MINI +1.5VS_MINI+3VALW_WWAN+3VS_MINI

4.7U_0805_10V4Z

1

C787

2

SMB_CK_CLK1
SMB_CK_DAT1

WW_LED#

1

2

UIM_PWR
UIM_DATA
UIM_CLK
UIM_RST
UIM_VPP

WW_OFF#
PLT_RST#

+3VS_MINI
+1.5VS_MINI

1 2

0_0402_5%

Max 0.5A

L79

@

0_0805_5%

C781

@

0.01U_0402_16V7K

R53

+3VALW_WWAN

Max 0.3A

USB20_N10 <20>
USB20_P10 <20>

WW_LED# <34>

12

4.7U_0805_10V4Z

1

@

2

0.1U_0402_16V4Z

WWOFF# <21>

E

C782

1

2

1

C783

@

2

9/20 STANDOFF (H=7.5 mm) ES000000D00

New Card

C681

0.1U_0402_16V4Z

12

C679

0.1U_0402_16V4Z

12

0.1U_0402_16V4Z

Max 0.275A

+3VALW

3 3

12

C680

PLT_RST#<11,14,19,25,27,32,33>

SYSON<33,34,36,40>
SUSP#<28,33,36,38,41>

EXP_CPPE#<20>

Express Card Power Switch

+1.5VS

+3VS

PLT_RST#

EXP_CPPE#

U21

12

1.5Vin

14

1.5Vin

2

3.3Vin

4

3.3Vin
AUX_IN17AUX_OUT

6

SYSRST#

20

SHDN#

1

STBY#

10

CPPE#

9

CPUSB#

THERMAL_PAD

18

RCLKEN

R5538D001-TR-F_QFN20_4X4~D

1.5Vout

1.5Vout

3.3Vout

3.3Vout

OC#

PERST#

GND

11
13

3
5

15
19
8
16

NC

7

21

+3V_PEC

PERST#

+1.5VS_PEC

Max 0.65A

+3VS_PEC

Max 1.3A

USE TI TPS2231MRGPR

Near to Express Card slot.

USB20_N11<20>

USB20_P11<20>

SMB_CK_CLK1<20>
SMB_CK_DAT1<20>

+1.5VS_PEC

CLKREQ_NCARD#<15>

CLK_PCIE_NCARD#<15>

4 4

CLK_PCIE_NCARD<15>

PCIE_PTX_C_IRX_N0<10>
PCIE_PTX_C_IRX_P0<10>

PCIE_ITX_C_PRX_N0<10>
PCIE_ITX_C_PRX_P0<10>

A

+3V_PEC

+3VS_PEC

EXP_CPPE#

SMB_CK_CLK1
SMB_CK_DAT1

MINI_PCIE_WAKE#

PERST#

CLKREQ_NCARD#
EXP_CPPE#

9/20 SP02000B000

JEXP

1

GND

2

USB_D-

3

USB_D+

4

CPUSB#

5

RSV

6

RSV

7

SMB_CLK

8

SMB_DATA

9

+1.5V

10

+1.5V

11

WAKE#

12

+3.3VAUX

13

PERST#

14

+3.3V

15

+3.3V

16

CLKREQ#

17

CPPE#

18

REFCLK-

19

REFCLK+

20

GND

21

PERn0

22

PERp0

23

GND

24

PETn0

25

PETp0

26

GND

27

GND

28

GND

SANTA_130801-5_LTCONN@

09/13 Update

+3VS_PEC

C677

+1.5VS_PEC

C683

+3V_PEC

C684

4.7U_0805_10V4Z

1

C678

2

0.1U_0402_16V4Z

4.7U_0805_10V4Z

1

C682

2

0.1U_0402_16V4Z

4.7U_0805_10V4Z

1

C685

2

0.1U_0402_16V4Z

B

1

2

1

2

1

2

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

11/09 update

Compal Secret Data

Deciphered Date

+3VS_MINI

UIM_PWR
UIM_DATA
UIM_CLK
UIM_RST
UIM_VPP

R1037

1 2

10K_0402_5%@

D

JP6

1

1

2

2

3

3

4

4

5

5

6

6

G1

7

7

G2

ACES_88266-07001

CONN@

UIM_PWRUIM_DATA

9/20 SP02000IQ00

8
9

0.1U_0402_16V4Z

1

1

C1071

C1070

4.7U_0805_10V4Z

2

2

Title

WLAN/TV tuner/ E xpress Card

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

LA-4111P

26 47Thursday, November 15, 2007

E

0.2

of

A

[e-mail]

B

C

D

E

+VCC_OUT +VCC_4IN1

+3VS

C895

0.1U_0402_16V4Z@

1 1

11/06 update

U22

3

IN

4

EN

1

2

GND

G5250C2T1U_SOT23-5@

2

reserved power circuit

40mil

1

OUT

5

OUT

C896

@

1U_0603_10V4Z

12

1

2

R123

@

150K_0402_5%

+VCC_4IN1 +VCC_4IN1

XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
XD_SD_D4
XD_SD_D5
XD_SD_D6
XD_SD_D7

SDCMD_MSBS_XDWE#
XDWP#_SDWP#
XD_ALE
XD_CD#
XD_RB#
XD_RE#
XDCE#
XD_CLE

Use 0805 type and over 20 mils
trace width on both side

+VCC_4IN1+VCC_OUT

R383

1 2

0_0805_5%

C689

10U_0805_10V4Z

2 2

3 3

11/13 update

CR_CPPE#<20>

CR_WAKE#<21>

1

2

+3VS

12

R124
10K_0402_5%

2

G

Q54

1 3

D

S

2N7002_SOT23-3
0_0402_5%

1 2

R369

1

C694

0.1U_0402_16V4Z

2

CPPE#

XDCD0#_SDCD#

470_0402_5%

PCIE_PTX_C_IRX_N1<10>
PCIE_PTX_C_IRX_P1<10>

R370

+5VS_LED

12

21

D5
HT-F196BP5_WHITE

CLK_PCIE_MCARD0#<15>

CLK_PCIE_MCARD0<15>

PCIE_ITX_C_PRX_N1<10>
PCIE_ITX_C_PRX_P1<10>

C693 0.1U_0402_16V7K
C697 0.1U_0402_16V7K

11/10 update

13

D

Q53

2

G

2N7002_SOT23-3

S

4.7K_0402_5%

R454

12

11/06 update

SDCLK

R413

@

100_0402_5%

1 2
2

C902

@

100P_0402_25V8K

L

11/06 update

1 2
1 2

+3VS_CR

PLT_RST#<11,14,19,25,26,32,33>

+VCC_OUT

White LED: VF=3V, IF = 10mA, Res = 200 ohm

1

Place R413,C902 close to JREAD.20; R412,C901
close to JREAD.26; R411,C900 close to JREAD.37

PCIE_PTX_IRX_N1
PCIE_PTX_IRX_P1

R114

10K_0402_1%

10K_0402_5%

CPPE#

XDCD1#_MSCD#
XDCD0#_SDCD#

At least 20mils

L

use for PWR_EN#

CR_LED

8mA sink current

Card Reader Connector

JREAD

3

XD-VCC

32

XD-D0

10

9
8
7
6
5
4

34
33
35
40
39
38
37
36

11
31

41
42

MSCLK XDCE#

R412

@

100_0402_5%

C901

@

100P_0402_25V8K

APREXT

12

12mil

R409

12

T45PAD

7 IN 1 CONN

XD-D1
XD-D2
XD-D3
XD-D4
XD-D5
XD-D6
XD-D7

XD-WE
XD-WP
XD-ALE
XD-CD
XD-R/B
XD-RE
XD-CE
XD-CLE

7IN1 GND
7IN1 GND

7IN1 GND
7IN1 GND

TAITW_R015-B10-LMCONN@

R411

@

100_0402_5%

1 2
2

1

11
12

38
39

13
14

15
16

17

21

C900

@

100P_0402_25V8K

Power Circuit

D3 Normal 30mA Deepest 3mA

U23

3

APCLKN

4

APCLKP

9

APRXN

8

APRXP
APTXN

APTXP

7

APREXT

PCIES_EN
PCIES

1

XRSTN

2

XTEST

SEEDAT
SEECLK

CR1_CD1N
CR1_CD0N

CR1_PCTLN

CR1_LEDN

JMB385-LGEZ0A_LQFP48_7X7

1 2
2

1

58mA

1mA

JMB385

SD-VCC

MS-VCC

SD_CLK
SD-DAT0
SD-DAT1
SD-DAT2
SD-DAT3
SD-DAT4
SD-DAT5
SD-DAT6
SD-DAT7

SD-CMD

SD-CD-SW
SD-WP-SW

MS-SCLK

MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3

MS-INS

MS-BS

APVDD

APV18
TAV33

DV33

45mA

DV33
DV33
DV18

25mA

DV18

MDIO0
MDIO1
MDIO2
MDIO3
MDIO4
MDIO5
MDIO6
MDIO7
MDIO8

MDIO9
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14

APGND

GND
GND
GND
GND

21
28

20
14
12
30
29
27
23
18
16
25
1

2

26
17
15
19
24
22
13

5
10
30

19
20
44
18
37

48
47
46
45
43
42
41
40
29
28
27
26
25
23
22

34

NC

35

NC

36

NC

6
24

31
32
33

SDCLK
XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
XD_SD_D4
XD_SD_D5
XD_SD_D6
XD_SD_D7
SDCMD_MSBS_XDWE#
XDCD0#_SDCD#

XDWP#_SDWP#

MSCLK
XD_SD_MS_D0
XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
XDCD1#_MSCD#
SDCMD_MSBS_XDWE#

+1.8VS_OUT

20mil

C892

Ripple 100mV

Ripple 100mV

Ripple 250mV

Ripple 250mV

XD_SD_MS_D0

XD_SD_MS_D1
XD_SD_MS_D2
XD_SD_MS_D3
SDCMD_MSBS_XDWE#
SDCLK_MSCLK_XDCE#
XDWP#_SDWP#
XD_CLE
XD_SD_D4
XD_SD_D5
XD_SD_D6
XD_SD_D7
XD_RE#
XD_RB#
XD_ALE

place near pin 5 and
pin 10.

0.1U_0402_16V4Z

1

C688

2

10U_0805_10V4Z

C6950.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

11/07 update

XDWP#_SDWP#
XD_RB#

1000P_0402_50V7K

1

C687

2

12

1

C691

2

1

C686

2

R457 22_0402_5%
R456 22_0402_5%
R455 22_0402_5%

L

1

1

C893

2

2

0.1U_0402_16V4Z

R1021

0_0603_5%

1

C692

2

0.1U_0402_16V4Z

+1.8VS_OUT

1

C690

0.1U_0402_16V4Z

2

12
12
12

Place R455~R457 close to U23.42

+VCC_4IN1

R45 10K_0402_5%

12
12

R106 10K_0402_5%

11/06 update

R1020

12

0_0603_5%

+3VS+3VS_CR

12

SDCLK
MSCLK
XDCE#

+1.8VS

11/06 update

D40

R121 4.7K_0402_5%

R111 4.7K_0402_5%

1

12

R40510K_0402_5%

12

R12210K_0402_5%

12

R86200K_0402_5%

XDCD0#_SDCD#

XDCD1#_MSCD#

2
3

DAN202U_SC70

Strap pin for JMicro

+3VS_CR

12

12

XD_CD#

1

C696

270P_0402_50V7K

2

XD_CLE
XD_ALE

XD_RE#

+3VS_CR

11/06 update

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

PCI-E I/F Card Reader-JM385

LA-4111P

27 47Thursday, November 15, 2007

E

of

0.2

A

B

C

D

E

CODEC POWER

R885

1 2

+3VS

BLM18BD601SN1D_0603

1 1

+3VDD_CODEC +VDDA_CODEC

0.1U_0402_16V4Z

1

C733

C734

2

1U_0603_10V4Z

+3VS_HDA

R978

1 2

1

2

BLM18BD601SN1D_0603

1

C1046

0.1U_0402_16V4Z

2

+VDDA_CODEC_R+3VS

1

C730

2

0.1U_0402_16V4Z

R979

1 2

0_0603_5%

1

C731
1U_0603_10V4Z

2

W=40Mil

1 2

C728 0.1U_0402_16V4Z

SUSP#<26,33,36,38,41>

+5VALW +VDDA_CODEC

U32

1

IN

OUT

2

GND

3

SHDN

BYP

G9191-475T1U_SOT23-5

5

4

1

2

1

C732

0.1U_0402_16V4Z

2

C729

2.2U_0805_16V4Z

(4.75V(4.56~4.94V))

300mA

U27

12

SENSEB#

9

DVDD_CORE*

1

DVDD_CORE

25

AVDD1*

38

AVDD2**

3

DVDD_IO

32

MONO_OUT

6

BITCLK

5

SDO

8

SDI_CODEC

10

SYNC

11

RESET#

46

DMIC_CLK

33

CAP2

12

PCBEEP

40

NC / OTP

34

SENSE_B / NC

37

NC

18

NC

19

NC

20

NC

27

VREFFILT

26

AVSS1*

42

AVSS2**

7

DVSS**

92HD71B7X5NLGXA1X8_QFN48_7X7

EAPD/ SPDIF OUT 0 or 1 / GPIO 0

VOL_UP/DMIC_0/GPIO 1
VOL_DN/DMIC_1/GPIO 2

GPIO 3

VREFOUT-E / GPIO 4

GPIO 5
GPIO 6

SPDIF OUT1 / GPIO 7

SPDIF OUT0

VREFOUT-B
VREFOUT-C

SENSE_A

PORTA_R

PORTA_L

PORTB_R

PORTB_L

PORTC_R
PORTC_L

PORTD_R
PORTD_L

PORTE_R

PORTE_L

PORTF_R

PORTF_L

+3VDD_CODEC

+VDDA_CODEC_R

+3VS_HDA

HDA_BITCLK_CODEC

12

@

R525

47_0402_5%

2 2

33P_0402_50V8K

3 3

1

C745

@

2

EC_BEEP<33>
SB_SPKR<20>

HDA_BITCLK_CODEC<20>
HDA_SDOUT_CODEC<20>

HDA_SYNC_CODEC<20>

HDA_RST#_CODEC<20>

R563 47K_0402_5%

1 2

R524 47K_0402_5%

1 2

R523 10K_0402_5%

1 2

C956 0.1U_0402_16V4Z

1 2

+VDDA_CODEC_R

SENSE_B#<35>

HDA_SDIN0<20>

DMIC_CLK<17>

R982 5.1K_0402_1%
R910 39.2K_0402_1%

1 2
1 2

HDA_BITCLK_CODEC
HDA_SDOUT_CODEC

R522 33_0402_5%

1 2

HDA_SYNC_CODEC
HDA_RST#_CODEC

R230

1 2

C979

0.1U_0402_16V4Z

10U_0805_10V4Z
C744

1 2

22_0402_5%

1 2

C913 1U_0603_10V4Z

MONO_INR

0.1U_0402_16V4Z
C955

1

2

VC_REFA

EAPD_CODEC

47
2
4
30
31
43
44
45

SPDIF_OUT

48

VREFOUT_B

28
29

SENSE

13

HP_OUTR

41

HP_OUTL

39

MIC_EXTR

22

MIC_EXTL

21

MIC_INR

24

MIC_INL

23

LINE_OUT_R

36

LINE_OUT_L

35

DOCK_MICR

15

DOCK_MICL

14

17
16

EAPD_CODEC <33>
DMIC_DAT <17>

SPDIF_OUT <35>

VREFOUT_B <29>

R548 5.1K_0402_1%

1 2

R569 20K_0402_1%

1 2

R571 39.2K_0402_1%

1 2

R570 10K_0402_1%

1 2

C951 0.1U_0402_16V4Z

1 2

HP_OUTR <29>
HP_OUTL <29>

1 2

C981 1U_0603_10V6K

1 2

C982 1U_0603_10V6K

LINE_OUT_R <29>
LINE_OUT_L <29>

1 2

C985 1U_0603_10V6K

1 2

C986 1U_0603_10V6K

+VDDA_CODEC_R

HP Jack & Dock

Internal SPKR.

EXTMIC_DET# <29>
JACK_DET# <29,35>
INTMIC_DET# <29>

1 2

C983 1U_0603_10V6K

12

R911

@

0_0603_5%
C984 1U_0603_10V6K

1 2

MIC_EXT_R <29>
MIC_EXT_L <29>

MIC_IN_R <29>

MIC_IN_L <29>

DOCK_MIC_R <35>
DOCK_MIC_L <35>

Jack MIC

Internal MIC

DOCK MIC

C746

@

1 2

0.1U_0402_16V4Z

C747

@

1 2

0.1U_0402_16V4Z

C748

SENSE A

Port

4 4

A

B

C

D

39.2K E

20K

10K

5.11K

A

PortResistor

F

G

H

SENSE B

Resistor

39.2K

20K

10K

5.11K

@

1 2

C749

@

1 2

@

1 2

0_0402_5%

@

1 2

0_0805_5%

1 2

0_1206_5%

B

R195

0.1U_0402_16V4Z

0.1U_0402_16V4Z
R1006

R198

Use an 80mil to
connection or place
a 1206 resistor under
CODEC with double
vias.

Security Classification

GNDA <29,35>

GNDAGND

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Audio Codec-IDT9271B7

LA-4111P

28 47Thursday, November 15, 2007

E

0.2

of

A

[e-mail]

B

C

D

E

0.1U_0402_16V4Z

1

C766

10U_0805_10V4Z

1 1

C1049 0.47U_0603_16V7K

1 2
1 2

LINE_OUT_R<28>

LINE_OUT_L<28>

2 2

3 3

4 4

R1002

20K_0402_5%

R1005

20K_0402_5%

EC_MUTE#<33>

HP_OUTR<28>

HP_OUTL<28>

A

C1052 47P_0402_50V8J
C1050 0.47U_0603_16V7K

12

C1053 47P_0402_50V8J

C1040 0.47U_0603_16V7K
C1054 47P_0402_50V8J
C1041 0.47U_0603_16V7K

12

C1055 47P_0402_50V8J

EC_MUTE#

10K_0402_5%

10/30 update

HP_DET#

+3VALW

R973

1 2
1 2

1 2
1 2

1 2
1 2

VREFOUT_B<28>

MIC_EXT_R<28>

MIC_EXT_L<28>

10K_0402_5%

1 2

R974

2

JACK_DET#<28,35>

+3VALW

MIC_EXT_R
MIC_EXT_L

1 2
61

U28

7

17

9

5

19

R909

12

0_0402_5%

R907

4.7K_0402_5%

Close to CODEC U27

2

G

2N7002DW-7-F_SOT363-6
Q145A

RIN+

RIN-

LIN+

LIN-

SHUTDOWN

C742

12

12

R908

4.7K_0402_5%

EXTMIC IN

13

D

Q161

S

2N7002_SOT23-3

B

16

15

6

VDD

PVDD1

PVDD2

GND41GND311GND213GND1

20

1 2

1U_0603_10V4Z

3

5

4

3

GAIN0
GAIN1

ROUT+

ROUT-

LOUT+

LOUT-

BYPASS

THERMAL PAD

21

TPA6017A2_TSSOP20

2N7002DW-7-F_SOT363-6
Q145B

1

C767

2

2

0.1U_0402_16V4Z

2
3

SPKR+

18

SPKR-

14

SPKL+

4

SPKL-

8

12

NC

10

1

2

B+

12

R975
330K_0402_5%

2

Q147A
2N7002DW-7-F_SOT363-6

6 1

5

Q147B
2N7002DW-7-F_SOT363-6

4

C773 150U_Y_6.3VM

+

1 2

C774 150U_Y_6.3VM

+

1 2

R594

1 2

0_1206_5%

1

C1051

2

100K_0402_5%

R1003

@

100K_0402_5%

Keep 10 mil width

C1044
10U_0805_10V4Z

DOCK_LOUT_R

DOCK_LOUT_L

HP_OUT_R

HP_OUT_L

+5VS+5VAMP

GAIN0 GA IN1 Av(inv)

+5VS

10 dB

12

12

R1000

12

R1001

@

100K_0402_5%

12

R1004
100K_0402_5%

11/05 update 11/14 update

C775 150U_Y_6.3VM

+

DOCK_LOUT_CR_R

1 2

C776 150U_Y_6.3VM

+

DOCK_LOUT_CR_L

1 2

0

0

1

1

R968

1 2

40.2_0402_1%
R969

1 2

40.2_0402_1%

0

1

0

1

DOCK_LOUT_C_R

HP OUT For Docking

DOCK_LOUT_C_L

6dB

10dB

15.6dB

21.6dB

+VDDA_CODEC

ANA_MIC_DET<33>

INTMIC_DET#<28>

DOCK_LOUT_C_R <35>

DOCK_LOUT_C_L <35>

HP OUT For M/B

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

D

SPKL+
SPKL­SPKR+
SPKR-

C760

100P_0402_50V8J

MIC_IN_L<28>

MIC_IN_R<28>

Q160

2N7002_SOT23-3

Close to CODEC U27

1

1

1

C761

2

2

100P_0402_50V8J

R906

0_0402_5%

12

12

R904

4.7K_0402_5%

+3VS

R955 10K_0402_5%

13

D

2N7002_SOT23-3

2

G

S

EXTMIC_DET#<28>

CIR_IN<33,35>

Title

Size Document Number Rev

Custom

Date: Sheet

C763

C762

2

100P_0402_50V8J

100P_0402_50V8J

C743

1U_0603_10V4Z

1 2

12

R905

4.7K_0402_5%

12

13

D

Q151

S

9/20 SP02000H700/SP02000H900

MIC_EXT_R
MIC_EXT_L

HP_OUT_R
HP_OUT_L

EXTMIC_DET#
HP_DET#

CIR_IN

+5VL

Compal Electronics, Inc.

AMP & Audio Jack

LA-4111P

SPEAKER

11/14 update

JP20

1

1

2

2

3

3

4

4

5

1

GND1

6

GND2

12

INTMIC IN

R951
100K_0402_5%

1
2
3
4

5
6

E&T_3806-F04N-02RCONN@

JP42

1
2
3
4

GND1

GND2

ACES_88231-04001

CONN@

2

Change JP20 PCB Footprint
from ACES _88231-04001_4P
to E-T_3806-F04N-02R_4P

+VDDA_CODEC

2

G

Audio/B & CIR

JP43

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

ACES_87213-1400GCONN@

09/13 update

9/20 SP02000H800

29 47Thursday, Novemb e r 15, 2007

E

of

0.2

A

1 1

B

C

D

E

ACCELEROMETER

+3VS_ACL+3VS +3VS_ACL_IO

1

2

R959 0_0603_5%

1 2

1

C1031
10U_0805_6.3V6M

2

D44

2 1

CH751H-40PT_SOD323-2

C1030

2 2

0.1U_0402_16V4Z

SMB_CK_CLK0

14

VDDIO absolute man

U63

rating is VDD+0.1

Vdd_IO
GND
Reserved
GND
GND
Vdd

12

C

SCL / SPC

SDA / SDI / SDO

SDO

Reserved

GND
INT 2
INT 1

CS

LIS302DLTR_LGA14_3x5

7

2007/08/02 2008/08/02

+3VS_ACL_IO

3 3

4 4

+3VS_ACL

R997
0_0402_5%

1 2

1
2
3
4
5
6

R999 10K_0402_5%

Must be pl aced in the center of the system.

L

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SMB_CK_DAT0

13

R998

12

0_0402_5%

11

1 2
10
9
8

Compal Secret Data

SMB_CK_CLK0 <8,9,15,20>

0011101b

SMB_CK_DAT0 <8,9,15,20>

HDD_HALTLED <34>
ACCEL_INT <19>

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Accelerometer

LA-4111P

30 47Thursday, Novemb e r 15, 2007

E

0.2

of

A

[e-mail]

B

C

D

E

Left side USB CONNECTOR Left side ESATA5/USB2 combination Connector Right side USB 0&1 Board Conn

Max 2.5A

1 1

1

C788

4.7U_0805_10V4Z

2

USB_EN#

U40

1

GND

2
3
4

OUT

IN

OUT
OUT

IN

OC#

EN#

TPS2061IDGN_MSOP8~N

8
7
6

1

5

+

C789

2

150U_D_6.3VM

W=100mils

1

C790

2

0.1U_0402_16V4Z

+USB_VCCA+5VALW

C791

1000P_0402_50V7K

+USB_VCCA

USB20_N2_R

1

+USB_VCCA

2

SATA_TXN2

D11

4

VIN

3

IO2

PRTR5V0U2X_SOT143-4@

D12

4

VIN

3

IO2

PRTR5V0U2X_SOT143-4@

GND

GND

USB20_P2_R

2

IO1

1

SATA_TXP2

2

IO1

1

Change PCB Footprint from SW_WCM2012F2S_4P to KING_WCM-2012-900T_4P

L

USB20_N2<20>

USB20_P2<20>

SATA_TXP2<21>
SATA_TXN2<21>

SATA_RXN2_C<21>

SATA_RXP2_C<21>

10/09 update

L51

4

4

1

1

WCM-2012-900T_4P

C792 0.01U_0402_16V7K
C793 0.01U_0402_16V7K

3

3

2

2

12
12

Max 0.5A

+USB_VCCA

USB20_N2_R
USB20_P2_R

SATA_TXP2
SATA_TXN2

SATA_RXN2
SATA_RXP2

JESAT

1
2
3
4

5
6
7
8
9

10
11

12
13
14
15

11/14 update

USB

VBUS
D­D+
GND

GND
A+

ESATA

A­GND
B­B+
GND

GND
GND
GND
GND

TYCO_1759576-1CONN@

JP47

+5VALW

USB_EN#<33>

USB20_N0<20>
USB20_P0<20>

USB20_N1<20>
USB20_P1<20>

USB_EN#

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

GND1

12

GND2

ACES_87213-1000G

9/20 SP02000DX00

CONN@

Update Symb ol TYCO_1759576-1_11P-T

2 2

Finger printer

11/14 update

R622

1 2

0_0603_5%@

Q31 SI2301BDS-T1-E3_SOT23-3@

S

D

13

G

2

USB_EN#

USB20_N7<20>
USB20_P7<20>

+3VS_FB
USB20_N7

3 3

D21

4

VIN

3

IO2

PRTR5V0U2X_SOT143-4@

GND

USB20_P7

2

IO1

1

20070209 Add for FPR

+3VS_FB

1

C832

0.1U_0402_16V4Z

2

USB20_N7
USB20_P7

R581

1 2

0_0603_5%

JP39

1

1

2

2

3

3

4

4

5

5

6

6

7

GND

8

GND

ACES_85201-06051

CONN@

9/20 SP01000B000

+3VS+3VALW

BT Connector

JP32

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

GND1

10

GND2

ACES_88231-08001

CONN@

9/20 SP02000HC00/SP02000HB00

1

C798
1U_0603_10V4Z

2

BT_OFF<21>

47K_0402_5%

USB20_P6
USB20_N6

R517 1K_0402_5%@

1 2

R518 1K_0402_5%@

1 2

0612 no install

+3VAUX_BT

USB20_N6

12

R519
100K_0402_5%

R520

1 2

+3VAUX_BT

D16

4

VIN

3

GND

IO2

PRTR5V0U2X_SOT143-4@

Q24 SI2301BDS-T1-E3_SOT23-3

S

D

13

G

2

0.01U_0402_16V7K

1 2

C802 0.1U_0402_16V4Z

2

IO1

1

1

C799

2

USB20_P6

0.1U_0402_16V4Z

1

2

+3VAUX_BT+3VALW

1

C800

2

4.7U_0805_10V4Z

USB20_P6 <20>
USB20_N6 <20>
BT_LED <34>
CH_DATA <26>

CH_CLK <26>

C801

Check BT power consumption < 1A

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

USB, BT, eSATA,FPR

LA-4111P

31 47Thursday, Novemb e r 15, 2007

E

0.2

of

A

B

C

D

E

SPI Flash (8Mb*1)

C803

0.1U_0402_16V4Z

+3VAL

1

2

U31

8
7
6
5

AT24C16AN-10SI-2.7_SO8

A0

VCC

A1

WP
SCL

A2

SDA

GND

0.1U_0402_16V4Z

12

R521
100K_0402_5%

1
2
3
4

12

R526
100K_0402_5%

SPI_CS#<33>
SPI_CLK<33>

EC_SO_SPI_SI<33>

INT_SPI_CS#

SB_INT_FLASH_SEL<21>

+3VL

1 2

R995 0_0402_5%@

+3VALW

1 2

1 1

2 2

R996 0_0402_5%

SMB_EC_CK1<33,34,37>
SMB_EC_DA1<33,34,37>

+3VL

1

C484

2

1 2

R221 0_0402_5%

1 2

R227 0_0402_5%
R229 0_0402_5%

EC_SO_SPI_SI_R EC_SI_SPI_SO_R

12

R228

1 2

22_0402_5%

SPI_CS#

EC_SI_SPI_SO_R

20mils

INT_SPI_CS#
SPI_CLK_R

CONN@

U29

8

VCC

3

W

7

HOLD

1

S

6

C

5

D

WIESON G6179 8P SPI

9/20 SP07000F500

+3VALW

C489

0.1U_0402_16V4Z

5

U30

2

B

4

Vcc

Y

1

A

G

NC7SZ32P5X_NL_SC70-5

3

JP12

112
334
556
778

E&T_2941-G08N-00E~D@

C:Chg. PN to LTC00000200

VSS

Q

12

INT_FLASH_EN#

SPI_CS#

2

INT_FLASH_EN#

4

SPI_CLK_R

6

EC_SO_SPI_SI_R

8

4

2

R226

100K_0402_5%

1 2

&U29

45@

SST25VF080B-50-4C-S2AF_SO8

9/20 SA000012E00/SA00000XT00

R223 0_0402_5%

+3VALW

12

EC_SI_SPI_SO <33>

11/13 update

3 3

SIRQ<19,33>

LPC_AD3<19,33>

LPC_AD1<19,33>

LPC_FRAME#<19,33>

4 4

LPC Debug Port

+3VALW

SIRQ

LPC_AD3

LPC_AD1

LPC_FRAME#

7

8

9

10

9/20 ??????

H31

LPC_DRQ#

56

PLT_RST#

4

LPC_AD2

3

LPC_AD0

2

CLK_PCI_SIO

1

DEBUG_PAD@

@

1 2
2

1

LPC_DRQ# <19>

PLT_RST# <11,14,19,25,26,27,33>

LPC_AD2 <19,33>

LPC_AD0 <19,33>

CLK_PCI_SIO <19,23>

R232

22_0402_5%

C486

@

22P_0402_50V8J

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

LPC Debug Port

JP41

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

ACES_85201-2005@

+3VS

CLK_14M_SIO
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LPC_DRQ#
PLT_RST#

R137 0_0402_5%@

1 2

CLK_PCI_SIO2
SIRQ

11/09 update

9/20 DC233105000

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

D

CLK_14M_SIO <15>

CLK_PCI_SIO2 <19>

CLK_14M_SIO

12

R310

@

100_0402_5%

1

C502

@

100P_0402_25V8K

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

BIOS ROM/Debug Tool

LA-4111P

32 47Thursday, November 15, 2007

E

of

0.2

A

[e-mail]

+3VL_EC

C808

C810

1 2

15P_0402_50V8J@

C811

ON/OFF#<34>

11/07 update

LAN_POWER_OFF<25>

1000P_0402_50V7K

1

C809

2

R530

1 2

33_0402_5%@

R533

1 2

47K_0402_5%

12

0.1U_0402_16V4Z

+3VL_EC

R543

4.7K_0402_5%

1 2

1 2

R542 0_0402_5%

32.768KHZ_12.5PF_1TJS125DJ4A420P

C813
15P_0402_50V8J

1 2

3

NC

2

NC

1 2

C815
15P_0402_50V8J

LAN_POWER_OFF E51_RXD

0.1U_0402_16V4Z

1

1

C805

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

1 2

10K_0402_5%

1 2

10K_0402_5%

C806

2

11/11 update

12
12
12
12

2

0.1U_0402_16V4Z

1 1

10/08 update

+3VALW

2 2

3 3

12

R538
10K_0402_5%

LID_SW#

11/13 update

+5VL

R528

+3VS

R529
R531
R532

+3VL

R514
R515

L

0.1U_0402_16V4Z

1

1

C807

2

1000P_0402_50V7K

SMB_EC_DA1
SMB_EC_CK1
SMB_EC_DA2
SMB_EC_CK2

ESB_CLK AC_IN_D
ESB_DAT

2

CLK_PCI_EC<19,23>

+3VL_EC

2nd source : SJ100004N00 same as IAL80

11/13 update

4 4

EC DEBUG port

@

JP34

1

1

2

2

3

3

4

4

ACES_85205-0400

E51_RXD
E51_TXD

+5VALW

9/20 SP020007200

A

OUT

H_THERMTRIP#_EC<6>

Y7

IN

LPC_FRAME#<19,32>

SMB_EC_CK1<32,34,37>
SMB_EC_DA1<32,34,37>
SMB_EC_CK2<6>
SMB_EC_DA2<6>

DIM_LED<36>
NUM_LED#<34>DOCK_SLP_BTN#<35>

4
1

R544

1 2

0_0402_5%

B

+3VL_EC+3VL

R527

1 2

0_0805_5%

U33

GATEA20<20>
KB_RST#<20>
SIRQ<19,32>

LPC_AD3<19,32>
LPC_AD2<19,32>
LPC_AD1<19,32>
LPC_AD0<19,32>

PLT_RST#<11,14,19,25,26,27,32>

EC_SCI#<20>

HDARST#<20,23>

SLP_S3#<20>
SLP_S5#<20>

EC_SMI#<20>
LID_SW#<34>
ESB_CLK<34>
ESB_DAT<34>

CONA#<35>

VLDT_EN<36>

GATEA20
KB_RST#
SIRQ
LPC_LFRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

CLK_PCI_EC

PLT_RST#
ECRST#
EC_SCI#

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

SMB_EC_CK1
SMB_EC_DA1

SMB_EC_DA2

SLP_S3#
SLP_S5#
EC_SMI#
LID_SW#
ESB_CLK
ESB_DAT

H_THERMTRIP#_EC

E51_TXD
E51_RXD
ON/OFF#

CRY2

12

@

R545
20M_0402_5%

CRY1

1

GA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ#

4

LFRAME#

5

LAD3

7

LAD2

8

LAD1

10

LPC & MISC

LAD0

12

PCICLK

13

PCIRST#/GPIO05

37

ECRST#

20

SCI#/GPIO0E

38

CLKRUN#/GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44

KSO5/GPIO25

45

KSO6/GPIO26

46

KSO7/GPIO27

47

KSO8/GPIO28

48

KSO9/GPIO29

49

KSO10/GPIO2A

50

KSO11/GPIO2B

51

KSO12/GPIO2C

52

KSO13/GPIO2D

53

KSO14/GPIO2E

54

KSO15/GPIO2F

81

KSO16/GPIO48

82

KSO17/GPIO49

77

SCL1/GPIO44

78

SDA1/GPIO45

79

SCL2/GPIO46

80

SDA2/GPIO47

6

PM_SLP_S3#/GPIO04

14

PM_SLP_S5#/GPIO07

15

EC_SMI#/GPIO08

16

LID_SW#/GPIO0A

17

SUSP#/GPIO0B

18

PBTN_OUT#/GPIO0C

19

EC_PME#/GPIO0D

25

EC_THERM#/GPIO11

28

FAN_SPEED1/FANFB1/GPIO14

29

FANFB2/GPIO15

30

EC_TX/GPIO16

31

EC_RX/GPIO17

32

ON_OFF/GPIO18

34

PWR_LED#/GPIO19

36

NUMLED#/GPIO1A

122

XCLK1

123

XCLK0

+3VL_EC

+EC_AVCC

Int. K/B
Matrix

SM Bus

12

L80
0_0603_5%

1 2

C816 0.1U_0402_16V4Z

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

+EC_AVCC

9

22

33

96

111

125

VCC

VCC

VCC

VCC

VCC

VCC

INVT_PWM/PWM1/GPIO0F

ACOFF/FANPWM2/GPIO13

PWM Output

AD Input

DA Output

PS2 Interface

TP_DATA/PSDAT3/GPIO4F

SPI Device Interface

SPI Flash ROM

BATT_CHGI_LED#/GPIO52

GPIO

BATT_LOW_LED#/GPIO54

GPO

GPIO

GPI

GND

GND

GND

GND

GND

11

24

35

94

113

C

67

AVCC

BEEP#/PWM2/GPIO10

FANPWM1/GPIO12

BATT_TEMP/AD0/GPIO38

BATT_OVP/AD1/GPIO39

ADP_I/AD2/GPIO3A

AD3/GPIO3B

AD4/GPIO42

SELIO2#/AD5/GPIO43

DAC_BRIG/DA0/GPIO3C

EN_DFAN1/DA1/GPIO3D

IREF/DA2/GPIO3E

DA3/GPIO3F

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C

PSDAT2/GPIO4D

TP_CLK/PSCLK3/GPIO4E

SDICS#/GPXOA00
SDICLK/GPXOA01

SDIDO/GPXOA02

SDIDI/GPXID0

SPIDI/RD#

SPIDO/WR#

SPICLK/GPIO58

SPICS#

CIR_RX/GPIO40

CIR_RLC_TX/GPIO41

FSTCHG/SELIO#/GPIO50

CAPS_LED#/GPIO53
SUSP_LED#/GPIO55

SYSON/GPIO56

VR_ON/XCLK32K/GPIO57

AC_IN/GPIO59

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04

EC_ON/GPXO05

EC_SWI#/GPXO06

ICH_PWROK/GPXO06

BKOFF#/GPXO08

WL_OFF#/GPXO09

GPXO10
GPXO11

PM_SLP_S4#/GPXID1

ENBKL/GPXID2

GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

V18R

AGND

KB926QFC0_LQFP128_14X14

69

ECAGND

L81

1 2

0_0603_5%

2007/08/02 2008/08/02

INV_PWM

21

FAN_PWM

23

EC_BEEP

26

ACOFF

27

BATT_TEMP

63

BATT_OVP

64
65
66

TP_BTN#

75
76

68
70

IREF

71
72

83
84
85
86

TP_CLK

87

TP_DATA

88

11/13 update

97
98
99
109

119
120
126
128

73
74
89
90
91
92
93
95
121
127

100
101
102
103
104
105
106
107
108

110
112
114
115
116
117
118

124

Need 1uf for 926 C version

T20 PAD

1 2

R1044 100K_0402_5%

CIR_IN
FSTCHG

BAT_LED#
ON/OFFBTN_LED#
SYSONSMB_EC_CK2
VR_ON

EC_RSMRST#

SB_PWRGD
BKOFF#

TP_LED#

SUSP#
PWRBTN_OUT#
NMI_DBG#

12

C814 1U_0805_25V4Z

11/13 update

Compal Secret Data

Deciphered Date

D

INV_PWM <17>
FAN_PWM <4>
EC_BEEP <28>
ACOFF <38>

C812

BATT_TEMP <37>
BATT_OVP <37>
ADP_I <38>
ADP_ID <37>
TP_BTN# <34>
ANA_MIC_DET <29>

DAC_BRIG <17>
VCTRL <38>
IREF <38>
AC_SET <38>

EC_MUTE# <29>
USB_EN# <31>
I2C_INT <34>
MUTE_LED <35>
TP_CLK <34>
TP_DATA <34>

DOCK_VOL_UP# <35>
DOCK_VOL_DWN# <35>
VGATE <43>

EC_SI_SPI_SO <32>
EC_SO_SPI_SI <32>
SPI_CLK <32>
SPI_CS# <32>

R46 10K_0402_5%

CIR_IN <29,35>
FSTCHG <38>

STD_ADP <38>
CAPS_LED# <34>
BAT_LED# <34>
ON/OFFBTN_LED# <34>

SYSON <26,34,36,40>

AC_IN_D <21>

EC_RSMRST# <20>

EC_LID_OUT# <20>
EC_ON <36,39>

WL_BLUE_LED# <34>
SB_PWRGD <6,20,43>
BKOFF# <17>

TP_LED# <34>

ENBKL <11>
EAPD_CODEC <28>
EC_THERM# <21>
SUSP# <26,28,36,38,41>

PWRBTN_OUT# <20>

11/13 update

0.01U_0402_16V7K

ECAGND

1 2

select SPI R O M or LPC ROM

+5VL

1 2

11/11 update

R541 10K_0402_5%

2 1

D54
CH751H-40PT_SOD323-2

R1040
10K_0402_5%

C1073
100P_0402_50V8J

TP_LED#=L, T/P disable

L

TP_LED#=float (GPO), T/P enable

1 2

0_0402_5%

D

12

12

1 2

R547

11/13 update

E

Keyboard Connector

KSO15
KSO10
KSO11
KSO14
KSO13
KSO12
KSO3
KSO6
KSO8
KSO7
KSO4
KSO2
KSI0
KSO1
KSO5
KSI3
KSI2

KSO0
KSI5
KSI4
KSO9
KSI6
KSI7
KSI1

JP33

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

GND1

26

GND2

ACES_85201-24051

CONN@

9/20 SP01000FF00/SP01000G300

KB Back Light Conn

VR_ON <43>
AC_IN <38,39>

11/13 update

+3VL_EC

PCI_SERR# <19>

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

EC KB926/KB conn

LA-4111P

For EMI

KSO15

C213 100P_0402_25V8K@

KSO10
KSO11
KSO14
KSO13
KSO12
KSO3
KSO6
KSO8
KSO7
KSO4
KSO2
KSI0
KSO1
KSO5
KSI3
KSI2
KSO0

KSI5
KSI4
KSO9
KSI6
KSI7
KSI1

1 2

C609 100P_0402_25V8K@

1 2

C754 100P_0402_25V8K@

1 2

C756 100P_0402_25V8K@

1 2

C757 100P_0402_25V8K@

1 2

C758 100P_0402_25V8K@

1 2

C759 100P_0402_25V8K@

1 2

C764 100P_0402_25V8K@

1 2

C768 100P_0402_25V8K@

1 2

C769 100P_0402_25V8K@

1 2

C822 100P_0402_25V8K@

1 2

C823 100P_0402_25V8K@

1 2

C824 100P_0402_25V8K@

1 2

C825 100P_0402_25V8K@

1 2

C826 100P_0402_25V8K@

1 2

C875 100P_0402_25V8K@

1 2

C876 100P_0402_25V8K@

1 2

C877 100P_0402_25V8K@

1 2

C878 100P_0402_25V8K@

1 2

C884 100P_0402_25V8K@

1 2

C885 100P_0402_25V8K@

1 2

C886 100P_0402_25V8K@

1 2

C887 100P_0402_25V8K@

1 2

C888 100P_0402_25V8K@

1 2

11/13 update

JP48

5

G1

6

G2

ACES_85201-04051

CONN@

+5VS_LED

R516

150_0603_1%

1

1

2

2

3

3

4

4

9/20 SP01000KC00/SP010009O10

R589

DOCK@

DOCK_VOL_UP#
DOCK_VOL_DWN#

TP_CLK

TP_DATA

10K_0402_5%

DOCK@

10K_0402_5%

R534

10K_0402_5%

1 2

R535

10K_0402_5%

1 2

SUSP# SYSON

12

R536
100K_0402_5%

R1050

TP_BTN#

1 2

10K_0402_5%

33 47Thursday, November 15, 2007

E

R590

12

R539
100K_0402_5%

of

12

+3VS

12
12

+5V_TP

+3VS

0.2

A

B

C

D

E

for debug only

BTN TOP

SW3

5

6

SMT1-05_4P

3
4

1

5

6

3

4

SW2
SMT1-05_4P

2

1

1 1

2

MDC 1.5 Conn.

HDA_SDOUT_MDC<20>

HDA_SYNC_MDC<20>

HDA_SDIN1<20>

HDA_RST#_MDC<20>

1

C778

2 2

2

1000P_0402_50V7K

+3VS

1

C779

2

0.1U_0402_16V4Z

R495

1 2

33_0402_5%

1

2

HDD/G-Sensor LED

+5VS

12

R20

10K_0402_5%

SATA_LED#<21>

3 3

2N7002DW-7-F_SOT363-6

11/10 update

61

Q7A

2N7002DW-7-F_SOT363-6

2

Q7B

5

ON/OFF Button Connector

ON/OFF#

ON/OFF#
ON/OFFBTN_LED#

JP25

1
3
5
7
9
11

GND13GND14GND15GND16GND17GND

18

D18 need correct pin
connection after netin

HDA_SDIN1_MDC

C780

4.7U_0805_10V4Z

@

+5VS_LED

R987

200_0402_5%

3

WHITE

4

Q156

2N7002_SOT23-3

ON/OFF#<33>

ON/OFFBTN_LED#<33>

9/20 SP01000J100
9/20 STANDOFF (H= 5.0 mm) ES000000800

11/01 update

1
3
5
7
9

11

ACES_88020-12101

CONN@

Change JP25 PCB Footprint
from ACES _8 8018-124G_12P
to ACES_88020-12101_12P

+3VS

11/14 update

12

12

R988
390_0402_5%

L

21

43

D18
HT-297UY5/BP5_YELLOW-WHITE

YELLOW

R42

1 2

0_0402_5%

13

D

2

G

S

+5VALW_LED

1
2
3
4

2

2

4

4

6

6

8

8

10

10

12

12

R496

@

10_0402_5%

1 2
1

@

10P_0402_50V8J

2

HDD_HALTLED# <21>

HDD_HALTLED <30>

TP ON/OFF

JP1

1
2

5

3

G1

6

4

G2

ACES_85201-04051

CONN@

+3VS
+3VS

HDA_BITCLK_MDC <20>

C777

TouchPAD ON/OFF LED

200_0402_5%

+5VS

10/08 update

12

R985

10K_0402_5%@

2N7002_SOT23-3

10/08 update

+3VALW

12

R1038
SW1
SMT1-05-A_4P

3
4

5

+5VALW +5V_TP

10K_0402_5%@

SYSON<26,33,36,40>

+5VS_LED

12

R983

21

WHITE

13

D

2

G

Q153

S

TP_BTN#

1
2

6

R235 0_0603_5%

1 2

Q85 SI2301BDS-T1-E3_SOT23-3@

S

12

R645

2

G

12

R984
390_0402_5%

L

43

D17
HT-297UY5/BP5_YELLOW-WHITE

YELLOW

T/P Enable (TP_LED#=X)-> White
T/P Disable (TP_LED#=L)-> Amber

TP_LED#

10K_0402_5% @

D

13

G

2

13

D

Q34

2N7002_SOT23-3@

S

D18 need correct pin
connection after netin
11/10 update

TP_LED# <33>

11/14 update

TP_BTN# <33>

Max 0.5A

11/13 update

SMB_EC_CK1<32,33,37>
SMB_EC_DA1<32,33,37>

ESB_CLK<33>
ESB_DAT<33>

+5VALW_LED

11/13 update

09/29 update

M/B TO TP/B

Max 0.5A

+5V_TP

1

C819

@

0.1U_0402_16V4Z

5
6

ACES_85201-04051

9/20
SP01000KC00/SP01E000900

JP37

G1
G2

CONN@

2

1

1

2

2

3

3

4

4

100P_0402_50V8J

TP_CLK
TP_DATA

SWITCH BOARD.

4.7K_0402_5%@

10K_0402_5%

R556

R558

4.7K_0402_5%@

12

12

10/08 update

R1046 0_0402_5%

1 2

R1047 0_0402_5%

1 2

R1048 0_0402_5%@

1 2

R1049 0_0402_5%@

1 2

R1036

1 2

150_0402_5%

NUM_LED#<33>

I2C_INT<33>

Reed switch BOARD.

11/14 update

LID_SW#<33>

Change JP40 PCB Footprint from
ACES_85204-03001_3P to ACES_88231-03041_3P

+3VALW

JP40

1

1

2

2

3

3

PSOT24C_SOT23-3

1

C820

@

2

11/13 update

12

+5VS_LED

R557

ON/OFFBTN_LED#

ON/OFF#

9/20 SP01000H400

4

GND

5

GND

ACES_88231-03041CONN@

TP_DATA
TP_CLK

2

3

D31

@

1

TP_CLK <33>
TP_DATA <33>

1

C821

@

2

100P_0402_50V8J

+3VL

JP36

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

GND

12

GND

ACES_85201-1005N

CONN@

Battery Charge LED

BAT_LED#<33>

CAPS LOCK LED

CAPS_LED#<33>

POWER LED

4 4

White LED: VF=3V, IF = 10mA, Res = 200 ohm
Amber LED: VF=1.8V, IF = 8mA, Res = 390 ohm

A

ON/OFFBTN_LED#

11/10 update

WHITE

D6

WHITE

D7

WHITE

D8

21

21

21

HT-F196BP5_WHITE

HT-F196BP5_WHITE

HT-F196BP5_WHITE

R550

1 2

200_0402_5%

R552

1 2

200_0402_5%

R549

1 2

200_0402_5%

+5VALW_LED

+5VS_LED

+5VALW_LED

B

WLAN and BT LED inform pin to KBC

R1024

+3VS+3VS

47K

1 3

12

D

10K

DTA114YKAT146_SOT23-3

R989

1 2

10K_0402_5%

WL_BLUE_LED#<33>

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Q158A

2N7002DW-7-F_SOT363-6

100K_0402_5%

2007/08/02 2008/08/02

C

61

R1025

2

12

3

Q158B

WL/WW_LED

5

2N7002DW-7-F_SOT363-6

4

BT_LED <31>

Compal Secret Data

Deciphered Date

100K_0402_5%

Q168

R1041

12

10K_0402_5%

2

1 2

R1007 0_0402_5%

1 2

R1008 0_0402_5%

+3VS

WL_LED# <26>

WW_LED# <26>

09/29 update

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

TP,MDC,ON/OFF,S/W,LED,Reed

LA-4111P

E

of

34 47Thursday, Novemb e r 15, 2007

0.2

A

[e-mail]

B

C

D

E

+DOCKVIN

1

DOCK@

C831

1000P_0402_50V7K

1 1

2

09/19 update

DOCK_PWR_ON Spec
0V = Notebook S4/S5, Dock off

2.5V = Notebook S3, Dock on
4V = Notebook S0, Dock on

DOCK@

1 2

+5VS

R586 1K_0402_5%
R585 1K_0402_5%

SYSON#<36,42>

Q36
2N7002_SOT23-3

DOCK@

1 2

R572 1K_0402_5%

H33

H_2P8@

1

1

1

H43

H_4P2@

1

1

H48

H_3P3@

1

1

H53

H_3P3X0P6N@

1

1

H51

H_6P0X5P0N@

1

1

1 2

DOCK@

DOCK@

H34

H_2P8@

H39

H_2P8@

H44

H_4P2@

13

D

2

G

S

12

R566
47K_0402_5%

DOCK@

H35

H_2P8@

1

1

H40

H_2P8@

1

1

1

H54

H_3P3X0P6N@

1

A

+3VALW

2 2

DOCK_PRESENT

3 3

H32

H_2P8@

H37

H_2P8@

H42

H_2P8@

H47

H_3P3@

H52

H_1P5N@

4 4

H55

H_5P6N@

D43

DOCK@

2
3

DAN202U_SC70

R588
10K_0402_5%

DOCK@

1 2

+3VL_EC

1 2

13

D

2

G

S

H36

H_2P8@

1

H41

H_2P8@

1

H46

H_4P2@

1

11/09 update

1

R565
10K_0402_5%

DOCK@

Q33
2N7002_SOT23-3

DOCK@

DOCK_PWR_ON

CONA# <33>

D_DDCDATA<16>
D_HSYNC<16>

D_DDCCLK<16>

USB20_N3<20>

D_VSYNC<16>

USB20_P3<20>

RJ45_MIDI1+<25>
RJ45_MIDI1-<25>
RJ45_MIDI0+<25>
RJ45_MIDI0-<25>

B+

B

GREEN_L<16>
RED_L<16>

BLUE_L<16>

PJP5

PAD-OPEN 2x2m

D_DDCDATA
D_HSYNC

D_DDCCLK
USB20_N3
D_VSYNC

USB20_P3

RJ45_MIDI1+
RJ45_MIDI1­RJ45_MIDI0+
RJ45_MIDI0­+V_BATTERY

21

Atlas/ Saturn Dock

JDOCK

38

CRT_Red

40

CRT_Green

34

CRT_Blue

36

DDC_DATA

30

DDC_Clock

32

Hsync

26

Vsync

28

USB-

22

USB+

24

Digital gnd

18

MDI3-

20

MDI3+

14

MD2I-

16

MDI2+

10

MDI1-

12

MDI1+

6

MDI0-

8

MDI0+

2

Battery out

4

Battery out

11/14 update

Update sym bol finish and swap back
JDOCK Pin3 8/ 40 , 34/36 , 30/32,

L

26/28, 22/24, 10/12, 6/8

R_VOL_UP# R _ VOL_DW N#

1

DOCK@

C843
1000P_0402_50V7K

2

1

C942

2

220P_0402_50V7KDOCK@

FOX_QL1122L-H212AR-7FCONN@

Audio Output gnd
Right headphone

C943

Left headphone

Dock_present

220P_0402_50V7KDOCK@

Digital gnd

TV Luma

TV chroma

TV composite

TV ground

CIR input

PWR_ON

Mute_LED

Sleep Botton

Jack Detect

VOL_up

VOL_down

SPDIF

Mic_Right

Mic_Left

Mic gnd

GND
GND
GND
GND

1

DOCK@

C844
1000P_0402_50V7K

2

DOCK_LOUT_C_LDOCK_LOUT_C_R

1

2

39

TV_LUMA_L

37

TV_CRMA_L

35

TV_COMPS_L

33
31

CIR_IN

29

DOCK_PWR_ON

27

MUTELED

25

DOCK_SLP_BTN#

23

JACK_DET#

21

R_VOL_UP# DOCK_VOL_UP#

19

R_VOL_DWN# DOCK_VOL_DWN#

17

SPDIFO_L

15

AUDIO_OGND

13

DOCK_LOUT_C_R

11

DOCK_LOUT_C_L

9

DOCK_MIC_R_C

7

DOCK_MIC_L_C

5

AUDIO_IGND

3

DOCK_PRESENT

1
41

42
43
44

11/05 update

T51PAD
T52PAD
T53PAD

CIR_IN <29,33>

1 2

R591 1K_0402_5%DOCK@
R567 200_0402_5%DOCK@

1 2

R568 200_0402_5%DOCK@

1 2

DOCK_LOUT_C_R <29>
DOCK_LOUT_C_L <29>

+DOCKVIN

R976/Q149/R646 be option with R992/C945

L

@

MMBT3904_NL_SOT23-3

+1.5VS

1 2

C

Q149

SPDIFO_L

3 1

Change PCB Footprint from L_FBM-11-160808_2P to TAI-T_FCM1608KF-601T02_2P

L

MIC_Dock

DOCK_MIC_R<28>

DOCK_MIC_L<28>

DOCK@

1.21K_0402_1%

DOCK_MIC_L_C

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

R976

E

D

33_0402_5%@

2

B

R992

1 2

12

R944

DOCK@

R912

1 2

10K_0402_5%

47K_0402_5%DOCK@

SPDIF

DOCK@

C944
0_0603_5%DOCK@
220P_0402_50V7K

R942 10K_0402_5%DOCK@
R943 10K_0402_5%DOCK@

12

DOCK@

1.21K_0402_1%

MMBT3904_NL_SOT23-3

R913

1 2

MUTE_LED <33>
DOCK_SLP_BTN# <33>
JACK_DET# <28,29>
DOCK_VOL_UP# <33>
DOCK_VOL_DWN# <33>

R646

1 2

0_0402_5%@

C945

1

2

DOCK@

1 2

12

0.1U_0402_16V7K

R573

110_0402_5%DOCK@

R647

1 2

220_0402_5%DOCK@

SPDIF_OUT <28>

09/29 update

Need 600 Ohm 500 mA

DOCK@

12

DOCK_MIC_L_R

12

R980

DOCK@

10K_0402_5%

DOCK@

FCM1608KF-601T02_2P

FCM1608KF-601T02_2P

DOCK@

10/09 update

+3VS

R914

1 2

Q16

C

2

B

E

2

3 1

C978

1

1U_0603_10V6KDOCK@

Title

Size Document Number Rev

Custom

Date: Sheet

L94

1 2
1 2

220P_0402_50V7K

DOCK@

R915

10K_0402_5%

1 2
13

2

G

DOCK@

Q18
2N7002_SOT23-3

DOCK@

D

S

DOCK_MIC_R_CDOCK_MIC_R_R
DOCK_MIC_L_C

L93

1

C921

2

13

D

Q100

2

G

S

DOCK@

Close to CODEC U27

1

DOCK@

2

220P_0402_50V7K

SENSE_B# <28>

2N7002_SOT23-3

Compal Electronics, Inc.

DOCK CONN

LA-4111P

E

C922

35 47Thursday, Novemb e r 15, 2007

0.2

of

A

B

C

D

E

DIM LED

PJP7

PAD-OPEN 2x2m

DIM_LED

PJP8

PAD-OPEN 2x2m

EC_ON<33,39>

21

10K_0402_5%

21

+5VALW TO +5VS

+5VALW

1 1

8
7
6
5

1

2

4.7U_0805_10V4Z

Q35

D
D
D
D

SI4800BDY_SO8

C864

S
S
S
G

C833

1
2
3
4

+5VS

4.7U_0805_10V4Z

1

2

1U_0402_6.3V4Z

RUNON

C835

1

2

+1.8V TO +1.8VS

+1.8V

Q4

IRF8113PBF_SO8

8
7

2 2

5

1

C842

2

4.7U_0805_10V4Z

0.01U_0402_25V7K

1
2
36

4

1.8VS_ENABLE

1

C849

2

+1.8VS

1

C848

2

1U_0402_6.3V4Z

330K_0402_5%

13

D

G

Q13

S

2N7002_SOT23-3

R138

1 2

SUSP

2

09/29 update

2

C841
10U_0805_10V4Z

1

B+

Discharge circuit

2

G

+1.8VS

R279

470_0805_5%

1 2
13

D

2N7002_SOT23-3

S

Q48

+5VS

3 3

SUSP SUSP

2

G

R239

470_0805_5%

1 2
13

D

Q46

2N7002_SOT23-3

S

+3VALW TO +3VS

+3VALW +3VS

8
7
6
5

SI4800BDY_SO8

1

C840

2

4.7U_0805_10V4Z

Q14

S

D

S

D

S

D

G

D

1
2
3
4

1

2

0.01U_0402_25V7K

1

C839

2

1U_0402_6.3V4Z

RUNON

C834

13

D

S

+1.2VALW TO +1.2V_HT

+1.2VALW +1.2V_HT

Q11

IRF8113PBF_SO8

8
7

5

1

2

4.7U_0805_10V4Z

4

C847

+1.2V_HT +1.8V +1.2VALW

VLDT_EN# SYSON#

2

G

C846

1
2
36

1

C837

2

0.01U_0402_25V7K

R280

470_0805_5%

1 2
13

D

Q37

2N7002_SOT23-3

S

1

2

1U_0402_6.3V4Z

1

C838 4.7U_0805_10V4Z

2

R152

12

330K_0402_5%

SUSP

Q17

2

2N7002_SOT23-3

G

1

C862 4.7U_0805_10V4Z

2

R233

330K_0402_5%

13

D

VLDT_EN#

Q12

2

2N7002_SOT23-3

G

S

2

G

B+

12

1 2
13

D

S

B+

R284
470_0805_5%

Q41

2N7002_SOT23-3

+3VALW TO +3V

+3VALW

10/8 update

R50

1 2

8
7
6
5

1

2

4.7U_0805_10V4Z

0_0603_5%@
Q137

D
D
D
D

SI4800BDY_SO8

C1025

G

S
S
S

C1023

1
2
3
4

1

2

0.01U_0402_25V7K

1U_0402_6.3V4Z

RUNON_S4

C1026

+1.2VALW TO +1.2V

+1.2VALW +1.2V

4.7U_0805_10V4Z

08/23 new add
Reserve until SI-1 stage after SB

USB PHY power saving report

EC_ON#

10/8 update

R51

1 2

0_0603_5%@

IRF8113PBF_SO8

8
7

5

Q139

1

C1029

2

4

1
2
36

RUNON_S4

09/29 update (Wait EC Code fix)

R368

470_0805_5%SI@

1 2
13

D

Q42

2

G

2N7002_SOT23-3SI@

S

+3V

1

2

D

S

C1027

1U_0402_6.3V4Z

1

C1024 4.7U_0805_10V4Z

2

R956

330K_0402_5%

13

Q138

SYSON#

2

G

2N7002_SOT23-3

1

C1028 4.7U_0805_10V4Z

2

Q140

2N7002_SOT23-3

SYSON# SYSON#

12

B+

1

2

+1.2V +3V

R957
470_0805_5%

1 2

2N7002_SOT23-3

13

D

2

G

S

Q141

R958

470_0805_5%

1 2
13

D

2

G

S

09/13 update (Del +V_DDR_MCH_REFP)

+5VALW

DIM_LED<33>

+5VS

11/06 update

Q32 SI2301BDS-T1-E3_SOT23-3

S

12

R587

DIM_LED#

13

D

Q51

2

2N7002_SOT23-3

G

S

DIM_LED#

09/13 update

EC_ON#

2

G

+5VALW_LED

D

13

+5VS_LED

D

13

Q44
2N7002_SOT23-3

1

C836

0.1U_0402_16V4Z

2

1

C1069

0.1U_0402_16V4Z

2

G

2

Q166 SI2301BDS-T1-E3_SOT23-3

S

G

2

+5VL

12

R598
100K_0402_5%

13

D

S

09/13 update 09/13 update

+5VL+5VL

12

+3VS

R288

470_0805_5%

1 2
13

2

G

D

Q47

2N7002_SOT23-3

S

4 4

SUSP

2

G

+0.9V

R292

470_0805_5%

1 2
13

D

Q49

2N7002_SOT23-3

S

+1.5VS +1.1VS

R293

470_0805_5%

1 2
13

2

G

D

Q50

2N7002_SOT23-3

S

SUSPSYSON#

SUSP

2

G

R294

470_0805_5%

1 2
13

D

Q52

2N7002_SOT23-3

S

R595

100K_0402_5%

SYSON#<35,42> SUSP <42>

SYSON#

Q38

SYSON

2

G

2N7002_SOT23-3

12

R596
100K_0402_5%

13

13

D

D

Q39

2N7002_SOT23-3

S

S

Change to +3VL(same as EC)
to avoid leakage

SUSP

2

G

SUSP# <26,28,33,38,41>SYSON<26,33,34,40> VLDT_EN<33>

+5VL

12

R597
100K_0402_5%

VLDT_EN#<13>

VLDT_EN#

VLDT_EN

2

G

13

D

Q40
2N7002_SOT23-3

S

09/13 update

CF2

FM3

FM2

FM1

1

1

CF1

1

1

A

CF3

1

1

B

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

DC/DC Circuits

LA-4111P

36 47Thursday, Novemb e r 15, 2007

E

of

0.2

A

[e-mail]

BATT1

45@

CR2032 RTC BATTERY

B

C

D

E

1 1

+3VALW

PQ3
TP0610K-T1-E3_SOT23-3

BATT

2

1 3

PR8
100_0402_5%

ACES_88334-057N

PJP1

2 2

1 2

ADP_SIGNAL

5

5

4

4

3

3

2

2

1

1

ADPINADPIN

2

PD1

PJSOT24C_SOT23-3

PR3
10K_0402_5%

3

1

AC_LED <38>

1 2

12

PC2

100P_0402_50V8J

12

PR2
10K_0402_5%

12

PC3
1000P_0402_50V7K

12

PD4

RLZ3.6B_LL34

PL1

SMB3025500YA_2P

1 2

PC12

12

@1000P_0402_50V7K

12

PC4

100P_0402_50V8J

ADP_ID <33>

VIN +DOCKVIN

PL2

PC5

SMB3025500YA_2P

12

1000P_0402_50V7K

12

12

+5VALW

PR1

340K_0402_1%

12

PR4

499K_0402_1%

12

PC6

0.01U_0402_25V7K

12

PR6

105K_0402_1%

12

PC1

0.01U_0402_25V7K

3
2

PU1A

LM358ADT_SO8

8

P

+

1

0

-

G

4

PR5

10K_0402_5%

12

BATT_OVP <33>

PH1 under CPU botten side :

PL3

VMB

HCB2012KF-121T50_0805

PJP2

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

9

GND

10

GND

3 3

SUYIN_200275MR008GXOLZR

6.49K_0402_1%

12

PR17
1K_0402_5%

10K_0402_5%

1 2

1 2

PR9

PR16

EC_SMD
EC_SMC

PR13

100_0402_5%

+3VL

BAT_ID <38>

+3VL

12

PD2
@SM05_SOT23

3
2

12

PR14
100_0402_5%

BATT_TEMP <33>

1

2

3

1

PD3
@SM24.TC_SOT23-3

SMB_EC_DA1

SMB_EC_CK1

1 2

1 2

PL4
HCB2012KF-121T50_0805

12

PC8
1000P_0402_50V7K

SMB_EC_DA1 <32,33,34>

SMB_EC_CK1 <32,33,34>

BATT

12

PC9

0.01U_0402_50V4Z

PC10

0.22U_0603_10V7K

CPU

12

+5VS

12

PH1
10KB_0603_1%_TH11-3H103FT

+5VALW

12

PR12

2.55K_0402_1%

CPU thermal protection at 90 +-3 degree C
Recovery at 47 +-3 degree C

PR7

47K_0402_1%

1 2

PR10
15K_0402_1%

1 2
1 2

PR11

150K_0402_1%

PR15

150K_0402_1%

12

8

5

P

+

6

-

G

4

12

PC11
1000P_0402_50V7K

7

0

PU1B
LM358ADT_SO8

2

G

2

G

13

D

PQ1
SSM3K7002FU_SC70-3

S

13

D

PQ2
SSM3K7002FU_SC70-3

S

ENTRIP1 <39>

ENTRIP2 <6,39>

4 4

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

DC Connector/CPU_OTP

LA-4111P

37 47Thursday, Novemb e r 15, 2007

E

0.1

of

A

B

C

D

P4

VIN

1 1

PR101

47K_0402_5%

1 2

12

PC101

47P_0402_50V8J

PR107
47K_0402_1%

1 2

2 2

2

G

PACIN

ACOFF#

2

13

D

S

PQ107
SSM3K7002FU_SC70-3

2

13

PQ105
DTC115EUA_SC70-3

PR111

3K_0402_1%

1 2

1 2

PD101

RLS4148_LL34-2

PQ101
AM4835EP-T1-PF_SO8

8
7

5

DTA144EUA_SC70-3

PQ104

1 3

13

D

2

G

S

VCTRL<33>

PQ109
SSM3K7002FU_SC70-3

Charge Detector

PR123

3
2

P2

12

8

+

-

4

1M_0402_5%

1 2

PR125
47_1206_5%

12

P

1

O

G

PU102A
LM393DG_SO8

PC125

0.1U_0603_25V7K

3 3

VIN

12

PR131
133K_0402_1%

12

PR135
10K_0603_0.1%

1.24VREF

4 4

1
2
36

4

PC106

1 2

1U_0603_10V6K

+3VL

12

PR129

10K_0402_1%

STD_ADP <33>

P2

12

0.22U_0603_16V7K

PR114
@0_0402_5%

PC117

BQ24740VREF

PR128

2

G

AM4835EP-T1-PF_SO8

1
2
3 6

12

PR106

200K_0402_5%

12

PR109
150K_0402_5%

143K_0402_1%

12

12

10K_0402_5%

CHGEN#

13

D

PQ112
SSM3K7002FU_SC70-3

S

FSTCHG<33>

PR113

4

FSTCHG#

PQ103

AC_SET<33>

SUSP#<26,28,33, 36,41>

12

12

PR115
100K_0402_1%

ADP_I<33>

1 2

PR137
20K_0402_1%

8
7

5

PR104
0_0402_5%

1 2

@0.01U_0402_16V7K

PR110
0_0402_5%

1 2

PC112

1 2

1U_0603_6.3V6M

39K_0402_5%

12

PC120

0.22U_0603_10V7K

+3VL

12

PR132

100K_0402_5%

13

D

PQ113

2

SSM3K7002FU_SC70-3

G

S

ACDET

12

PR138

100K_0402_1%

PC107

BQ24740VREF

+3VL

PR116

10K_0402_5%

1 2

12

10

11

12

13

14

12

PR118

0.1U_0402_10V7K

ACSET

8

9

IADSLP

AGND

VREF

VDAC

VADJ

EXTPWR

ISYNSET

PC121

100P_0402_50V8J

PC123

ACDET

7

LPREF

IADAPT

15

IADAPT

12

12

0.1U_0603_25V7K

6

5

4

LPMD

ACSET

ACDET

PU101
BQ24740RHDR_QFN28_5X5

BAT

SRSET

SRN

17

16

18

BATT

12

PR102

0.012_2512_1%

1 2

PC102

1U_0603_6.3V6M

1 2

PC108

3

2

ACP

SRP

19

20

PR120

133K_0402_1%

12

PR121
200K_0402_1%

B+

PL101
HCB2012KF-121T50_0805

1 2

12

PC109
@0.1U_0603_25V7K

CHGEN#

1

ACN

TP

CHGEN

PVCC

BTST

HIDRV

PH

REGN

LODRV

PGND

DPMDET

CELLS

21

SSM3K7002FU_SC70-3

12

29

28

27

26

25

24

23

22

PQ111

IREF <33>

BST_CHG

DH_CHG

LX_CHG

REGNVADJ

DL_CHG

12

PC103

4.7U_0805_25V6-K

PR108
10_1206_5%

1 2

PC110
1U_0805_25V6K

1 2

PD102

RLS4148_LL34-2

12

PC119
1U_0603_10V6K

PR117

100K_0402_5%

1 2

13

D

2

G

S

12

PC104

PC111

0.1U_0402_10V7K

12

4.7U_0805_25V6-K

1 2

12

PC105

4.7U_0805_25V6-K

BQ24740VREF

12

@47K_0402_5%
PR119

12

PC124

0.1U_0603_25V7K

CHG_B+

578

3 6

578

3 6

CHG_B+

PQ108
AO4466_SO8

241

PQ110
AO4466_SO8

241

BAT_ID <37>

12

PC122

0.047U_0402_16V7K

AC_LED<37>

PL102
10U_LF919AS-100M-P3_4.5A_20%

1 2

12

@0.1U_0603_25V7K

PR126

100K_0402_1%

12

PC126

PR139

+3VLP

100K_0402_5%

1 2

PACIN

12

PC113

PC114

4.7U_0805_25V6-K

VIN

12

PR130

2.15K_0402_1%

1 2

12

PR133
10K_0603_0.1%

PC127

22P_0402_50V8J

2

G

PR112

0.015_1206_1%

1 2

1 2

4.7U_0805_25V6-K
PC118

0.1U_0402_10V7K

12

PQ102
AM4835EP-T1-PF_SO8

1
2
3 6

4

ACOFF#

13

D

PQ114

S

SSM3K7002FU_SC70-3

BATT

12

PR122
681K_0402_1%

1 2

8

PU102B

5

P

+

O

6

-

G

LM393DG_SO8

4

49.9K_0402_1%

4

5

APL1431LBBC-TR_SOT23-5

8
7

5

12

PC115

4.7U_0805_25V6-K

7

RLZ4.3B_LL34

PR136

1 2

REF

ANODE

PC116

4.7U_0805_25V6-K

PD103

PU103

CATHODE

NC
NC

BATT

VIN

12

PR127
10K_0402_1%

12

P2

3
2
1

PR103

47K_0402_5%

1 2

12

PR105
10K_0402_5%

13

2

PQ106
DTC115EUA_SC70-3

PR124
1K_0402_5%

1 2

12

PR134
10K_0402_5%

1.24VREF

VIN

ACO FF <33>

AC_IN <33,39>

PACIN

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVIS ION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONT AINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.

2007/05/29 2008/05/29

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Docum e n t N u mb er Re v

Date: Sheet

Charger

LA-3941P

D

of

38 47Thursday, N ov em be r 15, 2007

0.1

A

[e-mail]

B

C

D

E

2VREF_51125

P PAD

VO2
VREG3
VBST2
DRVH2
LL2
DRVL2

PC302

12

PR302

30.9K_0402_1%

1 2

PR304
20K_0402_1%

1 2

PR306

ENTRIP2

3

4

5

6

VFB2

VREF

TONSEL

ENTRIP2

GND

VIN

SKIPSEL

EN0

15

16

14

13

133K_0402_1%

ENTRIP1

1 2

1

2

VFB1

ENTRIP1

24

VO1

23

PGOOD

22

VBST1

21

DRVH1

20

LL1

19

DRVL1

VREG5

VCLK

PU301

17

18

TPS51125RGER_QFN24_4X4

BST_5V

UG_5V
LX_5V
LG_5V

VL

12

PC311
10U_0805_10V6K

12

B++

PC312

0.1U_0603_25V7K

PR308

0_0402_5%

1 2

+3VL

12

B++

12

PC317

@0.1U_0402_25V4K

PC308

0.1U_0402_10V7K

1 2

PR317
100K_0402_5%

12

PC304

2200P_0402_50V7K

PR310
0_0402_5%

1 2

3/5V_OK <41>

12

12

PC313

PC305

4.7U_0805_25V6-K

4.7U_0805_25V6-K

578

3 6

241

578

3 6

241

FDS6690AS_NL_SO8

PQ302

AO4466_SO8

PL303

4.7UH_PCMC063T-4R7MN_5.5A_20%

1 2

12

PR316
@4.7_1206_5%

12

PC315
@680P_0603_50V8J

PQ304

1

+

PC310
150U_D_6.3VM

2

+5VALWP

12

PC319
@22U_0805_6.3V6M

1 1

B+

PL301

HCB2012KF-121T50_0805

1 2

2 2

3 3

B++

+3VLP

12

12

12

PC316

PC301

@0.1U_0402_25V4K

2200P_0402_50V7K

220U_6.3VM_R15

+3VALWP

PC309

PC303

4.7U_0805_25V6-K

PL302

4.7UH_SIQB74B-4R7PF_4A_20%

1

+

@4.7_1206_5%

2

@680P_0603_50V8J

PR315

PC314

ENTRIP2<6,37>ENTRIP1<37>

12

PQ301

1

D1

2

D1

3

G2

4

S2

SP8K10S-FD5_SO8

12

12

1S/2D
1S/2D
1S/2D

8

1G

7

10U_0805_6.3V6M

6

UG1_3V

5

PR309

0_0402_5%

1 2

PC306

12

1 2

PC307

0.1U_0402_10V7K

LX_3V

LG_3V

PR307

1 2

0_0402_5%

620K_0402_5%

13.7K_0402_1%

1 2

20K_0402_1%

1 2

137K_0402_1%

1 2

BST_3V

UG_3V

PR311

2VREF_51125

0.22U_0603_10V7K

PR301

PR303

PR305

25

7
8

9
10
11
12

12

13

D

PQ305

SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

A

1 2

PR318
330K_0402_1%

PC318

0.022U_0603_25V7K

AC_IN<33,38> EC_ON <33,36>

4 4

12

S

PQ308

2

G

13

D

2

G

D

S

S

2

G

1 2

PQ307

13

SSM3K7002FU_SC70-3

2

G

13

D

PQ306
SSM3K7002FU_SC70-3

S

PR313
100K_0402_5%

12

PR314
100K_0402_5%

B

PJP302

+5VALWP

VL

+3VALWP

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1 2

PAD-OPEN 4x4m
PJP303

1 2

PAD-OPEN 4x4m

C

2007/08/02 2008/08/02

(4.5A,180mils ,Via NO.= 9)

+5VALW

(3A,120mils ,Via NO.= 6)

+3VALW

Compal Secret Data

Deciphered Date

VL

Custom

D

Date: Sheet

2 1

PAD-OPEN 2x2m

2 1

PAD-OPEN 2x2m

Title

Size Document Number Rev

Compal Electronics, Inc.

+3VLP

+3VL

PJP301

+5VL

PJP304

3.3VALWP/5VALWP

LA-4111P

E

39 47Thursday, Novemb e r 15, 2007

0.1

of

A

1 1

PR401

0_0402_5%

SYSON<26,33,34,36>

1 2

PC401

@1000P_0402_50V7K

12

+5VALW

2 2

+1.8VP

3 3

PR405

0_0402_5%

PR403

316_0402_1%

12

+5VALW

12

12

PC409
1U_0603_10V6K

+1.8VP

PR404
255K_0402_1%

PR408

1 2

14.3K_0603_0.1%

1 2

PC413
@10P_0402_50V8J

PR409

10K_0603_0.1%

1 2

12

PU401

2
3
4
5
6

TON
VOUT
V5FILT
VFB
PGOOD

B

1

14

15

TP

EN_PSV

VBST

V5DRV

GND7PGND

TPS51117RGYR_QFN14_3.5x3.5

8

DRVH

TRIP

DRVL

1 2

PR402

0_0402_5%

13
12

LL

11
10
9

DH_1.8V
LX_1.8V

+5VALW+5VALW

DL_1.8V

BST1_1.8VBST_1.8V

0.1U_0402_10V7K

PR410

1 2

0_0402_5%

12

PC415

4.7U_0805_10V6K

1 2

PC402

1 2

PR406

12.1K_0402_1%

DH_1.8V_1

578

3 6

578

3 6

241

241

C

12

PC414

@0.1U_0402_25V4K

PQ401
AO4466_SO8

PQ402
FDS6690AS_NL_SO8

12

PC404

4.7U_0805_25V6-K

PL402

1 2

HCB1608KF-121T30_0603

1 2

12

PC405

2200P_0402_50V7K

1.8V_B+

12

PC403

4.7U_0805_25V6-K

2.2UH_PCMC063T-2R2MN_8A_20%

12

PR407

@4.7_1206_5%

PC412
@680P_0603_50V7K

1 2

PL401

D

B+

12

PC406
@680P_0402_50V7K

+1.8VP

1

+

PC408

2

220U_D2_4VY_R25M

PJP401

+1.8VP

4 4

1 2

PAD-OPEN 4x4m

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

(7A,280mils ,Via NO.= 14)

+1.8V

2007/05/29 2008/05/29

Compal Secret Data

Deciphered Date

C

Title

Size Document Number Re v

Date: Sheet of

Compal Electronics, Inc.

1.8VP

LA-3941P

D

40 47Thursday, November 15, 2007

0.1

A

[e-mail]

1 1

B+++

12

PC517

PC501

4.7U_0805_25V6-K

12

12

PC502

4.7U_0805_25V6-K

12

PC518

2200P_0402_50V7K

@0.1U_0402_25V4K

+1.1VS

+1.1VSP

B+++

B

PR518
0_0402_5%

1 2

1 2

PR517
10_0402_5%

+1.1VSP

PR501

11.5K_0402_1%

1 2

PR502

24.9K_0402_1%

1 2

PR505

0_0402_5%

C

PR503

18.7K_0402_1%

1 2

PR504

11.5K_0402_1%

12

+1.2VALWP

12

D

B+++

HCB2012KF-121T50_0805

PL502

B+

12

E

VCCP_POK

3

4

15

TONSEL

V5FILT

GND

V5IN

16

12

2

VFB1

TRIP1

17

12

PC515

4.7U_0805_10V6K

1

VO1

24

PGOOD1

23

EN1

BST_1.2V

22

VBST1

DR VH1

DR VL1

PGND1

TPS51124RGER_QFN24_4x4

18

PR510

16.5K_0402_1%

+5VALW

UG_1.2V

21

LX_1.2V

20

LL1

LG_1.2V

19

0_0402_5%

PR512

33K_0402_5%

1 2

12

PC512

0.1U_0402_16V7K

PR507

PR509

0_0402_5%

12

12

PC507

0.1U_0402_10V7K

1 2

UG1_1.2V

3/5V_OK <39>

PQ502

AO4466_SO8

PQ504

AO4466_SO8

578

PC516

@0.1U_0402_25V4K

3 6

241

3.3UH_SIQB74B-3R3PF_5.9A_20%

578

3 6

12

12

241

12

12

PC504

4.7U_0805_25V6-K

1 2

PR516

@4.7_1206_5%

PC520

@680P_0603_50V8J

PL503

12

PC505

2200P_0402_50V7K

+1.2VALWP

+1.2VALWP

1

+

1 2

2

PC511

PC510

4.7U_0805_6.3V6K
220U_D2_4VY_R25M

2 2

PQ501

AO4466_SO8

+1.1VSP

PL501

+1.1VSP

1

+

2

PC508

220U_D2_4VY_R25M

3 3

2.2UH_PCMC063T-2R2MN_8A_20%

12

PC509

4.7U_0805_6.3V6K

12

PR515

@4.7_1206_5%

PC519

@680P_0603_50V8J

12

12

578

3 6

241

578

3 6

241

SUSP#<26, 28,33,36,38>

@0.022U_0603_25V7K

PC506

0.1U_0402_10V7K

UG1_1.1V

PQ503
FDS6690AS_NL_SO8

0_0402_5%

@0.1U_0402_10V7K

12

PR513

PR506
0_0402_5%

12

PC513

PC503

PR5080_0402_5%

12

BST_1.1V

12

UG_1.1V

12

LX_1.1V

LG_1.1V

12

PC514

1U_0603_10V6K

PU501

25

P PAD

7

PGOOD2

8

EN2

9

VBST2

10

DR VH2

11

LL2

12

DR VL2

PR511

11K_0402_1%

1 2

12

6

5

VO2

VFB2

TRIP2

PGND2

14

13

1 2

PR514

3.3_0402_5%

(6A,240mils ,Via NO.=12)

PJP501

+1.1VSP

4 4

A

+1.1VSP

1 2

PAD-OPEN 4x4m
PJP503

1 2

PAD-OPEN 4x4m

+1.1VS

+1.1VS

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

(4A,160mils ,Via NO.=8)

+1.2VALWP

1 2

D

PJP502

PAD-OPEN 4x4m

+1.2VALW

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

1.1VSP/1.2VALWP

LA-4111P

41 47Thursday, Novemb e r 15, 2007

E

of

0.1

A

1 1

B

C

D

E

+1.8V

PU601

VIN1VCNTL

12

12

PC601

10U_0805_10V4Z

SYSON#<35,36>

2 2

SUSP<36>

3 3

1 2

PR602

0_0402_5%

SSM3K7002FU_SC70-3

1 2

PR604

@0_0402_5%

+1.5VSP

PQ601

2

G

12

PC606
@0.1U_0402_16V7K

+0.9VP

PC602

@10U_0805_10V4Z

13

D

S

PJP601

1 2

PAD-OPEN 3x3m

PJP603

1 2

PAD-OPEN 3x3m

12

PR601

1K_0402_1%

12

PR603
1K_0402_1%

2

GND

3

VREF

4

VOUT

G2992F1U_SO8

12

12

PC605
10U_0805_6.3V6M

0.1U_0402_16V7K

PC604

(2A,80mils ,Via NO.= 4)

+0.9V

(1A,40mils ,Via NO.= 2)

+1.5VS

+0.9VP

6
5

NC

7

NC

8

NC

9

TP

+5VALW

12

PC603
1U_0603_16V6K

10U_0805_10V4Z

SUSP<36>

+3VS

+1.8V

PC613

SSM3K7002FU_SC70-3

1 2

PR608

0_0402_5%

12

PC607

1U_0603_6.3V6M

12

12

PC609

@10U_0805_10V4Z

PQ602

13

D

2

G

S

12

PC610
@0.1U_0402_16V7K

(500mA,40mils ,Via NO.= 1)

PU602
APL5508-25DC-TRL_SOT89-3

2

IN

OUT

GND

1

12

PR606
1K_0402_1%

VREF1.5V

12

PR607

5.1K_0402_1%

3

PU603

VIN1VCNTL

2

GND

3

VREF

4

VOUT

G2992F1U_SO8

6
5

NC

7

NC

8

NC

9

TP

+5VALW

12

PC612
1U_0603_16V6K

+1.5VSP

12

12

PC614
10U_0805_6.3V6M

0.1U_0402_16V7K

PC611

+2.5VSP

12

12

PR605
@150_1206_5%

PC608

4.7U_0805_6.3V6K

PJP602

+2.5VSP

4 4

A

1 2

PAD-OPEN 3x3m

(500mA,40mils ,Via NO.= 1)

+2.5VS

B

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

0.9VSP/2.5VSP/1.5VSP

LA-4111P

42 47Thursday, Novemb e r 15, 2007

E

of

0.1

A

[e-mail]

+CPU_CORE_NB

VDD_NB_FB_H<6>

VDD_NB_FB_L<6>

1 1

PR204

22K_0402_1%

1 2

1 2

PC205

1000P_0402_50V7K

CPU_B+

+5VS

PC223

1 2

4700P_0402_25V7K

PR227

PC225

1 2

1200P_0402_50V7K

1 2

A

+3VS

PR216

10K_0402_1%

12

1 2

0_0402_5%

PR222

1 2

PR223

1 2

21K_0402_1%

PR218

2 2

VGATE<33>
SB_PWRGD<6,20,33>
CPU_SVD<6>

CPU_SVC<6>

VR_ON<33>

PR225

1 2

3 3

4 4

255_0402_1%

PR230

1 2

54.9K_0402_1%

CPU_VDD0_FB_H<6>

CPU_VDD0_FB_L<6>

CPU_VDD1_FB_L<6>

CPU_VDD1_FB_H<6>

1 2

1K_0402_1%

PC227
180P_0402_50V8J

+5VS

2_0402_5%

1 2

0.1U_0603_25V7K

1 2

PR212

0_0402_5%

1 2

PR213

@0_0402_5%

1 2

PR215

@10K_0402_5%

0_0402_5%

PR224

1 2

95.3K_0402_1%

PR232

1 2

6.81K_0402_1%

1 2

PC228
1000P_0402_50V7K

PR235
0_0402_5%

PR237
0_0402_5%

PR239
0_0402_5%

PR241
0_0402_5%

PR208

1 2

1 2

1 2

1 2

0.1U_0402_16V7K

PC216

SVD
SVC

PR205

2_0402_5%

1 2

PC207

12

PU201

1

OFS/VFIXEN

2

PGOOD

3

PWROK

4

SVD

5

SVC

6

ENABLE

7

RBIAS

8

OCSET

9

VDIFF0

10

FB0

11

COMP0

12

VW0

PC241
1000P_0402_50V7K

12

PC242
1000P_0402_50V7K

12

12

48

47

VIN

ISP0

14

13

ISP 0

+CPU_CORE_0

B

12

PR206

0_0402_5%

12

12

PC209

PC208

33P_0402_50V8K

1200P_0402_50V7K

12

PR210

1 2

44.2K_0402_1%

44

45

46

VCC

FB_NB

FSET_NB

COMP_NB

ISL6265IRZ-T_QFN48_6X6

RTN1

VSEN0

RTN0

ISN0

17

15

16

RTN1

RTN0

VSEN0

12

PC244

@1000P_0402_50V7K

12

PC245

@1000P_0402_50V7K

12

@1000P_0402_50V7K

B

VSEN_NB

43

18

VSEN1

PC246

12

PC243

VSEN_NB

VSEN1

@1000P_0402_50V7K

12

PR209

1000P_0402_50V7K

RTN_NB

42

RTN_NB

VDIFF1

19

PC247

12

0_0402_5%

12

PR207

40

41

PGND_NB

OCSET_NB

COMP121ISP1

FB1

20

PL201

4.7UH_SIQB74B-4R7PF_4A_20%

1

+

PC202
220U_D2_4VY_R25M

2

PC201

10U_0805_6.3V6M

0.1U_0603_16V7K

11.3K_0402_1%

UGATE NB

PHASE NB

LGATE NB

37

38

39

BOOT_NB

LGATE_NB

PHASE_NB

UGATE_NB

BOOT0

UGATE0

PHASE0

PGND0

LGATE0

LGATE1

PGND1

PHASE1

UGATE1

BOOT1

VW1

ISN1

22

23

24

+CPU_CORE_1

C

12

PQ201

AO4466_SO8

1
2
3 6

12

PC206

BOOT_NB1

12

PR211

1_0603_5%

2.2_0603_5%

1 2

PR228

12

12

PR214

1 2

1 2

0_0603_5%

PR219

PR226

1 2

0_0603_5%

1 2

PC224

0.22U_0603_10V7K

PC232

1200P_0402_50V7K

4700P_0402_25V7K

PVCC

TP

49

BOOT_NB

36
35

UGATE0

34

PHASE0

33
32

LGATE0

31
30

LGATE1

29
28

PHASE1

27

UGATE1

26

BOOT1

25

ISP 1

1000P_0402_50V7K

6.81K_0402_1%

BOOT0

2.2_0603_5%

PC230

PR236

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

8
7

5

4

0_0402_5%

12

PC210

2.2U_0603_6.3V6K

SI4684DY-T1-E3_SO8

PQ204

SI4684DY-T1-E3_SO8

PQ207
AO4456_SO8

PC231

12

PR238

54.9K_0402_1%

12

PR240

1K_0402_1%

PR243

255_0402_1%

12

PHASE NB

UGATE0_1

578

578

12

LGATE NB

+5VS

0.22U_0603_10V7K
PC217

1 2

AO4456_SO8

180P_0402_50V8J

PC233

2007/08/02 2008/08/02

PQ202

AO4466_SO8

1
2
3 6

4

PR203

1 2

UGATE NB

5

PQ203

4

578

3 6

241

3 6

241

12

12

UGATE1_1

PQ206

3 6

5

4

578

Compal Secret Data

Deciphered Date

8
7

5

D8D7D6D

S1S2S3G

241

3 6

241

12

PC238

PC239

330P_0402_50V7K

PQ205

AO4456_SO8

D8D7D6D

S1S2S3G

PQ208

AO4456_SO8

470P_0402_50V7K

12

PC234

PR220

D

12

PC203

2200P_0402_50V7K

12

PC235

4.7U_0805_25V6-K

12

4.7_1206_5%

12

PC240

@0.1U_0402_25V4K

12

12

D

CPU_B+

12

PC204

4.7U_0805_25V6-K

CPU_B+

12

4.7U_0805_25V6-K

PC218

470P_0603_50V8J

12

PR229

4.7_1206_5%

PC226
470P_0603_50V8J

12

12

PC213

PC212

4.7U_0805_25V6-K

4.7U_0805_25V6-K

0.36UH_PCMC104T-R36MN1R17_30A_20%

PR221

14K_0402_1%

PC219

0.1U_0603_25V7K

12

12

PC236

PC237

4.7U_0805_25V6-K

4.7U_0805_25V6-K

PR231

PC229

0.1U_0603_25V7K

+CPU_CORE_0

+CPU_CORE_0

E

1

12

+

2

+CPU_CORE_0

CPU_B+

+CPU_CORE_1

B+

PC215

1000P_0402_50V7K

43 47Thursday, Novemb e r 15, 2007

of

PL202

SMB3025500YA_2P

12

12

PC214

PC248

2200P_0402_50V7K

3300P_0402_50V7K

12

PL203

PR217

6.65K_0603_1%

1 2

1 2

ISP 0

12

12

PC220

PC221

4.7U_0805_25V6-K

4.7U_0805_25V6-K

PL204

0.36UH_PCMC104T-R36MN1R17_30A_20%

12

PR233

14K_0402_1%

6.65K_0603_1%

1 2

1 2

ISP 1

Title

Size Document Number Rev

Custom

Date: Sheet

12

12

12

PC211

PC249

PC250

@47U_25V_M

3300P_0402_50V7K

1800P_0402_50V7K

12

12

PC222

2200P_0402_50V7K

12

PJP201

1 2

PAD-OPEN 4x4m

PJP202

1 2

PAD-OPEN 4x4m

+CPU_CORE_1

+CPU_CORE_1

Compal Electronics, Inc.

CPU_CORE

LA-4111P

E

0.1

A

B

C

Version Change List ( P. I. R. List ) for Power Circuit

D

E

Page#

1 1

1

37

2

41

3

41

43

4

5

43

2 2

43 Add PJP201、PJP202

6

7

38 Charger 9/29 Compal the footprint is wrong Change the footprint of PR102

8

37

9

38 Charger 10/08 Compal the footprint is wrong Change the footprint of PR102

10

40 1.8VP 10/08 Compal Delete PC410 and PC411

Title

DC Connector
/CPU_OTP

1.1VSP/1.2VALWP Compal HW request

CPU_CORE Compal HW request

CPU_CORE Compal

CPU_CORE

DC Connector
/CPU_OTP

Request

Date

9/29

9/29

9/29

9/29

9/29

9/29

Owner

Compal

Compal1.1VSP/1.2VALWP

Compal

for Layout

HW request

TI FAE suggested that after he review
the layout.

TI FAE suggested that after he review
the layout.

Solution Description

PL3 change the value from SMB3025500YA_2P to HCB2012KF-121T50_0805
and add PL4 the same of the value.

PC508 and PC511 change the value from 220U_6.3VM_R15 to
220U_D24VY_R25M

Add PJP503

PC202 change the value from 220U_6.3VM_R15 to 220U_D24VY_R25M

Add PC241 PC242 PC243, and the val
Reserve PC244 PC245 PC246 PC2
1000P_0402_50V7K.

、、

、、、

ue are 1000P_0402_50V7K.

47, and the value are

10/08 Compal for Layout These two choke are parallel ,it's not series.

PWR request

Rev.Issue DescriptionItem

11

3 3

4 4

41 1.1VSP/1.2VALWP 10/08 Compal Add PR517、PR518PWR request

12

37

13

37 11/01 Compal for Layout change PQ301, Cencel PQ303

14

43 CPU_CORE EMI requestCompal11/02 Add PC248, PC249, PC250

15

37 3.3VALWP/5VALWP 11/12 Compal for Layout Change PC310, add PC319

DC Connector
/CPU_OTP

3.3VALWP/5VALWP

A

11/01 Compal PWR request Add PD4、PC12

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Power Changed-List History-1

LA-4111P

E

of

44 47Thursday, Novemb e r 15, 2007

0.1

A

[e-mail]

B

Version Change List ( P. I. R. List ) for HW Circuit

C

D

E

Item Issue DescriptionDate
125

1 1

225

429

45 0.2
629
734
8 11, 35

2 2

9 11, 21

Title

LAN 10/29
LAN 10/29

CRT 10/29
Audio

FAN
Speaker

10/30
11/01

11/01
MDC 11/01
TV_OUT 11/05

NB/SB Thermal 11 /05
SB SATA 11 /05

Owner
HW Change LAN Chip U20 from Marvell 88E8042 to

Realtek RTL8102EL

HPQ Add POE(Power Over Ethernet) design
HW CR T ca n not display

HW Speaker no sound

FAN Conn. not correct partHW
HW Speaker Conn. not correc t part
HW MDC Conn. not cor rect part 0.2
HW TV-OUT Function no support

HW N B Therm al Function no support (locate too far)
HW SB SATA Port 5 change to Port 2 for ATI Common

Design

11 0.221
12 21 0.2

13 31 0.2
14 29

3 3

15 25
16 0.221,24
17 36

18 27

SB SATA 11 /05
SB GPIO 11/05

SB SATA 11 /05
Audio HP OUT 11 /05
LAN Transfermor11/05
SB SATA 11 /06
DIM LED 11 /06

CardReader 1 1/06

HW SB SATA_ACT# Pull High become +3VS
HW Change SB GPIO refer to JBK00 for c ommon

HW Vertical L51 1<-->4 , 2<-->3 for layout routing
HW 0.2Add 150UF Caps for each DOCK_LOUT_R/L
HW Corre ct U19 LAN Transfermor pin definition
HW SB SATA Port 4 change to Port 3 for ATI Op en Issue
HW 0.2Reduce DIM LED unnecessary design

HW 0.2Change CardReader Socket for M/E new part and

Chip for JMicron new version

4 4

Solution Description

Update the LAN Design page and support circuit
Update the LAN Design page and support circuit

Change the CRT Conn. signals connection first.
Wait corre ct symbol for fix
Add R973(10K_0402) to +3VALW on HP_DET#

Change JP2 P CB Foo tprint f rom ACES_85204-02001_2P to
ACES_88231-02001_2P
Change JP20 PCB Fo otprint from ACE S_85204-04001_4P to
ACES_88231-04001_4P
Change JP20 PCB Fo otprin t from ACES_88018-124G_12P to
ACES_88020-12101_12P
Del R59,R60,R61,R115,R116,R117 and TV-OUT related design.

Cancel NB_ THERM AL_DA/DC connection between NB and
SB,del C500
Change SB SATA port 5 to port 2

Change R343.1 power rail from +5VS to +3VS. Install R343.

1. Connect U15.C6 to GND by 0_0402.

2. Change WL OFF# from GPIO50 to GPIO61.

3. Change BT_COMBO_EN# from GPIO51 to GPIO62.

4. Change WW OFF# f rom GPIO52 to GPIO63.
Vertical L51 1<-->4 , 2<-->3 for layout routing

Add 150UF Caps for each DOCK_LOUT_R/L
Correct U19 L AN Transfermor pin definition
Change SB SATA port 4 to port 3
Del R1026 and Q167, add Net "DIM_LED#" for connect.

Change loca tion from PJP604 to PJP8.
Change JREAD to TAITW_R015-B10-LM.
Reserve R413,C902 close to JREAD.20;
R412,C901 close to JREAD.26; R411,C900 close to JREAD.37.
Change R457 close to U23.42
Add R455,R456 close to U23.42
Del Q169,R1051.
Change net C R_L ED# become CR_ LED connect U23.21 and Q53.2
Add R454 pull down to GND
Change R405,R122 from 200K to 10K pull-high
Remove C895,U22

Rev.Page#

0.2

0.2

0.2316

0.2

0.2

0.2

0.2

0.21 0 21,31

0.2

Request

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

HW Changed-List History-1

LA-4111P

45 47Thursday, Novemb e r 15, 2007

E

0.2

of

A

B

Version Change List ( P. I. R. List ) for HW Circuit

C

D

E

Item Issue DescriptionDate
19 16

1 1

Title

CRT 11/07

Owner
HW Normaliz e CRT design for common

Solution Description

Change L83,L84 (10_0402) become R241,R240

Rev.Page#

0.2

(0_0603)

Request

1720

21 18

22 33

LCD 11/07
LCD 11/07
KBC 11/07

HW Normalize LCD design for common

CIC CIC feedback RMA co ncern for common

HW Normalize KB926 Crysta l part for common

Change R491 from 200_0402 to 200_0805
Change Q43 from AOS3413 to SI2301
Change Y7 from 9H03200413 small size become

0.2

0.2

0.2

1TJS125DJ4A420P normal size.

23

17

2 2

1824 HW

25 19,32

26 25

27 18
28 6
29 33
30 35

2631 0.2

3 3

32 33
33 27

34 34

35 21

4 4

36 33

WebCam 11/09

11/09HDMI

SB-CLK-Debug 11/09
LAN 11/09
HDMI 11/09

CPU 11/09
KBC 11/09
Holes 11/09

11/09Mini-Card

KBC 11/09
CardReader 1 1/10

LED Function 11/10

SB-GPIO 1 1/10
KBC-GPIO 11/11

HW Change U54 WebCam power design and related

Reduce HDMI Design
HW Debug C ard no function issue

HW RJ4 5 LED Power correct back

HW Reduce HDMI D esign
HW Add H_THERMTRIP# one more way
HW Up date KBC Pin D efinition for common
ME Update for M/E Drawing
HW

Reduce Mini-Card design, change SIM Card design
HW Reserve 0_0603 for KB Back Light

HW Correct CardReader LED part
HW Corre ct LED function for common

HW Ad d one mo re way for GSENSOR LED# inform pin
HW Add CIR_IN P H to +5VL

Add ESB_CLK/DAT PH to +3VL

Change U54 from G916-390T1UF to RT9193-39GB.
Remove R891,R892 if no use G916-390T1UF.
Add C718 close to U54.4 for RT9193-39GB.
Remove R1027~R1030 for JP7 no install.
Change JP7 from 8pin to 6pin

Remove R490(100K_0402)

Del R1031,add R303 close to R301 and U15.P2
Connect for CLK _PCI_SIO2 to JP41.15

Change JRJ45.13 and JRJ45.11 from +3V_LAN_LED to
+3V_LAN

Remove R490(100K_0402)
Add R16 close to Q3.1 for H_THERMTRIP#
Add H_THERMTRIP# to U33.25
Del H49 H50 H38 H45 for M/E drawing change

Replace D17 and D 47 become R52 and R53
Del R400 and R46, Change JP6 pin definition for common

Add R516 (0_0603) between JP48.1/4 and +5VS_LED
Change D5 from SC500004E00(AQUA_WHITE) to
SC500004W00(WHITE)

Change LED from D5 0,D30,D27 SC500004E00
(AQUA_WHITE) to D6,D7,D8 SC500004W00(WHITE)
Change LED from D45, D46 SC500004B00
(AQUA_WHITE/AMBER) to D17,D18 SC50 0005M00
(YELLOW/WHITE)
Add Q7,R20 and R42 close to D18
Add HDD_HALTLED# connect from U15.P8
Add R46 10K_0402 PH to +5VL close to U33
Add R514,R515 10K_0402 PH to +3VL close to U33

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.2

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

HW Changed-List History-2

LA-4111P

46 47Thursday, Novemb e r 15, 2007

E

0.2

of

A

[e-mail]

B

Version Change List ( P. I. R. List ) for HW Circuit

C

D

E

Item Issue DescriptionDate
37 6,31

1 1

38 11

Title

CPU,FPR
NB

11/13
11/13

Owner
HW Reduce S3 power consumption

HW Re duce th e level shift design for Chip A12.

Solution Description

Change R15.2,R21.2,R36.2,R30.2 connection from
+1.8V to +1. 8VS; R emove R622, install R581

Del Q6,R87; Q 5,R84 and replace by 0ohm (add R67,R68)

Rev.Page#

0.2

0.2

connect di rect ly. Install R371 (10K ohm)

Request

39 17
40 6,33

WebCam

11/13

CPU,KBC 11/13

HW Update the WebCam+Digital Mic reserve r conn.
HW Update THERMTRIP# design t o EC

Change JP7 from SP02000HC00(8pin)-->SP02000IL00(6pin)

Change R16.2 connection from THERMTRIP# to

0.2

0.2

THERMTRIP#_EC for separate

41 18
42 19.32

HDMI 11/13
SB,BIOS 11 /13

HW Re move EMI solution become reserve for verify
HW Re duce SB related design for Chip A12 and others

Add R112,R113,R115~R120 close to each L85~L88 for co-lay

Del Q155,R986, and add R311 close to U15.

0.2

0.2

Del R1011 become T18, Cancel R1012 and connect to H31
and JP41 directly

43 21,32

2 2

44 25
45 13
46 18
47 20

SB,BIOS 1 1 /1 3
LAN 11/13

NB 11/13
HDMI 11/13
SB 11/13

HW BIOS Debug Tool reserve
HW Up date L AN Chip Symbol link to CIS server

HW Add 0ohm_0603 to separate VDD18_MEM
HW Reduce HDMI related design for common
HW R educe SB related design for common and A12 chip

Add SB_INT_FLASH_SEL and related
(JP12,U30,R228,R226,C489 close to U29)

Update LAN Chip U20 Symbol link to CIS server
Add R1051(0_0603) between +1.8VS & +1.8V_VDD_SP
Del R490 (100K_0402)
Remove R994 (0_0402)

0.2

0.2

0.2

0.2

0.2

Change U15.F1 connection become test point
Remove R1053, change R1052 become 0_0402

48 20 ,21,

SB,Cardreader 11/ 13

27

49 21,33
50 28,33
51 33

3 3

52 33

SB,KBC 11/1 3
Codec,KBC 11 /13
KBC 11/13

KBC 11/13

HW Reserve Cardreader D3E f unction (CR_WAKE# &

CR_CPPE#)
HW Reduce SB related design for common

HPQ EC_BEEP function for KBC add
HW Reduce S5 Power Consumption

HW Reduce KBC Design for common and Ver:C0 Chip

Change from SA00001J530 to SA00001J540

53 34

54 34

Switch Design 11/13

LED 11/14

HW Update CSD function board design for common

HW Correct T/P On/Off LED desi gn define

Correct G-Sensor LED design define

29

Audio-Dock 11 /14
Holes 11/14

5 7 M E Update Symbol to meet M/E Drawing

4 4

Multi-Bay 11/14

HPQ For GS mark requirement
ME Update Holes to meet M/E Drawing

Add R81 close to U15;Q54,R124 close to U23 for connect U15.F8
to U23.13 ;Add R369 close to U23 for connect U15.M5 to U23.16
Del D51 and R1034, Change the net AC_ IN become AC_IN_D

Add R563 close to C955; Add R544 close to U33.31
Change R1040.1 connection from +3VL_EC to +3VALW

Del R546 PH to +3VL_ EC, Del D26 replace by add R547 close to
U33 for short

Del R537 become Test Point, change R516 become 150_0603
Remove R1044, change R1040 from 10K to 100K
Change R528.2 , R529.2 connection from +5VALW to +5VL
Install C814 (1U_0805)

Change JP36 .1 connec tion beco me + 3VL;Change R1046.1
and R1047.1 connection become SMB_EC_CK1/DA1
Change JP36.7 connection from G ND to +5VALW_LED by

Change Q153 from 2N7002DW to 2N7002
Change R98 8.1 connection from +5VS_LED to +3VS
Add R968,R969 close to C775/C776.

Add back H52 become H_1P5N; Del CF4
Update JP2,JP9,JP10,JP11,JP20,JP40,JHDMI,JESAT,JCRT,

JDOCK Symbol

0.2

0.2

0.2

0.2

0.2

0.2

0.2

0.255

0.256 29

0.24,24

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

HW Changed-List History-2

LA-4111P

47 47Thursday, November 15, 2007

E

0.2

of