HP CQ36 Schematics

A

1 1

2 2

B

C

D

E

Compal confidential

Schematics Docu ment

Mobile Auburndale rPGA989 with

3 3

4 4

A

Intel PCH(Ibex Peak-M) core logic

2009-04-13

Secur i t y Classification

Issued Date

THIS SHEET OF ENGINEE RING DRAWING IS TH E PROPRI ETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAI NS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS AUTHOR IZED BY COM PAL ELECTRONICS, IN C. N EITHER THIS SHEET NOR THE INFORMATION IT CONTAIN S

http://laptop-motherboard-schematic.blogspot.com/

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRON ICS, INC.

C

2007/08/28 2006/03/10

Compal Secret Data

Dec iphered Date

Title

Size Document Number Re v

Custom

D

Date: Sheet

Compal Electronics, Inc.

Cover Sheet

Cal p el la D I S L A4743P

0.1

of

149Monday, April 13, 2009

E

A

B

C

D

E

Compal confidential

1 1

Nv id ia
NB10M-GE

VRAM DDR3
128/512MB

page 28,29

2 2

Dis

HDMI Conn.

PCI-E BUS*4

Fan conn

page 24,25,26,27

Dis Dis(UMA)

Page 6

LCD Conn.

page 21

MUX

CRT

page 20

MUX

Dis(UMA)Dis

Level Shifter

page 23

page 23

Calpella Consumer 13.3" UMA +Switchable

USB2.0 X12

32QFN

P19

DDR 3 S O- D IMM X2

BANK 0, 1, 2, 3

USB Card Reader

USB conn x3

BT Conn

USB Camera

Finger print

PCIE-Express 16X

UMA

UMA

UMA

Mobile Arrandale

2C CPU + GMCH

Socket-rPGA989

Page 6,7,8,9,10

DMI X4

Intel PCH

Ibex Peak-M
FCBGA 951

Page 11,12,13,14,15,16

CK505

Clock Generator
SLG8SP585VTR

DDR3 1066/1333 MHz 1.5V

Dual Channel

Azalia

SATA Master-1

SATA Slave

P17, 18

P33

P36

P36

P21

P36

Audio CKT

JMC261 (LAN
+Card reader)

3 3

Mini-Card

WLAN

P31

RJ45/11 CONN

P31

Mini-Card

WWAN

P32P32 P32

New Card

LPC BUS

SPI

SPI ROM 16M

P34

MX25L1605AM2C-15G

SATA HDD Connector

Codec_IDT92HD81

P34 P35

Audio Jack

P30

ENE

KB926

P38

SATA ODD Connector

P30

C

P37

Int.KBD

P38

2006/02/13 2006/03/10

Compal Secret Data

Dec iphered Date

D

USB B o ard Conn
USB conn x2

Capsense switch Conn

Title

Size Document Number Re v

Custom

Date: Sheet

Compal Electronics, Inc.

Block Diagram

Cal p el la D I S L A4743P

E

249Monday, April 13, 2009

P33

P36

of

0.1

RTC CKT.

P21

LED

P36

ACC E LEROMETER
ST

4 4

P27

Touch Pad CONN.

P39

SPI ROM
SST25VF080

K/B b ac k light Conn

P36

Secur i t y C lassification

DC/DC Interface CKT.

P38

A

http://laptop-motherboard-schematic.blogspot.com/

B

Issued Date

THIS SHEET OF ENGINEE RING DRAWING IS TH E PROPRI ETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAI NS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS AUTHOR IZED BY COM PAL ELECTRONICS, IN C. N EITHER THIS SHEET NOR THE INFORMATION IT CONTAIN S
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRON ICS, INC.

A

Symbol Note :

Voltage Rails

power
plane

State

S0

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Batt ery
don't exist

1 1

SMBUS Control Table

SOURCE

SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
SMBCLK
SMBDATA
SML0CLK
SML0DATA
SML1CLK
SML1DATA

KB926

KB926

PCH

PCH

PCH

O MEANS ON X MEANS OFF

+B

O
O
O
O
O

+5VALW

+3VALW

O
O
O
O

X
XX

XDP BATT

X V
X

V

X

Thermal
Sensor

X
X
X
X

X

X

X

+1.8V

+5VS
+3VS
+1.5VS
+0.9V
+VCCP
+CPU_CORE
+2.5VS
+1.8VS

O
O
O

X
X
X

SODIMM CLK CHIP

X
X

WLAN
WWAN

X
X

X

X

VVV

X

X

X

+3VALW +3VALW+3VS+3VS+3VS +3VS+5VL +5VL

O
O

X
X
X
X

NB10M
Thermal
Sensor

X
XX
X
X
X

: means Digital Ground

: means Analog Ground

@ : means just reserve , no build

45@ : means need be mounted when 45 level assy or rework stage.
BATT @ : means need be mounted when 45 level assy or rework stage.
CONN@ : means ME part

SG@ : means stuff when Switchable graphic

UMA@ : means stuf f when UM A skus

VRAM@ : X76 level

8111DL@ : Only for Giga LAN
DE B UG@ : For debug
Cypress@ : Only For Cypress Capacito r sensor board

ENE@ : Only For ENE Capacitor sensor board

M3@ : Only For Intel DDR3 V RE F

PA@ : Only For PA

PR@ : Only For PR

NB10M-GE

X

X
X

Cap sensor
board

NEW

G sensor

CARD

V

X

X

X

XX
X

X

VV

X

X

XXXXXXXXX X

PCH I2C / SMBUS ADDRESSING

DEVICE

DDR SO-DIMM 0
DDR SO-DIMM 1
CLOCK GENERATOR (EXT.)

45172932L01ΚSwitchable graphic
45172932L02ΚUMA only

USB assignment:

USB-0 Right side
USB-1 Right side
USB-2 Left side(with ESATA)
USB-3 X
USB-4 Camera
USB-5 WLAN
USB-6 Bluetooth
USB-7 F i nger Printer
USB - 8 M iniCard (WW AN/T V)
USB-9 Express card
USB-10 X
USB-11 X

PCIe assignment:

PCIe-1 WWAN
PCIe- 2 WLAN
PCIe- 3 LAN
PCIe-4 New card
PCIe- 5 X
PCIe- 6 X

SATA assignment:

SATA0 HDD
SATA1 ODD
SATA2 X
SATA3 X
SAT A4 ESATA
SATA5 X

HEX

A0

D2

ADDRESS

1 0 1 0 0 0 0 0
1 0 1 0 0 1 0 0A4
1 1 0 1 0 0 1 0

NB10M -GE SMBUS Control Table

D_EDID_DATA
D_EDID_CLK
D_CRT_DDC_DATA
D_CRT_DDC_DATA
HDMIDAT_VGA
HDMICLK_VGA

SOURCE LVDS CRT

NB10M

NB10M

NB10M

V

X
X

HDMI

XX

X

V

X

V

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEE RING DRAWING IS TH E PROPRI ETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAI NS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS AUTHOR IZED BY COM PAL ELECTRONICS, IN C. N EITHER THIS SHEET NOR THE INFORMATION IT CONTAIN S

http://laptop-motherboard-schematic.blogspot.com/

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRON ICS, INC.

A

2007/08/28 2006/03/10

Compal Secret Data

Dec iphered Date

Title

Size Do c ument Number Re v

Custom

Date: Sheet

Compal Electronics, Inc.

Notes List

Cal p el la D I S L A4743P

of

349Monday, April 13, 2009

0.1

5

4

3

2

60mA

+3VAUX_BT

1

50mA

1A

D D

VIN

AC

C C

B+

7A

+V_BATTERY Dock con

0.3A

INVPWR_B+

2A

B++

LVDS CON

1.7A

+3VALW

+1.5VS

+5VALW

35mA

169mA

300mA

MDC 1.5

ICH9

LAN

3.39A5.89A

+3VS

RT5158

??mA

???A

1.3A0.58A

Mini card

New card

+5VS

35mA

10mA

25mA

20mA

10mA

1A

811mA

1.5A

250mA

1A

1A

+VDDA
IDT 9271B7

+5VAMP

Finger printer

+3VS_DVDD
ALC268

+3VALW_EC

SPI ROM

New card

PCH

+LCDVDD

LVDS CON

+3VS_CK505

Mini card (WLAN)

Mini card (TV tu/WWAN/Robeson)

1.8A

B B

3.7 X 3=11.1V

DC

BATT

B+++

A A

CPU_B+ +VCC_CORE

5

11.05A1.9A

4.7A

+1.5V

1.05V_B+

+1.05VS PCH

10mA2A

http://laptop-motherboard-schematic.blogspot.com/

4

38A/1.05V

3A

8 A

50mA

+VCCP

2.59A

CPU

CPU

DDR3 800Mhz 4G x2

+0.75V

162mA

??A

Securi ty Classification

Issued Date

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPER TY OF COMPAL ELECTR ONI CS, INC . AN D C ONT AINS CO NFID ENTI AL
AND TRADE SECRET INFORMATION. THIS SH EET MAY NOT BE TRANSFERED FRO M TH E CU STO DY O F TH E CO MPET ENT DIVI SIO N O F R& D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHE R TH IS SHEE T NO R TH E I NFOR MATI ON IT C ONTA INS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRI TTEN CON SENT OF COM PAL ELEC TRO NIC S, I NC.

3

PCH

CPU

2007/08/28 2006/03/10

700mA

50mA

Compal Secret Data

Dec iphered Date

ODD

SATA

PC Camera(4.75V)

2

Compal Electronics, Inc.

Title

Size Document Number Re v

C

Calpella DIS LA4743P

Date: Sheet

Pow e r d elevry

1

449Mond ay, April 13, 2009

of

0.1

A

1 1

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEE RING DRAWING IS TH E PROPRI ETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAI NS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS AUTHOR IZED BY COM PAL ELECTRONICS, IN C. N EITHER THIS SHEET NOR THE INFORMATION IT CONTAIN S

http://laptop-motherboard-schematic.blogspot.com/

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRON ICS, INC.

A

2007/08/28 2006/03/10

Compa l Secret Data

Dec iphered Date

Title

Size Do c ument Number Re v

Custom

Date: Sheet

Compal Electronics, Inc.

Notes List

Cal p el la D I S L A4743P

of

549Monday, April 13, 2009

0.1

Layout rule 10mΚil
width trace length <

0.5", spacing 20mil

D D

H_PECI<14>

H_PROCHOT#<46>

H_THERMTRIP#<14>

H_CPURST#

H_PM_SYNC<13>

H_CPUPWRGD

H_CPUPWRGD<14>

PM_DRAM_PWRGD<13>

C C

From power

VTTPWR GOOD<44>

BU F _ PLT_ RS T#<14>

5

R1 20_0402_1%

1 2

R3 20_0402_1%

1 2

R5 49.9_0402_1%

1 2

R7 49.9_0402_1%

1 2

TP_ S KTOCC#

T1PAD

H_C A TE RR#

R10

1 2

R15

1 2

R19

1 2

R20

1 2

R21

1 2

R23

1 2

R24

1 2

R25

1 2

R26

1 2

1.5K_0402_1%

750_0402_1%

H_P EC I_ISO

0_0402_5%

H_PROCHOT#

H_THERMTRIP#_R

0_0402_5%

H_CPURST#_R

0_0402_5%

H_PM_SYNC_R

0_0402_5%

SYS_AGENT_PWROK

0_0402_5%

VCCPWRGOOD_0

0_0402_5%

VDDPWRGOOD_R

0_0402_5%

H_ P W R G D _ XDP_RH_PWRGD_XDP

0_0402_5%

PL T_RST# _ R

12

R28

COMP3
COMP2
COMP1
COMP0

JCPU1B

AT23

COMP3

AT24

COMP2

G16

COMP1

AT26

COMP0

AH24

SKTOCC#

AK14

CATERR#

AT15

PECI

AN26

PROCHOT#

AK15

THERMTRIP#

AP26

RESET_OBS#

AL15

PM_SYNC

AN14

VCCPWRGOOD_1

AN27

VCCPWRGOOD_0

AK13

SM_DRAMPWROK

AM15

VTTPWRGOOD

AM26

TAPPWRGOOD

AL14

RSTIN#

IC , A U B _ CF D_r PGA, R1 P0

CONN@

MISC THERMAL

PWR MANAGEMENT

CLOCKS

DDR3

MISC

JTAG & BPM

4

BCLK

BCLK#

BCLK_ITP

BCLK_ITP#

PEG_CLK

PEG_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

SM_DRAMRST#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

PM_EXT_TS#[0]
PM_EXT_TS#[1]

PRDY#
PREQ#

TCK
TMS

TRST#

TDO

TDI_M

TDO_M

DBR#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

3

CLK_CPU_BCLK

A16

CLK_CPU_BCLK#

B16

CLK_CPU_XDP

AR30

CL K _ C PU_XDP#

AT30

CL K_EXP

E16

CL K_EXP#

D16
A18

A17

F6
AL1

AM1
AN1

AN15
AP15

AT28
AP27

AN28
AP28
AT27

AT29

TDI

AR27
AR29
AP29

AN25

AJ22
AK22
AK24
AJ24
AJ25
AH22
AK23
AH23

eDP

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

PM_EXTTS#0
PM_EXTTS#1

XDP_PRDY#
XDP _PREQ#

XDP_TCK
XDP_TMS
XD P_ TRST#

XDP_TDI_R
XDP_TDO_R
XDP_TDI_M
XDP_TDO_M

XDP _ D BRESET#

XDP_ BPM#0
XDP_ BPM#1
XDP_ BPM#2
XDP_ BPM#3
XDP_ BPM#4
XDP_ BPM#5
XDP_ BPM#6
XDP_ BPM#7

R14 0_0402_5%

DRAMR ST# <17,18>

T63 P AD

1 2

PM_EXTTS#0
PM_EXTTS#1

CLK_ C PU_BCLK <14>
CLK_CPU_BCLK# <14>

CLK_EXP <12>
CLK_EXP# <12>

R27 10K_0402_5%
R29 10K_0402_5%

1 2
1 2

OK

PM_EXTTS#1_R <17,18>

from DDR

+VCCP

H_CPUPWRGD

PM_PW RB TN#_R<13>

H_PWRGD_XDP

+VCCP

1

C1

@

0.1U_0402_16V4Z

2

R13
1K_0402_5%

1 2

R16 0_0402_5%

1 2

XDP _PREQ#
XDP_PRDY#

XDP_ BPM#0
XDP_ BPM#1

XDP_ BPM#2
XDP_ BPM#3

XDP_ BPM#4
XDP_ BPM#5

XDP_ BPM#6
XDP_ BPM#7

H_CPUPWRGD_R
PM_PWRBTN#_R

2

XDP Connector

JP1

1

GND0

3

OBSFN_A0

5

OBSFN_A1

7

GND2

9

OBSDATA_A0

11

OBSDATA_A1

13

GND4

15

OBSDATA_A2

17

OBSDATA_A3

19

GND6

21

OBSFN_B0

23

OBSFN_B1

25

GND8

27

OBSDATA_B0

29

OBSDATA_B1

31

GND10

33

OBSDATA_B2

35

OBSDATA_B3

37

GND12

39

PWRGOOD/HOOK0

41

HOOK1

43

VCC_OBS_AB

45

HOOK2

47

HOOK3

49

GND14

51

SDA

53

SCL

55

TCK1

57

TCK0

59

GND16

SAMTE_BSH-030- 01 -L - D-A CO NN@

XDP_RST#_R

R22 0_0402_5%@

1 2

GND1
OBSFN_C0
OBSFN_C1

GND3

OBSDATA_C0
OBSDATA_C1

GND5

OBSDATA_C2
OBSDATA_C3

GND7
OBSFN_D0
OBSFN_D1

GND9

OBSDATA_D0
OBSDATA_D1

GND11
OBSDATA_D2
OBSDATA_D3

GND13

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

GND15

TRST#

GND17

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

TD0

54
56

TDI

58

TMS

60

CLK_CPU_XDP
CL K _ C PU_XDP#

XDP _RST#_R
XDP _ D BRESET#_ R

XDP_TDO
XD P_ TRST#
XDP_TDI
XDP_TMSXDP_TCK

XDP _ D BRESET#

PLT_RST# <14,31,32>

1

XDP_TDI

R2 51_0402_1%@

1 2

R4 51_0402_1%@

XDP_TMS
XDP _PREQ#
XDP_TDO

This shall place near CPU

XDP_TCK

1 2

R6 51_0402_1%@

1 2

R8 51_0402_1%

1 2

R9 51_0402_1%@

1 2

+VCCP

R17
1K_0402_5%

1 2

1 2

R18

0_0402_5%

R603 1K_0402_5%

1 2

H_CPURST#

XDP _ DBRESET# < 13 >

+VCCP

+3VS

JTAG MAPPING

+1.5V

Fan Voltage Control circuit

SI-1 Change to voltage control circuit

+5VS

+3VS

1 2

1

2

U32

9

Thermal P ad

8

GND

7

GND

6
5

VSET

GND
GND

G99 6 RD1U_TDFN8_3X3

FAN_SET<37>

VEN

1
2

VIN

3

VO

4

R678

10K_0402_5%

FAN_SPEED<3 7>

FAN_SPEED

C775

1000P_0402_50V7K

1

C2

2.2U_0603_6.3V4Z

2

1

C774

2.2U_0603_6.3V4Z

2

+5VS_FAN

+5VS

D1

3

Vcc

2

Line to be protect ed

1

GND

DLPT05-7-F_SOT23-3

FAN_SPEED

1

C3

0.1U_0402_16V4Z

2

1
2
3

CONN@

JFAN1

1

4

2

G1

5

3

G2

ACES_85204-03001

XDP_TDI_M

XDP_TDO_R

XD P_ TRST#

R30 0_0402_5%

1 2

R32 0_0402_5%@

1 2

R34
0_0402_5%

1 2

R37 0_0402_5%@

1 2

R38 0_0402_5%

1 2

R39 51_0402_1%

1 2

XDP_TDI

XDP_TDOXDP_TDO_M

VDDPWRGOOD_R

R31 4.75K_0402_1%
R33 12K_0402_1%

CRB 0.9 R38 change to 1K

1 2
1 2

XDP_TDI_R

Processor Pullups

H_CATERR#
H_CPURST#_R

B B

H_PROCHOT#

R35 49.9_0402_1%

1 2

R36 68_0402_5%@

1 2

R11 68_0402_5%

+VCCP

12

DDR3 Compensation Signals

SM_RCOMP0

R40 100_0402_1%

SM_RCOMP1
SM_RCOMP2

Layout Note:Please these
resistors near Processor

A A

1 2

R41 24.9_0402_1%

1 2

R42 130_0402_1%

1 2

Security Classification

Issued Date

THIS SHE E T OF E NGIN EE RI NG DR A W ING I S THE P RO P RIE TAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/03/13 2009/05/11

Compal Secret Data

Deciphered Date

2

Title

Size D o cu ment Number Re v

Custom

Date: Sheet

Compal Electronics, Inc.

Auburndale(1/5)-Thermal/XDP

Calp ell a DI S L A4 743P

1

649Monday, April 13, 2009

of

0.1

http://laptop-motherboard-schematic.blogspot.com/

5

JCPU1A

DMI_CRX_PTX_N0<13>
DMI_CRX_PTX_N1<13>
DMI_CRX_PTX_N2<13>
DMI_CRX_PTX_N3<13>

DMI_CRX_PTX_P0<13>
DMI_CRX_PTX_P1<13>

D D

DMI_CRX_PTX_P2<13>
DMI_CRX_PTX_P3<13>

DMI_CTX_PRX_N0<13>
DMI_CTX_PRX_N1<13>
DMI_CTX_PRX_N2<13>
DMI_CTX_PRX_N3<13>

DMI_CTX _PRX_P0<13>
DMI_CTX _PRX_P1<13>
DMI_CTX _PRX_P2<13>
DMI_CTX _PRX_P3<13>

FDI_CTX_PRX_N0<13>
FDI_CTX_PRX_N1<13>
FDI_CTX_PRX_N2<13>
FDI_CTX_PRX_N3<13>
FDI_CTX_PRX_N4<13>
FDI_CTX_PRX_N5<13>
FDI_CTX_PRX_N6<13>
FDI_CTX_PRX_N7<13>

FDI_CTX_PRX_P0<13>
FDI_CTX_PRX_P1<13>
FDI_CTX_PRX_P2<13>
FDI_CTX_PRX_P3<13>
FDI_CTX_PRX_P4<13>
FDI_CTX_PRX_P5<13>

C C

FDI_CTX_PRX_P6<13>
FDI_CTX_PRX_P7<13>

FD I_FSY NC0<13>
FD I_FSY NC1<13>

FDI_INT<13>
FD I_LSYNC0<13>

FD I_LSYNC1<13>

B B

A24

DMI_RX#[0]

C23

DMI_RX#[1]

B22

DMI_RX#[2]

A21

DMI_RX#[3]

B24

DMI_RX[0]

D23

DMI_RX[1]

B23

DMI_RX[2]

A22

DMI_RX[3]

D24

DMI_TX#[0]

G24

DMI_TX#[1]

F23

DMI_TX#[2]

H23

DMI_TX#[3]

D25

DMI_TX[0]

F24

DMI_TX[1]

E23

DMI_TX[2]

G23

DMI_TX[3]

E22

FDI_TX#[0]

D21

FDI_TX#[1]

D19

FDI_TX#[2]

D18

FDI_TX#[3]

G21

FDI_TX#[4]

E19

FDI_TX#[5]

F21

FDI_TX#[6]

G18

FDI_TX#[7]

D22

FDI_TX[0]

C21

FDI_TX[1]

D20

FDI_TX[2]

C18

FDI_TX[3]

G22

FDI_TX[4]

E20

FDI_TX[5]

F20

FDI_TX[6]

G19

FDI_TX[7]

F17

FDI_FSYNC[0]

E17

FDI_FSYNC[1]

C17

FDI_INT

F18

FDI_LSYNC[0]

D17

FDI_LSYNC[1]

IC,AUB_CFD_rPGA,R1P0

CONN@

DMI Intel(R) FDI

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]

PCI EXPRESS -- GRAPHICS

PEG_TX#[15]

PEG_RBIAS
PEG_RX#[0]

PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]

PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]

PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]

PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

4

EXP_ICOMPI

B26
A26
B27

EXP_RBIAS

A25

PCIE_CRX_GTX_N0

K35

PCIE_CRX_GTX_N1

J34

PCIE_CRX_GTX_N2

J33

PCIE_CRX_GTX_N3

G35

PCIE_CRX_GTX_N4

G32

PCIE_CRX_GTX_N5

F34

PCIE_CRX_GTX_N6

F31

PCIE_CRX_GTX_N7

D35

PCIE_CRX_GTX_N8

E33

PCIE_CRX_GTX_N9

C33

PCIE_CRX_GTX_N10

D32

PCIE_CRX_GTX_N11

B32

PCIE_CRX_GTX_N12

C31

PCIE_CRX_GTX_N13

B28

PCIE_CRX_GTX_N14

B30

PCIE_CRX_GTX_N15

A31

PCIE_CRX_GTX_P0

J35

PCIE_CRX_GTX_P1

H34

PCIE_CRX_GTX_P2

H33

PCIE_CRX_GTX_P3

F35

PCIE_CRX_GTX_P4

G33

PCIE_CRX_GTX_P5

E34

PCIE_CRX_GTX_P6

F32

PCIE_CRX_GTX_P7

D34

PCIE_CRX_GTX_P8

F33

PCIE_CRX_GTX_P9

B33

PCIE_CRX_GTX_P10

D31

PCIE_CRX_GTX_P11

A32

PCIE_CRX_GTX_P12

C30

PCIE_CRX_GTX_P13

A28

PCIE_CRX_GTX_P14

B29

PCIE_CRX_GTX_P15

A30

PCIE_CTX_GRX_C_N0

L33

PCIE_CTX_GRX_C_N1

M35

PCIE_CTX_GRX_C_N2

M33

PCIE_CTX_GRX_C_N3

M30

PCIE_CTX_GRX_C_N4

L31

PCIE_CTX_GRX_C_N5

K32

PCIE_CTX_GRX_C_N6

M29

PCIE_CTX_GRX_C_N7

J31

PCIE_CTX_GRX_C_N8

K29

PCIE_CTX_GRX_C_N9

H30

PCIE_CTX_GRX_C_N10

H29

PCIE_CTX_GRX_C_N11

F29

PCIE_CTX_GRX_C_N12

E28

PCIE_CTX_GRX_C_N13

D29

PCIE_CTX_GRX_C_N14

D27

PCIE_CTX_GRX_C_N15

C26

PCIE_CTX_GRX_C_P0

L34

PCIE_CTX_GRX_C_P1

M34

PCIE_CTX_GRX_C_P2

M32

PCIE_CTX_GRX_C_P3

L30

PCIE_CTX_GRX_C_P4

M31

PCIE_CTX_GRX_C_P5

K31

PCIE_CTX_GRX_C_P6

M28

PCIE_CTX_GRX_C_P7

H31

PCIE_CTX_GRX_C_P8

K28

PCIE_CTX_GRX_C_P9

G30

PCIE_CTX _GRX_C_P10

G29

PCIE_CTX _GRX_C_P11

F28

PCIE_CTX _GRX_C_P12

E27

PCIE_CTX _GRX_C_P13

D28

PCIE_CTX _GRX_C_P14

C27

PCIE_CTX _GRX_C_P15

C25

R44 49.9_0402_1%

1 2

R45 750_04 02_1%

1 2

PCIE_CRX _GTX_N[0 ..15] <24>

PCIE_CRX_GTX_P[0..15] <24>

C4 0.1U_0402_16V4ZSG@

1 2

C5 0.1U_0402_16V4ZSG@

1 2

C6 0.1U_0402_16V4ZSG@

1 2

C7 0.1U_0402_16V4ZSG@

1 2

C8 0.1U_0402_16V4ZSG@

1 2

C9 0.1U_0402_16V4ZSG@

1 2

C10 0.1U_0402_16V4ZSG@

1 2

C11 0.1U_0402_16V4ZSG@

1 2

C12 0.1U_0402_16V4ZSG@

1 2

C13 0.1U_0402_16V4ZSG@

1 2

C14 0.1U_0402_16V4ZSG@

1 2

C15 0.1U_0402_16V4ZSG@

1 2

C16 0.1U_0402_16V4ZSG@

1 2

C17 0.1U_0402_16V4ZSG@

1 2

C18 0.1U_0402_16V4ZSG@

1 2

C19 0.1U_0402_16V4ZSG@

1 2

C20 0.1U_0402_16V4ZSG@

1 2

C21 0.1U_0402_16V4ZSG@

1 2

C22 0.1U_0402_16V4ZSG@

1 2

C23 0.1U_0402_16V4ZSG@

1 2

C24 0.1U_0402_16V4ZSG@

1 2

C25 0.1U_0402_16V4ZSG@

1 2

C26 0.1U_0402_16V4ZSG@

1 2

C27 0.1U_0402_16V4ZSG@

1 2

C28 0.1U_0402_16V4ZSG@

1 2

C29 0.1U_0402_16V4ZSG@

1 2

C30 0.1U_0402_16V4ZSG@

1 2

C31 0.1U_0402_16V4ZSG@

1 2

C32 0.1U_0402_16V4ZSG@

1 2

C33 0.1U_0402_16V4ZSG@

1 2

C34 0.1U_0402_16V4ZSG@

1 2

C35 0.1U_0402_16V4ZSG@

1 2

3

Lay out rule trace
length < 0.5"

PCIE_CTX_GRX_N0
PCIE_CTX_GRX_N1
PCIE_CTX_GRX_N2
PCIE_CTX_GRX_N3
PCIE_CTX_GRX_N4
PCIE_CTX_GRX_N5
PCIE_CTX_GRX_N6
PCIE_CTX_GRX_N7
PCIE_CTX_GRX_N8

PCIE_CTX_GRX_N9
PCIE_CTX_GRX_N10
PCIE_CTX_GRX_N11
PCIE_CTX_GRX_N12
PCIE_CTX_GRX_N13
PCIE_CTX_GRX_N14
PCIE_CTX_GRX_N15

PCIE_CTX_GRX_P0

PCIE_CTX_GRX_P1

PCIE_CTX_GRX_P2

PCIE_CTX_GRX_P3

PCIE_CTX_GRX_P4

PCIE_CTX_GRX_P5

PCIE_CTX_GRX_P6

PCIE_CTX_GRX_P7

PCIE_CTX_GRX_P8

PCIE_CTX_GRX_P9
PCIE_CTX _GRX_P10
PCIE_CTX _GRX_P11
PCIE_CTX _GRX_P12
PCIE_CTX _GRX_P13
PCIE_CTX _GRX_P14
PCIE_CTX _GRX_P15

Κ

+V _ DDR_CPU_REF1

PCIE_CT X_GRX_N[0 ..15] <24>

PCIE_CTX_GRX_P[0..15] <24>

R50 0_0402_5%@
R51 0_0402_5%@

1 2
1 2

2

+V _ DDR_CPU_REF0

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18

AP25
AL25
AL24
AL22
AJ33

AM30
AM28
AP31
AL32
AL30
AM31
AN29
AM32
AK32
AK31
AK28
AJ28
AN30
AN32
AJ32
AJ29
AJ30
AK30

AG9
M27

L28
J17

H17
G25
G17

E31

E30

H16

B19

A19

A20

B20

U9

T9

AC9

AB9

C1
A3

J29

J28

A34

A33

C35

B35

JCPU1E

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
SA_DIMM_VREF
SB_DIMM_VREF
RSVD11
RSVD12
RSVD13
RSVD14

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
RSVD_TP_86

RSVD15
RSVD16

RSVD17
RSVD18

RSVD19
RSVD20

RSVD21
RSVD22

RSVD_NCT F_23
RSVD_NCT F_24

RSVD26
RSVD27

RSVD_NCT F_28
RSVD_NCT F_29

RSVD_NCT F_30
RSVD_NCT F_31

RESERVED

RSVD32
RSVD33

RSVD34
RSVD35

RSVD36

RSVD_NCT F_37

RSVD38
RSVD39

RSVD_NCT F_40
RSVD_NCT F_41

RSVD_NCT F_42
RSVD_NCT F_43

RSVD45
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RSVD51
RSVD52

RSVD53
RSVD_NCT F_54
RSVD_NCT F_55
RSVD_NCT F_56
RSVD_NCT F_57

RSVD58

RSVD_TP_59
RSVD_TP_60

RSVD62

RSVD63

RSVD64

RSVD65

RSVD_TP_66
RSVD_TP_67
RSVD_TP_68
RSVD_TP_69
RSVD_TP_70
RSVD_TP_71
RSVD_TP_72
RSVD_TP_73
RSVD_TP_74
RSVD_TP_75

RSVD_TP_76
RSVD_TP_77
RSVD_TP_78
RSVD_TP_79
RSVD_TP_80
RSVD_TP_81
RSVD_TP_82
RSVD_TP_83
RSVD_TP_84
RSVD_TP_85

1

AJ13
AJ12

AH25
AK26

AL26
AR2

AJ26
AJ27

AP1
AT2

AT3
AR1

AL28
AL29
AP30
AP32
AL27
AT31
AT32
AP33
AR33
AT33
AT34
AP35
AR35
AR32

E15
F15
A2

KEY

D15
C15

R48 0_0402_5%@
R49 0_0402_5%@

1 2
1 2

AJ15
AH15

AA5
AA4
R8
AD3
AD2
AA2
AA1
R9
AG7
AE3

V4
V5
N2
AD5
AD7
W3
W2
N3
AE5
AD9

AP34

VSS

IC,AUB_CFD_rPGA,R1P0

CONN@

CFG Straps for PROCESSOR

CFG0

R52 3.01K_0402_1%@

1 2

PCI-Express Configuration Select

1: Single PEG

CFG0

A A

Not applicable for Clarksfield Processor

CFG3

0: B ifurcation enabled

R54 3.01K_0402_1%

1 2

CFG3-PCI Express Static Lane Reversal

CFG3

1: N ormal Operation
0: Lane Numbers Reversed

15 -> 0, 14 ->1, .....

5

*

CFG4

R53 3.01 K_0402_1%@

1 2

CFG4-Display Port Presence

1: Disabled; No Physical
Display Port

attached to Embedded Display Port
0: Enabled; An external

CFG4

Display Port

device is connected to the
Embedded Display Port

CFG7

R55 3.01 K_0402_1%@

Only temporary for early
CFD samples (rPGA/BGA)

Only for pre ES1 sample

1 2

http://laptop-motherboard-schematic.blogspot.com/

4

**

CFG7

WW33GPD 3.01K on CFG7 for PCIE Jitter

Κ

WW41 don't staff

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEE RING DRAWING IS TH E PROPRI ETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAI NS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS AUTHOR IZED BY COM PAL ELECTRONICS, IN C. N EITHER THIS SHEET NOR THE INFORMATION IT CONTAIN S
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRON ICS, INC.

3

2008/03/13 2009/05/11

Compa l Secret Data

Dec iphered Date

2

Title

Size Document Number Re v

Custom

Date: Sheet

Compal Electronics, Inc.

Auburndale(2/5)-DMI/PEG/FDI

Cal p el la D I S L A4743P

CRB 0.9 change to GND

of

749Monday, April 13, 2009

1

0.1

5

4

3

2

1

AR10
AT10

JCPU1D

W8

SB_CK[0]

W9

SB_CK#[0]

B5

SB_DQ[0]

A5

SB_DQ[1]

C3

SB_DQ[2]

B3

SB_DQ[3]

E4

SB_DQ[4]

A6

SB_DQ[5]

A4

SB_DQ[6]

C4

SB_DQ[7]

D1

SB_DQ[8]

D2

SB_DQ[9]

F2

SB_DQ[10]

F1

SB_DQ[11]

C2

SB_DQ[12]

F5

SB_DQ[13]

F3

SB_DQ[14]

G4

SB_DQ[15]

H6

SB_DQ[16]

G2

SB_DQ[17]

J6

SB_DQ[18]

J3

SB_DQ[19]

G1

SB_DQ[20]

G5

SB_DQ[21]

J2

SB_DQ[22]

J1

SB_DQ[23]

J5

SB_DQ[24]

K2

SB_DQ[25]

L3

SB_DQ[26]

M1

SB_DQ[27]

K5

SB_DQ[28]

K4

SB_DQ[29]

M4

SB_DQ[30]

N5

SB_DQ[31]

AF3

SB_DQ[32]

AG1

SB_DQ[33]

AJ3

SB_DQ[34]

AK1

SB_DQ[35]

AG4

SB_DQ[36]

AG3

SB_DQ[37]

AJ4

SB_DQ[38]

AH4

SB_DQ[39]

AK3

SB_DQ[40]

AK4

SB_DQ[41]

AM6

SB_DQ[42]

AN2

SB_DQ[43]

AK5

SB_DQ[44]

AK2

SB_DQ[45]

AM4

SB_DQ[46]

AM3

SB_DQ[47]

AP3

SB_DQ[48]

AN5

SB_DQ[49]

AT4

SB_DQ[50]

AN6

SB_DQ[51]

AN4

SB_DQ[52]

AN3

SB_DQ[53]

AT5

SB_DQ[54]

AT6

SB_DQ[55]

AN7

SB_DQ[56]

AP6

SB_DQ[57]

AP8

SB_DQ[58]

AT9

SB_DQ[59]

AT7

SB_DQ[60]

AP9

SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

AB1

SB_BS[0]

W5

SB_BS[1]

R7

SB_BS[2]

AC5

SB_CAS#

Y7

SB_RAS#

AC6

SB_WE#

DDR SYSTEM MEMORY - B

SB_CKE[0]

SB_CK[1]
SB_CK#[1]
SB_CKE[1]

SB_CS#[0]
SB_CS#[1]

SB_ODT[0]
SB_ODT[1]

SB_DM[0]

SB_DM[1]

SB_DM[2]

SB_DM[3]

SB_DM[4]

SB_DM[5]

SB_DM[6]

SB_DM[7]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

SB_MA[0]

SB_MA[1]

SB_MA[2]

SB_MA[3]

SB_MA[4]

SB_MA[5]

SB_MA[6]

SB_MA[7]

SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

M3

V7
V6
M2

AB8
AD6

AC7
AD1

D4
E1
H3
K1
AH1
AL2
AR4
AT8

D5
F4
J4
L4
AH2
AL4
AR5
AR8

C5
E3
H4
M5
AG2
AL5
AP5
AR7

U5
V2
T5
V3
R1
T8
R2
R6
R4
R5
AB5
P3
R3
AF7
P5
N1

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_ B _ M A 0
DDR_ B _ M A 1
DDR_ B _ M A 2
DDR_ B _ M A 3
DDR_ B _ M A 4
DDR_ B _ M A 5
DDR_ B _ M A 6
DDR_ B _ M A 7
DDR_ B _ M A 8
DDR_ B _ M A 9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

M_ CLK_DDR2 <18>
M_ CL K_DDR#2 <18>
DDR_CKE2_DIMMB <18>

M_ CLK_DDR3 <18>
M_ CL K_DDR#3 <18>
DDR_CKE3_DIMMB <18>

DDR_CS2_DIMMB# <18>
DDR_CS3_DIMMB# <18>

M_ODT2 <18>
M_ODT3 <18>

DDR _ B_ DM [0 ..7 ] <18>

DDR _ B_ DQS # [0 ..7 ] <18>

DDR_B_DQS[0..7] <18>

DDR_B_MA[0..15] <18>

JCPU1C

D D

DDR_A_D[0..63]<17>

C C

B B

DDR_A_BS0<17>
DDR_A_BS1<17>
DDR_A_BS2<17>

DDR_A_CAS#<17>
DDR_A_RAS#<17>
DDR_A_WE#<17>

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

AJ10
AL10

AK12

AK11

AM10

AR11
AL11

AT11
AP12

AM12

AN12

AM13

AT14
AT12
AL13
AR14
AP14

A10

SA_DQ[0]

C10

SA_DQ[1]

C7

SA_DQ[2]

A7

SA_DQ[3]

B10

SA_DQ[4]

D10

SA_DQ[5]

E10

SA_DQ[6]

A8

SA_DQ[7]

D8

SA_DQ[8]

F10

SA_DQ[9]

E6

SA_DQ[10]

F7

SA_DQ[11]

E9

SA_DQ[12]

B7

SA_DQ[13]

E7

SA_DQ[14]

C6

SA_DQ[15]

H10

SA_DQ[16]

G8

SA_DQ[17]

K7

SA_DQ[18]

J8

SA_DQ[19]

G7

SA_DQ[20]

G10

SA_DQ[21]

J7

SA_DQ[22]

J10

SA_DQ[23]

L7

SA_DQ[24]

M6

SA_DQ[25]

M8

SA_DQ[26]

L9

SA_DQ[27]

L6

SA_DQ[28]

K8

SA_DQ[29]

N8

SA_DQ[30]

P9

SA_DQ[31]

AH5

SA_DQ[32]

AF5

SA_DQ[33]

AK6

SA_DQ[34]

AK7

SA_DQ[35]

AF6

SA_DQ[36]

AG5

SA_DQ[37]

AJ7

SA_DQ[38]

AJ6

SA_DQ[39]
SA_DQ[40]

AJ9

SA_DQ[41]
SA_DQ[42]
SA_DQ[43]

AK8

SA_DQ[44]

AL7

SA_DQ[45]
SA_DQ[46]

AL8

SA_DQ[47]

AN8

SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]

AM9

SA_DQ[52]

AN9

SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

AC3

SA_BS[0]

AB2

SA_BS[1]

U7

SA_BS[2]

AE1

SA_CAS#

AB3

SA_RAS#

AE9

SA_WE#

DDR SYSTEM MEMORY A

SA_CK[0]

SA_CK#[0]

SA_CKE[0]

SA_CK[1]

SA_CK#[1]

SA_CKE[1]

SA_CS#[0]
SA_CS#[1]

SA_ODT[0]
SA_ODT[1]

SA_DM[0]
SA_DM[1]
SA_DM[2]
SA_DM[3]
SA_DM[4]
SA_DM[5]
SA_DM[6]
SA_DM[7]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]

SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

AA6
AA7
P7

Y6
Y5
P6

AE2
AE8

AD8
AF9

B9
D7
H7
M7
AG6
AM7
AN10
AN13

C9
F8
J9
N9
AH7
AK9
AP11
AT13

C8
F9
H9
M9
AH8
AK10
AN11
AR13

Y3
W1
AA8
AA3
V1
AA9
V8
T1
Y9
U6
AD4
T2
U3
AG8
T3
V9

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_ A _ M A 0
DDR_ A _ M A 1
DDR_ A _ M A 2
DDR_ A _ M A 3
DDR_ A _ M A 4
DDR_ A _ M A 5
DDR_ A _ M A 6
DDR_ A _ M A 7
DDR_ A _ M A 8
DDR_ A _ M A 9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

M_ CL K_DDR0 <17>
M_CLK _DDR#0 <17>
DDR_CKE0_DIMMA <17>

M_ CL K_DDR1 <17>
M_CLK _DDR#1 <17>
DDR_CKE1_DIMMA <17>

DDR_CS0_DIMMA# <17>
DDR_CS1_DIMMA# <17>

M_ODT0 <17>
M_ODT1 <17>

DDR_A_DM[0..7] <17>

DDR_A_DQS#[0..7] <17>

DDR_A_DQS[0..7] <17>

DDR_A_MA[0..15] <17>

DDR_B_D[0..63]<18>

DDR_B_BS0<18>
DDR_B_BS1<18>
DDR_B_BS2<18>

DDR_B_CAS#<18>
DDR_B_RAS#<18>
DDR_B_WE#<18>

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

IC,AUB_CFD_rPGA,R1P0

CONN@

A A

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEE RING DRAWING IS TH E PROPRI ETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAI NS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS AUTHOR IZED BY COM PAL ELECTRONICS, IN C. N EITHER THIS SHEET NOR THE INFORMATION IT CONTAIN S

5

http://laptop-motherboard-schematic.blogspot.com/

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRON ICS, INC.

3

2008/03/13 2009/05/11

Compa l Secret Data

IC,AUB_CFD_rPGA,R1P0

CONN@

Dec iphered Date

Title

Size Document Number Re v

Custom

2

Date: Sheet

Compal Electronics, Inc.

Cantiga(2/6)-DDR3 A/B CH

Cal p el la D I S L A4743P

1

0.1

of

849Monday, April 13, 2009

5

+V C C_CORE

JCPU1F

D D

C C

B B

A A

48A 15A18A

AG35

VCC1

AG34

VCC2

AG33

VCC3

AG32

VCC4

AG31

VCC5

AG30

VCC6

AG29

VCC7

AG28

VCC8

AG27

VCC9

AG26

VCC10

AF35

VCC11

AF34

VCC12

AF33

VCC13

AF32

VCC14

AF31

VCC15

AF30

VCC16

AF29

VCC17

AF28

VCC18

AF27

VCC19

AF26

VCC20

AD35

VCC21

AD34

VCC22

AD33

VCC23

AD32

VCC24

AD31

VCC25

AD30

VCC26

AD29

VCC27

AD28

VCC28

AD27

VCC29

AD26

VCC30

AC35

VCC31

AC34

VCC32

AC33

VCC33

AC32

VCC34

AC31

VCC35

AC30

VCC36

AC29

VCC37

AC28

VCC38

AC27

VCC39

AC26

VCC40

AA35

VCC41

AA34

VCC42

AA33

VCC43

AA32

VCC44

AA31

VCC45

AA30

VCC46

AA29

VCC47

AA28

VCC48

AA27

VCC49

AA26

VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

IC,AUB_CFD_rPGA,R1P0

CONN@

CPU CORE SUPPLY

5

1.1V RAIL POWER

POWER

PROC_DPR SLPVR

CPU VIDS

VSS_SENSE_VTT

SENSE LINES

VTT0_1
VTT0_2
VTT0_3
VTT0_4
VTT0_5
VTT0_6
VTT0_7
VTT0_8

VTT0_9
VTT0_10
VTT0_11
VTT0_12
VTT0_13
VTT0_14
VTT0_15
VTT0_16
VTT0_17
VTT0_18
VTT0_19
VTT0_20
VTT0_21
VTT0_22
VTT0_23
VTT0_24
VTT0_25
VTT0_26
VTT0_27
VTT0_28
VTT0_29
VTT0_30
VTT0_31
VTT0_32

VTT0_33
VTT0_34
VTT0_35
VTT0_36
VTT0_37
VTT0_38
VTT0_39
VTT0_40
VTT0_41
VTT0_42
VTT0_43
VTT0_44

PSI#

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VTT_SELECT

ISENSE

VCC_SENSE

VSS_SENSE

VTT_SENSE

AH14
AH12
AH11
AH10

1
J14
J13
H14
H12
G14
G13
G12
G11
F14
F13
F12
F11
E14
E12
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

AF10
AE10
AC10
AB10
Y10
W10
U10
T10
J12
J11
J16
J15

AN33

AK35
AK33
AK34
AL35
AL33
AM33
AM35
AM34

G15

C40

2

10U_0805_6.3V6M

1

C48

2

10U_0805_6.3V6M

1

C67

2

+VTT_43
+VTT_44

H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
H_VID6
PM_DPRSLPVR_R

H_VTTVID1 = Low, 1.1V(Clarksfield)

H_VTTVID1 = High, 1.05V(Auburndale)

AN35

VCCSENSE_R

AJ34

VSSSENSE_R

AJ35

B15

VSS_SENSE_VTT

A15

Near Processor

VCCSENSE
VSSSENSE

R61 100_0402_1%
R62 100_0402_1%

4

+VGA_CORE

+V CCP

1

C41

2

10U_0805_6.3V6M

1

C49

2

@

10U_0805_6.3V6M

1

2

22U_0805_6.3V6M

+VTT_44
+VTT_43

to power

R58 0_0402_5%

to power

R59 0_0402_5%

1 2

R60 0_0402_5%

1 2

R203 0_0402_5%

1 2
1 2

http://laptop-motherboard-schematic.blogspot.com/

1

1

2

1

2

C68

22U_0805_6.3V6M

1 2

1 2

C43

C42

2

10U_0805_6.3V6M

1

C51

C50

2

@

10U_0805_6.3V6M

+V CCP

R56 0_0603_5%

1 2

R57 0_0603_5%

1 2

H_PSI# <46>
H_V ID[0 ..6 ] <46>

to power

VTT _SELECT <44>

IMVP_IMON <46>

+VCC_CORE

4

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C52

2

1

2

VCCSENSE
VSSSENSE

10U_0805_6.3V6M

1

C61

2

22U_0805_6.3V6M

+VCCP

to power

VTT _SENSE <44>

+V CCP

1

C63

C62

2

22U_0805_6.3V6M

22U_0805_6.3V6M

H_ DP RSLPVR <46>

VCCSENSE <46>
VSSSENSE <46>

CPU

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEE RING DRAWING IS TH E PROPRI ETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAI NS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS AUTHOR IZED BY COM PAL ELECTRONICS, IN C. N EITHER THIS SHEET NOR THE INFORMATION IT CONTAIN S
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRON ICS, INC.

3

JCPU1G

AT21

22U_0805_6.3V6M

22U_0805_6.3V6M

C988

C987

1

1

2

2

22U_0805_6.3V6M

22U_0805_6.3V6M

C993

C991

1

1

@

@

2

330U_D2_2VY_R7M

C995

1

1

+

+

2

2

+V CCP

1

2

@

2

330U_D2_2VY_R7M

C996

+V CCP

1

C74

C73

2

22U_0805_6.3V6M

22U_0805_6.3V6M

3

10U_0805_6.3V6M

10U_0805_6.3V6M

C990

C989

1

1

2

2

22U_0805_6.3V6M

C994

1

2

1

1

C69

2

2

22U_0805_6.3V6M

1

1

C75

2

2

22U_0805_6.3V6M

2008/03/13 2009/05/11

VAXG1

AT19

VAXG2

AT18

VAXG3

AT16

VAXG4

AR21

VAXG5

AR19

VAXG6

AR18

VAXG7

AR16

VAXG8

AP21

VAXG9

AP19

VAXG10

AP18

VAXG11

AP16

VAXG12

AN21

VAXG13

AN19

VAXG14

AN18

VAXG15

AN16

VAXG16

AM21

VAXG17

AM19

VAXG18

AM18

VAXG19

AM16

VAXG20

AL21

VAXG21

AL19

VAXG22

AL18

VAXG23

AL16

VAXG24

AK21

VAXG25

AK19

VAXG26

AK18

VAXG27

AK16

VAXG28

AJ21

VAXG29

AJ19

VAXG30

AJ18

VAXG31

AJ16

VAXG32

AH21

VAXG33

AH19

VAXG34

AH18

VAXG35

AH16

VAXG36

J24

VTT1_45

J23

VTT1_46

H25

VTT1_47

C70

22U_0805_6.3V6M

K26

VTT1_48

J27

VTT1_49

J26

VTT1_50

J25

VTT1_51

C76

H27

VTT1_52

G28

VTT1_53

G27

VTT1_54

G26

VTT1_55

22U_0805_6.3V6M

F26

VTT1_56

E26

VTT1_57

E25

VTT1_58

IC,AUB_CFD_rPGA,R1P0

CONN@

Compa l Secret Data

Dec iphered Date

2

GRAPHICS

FDI PEG & DMI

POWER

2

SENSE

LINES

GRAPHICS VIDs

3A

0.6A

VAXG_SENSE

VSSAXG_SENSE

GFX_VID[0]
GFX_VID[1]
GFX_VID[2]
GFX_VID[3]
GFX_VID[4]
GFX_VID[5]
GFX_VID[6]

GFX_VR_EN

GFX_DPRSLPVR

GFX_IMON

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18

DDR3 - 1.5V RAILS

VTT0_59
VTT0_60
VTT0_61
VTT0_62

VTT1_63
VTT1_64
VTT1_65

1.1V1.8V

VTT1_66
VTT1_67
VTT1_68

VCCPLL1
VCCPLL2
VCCPLL3

AR22
AT22

AM22
AP22
AN22
AP23
AM23
AP24
AN24

AR25
AT25
AM24

AJ1
AF1
AE7
AE4
AC1
AB7
AB4
Y1
W7
W4
U1
T7
T4
P1
N7
N4
L1
H1

P10
N10
L10
K10

J22
J20
J18
H21
H20
H19

L26
L27
M26

1

VCC_A X G_SENSE
VSS_AXG_SENSE

GFXVR_VID_0
GFXVR_VID_1
GFXVR_VID_2
GFXVR_VID_3
GFXVR_VID_4
GFXVR_VID_5
GFXVR_VID_6

GFXVR_EN
GFXVR_DPRSLPVR
GFXVR_IMON

R128

@

1K_0402_5%

1

C56

2

1U_0603_10V4Z

1

+

C64

2

330U_D2_2VY_R7M

1

C71

2

10U_0805_6.3V6M

1

C77

2

22U_0805_6.3V6M

1

1

C79

2

2

1U_0603_10V4Z

Title

Size Document Number Re v

Custom

Cal p el la D I S L A4743P

Date: Sheet

VCC_A X G_SENSE <43>
VSS_AXG_SENSE <43>

GFXVR_VID_0 <43>
GFXVR_VID_1 <43>
GFXVR_VID_2 <43>
GFXVR_VID_3 <43>
GFXVR_VID_4 <43>
GFXVR_VID_5 <43>
GFXVR_VID_6 <43>

GFXVR_EN <43>
GFXVR_DPRSLPVR <43>
GFXVR_IMON <43>

12

1

2

1

2

1

2

1

2

C80

1U_0603_10V4Z

1

1

C57

2

1U_0603_10V4Z

1

C65

2

22U_0805_6.3V6M

+VCCP

C72

10U_0805_6.3V6M

+VCCP

C78

22U_0805_6.3V6M

1

C81

2

2.2U_0603_6.3V4Z

1

C59

C58

1U_0603_10V4Z

C66

22U_0805_6.3V6M

1

2

C60

2

2

1U_0603_10V4Z

1U_0603_10V4Z

1

C82

2

22U_0805_6.3V6M

+1.8VS

C83

4.7U_0603_6.3V6K

Compal Electronics, Inc.

Auburndale(4/5)-PWR

949Monday, April 13, 2009

1

+1.5V

of

0.1

5

4

3

2

1

JCPU1H

AT20

VSS1

AT17

VSS2

AR31

VSS3

AR28

VSS4

AR26

VSS5

AR24

VSS6

AR23

VSS7

AR20

D D

C C

B B

AR17
AR15
AR12

AP20
AP17
AP13
AP10

AN34
AN31
AN23
AN20

AN17
AM29
AM27
AM25
AM20
AM17
AM14
AM11

AL34

AL31

AL23

AL20

AL17

AL12

AK29

AK27

AK25

AK20

AK17

AJ31

AJ23

AJ20

AJ17

AJ14

AJ11

AH35

AH34

AH33

AH32

AH31

AH30

AH29

AH28

AH27

AH26

AH20

AH17

AH13

AG10

AE35

VSS8
VSS9
VSS10
VSS11

AR9

VSS12

AR6

VSS13

AR3

VSS14
VSS15
VSS16
VSS17
VSS18

AP7

VSS19

AP4

VSS20

AP2

VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33

AM8

VSS34

AM5

VSS35

AM2

VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42

AL9

VSS43

AL6

VSS44

AL3

VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56

AJ8

VSS57

AJ5

VSS58

AJ2

VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72

AH9

VSS73

AH6

VSS74

AH3

VSS75
VSS76

AF8

VSS77

AF4

VSS78

AF2

VSS79
VSS80

VSS

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE6
AD10
AC8
AC4
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
AB6
AA10
Y8
Y4
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
W6
V10
U8
U4
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
T6
R10
P8
P4
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
N6
M10
L35
L32
L29
L8
L5
L2
K34
K33
K30

JCPU1I

K27

VSS161

K9

VSS162

K6

VSS163

K3

VSS164

J32

VSS165

J30

VSS166

J21

VSS167

J19

VSS168

H35

VSS169

H32

VSS170

H28

VSS171

H26

VSS172

H24

VSS173

H22

VSS174

H18

VSS175

H15

VSS176

H13

VSS177

H11

VSS178

H8

VSS179

H5

VSS180

H2

VSS181

G34

VSS182

G31

VSS183

G20

VSS184

G9

VSS185

G6

VSS186

G3

VSS187

F30

VSS188

F27

VSS189

F25

VSS190

F22

VSS191

F19

VSS192

F16

VSS193

E35

VSS194

E32

VSS195

E29

VSS196

E24

VSS197

E21

VSS198

E18

VSS199

E13

VSS200

E11

VSS201

E8

VSS202

E5

VSS203

E2

VSS204

D33

VSS205

D30

VSS206

D26

VSS207

D9

VSS208

D6

VSS209

D3

VSS210

C34

VSS211

C32

VSS212

C29

VSS213

C28

VSS214

C24

VSS215

C22

VSS216

C20

VSS217

C19

VSS218

C16

VSS219

B31

VSS220

B25

VSS221

B21

VSS222

B18

VSS223

B17

VSS224

B13

VSS225

B11

VSS226

B8

VSS227

B6

VSS228

B4

VSS229

A29

VSS230

A27

VSS231

A23

VSS232

A9

VSS233

VSS

NCTF

VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7

AT35
AT1
AR34
B34
B2
B1
A35

+V C C_CORE

@

VSS_NCTF1_R
VSS_NCTF2_R

VSS_NCTF3_R
VSS_NCTF4_R
VSS_NCTF5_R

VSS_NCTF6_R
VSS_NCTF7_R

1

1

C84

2

1

2

1

1

C982

2

2

47P_0402_50V8J

C85

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C97

C96

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C114

C115

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C86

2

10U_0805_6.3V6M

1

C98

2

10U_0805_6.3V6M

1

C116

2

10U_0805_6.3V6M

CPU CORE

1

1

C87

2

1

2

1

2

C88

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C100

C99

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C117

C118

2

10U_0805_6.3V6M

22U_0805_6.3V6M

1

1

1

C89

2

1

2

1

2

C90

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C101

C102

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C119

C120

2

22U_0805_6.3V6M

22U_0805_6.3V6M

1

C91

2

1

2

1

2

C92

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

C104

C103

2

10U_0805_6.3V6M

10U_0805_6.3V6M

1

+

C121

C108

2

22U_0805_6.3V6M

470U_D2_2VM_ R4.5M

1

1

C93

2

10U_0805_6.3V6M

1

C105

2

10U_0805_6.3V6M

1

+

C109

2

470U_D2_2VM_ R4.5M

1

C94

2

10U_0805_6.3V6M

1

C106

2

10U_0805_6.3V6M

1

+

C110

2

470U_D2_2VM_ R4.5M

Inside cavity

C95

2

10U_0805_6.3V6M

1

bet ween

C107

Inductor and

2

10U_0805_6.3V6M

soc ket

1

+

C111

2

470U_D2_2VM_ R4.5M

470uF 4.5mohm

IC,AUB_CFD_rPGA,R1P0

CONN@

A A

5

http://laptop-motherboard-schematic.blogspot.com/

4

IC,AUB_CFD_rPGA,R1P0

CONN@

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEE RING DRAWING IS TH E PROPRI ETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAI NS CONFIDENTIAL
AND TRADE SECR ET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS AUTHOR IZED BY COM PAL ELECTRONICS, IN C. N EITHER THIS SHEET NOR THE INFORMATION IT CONTAIN S
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRON ICS, INC.

3

2008/03/13 2009/05/11

Compa l Secret Data

Dec iphered Date

2

Title

Size Document Number Re v

Custom

Date: Sheet

Compal Electronics, Inc.

Auburndale(5/5)-GND/Bypass

Cal p el la D I S L A4743P

10 49Monday, April 13, 2009

1

of

0.1

5

ICH _ RTCX1

Y1

32.768KHZ_12.5PF_Q13MC14610002

1

2

ICH _ RTCX2

C123

18P_0402_50V8J

SPI _ SB_CS#

SPI_SO_R

R63 10M_0402_5%

1 2

1

1

D D

2

C C

+3VS

R656 10K_0402_5%

R657 10K_0402_5%

B B

C122

18P_0402_50V8J

1 2

1 2

OSC4OSC

NC3NC

2

+RTCVCC

R65 1M_0402_5%

R66 330K_0402_5%

+RTCVCC

R69 20K_0402_1%
R70 20K_0402_1%

HDA_BITCLK_MDC<33>
HDA_BITCLK_CODEC<33>
HDA_SYNC_MDC<33>
HDA_SYNC_CODEC<33>

HDA_RST#_MDC<33>
HDA _ R ST # _CODEC<33,37>

HDA_SDOUT_MDC<33>
HDA_SDOUT_CODEC<33>

1U_0603_10V4Z

1 2
1 2

1U_0603_10V4Z

HDA_SDIN0<33>
HDA_SDIN1<33>

SPI _ CL K_ PCH<36>
SPI _ SB_CS#<36>

SPI_SI<36>

SPI_SO_R<36>

1 2

1 2

1

C124

2

1

C125

2

R72 33_0402_5%

1 2

R73 33_0402_5%

1 2

R74 33_0402_5%

1 2

R75 33_0402_5%

1 2

1 2

R77 33_0402_5%

1 2

R78 33_0402_5%

R81 33_0402_5%

1 2

R82 33_0402_5%

1 2

R670 100K_0402_5%@

1 2

SPI _ CL K_PCH
SPI _ SB_CS#

SPI_SI
SPI_SO_R

SM_ IN T R UDER#

PCH_INTVRMEN

INTVRMEN
HIn

Κ

LIn

Κ

12

CLRP1

SHORT PADS

12

CLRP2

SHORT PADS

SB_ SPKR<33>

R654 15_0402_5%

1 2

R655 15_0402_5%

1 2

4

tegrated VRM enable
tegrated VRM disable

ICH _ RTCX1
ICH _ RTCX2

ICH_RTCRST#
ICH_SRTCRST#
SM_ IN T R UDER#
PCH_INTVRMEN

HDA_BIT_CLK
H DA_SYNC
SB_ SPKR
HDA_RST#

HDA_SDIN0
HDA_SDIN1

HDA_SDOUT

HDA_DOCK_EN#

PCH_JTAG_TCK
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH _J TAG_RST#

B13
D13

C14
D17
A16
A14

A30
D29

P1

C30

G30

F30

E32

F32

B29

H32

J30

T16PAD

M3
K3
K1

J2
J4

BA2
AV3
AY3

AY1
AV1

*

U1A

RTCX1
RTCX2

RTCRST#
SRTCRST#
INTRUDER#
INTV RME N

HDA_BCLK
HDA_SYNC
SPKR
HDA_RS T#

HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3

HDA_SDO

HDA_DOCK_ EN# / GPIO33
HDA_DOCK_RST# / GPIO13

JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
TRST#

SPI_CLK
SPI_CS0#
SPI_CS1#

SPI_MOSI
SPI_MISO

IBEXPEAK-M_FCBGA10 71

+3VS

R64 10K_0402_5%

1 2

R67 1K_0402_5%@

1 2

LOW=Default
HIGH=No Reboot

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

FWH4 / LFRAME#

LDRQ0#

LDRQ1# / GPIO23

RTCIHDA

LPC

SERIRQ

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

SATA4RXN
SATA4RXP
SATA4TXN

SATA

SATA4TXP
SATA5RXN

SATA5RXP
SATA5TXN
SATA5TXP

SATAICOMPO

SATAICOMPI

SATALED#

SATA0GP / GPIO21
SATA1GP / GPIO19

SPI JTAG

3

SIRQ

SB_ SPKR

*

D33
B33
C32
A32

C34

LDRQ0#

A34

LDRQ1#

F34

SIRQ

AB9

AK7
AK6

SATA_TXN0_C

AK11

SATA_TXP0_C

AK9

AH6
AH5

SATA_TXN4_C

AH9

SATA_TXP4_C

AH8
AF11

AF9
AF7
AF6

AH3
AH1
AF3
AF1

AD9
AD8

SATA_TXN2_C

AD6

SATA_TXP2_C

AD5
AD3

AD1
AB3
AB1

AF16

R89 37.4_0402_1%

1 2

AF15

R91 10K_0402_1%

1 2

T3

GPIO21

Y9

HDDHALT_LED#

V1

LPC_AD0 <31,36,37>
LPC_AD1 <31,36,37>
LPC_AD2 <31,36,37>
LPC_AD3 <31,36,37>

LPC _F RAME# <31,36 ,3 7>

T13 P A D
T14 P A D

SIRQ <37>

C126 0.01U_0402_50V7K

1 2

C127 0.01U_0402_50V7K

1 2

C130 0.01U_0402_50V7K

1 2

C131 0.01U_0402_50V7K

1 2

C128 0.01U_0402_50V7K

1 2

C129 0.01U_0402_50V7K

1 2

+1.05VS

+3VS

SATA_LED# <38>

HDDHALT_LED# <38>

SATA_RXN0_C
SATA_RXP0_C
SATA_TXN0

SATA_TXP0

SATA_RXN4_C
SATA_RXP4_C
SATA_TXN4

SATA_TXP4

SATA_RXN2_C
SATA_RXP2_C
SATA_TXN2

SATA_TXP2

2

SATA_RXN0_C <30>
SATA_RXP0_C <30>

SATA_TXN0 <30>
SATA_TXP0 <30 >

SATA_RXN4_C <30>
SATA_RXP4_C <30>

SATA_TXN4 <30>
SATA_TXP4 <30 >

SATA_RXN2_C <35>
SATA_RXP2_C <35>

SATA_TXN2 <35>
SATA_TXP2 <35 >

HDD

ODD

E SATA

12

R86

@

200_0402_5%

12

R684

@

100_0402_1%

1

+3VALW+3VALW +3VALW +3VALW

12

R84

@

200_0402_5%

PCH_JTAG_TMS P C H_ J TAG_RST#PCH_JTAG_TDO PCH_J TAG_TDI

12

R683

@

100_0402_1%

R85
20K_0402_5%

1 2

R685
10K_0402_1%

1 2

@

1 2
12

@

R87
20K_0402_5%

R88

10K_0402_5%

HDA_SDO

HDA_SYNC

This signal has a weak internal pull down.

H=>On Die PLL is supplied by 1.5V
L=>On Die PLL is supplied by 1.8V

*

HDA_DOCK_EN#

ME debug mode , this signal has a weak internal PU

H=>security measures defined in the Flash

*

Descriptor will be in effect (default)

L=>Flash Descriptor Security will be overridden

A A

5

SPI_MOSI

This signal has a weak internal pull down.

Dis able iTPM=No Stuff

*

Enable iTPM=Stuff

iTPM ENABLE/DISABLE

+3VS

R68 1K_0402_5%@

1 2

SPI_SI

4

This signal has a weak internal pull down.
This signal can't PU

Dis able iTPM=No Stuff

*

Enable iTPM=Stuff

W=20milsW= 20mils

1

C132

2.2U_0603_6.3V4Z

2

Place near IBEX-M

+3VS

GPIO21

HDDHALT_LED#

R92 10K_0402_5%
R93 10K_0402_5%

12
12

Security Classification

THIS SHE E T OF E NGIN EE RI NG D RA W ING I S THE P RO P RIE TAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

D3

1

DAN202U_SC70

Issued Date

2

R94 1K_0402_5%

3

1 2

BATT1

@

BATT1.1+3VL+RTCVCC

CR2032 RTC BATTERY

JBATT1

1

W=20mils

2008/03/13 2009/05/11

1

2

2

3

GND

4

GND

ACES_85205-02001

CONN@

Com p a l S ecret Data

Deciphered Date

PCH _JTAG_TDO

PCH _JTAG_TMS

PCH _JTAG_TDI

PCH _JTAG_TCK

PCH _JTAG_RST#

2

1 2

R90 51_0402_5%

RefDesP CH Pin

R86

R684

R84

R683

R685

R90

R87

R88

PCH_JTAG_TCK

PCH JTAG Enable PCH JTAG Disable

ES1 ES1ES2 ES2

No Install

200ohm

200ohm

100ohm

200ohm

No Install

No Install

100ohm 100ohm

200ohm

200ohm

100ohm 100ohm

51ohm 51ohm 51ohm

20Kohm 20Kohm

10Kohm

10Kohm

Title

Size Do c u ment Numbe r R e v

Custom

Date: Sheet

Compal Electronics, Inc.

IBEX-M(1/6)- HDA/ JTAG/S ATA

Calp ell a DI S L A4 743P

No Install

No Install

No Install

20Kohm

10Kohm

No Install

1

No Install

No Install

No Install

No Install

No InstallR85

No Install

51ohm

No Install

No InstallNo Install

11 49Monday, April 13, 2009

of

0.1

http://laptop-motherboard-schematic.blogspot.com/

5

D D

PCIE_RXN1<31>

WWAN

WLAN

LAN

New Card

C C

OK

OK

OK

B B

OK

A A

+3 VALW

+3VS

+3VS

+3 VALW

WWAN

WLAN

LAN

EXP

PCI E_RXP1<31>
PCIE_TXN1<31>
PCIE_TXP1<31>

PCIE_RXN2<31>
PCI E_RXP2<31>
PCIE_TXN2<31>
PCIE_TXP2<31>

PCIE_RXN3<32>
PCI E_RXP3<32>
PCIE_TXN3<32>
PCIE_TXP3<32>

PCIE_RXN4<31>
PCI E_RXP4<31>
PCIE_TXN4<31>
PCIE_TXP4<31>

R405 10K_0402_5%

1 2

R411 10K_0402_5%

1 2

R677 10K_0402_5%

1 2

R415 10K_0402_5%

1 2

CLK_PCIE_WWAN#<31>
CLK_PCIE_WWAN<31>

CLKREQ_WW AN#<31>

CLK_PCIE_WLAN#<31>
CLK_PCIE_WLAN<31>

CLKREQ_WLAN#<31>

CLK_PCIE_LAN#<32>
CLK_PCIE_LAN<32>

CLKREQ_LAN#<32>

CL K _PC IE_EXP#<31>
CL K _ PC IE_ EXP<31>

CL K REQ _EXP#<31>

C133 0.1U_0402_16V4Z
C134 0.1U_0402_16V4Z

C135 0.1U_0402_16V4Z
C136 0.1U_0402_16V4Z

C137 0.1U_0402_16V4Z
C138 0.1U_0402_16V4Z

C139 0.1U_0402_16V4Z
C140 0.1U_0402_16V4Z

CLKREQ_WW AN#_R

CLKREQ_ WLAN#

CLKREQ_LAN#

CL K R EQ_EXP#_ R

R107 0_0402_5%

1 2

R108 0_0402_5%

1 2

R80 100_0402_5%

1 2

R109 0_0402_5%

1 2

R110 0_0402_5%

1 2

R111 0_0402_5%

1 2

R112 0_0402_5%

1 2

R114 0_0402_5%

1 2

R115 0_0402_5%

1 2

R83 100_0402_5%

1 2

R756 10K_0402_5%

+3VALW

+3VALW

+3VALW

1 2

R757 10K_0402_5%

1 2

R606 10K_0402_5%

1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

PCIE_RXN1
PCI E_RXP1
PCI E_C_TXN1
PCIE_C_TXP1

PCIE_RXN2
PCI E_RXP2
PCI E_C_TXN2
PCIE_C_TXP2

PCIE_RXN3
PCI E_RXP3
GLA N_C_TXN
GL AN_C_TXP

PCIE_RXN4
PCI E_RXP4
PCI E_C_TXN4
PCIE_C_TXP4

CLK_PCIE_W WAN#_R
CLK_PCIE_W WAN_R

CLKREQ_WW AN#_R

CLK_PCIE _WLAN#_R
CLK_PCIE _WLAN_R

CLK_PC IE_LAN#_R
CLK_PC IE_LAN_R

CL K _ PCIE_EXP# _R
CL K _ PCIE_EXP_ R

CL K R EQ_EXP#_ R

PCI ECL KREQ4 #

PCI ECL KREQ5 #

PEG _ B_CL KRQ #

4

U1B

BG30

PERN1

BJ30

PERP1

BF29

PETN1

BH29

PETP1

AW30

PERN2

BA30

PERP2

BC30

PETN2

BD30

PETP2

AU30

PERN3

AT30

PERP3

AU32

PETN3

AV32

PETP3

BA32

PERN4

BB32

PERP4

BD32

PETN4

BE32

PETP4

BF33

PERN5

BH33

PERP5

BG32

PETN5

BJ32

PETP5

BA34

PERN6

AW34

PERP6

BC34

PETN6

BD34

PETP6

AT34

PERN7

AU34

PERP7

AU36

PETN7

AV36

PETP7

BG34

PERN8

BJ34

PERP8

BG36

PETN8

BJ36

PETP8

AK48

CLKOUT_PCIE0N

AK47

CLKOUT_PCIE0P

P9

PCIECLKRQ0# / GPIO73

AM43

CLKOUT_PCIE1N

AM45

CLKOUT_PCIE1P

U4

PCIECLKRQ1# / GPIO18

AM47

CLKOUT_PCIE2N

AM48

CLKOUT_PCIE2P

N4

PCIECLKRQ2# / GPIO20

AH42

CLKOUT_PCIE3N

AH41

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

AM51

T57PAD
T58PAD

T59PAD
T60PAD

T61PAD
T62PAD

CLKOUT_PCIE4N

AM53

CLKOUT_PCIE4P

M9

PCIECLKRQ4# / GPIO26

AJ50

CLKOUT_PCIE5N

AJ52

CLKOUT_PCIE5P

H6

PCIECLKRQ5# / GPIO44

AK53

CLKOUT_PEG_B_N

AK51

CLKOUT_PEG_B_P

P13

PEG_B_CLKRQ# / GPIO56

IBE X PEAK- M_FCBG A10 71

PCI-E*

SMBALERT # / GPIO11

SMBCLK

SMBDATA

SML0ALERT# / GPIO60

SML0CLK

SML0DATA

SML1ALERT# / GPIO74

SMBus

SML1CLK / GPIO58

SML1DATA / GPIO75

CL_CLK1

Link

Controller

PEG

CLKOUT _DP_ N / CLKOUT_BCLK1_N
CLKOUT _DP_ P / CLKOUT_BCL K1_ P

From CLK BUFFER

CLKIN _SATA_N / CKSSCD_N
CLKIN _SATA_P / CKSSCD_P

Clock Flex

CL_DATA1

CL_RST1#

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

CLKOUT_DMI_N
CLKOUT_DMI_P

CLKIN_DMI_N
CLKIN_DMI_P

CLKIN_BCLK_N
CLKIN_BCLK_P

CLKIN_DOT_96N
CLKIN_DOT_96P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

CLKOUT FL EX0 / GPIO64

CLKOUT FL EX1 / GPIO65

CLKOUT FL EX2 / GPIO66

CLKOUT FL EX3 / GPIO67

3

EC_LID_OUT#
SMBCLK
SMBDATA
SML0CLK
SML0DATA
SM L0 ALER T#
SM L1 ALER T#
SML1CLK
SML1DATA

EC_LID_OUT#

B9

SMBCLK

H14

SMBDATA

C8

SM L0 ALER T#

J14

SML0CLK

C6

SML0DATA

G8

SM L1 ALER T#

M14

SML1CLK

E10

SML1DATA

G12

T13
T11
T9

PEG _C LKREQ#

H1

L_ C L K_PCI E_VG A#

AD43

L_ C L K_PCI E_VG A

AD45
AN4

AN2

CLK_DP#

AT1

CLK_DP

AT3

AW24
BA24

AP3
AP1

F18
E18

AH13
AH12

P41

J42

XTAL25_IN

AH51

XTAL25_OUT

AH53

R116 90.9_0402_1%

AF38

T45

P43

T42

N50

1 2

R95 10K_0402_5%

1 2

R96 2.2K_0402_5%

1 2

R97 2.2K_0402_5%

1 2

R98 2.2K_0402_5%

1 2

R99 2.2K_0402_5%

1 2

R100 10K_0402_5%

1 2

R101 10K_0402_5%

1 2

R103 2.2K_0402_5%

1 2

R104 2.2K_0402_5%

1 2

EC_L ID_OUT# <37>

SMBCLK <31>
SMBDATA <31>

R215
R231

0_0402_5%
0_0402_5%

DTS , read from EC

R102 10K_0402_5%

1 2

R604 0_0402_5%

1 2

R605 0_0402_5%

1 2

CLK_EXP# <6>
CLK_EXP <6>

T71 P A D
T72 P A D

CLK_DMI# <19>
CLK_DMI <19>

CLK_BUF_BCLK# <19>
CLK_BUF_BCLK <19>

CLK_ BUF_DOT96# <19>
CLK_BUF_DOT96 <19>

CLK_BUF_CKSSCD# <19>
CL K _ B U F_ C KSSCD <19>

CLK_ 14M_PCH <19>

CLK_PCI_FB <14>

+3VALW

WLAN WWAN New Ε

ΕΕ

ΕΕ

For Intel LAN only

SMB _ EC _CK2 <37>
SMB _ EC _DA2 <37>

PEG _CLKR EQ# <14>

OK

OK

OK

OK

OK

OK

OK

+1.05VS

Ε card

ΕΕ

CLK_ PCIE_VGA# <24>

CLK_ PCIE_VGA <24>

PCH

2

+3VS

5

Q1B

3

2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6

4

+3VS

5

Q4B

3

2N7002DW-7-F_SOT363-6

4

OK

XTAL25_IN

XTAL25_OUT

+3VS

2.2K_0402_5%

2

Q1A

6 1

2N7002DW-7-F_SOT363-6

+3VS

2.2K_0402_5%

2

Q4A

6 1

+3VS

R105

R106

2.2K_0402_5%

SMB_DATA_S3SMBDATA

SMB _CLK_S3SMBCLK

+3VS

R681

R682

2.2K_0402_5%

SMB_E C_DA2_RS M B _ EC_DA2

SMB_E C_CK2_RS M B _ EC_CK2

R113 1M_0402_5%

1 2

Y2

1 2

25MHZ_20P_1BG25000CK1A

1

C141

2

18P_0402_50V8J

1

SMB_DATA_S3 <17,18,19,30>

XDP SO DIM MΕ

ΕΕ

ΕΕ

SMB_CLK_S3 <17,18,19,30>

SMB_E C_DA2_R <24>

Nvidisa thermall sensor

SMB_E C_CK2_R <24>

1

C142

2

18P_0402_50V8J

ΕClock genΕΕΕΕG sensor

ΕΕ

Security Classification

Issued Date

THIS SHE E T OF E NGIN EE RI NG D RA W ING I S THE P RO P RIE TAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/03/13 2009/05/11

Com p a l S ecret Data

Deciphered Date

2

Title

Size Do c u ment Numbe r R e v

Custom

Date: Sheet

Compal Electronics, Inc.

IBEX-M(2/6)- PCI-E/S MBUS/CLK

Calp ell a DI S L A4 743P

1

12 49Monday, April 13, 2009

of

0.1

http://laptop-motherboard-schematic.blogspot.com/

5

U1C

DMI_ CTX_PR X_N0<7>
DMI_ CTX_PR X_N1<7>
DMI_ CTX_PR X_N2<7>
DMI_ CTX_PR X_N3<7>

DMI_ CTX_PR X_P0<7>
DMI_ CTX_PR X_P1<7>
DMI_ CTX_PR X_P2<7>

D D

Che cklist0.8 MEPWROK
can be connect to
PWROK if iAMT disable

XDP _ DBRESET#<6>

PM_PWROK<3 7>

M_PWROK<37>

C C

PM_DRAM_PWRGD<6>

R_EC_RSMRST#<42>

EC_RSMRST#<37>

PM_PW RBTN#_R<6>

B B

DMI_ CTX_PR X_P3<7>

DMI_CRX_PTX_N0<7>
DMI_CRX_PTX_N1<7>
DMI_CRX_PTX_N2<7>
DMI_CRX_PTX_N3<7>

DMI_CRX_PTX_P0<7>
DMI_CRX_PTX_P1<7>
DMI_CRX_PTX_P2<7>
DMI_CRX_PTX_P3<7>

+1.05VS

R118 49.9_0402_1%

1 2

4mil width and place
within 500mil of the PCH

Κ

R119 0_0402_5%

R365 0_0402_5%

VGATE<19,46>

R120 10K_0402_5%@

R124 10K_0402_5%

PWRBTN_OUT#<37>

PM_PWROK PM_R SMRST#

CH751H-40PT_SOD323-2

SYS_RST#
PM_ CL K RUN#

LO W _BAT#
PM_RI#
IC H _ P CI E _WAKE#
EC_ACIN

1 2

R373 0_0402_5%@

1 2

12

R121 0_0402_5%
R379 0_0402_5%@

R123

1 2

12

+3 VALW

EC_ACIN<37>

D37

2 1

R133 10K_0402_5%@
R129 8.2K_0402_5%

R134 8.2K_0402_5%
R136 10K_0402_5%
R137 1K_0402_5%
R138 8.2K_0402_5%

DM I_ CTX_PR X_N0
DM I_ CTX_PR X_N1
DM I_ CTX_PR X_N2
DM I_ CTX_PR X_N3

DM I_ CTX_PR X_P0
DM I_ CTX_PR X_P1
DM I_ CTX_PR X_P2
DM I_ CTX_PR X_P3

DMI_ CRX_PTX_N0
DMI_ CRX_PTX_N1
DMI_ CRX_PTX_N2
DMI_ CRX_PTX_N3

DMI_ CRX_PTX_P0
DMI_ CRX_PTX_P1
DMI_ CRX_PTX_P2
DMI_ CRX_PTX_P3

DMI_IRCOMP

1 2

1 2
1 2

R122 10K_0402_5%

1 2

PM_DRAM_PWRGD

100_0402_5%

R151 10K_0402_5%

1 2

R125 0_0402_5%

1 2

1 2
1 2

1 2
1 2
1 2

12

SYS_RST#

PM_RSMRST#

EC_ACIN

LO W _BAT#

PM_RI#

+3VS

+3VALW

BC24

DMI0RXN

BJ22

DMI1RXN

AW20

DMI2RXN

BJ20

DMI3RXN

BD24

DMI0RXP

BG22

DMI1RXP

BA20

DMI2RXP

BG20

DMI3RXP

BE22

DMI0TXN

BF21

DMI1TXN

BD20

DMI2TXN

BE18

DMI3TXN

BD22

DMI0TXP

BH21

DMI1TXP

BC20

DMI2TXP

BD18

DMI3TXP

BH25

DMI_ZCOMP

BF25

DMI_IRC OMP

T6

SYS_RESET#

M6

SYS_PWROK

B17

PWROK

K5

MEPWROK

A10

LAN_RST#

D9

DRAMPWROK

C16

RSMRST#

M1

SUS_PWR_DN_ACK / GPIO30

P5

PWRBTN#

P7

ACPRESENT / GPIO31

A6

BATLOW# / GP IO72

F14

RI#

IBEXPEAK-M_FCBGA10 71

Check PM_SLP_LAN#

DMI

FDI

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

System Power Management

SLP_LAN# / GPIO 29

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

FD I_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1

WAKE#

SLP_S4#

SLP_S3#

SLP_M#

TP23

PMSYNCH

4

BA18
BH17
BD16
BJ16
BA16
BE14
BA14
BC12

BB18
BF17
BC16
BG16
AW16
BD14
BB14
BD12

BJ14
BF13
BH13
BJ12
BG14

J12

Y1

P8

F3

E4

H7

P12

K8

N2

BJ10

F6

FDI _ CTX_PRX_ N0
FDI _ CTX_PRX_ N1
FDI _ CTX_PRX_ N2
FDI _ CTX_PRX_ N3
FDI _ CTX_PRX_ N4
FDI _ CTX_PRX_ N5
FDI _ CTX_PRX_ N6
FDI _ CTX_PRX_ N7

FDI _CTX_PRX_ P0
FDI _CTX_PRX_ P1
FDI _CTX_PRX_ P2
FDI _CTX_PRX_ P3
FDI _CTX_PRX_ P4
FDI _CTX_PRX_ P5
FDI _CTX_PRX_ P6
FDI _CTX_PRX_ P7

IC H _ P CI E _WAKE#

PM_ CL K RUN#

PM_SUS_STAT#

SUS_CLK

Can be left NC when IAMT is
not support on the platfrom

If not using integrated
LAN,signal may be left as NC.

FDI _ CTX_PRX_N0 <7>
FDI _ CTX_PRX_N1 <7>
FDI _ CTX_PRX_N2 <7>
FDI _ CTX_PRX_N3 <7>
FDI _ CTX_PRX_N4 <7>
FDI _ CTX_PRX_N5 <7>
FDI _ CTX_PRX_N6 <7>
FDI _ CTX_PRX_N7 <7>

FDI _ CTX_PR X_P0 <7>
FDI _ CTX_PR X_P1 <7>
FDI _ CTX_PR X_P2 <7>
FDI _ CTX_PR X_P3 <7>
FDI _ CTX_PR X_P4 <7>
FDI _ CTX_PR X_P5 <7>
FDI _ CTX_PR X_P6 <7>
FDI _ CTX_PR X_P7 <7>

FDI_INT <7>
FDI_FSYNC0 <7>
FDI_FSYNC1 <7>
FDI_LSYNC0 <7>
FDI_LSYNC1 <7>

IC H _ P CI E _W AKE# <3 1, 32 >

T17

T18

SLP_ S5 # <3 7>

SLP_ S4 # <3 7>

SLP_ S3 # <3 7>

H_PM_SYNC <6>

3

R770

IG P U _BKLT_EN

1 2

100K_0402_5%

IG P U _ BKLT_EN<22>

I_ENAVDD<21>

DPST_PWM<22>

+3VS

Close PCH and mini space 20mil

I_C R T_ DDC_CLK<20>
I_CRT_DDC_DATA<20>

I_CRT_HSYNC<2 2>
I_CRT_VSYNC<22>

CRB0.9 change to 0 ohm

EDID_CLK and EDID_DATA single
end and keep 30 mil with other
LVDS signal avoid noise

IG P U _BKLT_EN
I_ENAVDD

DPST_PWM

I_ED ID_CLK<22>
I_EDID_DATA<22>

I_L V DS_ACLK-<22>
I_L V DS_ACLK+<22>

I_LVDS_A0-<22>
I_LVDS_A1-<22>
I_LVDS_A2-<22>

I_L VDS_A0+<2 2>
I_L VDS_A1+<2 2>
I_L VDS_A2+<2 2>

I_BLUE<22>
I_GREEN<22>
I_RED<22>

1 2

R771 10K_0402_5%

1 2

R772 10K_0402_5%

R773 2.37K_0402_1%

1 2

T69PAD

I_BLUE
I_ G R EEN
I_RED

0_0402_5%

HSYNC

R774

1 2
1 2

VSYNC

R775 0_0402_5%

12

R126

CRB0.9 change to 1K_0402_0.5%

I_BLUE
I_ G R EEN
I_RED

Place the 3 resistors close to IBEX

1 2

R776 150_0402_1%

1 2

R777 150_0402_1%

1 2

R778 150_0402_1%

T48

T47

Y48

AB48

Y45

AB46

V48

AP39
AP41

AT43
AT42

AV53
AV51

BB47
BA52
AY48
AV47

BB48
BA50
AY49
AV48

AP48
AP47

AY53
AT49
AU52
AT53

AY51
AT48
AU50
AT51

AA52
AB53

AD53

V51
V53

Y53
Y51

AD48

AB51

1K_0402_0.5%

U1D

L_BKLTEN
L_VDD_EN

L_BKLTCTL
L_DDC_CLK

L_DDC_DATA
L_CTRL_CLK

L_CTRL_DATA
LVD_IBG

LVD_VBG
LVD_VREFH

LVD_VREFL

LVDSA_CLK#
LVDSA_CLK

LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3

LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3

LVDSB_CLK#
LVDSB_CLK

LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3

LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

CRT_BLUE
CRT_GREEN
CRT_RED

CRT_DDC_CLK
CRT_DDC_DATA

CRT_HSYNC
CRT_VSYNC

DAC_IREF
CRT_IRTN

IBE X PEAK- M_FCBG A1071

LVDS

CRT

2

SDVO_TVCLKINN
SDVO_TVCLKINP

SDVO_STALLN
SDVO_STALLP

SDVO_INTN
SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN
DDPB_AUXP

DDPB_HPD

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN
DDPC_AUXP

DDPC_HPD

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN
DDPD_AUXP

DDPD_HPD

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

BJ46
BG46

BJ48
BG48

BF45
BH45

T51
T53

BG44
BJ44
AU38

BD42
BC42
BJ42
BG42
BB40
BA40
AW38
BA38

Y49
AB49

BE44
BD44
AV40

BE40
BD40
BF41
BH41
BD38
BC38
BB36
BA36

U50
U52

BC46
BD46
AT38

BJ40
BG40
BJ38
BG38
BF37
BH37
BE36
BD36

HDMI D_ CT RLCLK
HDMID_CTRLDATA

TMDS_B_HPD#

1

HDMI D_ CTRLCLK <23>
HDMI D_ CTRLDATA <23>

TMDS_ B_HPD# <23>
TMDSD_DATA0# <23>

TMDSD_DATA0 <23>
TMDSD_DATA1# <23>
TMDSD_DATA1 <23>
TMDSD_DATA2# <23>
TMDSD_DATA2 <23>
TMDS D_CLK# <23>
TMDSD_CLK <23>

SDVO

Display Port B

Display Port C Display Port D

A A

Security Classification

Issued Date

THIS SHE E T OF E NGIN EE RI NG D RA W ING I S THE P RO P RIE TAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

http://laptop-motherboard-schematic.blogspot.com/

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/03/13 2009/05/11

Com p a l S ecret Data

Deciphered Date

2

Title

Size Do c u ment Numbe r R e v

Custom

Date: Sheet

Compal Electronics, Inc.

IBEX-M(3/6)- DMI/GPIO/LVDS

Calp ell a DI S L A4 743P

1

13 49Monday, April 13, 2009

of

0.1

5

PCI _D EVSEL#
PCI _ S ERR#
PCI_REQ0#
PCI_PIRQB#

PCI_REQ1#
PCI _F R AME#
PCI_TRDY#
PCI _ P IRQ H#

D D

PCI_REQ3#
PCI_PIRQF#
PCI _ P ERR#
PCI_LOCK#

PCI_PIRQA#
PCI _ P IRQ D#
PCI_ PIRQG#
PCI _ P IRQ C#

PCI_PIRQE#
PCI_STOP#
PCI_IRDY#

DG P U _ SELECT#

C C

RP3

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%
RP4

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%
RP5

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

RP6

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%
RP7

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

ACCEL_INT<30>

GNT2

Default-Internal pull up

Low=Configures DMI for ESI
compatible operation(for
servers only.Not for
mob ile/desktops)

B B

CLK_DEBUG_PORT_0<36>
CLK_DEBUG_PORT_1<31>

A A

PCI_GNT3#

R183 1K_0402_5%@

A16 swap overide Strap/Top-Block
Swap Override jumper

PCI_GNT3#

+3VS

+3VS

DG P U _ SELECT#<22>

PCI _ SE RR#<37>

0_0402_5%

PCI_RST#<36,37>

DG P U _ PW M_SELECT#

R150

12

T70 P AD

ACCEL_INT

*

PCI _PME#<37>
PLT_ RS T#<6,31,32>

R_CLK_PCI_FB
R_CLK_PCI_EC
R_ C L K_ D EBUG_PO RT_0
R_ C L K_ D EBUG_PO RT_1

CLK_PCI_FB<12>
CLK_PCI_EC<37>

1 2

Low=A16 swap
override/Top-Block
Swap Override enabled
High=Default

R158 22_0402_5%
R160 22_0402_5%
R161 22_0402_5%
R162 22_0402_5%

*

5

PCI_PIRQA#
PCI_PIRQB#
PCI _ P IRQ C#
PCI _ P IRQ D#

PCI_REQ0#
PCI_REQ1#

DG P U _ SELECT#

PCI_REQ3#
PCI_GNT0#

PCI_GNT1#
PCI_GNT3#
PCI_PIRQE#

PCI_PIRQF#
PCI_ PIRQG#
PCI _ P IRQ H#

PCI _ S ERR#
PCI _ P ERR#

PCI_IRD Y#
PCI _D EVSEL#

PCI _F R AME#
PCI_LOCK#
PCI_STOP#

PCI_TRDY#

PLT_RST#

1 2
1 2
1 2
1 2

USB_OC#0
WX M I T_O FF#
USB_OC#1
USB_OC#2

USB_OC#6
USB_OC#5
USB_OC#4
USB_OC#7

U1E

H40

AD0

N34

AD1

C44

AD2

A38

AD3

C36

AD4

J34

AD5

A40

AD6

D45

AD7

E36

AD8

H48

AD9

E40

AD10

C40

AD11

M48

AD12

M45

AD13

F53

AD14

M40

AD15

M43

AD16

J36

AD17

K48

AD18

F40

AD19

C42

AD20

K46

AD21

M51

AD22

J52

AD23

K51

AD24

L34

AD25

F42

AD26

J40

AD27

G46

AD28

F44

AD29

M47

AD30

H36

AD31

J50

C/BE0#

G42

C/BE1#

H47

C/BE2#

G34

C/BE3#

G38

PIRQA#

H51

PIRQB#

B37

PIRQC#

A44

PIRQD#

F51

REQ0#

A46

REQ1# / GPIO50

B45

REQ2# / GPIO52

M53

REQ3# / GPIO54

F48

GNT0#

K45

GNT1# / G PIO51

F36

GNT2# / G PIO53

H53

GNT3# / G PIO55

B41

PIRQE# / GPIO2

K53

PIRQF# / GPIO3

A36

PIRQG# / GPIO4

A48

PIRQH# / GPIO5

K6

PCIRST#

E44

SERR#

E50

PERR#

A42

IRDY#

H44

PAR

F46

DEVSEL#

C46

FRAME#

D49

PLOCK#

D41

STOP#

C48

TRDY#

M7

PME#

D5

PLTRST#

N52

CLKOUT_PCI0

P53

CLKOUT_PCI1

P46

CLKOUT_PCI2

P51

CLKOUT_PCI3

P48

CLKOUT_PCI4

IBE X PEAK- M_FCBG A1071

R_ C L K_ D EBUG_PO RT_0
R_ C L K_ D EBUG_PO RT_1

RP8

4 5
3 6
2 7
1 8

10K_1206_8P4R_5%

RP9

4 5
3 6
2 7
1 8

10K_1206_8P4R_5%

PCI

R_CLK_PCI_FB
R_CLK_PCI_EC

+3VALW

BU F _ PLT_ RS T#<6>

4

NV_CE #0
NV_CE #1
NV_CE #2
NV_CE #3

NV_DQS 0
NV_DQS 1

NV_DQ0 / NV_I O0
NV_DQ1 / NV_I O1
NV_DQ2 / NV_I O2
NV_DQ3 / NV_I O3
NV_DQ4 / NV_I O4
NV_DQ5 / NV_I O5
NV_DQ6 / NV_I O6
NV_DQ7 / NV_I O7
NV_DQ8 / NV_I O8

NV_DQ9 / NV_I O9
NV_DQ10 / NV_I O10
NV_DQ11 / NV_I O11

NVRAM

NV_DQ12 / NV_I O12
NV_DQ13 / NV_I O13
NV_DQ14 / NV_I O14
NV_DQ15 / NV_I O15

NV_ALE
NV_CLE

NV_RCOMP

NV_RB#

NV_WR#0_RE#
NV_WR#1_RE#

NV_WE#_CK0
NV_WE#_CK1

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P

USB

USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

USBRBIAS#

USBRBIAS

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43

OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

PCI_GNT0#
PCI_GNT1#

Boot BIOS Strap

0

0

1

R179 0_0402_5%

12

@

100K_0402_5%

4

R185

AY9
BD1
AP15
BD8

AV9
BG8

AP7
AP6
AT6
AT9
BB1
AV6
BB3
BA4
BE4
BB6
BD6
BB7
BC8
BJ8
BJ6
BG6

BD3
AY6

AU2
AV7
AY8

AY5
AV11

BF5

H18
J18
A18
C18
N20
P20
J20
L20
F20
G20
A20
C20
M22
N22
B21
D21
H22
J22
E22
F22
A22
C22
G24
H24
L24
M24
A24
C24

B25
D25

N16
J16
F16
L16
E14
G16
F12
T15

R163 1K_0402_5%@

1 2

R164 1K_0402_5%@

1 2

PCI_GNT1#PCI_GNT0#

1 2

+3VS

U2

@

4

O

GPIO8

This signal has a weak internal
pull up ,can't Pull low

GPIO15

L IntΚel ME Crypto Transport
Layer Security(TLS) chiper suite
with no confidentiality

H Int

Κ

el ME Crypto Transport
Layer Security(TLS) chiper suite
with confidentiality

*

it have weak internal PU 20K

Check list Rev0.8 section1.23.2 If not
implemented, the Braidwood interface
signals can be left as No Connect (NC).

NV_ALE
NV_CLE

GPIO27

On-Die PLL Voltage Regulator
This signal has a weak internal pull up

H On-D

Κ

ie voltage regulator enable

*

USB 20_N0
US B2 0_ P0
USB 20_N1
US B2 0_ P1
USB 20_N2
US B2 0_ P2

USB 20_N4
US B2 0_ P4
USB 20_N5
US B2 0_ P5
USB 20_N6
US B2 0_ P6
USB 20_N7
US B2 0_ P7
USB 20_N8
US B2 0_ P8
USB 20_N9
US B2 0_ P9

USBRBIAS

USB_OC#0

USB_OC#1

USB_OC#2
WX M I T_O FF#
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7

L On-DiΚe PLL Voltage Regulator disable

USB20_N0 <35>
USB2 0_ P0 <35>
USB20_N1 <35>
USB2 0_ P1 <35>
USB20_N2 <35>
USB2 0_ P2 <35>

USB20_N4 <21>
USB2 0_ P4 <21>
USB20_N5 <31>
USB2 0_ P5 <31>
USB20_N6 <35>
USB2 0_ P6 <35>
USB20_N7 <35>
USB2 0_ P7 <35>
USB20_N8 <31>
USB2 0_ P8 <31>
USB20_N9 <31>
USB2 0_ P9 <31>

R155 22.6_0402_1%

Within 500
mils

1 2

R156 0_0402_5%

12

MB
MB
MB USB/ESATA
DOCK
USB Camera
WLAN
BT
Finger print
WWAN
New Card

BT_OFF <35>

WX M I T_OFF# <31>

Intel Anti-Theft Techonlogy

NV_ALE

Boot BIOS
Location

LPC

0

1

Reserved(NAND)

0

PCI

SPI

11

5

P

IN1
IN22G

SN7 4 A HC 1 G 08DCKR_SC70- 5

3

*

PLT_RST#

1

NV_ALE

NV_CLE

3

R140 1K_0402_1%

1 2

+3VS

+3VS

DG P U _ ED IDSEL #<20>
DGPU_HPD_INT#<23>

DGP U _ H OLD_RST#<24>

R145 10K_0402_5%

1 2

DGPU_PWR_EN<23,39,45,47>

PCH_TEMP_ALERT#

High=Endabled

Low =Disable(floating)

R174 1K_0402_5%@

1 2

DMI Termination Voltage

Set to Vcc when HIGH

NV_CLE

Set to Vss when LOW

Wea k internal
PU,Do not pull low

R184 1K_0402_5%@

1 2

Security Classification

Issued Date

THIS SHE E T OF E NGIN EE RI NG D RA W ING I S THE P RO P RIE TAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

PCH_GPIO0
DG P U _ ED IDSEL#
DGPU_HPD_INT#

EC_SCI#<37>
EC_SMI#<3 7>

CR_WAKE#<32>

XMIT_OFF<31>

*

EC_SCI#
EC_SMI#
PCH_GPIO12
PCH_GPIO15
DGP U _ H O LD_RST#
DGPU_PWROK
CR_WAKE#
XMIT_OFF

Int ernal VccVRM Option

PCH_GPIO28
H_ S T P_PCI#
GPIO35
DGPU_PWR_EN
VGA _ PRSNT_L #
GPIO38
GPIO39
PCI ECL KREQ6 #
PCI ECL KREQ7 #
GPIO48
PCH_ T EMP_ALERT#
GPIO57

NV_ALE

+1.8VS

Enable Intel Anti-Theft
Technology 8.2K PU to +3VS

Κ

Disable Intel Anti-Theft

Κ

Technology floating(internal PD)

NV_CLE

DMI termination voltage.
weak internal PU, don't PD

+3VS

2008/03/13 2009/05/11

U1F

Y3

BMBUSY# / GPIO0

C38

TACH1 / GPIO1

D37

TACH2 / GPIO6

J32

TACH3 / GPIO7

F10

GPIO8

K9

LAN_PHY_PWR_CTRL / GPIO12

T7

GPIO15

AA2

SATA4GP / GPI O 16

F38

TACH0 / GPIO17

Y7

SCLOCK / GPIO22

H10

GPIO24

AB12

GPIO27

V13

GPIO28

M11

STP_PCI # / GPIO 3 4

V6

SATACLKREQ # / GPIO35

AB7

SATA2GP / GPI O 36

AB13

SATA3GP / GPI O 37

V3

SLOAD / GPIO38

P3

SDATAOUT0 / GPIO39

H3

PC IEC LK RQ6 # / GPIO 45

F1

PC IEC LK RQ7 # / GPIO 46

AB6

SDATAOUT1 / GPIO48

AA4

SATA5GP / GPI O 49

F8

GPIO57

A4

VSS_NCTF_1

A49

VSS_NCTF_2

A5

VSS_NCTF_3

A50

VSS_NCTF_4

A52

VSS_NCTF_5

A53

VSS_NCTF_6

B2

VSS_NCTF_7

B4

VSS_NCTF_8

B52

VSS_NCTF_9

B53

VSS_NCTF_10

BE1

VSS_NCTF_11

BE53

VSS_NCTF_12

BF1

VSS_NCTF_13

BF53

VSS_NCTF_14

BH1

VSS_NCTF_15

BH2

VSS_NCTF_16

BH52

VSS_NCTF_17

BH53

VSS_NCTF_18

BJ1

VSS_NCTF_19

BJ2

VSS_NCTF_20

BJ4

VSS_NCTF_21

BJ49

VSS_NCTF_22

BJ5

VSS_NCTF_23

BJ50

VSS_NCTF_24

BJ52

VSS_NCTF_25

BJ53

VSS_NCTF_26

D1

VSS_NCTF_27

D2

VSS_NCTF_28

D53

VSS_NCTF_29

E1

VSS_NCTF_30

E53

VSS_NCTF_31

IBE X PEAK- M_FCBG A1071

PEG _CLKR EQ#<12>

Com p a l S ecret Data

Deciphered Date

2

MISC

CLKOUT _BCL K0_ N / CLKOUT_PCIE8N
CLKOUT _BCL K0_ P / CLKOUT_ PCIE8P

GPIO

CPU

NCTF

RSVD

+3VS_NV

2

61

Q29A
2N7002DW-7-F_SOT363-6

2

CLKOUT_PCIE6N
CLKOUT_PCIE6P

CLKOUT_PCIE7N
CLKOUT_PCIE7P

PROCPWRGD

Q29B

5

AH45

T19 P A D

AH46

T20 P A D

AF48

T21 P A D

AF47

T22 P A D

GA TEA20

U2

A20GATE

AM3
AM1

PCH_PECI_R

BG10

PECI

KB_RST#

T1

RCIN#

BE10

H_TH E RMTRIP#_L

BD10

THRMTRIP#

BA22

TP1

AW22

TP2

BB22

TP3

AY45

TP4

AY46

TP5

AV43

TP6

AV45

TP7

AF13

TP8

M18

TP9

N18

TP10

AJ24

TP11

AK41

TP12

AK42

TP13

M32

TP14

N32

TP15

M30

TP16

N30

TP17

H12

TP18

AA23

TP19

AB45

NC_1

AB38

NC_2

AB42

NC_3

AB41

NC_4

T39

NC_5

P6

INIT3_3V#

C10

TP24

DGPU_PWROK

3

4

2N7002DW-7-F_SOT363-6

Title

Size Do c u ment Numbe r R e v

Custom

Calp ell a DI S L A4 743P

Date: Sheet of

GATEA2 0 < 37 >

CLK_CPU_BCLK# <6>
CLK_CPU_BCLK <6>

R144 0_0402_5%

KB_RST# <37>
H_CPUPWRGD <6>

1 2

R146

EC_SCI#
DG P U _ ED IDSEL#
KB_RST#
DGPU_PWR_EN
DGPU_HPD_INT#
VGA _ PRSNT_ L#
DGP U _ H O LD_RST#
GPIO38
GA TEA20
PCH_TEMP_ALERT#
GPIO39
GPIO48
CR_WAKE#
DGPU_PWROK

INIT3_3V

This signal has weak internal
PU, can't pull low

T48 P A D

EC_SMI#
PCH_GPIO15
PCH_GPIO12
PCI ECL KREQ6 #
PCI ECL KREQ7 #
PCH_GPIO28
GPIO57
GPIO35
VGA _ PRSNT_L #

Compal Electronics, Inc.

IBEX-M(4/6)- PCI/USB/RSVD

1

OK

1 2

54.9_0402_1%

12

R147
56_0402_5%

+VCCP

R166 10K_0402_5%

1 2

R167 10K_0402_5%

1 2

R171 10K_0402_5%

1 2

R172 10K_0402_5%

1 2

R173 10K_0402_5%

1 2

R175 10K_0402_5%

1 2

R176 10K_0402_5%

1 2

R178 10K_0402_5%

1 2

R180 10K_0402_5%

1 2

R181 10K_0402_5%

1 2

R169 10K_0402_5%

1 2

R170 10K_0402_5%

1 2

R168 10K_0402_5%

1 2

R874 10K_0402_5%

1 2

R157 10K_0402_5%

1 2

R159 1K_0402_5%

1 2

R811 10K_0402_5%

1 2

R812 10K_0402_5%

1 2

R813 10K_0402_5%

1 2

R814 10K_0402_5%

1 2

R182 10K_0402_5%

1 2

R165 10K_0402_5%
R911 10K_0402_5%

1 2

1

H_PECI <6>

H_THERMTRIP# <6>

+3VS

+3VALW

12

0.1

14 49Monday, April 13, 2009

http://laptop-motherboard-schematic.blogspot.com/

5

4

3

2

1

1

2

1 2

1

1

C162

2

2

10U_0805_6.3V6M

1 2

0.1U_0402_16V4Z

+1.8VS

+1.05VS

1

C173

2

1U_0402_6.3V6K

+V1 . 1 A_ INT_VCCSUS

+3 VALW

+3VS

1/

1/ 2BA2/2W

1/1/

1

1

C188

2

2

4.7U_0603_6.3V6K

3n

3n BA4/4W

3n3n

1

2

+VCCP_VCCA_CLK

1

C143

@

@

2

10U_0805_6.3V6M

C152

0.1U_0402_16V4Z

+1.05VS

1

C153

2

1

C163

2

10U_0805_6.3V6M

+VC C RTCEXT

1

C174

C175

2

1U_0402_6.3V6K

+VC C SST

1/

1/ 3BA4/4W

3BA4/4W

1/1/

3BA4/4W3BA4/4W

1/

1/ 5BA4/4W

5BA4/4W

1/1/

5BA4/4W5BA4/4W

2BA2/2W

2BA2/2W2BA2/2W

1

C189

2

0.1U_0402_16V4Z

BA4/4W

BA4/4WBA4/4W

1

C197

C196

2

0.1U_0402_16V4Z

AP51

C144

AP53

1U_0402_6.3V6K

AF23
AF24

Y20

AD38
AD39
AD41
AF43
AF41

1U_0402_6.3V6K

AF42

V39
V41
V42
Y39

C161

Y41

1U_0402_6.3V6K

Y42

V9

AU24

BB51
BB53

BD51
BD53

AH23

AJ35

AH35
AF34
AH34

1U_0402_6.3V6K

AF32

V12

Y22

P18
U19
U20
U22

V15
V16
Y16

AT18

AU18

C190

A12

0.1U_0402_16V4Z

0.1U_0402_16V4Z

U1J

VCCACLK[1]
VCCACLK[2]

VCCLAN[1]
VCCLAN[2]

DCPSUSBYP

VCCME[1]
VCCME[2]
VCCME[3]
VCCME[4]
VCCME[5]
VCCME[6]
VCCME[7]
VCCME[8]
VCCME[9]
VCCME[10]
VCCME[11]
VCCME[12]

DCPRTC

VCCVRM[3]

VCCADPLLA[1]
VCCADPLLA[2]

VCCADPLLB[1]
VCCADPLLB[2]

VCCIO[21]
VCCIO[22]
VCCIO[23]

VCCIO[2]
VCCIO[3]
VCCIO[4]
DCPSST

DCPSUS

VCCSUS3_3[29]
VCCSUS3_3[30]
VCCSUS3_3[31]
VCCSUS3_3[32]

VCC3_3[5]
VCC3_3[6]
VCC3_3[7]

V_CPU_IO[1]

V_CPU_IO[2]

VCCRTC

IBE X PEAK- M_FCBG A10 71

0.035A

0.072A

0.073A

POWER

0.052A

0.344A

1.998A

Clock and Miscellaneous

3.208A

PCI/GPIO/LPC

CPU

2mA

RTC

VCCSUS3_3[1]
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
VCCSUS3_3[6]
VCCSUS3_3[7]
VCCSUS3_3[8]

VCCSUS3_3[9]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]

USB

VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]

0.163A

VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]
VCCSUS3_3[21]
VCCSUS3_3[22]
VCCSUS3_3[23]
VCCSUS3_3[24]
VCCSUS3_3[25]
VCCSUS3_3[26]
VCCSUS3_3[27]

VCCSUS3_3[28]

>1mA

>1mA

0.357A

PCI/GPIO/LPC

VCCSATAPLL[1]

0.032A

VCCSATAPLL[2]

SATA

6mA

HDA

VCCIO[5]
VCCIO[6]
VCCIO[7]
VCCIO[8]

VCCIO[56]

V5REF_SUS

V5REF

VCC3_3[8]

VCC3_3[9]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]

VCC3_3[14]

VCCIO[9]

VCCVRM[4]

VCCIO[10]
VCCIO[11]
VCCIO[12]
VCCIO[13]

VCCIO[14]
VCCIO[15]
VCCIO[16]

VCCIO[17]
VCCIO[18]
VCCIO[19]
VCCIO[20]

VCCME[13]
VCCME[14]
VCCME[15]
VCCME[16]

VCCSUSHDA

V24
V26
Y24
Y26

V28
U28
U26
U24
P28
P26
N28
N26
M28
M26
L28
L26
J28
J26
H28
H26
G28
G26
F28
F26
E28
E26
C28
C26
B27
A28
A26

U23
V23
F24

K49

J38
L38
M36
N36
P36
U35

AD13

AK3
AK1

AH22

AT20

AH19
AD20
AF22
AD19

AF20
AF19
AH20

AB19
AB20
AB22
AD22

AA34
Y34
Y35
AA35

L30

4

+1.05VS

1

C150

2

1U_0402_6.3V6K

1

C157

2

+1.05VS

ICH_V5REF_SUS

ICH_V5REF_RUN

+3VS

1

C171

2

0.1U_0402_16V4Z

+3VS

C176 0.1U_0402_16V4Z

1 2

+1 . 0 5VS_ VCCAPL L

+1.8VS

1

C184

2

1U_0402_6.3V6K

+PCH _VCC1_1_20
+PCH _VCC1_1_21
+PCH _VCC1_1_22
+PCH _VCC1_1_23

+3 . 3 A_ 1 .5A_VC CPAZSUS

+3VALW

1

C158

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1/

1/ 2BA2/2W

2BA2/2W

1/1/

2BA2/2W2BA2/2W

1

C180

@

2

1U_0402_6.3V6K

R194 0_0402_5%

1 2

R195 0_0402_5%

1 2

R198 0_0402_5%

1 2

R200 0_0402_5%

1 2

1

2

@

1 2

10UH_LB2012T100MR_20%_0805

1

C181

2

@

10U_0805_6.3V6M

+1.05VS

+3VALW

C193

1U_0402_6.3V6K

L4

+1.05VS

+1.05VS

R188

@

1 2

10UH_LB2012T100MR_20%_0805

0_0603_5%

C682 0.1U_0402_16V4Z

+1.05VS+1.0 5VS_ VCCAPL L_ L

R189

@

1 2

0_0603_5%

+1.05 VS_L+1.05VS +V1. 05S_VCCA_A_DPL_L

R191

1 2

0_0603_5%

1 2

0_0603_5%

R201

1 2

0_0603_5%

Security Classification

Issued Date

THIS SHE E T OF E NGIN EE RI NG D RA W ING I S THE P RO P RIE TAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+1.05VS

1

C145

2

L3

@

1 2

+1.05VS

1

C164

2

1

1

C168

2

2

1U_0402_6.3V6K

+3VS

1 2

+1.8VS

+1. 0 5 V S_VCCFDIPLL

+1.05VS

R192

+V1. 05S_VCCA_B_DPL_L

1 2

10UH_LB2012T100MR_20%_0805

1 2

10UH_LB2012T100MR_20%_0805

U1G

AB24

VCCCORE[1]

AB26

VCCCORE[2]

AB28

1

2

1U_0402_6.3V6K

+1.05 VS_APL L

1

2

1

2

1U_0402_6.3V6K

1

C169

2

1U_0402_6.3V6K

L6

L7

AD26
AD28

C146

10U_0603_6.3V6M

AH26
AH28
AH30
AH31

AK24

AN20
AN22
AN23

C159

@

AN24
AN26

10U_0805_6.3V6M

AN28

AU26
AU28
AV26
AV28
AW26
AW28
BA26

C165

BA28
BB26

1U_0402_6.3V6K

BB28
BC26
BC28
BD26
BD28
BE26
BE28
BG26
BG28

C170

BH27

10U_0603_6.3V6M

AN30
AN31

AN35

AM23

VCCCORE[3]
VCCCORE[4]
VCCCORE[5]

AF26

VCCCORE[6]

AF28

VCCCORE[7]

AF30

VCCCORE[8]

AF31

VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]

AJ30

VCCCORE[14]

AJ31

VCCCORE[15]

VCCIO[24]

BJ24

VCCAPLLEXP

VCCIO[25]
VCCIO[26]
VCCIO[27]
VCCIO[28]
VCCIO[29]
VCCIO[30]

BJ26

VCCIO[31]

BJ28

VCCIO[32]

AT26

VCCIO[33]

AT28

VCCIO[34]
VCCIO[35]
VCCIO[36]
VCCIO[37]
VCCIO[38]
VCCIO[39]
VCCIO[40]
VCCIO[41]
VCCIO[42]
VCCIO[43]
VCCIO[44]
VCCIO[45]
VCCIO[46]
VCCIO[47]
VCCIO[48]
VCCIO[49]
VCCIO[50]
VCCIO[51]
VCCIO[52]
VCCIO[53]

VCCIO[54]
VCCIO[55]

VCC3_3[1]

AT22

VCCVRM[1]

BJ18

VCCFDIPLL
VCCIO[1]

IBE X PEAK- M_FCBG A1071

+V1 .0 5S_VCCA_ A_D PL

2

1

+V1 .0 5S_VCCA_ B_D PL

1

2

2008/03/13 2009/05/11

POWER

1.524A

0.042A

0.035A
6mA

1

+

C186

C187

2

1U_0402_6.3V6K

220U_D2_4VM_R15

1

+

C192

C191

2

1U_0402_6.3V6K

220U_B_2.5VM_R15M

Com p a l S ecret Data

Deciphered Date

VCC CORE

0.059A

PCI E*

FDI

0.069A

CRTLVDS

0.030A

HVCMOS

DMI

0.156A

NAND / SPI

0.085A

12

2

VCCTX_LVDS[1]
VCCTX_LVDS[2]
VCCTX_LVDS[3]
VCCTX_LVDS[4]

0.061A

R193

@

0_0603_5%

VCCADAC[1]

VCCADAC[2]
VSSA_DAC[1]
VSSA_DAC[2]

VCCALVDS

VSSA_LVDS

VCCPNAND[1]
VCCPNAND[2]
VCCPNAND[3]
VCCPNAND[4]
VCCPNAND[5]
VCCPNAND[6]
VCCPNAND[7]
VCCPNAND[8]
VCCPNAND[9]

VCCME3_3[1]
VCCME3_3[2]
VCCME3_3[3]
VCCME3_3[4]

VCC3_3[2]
VCC3_3[3]
VCC3_3[4]

VCCVRM[2]

VCCDMI[1]
VCCDMI[2]

AE50
AE52
AF53
AF51

AH38
AH39

AP43
AP45
AT46
AT45

AB34
AB35
AD35

AT24

AT16
AU16

AM16
AK16
AK20
AK19
AK15
AK13
AM12
AM13
AM15

AM8
AM9
AP11
AP9

1

2

C998

1

2

+1.8VS

+VCCP

+1.05VS

R196

100_0402_5%

12

L5

@

1 2

R197

100_0402_5%

1

+3VS

+1.8VS

+1.8VS

+3VS

+1. 0 5 V S_VCCFDIPLL

+5VS +3VS+3VALW+5 VALW

12

L45

MURATA_BLM18AG601SN1D_0603

1

1

C148

C147

0.01U_0603_16V7K
C999

1

2

+3VS

12

C149

2

2

0.1U_0402_16V4Z

10U_0805_6.3V6M

0.01U_0402_25V7K

+3VS

R779 0_0603_5%

1 2

10U_0805_6.3V6M

0.01U_0603_16V7K
C1000

1

1

2

2

+3VS

1

C160

2

0.1U_0402_16V4Z

C167

1U_0402_6.3V6K

R671 0_0402_5%

1

C172

2

0.1U_0402_16V4Z

1

C178

2

0.1U_0402_16V4Z

R190

@

1 2

0_0603_5%

21

D4
CH751H-40PT_SOD323-2

1

C194
1U_0402_6.3V4K_X5R

2

Title

Size Do c u ment Numbe r R e v

Custom

Date: Sheet

1 2

R672 0_0402_5%@

1 2

+1.0 5 VS_VCCFDIPLL_L

10UH_LB2012T100MR_20%_0805

ICH_V5REF_SUS

Compal Electronics, Inc.

IBEX-M(5/6)- PWR

Calp ell a DI S L A4 743P

1

C183

@

2

10U_0805_6.3V6M

21

D5

CH751H-40PT_SOD323-2

ICH_V5REF_RUN

20 mils20 mi ls

1

C195
1U_0402_6.3V4K_X5R

2

15 49Monday, April 13, 2009

of

0.1

+1.05VS +VCCP_ VCCA_CLK_L

R186

@

1 2

0_0603_5%

10UH_LB2012T100MR_20%_0805

D D

C C

B B

A A

DG1.1 no M3
support and not
Intel LAN, VCCLAN
Source=>GND

+RTCVCC

@

L1

1 2

C166

+V1 .0 5S_VCCA_ A_D PL
+V1 .0 5S_VCCA_ B_D PL

1

2

1 2

0.1U_0402_16V4Z

C177

1 2

0.1U_0402_16V4Z

C179

1 2

0.1U_0402_16V4Z

C182

1 2

0.1U_0402_16V4Z

C185

+VCCP

5

http://laptop-motherboard-schematic.blogspot.com/

5

4

3

2

1

U1I

AY7

VSS[159]

B11

VSS[160]

B15

VSS[161]

B19

VSS[162]

B23

VSS[163]

B31

VSS[164]

B35

VSS[165]

B39

VSS[166]

B43

VSS[167]

B47

D D

C C

B B

BG12
BB12
BB16
BB20
BB24
BB30
BB34
BB38
BB42
BB49

BC10
BC14
BC18

BC22
BC32
BC36
BC40
BC44
BC52

BD48
BD49

BE12
BE16
BE20
BE24
BE30
BE34
BE38
BE42
BE46
BE48
BE50

BF49
BF51
BG18
BG24

BG50
BH11
BH15
BH19
BH23
BH31
BH35
BH39
BH43
BH47

AF39

VSS[168]

B7

VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]

BB5

VSS[180]
VSS[181]
VSS[182]
VSS[183]

BC2

VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]

BH9

VSS[191]
VSS[192]
VSS[193]

BD5

VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]

BE6

VSS[206]

BE8

VSS[207]

BF3

VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]

BG4

VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]

BH7

VSS[224]

C12

VSS[225]

C50

VSS[226]

D51

VSS[227]

E12

VSS[228]

E16

VSS[229]

E20

VSS[230]

E24

VSS[231]

E30

VSS[232]

E34

VSS[233]

E38

VSS[234]

E42

VSS[235]

E46

VSS[236]

E48

VSS[237]

E6

VSS[238]

E8

VSS[239]

F49

VSS[240]

F5

VSS[241]

G10

VSS[242]

G14

VSS[243]

G18

VSS[244]

G2

VSS[245]

G22

VSS[246]

G32

VSS[247]

G36

VSS[248]

G40

VSS[249]

G44

VSS[250]

G52

VSS[251]
VSS[252]

H16

VSS[253]

H20

VSS[254]

H30

VSS[255]

H34

VSS[256]

H38

VSS[257]

H42

VSS[258]

VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[326]
VSS[327]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[332]
VSS[333]
VSS[334]
VSS[335]
VSS[336]
VSS[337]
VSS[338]
VSS[339]
VSS[340]
VSS[341]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
VSS[353]
VSS[354]
VSS[355]
VSS[356]
VSS[366]

H49
H5
J24
K11
K43
K47
K7
L14
L18
L2
L22
L32
L36
L40
L52
M12
M16
M20
N38
M34
M38
M42
M46
M49
M5
M8
N24
P11
AD15
P22
P30
P32
P34
P42
P45
P47
R2
R52
T12
T41
T46
T49
T5
T8
U30
U31
U32
U34
P38
V11
P16
V19
V20
V22
V30
V31
V32
V34
V35
V38
V43
V45
V46
V47
V49
V5
V7
V8
W2
W52
Y11
Y12
Y15
Y19
Y23
Y28
Y30
Y31
Y32
Y38
Y43
Y46
P49
Y5
Y6
Y8
P24
T43
AD51
AT8
AD47
Y47
AT12
AM6
AT13
AM5
AK45
AK39
AV14

U1H

AB16

VSS[0]

AA19

VSS[1]

AA20

VSS[2]

AA22

VSS[3]

AM19

VSS[4]

AA24

VSS[5]

AA26

VSS[6]

AA28

VSS[7]

AA30

VSS[8]

AA31

VSS[9]

AA32

VSS[10]

AB11

VSS[11]

AB15

VSS[12]

AB23

VSS[13]

AB30

VSS[14]

AB31

VSS[15]

AB32

VSS[16]

AB39

VSS[17]

AB43

VSS[18]

AB47

VSS[19]

AB5

VSS[20]

AB8

VSS[21]

AC2

VSS[22]

AC52

VSS[23]

AD11

VSS[24]

AD12

VSS[25]

AD16

VSS[26]

AD23

VSS[27]

AD30

VSS[28]

AD31

VSS[29]

AD32

VSS[30]

AD34

VSS[31]

AU22

VSS[32]

AD42

VSS[33]

AD46

VSS[34]

AD49

VSS[35]

AD7

VSS[36]

AE2

VSS[37]

AE4

VSS[38]

AF12

VSS[39]

Y13

VSS[40]

AH49

VSS[41]

AU4

VSS[42]

AF35

VSS[43]

AP13

VSS[44]

AN34

VSS[45]

AF45

VSS[46]

AF46

VSS[47]

AF49

VSS[48]

AF5

VSS[49]

AF8

VSS[50]

AG2

VSS[51]

AG52

VSS[52]

AH11

VSS[53]

AH15

VSS[54]

AH16

VSS[55]

AH24

VSS[56]

AH32

VSS[57]

AV18

VSS[58]

AH43

VSS[59]

AH47

VSS[60]

AH7

VSS[61]

AJ19

VSS[62]

AJ2

VSS[63]

AJ20

VSS[64]

AJ22

VSS[65]

AJ23

VSS[66]

AJ26

VSS[67]

AJ28

VSS[68]

AJ32

VSS[69]

AJ34

VSS[70]

AT5

VSS[71]

AJ4

VSS[72]

AK12

VSS[73]

AM41

VSS[74]

AN19

VSS[75]

AK26

VSS[76]

AK22

VSS[77]

AK23

VSS[78]

AK28

VSS[79]

IBE X PEAK- M_FCBG A10 71

VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]

VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]

AK30
AK31
AK32
AK34
AK35
AK38
AK43
AK46
AK49
AK5
AK8
AL2
AL52
AM11
BB44
AD24
AM20
AM22
AM24
AM26
AM28
BA42
AM30
AM31
AM32
AM34
AM35
AM38
AM39
AM42
AU20
AM46
AV22
AM49
AM7
AA50
BB10
AN32
AN50
AN52
AP12
AP42
AP46
AP49
AP5
AP8
AR2
AR52
AT11
BA12
AH48
AT32
AT36
AT41
AT47
AT7
AV12
AV16
AV20
AV24
AV30
AV34
AV38
AV42
AV46
AV49
AV5
AV8
AW14
AW18
AW2
BF9
AW32
AW36
AW40
AW52
AY11
AY43
AY47

A A

5

IBE X PEAK- M_FCBG A10 71

Security Classification

Issued Date

THIS SHE E T OF E NGIN EE RI NG D RA W ING I S THE P RO P RIE TAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/03/13 2009/05/11

Com p a l S ecret Data

Deciphered Date

2

Title

Size Do c u ment Numbe r R e v

Custom

Date: Sheet

Compal Electronics, Inc.

IBEX-M(6/6)-GND

Calp ell a DI S L A4 743P

1

16 49Monday, April 13, 2009

of

0.1

http://laptop-motherboard-schematic.blogspot.com/

5

+VREF_DQ_DIMMA

0.1U_0402_10V6K

2.2U_0603_6.3V4Z

C1057

1

D D

C C

B B

A A

2

C1058

1

2

DDR_CKE0_DIMMA<8>

DDR_A_BS2<8>

M_C L K_ DDR0<8>
M_C L K_ DDR#0<8>

DDR_A_BS0<8>
DDR_A_WE#<8>

DDR_A_CAS#<8>

DDR_CS1_DIMMA#<8>

+3VS

1

2

5

DDR_A_D0
DDR_A_D1

DDR_A_DM0
DDR_A_D2

DDR_A_D3
DDR_A_D8

DDR_A_D9
DDR_A_DQS#1

DDR_A_DQS1
DDR_A_D10

DDR_A_D11
DDR_A_D16

DDR_A_D17
DDR_A_DQS#2

DDR_A_DQS2
DDR_A_D18

DDR_A_D19
DDR_A_D24

DDR_A_D25
DDR_A_DM3
DDR_A_D26

DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS2
DDR_A_MA12

DDR_A_MA9
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3

DDR_A_MA1
M_C L K _ DDR0

M_C L K _ DDR#0
DDR_A_MA10

DDR_A_BS0
DDR_A_WE#

DDR_A_CAS# M_ODT0
DDR_A_MA13

DDR_CS1_DIMMA#

DDR_A_D32
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A_DM5
DDR_A_D42

DDR_A_D43
DDR_A_D48

DDR_A_D49
DDR_A_DQS#6

DDR_A_DQS6
DDR_A_D50

DDR_A_D51
DDR_A_D56

DDR_A_D57
DDR_A_DM7
DDR_A_D58

DDR_A_D59

1 2

10K_0402_5%

1

C220

C219

2

0.1U_0402_16V4Z

2.2U_0402_6.3V6M

+1.5V +1.5V

4BA2

4BA2/6W

/6W

4BA24BA2

/6W/6W

JDIMM1 CO NN@

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1
VSS49DQS#0

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9
VSS925VSS10

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2
DQS247VSS17
VSS1849DQ22

51

DQ18
DQ1953VSS19
VSS2055DQ28

57

DQ24
DQ2559VSS21
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3
A12/BC#83A11

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1
VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

R208

10K_0402_5%

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

R207

12

VREF_CA

EVENT#

+0.75VS

VSS3

DQS0

VSS6

VSS8
DQ12
DQ13

DM1

DQ14
DQ15

DQ20
DQ21

DM2

DQ23

DQ29

DQS3

DQ30
DQ31

CKE1

VDD2

VDD4

VDD6

VDD8

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VSS28

DQ36
DQ37

VSS30

DM4

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

DM6

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

SDA

VTT2

DQ4
DQ5

DQ6
DQ7

CK1

BA1

NC2

SCL

A15
A14

A7
A6

A4
A2

A0

S0#

G2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

4

DDR_A_D4
DDR_A_D5

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D6
DDR_A_D7

DDR_A_D12
DDR_A_D13

DDR_A_DM1
DRAMRST#

DDR_A_D14
DDR_A_D15

DDR_A_D20
DDR_A_D21

DDR_A_DM2
DDR_A_D22

DDR_A_D23
DDR_A_D28

DDR_A_D29
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D30

DDR_A_D31

DDR_CKE1_DIMMA
DDR_A_MA15

DDR_A_MA14
DDR_A_MA11

DDR_A_MA7
DDR_A_MA6

DDR_A_MA4
DDR_A_MA2

DDR_A_MA0
M_C L K _DDR1

M_C L K _DDR# 1
DDR_A_BS1

DDR_A_RAS#
DDR_CS0_DIMMA#

M_ODT1

V_DDR_MCH_REF

DDR_A_D36
DDR_A_D37

DDR_A_DM4
DDR_A_D38

DDR_A_D39
DDR_A_D44

DDR_A_D45
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D46

DDR_A_D47
DDR_A_D52

DDR_A_D53
DDR_A_DM6
DDR_A_D54

DDR_A_D55
DDR_A_D60

DDR_A_D61
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62

DDR_A_D63
PM_EXTTS#1_R

SMB_DATA_S3
SMB _CLK_S3

1/76B

1/76BA1/86W

1/76B1/76B

4

+0.75VS

A1/86W

A1/86WA1/86W

DRAMR ST# <6,18>

DDR_CKE1_DIMMA <8>

M_C L K_ DDR1 <8>
M_C L K_ DDR#1 <8>

DDR_A_BS1 <8>
DDR_A_RAS# <8>

DDR_CS0_DIMMA# <8>
M_ODT0 <8>

M_ODT1 <8>

PM_EXTTS#1_R <6,18>

SMB_DATA_S3 <12,18,19,30>
SMB _C LK_ S3 <12,18 ,1 9, 30>

+VREF_CA +V_DDR_CPU_REF

1

1

C213

C214

2

2

0.1U_0402_16V4Z

2.2U_0402_6.3V6M

DDR_A_D[0..63]<8>
DDR _ A_ DM[0..7]<8>
DDR_A_DQS[0..7]<8>
DDR _ A_ DQ S#[0..7]<8>
DDR _ A_ MA[0..15]<8>

1 2

R877 0_0402_5%

3

Layout Note:
Place near JP4

1

2

+1.5V

1

1

C203

C201

10U_0603_6.3V6M

C204

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

Layout Note:
Place near JP4.203 & JP4.204

1

C205

2

10U_0603_6.3V6M

+0.75VS

1

1

C206

2

2

10U_0603_6.3V6M

1

1

C216

C215

2

2

1U_0402_6.3V6K

+VREF_DQ_DIMMA

1

C208

C207

2

10U_0603_6.3V6M

1

1

C217

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

2

1 2

R884 0_0402_5%

1 2

R898 0_0402_5%

1

C209

2

0.1U_0402_16V4Z

10U_0603_6.3V6M

1

C202

C218

2

1U_0402_6.3V6K

10U_0805_6.3V6M

1

2

DDR3 SO-DIMM A

Security Classification

Issued Date

THIS SHE E T OF E NGIN EE RI NG D RA W ING I S THE P RO P RIE TAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/03/13 2009/05/11

Com p a l S ecret Data

Deciphered Date

2

M3@

C210

1

V_DDR_CPU_REF+V R EF_ D Q_DI MMA

+V_DDR_CPU_REF

+V_DDR_CPU_REF0

R205

1K_0402_1%

+1.5V

12

+V_DDR_CPU_REF

12

R206
1K_0402_1%

1

C211

2

0.1U_0402_16V4Z

1

1

+

C200
330U_D2_2VY_R7M

C212

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

REVERSE

Title

Size Do c u ment Numbe r R e v

Custom

Date: Sheet

Compal Electronics, Inc.

DDRIII-S ODIM M S LOT1

Calp ell a DI S L A4 743P

1

17 49Monday, April 13, 2009

0.1

of

http://laptop-motherboard-schematic.blogspot.com/

5

+1.5V +1.5V

4BA2

4BA2/6W

/6W

4BA24BA2

+VREF_DQ_DIMMB

1

2

D D

C C

B B

A A

C221

2.2U_0402_6.3V6M

+3VS

1

2

DDR_CKE2_DIMMB<8>

DDR_B_BS2<8>

M_C L K_ DDR2<8>
M_C L K_ DDR#2<8>

DDR_B_BS0<8>
DDR_B_WE#<8>

DDR_B_CAS#<8>

DDR_CS3_DIMMB#<8>

V_DDR_MCH_REF

C1059

0.1U_0402_10V6K

1

1

C241

2

2

2.2U_0402_6.3V6M

DDR_B_D0
DDR_B_D1

DDR_B_DM0
DDR_B_D2

DDR_B_D3
DDR_B_D8

DDR_B_D9
DDR_B_DQS#1

DDR_B_DQS1
DDR_B_D10

DDR_B_D11
DDR_B_D16

DDR_B_D17
DDR_B_DQS#2

DDR_B_DQS2
DDR_B_D18

DDR_B_D19
DDR_B_D24

DDR_B_D25
DDR_B_DM3
DDR_B_D26

DDR_B_D27

DDR_CKE2_DIMMB

DDR_B_BS2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3

DDR_B_MA1
M_C L K _ DDR2

M_C L K _ DDR#2
DDR_B_MA10

DDR_B_BS0
DDR_B_WE#

DDR_B_CAS# M_ ODT2
DDR_B_MA13

DDR_CS3_DIMMB#

DDR_B_D32
DDR_B_D33

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41

DDR_B_DM5
DDR_B_D42

DDR_B_D43
DDR_B_D48

DDR_B_D49
DDR_B_DQS#6

DDR_B_DQS6
DDR_B_D50

DDR_B_D51
DDR_B_D56

DDR_B_D57
DDR_B_DM7
DDR_B_D58

DDR_B_D59

R210

1 2

10K_0402_5%

R211

1 2

10K_0402_5%

C242

0.1U_0402_16V4Z

5

/6W/6W

JD I MM2

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1
VSS49DQS#0

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9
VSS925VSS10

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2
DQS247VSS17
VSS1849DQ22

51

DQ18
DQ1953VSS19
VSS2055DQ28

57

DQ24
DQ2559VSS21
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3
A12/BC#83A11

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1
VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

CONN@

+0.75VS

VSS3
DQS0

VSS6

VSS8
DQ12
DQ13

DQ14
DQ15

DQ20
DQ21

DQ23

DQ29

DQS3
DQ30

DQ31

CKE1
VDD2

VDD4

VDD6

VDD8

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30
VSS31

DQ38
DQ39

VSS33

DQ44

DQ45
VSS35
DQS#5

DQS5
VSS38

DQ46

DQ47
VSS40

DQ52

DQ53
VSS42

VSS43

DQ54

DQ55
VSS45

DQ60

DQ61
VSS47
DQS#7

DQS7
VSS50

DQ62

DQ63
VSS52

EVENT#

VTT2

DQ4
DQ5

DQ6
DQ7

DM1

DM2

CK1

BA1

NC2

DM4

DM6

SDA
SCL

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78

A15

80

A14

82
84
86

A7

88
90

A6

92

A4

94
96

A2

98

A0

100
102
104
106
108
110
112
114

S0#

116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

G2

4

DDR_B_D4
DDR_B_D5

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D6
DDR_B_D7

DDR_B_D12
DDR_B_D13

DDR_B_DM1
DRAMRST#

DDR_B_D14
DDR_B_D15

DDR_B_D20
DDR_B_D21

DDR_B_DM2
DDR_B_D22

DDR_B_D23
DDR_B_D28

DDR_B_D29
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D30

DDR_B_D31

DDR_CKE3_DIMMB
DDR_B_MA15

DDR_B_MA14
DDR_B_MA11

DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2

DDR_B_MA0
M_C L K _DDR3

M_C L K _DDR# 3
DDR_B_BS1

DDR_B_RAS#
DDR_CS2_DIMMB#

M_ODT3

V_DDR_MCH_REF
DDR_B_D36

DDR_B_D37
DDR_B_DM4
DDR_B_D38

DDR_B_D39
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D47
DDR_B_D52

DDR_B_D53
DDR_B_DM6
DDR_B_D54

DDR_B_D55
DDR_B_D60

DDR_B_D61
DDR_B_DQS#7

DDR_B_DQS7
DDR_B_D62

DDR_B_D63
PM_EXTTS#1_R

SMB_DATA_S3
SMB _CLK_S3

4

1/76B

1/76BA1/86W

A1/86W

1/76B1/76B

A1/86WA1/86W

DRAMRST# <6,17>

DDR_CKE3_DIMMB <8>

M_C L K_ DDR3 <8>
M_C L K_ DDR#3 <8>

DDR_B_BS1 <8>
DDR_B_RAS# <8>

DDR_CS2_DIMMB# <8>
M_ODT2 <8>

M_ODT3 <8>

PM_EXTTS#1_R <6,17>

SMB_DATA_S3 <12,17,19,30>
SMB_CLK_S3 <12,17,19,30>

+0.75VS

3

DDR _ B_ DQ S#[0..7]<8>
DDR_B_D[0..63]<8>
DDR _ B_ DM[0..7]<8>
DDR_B_DQS[0..7]<8>
DDR _ B_ MA[0..15]<8>

Layout Note:
Place near JP5

1

1

C223

2

2

@

@

10U_0603_6.3V6M

+VREF_CA

1

1

C235

C1060

2

2

0.1U_0402_16V4Z

2.2U_0603_6.3V4Z

Layout Note:
Place near JP5.203 & JP5.204

+0.75VS

R885

1 2

0_0402_5%

1 2

R899 0_0402_5%M3@

+1.5V

1

1

1

C227

C226

C225

C224

2

10U_0603_6.3V6M

1

1

C237

2

2

1U_0402_6.3V6K

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

C238

C240

C239

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

2

+V_DDR_CPU_REF+VREF_DQ_DIMMB

+V_DDR_CPU_REF1

1

1

C228

C229

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

C230

2

10U_0603_6.3V6M

10U_0603_6.3V6M

1

C231

C232

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C234

C233

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

DDR3 SO-DIMM B
REVERSE

Security Classification

Issued Date

THIS SHE E T OF E NGIN EE RI NG DR A W ING I S THE P RO P RIE TAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/03/13 2009/05/11

Compal Secret Data

Deciphered Date

2

Title

Size D o cu ment Number Re v

Date: Sheet

Compal Electronics, Inc.

DDRIII-S ODIM M S LOT2

Calp ell a DI S L A4 743P

1

18 49Monday, April 13, 2009

of

0.1

http://laptop-motherboard-schematic.blogspot.com/

5

4

3

2

1

+1.05VS_CK505

80mA

+3VS_CK505

250mA

DOT96

OK

CLK_BUF_DOT96<12>
CLK_BUF_DOT96#<12>

DMI

27M_CLK<24>

27M_SSC<24>

CLK_DMI<12>

CLK_DMI#<12>

CLK_BUF_CKSSCD<12>

CLK_BUF_CKSSCD#<12>

27M

OK

OK

D D

OK

CKSSCD

CLK_BUF_DOT96
CLK_BUF_DOT96#

27M_CLK L_27M_CLK
27M_ SSC L_27M_SSC

CLK_DMI
CLK_DMI#

CLK _BUF_CKSSCD
CLK_BUF_CKSSCD#

R213 33_0402_5%
R214 33_0402_5%

R216 33_0402_5%@
R217 33_0402_5%@

R221 33_0402_5%
R223 33_0402_5%

R219 33_0402_5%
R220 33_0402_5%

1 2
1 2

1 2
1 2

12
12

12
12

L_CLK_BUF_DOT96 CLK_14M_PCH
L_CLK_BUF_DOT96#

L _ CL K _DMI
L_CLK _ DMI#

L_CLK_BUF_CKSSCD
L_CLK_BUF_CKSSCD#

CPU_STOP#

U3

1

VDD_DOT

2

VSS_DOT

3

DOT_96

4

96MHz

DOT_96#

5

VDD_27

6

27MHZ

7

27MHZ _SS

8

VSS_27

9

VSS_SATA

10

SRC_1/SATA

11
12
13
14
15
16

SLG 8 SP 5 85VTR_QFN32_5X5

SRC_1#/SATA#
VSS_SRC
SRC_2

100MHz

SRC_2#
VDD_SRC_IO
CPU_STO P#

100MHz

REF_0/CPU_SEL

CKPWRGD/PD#

133MHz

VDD_CPU_IO

TGND

33

Num ber of Clock Outputs

+3VS_CK505

SLG8SP585
SLG8SP587

Κ

pin8 is GND (for DELLΕHP)

Κ

pin8 is 48MHz (For ABO or 030)

CLK_EN#<46>

CLK_EN#

2

Output

133MHz

SRC (100MHz_SS)

SRC /SATA(100MHz)

REF (14.318MHz)

DOT _CLK(96MHz) 1

C C

27MHz

27MHz_SS

PIN 30

0(default)

1

CPU_SEL During CK_PEWGD Latch Pin1

+3VS

@

R244 10 K _0402_5%

1 2

R247 10 K _0402_5%

1 2

Number

133MHz

100MHz

2

1

1

1

1

1

CPU_1C PU_0

133MHz

100MHz

RE F _0/CPU_S EL

C259

18P_0402_50V8J

CPU_STOP#

CLK_XTAL_OUT
CLK_XTAL_IN

Y3

1 2

14.3 18M HZ_16 PF _ 7A14300083

2

2

1

C260
18P_0402_50V8J

Vendor suggests 22pF

1

R234 10K_0 402_5%

1 2

SCL
SDA

VDD_REF

XTAL_IN

XTAL_OU T

VSS_REF

VDD_CPU

CPU_0

CPU_0#

VSS_CPU

CPU_1

CPU_1#

VDD_SRC

+3VS_CK505

12

13

D

G

S

+1.05VS_CK505

+3VS_CK505

32
31
30
29
28
27
26
25

24
23
22
21
20
19
18
17

R607
10K_0402_5%

CKPWRGD

Q30

2N7002_SOT23-3

SMB_CLK_S3
SMB_DATA_S3
RE F _0/CPU_S EL

CLK_XTAL_IN
CLK_XTAL_OUT

R_CKP WRGD

L_CLK_BUF_BCLK
L_CLK_BUF_BCLK#

SMB_CLK_S3 <12,17,18,30>

SMB_DATA_S3 <12,17,18,30>

R222 33_0402_5%

R226 0 _ 0402_5%@
R237 0 _ 0402_5%

R224 33_0402_5%
R225 33_0402_5%

+V CCP

+3VS

1 2
1 2

1 2
1 2

+3VS_CK505

R212

1 2

0_0805_5%

R218

1 2

0_0805_5%

12

1

2

+1.05VS_CK505

1

2

CLK_14M_PCH

CKPWRGD

1

C246

C245

2

10U_0805_10V4Z

Place close to U51

1

C253

C252

2

10U_0805_10V4Z

C80 8 10P_0402_50V8J@

CLK_14M_PCH <12>

VGATE <13,46>

CLK_BUF_BCLK <12>
CLK_BUF_BCLK# <12>

1

1

C247

2

0.1U_0402_16V4Z

1

2

0.1U_0402_16V4Z

C248

2

0.1U_0402_16V4Z

Routing the trace at least 10mil

C254

0.1U_0402_16V4Z

1 2

0.1U_0402_16V4Z

BCLK

1

2

OK

14M

OK

1

C250

C249

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

B B

A A

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEERING DRA WING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND T RADE SEC RET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D
DEP ARTMENT EXCE PT AS AUTHO RIZED BY COMPAL ELECTRONICS, IN C. NEITHER THIS SHEET NOR THE INFORMA T ION IT CONTAINS

5

http://laptop-motherboard-schematic.blogspot.com/

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/08/28 2006/03/10

3

Compa l Secret Data

Dec iphered Date

Title

Size Document Number Re v

Date: Sheet

2

Compal Electronics, Inc.

Clock Generator CK505

Cal p el la D I S L A4743P

19 49Monday, April 13, 2009

1

0.1

of

A

1 1

CRT Connector

+5VS +5VS

C267

0.1U_0402_16V4Z

1 2

1

5

U5
SN74AHCT1G125GW_SOT353-5

2 2

CRT_HSYNC<22>

CRT_VSYNC<22>

CRT_HS YNC

CRT_ VSYNC

P

A2Y

G

3

OE#

4

B

C268

0.1U_0402_16V4Z

1 2

R815 10K_0 4 02_5%

5

P

A2Y

G

3

HSYNC_G_A

1

VS YNC_ G_ A D_V S YNC

4

OE#

U6
SN74AHCT1G125GW_SOT353-5

12

R269 0_0603_5%

1 2

R274 0_0603_5%

1 2

RED

GREEN

BLUE

D_HSYNC

1

C269

@

5P_0402_50V8C

2

C

D9

2 1

RB491D_SC59-3

1

C270

@

5P_0402_50V8C

2

F1

1.1A_6VDC_ F US E

4.7K _0402_5%

D_ D D CDAT A

D_DDCCLK

21

W=40mils

0.1U_0402_16V4Z

JCRT1

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

SUYIN_070546FR015S263ZR

CONN@

+CRTVDD +CRTVDD

12

R270

R271

4.7K_0402_5%

+CRTVDD+RCRT_VCC+5VS

1

2

C266

16
17

12

6 1

2N7002DW-7-F_SOT363-6

D

2

Q2A

2N7002DW-7-F_SOT363-6

3

5

Q2B

BLUE
GREEN
RED

D6

DGP U_E DIDSEL#

R272

4.7K_0402_5%

4

1

2

+3VS

12

+3VS_NV

3

DAN217T146_SC59-3

12

R273

4.7K_0402_5%

D7

1

2

3

DGP U_E DIDS EL#

I_ C RT_DDC_ DA TA

I_ C R T _ DDC_ CLK

D8

DAN217T146_SC59-3

10K_0402_5%

E

Place close to
JCRT1

1

2

3

DAN217T146_SC59-3

+3VS

UMA@

R901

+3VS

1 2

I_ C RT_DDC_DAT A <13>

I_ C R T_DDC_CL K <13>

DGP U_E DIDSEL ED IDSEL

3 3

CRT Ter m i n ation/ EMI Filter

R276

12

150_0402_1%

C_RED

C_GRN

1

1

C271

C272

@

R277

150_0402_1%

@

2

2

22P_0402_50V8J

http://laptop-motherboard-schematic.blogspot.com/

M_RED<22>

M_GREEN<22>

M_BLUE<22>

4 4

A

12

12

R275

150_0402_1%

L8 HLC0603CSCCR11JT_0603

1 2

L9 HLC0603CSCCR11JT_0603

1 2

L10 HLC0603CSCCR11JT_0603

1 2

1

C273

@

2

22P_0402_50V8J

22P_0402_50V8J

B

1

1

C274

2

2

10P_0402_50V8J

RED

GREEN

BLUEC_BLU

1

C276

C275

2

10P_0402_50V8J

10P_0402_50V8J

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEERING DRA WING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND T RADE SEC RET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D
DEP ARTMENT EXCE PT AS AUTHO RIZED BY COMPAL ELECTRONICS, IN C. NEITHER THIS SHEET NOR THE INFORMA T ION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/28 2006/07/26

R900 0_0402_5%

1 2

SG@

D_ D D CDAT A

D_DDCCLK

DGPU_EDIDSEL#<14>

Compa l Secret Data

Dec iphered Date

2

6 1

SG@

Q11A

2N7002DW-7-F_SOT363-6

EDIDSEL

DGP U_E DIDS EL#

D

4.7K_0402_5%

5

3

Q11B

+3VS

SG@

R902
10K_0402_5%

1 2

DGP U_E DIDSEL

3

SG@

Q12B
2N70 02DW-7-F_SOT 363-6

4

4

SG@

2N70 02DW-7-F_SOT 363-6

5

12

12

SG@

R878

Title

Size Document Number Re v

Date: Sheet

SG@

R879

4.7K_0402_5%

D_ C R T_DDC_DA TA <24>

EDIDSEL <22>

D_ C R T_DDC_CLK <24>

Q12A

2

2N7002DW-7-F_SOT363-6

6 1

Compal Electronics, Inc.

CRT Connector

Cal p el la D I S L A4743P

20 49Monday, April 13, 2009

E

of

0.1

5

INVPWR_B++LCDVDD+3VS

D D

1

12

C277

2

680P_0402_50V7K

USB20_P4<14>
USB20_N4<14>

C C

12

C278

680P_0402_50V7K

USB20_P4

C279

680P_0402_50V7K

USB20_N4

LVDS CONN & USB Camera + Dig Mic

JLVDS1

+3VS

1
3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

GND41GND

ACES_88242-4001

CONN@

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42

4

LVDS_A2­LVDS_A2+
LVDS_A1­LVDS_A1+
LVDS_A0­LVDS_A0+
LVDS_ ACLK­LVDS_ ACLK+

DMIC_DAT
DMIC_CLK
+3V_LOGO
LVDS_ INV _PWM
BKOFF#

LV DS_ E DID_ CL K
LVDS_ EDID_DATA

R284

2.2K_0402_5%

LV DS_ E DID_ CL K
LVDS_ EDID_DATA

R281

1 2

100_08 05_5%

+USB_CAM

EMI request.

+3VS

1 2

1

C286
680P_0402_50V7K

2

R285

2.2K _0402_5%

1 2

LVD S _A2- <22>
LVDS_A2+ <22>
LVD S _A1- <22>
LVDS_A1+ <22>
LVD S _A0- <22>
LVDS_A0+ <22>
LVDS_ACLK- <22>
LVDS_ACLK+ <22>

DMIC_DAT <33>

DMIC_CLK <33>

+5VS

LVDS_INV_PWM <22>

BKOFF# <37>

LV DS_EDID_ CLK <22>
LVDS_ EDID_DATA <22>

Must cl ose JLVDS1pin 24ΕΕΕΕ26

DMIC_CLK
DMIC_DAT

1

C287

@

220P_0402_25V8J

2

3

0.1U_0402_16V4Z

02/13 Reserve

BKOFF#

1

C288

@

220P_0402_25V8J

2

C281

1

2

@

10K_0402_5%

1 2

1

C282

0.1U_0402_16V4Z

2

R282

02/20 Cha nge to 0805 size

12

R278

470_0805_5%

61

2

2N7002DW-7-F_SOT363-6
Q3A

Limited Current < 1A

I_ENAVDD<13>

I_E NAVDD

10K_0402_5%

D_ENAVDD<24>

@

L11 0_0805_5%

L12
FBMA-L11-201209-221LMA30T_0805

2

12

R283

2.2K_0402_5%

1 2

1 2

R279

1M_0402_5%

5

SG@

R880

1

C280

4.7U_0805_10V4Z

12

SG@

Q33
2N7002_SOT23-3

+LCDVDD

SI2301BDS-T1-E3_SOT23-3

1 3

1

2

C284

0.047U_0402_16V7K

Q13

D

01/03 Chan ge to 0.047u to meet T1 timing

+5VALW+LCDVDD+LCDVDD

12

R280

100K_0402_5%

3

Q3B

4

2N7002DW-7-F_SOT363-6

13

D

2

G

S

1 2

INVPWR_B+B+

+3VS

S

G

2

1

C283

4.7U_0805_10V4Z

2

0308_Reserve L10 and install L11.

B B

USB Camera

+5VS

R288

0_0402_5%

1

C290

10U_0805_6.3V6M

A A

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEERING DRA WING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND T RADE SEC RET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D
DEP ARTMENT EXCE PT AS AUTHO RIZED BY COMPAL ELECTRONICS, IN C. NEITHER THIS SHEET NOR THE INFORMA T ION IT CONTAINS

5

http://laptop-motherboard-schematic.blogspot.com/

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/07/26

+USB_CAM is +3.9VS, R286:215K; R287:100Kohm

Compa l Secret Data

Dec iphered Date

2

2

1 2

U7

1

IN

2

GND

3

SHDN

G916-390T1UF_SOT23-5

5

OUT

4

BYP

+USB_CAM=1.25(1+R1091/R1093)

Title

Size Document Number Re v

Date: Sheet

Compal Electronics, Inc.

LCD CONN.

Cal p el la D I S L A4743P

12

R286
215K_0603_1%

12

R287
100K_0402_1%

1

+USB_CAM

1

2

1

C981

C289

@

2

47P_0402_50V8J

10U_0805_6.3V6M

0.1

of

21 49Monday, April 13, 2009

5

4

3

2

1

LVDS Switch

U35

D_L VDS_A0+<25>

D_L VDS_A0-<25>

D_L VDS_A1+<25>

D_L VDS_A1-<25>

D_L VDS_A2+<25>
D_L VDS_A2-<25>
D_L V DS_ACLK+<25>

D D

D_LVDS_ACLK-<25>

I_L VDS_A0+<13>

I_LVDS_A0-<13>

I_L VDS_A1+<13>

I_LVDS_A1-<13>

I_L VDS_A2+<13>

I_LVDS_A2-<13>

I_L V DS_ACLK+<13>

I_L VDS_ACLK-<13>

C C

D_L VDS_A0+
D_L VDS_A0­D_L VDS_A1+
D_L VDS_A1­D_L VDS_A2+
D_L VDS_A2­D_LVDS_ACLK+
D_L V DS_ACLK-

I_ LVDS_A0+
I_ LVDS_A0­I_ LVDS_A1+
I_ LVDS_A1­I_ LVDS_A2+
I_ LVDS_A2­I_L V DS_ACLK+
I_L VDS_ACLK-

48

0B1

47

1B1

43

2B1

42

3B1

37

4B1

36

5B1

32

6B1

31

7B1

22

8B1

23

9B1

46

0B2

45

1B2

41

2B2

40

3B2

35

4B2

34

5B2

30

6B2

29

7B2

25

8B2

26

9B2

52

NC

5

NC

54

NC

51

NC

57

Thermal_ GND

TS3 DV 5 2 0ERHUR_Q FN56_11X5~D

SG@

VCC
VCC
VCC
VCC
VCC
VCC
VCC

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9

SEL

CRT Switch

+3VS

B B

0.1U_0402_16V4Z

SG@

1

C1011

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C1012

2

SG@

1

C1013

2

SG@

4
10
18
27
38
50
56

2
3
7
8
11
12
14
15
19
20

17
1

6
9
13
16
21
24
28
33
39
44
49
53
55

0.1U_0402_16V4Z

1

C1014

2

+3VS

LVDS_A0+
LVDS_A0­LVDS_A1+
LVDS_A1­LVDS_A2+
LVDS_A2­LVDS_ACLK+
LVDS_ACLK-

R790

1 2

0_0402_5%

SG@

SG@

1

2

C1004

0.1U_0402_16V4Z

SG@

DG P U _ SELECT#

C1005

4.7U_0805_10V4Z

SG@
LVDS_A0+ <21>
LVDS_A0- <21>
LVDS_A1+ <21>
LVDS_A1- <21>
LVDS_A2+ <21>
LVDS_A2- <21>
LVDS_ACLK+ <21>
LVDS_ACLK- <21>

DG P U _ SELECT# <14>

DPST_PWM<1 3>

D_INV_PWM<24>

I_EDID_DATA<13>

I_ED ID_CLK<13>

2N7002DW-7-F_SOT363-6

LVDS I2C switch

EDIDSEL

2

LVD S _ ED ID_DATA

D_EDID_DATA<24> LVDS_EDID_DATA <21>

R919 0_0402_5%

1 2

D_EDID_CLK<2 4>

R920 0_0402_5%

1 2

SG@

R891

4.7K_0402_5%

1 2

61

SG@

Q36A

2

3

5

SG@

4

Q36B
2N7002DW-7-F_SOT363-6

2

SG@

2N7002DW-7-F_SOT363-6

5

4

Q34B

SG@

2N7002DW-7-F_SOT363-6

LVDS PWM switch

+3VS

SG@

R889

4.7K_0402_5%

1 2
61

SG@

Q37A
2N7002DW-7-F_SOT363-6

61

Q34A

LVD S _ ED ID_CLK

3

R890 0_0402_5%@

DPST_PWM LVDS_INV_PWM

12

UMA@

R892 0_0402_5%

EDI DSEL < 20 >

LVD S _ EDID_CL K <2 1>

INV_PWM <37>

LVDS _I NV_PWM <21>

12

Backlight Enable

SG@

R883

4.7K_0402_5%

61

SG@

2N7002DW-7-F_SOT363-6

IG P U _ BKLT_ EN<13>

DGPU _ BKL_EN<24>

Q35A

SG@

R886

10K_0402_5%

2

5

1 2

UMA ONLY (LVDS)

I_ LVDS_A0­I_ LVDS_A0+

I_ LVDS_A1­I_ LVDS_A1+

I_ LVDS_A2+ LVDS_A2+
I_ LVDS_A2-

I_L VDS_ACLK­I_L V DS_ACLK+

+3VS

1 2

1 2

3

5

3

4

SG@

Q35B

4

2N7002DW-7-F_SOT363-6

R799 0_0402_5%

RP36

RP37

RP38

RP39

14
23

14
23

23
14

14
23

SG@

R882

4.7K_0402_5%

ENBKL

SG@

Q37B
2N7002DW-7-F_SOT363-6

UMA@

1 2

LVDS_A0-

LVDS_A0+

0_0404_4P2R_5%UMA@

LVDS_A1-

LVDS_A1+

0_0404_4P2R_5%UMA@

LVDS_A2-

0_0404_4P2R_5%UMA@

LVDS_ACLK-

LVDS_ACLK+

0_0404_4P2R_5%UMA@

ENBKL <37>

ENBKLIG PU _BKLT_EN

U43

+3VS

D_RED<24>
D_GREEN<24>
D_BLUE<24>
D_CRT_HSYNC<24>
D_CRT_VSYNC<24>

I_RED<13>
I_ G R EEN<13>
I_BLUE<13>
I_CRT_HSYNC<13>
I_CRT_VSYNC<13>

A A

5

1

VDD

4

VDD

9

VDD

19

VDD

24

A0

22

B0

18

C0

17

D0

14

E0

23

A1

21

B1

16

C1

15

D1

13

E1

PI3V512QE_QSOP24

SG@

GND
GND
GND
GND

SEL

YA
YB
YC

YD
YE

DG P U _ SELECT#

12

M_RED

2

M_G R EEN

5

M_BLUE

6

C RT_HSYNC

8

CRT_VSYNC

11

3
7
10
20

M_RED <20>
M_G REEN <20>
M_BLUE <20>

CRT_ HSYNC <20>
CRT_VSYNC <20>

UMA ONLY (CRT)

I_RED
I_ G R EEN
I_BLUE
I_CRT_HSYNC
I_CRT_VSYNC

4

R893 0_0402_5%UMA@
R894 0_0402_5%UMA@
R895 0_0402_5%UMA@
R896 0_0402_5%UMA@
R897 0_0402_5%UMA@

12
12
12
12
12

M_RED
M_G R EEN
M_BLUE
C RT_HSYNC

CRT_VSYNC

Security Classification

Issued Date

THIS SHE E T OF E NGIN EE RI NG DR A W ING I S THE P RO P RIE TAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/09/29 2007/09/29

Compal Secret Data

Deciphered Date

2

Title

Size D o cu ment Number Re v

Custom

Date: Sheet

Compal Electronics, Inc.

LVDS Switch

Calp ell a DI S L A4 743P

1

22 49Monday, April 13, 2009

of

0.1

http://laptop-motherboard-schematic.blogspot.com/

5

Parade

Parade

ST

R833

R837

R836

R840

R838

R842

D D

R849

R850

XXX

0 ohm

4.7K ohmX

4.7K ohm

X

X

3.9K ohm499 ohm

0 ohmXXX

C1052

0 ohm 0 ohm X

R853

X X 4.7K o hm

R855
R857

X X 4.7K o hm

R858

0 ohm 0 ohm

R851

XXX4.7K ohm

R854

0 ohm 0 ohm

R843

0 ohm 0 ohm

R844

XXX4.7K ohm

R839

0 ohm 4.7K ohm

R834

XX X

0 ohm

R841

XX

R835
C667 0.1uF 1uF

C C

B B

A A

R862

R867

V

V

HDMI_C_CLK-<25>

HDMI_C_CLK+<25>

HDMI_C_TX0-<25>

HDMI_C_TX0+<25>

HDMI_C_TX1-<25>

HDMI_C_TX1+<25>

HDMI_C_TX2-<25>

HDMI_C_TX2+<25>

8171

8101T

0 ohm 4.7K ohm

X

X 4.7K ohm

X

4.7K ohm

XX

499 ohm

X2.2uF

X

X

XX

4.7K ohm
1uF

X

X

X

X

SG@

C375 0.1U_0402_16V4Z

12

SG@

C376 0.1U_0402_16V4Z

12

SG@

C377 0.1U_0402_16V4Z

12

SG@

C378 0.1U_0402_16V4Z

12

SG@

C379 0.1U_0402_16V4Z

12

SG@

C380 0.1U_0402_16V4Z

12

SG@

C382 0.1U_0402_16V4Z

12

SG@

C381 0.1U_0402_16V4Z

12

+3VS_NV

5

R571

@

2.2K_0402_5%

HDMIDAT_VGA<25>

HDMICLK_VGA<25>

EQUALIZATION SETTING:
[PC1,PC0]=00,8dB
[PC1,PC0]=01,4dB (Recommanded)
[PC1,PC0]=10,12dB
[PC1,PC0]=11,0dB

R859 0_0402_5%@

HDMICLK-

HDMICLK+

R866

@

R868 0_0402_5%@

HDMI_TX_0-

HDMI_TX_0+

R869

@

R870 0_0402_5%@

HDMI_TX_1-

HDMI_TX_1+

R871

@

R872 0_0402_5%@

HDMI_TX_2-

HDMI_TX_2+

R873

@

HDMICLK­HDMICLK+
HDMI_TX_0­HDMI_TX_0+
HDMI_TX_1- HDMI_DETECT
HDMI_TX_1+
HDMI_TX_2­HDMI_TX_2+

12

SG@

SG@

R734

R733

499_04 02_1%

499_0402_1%

13

D

SG@

2

2N7002_SOT23-3

G

S

12

1 2

L28

1

1

4

4

1 2

1 2

L29

1

1

4

4

1 2

1 2

L30

1

1

4

4

1 2

1 2

L31

1

1

4

4

1 2

12

SG@

R735

499_04 02_1%

Q31

+3VS_NV

12

499_0402_1%

4

R572

@

2.2K _0402_5%

1 2

4

R576 0_0402_5%@

2

2

WCM-2012-900T_0805

3

3

0_0402_5%

2

2

WCM-2012-900T_0805

3

3

0_0402_5%

2

2

WCM-2012-900T_0805

3

3

0_0402_5%

2

2

WCM-2012-900T_0805

3

3

0_0402_5%

12

SG@

SG@

R736

R737

499_0402_1%

SG@

5

Q5B
2N70 02DW-7-F_SOT363-6

3

1 2

HDMID_CTRLDATA<13>
HDMID_CTRLCLK<13>

HDMI_R_CLK-

HDM I_R_CL K +

HDMI_R_TX0-

HDMI_R_TX0+

HDMI_R_TX1-

HDMI_R_TX1+

HDMI_R_TX2-

HDMI_R_TX2+

12

SG@

R738

499_0402_1%

2.2K _0402_5%

12

SG@

R739

499_0402_1%

+3VS_NV

SG@

Q5A

2

2N70 02DW-7-F_SOT 363-6

61

R575 0_0402_5%@

1 2

+3VS_LS

1 2

12

12

UMA@

12

UMA@

R848

R847

2.2K_0402_5%

UMA@

R850 0_0402_5%

1 2

1 2

C1052

@

2.2U_0603_6.3V4Z

12

SG@

R740

499_0402_1%

+3VS_LS

R838

@

4.7K_0402_5%
R842

@

0_0402_5%

HDMI_DET<24>

HDMIDAT

HDMICLK

12

+3VS_LS

+3VS_LS

SG@

R924

10K_0402_5%

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEERING DRA WING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND T RADE SEC RET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D
DEP ARTMENT EXCE PT AS AUTHO RIZED BY COMPAL ELECTRONICS, IN C. NEITHER THIS SHEET NOR THE INFORMA T ION IT CONTAINS

http://laptop-motherboard-schematic.blogspot.com/

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

TMDSD_DA TA2#<13>
TMDSD_DA TA2<13>

TMDSD_CLK#<13>
TMDSD_CLK<13>

+3VS_LS

4.7K_0402_5%

UMA@

12

R836

@

4.7K _0402_5%

UMA@

R840

1 2

4.7K _0402_5%

UMA@

R853 0_0402_5%

1 2

R855 4.7K_0402_5%@

1 2

R857 4.7K_0402_5%@

1 2
UMA@

R858 0_0402_5%

1 2

4

Y

12

DGPU_HPD_INT#<14>

R837

1 2

0_0402_5%

+3VS_LS

UMA@

R84 9 4 .3K_ 0 402_1%

TMDS_B_HPD

HDMICLK+
HDMICLK-

+3VS

5

2

P

B

1

A

G

U51

3

NC7SZ08P5X_NL_SC70-5

SG@

2N7002DW-7-F_SOT363-6

3

2

+3VS_LS +3VS_LS

TMDSD_DATA1 <13>
TMDSD_DA TA1# <13>

TMDSD_DATA0 <13>
TMDSD_DA TA0# <13>

+3VS_LS

R833

@

12

HDMI_ T X_2+ TMDS_B_HPD
HDMI_ T X_2-

12

1
2
3
4
5
6
7
8

9
10
11
12
49

C1053

@

1 2

68_0402_5%

0.5P _0402_50V8B

0.5P_0402_50V8B

UMA@

48

45

43

IN_D3+

44

IN_D3-

42

GND

47

U47

GND
VCC3V
FUNCTI ON1
FUCNT ION2
GND
ANALOG 1(REXT)
HPD_SOURCE
SDA_SOUR CE
SCL_SOUR CE
ANALOG 2
VCC3V
GND
thm_pad

R860

@

C1055

@

46

IN_D4-

VCC3V

IN_D4+

PC0

PC1

OUT_D4+13OUT_D4-14VCC3V15OUT_D3+16OUT_D3-17GND18OUT_D2+19OUT_D2-20VCC3V21OUT_D1+22OUT_D1-23GND

R863

@

1 2

68_0402_5%

IN_D2+

41

IN_D2-

+3VS_LS+3VS_LS

39

40

VCC3V

IN_D1+

R864

@

1 2

68_0402_5%

37

38

GND

IN_D1-

0.5P_0402_50V8B

36

GND

35

FUNCTI ON4

34

FUNCTI ON3

33

VCC3V

32

DDC_EN

31

GND

30

HPD_SINK

29

SDA_SINK

28

SCL_SINK

27

GND

26

VCC3V

25

OE*

S IC S T HDL S101TQ T R QF N 4 8 P HDMI SHIFTE R

24

R861

@

1 2

68_0402_5%

HDMI_ T X_1-

C1056

@

HDMI_ T X_1+

HDMI Connector

HDMI_DETECT
DGPU_PWR_EN

3

2007/08/28 2006/03/10

5

Q19B

SG@

SKS10-04AT_TSMA

4

DGPU_P WR_EN <14,39,45,47>

12

D35

2 1

Compa l Secret Data

Dec iphered Date

R579

1 2

10K_0402_1%

R580
100K_0402_1%

HDMIDAT

C668

HDMICLK

1

2

L32 FBML10 1 60808121LMT_0603

1 2

330P_0402_50V7K

2

1

UMA@

R832

1 2

0_0603_5%

2

UMA@

1

C1048

0.01U_0402_16V7K

R834 4.7K_0402_5%@
R835 4.7K_0402_5%@

UMA@

R839 0_0402_5%

UMA@

R841 0_0402_5%

R843 0_0402_5%UMA@
R844 0_0402_5%@
R845 4.7K_0402_5%UMA@
R846 0_0402_5%@

HDMI_DETECT
HDMIDAT
HDMICLK

+3VS_LS

R856 0_0402_5%

UMA@

HDMI_TX_0-

C1054

@

HDMI_TX_0+

0.5P_0402_50V8B

RB411DT146_SOT23-3

R577

1 2

1.5K _0402_5%

HDM I_R_CL K ­HDM I_R_CL K +
HDMI_R_TX0­HDMI_R_TX0+
HDMI_R_TX1­HDMI_R_TX1+
HDMI_R_TX2­HDMI_R_TX2+

Title

Size Document Number Re v

Custom

Cal p el la D I S L A4743P

Date: Sheet

12
12

12
12
12

12
12
12

R851 4.7K_0402_5%@
R854 0_0402_5%

1 2

UMA@

12

TMDS_B_HPD#<13>

21

C665

D34

@

+5VS_HDMI

@

R578

1 2

1.5K _0402_5%

Compal Electronics, Inc.

HDMI LS & Conn.

1

1

UMA@

UMA@

2

2

C1050

C1049

12

2N7002DW-7-F_SOT363-6

1

2

C666

22N_0402_16V7K

18
16
15
19

12
10

9
7
6
4
3
1

0.1U_0402_10V6K

0.1U_0402_10V6K

+3VS_LS
+3VS_LS

+3VS_LS
+3VS_LS

+3VS_LS

HDMI_DETECT

Q19A

SG@

+3VS_LS

12

UMA@

R862
20K_0402_5%

UMA@

R865

12

0_0402_5%

UMA@

R867

7.5K_0402_1%

+5VS_HDMI+5VS

22N_0402_16V7K

1

1

C667

2

2

0.1U_0402_16V4Z

JHDMI1

+5V
SDA
SCL
HP_DET

CK­CK+
D0­D0+
D1­D1+
D2­D2+

DDC/CEC_GND

SUYIN_100042MR019S153ZL

CONN@

1

C1051

+3VS_LS

2

CEC

Reserved

GND
GND
GND
GND
GND
GND
GND
GND

23 49Monday, April 13, 2009

1

UMA@

2

10U_0805_6.3V6M

12

61

12

+3VS_LS+3VS

R852
10K_0402_5%

UMA@

13
14

2
5
8
11
20
21
22
23
17

of

0.1

1

U8A

PEX_R ST#

AE12

AF12
AG12
AG13

AF13

AE13

AE15

AF15
AG15
AG16

AF16

AE16

AE18

AF18
AG18
AG19

AF19

AE19

AE21

AF21
AG21
AG22

AF22

AE22

AE24

AF24
AG24

AF25
AG25
AG26

AF27

AE27
AD10

AD11
AD12
AC12

AB11

AB12
AD13
AD14
AD15
AC15

AB14

AB15
AC16
AD16
AD17
AD18
AC18

AB18

AB19

AB20
AD19
AD20
AD21
AC21

AB21

AB22
AC22
AD22
AD23
AD24

AE25

AE26

AB10
AC10

AF10

AE10
AG10

AD9
AE9

N10M-GLM-S-A1_BGA533

SG@

PCIE_CTX_GRX_P15<7>
PCIE_CTX_GRX_N15<7>
PCIE_CTX_GRX_P14<7>
PCIE_CTX_GRX_N14<7>
PCIE_CTX_GRX_P13<7>
PCIE_CTX_GRX_N13<7>
PCIE_CTX_GRX_P12<7>
PCIE_CTX_GRX_N12<7>
PCIE_CTX_GRX_P11<7>
PCIE_CTX_GRX_N11<7>

A A

PCIE_CTX_GRX_P10<7>
PCIE_CTX_GRX_N10<7>
PCIE_CTX_GRX_P9<7>
PCIE_CTX_GRX_N9<7>
PCIE_CTX_GRX_P8<7>
PCIE_CTX_GRX_N8<7>
PCIE_CTX_GRX_P7<7>
PCIE_CTX_GRX_N7<7>
PCIE_CTX_GRX_P6<7>
PCIE_CTX_GRX_N6<7>
PCIE_CTX_GRX_P5<7>
PCIE_CTX_GRX_N5<7>
PCIE_CTX_GRX_P4<7>
PCIE_CTX_GRX_N4<7>
PCIE_CTX_GRX_P3<7>
PCIE_CTX_GRX_N3<7>
PCIE_CTX_GRX_P2<7>
PCIE_CTX_GRX_N2<7>
PCIE_CTX_GRX_P1<7>
PCIE_CTX_GRX_N1<7>
PCIE_CTX_GRX_P0<7>
PCIE_CTX_GRX_N0<7>

PCIE_CRX_GTX_P15<7>
PCIE_CRX_GTX_N15<7>
PCIE_CRX_GTX_P14<7>
PCIE_CRX_GTX_N14<7>
PCIE_CRX_GTX_P13<7>
PCIE_CRX_GTX_N13<7>
PCIE_CRX_GTX_P12<7>
PCIE_CRX_GTX_N12<7>
PCIE_CRX_GTX_P11<7>
PCIE_CRX_GTX_N11<7>
PCIE_CRX_GTX_P10<7>
PCIE_CRX_GTX_N10<7>

B B

PCIE_CRX_GTX_P9<7>
PCIE_CRX_GTX_N9<7>
PCIE_CRX_GTX_P8<7>
PCIE_CRX_GTX_N8<7>
PCIE_CRX_GTX_P7<7>
PCIE_CRX_GTX_N7<7>
PCIE_CRX_GTX_P6<7>
PCIE_CRX_GTX_N6<7>
PCIE_CRX_GTX_P5<7>
PCIE_CRX_GTX_N5<7>
PCIE_CRX_GTX_P4<7>
PCIE_CRX_GTX_N4<7>
PCIE_CRX_GTX_P3<7>
PCIE_CRX_GTX_N3<7>
PCIE_CRX_GTX_P2<7>
PCIE_CRX_GTX_N2<7>
PCIE_CRX_GTX_P1<7>
PCIE_CRX_GTX_N1<7>
PCIE_CRX_GTX_P0<7>
PCIE_CRX_GTX_N0<7>

CLK_PCIE_VGA<12>
CLK_PCIE_VGA#<12>

DGP U _ H O LD_RST#<14>

C C

D D

+3 VS_NV

C776 0.1U_0402_16V4ZSG@
C777 0.1U_0402_16V4ZSG@
C778 0.1U_0402_16V4ZSG@
C779 0.1U_0402_16V4ZSG@
C780 0.1U_0402_16V4ZSG@
C781 0.1U_0402_16V4ZSG@
C782 0.1U_0402_16V4ZSG@
C783 0.1U_0402_16V4ZSG@
C784 0.1U_0402_16V4ZSG@
C785 0.1U_0402_16V4ZSG@
C786 0.1U_0402_16V4ZSG@
C787 0.1U_0402_16V4ZSG@
C788 0.1U_0402_16V4ZSG@
C789 0.1U_0402_16V4ZSG@
C790 0.1U_0402_16V4ZSG@
C791 0.1U_0402_16V4ZSG@
C792 0.1U_0402_16V4ZSG@
C793 0.1U_0402_16V4ZSG@
C794 0.1U_0402_16V4ZSG@
C795 0.1U_0402_16V4ZSG@
C796 0.1U_0402_16V4ZSG@
C797 0.1U_0402_16V4ZSG@
C798 0.1U_0402_16V4ZSG@
C799 0.1U_0402_16V4ZSG@
C800 0.1U_0402_16V4ZSG@
C801 0.1U_0402_16V4ZSG@
C802 0.1U_0402_16V4ZSG@
C803 0.1U_0402_16V4ZSG@
C804 0.1U_0402_16V4ZSG@
C805 0.1U_0402_16V4ZSG@
C806 0.1U_0402_16V4ZSG@
C807 0.1U_0402_16V4ZSG@

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

R689 200_0402_1%@

1 2

R691 2.49K_0402_1%SG@

1 2

R693 0_0402_5%SG@

1 2

R694 10K_0402_5%SG@

1 2

PCIE_CRX_GTX_G_P15
PCIE_CRX_GTX_G_N15
PCIE_CRX_GTX_G_P14
PCIE_CRX_GTX_G_N14
PCIE_CRX_GTX_G_P13
PCIE_CRX_GTX_G_N13
PCIE_CRX_GTX_G_P12
PCIE_CRX_GTX_G_N12
PCIE_CRX_GTX_G_P11
PCIE_CRX_GTX_G_N11
PCIE_CRX_GTX_G_P10
PCIE_CRX_GTX_G_N10
PCIE_CRX_GTX_G_P9
PCI E_CRX_GTX_G_N9
PCIE_C RX_G TX_G_P8
PCIE_CRX_GTX_G_N8
PCIE_C RX_G TX_G_P7
PCIE_CRX_GTX_G_N7
PCIE_C RX_G TX_G_P6
PCIE_CRX_GTX_G_N6
PCIE_C RX_G TX_G_P5
PCIE_CRX_GTX_G_N5
PCIE_C RX_G TX_G_P4
PCIE_CRX_GTX_G_N4
PCIE_C RX_G TX_G_P3
PCIE_CRX_GTX_G_N3
PCIE_C RX_G TX_G_P2
PCIE_CRX_GTX_G_N2
PCIE_C RX_G TX_G_P1
PCIE_CRX_GTX_G_N1
PCIE_C RX_G TX_G_P0
PCIE_CRX_GTX_G_N0

CLK_PCIE_VGA
CLK_PCIE_VGA#

2

Part 1 of 5

PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
PEX_RX8
PEX_RX8_N
PEX_RX9
PEX_RX9_N
PEX_RX10
PEX_RX10_N
PEX_RX11
PEX_RX11_N
PEX_RX12
PEX_RX12_N
PEX_RX13
PEX_RX13_N
PEX_RX14
PEX_RX14_N
PEX_RX15
PEX_RX15_N

PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
PEX_TX8
PEX_TX8_N
PEX_TX9
PEX_TX9_N
PEX_TX10
PEX_TX10_N
PEX_TX11
PEX_TX11_N
PEX_TX12
PEX_TX12_N
PEX_TX13
PEX_TX13_N
PEX_TX14
PEX_TX14_N
PEX_TX15
PEX_TX15_N

PEX_REFCLK
PEX_REFCLK_N

PEX_TSTCLK_OUT
PEX_TSTCLK_OUT_N

PEX_TERMP
PEX_RST_N
PEX_CLKREQ_N

PCI EXPRESS

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11

GPIO

GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19

DACA_HSYNC
DACA_VSYNC

DACA_RED

DACA_BLUE

DACA_GREEN

DACA_VREF
DACA_RSET

DACB_HSYNC
DACB_VSYNC

DACB_RED

DACB_BLUE

DACB_GREEN

DACB_VREF
DACB_RSET

JTAG_TCK

JTAG_TDI
JTAG_TDO
JTAG_TMS

JTAG_TRST_N

TEST

TESTMODE

I2CA_SCL
I2CA_SDA

I2CB_SCL
I2CB_SDA

I2CC_SCL

I2CC_SDA

I2C DACADACB

I2CH_SCL
I2CH_SDA

I2CS_SCL
I2CS_SDA

XTAL_SSIN

XTAL_OUTBUFF

XTAL_OUT

XTAL_IN

CLK

20P_0402_50V8

N1
G1
C1
M2
M3
K3
K2
J2
C2
M1
D2
D1
J3
J1
K1
F3
G3
G2
F1
F2

AD2
AD1

AE2
AD3
AE3

AF1
AE1

U6
U4

T5
R4
T4

R6
V6

AF3
AG4
AE4
AF4
AG3

AD25

R1
T3

R2
R3

A2
B1

A3
A4

T1
T2

D11
E9
E10
D10

SG@

C810

XTALIN

THERMAL ALERT
SINN_GPIO9

D_RED
D_BLUE
D_GREEN

DACA_VREF
DACA_RSEF

JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST

R903 10K_0402_5%@
R688 10K_0402_5%SG@

I2CB_SCL
I2CB_SDA

D_EDID_CLK
D_EDID_DATA

HDCP_SCL
HDCP_SDA

VGA_SM_CLK

27 M_SSC

XTALOUT
XTALIN

27MHZ_18PF_X3S027000FI1H-X

1

2

C358 0.1U_0402_16V4ZSG@
R294 124_0402_1%SG@

1 2
1 2

SG@

1 3
2 4

HDMI_DET <23>
D_INV_PWM <22>
D_ENAVDD <21>
DGPU _ BKL_EN <22>
GPU_VID0 <47>
GPU_VID1 <47>
GPU_VID2

D_CRT_HSYNC <22>
D_CRT_VSYNC <22>

D_RED <22>
D_BLUE <22>

D_GREEN <22>

1 2
1 2

T64 TPC 12
T65 TPC 12
T66 TPC 12
T67 TPC 12

R690 10K_0402_5%@

R692 10K_0402_5%@

R695 0_0402_5%@

Y7

R327 0_0402_5%SG@
R328 0_0402_5%SG@

1 2
1 2

1 2

3

1 2
1 2

D_CR T_ DD C_CLK <20>
D_CRT_DDC_DATA <20>

D_ED ID _CLK <22>
D_ED ID _DATA <22>

D_EDID_CLK

R3250_0402_5% @
R3260_0402_5% @

XTALOUT

1

SG@

C811
20P_0402_50V8

2

D_EDID_DATAVGA_SM_DA

12

12

THERM#_VGA
THERM_SCI#

CRT

LVDS

HDCP_SCL <25>

HDCP_SDA <25>

27 M _SSC <19>

27M_CLK <19>

THERM_SCI#<37>

HDCP

VGA _SM_CLK
VGA_SM_DA

R315 0_0402_5%SG@
R316 0_0402_5%SG@

THERM_SCI#

THER M#_VGA

Close to GPU

D_RED
D_GREEN
D_BLUE

I2CB_SCL
I2CB_SDA

HDCP_SCL
HDCP_SDA

GPU_VID0
GPU_VID1

D_ED ID _CLK
D_EDID_DATA

12
12

4

1 2

R297 150_0402_1%SG@
R296 150_0402_1%SG@
R295 150_0402_1%SG@

R319 2.2K_0402_5%SG@
R320 2.2K_0402_5%SG@

R686 2.2K_0402_5%SG@
R687 2.2K_0402_5%SG@

R595 10K_0402_5%@
R187 10K_0402_5%@

R808 2.2K_0402_5%SG@
R809 2.2K_0402_5%SG@

12

1 2
1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

SMB_E C_CK2_R <12>

SMB_E C_DA2_R <12>

+3 VS_NV

SG@

R69610K_0402_5%

SG@

R31410K_0402_5%

+3VS_NV

GPIO I/O ACTIVE USAGE

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

IN

OUT

OUT

OUT

N/A

N/A

H

H

H

N/A

N/A

N/A

L

L

N/A

L

N/A

L

H

N/A

N/A

N/A

N/A

GPIO0

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

GPIO9

GPIO10

GPIO11

GPIO12

GPIO13

GPIO14

GPIO15

GPIO16

GPIO17

GPIO18

5

HPD-C (used for IFPC)

2nd DVI Hot-plug

Panel Back-Light PW M

Panel Power Enable

Panel Back-Light Enable

NVVDD VID0

NVVDD VID1

NVVDD VID2

OVERT

T h e rmal Alert

MEM_VREF

SLI SYNCO

AC Detect

MEM_V ID

PS Control

HPD-E (used for IFPE)IN

FAN PWM Control

GPIO19 N/A HPD-D (used for IFPD)IN

Security Classification

Issued Date

THIS SHE E T OF E NGIN EE RI NG DR A W ING I S THE P RO P RIE TAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

1

http://laptop-motherboard-schematic.blogspot.com/

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/09/15 2009/12/31

Compal Secret Data

Deciphered Date

4

Title

Size D o cu ment Number Re v

Custom

Date: Sheet

Comp al El ectronics, Inc.

PEG Interface

Calpella DIS LA4743P

5

24 49Monday, April 13, 2009

of

0.1

1

2

3

4

5

LVDS Interface

U8C

D_LVDS_ACLK+<22>
D_LVDS_ACLK-<22>
D_L VDS_A0+<22>
D_L VDS_A0-<22>
D_L VDS_A1+<22>
D_L VDS_A1-<22>
D_L VDS_A2+<22>

A A

B B

D_L VDS_A2-<22>

HDMICLK_VGA<23>
HDMIDAT_VGA<23>

HDMI_C_TX2+<23>
HDMI_C_TX2-<23 >
HDMI_C_TX1+<23>
HDMI_C_TX1-<23 >
HDMI_C_TX0+<23>
HDMI_C_TX0-<23 >
HDM I_ C_ CLK+<23>
HDM I_ C_ CLK-<23>

HDMI_C_TX2+

HDMI_C_TX2-

HDMI_C_TX1+

HDMI_C_TX1-

HDMI_C_TX0+

HDMI_C_TX0-

HDM I_ C_CLK+

HDM I_ C_CLK-

AC4

IFPA_TXC

AD4

IFPA_TXC_N

V5

IFPA_TXD0

V4

IFPA_TXD0_N

AA5

IFPA_TXD1

AA4

IFPA_TXD1_N

W4

IFPA_TXD2

Y4

IFPA_TXD2_N

AB4

IFPA_TXD3

AB5

IFPA_TXD3_N

AB3

IFPB_TXC

AB2

IFPB_TXC_N

W1

IFPB_TXD4

V1

IFPB_TXD4_N

W3

IFPB_TXD5

W2

IFPB_TXD5_N

AA2

IFPB_TXD6

AA3

IFPB_TXD6_N

AB1

IFPB_TXD7

AA1

IFPB_TXD7_N

G4

IFPC_AUX_I2CW_SCL

G5

IFPC_AUX_I2CW_SDA_N

P4

IFPC_L0

N4

IFPC_L0_N

M5

IFPC_L1

M4

IFPC_L1_N

L4

IFPC_L2

K4

IFPC_L2_N

H4

IFPC_L3

J4

IFPC_L3_N

D3

IFPD_AUX_I2CX_SCL

D4

IFPD_AUX_I2CX_SDA_N

F5

IFPD_L0

F4

IFPD_L0_N

E4

IFPD_L1

D5

IFPD_L1_N

C3

IFPD_L2

C4

IFPD_L2_N

B3

IFPD_L3

B4

IFPD_L3_N

F7

IFPE_AUX_I2CY_SCL

G6

IFPE_AUX_I2CY_SDA_N

D6

IFPE_L0

C6

IFPE_L0_N

A6

IFPE_L1

A7

IFPE_L1_N

B6

IFPE_L2

B7

IFPE_L2_N

E6

IFPE_L3

E7

IFPE_L3_N

N10M-GLM-S-A1_BGA533

SG@

Part 3 of 5

C15

NC

D15

NC

J5

NC

NCRFU

T6

RFU_1

W6

RFU_2

Y6

RFU_3

AA6

RFU_4

N3

RFU_5

STR AP0

C7

STRAP0
STRAP1
STRAP2

BUFRST_N

LVDS / TMDS

THERMDN
THERMDP

GENERAL STRAPSERIAL

SPDIF

ROM_CS_N
ROM_SCLK

ROM_SI

ROM_SO

IFPAB_RSET

IFPC_RSET
IFPD_RSET
IFPE_RSET

CEC

B9
A9

N5

D8
D9

N2
F9

B10
C9
A10
C10

AB6
R5
M6
F8

STR AP1
STR AP2

VGA_THERMDC
VGA_THERMDA

SPDIF_IN

ROM_CS#
ROM_SCLK
ROM_SI
ROM_SO

IFPAB_RSET
IFPC_RSET
IFP D _ R SET
IFPE_RSET

SG@

R669 36K_0402_1%

1 2

SG@

R301 10K_0402_5%

1 2

R290 1K_0402_1%@

1 2

SG@

R302 1K_0402_1%

1 2

SG@

R697 1K_0402_1%

1 2

SG@

R698 1K_0402_1%

1 2

SPDIF

+3VS_NV

Straps

C C

D D

1

http://laptop-motherboard-schematic.blogspot.com/

2

HDCP ROM

U10

1

A0

VCC

2

A1

WP

3

SCL

A2

4

SDA

GND

AT2 4 C1 6 BN- SHBY- B

SG@

Security Classification

Issued Date

THIS SHE E T OF E NGIN EE RI NG DR A W ING I S THE P RO P RIE TAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

8
7
6
5

+3 VS_NV

1

SG@

C388

0.1U_0402_16V4Z

2

HDCP_SCL
HDCP_SDA

HDCP_SCL

R313
10K_0402_5%

HDCP_SCL <24>

HDCP_SDA <24>

12

@

2008/09/15 2009/12/31

Compal Secret Data

Deciphered Date

MULTI LEVEL STRAPS

4

@

SG@

SG@

SG@

SG@

@

STR AP0
STR AP1
STR AP2
ROM_SI
ROM_SO
ROM_SCLK

R329

1 2

4.99K_0402_1%
R339

1 2

35K_0402_1%

R342

1 2

24.9K_0402_1%
R344

1 2

15K_0402_1%

R346

1 2

4.99K_0402_1%
R348

1 2

4.99K_0402_1%

SG@

R330

1 2

45.3K_0402_1%
R340

@

1 2

4.99K_0402_1%
R343

@

1 2

4.99K_0402_1%
R345

@

1 2

4.99K_0402_1%
R347

@

1 2

4.99K_0402_1%
R349

SG@

1 2

4.99K_0402_1%

Title

N10M(2)_ LVDS&DP&HDCP

Size D o cu ment Number Re v

Custom

Date: Sheet

FB HW Strap for DDR3: (RAM_CFG @ROM_SI)

- Hynix 64Mx16: 0000 (R344 pull-down 15K)

- Samsung 64Mx16: 0001 (R344 pull-down 20K)

+3 VS_NV

Compal Electronics, Inc.

Calp ell a DI S L A4743P

5

25 49Monday, April 13, 2009

0.1

of

1

2

3

4

5

CMDA7

32~63 CKE 0~31 CKE0~31 ODT32~63 ODT

@

R745

100_0402_5%

1 2

12

SG@

R747
10K_0402_5%

CMDA18

@

100_0402_5%

1 2

12

SG@

R751
10K_0402_5%

R749

A A

U8B

MDA[15..0]<28>

MDA[31..16]<28>

B B

MDA[47..32]<29>

MDA[63..48]<29>

C C

MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

+VDD_MEM

AC24
AB23
AB24

W24

AA22

W23
W22

AA25

W27
W26

W25
AB25
AB26
AD26
AD27

D22
E24
E22
D24
D26
D27
C27
B27
A21
B21
C21
C19
C18
D18
B18
C16
E21

F21

D20

F20

D17

F18
D16
E16
A22
C24
D21
B22
C22
A25
B25
A26
U24
V24
V23
R24

T23
R23
P24
P22

V22

V25
R25
V26
V27
R26

T25
N25
N26

Part 2 of 5

FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31

MEMORY INTERFACE

FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

N10M-GLM-S-A1_BGA533

SG@

FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7

FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8

FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28

FBA_CMD29
FBA_CMD30

FBA_DQM0

FBA_DQM1

FBA_DQM2

FBA_DQM3

FBA_DQM4

FBA_DQM5

FBA_DQM6

FBA_DQM7

FB_VREF

FBA_CLK0

FBA_CLK0_N

FBA_CLK1

FBA_CLK1_N

FBA_DEBUG

CMDA0

F26

CMDA1

J24

CMDA2

F25

CMDA3

M23

CMDA4

N27

CMDA5

M27

CMDA6

K26

CMDA7

J25

CMDA8

J27

CMDA9

G23

CMDA10

G26

CMDA11

J23

CMDA12

M25

CMDA13

K27

CMDA14

G25

CMDA15

L24

CMDA16

K23

CMDA17

K24

CMDA18

G22

CMDA19

K25

CMDA20

H22

CMDA21

M26

CMDA22

H24

CMDA23

F27

CMDA24

J26

CMDA25

G24

CMDA26

G27

CMDA27

M24

CMDA28

K22

CMDA29

J22

CMDA30

L22

DQMA0

C26

DQMA1

B19

DQMA2

D19

DQMA3

D23

DQMA4

T24

DQMA5

AA23

DQMA6

AB27

DQMA7

T26

DQSA#0

D25

DQSA#1

A18

DQSA#2

E18

DQSA#3

B24

DQSA#4

R22

DQSA#5

Y24

DQSA#6

AA27

DQSA#7

R27

DQSA0

C25

DQSA1

A19

DQSA2

E19

DQSA3

A24

DQSA4

T22

DQSA5

AA24

DQSA6

AA26

DQSA7

T27

FB_VREF

A16
F24

F23
N24

N23

ODT

M22

SG@

ODT

R12 10K_0402_5%

W=15mils

1 2

CMDA[30..0] <28,29>

DQM A[3..0 ] <28>

DQM A[7..4 ] <29>

DQS A# [3..0] <28>

DQS A# [7..4] <29>

DQSA [3..0] <28>

DQSA [7..4] <29>

CL KA0 <28>
CL KA0# <28>

CL KA1 <29>
CL KA1# <29>

+VDD_MEM

+VDD_MEM +VDD_MEM +VDD_MEM +VDD_MEM

CMDA28

@

100_0402_5%

1 2

12

SG@

R748
10K_0402_5%

R746

CMDA30

@

R750

100_0402_5%

1 2

12

SG@

R752
10K_0402_5%

12

R699

@

Rt

1K_0402_1%

R701

@

1K_0402_1%

D D

12

C813

Rb

@

Close to U8

FB_VREF

0.1U_0402_16V4Z

1

2

Security Classification

Issued Date

THIS SHE E T OF E NGIN EE RI NG DR A W ING I S THE P RO P RIE TAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

1

http://laptop-motherboard-schematic.blogspot.com/

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/09/15 2009/12/31

Co m pa l Secret Data

Deciphered Date

4

Title

Size D o cu ment Number Re v

Custom

Date: Sheet

Compal Electronics, Inc.

N10M(3)_VGA RAM In terface

Calp ell a DI S L A4 743P

5

26 49Monday, April 13, 2009

of

0.1

1

VGA P ow er se qu e nc e : + . 3 V S->+NVVDD->+VDD_MEM

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C814

1

2

A A

0.022u X 9

0.01u X 3

0.1u X 8

4.7u X 1
1u( 0402) X 1
1u( 0603) X 1
10u (0805) X 3

B B

SG@

0.022U_0402_16V7K

C831

1

2

SG@

+3 VS_NV

SG@

R703 0_0603_5%

1 2

1U_0603_10V4Z

C858

1

0.1U_0402_16V4Z

C815

C816

1

1

2

2

SG@

SG@

0.022U_0402_16V7K

0.022U_0402_16V7K

C832

C833

1

1

2

2

SG@

SG@

2

SG@

11.44A

C818

C835

C848

C860

1

2

SG@

1

2

SG@

1

2

SG@

1

2

SG@

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C819

1

2

SG@

0.022U_0402_16V7K

0.022U_0402_16V7K
C836

1

2

SG@

4.7U_0603_6.3V6K

1U_0402_6.3V4Z

C849

1

2

SG@

150mA

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C861

1

2

SG@

0.1U_0402_16V4Z

C817

1

2

SG@

0.022U_0402_16V7K

C834

1

2

SG@

10U_0805_6.3V6M

C847

1

2

SG@

VDD33

1U_0402_6.3V4Z

C859

1

2

SG@

150mA

SG@

R71 10K_0402_5%

1 2

SG@

R76 10K_0402_5%

1 2

SG@

R79 10K_0402_5%

1 2

+PCIE

C C

SG@

SG@

D D

SG@

L34

1 2

BLM18PG181SN1D_0603

4.7U_0603_6.3V6K

C868

1

2

+3 VS_NV

SG@

L38

1 2

BLM18PG181SN1D_0603

4.7U_0603_6.3V6K

C883

1

2

+3 VS_NV

SG@

L41

1 2

BLM18PG181SN1D_0603

C869

C884

C958

1

2

SG@

1

2

SG@

1

2

SG@

85mA

4.7U_0603_6.3V6K

70mA

4.7U_0603_6.3V6K

120mA

4.7U_0603_6.3V6K

IFPAB_PLLVDD

4700P_0402_25V7K

1U_0603_10V6K

@

C871

C870

1

1

2

2

SG@

IFPC_PLLVDD

1U_0603_10V6K

0.1U_0402_10V6K

C885

C886

1

1

2

2

SG@

SG@

1U_0402_6.3V4Z

4700P_0402_25V7K

C899

C900

1

1

2

2

SG@

SG@

1

0.1U_0402_10V6K

@

C952

1

2

0.1U_0402_10V6K

C961

1

2

SG@

DACA_VDD

0.1U_0402_10V6K

C901

1

2

SG@

0.1U_0402_10V6K

@

C959

1

2

0.1U_0402_10V6K

C962

1

2

SG@

0.1U_0402_10V6K

C887

1

1

C888
470P_0402_50V8J

2

2

SG@

SG@

150mA

+1 .8VS_ NV

BLM18PG181SN1D_0603

+PCIE +PCIE

SG@

http://laptop-motherboard-schematic.blogspot.com/

2

+NVVDD

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C820

C821

1

1

2

2

SG@

SG@

0.022U_0402_16V7K

0.022U_0402_16V7K
C838

C837

1

1

2

2

SG@

SG@

1U_0402_6.3V4Z

C850

1

2

SG@

PEX_SVDD_3V3

IFP A_IOVDD
IFPB_IOVDD
IFP C_IOVDD
IFPDE_IO VDD

IFPAB_PLLVDD
IFPC_PLLVDD
IFPD_PLLVDD
IFPE_PLLVDD

SG@

L44

1 2

SG@

L42

1 2

BLM18PG181SN1D_0603

4.7U_0603_6.3V6K

C902

1

2

2

U8D

J9

VDD

J10

VDD

J12

VDD

J13

VDD

L9

VDD

M9

VDD

M11

VDD

M17

VDD

N9

VDD

N11

VDD

N12

VDD

N13

VDD

N14

VDD

N15

VDD

N16

VDD

N17

VDD

N19

VDD

P11

VDD

P12

VDD

P13

VDD

P14

VDD

P15

VDD

P16

VDD

P17

VDD

R9

VDD

R11

VDD

R12

VDD

R13

VDD

R14

VDD

R15

VDD

R16

VDD

R17

VDD

T9

VDD

T11

VDD

T17

VDD

U9

VDD

U19

VDD

W9

VDD

W10

VDD

W12

VDD

W13

VDD

W18

VDD

W19

VDD

A12

VDD33

B12

VDD33

C12

VDD33

D12

VDD33

E12

VDD33

F12

VDD33

AG9

PEX_SVDD_3V3

V3

IFPA_IOVDD

V2

IFPB_IOVDD

J6

IFP C_ IOVDD

H6

IFPDE_IOVDD

AD5

IFPAB_PLLVDD

P6

IFPC_PLLVDD

N6

IFPD_PLLVDD

D7

IFPE_PLLVDD

N10M-GLM-S-A1_BGA533

SG@

100mA

1U_0603_10V6K

C876

C877

1

2

SG@

100mA

150mA

4.7U_0603_6.3V6K

C903

C904

1

2

SG@

0.1U_0402_10V6K

1

2

SG@

1U_0603_10V6K

1

2

SG@

3

Part 4 of 5

FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ

3.4A

FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ

PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ

POWER

PEX_IOVDDQ
PEX_IOVDDQ

1.8A

PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ

PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD

PEX_PLLVDD

VID_PLLVDD

SP_PLLVDD

PLLVDD
FB_PLLAVDD
FB_PLLAVDD

FB_DLLAVDD

DACA_VDD

120mA

DACB_VDD

FB_CAL_PD_VDDQ

VDD_SENSE
VDD_SENSE

0.1U_0402_10V6K

4.7U_0603_6.3V6K

C878

C891

1

1

2

2

SG@

SG@

IFP C_IOVDD PEX_PLLDVDD

0.1U_0402_10V6K

0.1U_0402_10V6K
C963

C905

1

1

2

2

SG@

SG@

A13
B13
C13
D13
D14
E13
F13
F14
F15
F16
F17
F19
F22
H23
H26
J15
J16
J18
J19
L19
L23
L26
M19
N22
U22
Y22

AG6
AF6
AE6
AD6
AC13
AC7
AB17
AB16
AB13
AB9
AB8
AB7

AG7
AF7
AE7
AD8
AD7
AC9

AF9
K6
L6
K5
R19
AC19
T19

AG2
W5

B15
W15
E15

IFPB_IOVDD

IFP A_IOVDD

+VDD_MEM

0.047U_0402_16V7K

C822

SG@

0.1U_0402_16V4Z

C839

1

2

SG@

Layout Note:Please
colse to Ball.

PEX_PLLDVDD
GPU_ P LLVDD

SP_PLLVDD

FB_ P L L AVDD

DACA_VDD
DACB_VDD

0.047U_0402_16V7K

0.047U_0402_16V7K

C823

0.01U_0402_16V7K

C824

C826

1

2

SG@

SG@

C840

1

2

SG@

SG@

0.1U_0402_16V4Z

R709 10K_0402_5%SG@

R710 40.2_0402_1%SG@
R744 0_0402_5%SG@
R711 0_0402_5%SG@

1U_0603_10V4Z

1U_0603_10V4Z

C842

C841

1

1

2

2

SG@

SG@

0.1U_0402_16V4Z
C853

C852

1

1

2

2

SG@

SG@

1 2

1 2
1 2
1 2

Security Classification

Issued Date

THIS SHE E T OF E NGIN EE RI NG DR A W ING I S THE P RO P RIE TAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

0.01U_0402_16V7K

C828

+PCIE

C844

1U_0603_10V4Z

1

2

SG@

10U_0805_6.3V6M

1

2

SG@

C855

4.7U_0603_6.3V6K

C829

1

2

SG@

+PCIE

600 mA

1U_0603_10V4Z

1

2

SG@

+VDD_MEM

+NVVDD_SENSE

10U_0805_6.3V6M

4.7U_0603_6.3V6K
C857

C856

1

1

2

2

SG@

SG@

1 2
1 2

to Pow er

SP_P LLVDD

2008/09/15 2009/12/31

Co m pa l Secret Data

BLM18PG181SN1D_0603

C1061

4.7U_0603_6.3V6K

C960

1U_0402_6.3V4Z

1

1

2

2

SG@

SG@

Lay out Note:Please
colse to Ball.

Deciphered Date

0.01U_0402_16V7K

C827

1

2

SG@

4.7U_0603_6.3V6K

C843

1

2

SG@

0.1U_0402_16V4Z
C854

1

2

SG@

4

SG@

R7040_0402_5%

SG@

R7060_0402_5%

SG@

L46

1 2

4

U8E

B2

GND

B5

GND

B8

GND

B11

GND

B14

GND

B17

GND

B20

GND

B23

GND

B26

GND

E2

GND

E5

GND

E8

GND

E11

GND

E17

GND

E20

GND

E23

GND

E26

GND

H2

GND

H5

GND

J11

GND

J14

GND

J17

GND

K9

GND

K19

GND

L2

GND

L5

GND

L11

GND

L12

GND

L13

GND

L14

GND

L15

GND

L16

GND

L17

GND

M12

GND

M13

GND

M14

GND

M15

GND

M16

GND

P2

GND

P5

GND

P9

GND

P19

GND

P23

GND

P26

GND

T12

GND

T13

GND

W16

GND_SENSE

E14

GND_SENSE

N10M-GLM-S-A1_BGA533

SG@

+PCIE

C894

1

2

SG@

Part 5 of 5

GND

FB_CAL_PU_GND

FB_CAL_TERM_GND
MULTI_STRAP_REF1_GND
MULTI_STRAP_REF0_GND

GPU_ P LLVDD

0.1U_0402_16V4Z

1U_0402_6.3V4Z

C895

1

2

SG@

5

U2

GND

U5

GND

U11

GND

U12

GND

U13

GND

U14

GND

U15

GND

U16

GND

U17

GND

U23

GND

U26

GND

V9

GND

V19

GND

W11

GND

W14

GND

W17

GND

Y2

GND

Y5

GND

Y23

GND

Y26

GND

AC2

GND

AC5

GND

AC6

GND

AC8

GND

AC11

GND

AC14

GND

AC17

GND

AC20

GND

AC23

GND

AC26

GND

AF2

GND

AF5

GND

AF8

GND

AF11

GND

AF14

GND

AF17

GND

AF20

GND

AF23

GND

AF26

GND

T16

GND

T15

GND

T14

GND

F6

GND

PEX_SVDD_3V3

FB_ P L L AVDD

135mA

C879

4.7U_0603_6.3V6M

C896

1

2

SG@

Title

Size D o cu ment Number Re v

Custom

Date: Sheet

R742 40.2_0402_1%SG@

A15
B16
F11
F10

SG@

1 2

R743 60.4_0402_1%SG@

1 2

R705 40.2K_0402_1%SG@

1 2

R707 40.2K_0402_1%SG@

1 2

SG@

R708 0_0402_5%

1 2

0.1U_0402_16V4Z

C862

1

2

10mA

1U_0402_6.3V4Z

4.7U_0603_6.3V6K
C867

C866

1

1

2

2

SG@

SG@

0.1U_0402_16V4Z

1

2

SG@

C897

4.7U_0603_6.3V6K

1

2

SG@

1U_0402_6.3V4Z

C880

1

2

SG@

110mA

1U_0402_6.3V4Z

C893

1

2

SG@

0.1U_0402_16V4Z

C881

C882

1

1

2

2

SG@

SG@

1 2

1U_0402_6.3V4Z

C964

1

10N H_MLG1608B10NJT_5%

1U_0402_6.3V4Z

2

SG@

Compal Electronics, Inc.

N10M(4)_Power/GND

Calp ell a DI S L A4 743P

5

+3VS_NV

SG@

L33

1 2

BLM18PG181SN1D_0603

Layout Note:Please
colse to BGA.

SG@

L37

1 2

BLM18PG181SN1D_0603

SG@

L40

Lay out Note:Please
colse to BGA.

27 49Monday, April 13, 2009

of

+PCIE

+PCIE

1U_0402_6.3V4Z

C898

1

2

SG@

0.1

1

2

3

4

5

VRAM DDR3 chips (512MB)

64Mx16 DDR3 700MHz*4==>512MB
Low 32 bit FB

10K_0402_5%

12

R714

SG@

MEM_VREF0

SG@

1

C908

0.01U_0402_16V7K

2

R715

SG@

MEM_VREF0

CMDA19
CMDA25
CMDA22
CMDA24
CMDA0
CMDA2
CMDA21
CMDA16
CMDA23
CMDA20
CMDA17
CMDA9
CMDA14
CMDA26

CMDA12
CMDA3
CMDA27

CL KA0
CL KA0#
CMDA18

CMDA30
CMDA29
CMDA1
CMDA10
CMDA11

DQSA2
DQSA1

DQMA2
DQMA1

DQSA#2
DQSA#1

CMDA15

ZQ0

243_0402_1%

12

A A

B B

C C

DQS A[7..0]<26,29>
DQSA#[7..0]<26,29>
DQM A[7..0]<26,29>
MDA[63..0]<26,29>
CMDA[30..0]<26,29>

DQS A [7..0 ]

DQS A#[7..0]
DQM A[7..0 ]
MDA [63..0 ]
CMDA [30..0]

CMDA15<26,29>

SG@

R719

1K_0402_1%

SG@

R721

1K_0402_1%

+VDD_MEM

12

12

Hyn i x : H 5 TQ1G63BF R-12C--> SA000032400
Samsu n g : K4 W1 G 1646E-H C12-->SA000035700

U11

M9

VREFCA

H2

VREFDQ

N4

A0

P8

A1

P4

A2

N3

A3

P9

A4

P3

A5

R9

A6

R3

A7

T9

A8

R4

A9

L8

A10/AP

R8

A11

N8

A12

T4

A13

T8

A14

M8

A15/BA3

M3

BA0

N9

BA1

M4

BA2

J8

CK

K8

CK

K10

CKE/CKE0

K2

ODT/OD T0

L3

CS

J4

RAS

K4

CAS

L4

WE

F4

DQSL

C8

DQSU

E8

DML

D4

DMU

G4

DQSL

B8

DQSU

T3

RESET

L9

ZQ/ZQ0

J2

NC/ODT1

L2

NC/CS1

J10

NC/CE1

L10

NCZQ1

A1

NC

A11

NC

T1

NC

T11

NC

K4B1 G 1646D-HCF8_FBGA100

VRAM@

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDDQ
VDDQ
VDDQ
VDDQ

310mA 310mA

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

100-BALL
SDRAM DDR3

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

MDA21

E4

MDA18

F8

MDA23

F3

MDA16

F9

MDA20

H4

MDA19

H9

MDA22

G3

MDA17

H8

MDA8

D8

MDA14

C4

MDA10

C9

MDA12

C3

MDA11

A8

MDA13

A3

MDA9

B9

MDA15

A4

+VDD_MEM

B3
D10
G8
K3
K9
N2
N10
R2
R10

+VDD_MEM

A2
A9
C2
C10
D3
E10
F2
H3
H10

A10

VSS

B4

VSS

E2

VSS

G9

VSS

J3

VSS

J9

VSS

M2

VSS

M10

VSS

P2

VSS

P10

VSS

T2

VSS

T10

VSS

B2
B10
D2
D9
E3
E9
F10
G2
G10

+VDD_MEM

CLKA0<26>

1 2

SG@

CL KA0#<26>

CL KA0

12

SG@

R718
121_0402_1%

C9060.01U_0402_16V7K

12

SG@

R722
121_0402_1%

CL KA0#

SG@

R717

1K_0402_1%

SG@

R720

1K_0402_1%

12

12

MEM_VREF1

SG@

1

C907

0.01U_0402_16V7K

2

MEM_VREF1

CMDA19
CMDA25
CMDA22
CMDA24
CMDA0
CMDA2
CMDA21
CMDA16
CMDA23
CMDA20
CMDA17
CMDA9
CMDA14
CMDA26

CMDA12
CMDA3
CMDA27

CL KA0
CL KA0#
CMDA18

CMDA30
CMDA29
CMDA1
CMDA10
CMDA11

DQSA0
DQSA3

DQMA0
DQMA3

DQSA#0
DQSA#3

CMDA15

R716

SG@

ZQ1

243_0402_1%

12

U12

M9

VREFCA

H2

VREFDQ

N4

A0

P8

A1

P4

A2

N3

A3

P9

A4

P3

A5

R9

A6

R3

A7

T9

A8

R4

A9

L8

A10/AP

R8

A11

N8

A12

T4

A13

T8

A14

M8

A15/BA3

M3

BA0

N9

BA1

M4

BA2

J8

CK

K8

CK

K10

CKE/CKE0

K2

ODT/OD T0

L3

CS

J4

RAS

K4

CAS

L4

WE

F4

DQSL

C8

DQSU

E8

DML

D4

DMU

G4

DQSL

B8

DQSU

T3

RESET

L9

ZQ/ZQ0

J2

NC/ODT1

L2

NC/CS1

J10

NC/CE1

L10

NCZQ1

A1

NC

A11

NC

T1

NC

T11

NC

100-BALL

SDRAM DDR3

K4B1 G 1646D-HCF8_FBGA100

VRAM@

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

Address

CMD0

CMD1

MDA5

E4

MDA1

F8

MDA6

F3

MDA2

F9

MDA4

H4

MDA0

H9

MDA7

G3

MDA3

H8

MDA26

D8

MDA30

C4

MDA28

C9

MDA29

C3

MDA27

A8

MDA25

A3

MDA24

B9

MDA31

A4

+VDD_MEM

B3
D10
G8
K3
K9
N2
N10
R2
R10

+VDD_MEM

A2
A9
C2
C10
D3
E10
F2
H3
H10

A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10

B2
B10
D2
D9
E3
E9
F10
G2
G10

CMD2

CMD3

CMD4

CMD5

CMD6

CMD7

CMD9

CMD10

CMD11

CMD12

CMD13

CMD14

CMD15

CMD16

CMD17

CMD18

CMD19

CMD20

CMD21

CMD22

CMD23

CMD24

CMD25

CMD26

CMD27

CMD28

CMD29

CMD30

DATA Bus

0..31

32..63

A4

RAS#

A5

BA1

A11

CAS#

WE#

BA0

A12

RST RST

A7

A10

CKE

A0

A9

A6

A2

A8

A3

A1

A13

BA2

CS#

LOW HIGH

RAS#

BA1

A2

A4

A3

CKE

CS#CMD8

A11

CAS#

WE#

BA0

A5

A12

A7

A10

A0

A9

A6

A8

A1

A13

BA2

ODT

+VDD_MEM

1U_0402_6.3V6K

C919

1

D D

1

2

SG@

DDR3 BGA MEMORY

1U_0402_6.3V6K

1U_0402_6.3V6K

C920

1

2

SG@

1U_0402_6.3V6K

C921

1

2

SG@

0.1U_0402_16V7K

C922

C923

1

1

2

2

SG@

SG@

http://laptop-motherboard-schematic.blogspot.com/

0.1U_0402_16V7K

0.1U_0402_16V7K
C925

C924

1

1

2

2

SG@

SG@

0.1U_0402_16V7K

0.1U_0402_16V7K

C926

1

2

SG@

2

0.1U_0402_16V7K

C927

C928

1

1

2

2

SG@

SG@

Security Classification

Issued Date

THIS SHE E T OF E NGIN EE RI NG DR A W ING I S THE P RO P RIE TAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+VDD_MEM

C909

1

2

SG@

DDR3 BGA MEMORY

1U_0402_6.3V6K

1U_0402_6.3V6K

C910

1

2

SG@

2008/09/15 2009/12/31

1U_0402_6.3V6K

C911

1

2

SG@

1U_0402_6.3V6K

C912

1

2

SG@

Co m pa l Secret Data

0.1U_0402_16V7K
C914

C913

1

2

SG@

Deciphered Date

1

2

SG@

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

C915

C916

1

1

2

2

SG@

SG@

4

0.1U_0402_16V7K

0.1U_0402_16V7K
C918

C917

1

1

2

2

SG@

SG@

Title

Size D o cu ment Number Re v

Date: Sheet

Compal Electronics, Inc.

VRAM DDR3

LA-4901P

Monday, April 13, 2009

5

0.1

of

28

49

1

VRAM DDR3 chips (512MB)

64Mx16 DDR3 700MHz*4==>512MB
High 32 bit FB

MEM_VREF2

CMDA19

R725

243_0402_1%

SG@

CMDA25
CMDA4
CMDA6
CMDA5
CMDA13
CMDA21
CMDA16
CMDA23
CMDA20
CMDA17
CMDA9
CMDA14
CMDA26

CMDA12
CMDA3
CMDA27

CL KA1
CL KA1#
CMDA7

CMDA28
CMDA8
CMDA1
CMDA10
CMDA11

DQSA4
DQSA7

DQMA4
DQMA7

DQSA#4
DQSA#7

CMDA15
ZQ2

12

A A

CMDA7<26>

CMDA28<26>

B B

C C

+VDD_MEM

SG@

R729

1K_0402_1%

SG@

R732

1K_0402_1%

12

12

MEM_VREF2

SG@

1

C931

0.01U_0402_16V7K

2

2

DQS A[7..0]<26,28>
DQSA#[7..0]<26,28>

DQM A[7..0]<26,28>

U13

M9

VREFCA

H2

VREFDQ

N4

A0

P8

A1

P4

A2

N3

A3

P9

A4

P3

A5

R9

A6

R3

A7

T9

A8

R4

A9

L8

A10/AP

R8

A11

N8

A12

T4

A13

T8

A14

M8

A15/BA3

M3

BA0

N9

BA1

M4

BA2

J8

CK

K8

CK

K10

CKE/CKE0

K2

ODT/OD T0

L3

CS

J4

RAS

K4

CAS

L4

WE

F4

DQSL

C8

DQSU

E8

DML

D4

DMU

G4

DQSL

B8

DQSU

T3

RESET

L9

ZQ/ZQ0

J2

NC/ODT1

L2

NC/CS1

J10

NC/CE1

L10

NCZQ1

A1

NC

A11

NC

T1

NC

T11

NC

K4B1 G 1646D-HCF8_FBGA100

VRAM@

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VDDQ
VDDQ
VDDQ
VDDQ

310mA 310mA

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

100-BALL
SDRAM DDR3

MDA39

E4

MDA36

F8

MDA37

F3

MDA34

F9

MDA38

H4

MDA33

H9

MDA35

G3

MDA32

H8

MDA61

D8

MDA60

C4

MDA59

C9

MDA62

C3

MDA58

A8

MDA63

A3

MDA57

B9

MDA56

A4

+VDD_MEM

B3
D10
G8
K3
K9
N2
N10
R2
R10

+VDD_MEM

A2
A9
C2
C10
D3
E10
F2
H3
H10

A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10

B2
B10
D2
D9
E3
E9
F10
G2
G10

CLKA1<26>

CLKA1#<26>

MDA[63 ..0]<26,28>
CMDA [30..0]<26,28>

SG@

C929 0.01U_0402_16V7K

1 2

3

12

12

DQS A [7..0 ]

DQS A#[7..0]
DQM A[7..0 ]
MDA [63..0 ]
CMDA[30..0]

CL KA1

SG@

R727
121_0402_1%

SG@

R731
121_0402_1%

CL KA1#

MEM_VREF3

R726

243_0402_1%

CMDA19
CMDA25
CMDA4
CMDA6
CMDA5
CMDA13
CMDA21
CMDA16
CMDA23
CMDA20
CMDA17
CMDA9
CMDA14
CMDA26

CMDA12
CMDA3
CMDA27

CL KA1
CL KA1#
CMDA7

CMDA28
CMDA8
CMDA1
CMDA10
CMDA11

DQSA5
DQSA6

DQMA5
DQMA6

DQSA#5
DQSA#6

CMDA15

ZQ3

12

SG@

4

U14

M9

VREFCA

H2

VREFDQ

N4

A0

P8

A1

P4

A2

N3

A3

P9

A4

P3

A5

R9

A6

R3

A7

T9

A8

R4

A9

L8

A10/AP

R8

A11

N8

A12

T4

A13

T8

A14

M8

A15/BA3

M3

BA0

N9

BA1

M4

BA2

J8

CK

K8

CK

K10

CKE/CKE0

K2

ODT/OD T0

L3

CS

J4

RAS

K4

CAS

L4

WE

F4

DQSL

C8

DQSU

E8

DML

D4

DMU

G4

DQSL

B8

DQSU

T3

RESET

L9

ZQ/ZQ0

J2

NC/ODT1

L2

NC/CS1

J10

NC/CE1

L10

NCZQ1

A1

NC

A11

NC

T1

NC

T11

NC

100-BALL

SDRAM DDR3

K4B1 G 1646D-HCF8_FBGA100

VRAM@

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

5

MDA41

E4

MDA46

F8

MDA40

F3

MDA45

F9

MDA42

H4

MDA47

H9

MDA44

G3

MDA43

H8

MDA48

D8

MDA53

C4

MDA50

C9

MDA52

C3

MDA51

A8

MDA54

A3

MDA49

B9

MDA55

A4

+VDD_MEM

B3
D10
G8
K3
K9
N2
N10
R2
R10

+VDD_MEM

A2
A9
C2
C10
D3
E10
F2
H3
H10

A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10

B2
B10
D2
D9
E3
E9
F10
G2
G10

+VDD_MEM

12

SG@

R728

1K_0402_1%

MEM_VREF3

12

SG@

R730

1K_0402_1%

SG@

1

C930

0.01U_0402_16V7K

2

+VDD_MEM +VDD_MEM

1U_0402_6.3V6K

C932

1

2

SG@

D D

1

DDR3 BGA MEMORY DDR3 BGA MEMORY

C933

1

2

SG@

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

C935

C934

1

1

2

2

SG@

SG@

http://laptop-motherboard-schematic.blogspot.com/

0.1U_0402_16V7K

0.1U_0402_16V7K

C936

1

2

SG@

0.1U_0402_16V7K

C937

C938

1

1

2

2

SG@

SG@

2

0.1U_0402_16V7K

0.1U_0402_16V7K

C939

1

2

SG@

0.1U_0402_16V7K

C940

C941

1

1

2

2

SG@

SG@

Security Classification

Issued Date

THIS SHE E T OF E NGIN EE RI NG D RA W ING I S THE P RO P RIE TAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1U_0402_6.3V6K

C942

1

2

SG@

2008/09/15 2009/12/31

1U_0402_6.3V6K

1U_0402_6.3V6K

C944

C943

1

1

2

2

SG@

SG@

0.1U_0402_16V7K

1U_0402_6.3V6K

C946

C945

1

1

2

2

SG@

SG@

Co m pa l Secret Data

Deciphered Date

C949

1

2

SG@

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

C950

C951

1

1

2

2

SG@

SG@

Title

Size Do c u ment Numbe r R e v

Date: Sheet

Compal Electronics, Inc.

VRAM DDR3

Cartier DIS

Monday, April 13, 2009

5

0.1

of

4929

0.1U_0402_16V7K

0.1U_0402_16V7K
C948

C947

1

1

2

2

SG@

SG@

4

5

D D

4

3

2

1

HDD Connector

JHDD

C C

24

GND

23

GND

OCTEK_SAT-22EH1G_RV

CONN@

CD- RO M Connec t o r

GND

GND

GND

GND
GND
GND

GND

Reserved

GND

1
2

A+

3

A-

4

SATA_RXN0

C466 0.01U_0402_16V7K

5

B-

B+

V33
V33
V33

V5
V5
V5

V12
V12
V12

SATA_RXP0 SATA_RXP0_C

6
7

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

+3VS

+5VS

12

C467 0.01U_0402_16V7K

12

Near CONN side.

SATA_TXP0
SATA_TXN0

SAT A_RXN0_C

SATA_TXP0 <11>

SATA_TXN0 <11>

SAT A_RXN0_C <11>

SAT A_RXP0_C <11>

Pleace near HDD CONN (JP3)

+5VS

1

C462

2

10U_0805_10V4Z

1

1

C463

2

2

0.1U_0402_16V4Z

ACCELEROMETER (ST)

D10

2 1

CH751H-4 0 P T_SOD323-2

1

C465

C464

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

VDDIO absolute man
rating is VDD+0.1

+3VS_ACL_IO

+3VS_ACL

+3VS_ACL+3VS +3VS_ACL_IO

1 2

U15

1

R366
0_0402_5%

1 2

2
3
4
5
6

Vdd_IO
GND
Reserved
GND
GND
Vdd

R364

0_0603_5%

SMB_CLK_S3

14

SCL / SPC

SDA / SDI / SDO

SDO

Reserved

GND
INT 2
INT 1

13
12
11
10
9
8

SMB_DATA_S3

R367

1 2

1

2

0_0402_5%

+3VS_ACL

1

C468

C469

2

0.1U_0402_16V4Z

10U_0805_6.3V6M

SMB_CLK_S3 <12,17,18,19>

0011101b

SMB_DATA_S3 <12,17,18,19>

ACCE L _ INT <14>

JODD

B B

SUYIN_127382FR013GX09ZR

CONN@

13

GND

12

A+

11

A-

10

GND

B-

B+

GND

DP

V5
V5

MD
GND
GND

SATA_RXN4

9

SATA_RXP4

8
7

6
5
4
3
2
1

C473 0.01U_0402_16V7K

12

C474 0.01U_0402_16V7K

12

Near CONN side.

+5VS

SATA_TXP4
SATA_TXN4

SAT A_RXN4_C
SAT A _RXP4_C

SATA_TXP4 <11>

SATA_TXN4 <11>

SAT A_RXN4_C <11>
SAT A_RXP4_C <11>

Placea caps. n ear ODD CONN.

+5VS

1

1

C475

2

0.1U_0402_16V4Z

1

C476

C477

2

2

1U_0603_10V4Z

R368

Must b e p l a c ed i n t he center of the system.

02/12 Change SM bus to VS

1

C478

2

10U_ 0805_10V4Z

10U_ 0805_10V4Z

ZZZ1

12

10K_0402_5%

CS

LIS302DLTR_LGA14_3x5

7

PCB-MB

A A

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEERING DRA WING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND T RADE SEC RET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D
DEP ARTMENT EXCE PT AS AUTHO RIZED BY COMPAL ELECTRONICS, IN C. NEITHER THIS SHEET NOR THE INFORMA T ION IT CONTAINS

5

http://laptop-motherboard-schematic.blogspot.com/

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/03/10

Compa l Secret Data

Dec iphered Date

Title

Size Document Number Re v

Custom

2

Date: Sheet

Compal Electronics, Inc.

HDD & CDROM

Cal p el la D I S L A4743P

1

0.1

of

30 49Monday, April 13, 2009

A

B

C

D

E

+3VALW +3VS_WWAN

0.01U_0402_16V7K

1

C515

1 1

2 2

2

0.1U_0402_16V4Z

+3VALW

WWAN_POWER_OFF<37>

SIM c ard C o nnector

UIM_PWR
UIM_DATA
UIM_CLK
UIM_RST
UIM_VPP

1

C516

2

0.1U_0402_16V4Z

R409

@

1 2

0_0603_5%

S

G

2

JSIM

6

6

G2

5

5

G1

4

4

3

3

2

2

1

1

ACES_87212-06G0

CONN@

4.7U_0805_10V4Z

1

C517

2

+3VS_WWAN

D

13

Q16

@

SI2301BDS_SOT23

8
7

1

C518

2

R410

1 2

0_1206_5%

UIM_PWR

+3VS

1 2

47K_0402_5%

1

C519
18P_0402_50V8J

2

+3VALW +1.5VS_WLAN

1

1

C509

2

2

0.1U_0402_16V4Z

R406

@

UIM_DATA

UIM_CLK

@

WL_LED# WW_ LE D#_R

XMIT_OFF# M_WXMIT_OFF#

UIM_PWR_R
UIM_DATA_R
UIM_CLK_R
UIM_RST_R
UIM_VPP_R

UIM_PWR_R
UIM_DATA_R
UIM_CLK_R
UIM_RST_R
UIM_VPP_R

R760 0_0402_5%
R761 0_0402_5%
R762 0_0402_5%
R763 0_0402_5%
R764 0_0402_5%

R765 0_0402_5%
R766 0_0402_5%
R767 0_0402_5%
R768 0_0402_5%
R769 0_0402_5%

R388

12

0_0805_5%

1

1

C512

2

0.01U_0402_16V7K

1

2

C513

0.1U_0402_16V4Z

+3VS_WLAN

C510

0.1U_0402_16V4Z

C514

2

4.7U_0805_10V4Z

R389

0_0805_5%

1

C511

2

4.7U_0805_10V4Z

For PR

1 2

R75 8 0_04 02_5%PR@

1 2

R75 9 0_04 02_5%PR@

1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2

LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

UIM_PWR
UIM_DATA
UIM_CLK
UIM_RST
UIM_VPP

Mini C ard S olt- -WLAN/WWAN

ICH_PCIE_WAKE#

+1.5VS

PCIE_RXN2<12>
PCIE_RXP2<12>

12

+3VS

PR@
PR@
PR@
PR@
PR@

PA@
PA@
PA@
PA@
PA@

CH_DATA<35>

CH_CLK<35>

CLKREQ_WLAN#<12>

CLK_PCIE_WLAN#<12>
CLK_PCIE_WLAN<12>

CLK_DEBUG_PORT_1<14>

R399 0_0402_5%

1 2

R401 0_0402_5%

1 2

PCIE_TXN2<12>

PCIE_TXP2<12>

CLK RE Q_WWAN#<12>

CLK_PCIE_WWAN#<12>
CLK _PCIE_WWA N<12>

PCIE_RXN1<12>
PCIE_RXP1<12>

PCIE_TXN1<12>

PCIE_TXP1<12>

+3VS_WWAN

CH_DATA
CH_CLK

CL K_P CIE _ M CA RD2 #
CL K_P CIE _ M CA RD2

PLT_RST#

PCIE_TXN2
PCIE_TXP2

+3VS_WLAN

ICH_PCIE_WAKE#
CH_DATA
CH_CLK

0_0402_5%

1 2
1 2

PCIE_C_RXN1
PCIE_C_RXP1

PCIE_TXN1
PCIE_TXP1

R403 0_0603_5%

1 2
1 2

R404 0_0603_5%

R395
R397 0_0402_5%

PCIE_C_RXN2
PCIE_C_RXP2

JMINIA

A1

WAKE#

A3

COEX1

A5

COEX2

A7

CLKREQ#

A9

GND

A11

REFCLK-

A13

REFCLK+

A15

GND

A17

Reserved

A19

Reserved

A21

GND

A23

PERn0

A25

PERp0

A27

GND

A29

GND

A31

PETn0

A33

PETp0

A35

GND

A37

GND

A39

+3.3Vaux

A41

+3.3Vaux

A43

GND

A45

Reserved

A47

Reserved

A49

Reserved

A51

Reserved

A53

GND

QUASA_CA0416-092N21

CONN@

JMINIB

B1

WAKE#

B3

COEX1

B5

COEX1

B7

CLKREQ#

GND

B11

REFCLK-

B13

REFCLK+

GND

B17

Reserved

B19

Reserved

GND

B23

PERn0

B25

PERp0

GND
GND

B31

PETn0

B33

PETp0

GND

B37

GND

B39

+3.3Vaux

B41

+3.3Vaux

B43

GND

B45

Reserved

B47

Reserved

B49

Reserved

B51

Reserved

QUASA_CA0416-092N21

CONN@

+3.3Vaux

GND

+1.5V

UIM_PWR

UIM_DATA

UIM_CLK

UIM_RESET

UIM_VPP

GND

W_DISABLE#

PERST#

+3.3Vaux

GND

+1.5V

SMB_CLK

SMB_DATA

GND

USB_D-

USB_D+

GND

LED_WWAN#

LED_WLAN#

LED_WPAN#

+1.5V

GND

+3.3Vaux

+3.3Vaux

+1.5V

UIM_PWR

UIM_DATA

UIM_CLK

UIM_RESET

UIM_VPP

W_DISABLE#

PERST#

+3.3Vaux

+1.5V

SMB_CLK

SMB_DATA

USB_D-

USB_D+

LED_WWAN#

LED_WLAN#

LED_WPAN#

+1.5V

+3.3Vaux

C977 47P_0402_50V8J@

A2
A6

A8
A10
A12
A14
A16

A20
A22
A24

A28
A30
A32

A36
A38

A42
A44
A46
A48

A52
A54

GND

B2
B4

GND

B6
B8
B10
B12
B14
B16
B18

GND

B20
B22
B24
B26

GND

B28
B30
B32
B34

GND

B36
B38
B40

GND

B42
B44
B46
B48
B50

GND

B52

1 2

+1.5VS_WLAN

XMIT_OFF#

D13

PLT_RST#

R400 0_0805_5%@
R402 0_0805_5%

SMBCLK

SMBDATA

2

C978

@

47P_0402_50V8J

1

C979 47P_0402_50V8J@

+1.5VS_WLAN

M_WXMIT_OFF#

PLT_RST#

SMBCLK

SMBDATA

+1.5VS_WLAN

1

2

2 1

1 2
1 2

USB20_N5 <14>
USB20_P5 <14>

WL_LED# <38>
+1.5VS_WLAN
+3VS_WLAN

1 2

UIM_PWR_R

UIM_DATA_R

UIM_CLK_R

UIM_RST_R

UIM_VPP_R

D12

1 2
1 2

USB20_N8 <14>
USB20_P8 <14>

WW_ LE D#_R

2 1

+1.5VS_WLAN

R396 0_0805_5%@
R398 0_0805_5%

+3VS_WWAN

C980
47P_0402_50V8J

@

+3VS_WLAN

LPC_FRAME# <11,36,37>
LPC_AD3 <11,36,37>
LPC_AD2 <11,36,37>
LPC_AD1 <11,36,37>
LPC_AD0 <11,36,37>

CH751H-40_SC76

+3VALW
+3VS_WLAN
+1.5VS_WLAN

+3VS_WWAN

CH751H-40_SC76

+3VALW
+3VS_WWAN

WW_LED# <38>

XMIT_OFF <14>

WXMIT _OFF# <14>

3 3

C520

1 2

C523 0.1U_0402_16V4Z

1 2

C524 0.1U_0402_16V4Z

+3VALW

PLT_RST#<6,14,32>

SYSON<37,38,39,48>
SUSP#<37,39,41,44,45>

+3VALW

4 4

internal pull high to 3.3Vaux-in
EC need setting at Hi-Z & output Low

A

1 2

PLT_RST#
SYSON
SUSP#

R414 100K_0402_5%@

1 2

EXP _CPPE#

New Card

Express Card Power Switch

0.1U_0402_16V4Z

+1.5VS

U19

12

+3VS

http://laptop-motherboard-schematic.blogspot.com/

1.5Vin

14

1.5Vin

2

3.3Vin

4

3.3Vin
AUX_IN17AUX_OU T

6

SYSRST#

20

SHDN#

1

STBY#

10

CPPE#

9

CPUSB#

18

RCLKEN

R5538D001-TR-F_QFN20_4X4~D

B

1.5Vout

1.5Vout

3.3Vout

3.3Vout

PERST#

GND

11
13

3
5

15
19

OC#

8
16

NC

7

PERST#

+1.5VS_PEC

+3VS_PEC

+3V_ PEC

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEERING DRA WING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND T RADE SEC RET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D
DEP ARTMENT EXCE PT AS AUTHO RIZED BY COMPAL ELECTRONICS, IN C. NEITHER THIS SHEET NOR THE INFORMA T ION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

ICH_PCIE_WAKE#<13,32>

2007/08/28 2006/07/26

C

USB20_N9<14>
USB20_P9<14>

SMBCLK<12>

SMBDATA<12>

1 2

CLKRE Q _EXP#<12>

PCIE_RXN4<12>

PCIE_RXP4<12>
PCIE_TXN4<12>

PCIE_TXP4<12>

+1.5VS_PEC

+3V_ PEC

+3VS_PEC

330P_0402_50V7K

R413 0_0402_5%

CLK_ PCIE_EXP#<12>
CLK_PCIE_EXP<12>

Compa l Secret Data

Dec iphered Date

EXP _CPPE#

SMBCLK
SMBDATA

PCIE_PME#_R
PERST#

EXP _CPPE#

C527

@

D

1

2

JEXP

1

GND

2

USB_D-

3

USB_D+

4

CPUSB#

5

RSV

6

RSV

7

SMB_CLK

8

SMB_DATA

9

+1.5V

10

+1.5V

11

WAKE#

12

+3.3VAUX

13

PERST#

14

+3.3V

15

+3.3V

16

CLKREQ#

17

CPPE#

18

REFCLK-

19

REFCLK+

20

GND

21

PERn0

22

PERp0

23

GND

24

PETn0

25

PETp0

26

GND

27

GND

28

GND

SANTA_130801-5_RT

CONN@

Title

Size Document Number Re v

Date: Sheet

Near to Express Card slot.

+3VS_PEC

1

C521

0.1U_0402_16V4Z

C525

0.1U_0402_16V4Z

C528

0.1U_0402_16V4Z

+1.5VS_PEC

+3V_PEC

1

2

2

1

1

2

2

1

1

2

2

Compal Electronics, Inc.

WLAN, WWAN, New Card

Cal p el la D I S L A4743P

31 49Monday, April 13, 2009

E

C522

4.7U_0805_10V4Z

C526

4.7U_0805_10V4Z

C529

4.7U_0805_10V4Z

of

0.1

5

+DVDD

D D

4.7 UH_1008HC-472EJFS-A_5%_1008

L2

1 2

Close to Pin8.

+VDD33

CR_WAKE#<14>

C C

27P_0402_50V8J

B B

A A

1

1

C1035

2

2

C1034

10U_0805_6.3V6M

0.1U_0402_16V4Z

D41 C H 751H-40PT_SOD323-2

LAN_X1

1

C1043

1

2

2

+VCC _4IN1 +VCC_4IN1

MDIO0
MDIO1
MDIO2
MDIO3
MDIO8

MDIO9
MDIO10
MDIO11

MDIO4

MDIO6
MDIO14

XD_CD

MDIO13
MDIO12

MDI O5_R

MDIO7

+DVDD12

2

1

1

2

C1020

C1019

C1018

0.1U_0402_16V4Z

0.1U_0402_16V4Z

10U_0805_6.3V6M

CLK_PCIE_LAN#<12>

CLK_PCIE_LAN<12>

PCI E_TXP3<12 >

PCIE_TXN3<12>

PCIE_RXN3<12>
PCI E_RXP3<12>

21

C481 0.1U_0402_16V7K
C479 0.1U_0402_16V7K

PL T_ R ST#<6,14,31>

IC H _ P CI E _W AKE#<13,31>

+VCC _4IN1

CLKREQ_LAN#<12>

2

1

C1040

1

C1044
27P_0402_50V8J

2

0.1U_0402_16V4Z

LAN_X2

3

IN

OUT

Y4

NC

NC

4

25MHZ_16PF_X3S025000FG1H-HX

Car d Read e r Connector

JREAD1

3

XD-VCC

32

XD-D0

10

9
8
7
6
5
4

34
33
35
40
39
38
37
36

11
31

41
42

7 IN 1 CONN

XD-D1
XD-D2
XD-D3
XD-D4
XD-D5
XD-D6
XD-D7

XD-WE
XD-WP
XD-ALE
XD-CD
XD-R/B
XD-RE
XD-CE
XD-CLE

7IN1 GND
7IN1 GND

7IN1 GND
7IN1 GND

TAITW_R015-B10-LM

CONN@

2

2

1

1

C1021

0.1U_0402_16V4Z

12
12

SD-CD-SW

SD-WP-SW

MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3

2

2

1

1

C1023

C1022

0.1U_0402_16V4Z

0.1U_0402_16V4Z

R819 12K_0402_1%

SD-DAT0
SD-DAT1
SD-DAT2
SD-DAT3
SD-DAT4
SD-DAT5
SD-DAT6
SD-DAT7

MS-SCLK

12

+VDD33

LAN_X1
LAN_X2

+DVDD

+DVDD12

+VDD33

PCIE_PTX_IRX_N3
PCIE_PTX_IRX_P3

+DVDD12

MPD
CLKREQ_LAN#

CR_CD0N

+DVDD12

+VDD33 +VDD33

CR_LED#

MDIO14
MDIO13

21

SD-VCC

28

MS-VCC
SD_CLK

SD-CMD

MS-INS

MS-BS

20
14
12
30
29
27
23
18
16
25
1

2

26
17
15
19
24
22
13

MDIO5_R
MDIO0
MDIO1
MDIO2
MDIO3
MDIO8
MDIO9
MDIO10
MDIO11
MDIO4

CR_CD0N

MDIO6

MDIO5_R
MDIO0
MDIO1
MDIO2
MDIO3

CR_CD1N

MDIO4

4

+3V_LAN

U46

1

REXT

2

VDDX33

3

XIN

4

XOUT

5

GND

6

LX

7

FB12

8

VDDREG

9

CLKN

10

CLKP

11

AVDDH

12

RXP

13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

JMC261

RXN
GND

(LQFP 64)

TXN
TXP
AVDDX
RSTN
WAKEN
MPD
CREQN
SMB_SCL/LED2
CR_CD1N
CR_CD0N
VCC3O
VDD
VDDIO
TESTN
SMB_SDA/CR_LEDN
MDIO14
MDIO13
GND

JMC261-LGBZ0A_LQFP64_7X7

JMC251 SA000039X

JMC261 SA000037N

1

C1062

2

10U_0805_6.3V6M

R817

1 2

0_0805_5%

Κ

Κ

+VDD33

2

2

1

1

C1028

C1029

0.1U_0402_16V4Z

0.1U_0402_16V4Z

LAN_MDI3­LAN_MDI3+

LAN_MDI2­LAN_MDI2+

LAN_MDI1­LAN_MDI1+

LAN_MDI0­LAN_MDI0+

LAN_LINK#
LAN_ACT#
MDIO0
MDIO1
MDIO2

MDIO3
MDIO4

R333 22_0402_5%

MDIO5
MDIO6

MDIO7
MDIO8

MDIO9
MDIO10
MDIO11
MDIO12

C1030

0.1U_0402_16V4Z

+DVDD12

+DVDD12

+DVDD12

1 2

C1025

1

2

10U_0805_6.3V6M

AVDD33

VIN_2
VIP_2

AVDD12

VIN_1
VIP_1

LED1

LED0
MDIO0
MDIO1
MDIO2
VDDIO
MDIO3
MDIO4
MDIO5

MDIO6
MDIO7
VDDIO

MDIO8

MDIO9

MDIO10
MDIO11
MDIO12

GND

GND
VDD

GND

2

2

1

1

C1026

C1027

0.1U_0402_16V4Z

0.1U_0402_16V4Z

64

NC

63

NC

62

NC

61

NC

60

NC

59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

00

00

D3E support

PL T_RST# MPD

R926 0_0402_5%

1 2

C1086

@

R382 0_0402_5%

LAN_POWER_OFF<37>

1 2

2

1

+VDD33

+VDD33

3

2

LAN_ACT#

LAN_LINK#

0.1U_0402_16V4Z

C482

0.1U_0402_16V4Z

C480

1

2

2

1

R369
300_0402_5%

R371
300_0402_5%

12

12

+3V_LAN

LANLED_ACT#
RJ4 5_MIDI3­RJ4 5_MIDI3+
RJ4 5_MIDI1­RJ4 5_MIDI2­RJ4 5_MIDI2+
RJ4 5_MIDI1+
RJ4 5_MIDI0­RJ4 5_MIDI0+

+3V_LAN

LANL E D_LINK#

LA N Conn.

JRJ45

13

Yellow LED+

14

Yellow LED-

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

11

Green LED+

12

Green LED-

FOX_JM36113-P1122-7F

CONN@

1

C483

0.1U_0402_16V4Z

2

1

SHLD1

DETECT P IN1

DETCET PIN2

SHLD1

1

C484

4.7U_0805_10V4Z

2

16
9

10
15

LANGND

10/100 and Giga T ran sformer Co lay

MDI O5_RCR_CD1N

C1042 0.1U_0402_16V4Z

1 2

1.For Giga LAN (RTL8111DL):
Mail source: LANKom: LG-2446S-1 (P/N: SP050005L00)
2nd Source: MHPC: NS892406 (P/N: SP050005900)

2.For 10/100M (RTL 8103EL):
Main Source: MHPC NS892404 (P/N: SP050003P00)

R925 0_0402_5%@
R927 0_0402_5%@

2

12
12

+VDD33
+3VS

LAN_MDI0+
LAN_MDI0-

LAN_MDI1+
LAN_MDI1-

LAN_MDI2+
LAN_MDI2-

LAN_MDI3+
LAN_MDI3-

1

0.1U_0402_16V4Z

R823 0_0805_5%@

1 2

S

2

G

2

1

Q15

SI2301BDS-T1-E3_SOT23-3

C485

@

0.1U_0402_16V4Z

40 mils

D

13

+3V_LAN

4.7K_0402_5%

R824

@

+3VALW

1 2

100K_0402_5%

R825

CR_CD1N
CR_CD0N

U17

1

TCT1

MCT1

2

TD1+

MX1+

3

TD1-

MX1-

4

TCT2

MCT2

5

TD2+

MX2+

TD2-6MX2-

7

TCT3

MCT3

8

TD3+

MX3+

9

TD3-

MX3-

10

TCT4

MCT4

11

TD4+

MX4+

12

TD4-

MX4-

SUPER WO R LD_SWG150401

+VDD33

12

12

R826

4.7K_0402_5%

D39

2
3

DAN2 02U_SC70

C1041 1000P_0402_50V7K

24
23
22

21
20
19

18
17
16

15
14
13

1

12

C1039 1000P_0402_50V7K

12

C1085 1000P_0402_50V7K

12

C1083 1000P_0402_50V7K

12

XD_CD

1

C1047
270P_0402_25V7

2

R822 75_0402_1%

RJ4 5_MIDI0+
RJ4 5_MIDI0-

R821 75_0402_1%

RJ4 5_MIDI1+
RJ4 5_MIDI1-

R923 75_0402_1%

RJ4 5_MIDI2+
RJ4 5_MIDI2-

R922 75_0402_1%

RJ4 5_MIDI3+
RJ4 5_MIDI3-

R828 1.2K_0402_5%

1 2

+5VS

+VCC _4IN1

1 2

1 2

1 2

8111DL@

1 2

8111DL@

C1045

1000P_1206_2KV7K

D40

2 1

HT- 1 1 0TW_W H I TE

White

R829 10K_0402_5%

1 2

R830 10K_0402_5%

1 2

R831 1K_0402_5%

1 2

RJ45_GND

1

2

CR_LED#

MDIO4
MDIO6
MDIO13

Security Classification

Issued Date

THIS SHE E T OF E NGIN EE RI NG DR A W ING I S THE P RO P RIE TAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/10/06

Co m pa l Secret Data

Deciphered Date

2

Title

Size D o cu ment Number Re v

Custom

Date: Sheet of

Compal Electronics, Inc.

USB CardReader&CONN

Calp ell a DI S L A4 743P

1

32 49Monday, April 13, 2009

0.1

http://laptop-motherboard-schematic.blogspot.com/

A

B

C

D

E

R430

12

0_0402_5%

R432

4.7K_0402_5%

MIC_EXT_R
MIC_EXT_L

+A V DD_ CODE C

HP_DET# <34>
EXT MIC_DET# <34>

C1070 0.1U_0402_16V4Z

1 2

EC_BEEP <37>

2N7002_SOT23-3

12

C545

12

1U_0603_10V4Z

R433

4.7K_0402_5%

+A V DD _ CO DE C

D

Q38

S

1 2

R909

10K_0402_5%

1 2

13

2

G

SB_ SPKR

+V REFOUT_INTMIC

SB_ SPKR <11>

1 2
1 2
1 2

1 2

HP_OUTL <34>
HP_OUTR <34>

MIC_EXT_L <34>
MIC_E XT_R <34>

SPKL+ <34>
SPKL- <34>

SPKR- <34>
SPKR+ <34>

MIC_IN _ L <34>
MIC_IN_R <34>

+VREF OUT _ E XTMIC

HP Jack
Ext MIC

Internal SPKR

Int MI C

12

12

+3VS

R437

BLM18B D601S N1D_0603

C551

HDA _BIT CL K _CODEC<11>
HDA _S DIN0<11>

HDA _S DOUT_CODEC<11>
HDA_SY NC_CODEC<11>
HDA_RST#_CODEC<11,37>

+3VS_HDA

1

2

0.1U_0402_16V4Z
33P_0402_50V8K

DMIC_CLK<21>

DMIC_DAT<21>

C554

@

EAPD_CODEC<37>

+3VS

R907 0_0603_5%

1 2

1 1

2 2

+3V S _ DV DD

12

1

1

C553

C976

2

2

0.1U_0402_16V4Z
1U_0402_6.3V6K

C1065 10U_0805_10V4Z

12

R441

@

12

EC_MUTE#<37>

12

47_040 2_5%

+3VS

HDA _BITCLK_CODEC

R444

HDA_SDIN0_CODEC

1 2

33_0402_5%

HDA _S DOUT_CODEC
HDA_SYNC_CODEC
HDA_RST#_CODEC

R679 33_0402_5%

1 2

R446 0_0603_5%

1 2

R910 0_0402_5%@

1 2

R908 10K_0402_5%

1 2

EC_MUTE#

4.7U_0603_6.3V6M

C1069

2

1

U22

1

DVDD_CORE

9

DVDD

3

DVDD_IO

6

HDA_BITCLK

8

HDA_SDI

5

HDA_SDO

10

HDA_SYNC

11

HDA_RST#

2

DMIC_CLK/GPIO1

4

DMIC0/GPIO2

46

DMIC1/GPIO0/SPDIF_OUT_1

48

SPDIF_OUT_0

47

EAPD

35

CAP-

36

CAP+

7

DVSS

33

AVSS

30

AVSS

26

AVSS

42

PVSS

49

DAP

92HD 8 1B1 X5N L GXB1X8_QFN48_7X7~D

HP0_POR T_A_L
HP0_POR T_A_R

VREFOU T_A_or_F

HP1_POR T_B_L
HP1_POR T_B_R

VREFOU T_C

SPKR_POR T_D_L+

SPKR_POR T_D_L­SPKR_POR T_D_R -

SPKR_POR T_D_R +

MONO_OUT

+A V DD _ CO DE C +5VS

R904 0_0805_5%

1

1

C1064

C1063

2

2

27

AVDD
AVDD

PVDD
PVDD

SENSE_A
SENSE_B

PORT _C_L
PORT _C_R

PORT _E_L
PORT _E_R

PORT _F_L

PORT _F_R

PC_BEEP

CAP2

VREFFILT

VREG

38
39

45
13

R442 100K_ 0 402_5%

14

C555 1000P _ 0402_50V7K@

28
29

+V REFOUT_INTMIC

23

HP_OUTL

31

HP_OUTR

32

MIC_EXTL

19

MIC_EXTR

20
24

SPKL+

40

SPKL-

41

SPKR-

43

SPKR+

44
15

16

MIC_INL

17

MIC_INR MIC_IN_R

18

MONO_INR MONO_IN

12
25

22
21
34

V-

37

2

1

C1072

C1071

4.7U_0603_6.3V6M

1U_0402_6.3V6K

0.1U_0402_16V4Z

SENSEA

12

1 2

C557 2.2U_0603_6.3V4Z

1 2

C558 2.2U_0603_6.3V4Z

1 2

+VREF OUT _ E XTMIC

C559 2.2U_0603_6.3V4Z

1 2

C560 2.2U_0603_6.3V4Z

1 2

C561 0.1U_0402_16V4Z

12

1

2

10U_0805_10V4Z

2

C563

1 2

C564

1

1U_0603_10V6K

10U_0805_10V4Z

1

2

12

1

C1066

2

0.1U_0402_16V4Z

+A V DD_ CODE C

C1067

1U_0402_6.3V6K

MIC_EXT_L
MIC_EXT_R

C562

0.1U_0402_16V4Z

1

C1068

2

R43 8 2.5K_0402_1%
R439 39.2K_0402_1%

10U_0805_10V4Z

R440 20K_0402_1%
C556 1000P_0402_50V7K

MIC_IN_L

R447 47K_0402_5%

R448 47K_0402_5%@

2

R449

1

10K_0402_5%

1 2

R431

1K_0402_5%

4.7K_0402_5%

MIC_IN_R
MIC_IN_L

12

R434

12

C546

12

1U_0603_10V4Z

R435

4.7K_0402_5%

1 2

3 3

C983 1000P_0402_50V7K@

MDC 1.5 Conn.

HDA_SDOUT_MDC<11>

H9
HOLEA

1

HDA_SY NC_MDC<11>

HDA_SDIN1<11>

HDA_RST#_MDC<11>

H10
HOLEA

1

R452 33_0402_5%

1 2

HDA _ S DOUT_MDC
HDA_SY NC_MDC

HDA _S DIN1_ MDC

JP8

1

GND1

3

IAC_SDATA_OUT

5

GND2

7

IAC_SYNC

9

IAC_SDATA_IN

11

IAC_RESET#

Connector for MDC Rev1.5

CONN@

IAC_BITCLK

GND13GND14GND15GND16GND17GND

ACES_88018-124G

18

RES0
RES1

3.3V
GND3
GND4

R450 0_0603_5%

1 2

2
4
6
8
10
12

R453

@

10_0402_5%

+3VS

HDA_BITCLK_MDC <11>

C568

@

12

10P_0402_25V8K

+3VS

1 2

+3VS

1

1

C566

C565

2

2

0.1U_0402_16V4Z

1000P_0402_50V7K

1 2

C984 1000P_0402_50V7K@

1 2

C985 1000P_0402_50V7K@

1 2

C986 1000P_0402_50V7K@

1 2

R754 0_0603_5%

1 2

R132 0_0603_5%@

1 2

R135 0_0603_5%@

1 2

R139 0_0603_5%@

1 2

GNDA <34>

GNDAGND

MDC Standoff

4 4

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEERING DRA WING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND T RADE SEC RET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D
DEP ARTMENT EXCE PT AS AUTHO RIZED BY COMPAL ELECTRONICS, IN C. NEITHER THIS SHEET NOR THE INFORMA T ION IT CONTAINS

A

http://laptop-motherboard-schematic.blogspot.com/

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/28 2006/07/26

Compa l Secret Data

Dec iphered Date

Title

Size Document Number Re v

Custom

D

Date: Sheet

Codec_IDT9271B7

Calpella DIS LA4743P

E

0.1

of

33 49Monday, April 13, 2009

A

B

C

D

E

SPEAKER

MIC_IN_L<33>

MIC_IN_R<33>

PSOT24C_SOT23-3

R469

0_0402_5%

SPKR-

R45 4 0 _ 0603_5%

SPKR-<33>
SPKR+<33>
SPKL-<33>

1 1

SPKL+<33>

SPKR+
SPKL­SPKL+

1 2

R45 5 0 _ 0603_5%

1 2

R45 6 0 _ 0603_5%

1 2

R45 7 0 _ 0603_5%

1 2

1

1

2

2

3

1

2

D15
PSOT24C_SOT23-3

C569

330P_0402_50V7K

1

C571

C570

2

330P_0402_50V7K

330P_0402_50V7K

2

3

1

SPK_R­SPK_R+
SPK_L­SPK_L+

1

C572

2

330P_0402_50V7K

D16
PSOT24C_SOT23-3

JSPK1

1

1

2

2

3

3

4

4

5

GND1

6

GND2

E&T_3806-F04N-02R

CONN@

1

D17

2

12

3

INTMIC IN

CONN@

JP10

1

1

2

2

3

GND

4

GND

ACES_8 8 231-02001

Audio connector

JAUDIO

1

MIC_EXT_R<33>

2 2

Add JSPK2 for PA

SPK_L­SPK_L+

CONN@

JSPK2

1

1

2

2

3

GND

4

GND

ACES_88231-02001

MIC_EXT_L<33>

HP_OUTL<33>
HP_OUTR<33>

EXTMIC_DET#<33>

HP_DET#<33>

MIC_EXT_R
MIC_EXT_L

HP_OUTL
HP_OUTR

EXTMIC_DET#
HP_DET#

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

GND1

12

GND2

ACES_87213-1000G

CONN@

Consumer IR

3 3

CIR_IN<37>

4.7U_0805_10V4Z

4 4

A

http://laptop-motherboard-schematic.blogspot.com/

B

+5VL

12

R476
100_0805_5%

CIR_IN

C597

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEERING DRA WING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND T RADE SEC RET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D
DEP ARTMENT EXCE PT AS AUTHO RIZED BY COMPAL ELECTRONICS, IN C. NEITHER THIS SHEET NOR THE INFORMA T ION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

IR1

1

Vout

2

VCC

3

GND

4

GND

IRM-V536 /TR1_3P

2007/08/28 2006/07/26

Compa l Secret Data

Dec iphered Date

D

Title

Size Document Number Re v

Custom

Date: Sheet

AMP & Audio Jack

Calpella DIS LA4743P

E

of

34 49Monday, April 13, 2009

0.1

5

4

3

2

1

Right side USB Power Switch Right side ESATA/USB combination Connector

+5VALW

U24

1

GND

2

D D

C599

USB_EN#

1

2

4.7U_0805_10V4Z

IN

3

IN

4

EN#

TPS2061IDGNR_MSOP8

8

OUT
OUT
OUT
OC#

W=100mils

7
6
5

1

+

C598

2

150U_B_6.3VM_R40M

R481 10K_0402_5%

1

C600

2

0.1U_0402_16V4Z

1 2

+USB_VCCC

1

C601

2

1000P_0402_50V7K

+5VALW

+US B_V CCC

R479 0_0402_5%

USB20_N2<14>
USB20_P2<14>

SATA_TXP2<11>
SATA_TXN2<11>

SATA_RXN2_C<11>
SAT A _RXP2_C<11>

1 2

R480 0_0402_5%

1 2

C602 0.01U_0402_16V7K

12

C603 0.01U_0402_16V7K

12

USB20_N2_R
USB20_P2_R

SATA_TXP2
SATA_TXN2

SATA_RXN2
SATA_RXP2

JESATA

1

VBUS

2

D-

3

D+

4

GND

5

GND

6

A+

7

A-

8

GND

9

B-

10

B+

11

GND

12

GND

13

GND

14

GND

15

GND

TYCO_1759576-1

CONN@

USB

ESATA

D20

+5VALW

Finger printer

C C

B B

+3VS

R483
0_0603_5%

1 2

+3VS_FP

1

C604

0.1U_0402_16V4Z

2

+5VALW

USB20_N7<14>
USB20_P7<14>

USB20_N7_R

R484 0_0402_5%

1 2

R485 0_0402_5%

1 2

D22

4
3

2

IO1

VIN

1

GND

IO2

PRTR5V0U2X_SOT143-4

USB20_P7_R

USB cable connector for Left side

JUSB

+5VALW

USB_EN#<37>

USB20_N0<14>
USB20_P0<14>

USB20_N1<14>
USB20_P1<14>

USB_EN#

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

GND1

12

GND2

ACES_87213-1000G

CONN@

USB20_N7_R
USB20_P7_R

CONN@

JFPR

1

1

2

2

3

3

4

4

5

GND

6

GND

P-TWO_161011-04021

BT C onnector

JBT

9

GND

10

GND

ACES_87213-0800G

CONN@

R491

1 2

+3VS

0_0603_5%

BT_OFF<14>

4
3

PRTR5V0U2X_SOT143-4

1
2

USB20_P6_R

3

USB20_N6_R

4
5

R489 1K_0402_5%@

6

R490 1K_0402_5%@

7
8

1

C605

2

1U_0603_10V4Z

1 2

VIN
IO2

USB20_N2

1
2
3
4
5
6
7
8

R494 10K_0402_5%

USB20_P2

2

IO1

1

GND

R487 0_0402_5%
R488 0_0402_5%

1 2
1 2

Q20 SI2301BDS_SOT23

S

G

12

R493
100K_0402_5%

2

C609 0.1U_0402_16V4Z

+5VALW

SATA_TXN2

Need change to New version

USB20_N6_R

0.1U_0402_16V4Z

1

C606

2

+3VAUX_BT

D23

4
3

PRTR5V0U2X_SOT143-4

+3VAUX_BT

1

C607

2

4.7U_0805_10V4Z

12
12

+5VALW

D

13

0.01U_0402_16V7K

1 2

4
3

USB20_P6 <14>
USB20_N6 <14>
BT_LED <38>
CH_ DATA <31>

CH_CLK <31>

2

IO1

VIN

1

GND

IO2

10/08 ESD request

1

C608

2

D21

VIN
IO2

PRT R5V0 U2X_SOT143-4

SATA_TXP2

2

IO1

1

GND

10/08 ESD request

USB20_P6_R

A A

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEERING DRA WING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND T RADE SEC RET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D
DEP ARTMENT EXCE PT AS AUTHO RIZED BY COMPAL ELECTRONICS, IN C. NEITHER THIS SHEET NOR THE INFORMA T ION IT CONTAINS

5

http://laptop-motherboard-schematic.blogspot.com/

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/07/26

Compa l Secret Data

Dec iphered Date

Title

Size Document Number Re v

2

Date: Sheet

Compal Electronics, Inc.

USB, BT, eSATA

Cal p el la D I S L A4743P

35 49Monday, April 13, 2009

1

0.1

of

5

4

3

2

1

D D

0.1U_0402_16V4Z

FSEL#<37>
SPI_CLK<37>

C C

R495 10_0402_5%
R496 10_0402_5%
R497 10_0402_5%

SPI ROM on PCH => 4M (ME code + System BIOS)

+3VS

1 2

1 2

SPI_SI<11>

SPI_WP#

3.3K_0402_5%

SPI_HOLD#

3.3K_0402_5%

SPI_SB_CS#
SPI_CLK_PCH

SPI_SI

R661

1 2

15_0402_5%

R658

R659

SPI_SB_CS#<11>

SPI_CLK_PCH<11>

B B

SPI ROM => 1M (EC code)

+3VL

20mils

1

C610

2

+3VS

1 2

SPI_FSEL#
SPI_CLK_R

ΚΚΚΚ

ΚΚΚΚ

ΚΚΚΚ

ΚΚΚΚ

0.1U_0402_16V4Z

R660

@

1K_0402_5%

1 2
1 2
1 2

SP07000F500 S SOCKET WIESON G6179-100000 8P SPIFLASH
WIESO_G6179-100000_8P

SA00000XT00 S IC FL 8M
SA00001AW00 S IC FL 16M MX25L
SA000021A00 S IC FL 32M
SA000031Q00 S IC

U25

8

VCC

3

W

7

HOLD

1

S

6

C

5

D

WIESON G6179 8P SPI

4

VSS

SPI_SOSPI_FWR#

2

Q

MX25L8005M2C-15G SOP 8P (MXIC)

1605AM2C-15G SOP 8P SPI (MXIC)

MX25L3205DM2I-12G SOP 8P (MXIC)

FL 32M AT25DF321-SU SOIC 8P (ATMEL)

+3VS

1

C773

2

U31

8

SPI_WP#
SPI_HOLD#

VCC

3

W

7

HOLD

1

S

6

C

5

D

WIESON G6179 8P SPI

1 2

R498 0_0402_5%

4

VSS

2

Q

&U25

MX25L8005M2C-15G SOP 8P

45@

FRD#

SPI_CLK_R

FRD# <37>FWR#<37>

R233

1 2

10_0402_5%

091 9 E M I r e q uest

&U31

32M AT25DF321-SU SOIC 8P

45@

R662

1 2

15_0402_5%

SPI_SO_RSPI_SO_L

C391

1 2

6P_0402_50V8D

SPI_SO_R <11>

LPC Debug Port

CLK_DEBUG_PORT_0<14>

LPC_FRAME#<11,31,37>

PCI_RST#<14,37>

LPC_AD0<11,31,37>
LPC_AD1<11,31,37>
LPC_AD2<11,31,37>
LPC_AD3<11,31,37>

ON/OFFBTNLED#

VCC1P WRGD

Connect pin3 & 23
toge ther and pin 24
to GND in 6/ 29.

+3VALW

R504

1 2

ON/OFF B TN_LED#<37,38>

VCC1_PWRGD<37>

SPI_CLK_JP18
SPI_CS#_JP18
SPI_SI_JP18
SPI_SO_JP18
SPI_HOLD#_0

SPI_CLK

FSEL#

FWR#

HOLD#

3.3K_0402_5%

FRD#

ON/OFFBTN_LED#

VCC1_ PWRGD

Change fro m +3VL to +3VS. 6/9
Removed +3VS. 6/13

B+

JP15

1

Ground

2

LPC_PCI_CLK

3

Ground

4

LPC_FRAME#

5

+V3S

6

LPC_RESET#

7

+V3S

8

LPC_AD0

9

LPC_AD1

10

LPC_AD2

11

LPC_AD3

12

VCC_3VA

13

PWR_LED#

14

CAPS_LED#

15

NUM _LED#

16

VCC1_PWRGD

17

SPI_CLK

18

SPI_CS#

19

SPI_SI

20

SPI_SO

21

SPI_HOLD#

22

Reserved

23

Reserved

24

Reserved

ACES_87216-2404_24P

CONN@

1 2

R501 0_0402_5%

DEBUG@

1 2

R502 0_0402_5%

DEBUG@

1 2

R503 0_0402_5%

DEBUG@

1 2

R505 0_0402_5%

DEBUG@

1 2

R506 0_0402_5%

DEBUG@

1 2

R507 0_0402_5%

DEBUG@

1 2

R508 0_0402_5%

DEBUG@

SPI_CLK_JP18

SPI_CS#_JP18

SPI_SI_JP18

SPI_HOLD#_0

SPI_SO_JP18

ON/OFFBTNLED#

VCC1P WRGD

11/07 Add 0 Ohm for debug port

A A

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEERING DRA WING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND T RADE SEC RET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D
DEP ARTMENT EXCE PT AS AUTHO RIZED BY COMPAL ELECTRONICS, IN C. NEITHER THIS SHEET NOR THE INFORMA T ION IT CONTAINS

5

http://laptop-motherboard-schematic.blogspot.com/

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/07/26

Compa l Secret Data

Dec iphered Date

Title

Size Document Number Re v

2

Date: Sheet

Compal Electronics, Inc.

BIOS ROM

Cal p el la D I S L A4743P

1

0.1

of

36 49Monday, April 13, 2009

+3VL_EC

0.1U_0402_16V4Z

1

1

C613

C614

2

R512 4.7K_0402_5%
R513 4.7K_0402_5%
R514 4.7K_0402_5%
R515 4.7K_0402_5%

+3VL

R517 47K_0402_5%

SUSP#

12

R522

8.2K_0402_5%

SYSON

R521

8.2K _0402_5%

1 2

2

0.1U_0402_16V4Z

SMB_EC_DA1
SMB_EC_CK1
SMB_EC_DA2
SMB_EC_CK2

11/1 5 D el e t e PCI_PME#

PCI_PME#<14>

EC_PME# PCI_RST#

1

C645

0.1U_0402_16V4Z

2

@

03/13 PV2 Add EMI solution

EC DEBUG port

UTX

R542

@

LA N_POWE R_OFF<32>

0.1U_0402_16V4Z

1

1

2

1000P_0402_50V7K

1 2

C630 0.1U_0402_16V4Z

R533

1

C646

0.1U_0402_16V4Z

2

C615

1 2
1 2
1 2
1 2

CLK_PCI_EC<14>

12

1 2

R543

1 2

0_0402_5%

C616

2

@

PCI_RST#

12

R523
100K_0402_5%

0_0402_5%

12

0_0805_5%

1000P_0402_50V7K

1

C617

2

+3VL +3VALW

C623

15P_0402_50V8J

LAN _POWER_OFF_R

1 2

1 2

12

J4
JOPEN

+3VL

12

R526
10K_0402_5%

LID_SW#

+3VL

R531

@

10K_0402_5%

1 2

EC_PME#

EC_PME#

+3VL

ON/OFFBTN#<38>

32.7 68KHZ_1 2.5P F_Q13MC14610002

ESB_CLK<38>

ESB_DAT<38>

R516

@

33_0402_5%

HDA_RST#_CODEC<11,33>

+3VS

12

R525
10K_0402_5%

TP_BTN#

01/03 Chan ge to +3VS

+3VALW

12

R532
10K_0402_5%

EC_ACIN<13>

FAN_SPEED<6>

WWAN_POWER_OFF<31>

1 2

R538 4.7K_0402_5%

C647
15P_0402_50V8J

1 2

3

NC

2

NC

1 2

C649
15P_0402_50V8J

+3VL +3VL

12

R544

4.7K_0402_5%

+EC_AVCC

9

22

33

96

111

125

VCC

VCC

VCC

VCC

VCC

VCC

PWM Output

AD Input

DA Output

PS2 Interface

SPI Device Interface

SPI Flas h ROM

GPIO

GPO

GPIO

GPI

GND

GND

GND

GND

GND

11

24

35

94

113

Issued Date

67

AVCC

INVT_PWM/PWM1/GPIO0F

BEEP#/PWM2/GPIO10

FANPWM1/GPIO12

ACOFF/FANPWM2/GPIO13

BATT_TEM P/AD0/GPIO38

BATT_O VP/AD1/GPIO39

ADP_I/AD2/GPIO3A

AD3/GPIO3B
AD4/GPIO42

SELIO2#/AD5/GPIO43

DAC_BRIG/DA0/GPIO3C

EN_DFAN1/DA1/GPIO3D

IREF/DA2/GPIO3E

DA3/GPIO3F

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D

TP_CLK/PSCLK3/GPIO4E

TP_DATA/PSDAT3/GPIO4F

SDICS#/GPXOA00
SDICLK/GPXOA01

SDIDO/GPXOA02

SDIDI/GPXID0

SPIDI/RD#

SPIDO/WR#

SPICLK/GPIO58

SPICS#

CIR_RX/GPIO40

CIR_RLC_TX/GPIO41

FSTCHG/SELIO#/GPIO50

BATT_CHG I_LED#/GPIO52

CAPS_LED#/GPIO53

BATT_LOW_LED#/GPI O54

SUSP_LED#/GPIO55

SYSON/GPIO56

VR_ON /XCLK32K/GPIO57

AC_IN/GPIO59

EC_RSMR ST#/GPXO 03
EC_LID_OUT#/GPXO 04

EC_ON/GPXO 05

EC_SWI#/GPXO06

ICH_PWROK/GPXO06

BKOFF#/GPXO08

WL_OFF#/GPXO09

GPXO10
GPXO11

PM_SLP_S4#/GPXID1

ENBKL/GPXID2

GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

V18R

AGND

KB9 26Q F B0_ LQFP128_14X14

69

ECAGND

L27

1 2

0_0603_5%

2007/08/28 2006/07/26

21
23
26
27

63
64
65
66
75
76

68
70
71
72

83
84
85
86
87
88

97
98
99
109

119
120
126
128

73
74
89
90
91
92
93
95
121
127

100

R535

101
102
103
104
105
106
107
108

110
112
114
115
116
117
118

124

1

2

For C
Revision

C651 100P_0402_50V8J

INV_PWM
EC_B EEP

ACOFF

BATT_TEMP
BATT_OVP
ADP_I
ADP_ID
TP_BTN#

FAB_SET
VCTRL

IREF

AC_SET

EC_MUTE#
USB_EN#
I2C_INT

TP_CLK
TP_DATA

R527 33_0402_5%

1 2

R528 33_0402_5%

1 2

R529 33_0402_5%

1 2

CIR_IN
VCC1_ PWRGD
FS TCHG
STD_ADP
CAPS_LED#
BAT_LED#
ON/OFFBTN_LED#
SYSON
VR_ON
AC_IN

EC_RSMRST#

1 2

EC_ON

0_0402_5%

WL_BLUE_LED#
PM_PWROK_R
BKOFF#
M_PWROK
TP_LED#

SLP_S4#
ENBKL
EAPD_CODEC
THERM_SCI#
SUSP#
PWRBT N_ O UT #
NMI_DBG#

C648

4.7U_0603_6.3V6K

NMI_DBG# P C I_ SERR#

AC_IN ACIN

1 2

INV_PWM <22>
EC_BEEP <33>

ACOFF <41>

C624

1 2

BATT_TEMP <40>
BATT_OVP <40>
ADP_I <41>
ADP_ID <40>
TP_BTN# <38>

FAN_SET <6>

VCTRL <41>
IREF <41>
AC_ S ET <41>

EC_ MUTE# <33>

USB_EN# <35>
I2C_INT <38>

R524 0_0402_5%

1 2

R530 10K_0402_5%

1 2

CIR_IN <34>

VCC1_PWRGD <36>

FS TCHG <41>

STD_ADP <41>

CAPS_LED# <38>

BAT_LED# <38>

ON/OFFBTN_LED# <36,38>
SYS ON <31,38,39,48>

VR_ON <46>

R534 10K_0402_5%

12

EC_RSMRST# <13>

EC_LID_OUT# <12>

EC_ON <42>

WL_BLUE_LED# <38>
BK OFF# <21>

M_ P WROK <13>
TP_LED# <38>

SLP_S4# <13>

ENBKL <22>
EAPD_CODEC <33>

THERM_SCI# <24>
SUSP# <31,39,41,44,45>

PWRBT N_ O UT # <13>

+3VL

12

R540

10K_0402_5%

D25

+3VL

CH751H-40PT_SOD323-2

12

R541
150K_0402_5%

2 1

CH751H-40PT_SOD323-2

21

D26

Compa l Secret Data

Dec iphered Date

0.01U_0402_16V7K

ECAGND

R519 10K_0402_5%

1 2

R520 10K_0402_5%

1 2

TP_CLK <38>
TP_DATA <38>

11/09 don't stuff when use C0

FRD#
FWR#
SPI_CLK

FSEL#

FRD# <36>
FW R# <36>
SPI_CLK <36>
FSEL# <36>

+5VL

R536

1 2

100_0402_5%

PV P WROK s e qu ence issu e

ADP_ID

CH751H-40PT_SOD323-2

PC I_ SERR# <14>

ACIN <41>

AC _ LED # <40>

2 1

GATEA20<14>
KB_RST#<14>

SIRQ<11>

LPC_FRAME#<11,31,36>

LPC_AD3<11,31,36>
LPC_AD2<11,31,36>
LPC_AD1<11,31,36>
LPC_AD0<11,31,36>

PCI_RST#<14,36>

EC_SCI#<14>

SMB_EC_CK1<38,40>
SMB_EC_DA1<38,40>
SMB_EC_CK2<12>
SMB_EC_DA2<12>

SLP_S3#<13>
SLP_S5#<13>
EC_SMI#<14>
LID_SW#<38>

EC_ACIN

FAN_SPEED
UTX

LAN_POWER_OFF_R

DIM_LED<39>

Y6

OSC
OSC

4.7K _0402_5%

1 2

12

4
1

R545

R54 6 0_ 0 402_5%

1 2

R54 7 0_ 0 402_5%

1 2

GATEA20
KB_RST#
SIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

CLK_PCI_EC

PCI_RST#
ECRST#

1 2

R518

0_0402_5%

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2

SLP_S3#
SLP_S5#
EC_SMI#
LID_SW#
ESB_CLK_R
ESB_DAT_R
EC_PME#

WWAN_POWER_OFF

ON/OFFBTN#

DIM_LED

CRY2

@

R539
20M _ 0402_5%

CRY1

+3VL +3VL_EC

R511

1 2

0_0805_5%

U27

1

GA20/GPIO00

2

KBRST#/GPIO01

3

SERI RQ#

4

LFRAME#

5

LAD3

7

LAD2

8

LAD1

10

LPC & MISC

LAD0

12

PCICLK

13

PCIRST#/GPIO05

37

ECRST#

20

SCI#/GPIO0E

38

CLKRUN#/GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPI O20

40

KSO1/GPI O21

41

KSO2/GPI O22

42

KSO3/GPI O23

43

KSO4/GPI O24

44
45
46
47
48
49
50
51
52
53
54
81
82

77
78
79
80

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

122
123

+EC_AVCC

1

C652
10P_0402_50V8J

2

ESB_CLK_R
ESB_DAT_R

Int. K/B

KSO5/GPI O25

Matrix

KSO6/GPI O26
KSO7/GPI O27
KSO8/GPI O28
KSO9/GPI O29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_O UT #/GPIO0C
EC_PME#/GPIO0D
EC_THER M #/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPI O18
PWR_LED#/GPIO19
NUM LED#/GPIO1A

XCLK1
XCLK0

@

SM Bus

+3VL_EC

12

L26
0_0603_5%

1 2

C650 0.1U_0402_16V4Z

Secur i t y C lassification

THIS SHEET OF ENGINEERING DRA WING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND T RADE SEC RET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D
DEP ARTMENT EXCE PT AS AUTHO RIZED BY COMPAL ELECTRONICS, IN C. NEITHER THIS SHEET NOR THE INFORMA T ION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

http://laptop-motherboard-schematic.blogspot.com/

BATT_OVP

C612

12

100P_0402_50V8J

For EMI

KSO15

C618 100P_0402_50V8J@

1 2

C619 100P_0402_50V8J@

1 2

C620 100P_0402_50V8J@

1 2

C621 100P_0402_50V8J@

1 2

C622 100P_0402_50V8J@

1 2

C625 100P_0402_50V8J@

1 2

C626 100P_0402_50V8J@

1 2

C627 100P_0402_50V8J@

1 2

C628 100P_0402_50V8J@

1 2

C629 100P_0402_50V8J@

1 2

C631 100P_0402_50V8J@

1 2

C632 100P_0402_50V8J@

1 2

C633 100P_0402_50V8J@

1 2

C634 100P_0402_50V8J@

1 2

C635 100P_0402_50V8J@

1 2

C636 100P_0402_50V8J@

1 2

C637 100P_0402_50V8J@

1 2

C638 100P_0402_50V8J@

1 2

C639 100P_0402_50V8J@

1 2

C640 100P_0402_50V8J@

1 2

C641 100P_0402_50V8J@

1 2

C642 100P_0402_50V8J@

1 2

C643 100P_0402_50V8J@

1 2

C644 100P_0402_50V8J@

1 2

ENBKL

R741 10K_ 0402_5%

13" INT_KBD

12

+5V_TP

PM_PWROK <13>

KSO10
KSO11
KSO14
KSO13
KSO12
KSO3
KSO6
KSO8
KSO7
KSO4
KSO2
KSI0
KSO1
KSO5
KSI3
KSI2
KSO0
KSI5
KSI4
KSO9
KSI6
KSI7
KSI1

CONN.( TYPE "D"
KB)

JKB1

KSO15

1

1

KSO10

2

+3VL

D24

Title

Size Document Number Re v

Date: Sheet

Compal Electronics, Inc.

EC KB926/KB Conn.

Cal p el la D I S L A4743P

2

KSO11

3

3

KSO14

4

4

KSO13

5

5

KSO12

6

6

KSO3

7

7

KSO6

8

8

KSO8

9

9

KSO7

10

10

KSO4

11

11

KSO2

12

12

13

13

KSO1

14

14

KSO5

15

15

16

16

17

17

KSO0

18

18

19

19

20

20

KSO9

21

21

22

22

23

23

24

24

25

G1

26

G2

ACES_85202-24051

CONN@

KSI0

KSI3
KSI2

KSI5
KSI4

KSI6
KSI7
KSI1

of

37 49Monday, April 13, 2009

0.1

A

1 1

B

C

D

E

System LED C onn

JLED

1

1

GND

2

2

3

3

4

4

5

5

6

6

7

7

8

8

GND

ACES_87213-0800G

CONN@

9

10

White

AMBER

+5VALW

+5VS

+3VS

BAT_LED#<37>

SATA_LED#<11>

HDDHA L T_LED#<11>

ON/OFFBTN_LED#

Capacitor Sensor Conn

2 2

Cypr ess@

R597 0_0402_5%

SMB_EC_CK1<37,40>
SMB_EC_DA1<37,40>

ON/OFFBTN_LED#<36,37>

ESB_CLK<37>
ESB_DAT<37>

I2C_INT<37>

+5VALW

LID_SW#<37>

ON/OFFBTN#<37>

3 3

ON/OFFBTN_LED#

R561 FBMA-11-100505 -801T 04 02ENE@

1 2

R562 FBMA-11-100505 -801T 04 02ENE@

1 2

1 2

R598 0_0402_5%

1 2

Cypr ess@

R596 1.8K_0402_5%

1 2

R563 1K_0402_5%

1 2

Caps-Lock Conn

JCAP

1
2
3

4
GND
GND

P-TWO_161011-04021

CONN@

+5VS

+3VL

12

R557
0_0805_5%

1

1

@

C772

15P_0402_50V8J

C661

2

2

4.7U_0603_6.3V6K

1
2
3
4
5
6

+5VS

JCSB

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

GND

12

GND

P-TWO_161021-10021

CONN@

CAPS_LED# <37>

ESB_DAT

ESB_CLK

Keyboard backlight Conn

Power Button

for debug only

SW2

1
2

5

6

SMT1-05_4P

@

12

@

12

C662

15P_0402_50V8J

C660

15P_0402_50V8J

R570

@

33_0402_5%

R564

@

33_0402_5%

T/P Board (Inculde T/P_ON/OFF)

3
4

12

12

ON/OFFBTN#

+5VALW +5V_TP

R558 0_0603_5%

12

R560

@

10K_0402_5%

13

SYSON<31,37,39,48>

SYSON

D

2

G

S

Mini c a rd LED

JTPSW

P-TWO_161011-04021

CONN@

1 2

S

D

13

Q23

G

SI2301BDS-T1-E3_SOT23-3

2

Q24

@

2N7002_SOT23-3

1

1

TP_LED#

2

2

TP_BTN#

3

3

4

4

5

GND

6

GND

T / P B oar d Conn

@

JTP

1
2
3

4
GND
GND

P-TWO_161011-04021

CONN@

+5VS

1
2
3
4
5
6

TP_ LED# <37>
TP_BTN# <37>

+5V_TP

TP_CLK
TP_DATA

100P_0402_50V8J

+3VS

12

R565
10K_0402_5%

TP_DATA
TP_CLK

1

C654

0.1U_0402_16V4Z

2

C658

@

1

1

@

100P_0402_50V8J

2

2

3

C659

2

1

D32
PSOT24C_SOT23-3

TP_CLK <37>
TP_DATA <37>

R566

+5VS_LED

4 4

A

http://laptop-motherboard-schematic.blogspot.com/

B

1 2

0_0805_5%

JKBL

1

1

2

2

3

3

4

4

5

GND

6

GND

P-TWO_161011-04021

CONN@

WL_LED#<31>
WW_LED#<31>

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEERING DRA WING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND T RADE SEC RET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D
DEP ARTMENT EXCE PT AS AUTHO RIZED BY COMPAL ELECTRONICS, IN C. NEITHER THIS SHEET NOR THE INFORMA T ION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/28 2006/07/26

Compa l Secret Data

Dec iphered Date

D

BT_LED<35>

D33

2
3

PSOT24 C_SOT23-3

2N7002_SOT23-3

R567

100K_0402_5%

1

Q25

13

D

2

G

12

S

WL_LED

Title

Size Document Number Re v

Date: Sheet

WL_BLUE_LED# <37>

Compal Electronics, Inc.

KBD, ON/OFF, SW, CIR

Cal p el la D I S L A4743P

38 49Monday, April 13, 2009

E

0.1

of

5

4

3

2

1

+5VALW to +5VS Transfer +3VALW to +3VS Transfer

+5VALW +3VALW

B+

D D

12

R583

C675

330K_0402_5%

SUSP

2

2N7002DW-7-F_SOT363-6

Q10A

SI73 2 6DN-T1-E 3_PAK1212-8

1

2

10U_0805_10V4Z

RUNON

61

U28

4

12

1

2

+3VALW to +3VS_NV Transfer

SI73 2 6DN-T1-E 3_PAK1212-8

U48

SG@

C C

12

SG@

R912

330K_0402_5%

DGPU_PWR_EN<14,23,45,47>

SG@

2N7002DW-7-F_SOT363-6

1

2

DGPU _PWR_EN#

3

5

Q14B

4

SG@

C1073
10U_0805_10V4Z

+5VS +3VS

1
2
35

1

1

C671

C672

2

0.1U_0402_16V4Z
10U_0805_10V4Z

01/03 Sparate+5VS
and +3VS power
timing

R585

470_0402_5%

C677
4700P_0402_25V7K

2

B+

12

R581

330K_0402_5%

SUSP

5

2N70 02DW-7-F_SOT 363-6

Q10B

SI7 3 26DN-T1- E 3_PAK1212-8

U29

1

C669
10U_0805_10V4Z

2

RUNON_3VS

3

4

+1.8VS to +1.8VS_NV Transfer +1.5 V to +1.5VS_NV Transfer

+3VS_NVB+ +3VALW +1.8VS_NV

1
2
35

4

12

SG@

R915
470_0402_5%

1

SG@

C1077

0.01U_0402_16V7K

2

400 mA 100 mA 4.64A

Q14A

SG@

2

12

R913

470_0402_5%

61

2N70 02DW-7-F_SOT363-6

SG@

1

SG@

2

C1075

DGPU _PWR_EN

0.1U_0402_16V4Z

SG@

+1.8VS

B+

12

1

SG@

R918

2

330K_0402_5%

NV VDD_P G#

NV VDD_PG<47>

SG@

2N70 02DW-7-F_SOT363-6

C1076

10U_0805_10V4Z

Q17B

3

5

4

1
2
35

4

12

R584
470_0402_5%

1

C676

0.01U_0402_16V7K

2

SI7 3 26DN-T1- E 3_PAK1212-8

U49

SG@

1
2
35

4

12

SG@

R916
1K_0402_5%

SG@

1

C1078

0.1U _ 0402_25V4K

2

1

C673

2

1

SG@

2

NV VDD_P G

1

C674

2

10U_0805_10V4Z

0.1U_0402_16V4Z

12

C1074

SG@

R594

0.1U_0402_16V4Z

SG@

Q17A

470_0402_5%

61

2

2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6

+1. 5V to +1.5VS Transfer

SI73 2 6DN-T1-E 3_PAK1212-8

U30

1

C681

2

RUNON

10U_0805_10V4Z

SI73 2 6DN-T1-E 3_PAK1212-8

U50

SG@

1

SG@

2

C1081

10U_0805_10V4Z

NV VDD_P G#

3

5

Q18B

SG@

4

1
2
35

4

12

R650
1K_0402_5%

1

C770

0.1U_0402_25V4K

2

1
2
35

4

+1.5VS+1.5V

+VDD_MEM+1.5V

SG@

NV VDD_P G

C679

C1079

0.1U_0402_16V4Z

0.1U_0402_16V4Z

SG@

Q18A

1

2

SG@

2

C680

10U_0805_10V4Z

12

R917

470_0402_5%

61

2N7002DW-7-F_SOT363-6

1

2

1

2

Discharge circuit DIM LED

+1.5VS

12

R590

470_0402_5%

61

Q8A

SUSPSUSP SUSPSUSP SYSON#SUSP

2

2N70 02DW-7-F_SOT363-6

H15

H14

H13
HOLEA

1

HOLEA

HOLEA

1

1

http://laptop-motherboard-schematic.blogspot.com/

4

470_0402_5%

Q9B

12

R587
100K_0402_5%

3

Q6B

5

4

H11
HOLEA

1

R589

5

1

+3VS

12

3

4

H12
HOLEA

1

2N70 02DW-7-F_SOT363-6

+5VS

12

B B

SYSON#<45> SUSP <45>

A A

H1
HOLEA

1

SYSON<31,37,38,48> SUSP# <31,37,41,44,45>

H2

H3
HOLEA

1

H4
HOLEA

1

5

HOLEA

1

470_0402_5%

R586

100K_0402_5%

Q6A

2

H6

H5

HOLEA

HOLEA

1

Q9A

+3VL

1

2

R588

12

61

61

2N7002DW-7-F_SOT363-6

H7
HOLEA

1

2N70 02DW-7-F_SOT363-6

+3VL

2N7002DW-7-F_SOT363-6

H8
HOLEA

+VCCP +0.75VS

12

R591

470_0402_5%

3

Q8B

5

4

2N70 02DW-7-F_SOT363-6

H17
HOLEA

1

H18
HOLEA

1

H16
HOLEA

1

R592

470_04 02_5%

Q7A

2

FM1

1

FM3

1

+1.5V

12

61

2N70 02DW-7-F_SOT363-6

FM2

1

FM4

1

12

R593

470_04 02_5%

3

Q7B

5

4

2N70 02DW-7-F_SOT363-6

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEERING DRA WING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND T RADE SEC RET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D
DEP ARTMENT EXCE PT AS AUTHO RIZED BY COMPAL ELECTRONICS, IN C. NEITHER THIS SHEET NOR THE INFORMA T ION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/07/26

Compa l Secret Data

DIM_LED<37>

Dec iphered Date

DIM_LED

2

+5VS +5VS_LED

12

R582

10K_0402_5%

13

D

2

G

S

Q26

SI2301BDS-T1-E3_SOT23-3

S

DIM_LED#

Q27
2N7002_SOT23-3

D

13

G

2

Title

Size Document Number Re v

Date: Sheet

1

C670

0.1U_0402_16V4Z

2

Compal Electronics, Inc.

DC/DC Interface

Cal p el la D I S L A4743P

39 49Monday, April 13, 2009

1

of

0.1

A

B

C

D

+3VALW

PQ3
TP0610K-T1-E3_SOT23-3

1 2

1 1

100K_0402_5%

2

1 3

PR8
2K_0402_5%

1 2

ADP _SIGNAL

JDC

6

GND

5

GND

4

4

3

3

2

2

1

1

ACES_87302-0441

2 2

ADPINADP IN

1 2

PR3
10K_0402_5%

2

3

PD1

@PJSOT24C_SOT23-3

1

PR9

12

+3VL

PC2

100P_0402_50V8J

connect to KBC pin97

AC_LED# <37>

12

PR2
10K_0402_5%

12

PD4

RLZ3.6B_LL34

PL1

HCB2012KF-121T50_0805

1 2

PL2

HCB2012KF-121T50_0805

1 2

12

PC3
1000P_0402_50V7K

12

12

PC4

100P_0402_50V8J

PC12
@1000P_0402_50V7K

VIN

12

PC5

1000P_0402_50V7K

ADP_ID <37>

PC6

0.01U_0402_25V7K

BATT

12

+5VALW

PR1

340K_0402_1%

12

PR4

499K_0402_1%

12

12

PR6

105K_0402_1%

12

PC1

0.01U_0402_25V7K

3
2

PU1A

LM358ADT_SO8

8

P

+

1

0

-

G

PR5

10K_0402_5%

12

BATT_OVP <37>

4

JBATT

1

BATT+

2

SMD

3

SMC

4

B/I

GND

5

TS

6

PR16

6.49K_0402_1%

1 2

12

PR17
1K_0402_5%

7

GND

8

GND

SUYIN_200275MR006G113ZL

3 3

4 4

EC_SMD
EC_SMC

PD3

3

1

2

PJSOT24C_SOT23-3

BAT_ID <41>

+3VL

12

PR13

100_0402_5%

PD2

3
2

PJSOT24C_SOT23-3

12

PR14
100_0402_5%

BATT_TEMP <37>

1

VMB

SMB_EC_DA1

SMB_EC_CK1

PL3

HCB2012KF-121T50_0805

1 2

PL4

HCB2012KF-121T50_0805

1 2

12

PC8
1000P_0402_50V7K

12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

http://laptop-motherboard-schematic.blogspot.com/

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.

B

BATT

PC9

0.01U_0402_50V4Z

SMB_EC_DA1 <37,38>

SMB_EC_CK1 <37,38>

0.22U_0603_10V7K

PH1 under CPU botten side :

CPU thermal protection at 90 +-3 degree C

+5VS

CPU

12

PH1

10K_TH11-3H103FT_0603_1%

PR10

200K_0402_1%

1 2

+5VALW

12

12

PC10

2.49K_0402_1%

2007/05/29 2008/05/29

1 2

PR11

150K_0402_1%

PR12

150K_0402_1%

Compal Secret Data

Deciphered Date

C

12

PR15

PR7

604K_0402_1%

1 2

5

+

6

-

12

PC11
1000P_0402_50V7K

8

P

7

0

G

PU1B

4

LM358ADT_SO8

EN0 <42>

13

D

2

G

Title

Size Document Number R e v

Date: Sheet

Compal Electronics, Inc.

DC Con ne ctor/CPU_OTP

PQ1
SSM3K7002FU_SC70-3

S

Calpella DIS LA4743P

D

of

40 49Monday, April 13, 2009

0.1

A

VIN

1 1

PC101

PR107
47K_0402_1%

1 2

PQ107

13

SSM3K7002FU_SC70-3

2 2

D

2

G

S

PACIN

ACOFF#

PR101

47K_0402_5%

1 2

12

47P_0402_50V8J

2

13

2

PQ105
DTC115EUA_SC70-3

PR111

3K_0402_1%

1 2

PD101

1 2

1SS3 5 5_SOD323-2

PQ101
AO4433_SO8

8
7

5

PQ104

DTA144EUA_SC70-3

1 3

PQ109

13

D

SSM3K7002FU_SC70-3

2

G

S

VCTRL<37>

1
2
36

4

PC106

1 2

1U_0 6 03_10V6K

P2

12

0.1 U _ 0603_16V7K

12

PR114
@0_0402_5%

PC117

1
2
3 6

12

PR106

200 K_0402_5%

PR109
150 K_0402_5%

143 K_0402_1%

12

PR113

PQ103

AO4409_SO8

4

12

12

8
7

5

AC_ SET<37>

SUSP#<3 1,37,39,44,45>

PR115
100K_0402_1%

@0.0 1U_0402_16V7K

PC112

1 2

1U_0 6 03_6.3V6M

ADP_I<37>

2

G

+3VL

PR132

12

PC120

100 K_0402_5%

ACDET

100K_0402_1%

Charge Detector

VIN

PD104
1SS3 55_SOD323-2

PR123

1 2

1M_0402_5%

1 2

3 3

VIN

12

PR131
133 K_0402_1%

12

PR135
10K_0603_0.1%

4 4

1.24VREF

3
2

VIN_1

12

8

+

-

4

PR125
47_1206_5%

12

P

1

O

G

PU102A
LM393DG_SO8

PC125

0.1 U_ 0603_25V7K

+3VL

12

PR129

10K_0402_1%

STD_ADP <37 >

+3VL

PR128

2

G

12

10K_0402_5%

13

D

S

FSTCHG<37>

CHGEN#

PQ112
SSM3K7002FU_SC70-3

FSTCHG#

1 2

PR137
20K_0402_1%

PR104
0_0402_5%

1 2

PC107

PR110
0_0402_5%

1 2

BQ24740VREF

PR116

39K_0402_5%

1 2

12

0.2 2 U_0603_10V7K

12

13

D

PQ113
SSM3K7002FU_SC70-3

S

PR138

B

12

+3VL

12

PR118

10K_0402_5%

0.1 U_ 0 402_10V7K

ACSET

ACSET

12

PR140
100 K_0402_5%

8

IADSLP

9

AGND

10

VREF

11

VDAC

12

VADJ

13

EXTPWR

14

ISYNSET

PC121

100 P _0402_50V8J

PC123

ACDET

7

6

LPREF

ACSET

PU101
BQ24740RHDR_QFN28_5X5

IADAPT

SRSET

15

16

IADAPT

12

12

5

ACDET

BAT

17

BATT

P4

PC108

0.1 U _ 0603_25V7K

4

LPMD

SRN

18

PR102

1
2

0.0 12_2512_1%

1 2

PC102

1U_0603_6.3V6M

12

ACP

ACN

2

3

ACP

SRP

19

20

PR120

133K_0402_1%

12

PR121
200K_0402_1%

B+

PL101

4

HCB20 1 2KF-121T50_0805

3

1 2

CHGEN#

1

ACN

TP

CHGEN

PVCC

BTST

HIDRV

PH

REGN

LODRV

PGND

DPMDET

CELLS

21

SSM3K7002FU_SC70-3

12

12

12

PC103

4.7 U _0805_25V6-K

PR108
10_1206_5%

1 2

29

PC110
1U_0805_25V6K

1 2

28

PR142

0_0402_5%

BST_CHG

1 2

27

PR139

0_0402_5%

DH_CHG DH_CHG1

1 2

26

LX_CHG

25

PD102

REGNVADJ

24

DL_CHG

23

12

1SS3 5 5_SOD323-2

22

12

PC119
1U_0603_10V6K

PR117

100K_0402_5%

1 2

13

D

PQ111

IREF <37>

2

G

S

12

PC105

PC104

4.7 U _0805_25V6-K

PC111

1 2

0.1U_0402_10V7K

PQ110

AO4468_SO8

BQ24740VREF

12

47K_0402_5%
PR119

PC124

0.1 U _ 0603_25V7K

C

PQ102
AO4407_SO8

1
2

0.0 15_1206_1%

1 2

PC114

4.7 U _ 0805_25V6-K

0.1 U_ 0 402_10V7K

3 6

PR112

1 2

PC118

CHG_B+

4.7 U _0805_25V6-K

CHG_B+

PQ108
AON7408L_DFN8-5

PL102

3 5

241

10U_LF919AS-100M-P3_4.5A_20%

1 2

12

578

PR141

@4.7_1206_5%

12

12

PC113

4.7 U _ 0805_25V6-K

3 6

241

PC135
@47 0 P_0603_50V8J

1 2

BAT_ID <40>

8
7

5

4

ACOFF#

BATT

12

12

PC115

4.7 U _ 0805_25V6-K

D

BATT

PR103

47K_0402_5%

1 2

12

PR105
10K_0402_5%

13

PQ106
DTC115EUA_SC70-3

12

PC122

PC116

4.7 U _ 0805_25V6-K

4.7 U _ 0805_25V6-K

VIN

2

ACOF F <37>

12

PR122
681 K_0402_1%

1 2

PR127

10K_0402_1%

PR124
1K_0402_5%

1 2

12

PR134
10K_0402_5%

ACIN <37>

PACIN

1.24VREF

PC126

0.0 4 7U_0402_16V7K

PR126

100K_0402_1%

12

VIN

12

PR130

2.1 5K_0402_1%

1 2

12

PR133
10K_0603_0.1%

PC127

22P_ 0402_50V8J

VIN

12

8

PU102B

5

P

+

7

O

6

-

G

LM393DG_SO8

4

PR136

60. 4K_0402_1%

1 2

4

12

REF

5

ANODE

LMV 431ACM5X_SOT23-5

PD103

RLZ4 . 3B_LL34

PU104

CATHODE

VIN_1

NC
NC

12

3
2
1

Securi ty Classification

Issued Date

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPER TY OF COMPAL ELECTR ONI CS, INC . AN D C ONT AINS CO NFID ENTI AL
AND TRADE SECRET INFORMATION. THIS SH EET MAY NOT BE TRANSFERED FRO M TH E CU STO DY O F TH E CO MPET ENT DIVI SIO N O F R& D

A

http://laptop-motherboard-schematic.blogspot.com/

B

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHE R TH IS SHEE T NO R TH E I NFOR MATI ON IT C ONTA INS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRI TTEN CON SENT OF COM PAL ELEC TRO NIC S, I NC.

2007/05/29 2008/05/29

C

Compal Secret Data

Dec iphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Charger

Calpella DIS LA4743P

D

of

41 49Monday, April 13, 2009

0.1

A

B

C

D

E

2VREF_51125

1 1

B+

2 2

3 3

PL301

HCB2012 K F-121T50_0805

1 2

B++

12

PC313

0.1U _ 0402_25V6

+3VALWP

12

PC301

1000P_0402_50V7K

SSM3K7002FU_SC70-3

12

PC303

4.7U_0805_25V6-K

4.7U H_SIQ B 74B -4R7PF_4A_20%

1

PC309

+

2

150U_B_6.3V M_R45M

PQ305

PL302

+3VLP

PQ301
AON7408L_DFN8-5

10U_0805_6.3V6M

UG1_3V

3 5

241

PR309

0_0402_5%

12

12

PR315

4.7_ 1206_5%

12

ENTRIP1

13

D

2

G

S

123

PC314

680P_0603_50V8J

2

G

PQ307

13

D

SSM3K7002FU_SC70-3

2

G

S

5

1 2

1 2

PQ303

4

AON7406L_DFN8-5

ENTRIP2

13

D

PQ306
SSM3K7002FU_SC70-3

S

PR313
100K_0402_5%

12

PR314
100K_0402_5%

PC306

VL

12

1 2

1 2

0_0402_5%

PC307

0.1U_0402_10V7K

LX_3V

B++

EN0<40>

EC_ON <37>

PR307

LG_3V

1M_ 0 402_1%

1 2

191K_0402_1%

PR312

13.7K_0402_1%

20K_0402_1%

105K_0402_1%

BST_3V

UG_3V

PR311

2VREF_51125

+5VALWP

+3VALWP

0.22U_0603_10V7K

PR301

1 2

PR303

1 2

PR305

1 2

25

7
8

9
10
11
12

12

PC302

ENTRIP2

6

P PAD

ENTRIP2

VO2
VREG3
VBST2
DRVH2
LL2
DRVL2

EN0

13

PJP302

1 2

PAD-OPEN 4x4m
PJP303

1 2

PAD-OPEN 4x4m

B++

12

5

VFB2

SKIPSEL

14

4

TONSEL

GND

15

3

16

12

PR302

30.9K_0402_1%

1 2

PR304
20K_0402_1%

1 2

PR306
115K_0402_1%

ENTRIP1

1 2

1

2

VFB1

VREF

ENTRIP1

24

VO1

23

PGOOD

22

VBST1

21

DRVH1

20

LL1

19

DRVL1

VREG5

VIN

VCLK

PU301

17

18

TPS 51125RG E R_QFN24_4X4

VL

12

PC311
10U_0805_10V6K

PC312

0.1U_0603_25V7K

(4. 5A,180mils ,Via NO.= 9)

+5VALW

(3A,120mils ,Via NO.= 6)

+3VALW

BST_5V

UG_5V
LX_5V
LG_5V

1 2

PR308

0_0402_5%

1 2

PR317

0_0402_5%

B++

12

PC304

PC316

0.1U _ 0402_25V6

PC308

0.1U_0402_10V7K

1 2

R_EC_RSMRST# <13>

12

1000P_0402_50V7K

1 2

12

PC305

PR310
0_0402_5%

10U_1206_25V6M

PQ304

STL8 NH3 LL

4

3 5

5

+3VLP

VL

241

PQ302
AON7408L_DFN8-5

PR316

4.7_ 1206_5%

123

2 1

PAD-OPEN 2x2m

2 1

PAD-OPEN 2x2m

PL303

4.7UH_PCMC063T-4R7MN_5.5A_20%

1 2

12

1

+

PC310

+3VL

+5VL

150U_B_6.3VM_R45M

2

12

PC315

680P_0603_50V8J

PJP301

PJP304

+5VALWP

4 4

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEERING DRA WING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND T RADE SEC RET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D
DEP ARTMENT EXCE PT AS AUTHO RIZED BY COMPAL ELECTRONICS, IN C. NEITHER THIS SHEET NOR THE INFORMA T ION IT CONTAINS

A

http://laptop-motherboard-schematic.blogspot.com/

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compa l Secret Data

Dec iphered Date

Title

Size Document Number Re v

Custom

D

Date: Sheet

Compal Electronics, Inc.

3.3VALWP/5VALWP

Cal p el la D I S L A4743P

42 49Monday, April 13, 2009

E

0.1

of

5

CPU_B+

4

3

2

1

12

D D

PR404

10_0402_5%

1 2

VSS_AXG_SENSE<9>

VCC_AXG_SENSE<9>

+VGA_CORE

C C

B B

PR406

10_0402_5%

1 2

150P_0402_50V8J

PC421

1 2

PC411
1000P_0402_50V7K

1 2

PC412
330P_0402_50V7K

PR413

8.66K_0402_1%

12

12

PR416

17.8K_0402_1%

825K_0402_1%

1 2

12

12

PR414

1 2

PC417

100P_0402_50V8J
PC422

22P_0402_50V8J

1 2

GF XVR_PWRGD
GFXVR_CLKEN#

PC413
330P_0402_50V7K

12

PC401

PC402

1000P_0402_50V7K

PC418

1000P_0402_50V7K

12

12

PR417

8.06K_0402_1%

10U_1206_25V6

12

10U_1206_25V6

PC403

12

+5VALW

PC406

0.1U_0402_25V6

PR409

47K_0402_1%

+VGA_CORE

12

PR419

@1.91K_0402_1%

PR401

1_0603_5%

12

PR420

@10K_0402_1%

12

12

PC407
1U_0603_6.3V6M

29

7

VSEN

6

FB

5

COMP

4

VW

12

3

RBIAS

2

PGOOD

1

CLK_EN#

AGND

PR402

0_0603_5%

ISUM+

ISUM-

10

11

9

ISUM

VR_ON

27

ISUM+

VID6

26

12

VIN

VDD

VID5

VID4

25

24

8

RTN

PU401
ISL62881HRZ-T_QFN28_4X4

DPRSLPVR

28

1 2
12

13

23

IMON

VID3

PC408

0.22U_0603_25V7K

BST_GFX

14

BOOT

UGATE
PHASE

VSSP

LGATE

VCCP

VID0
VID1

VID2

22

12

PR403

22.6K_0402_1%

1 2

PR405

2.2_0603_5%

15

LX_GFX

16
17

DL_GFX

18
19
20
21

12

PC409

0.22U_0402_6.3V6K

1 2

PC410

0.22U_0603_16V7K

PR407

0_0603_5%

1 2

PR410

1 2

0_0603_5%

12

PC419

2.2U_0603_6.3V6K

GFXVR_IMON <9>

VSS_AXG_SENSE

DH_GFX1D H_GFX

+5VALW

TPCA8028_PSO8

PR4210_0402_5%

12

PR4220_0402_5%

12

PR4250_0402_5%

12

PR4260_0402_5%

12

PR4270_0402_5%

12

PR4280_0402_5%

12

PR4300_0402_5%

12

PR4310_0402_5%

12

PR4320_0402_5%

12

578

PQ401
AO4474_SO8

3 6

241

3 5

241

PQ402

GFXVR_VID_0 <9>
GFXVR_VID_1 <9>
GFXVR_VID_2 <9>
GFXVR_VID_3 <9>
GFXVR_VID_4 <9>
GFXVR_VID_5 <9>
GFXVR_VID_6 <9>
GFXVR_EN <9>
GFXVR_DPRSLPVR <9>

12

PR408

4.7_1206_5%

PC420

1 2

680P_0603_50V7K

ISUM+
ISUM-

PL402

4
3

12

PR411

3.65K_0805_1%

1 2

PR415

2.61K_0402_1%

1 2

11K_0402_1%

PC423

0.1U_0402_16V7K

PC424

0.033U_0402_16V7K

PR429

82.5_0402_1%

1 2

1
2

0.56UH_MMD-10CZ-R56M-M1_19A_20%

PH401

1 2

10KB_0603_5%_ERTJ1VR103J

PR418

1 2

1 2

PR423

3.01K_0402_1%

1 2

PC425

0.01U_0402_16V7K

12

PR412
0_0402_5%

1 2

PR424
100_0402_1%

1 2

PC426
180P_0402_50V8J

1 2

+VGA_CORE

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

http://laptop-motherboard-schematic.blogspot.com/

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.

2008/10/31 2009/10/31

3

Compal Secret Data

Deciphered Date

Title

Size Document Number R e v

Custom

2

Date: Sheet

Compal Electronics, Inc.

VCCGFX

Calpella DIS LA4743P

1

of

43 49Mon d a y , Ap r i l 1 3 , 2009

5

4

3

2

1

PR517
0_0402_5%

PR518
10_0402_5%

VTT PWRGOOD<6>

PC506

0_0402_5%

VTT_SELECT<9>

12

12

12

PR513

26.7K_0402_1%

0.022U_0402_25V7K@

PR506
0_0402_5%

12

PR5080_0402_5%

12

12

PR520

174K_0402_1%

PR501

1 2

PR502

10.5K_0402_1%

1 2

PR505

0_0402_5%

1 2

12

PC524

BST_1.1VTT

12

UG_1.1VTT

LX_1.1VTT LX_1.05V

LG_1.1VTT

PU501

25

P PAD

7

PGOOD2

8

EN2

9

VBST2

10

DR VH2

11

LL2

12

DR VL2

PR510

14.7K_0402_1%

1 2

6

VO2

PGND2

13

VFB2

TRIP2

14

4

TONSEL

V5FILT

15

3

GND

V5IN

17

16

1 2

VFB1

TRIP1

PR511

12.1K_0402_1%

2

5

1 2

PR514

3.3_0402_5%

12

1U_0603_10V6K
PC513
@0.1U_0402_16V7K

PC514

12

12

PC515

4.7U_0805_10V6K

PR503

75K_0402_1%

1 2

1

VO1

24

PGOOD1

23

EN1

BST_1.05V

22

VBST1

21

DR VH1

20

LL1

LG_1.05V

19

DR VL1

PGND1

TPS51124RGER_QFN24_4x4

18

+5VALW

PR504

29.4K_0402_1%

1 2

12

PC512
@0.1U_0402_16V7K

PR507

0_0402_5%

PR509

0_0402_5%

PR512

0_0402_5%

1 2

12

12

+1.05VSP

PC507

0.1U_0402_10V7K

1 2

UG1_1.05V

SUSP#

PQ501
AON7408L_DFN8-5

B+++

3 5

241

PQ503
FDMC8296_POWER33-8-5

3 5

241

PL502

HCB2012KF-121T50_0805

12

12

PC503

10U_1206_25V6

B+

12

12

PC521

0.1U_0402_25V6

PC505

1000P_0402_50V7K

PL501

2.2UH_PCMC063T-2R2MN_8A_20%

1 2

12

PR516

4.7_1206_5%

12

PC519

680P_0603_50V7K

+

PC508

1

2

+1.05VSP

220U_B2_2.5VM_R25M

D D

VTT_SENSE<9>

B+++

12

12

PC511

PC501

C C

10U_1206_25V6

4.7U_0805_25V6-K

12

PC502

1000P_0402_50V7K

0.1U_0402_25V6

12

PC520

+1.1VTT

1

2

680P_0603_50V7K

330U_X_2VM_R6M

PL503

4.7_1206_5%

PC518

12

PR515

0.47UH_FDV0630-R47M-P3_18A_20%

+

PC523

B B

+VCCP

+

PC517

1

2

1

+

PC522

2

330U_X_2VM_R6M

330U_X_2VM_R6M

VTT _SENSE

+1.1VTT

578

PQ502
AO4474_SO8

0.1U_0402_10V7K

3 6

241

UG1_1.1VTT UG_1.05V

12

PQ504
TPCA8028_PSO8

12

3 5

241

SUSP#<31,37,39,41,45>

PJP501

+1.05VSP

A A

+1.1VTT

1 2

PAD-OPEN 4x4m

PJP502

1 2

PAD-OPEN 4x4m
PJP503

1 2

PAD-OPEN 4x4m

5

+1.05VS

(6A,240mils ,Via NO.= 12)

(14A,240mils ,Via NO.= 28)

+VCCP

http://laptop-motherboard-schematic.blogspot.com/

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.

2007/05/29 2008/05/29

3

Compal Secret Data

Deciphered Date

Title

Size Document Number R e v

2

Date: Sheet

Compal Electronics, Inc.

1.1VTTP/1.1VSP

Calpella DIS LA4743P

1

of

44 49Monday, April 13, 2009

0.1

5

D D

C C

PJP601

+0.75 VSP

+1 . 1 V_PCI E

B B

+1 .8VSP

1 2

PAD-OPEN 3x3m

PJP603

1 2

PAD-OPEN 3x3m

PJP602

1 2

PAD-OPEN 3x3m

(2A,80mils ,Via NO.= 4)

+0.75VS

(2A,80mils ,Via NO.= 4)

+PCIE

(1.5A,60mils ,Via NO.= 3)

+1.8VS

4

+1.5V

12

12

PC601

10U_0805_10V4Z

SYSON#<39>

SUSP<39>

1 2

PR602

@0_0402_5%

SSM3K7002FU_SC70-3

1 2

PR604

0_0402_5%

SUSP#<31,37,39,41,44>

PQ601

2

12

PC606
@0.1U_0402_16V7K

SUSP#

0.01U_0402_16V7K

PC602

G

1 2

PR609

0_0402_5%

PC617

@10U_0805_10V4Z

13

D

S

12

PR601
1K_0402_1%

12

PR603
1K_0402_1%

PU602

7

POK

8

EN

12

APL5915KAI-TRL_SO8

3

PU601

VIN1VCNTL

2

GND

3

VREF

4

VOUT

G29 92F1U_SO8

6
5

NC

7

NC

8

NC

9

TP

+5VALW

12

PC603
1U_0603_16V6K

2

1

+0.75VSP

12

12

PC605
10U_0805_6.3V6M

0.1U_0402_16V7K

PC604

+5 VALW

12

PC609
1U_0603_6.3V6M

6

PU603

7

POK

DGPU_PWR_EN<14,23,39,47>

+5VALW

PC618

12

1U_0603_6.3V6M

6

5

VIN

4

VOUT

VCNTL

3

VOUT

2

FB

9

TP

GND

1

PR611

15K_0402_1%

12

12

PC614
150P_0402_50V8J

+3VS

12

+1.8VSP

12

PC616
22U_0805_6.3V6M

PC615
10U_0805_10V6K

@0.01U_0402_16V7K

1 2

PR606

0_0402_5%

PC611

8

EN

12

APL5913-KAC-TRL_SO8

1

VCNTL

VOUT
VOUT

GND

VIN
VIN

FB

5
9
3
4
2

PR607

15K_0402_1%

PR608

39.2K_0402_1%

12

12

12

12

PC613
@47P_0402_50V8J

+1.5VS

12

PC610
10U_0805_10V6K

+1.1V_PCIE

PC612
22U_0805_6.3V6M

12

PR610

12K_0402_1%

A A

Security Classification

Issued Date

THIS SHE E T OF E NGIN EE RI NG DR A W ING I S THE P RO P RIE TAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/11/23 2007/11/23

Co m pa l Secret Data

Deciphered Date

2

Title

Size D o cu ment Number Re v

Date: Sheet

Compal Electronics, Inc.

0.7 5 VP /1.8VSP/1.1V_PCIE

Calp ell a DI S L A4 743P

1

45 49Monday, April 13, 2009

of

0.1

http://laptop-motherboard-schematic.blogspot.com/

8

H H

H_VID0<9>
H_VID1<9>
H_VID2<9>
H_VID3<9>
H_VID4<9>
H_VID5<9>
H_VID6<9>

G G

H_DPRSLPVR<9>

+3VS

VGATE<13,19>

F F

E E

12

@

PR234

249 K_0402_1%

D D

PC227

150P_0402_50V8J

C C

VCCSENSE>

B B

VSSSENSE<9>

A A

VR_ON<37>

CLK_EN#<19>

PR219
0_0402_5%

H_PR OCHO T#<6>

12

PR235

8.0 6 K_0402_1%

1 2

10P_0402_50V8K

1 2

PR209 0_0402_5%

1 2

H_PSI#<9>

1 2

PR223 14 7 K_0402_1%

+VCCP

12

PC222

1000P_0402_50V7K

PC225

1 2

PR241
412 K_0402_1%

1 2

PR252 0_0402_5%

PR263 0_0402_5%

1 2

8

1 2

+VCCP

PR212

1.9 1K_0402_1%

1 2

12

PR217

1.9 1 K_0402_1%

+VCCP

68_0402_5%

1 2

PR225 0_0402_5%

PR236
562_0402_1%

1 2

PR238

2.4 3 K_0402_1%

ISEN2
ISEN1

PR281

1K_0402_1%

PR290

1K_0402_1%@

PR221 1K_ 0402_5%@

1 2

PR222 0_0402_5%

1 2

PR282

1K_0402_1%

PR224

1 2

PC221

22P_ 0402_50V8J

390 P_0402_50V7K

1 2

PC224

330 P _0402_50V7K

100 0 P_0402_50V7K

12

PR210 499_0402_1%

1 2

12

12

12

0.2 2 U_0402_10V4Z

PC232

PC245

PC247

7

1
2
3
4
5
6
7
8
9

10
41

12

PC233

12

12

7

PR201 0_0402_5%

1 2

PR202 0_0402_5%

1 2

PR203 0_0402_5%

1 2

PR204 0_0402_5%

1 2

PR205 0_0402_5%

1 2

PR206 0_0402_5%

1 2

PR207 0_0402_5%

1 2

CLK_EN#

40

39

PU201

CLK_EN#
PGOOD
PSI#
RBIAS
VR_TT#
NTC
VW
COMP
FB
ISEN3
ISEN2

AGND

ISEN111VSEN12RTN13ISUM-14ISUM+15VDD

0.2 2 U_0402_10V4Z

PC248

12

330P_0402_50V7K

120 0 P_0402_50V7K

6

+VCCP

@

1 2

1 2

1K_0402_1%

PR278

PR277

@

1 2

1 2

1K_0402_1%

PR289

PR275

PC212
1U_0603_10V6K

1 2

12

PC223

1U_ 0 603_10V6K

@

1 2

1K_0402_1%

1K_0402_1%

PR279

1 2

1K_0402_1%

1K_0402_1%

PR288

+5VALW

1 2

0_0402_5%

PR228

CPU_B+

+5VALW

8.2 5K_0402_1%

1 2

1K_0402_1%

PR283

PR280

@

1 2

1K_0402_1%

PR287

PR286

PR239 0_0402_5%

PR246

1 2

1K_0402_1%

@

1 2

1K_0402_1%

1 2

12

1 2

1K_0402_1%

PR284

@

1 2

1K_0402_1%

PR285

12

PC230

0.2 2 U_0603_25V7K

VSSSENSE

VSUM+

IMVP_ IMON <9>

@

1 2

1K_0402_1%

PR276

1 2

1K_0402_1%

PR274

37

35

38

VID031VID132VID233VID334VID536VID6

VID4

VR_ON

DPRSLPVR

16

BOOT2

UGATE2

PHASE2

VSSP2

LGATE2

VCCP

PWM3

LGATE1

VSSP1

PHASE1

ISL62883HRZ-T_QFN40_5X5

VIN

IMON18BOOT119UGATE1

17

20

1 2

1 2

12

12

PC228

PC229

1U_ 0 603_10V6K

30
29
28
27
26
25
24
23
22
21

PR242 0_0402_5%

PR244 1_0402_5%

0.2 2 U_0603_25V7K

12

12

PC249

12

1 2

82.5_0402_1%

PR250

PC244

0.0 1 U_0402_25V7K

PR260

1.1 K_0402_1%

1 2

100_0402_1%

1 2

PR265

12

PC241

@27 0 0P_0402_50V7K

PC242

PR261

0_0402_5%

0.2 2 U_0603_10V7K

PR251

2.6 1K_0402_1%

0.0 4 7U_0603_16V7K

PC243

12

12

12

PR262

11K_0402_1%

PH202
10KB_0603_5%_ERTJ1VR103J

VSUM-

12

PC250

0.1 U _ 0402_16V7K

http://laptop-motherboard-schematic.blogspot.com/

6

BOOST_CPU2
UGATE_CPU2
PHASE_CPU2

LGATE_CPU2

5

PR208

0_0603_5%

12

BOO ST_CPU1

UGATE_CPU1

PR248
0_0603_5%

PHASE_CPU1

LGATE_CPU1

Securi ty Classification

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPER TY OF COMPAL ELECTR ONI CS, INC . AN D C ONT AINS CO NFID ENTI AL
AND TRADE SECRET INFORMATION. THIS SH EET MAY NOT BE TRANSFERED FRO M TH E CU STO DY O F TH E CO MPET ENT DIVI SIO N O F R& D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRO NICS, INC. NEITHE R TH IS SHEE T NO R TH E I NFOR MATI ON IT C ONTA INS

5

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRI TTEN CON SENT OF COM PAL ELEC TRO NIC S, I NC.

PC210

0.2 2 U_0603_10V7K

1 2

PR243

0_0603_5%

12

Issued Date

4

PR213

0_0603_5%

12

PC240

0.2 2 U_0603_10V7K

1 2

4

3

CPU_B+

12

12

12

PC205

10U _1206_25V6

100 0 P_0402_50V7K

578

3 6

241

PQ202
AO4474_SO8

PC203

PC204

0.1 U _0402_25V6

12

PQ203

12

PR211

4.7_1206_5%

4

TPCA8028-H_SOP-ADVANCE8-5

123 5

578

PQ205
AO4474_SO8

3 6

241

4

12

PC234

0.1 U _0402_25V6

PQ206

TPCA8028-H_SOP-ADVANCE8-5

123 5

2007/05/29 2008/05/29

Compal Secret Data

Dec iphered Date

3

12

PC211

680 P_0603_50V7K

12

PC235

100 0P_0402_50V7K

12

PR253

4.7 _1206_5%

12

PC246

680P_0603_50V7K

2

PL202

HCB2012KF-121T50_0805

12

PL205

HCB2012KF-121T50_0805

12

12

PC206

10U _1206_25V6

0.3 6 UH_PCMC1 04T -R36MN1R17_30A_20%
PL201

1

4

LF2

3

12

12

PR215

10K_0402_5%

3.6 5K_0603_1%

PR214

ISEN2

VSUM+

CPU_B+

12

12

PC237

10U _1206_25V6

PC236

10U _1206_25V6

LF1

12

12

PR256

PR255

10K_0402_5%

3.65K_0603_1%

ISEN1

VSUM+

Iccmax= 35A
I_TDC=TDB
OCP=TDBA, Intel spec=TDBA

Title

Size Document Number Re v

Date: Sheet

2

2

0.3 6 UH_PCMC1 04T -R36MN1R17_30A_20%

PL204

1

4
3

2

Compal Electronics, Inc.

+CPU_CORE

Calpella DIS LA4743P

1

B+

1

1

+

+

PC202

PC209

100U_25V_M

100U_25V_M

2

2

+VCC_CORE

V2N

12

PR216
1_0402_5%

VSUM-

+VCC_CORE

V1N

12

PR257
1_0402_5%

VSUM-

0.1

of

46 49Mond ay, April 13, 2009

1

A

1 1

PR701

0_0402_5%

DGPU_PWR_EN<14,23,39,45>

2 2

+NVVDDP

3 3

4 4

PR703

0_0402_5%

1U_0603_10V6K

PR702

316_0402_1%

12

PC702

1 2

@1000P_0402_50V7K

+5VALW

+5VALW

12

12

12

PC701

+VGA_COREP1

0_0402_5%

+NVVDD_SENSE

PR714

12

+NVVDDP

+NVVDD_SENSE

5.11K_0402_1%

12

PR713
10_0402_5%

1 2

PR708

1 2

PC713

@1000P_0402_50V7K

PR711

75K_0402_1%

PR705
255K_0402_1%

1 2

12

12

PR712

76.8K_0402_1%

PR721

0_0402_5%

12

34

2
3
4
5
6

NVVDD_PG <39>

B

1

EN_PSV

GND7PGND

PR718

1 2

38.3K_0402_1%

12

PC714

0.022U_0402_16V7K

15

TP

8

1 2

PU701

TON
VOUT
V5FILT
VFB
PGOOD

PQ713B
2N7002KDW-2N_SOT363-6

5

BST_VGA

14

VBST

DRVH

LL

TRIP

V5DRV

DRVL

TPS51117RGYR_QFN14_3.5x3.5

PQ713A
2N7002KDW-2N_SOT363-6

6 1

2

PR715

10K_0402_1%

1 2

1 2

PR704

0_0402_5%

DH_VGA

13

LX_VGA

12
11

+5VALW

10
9

DL_VGA

1 2

12

10K_0402_1%

PC715

0.022U_0402_16V7K

12

PR716
10K_0402_5%

PC706

0.1U_0402_10V7K

12

PC707

4.7U_0805_10V6K

PR717

GPU_VID0 <24>

1 2

PR707
0_0402_5%

1 2

PR706

7.15K_0402_1%

12

PR719
10K_0402_5%

C

DH _VGA_1

GPU_VID1 <24>

VGA_B+

@0.1U_0402_25V6

12

PQ701
AON7408L_DFN8-5

3 5

241

12

786

5

PQ702

4

AO4714_SO8

123

PR720

4.7_1206_5%

12

PC716
680P_0603_50V7K

4.7U_0805_25V6-K

PC708

PC703

12

0.82UH_PCMC063T-R82MN_13A_20%

PL702

1 2

GPU_VID1 GPU_VID0 +NVVDD

1

0

0

0

1

0

0.9V

0.85V

0.8V

D

PL701

HCB1608KF-121T30_0603

1 2

PC704

12

1000P_0402_50V7K

PC710

4.7U_0805_25V6-K

12

B+

12

PC705
2200P_0402_50V7K

+NVV DDP

22U_0805_6.3V6M

470U_D2_2VM_R4.5M

1

PC709

+

2

22U_0805_6.3V6M

PC712

PC711

12

12

+NVVDDP

PJP701

1 2

PAD-OPEN 4x4m
PJP702

1 2

PAD-OPEN 4x4m

A

(11A,489mils ,Via NO.= 22)

+N VVDD

http://laptop-motherboard-schematic.blogspot.com/

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.

B

2007/05/29 200810/11

Compal Secret Data

Deciphered Date

C

Title

Size Document Number R e v

Date: Sheet

Compal Electronics, Inc.

VGA_ CORE

Calpella DIS LA4743P

D

47 49Monday, April 13, 2009

of

0.1

A

1 1

B

C

D

PR901

0_0402_5%

1000P_0402_50V7K@

1 2

PC901

+1.5VP

12

PR906

0_0402_5%

+5VALW

PR903

316_0402_1%

12

+5VALW

12

12

PC907
1U_0603_10V6K

PR904
255K_0402_1%

1 2

2
3
4
5
6

PU901

TON
VOUT
V5FILT
VFB
PGOOD

1

EN_PSV

DH_1.5V_1
LX_1.5V

+5VALW
DL_1.5V

PC905

1 2

0.1U_0402_10V7K

12

1 2

PR905 0_0402_5%

1 2

PR907 13.7K_0402_1%

PC908

4.7U_0805_10V6K

DH _1.5V

PQ901
AON7408L_DFN8-5

3 5

241

PQ902
FDMC8296_POWER33-8-5

BST_1.5V

1 2

PR902

0_0402_5%

14

15

TP

VBST

13

DRVH

12

LL

11

TRIP

10

V5DRV

9

DRVL

SYSON1,37,38,39>

2 2

GND7PGND

8

3 5

241

+1.5VP

PR908

1 2

10.2K_0603_0.1%

TPS51117RGYR_QFN14_3.5x3.5

1.5V_B+

0.1U_0402_25V6
10U_1206_25V6

PC906

12

PC903

12

12

2.2UH_PCMC063T-2R2MN_8A_20%

1 2

PR909

4.7_1206_5%

1 2

PC913

680P_0603_50V8J

1 2

1000P_0402_50V7K

PC904

PL901

12

3 3

PR911

10K_0603_0.1%

+1.5VP

PJP901

1 2

PAD-OPEN 4x4m

+1.5V

(6A,240mils ,Via NO.= 12)

PL902

HCB1608KF-121T30_0603

1 2

B+

+1.5VP

1

+

PC909

1 2

OCP=9.8913(min)
MOSTemperature Factor=1.3 (100C)

PC910

2

4.7U_0805_6.3V6K
330U_B2_2.5VM_R15M

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVI SION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

http://laptop-motherboard-schematic.blogspot.com/

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.

B

2007/05/29 2008/05/29

Compal Secret Data

Deciphered Date

C

Title

Size Document Number R e v

Date: Sheet

Compal Electronics, Inc.

1.5VP

Calpella DIS LA4743P

D

48 49Monday, April 13, 2009

of

0.1

A

B

C

Version Change List ( P. I. R. List ) for Power Circuit

D

E

Request

Page#

1 1

2 2

Title

Date

Owner

Solution Description

Rev.Issue DescriptionItem

3 3

4 4

Secur i t y C lassification

Issued Date

THIS SHEET OF ENGINEERING DRA WING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND T RADE SEC RET INFOR MATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUST ODY OF THE COMPETENT DIVISION OF R&D
DEP ARTMENT EXCE PT AS AUTHO RIZED BY COMPAL ELECTRONICS, IN C. NEITHER THIS SHEET NOR THE INFORMA T ION IT CONTAINS

A

http://laptop-motherboard-schematic.blogspot.com/

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compa l Secret Data

Dec iphered Date

Title

Size Document Number Re v

Custom

D

Date: Sheet

Compal Electronics, Inc.

Power Changed-List History-1

Cal p el la D I S L A4743P

E

of

49 49Monday, April 13, 2009

0.1