MobilePenryn uFCPGA with Intel
Cantiga_GM+ICH9-M core logic
33
2008-01-01
44
Securi ty Classification
Issued Date
THIS SHEET OF ENGINEERINGDRAWINGISTHE PROPRIETARYPROPERTYOF COMPALELECTRONICS,INC. ANDCONTAINSCONFIDENTIAL
AND TRADE SECRET INFORMATION. THISSHEETMAYNOTBE TRANSFERED FROMTHE CUSTODYOF THECOMPETENT DIVISIONOF R&D
DEPARTMENT EXCEPT AS AUTHORIZEDBYCOMPALELECTRONICS,INC. NEITHERTHISSHEETNOR THEINFORMATIONIT CONTAINS
A
B
MAYB E USED BYOR DISCLOSED TOANYTHIRDPARTYWITHOUTPRIORWRITTENCONSENTOF COMPALELECTRONICS, INC.
C
2007/08/282006/03/10
Compal Secret Data
Deciphered Date
Title
Size Do cu men t Num berRe v
Cu st om
D
Da te:Sh eet
Compal Electronics, Inc.
Cover Sheet
Mo nt ev i na B l ad e U MA LA 4 101P
E
0.3
o f
146Sa turd ay, Jan uary 05 , 20 08
A
B
C
D
E
Compal confidential
11
LVDS Panel
Interface
CRT
Support V1.3
22
PCIE
CardReader
JMB385
P27
RTL8102EL
(10/100M)
HDMI
P25
P19
P18
P35
Mini-Card
WLAN
Thermal Sensor
EMC1402
Fan conn
Mini-Card
TV-tuner or
Robson
Montevina Consumer 14" UMA
Mobile Penryn
P06
P06
PCI-E BUS*5
New Card
P26P26
DMI X4
P26
uFCPGA-478 CPU
P6, 7, 8
H_A#(3..35)
H_D#(0..63)
FSB
667/800/1066 MHz 1.05V
Intel Cantiga MCH
FCBGA 1329
P9,10, 11, 12, 13, 14
C-Link
Intel ICH9-M
mBGA-676
P20,21,22,23
DDR2 667MHz 1.8V
Dual Channel
USB2.0 X12
Azalia
SATA Master-1
SATA Slave
SATA Slave
CK505
72QFN
Clock Generator
SLG8SP553V
P17
DDR2 SO-DIMM X2
BANK 0, 1, 2, 3
USB conn x1
BT Conn
USB Camera
Finger print
Codec_IDT9271B7
P15, 16
P30
P30
P19
P30
Audio CKTAMP & Audio Jack
P28P29
TPA6017A2
5 in1 Slot
33
RJ45/11 CONN
P33
P25
LPC BUS
MDC
P29
SATA HDD Connector
P24
ENE
RTC CKT.
ACCELEROMETER-1
ST
ACCELEROMETER-2
BOSCH
44
K/B backlight Conn
P21
LED
P33
P24
P24
P33
Dock
USB2.0*1
RGB
RJ45
SPDIF
CIR
MIC*1
LINE-OUT*1
Touch Pad CONN.
P33
DC/DC Interface CKT.
P36
A
P34
B
KB926
SPI ROM
25LF080A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
45@ : means need be mounted when 45 level assy or rework stage.
DEBUG@ : means just reserve for debug.
BATT @ : means need be mounted when 45 level assy or rework stage.
CONN@ : means ME part
ESATA @ : means just reserve for ESATA
GS @ : means just reserve for G sensor
FP @ : means just reserve for Finger Print
Multi @ : means just reserve for Multi Bay
NewC@ : means just reserve for New card
DOCK@ : means just reserve for Docking
Main@ : means just reserve for Main stream
OPP@ : means just reserve for OPP
2MiniC@ : means just reserve for 2nd Mini card slot
USB assignment:
USB-0 Right side
USB-1 Right side
USB-2 Left side(with ESATA)
USB-3 Dock
USB-4 Camera
USB-5 WLAN
USB-6 Bluetooth
USB-7 Finger Printer
USB-8 MiniCard(WWAN/TV)
USB-9 Express card
USB-10 X
USB-11 X
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
43154432L01 UMA GM
43154432L02 UMA GM
43154432L03 UMA
43154432L04 UMA GM
43154432L05 U
Cantiga GM45 B0(QR32)SA00001P930
ICH9M A2 ES2 Base
2007/08/282006/03/10
Compal Secret Data
Deciphered Date
::::
::::
::::
::::
::::
HEX
A0
D2
PA FF (SI-1)
PR FF (SI-1)
GL PR FF-
OPP (SI-1)
MA GL OPP
::::
::::
SA00002AN10
Title
Size Document NumberRe v
Cu stom
Da te:Sheet
ADDRESS
1 0 1 0 0 0 0 0
1 0 1 0 0 1 0 0A4
1 1 0 1 0 0 1 0
Compal Electronics, Inc.
Notes List
Montev ina Blade UMA LA4101P
0.3
o f
346Sa turday, January 05 , 20 08
5
4
3
2
1
50mA
177mA
1A
DD
VIN
AC
CC
B+
7A
+V_BATTERYDock con
0.3A
INVPWR_B+
2A
B++
LVDS CON
1.7A
+3VALW
+1.5VS
+5VALW
300mA
60mA
20mA
10mA
550mA
657mA
2.2A0.3A
1.3A0.58A
1.56A
ICH9
LAN+3VS_DVDD
+3VAUX_BT
+3VALW_EC
SPI ROM
3.39A5.89A
+3VS
50mA
25mA
35mA
1A
278mA
1.5A
JMB385
250mA
ICH_VCC1_5
ICH9
ICH9
+5VS
35mA
10mA
1A
1A
+VDDA
IDT 9271B7
+5VAMP
Finger printer
PC Camera
ALC268
MDC 1.5
New card
ICH9
+LCDVDD
LVDS CON
+3VS_CK505
Mini card (WLAN)
Mini card (TV tu/WWAN/Robeson)
1.8A
700mA
BB
3.7 X 3=11.1V
DC
BATT
B+++
AA
5
CPU_B++VCC_CORE
12.11A1.9A
4.7A
10mA2A
+1.8V
1.05V_B+
34A/1.025V
4
3.7A
8 A
50mA
+VCCP
CPU
MCH
1.8A
DDR2 800Mhz 4G x2
+0.9V
1.17A
1.26A
2.3A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CO NFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
ICH9
MCH
CPU
2007/08/282006/03/10
Compal Secret Data
Deciphered Date
2
ODD
SATA
Muti Bay
Compal Electronics, Inc.
Title
Size Doc ume nt NumberRe v
C
Mo ntevina Blade UMA LA4101P
Dat e:Sheetof
Power delivery
1
446Sat urd ay, Ja nuar y 05, 2008
0.3
A
11
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
For Merom, R14 and R15 are 0ohm
For Penryn, R14 and R15 are 100ohm.
H_ADS# <9>
H_ BNR# <9>
H_ BPRI# <9>
H_ DEFER# <9>
H_ DRDY# <9>
H_ DBS Y# <9>
H_BR0# <9>
H_ INIT# <21>
H_LOCK# <9>
H_RE SET# <9>
H_RS#0 <9>
H_RS#1 <9>
H_RS#2 <9>
H_ TRDY# <9>
H_HIT# <9>
H_HITM# <9>
R1349.9_0402_1%
R14100 _04 02_5%
R15100 _04 02_5%
H_THERMTRIP # <9,21>
CLK_CP U_BCLK <17>
CLK_CPU_BCL K# <17>
T1
Place TP with a
GND 0.1" away
XDP _DBRESET# <22>
12
12
12
H_THERMDA, H_THERMDC routing together,
Trace w idth / Spacing = 10 / 10 mil
+V CCP
H_ THERMDAH_ THERMDA _R
H_ TH ERMDC
H_ PW RGOOD<7,2 1>CLK_CPU_XDP <17>
C1 0.1U_04 02_ 16V4Z
Removed at 5/30.(Follow
Chimay)
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
* Route the TEST3 and TEST5 signals through
a ground referenced Zo = 55-ohm trace that
ends in a via that is near a GND via and is
accessible through an oscilloscope
connection.
Resistor placed within 0.5"
of CPU pin.Trace should be
at least 25 mils away from
any other toggling signal.
COMP[0,2] trace width is 18
mils. COMP[1,3] trace width
is 4 mils.
Length match within 25 mils.
The trace width/space/other is 20/7/25.
+V CC _CORE
R28100 _04 02_1%
12
R30100 _04 02_1%
12
+VCCP
10U_0805_6.3V6M
V CCSE NSE
VSSSE NSE
1
+
C6
330 U_D2E_2 .5VM_R7
2
1
C7
2
0.01U_0402_16V7K
+1.5VS
1
C8
2
Near pin B26
Close to CPU pin within
AA
Close to CPU pin AD26
within 500mils.
500mils.
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Place these capacitors on
L8 (North side,Secondary
Layer)
Place these capacitors on
L8 (North side,Secondary
Layer)
Place these capacitors on
L8 (North side,Secondary
Layer)
Place these capacitors on
L8 (North side,Secondary
Layer)
Mid Frequence Decoupling
Near CPU CORE regulator
+V CC_ CORE
C41
11/21 Change ESR=7m ohm
+V CCP
1
C45
0.1U_0402_10V6K
2
3
+V CC _CORE
1
2
+V CC _CORE
1
2
+V CC _CORE
1
2
+V CC _CORE
1
2
C9
10U_0805_6.3V6M
C17
10U_0805_6.3V6M
C25
10U_0805_6.3V6M
C33
10U_0805_6.3V6M
1
C10
10U_0805_6.3V6M
2
1
C18
10U_0805_6.3V6M
2
1
C26
10U_0805_6.3V6M
2
1
C34
10U_0805_6.3V6M
2
ESR <= 1.5m ohm
Capacitor > 1980uF
1
1
@
+
+
C42
2
2
330 U_D2_2V Y_R7M
Inside CPU center cavity in 2 rows
1
C46
0.1U_0402_10V6K
2
330 U_D2_2V Y_R7M
C43
1
2
1
+
C44
2
330 U_D2_2V Y_R7M
C47
0.1U_0402_10V6K
1
+
2
330 U_D2_2V Y_R7M
1
2
1
C11
10U_0805_6.3V6M
2
1
C19
10U_0805_6.3V6M
2
1
C27
10U_0805_6.3V6M
2
1
C35
10U_0805_6.3V6M
2
C48
0.1U_0402_10V6K
1
C1 2
10U_0805_6 .3V6M
2
1
C2 0
10U_0805_6 .3V6M
2
1
C2 8
10U_0805_6 .3V6M
2
1
C3 6
10U_0805_6 .3V6M
2
5
1
C49
0.1U_0402_10V6K
2
5
1
C13
10U_0805_6 .3V6M
2
5
1
C21
10U_0805_6 .3V6M
2
5
1
C29
10U_0805_6 .3V6M
2
5
1
C37
10U_0805_6 .3V6M
2
1
C50
0.1U_0402_10V6K
2
2
1
C14
10U_0805_6 .3V6M
2
1
C22
10U_0805_6 .3V6M
2
1
C30
10U_0805_6 .3V6M
2
1
C38
10U_0805_6 .3V6M
2
1
C15
10U_0805_6 .3V6M
2
1
C23
10U_0805_6 .3V6M
2
1
C31
10U_0805_6 .3V6M
2
1
C39
10U_0805_6 .3V6M
2
1
2
1
2
1
2
1
2
1
C16
10U_0805_6.3V6M
C24
10U_0805_6.3V6M
C32
10U_0805_6.3V6M
C40
10U_0805_6.3V6M
AA
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2007/08/282006/03/10
Compal Secret Data
Deciphered Date
Title
Size Do cument NumberRe v
Cu st om
2
Da te:Sheet
Compal Electronics, Inc.
Penryn(3/3)-AGTL+/ITP-XDP
Montev ina Blade UMA LA4101P
1
0.3
o f
846Sa turd ay, January 05, 200 8
5
H_ RCOMP
12
R54
AD14
AA13
AA11
AD11
AD10
AD13
AE12
AE14
AE11
U2A
F2
H_D#_0
G8
H_D#_1
F8
H_D#_2
E6
H_D#_3
G2
H_D#_4
H6
H_D#_5
H2
H_D#_6
F6
H_D#_7
D4
H_D#_8
H3
H_D#_9
M9
H_D#_10
M11
H_D#_11
J1
H_D#_12
J2
H_D#_13
N12
H_D#_14
J6
H_D#_15
P2
H_D#_16
L2
H_D#_17
R2
H_D#_18
N9
H_D#_19
L6
H_D#_20
M5
H_D#_21
J3
H_D#_22
N2
H_D#_23
R1
H_D#_24
N5
H_D#_25
N6
H_D#_26
P13
H_D#_27
N8
H_D#_28
L7
H_D#_29
N10
H_D#_30
M3
H_D#_31
Y3
H_D#_32
H_D#_33
Y6
H_D#_34
Y10
H_D#_35
Y12
H_D#_36
Y14
H_D#_37
Y7
H_D#_38
W2
H_D#_39
AA8
H_D#_40
Y9
H_D#_41
H_D#_42
AA9
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
AE9
H_D#_49
AA2
H_D#_50
AD8
H_D#_51
AA3
H_D#_52
AD3
H_D#_53
AD7
H_D#_54
H_D#_55
AF3
H_D#_56
AC1
H_D#_57
AE3
H_D#_58
AC3
H_D#_59
H_D#_60
AE8
H_D#_61
AG2
H_D#_62
AD6
H_D#_63
C5
H_SWING
E3
H_RCOMP
C12
H_CPURST#
E11
H_CPUSLP#
A11
H_AVREF
B11
H_DVREF
CANT IGA ES_ FCBGA1329
+VCCP
12
R47
221 _0603_1%
12
R55
100 _0402_1%
+H_SWNG
1
2
0.1U_0402_16V4Z
H_ADSTB#_0
H_ADSTB#_1
H_DEFER#
HPLL_CLK
HPLL_CLK#
H_DPWR#
HOST
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
C59
H_ D#[0..63]<7>
DD
CC
H_RE SET#<6>
H_CPUSLP#<7>
BB
Layout note:
Route H_SCOMP and H_SCOMP# with trace
width, spacing and impedance (55 ohm) same as
FSB data traces
Layout Note:
H_RCOMP / H_VREF / H_SWNG
trace width and spacing is 10/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1 = The iTPM Host Interface is disable
0 =(TLS)chiper suite with no confidentiality
1 =(TLS)chiper suite with confidentiality
Reserved
0 = Reverse Lane,15->0, 14->1
1 = Normal Operation,Lane Number in
order
0 = Enable
1 = Disable
Reserved
00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
*
Reserved
0 = Disabled
1 = Enabled
*
Reserved
0 = Normal Operation
(Lane number in Order)
1 = Reverse Lane
0 = Only PCIE or SDVO is operational.
1 = PCIE/SDVO are operating simu.
12
12
CF G16<9>
CF G19<9>
CF G20<9>
R72
R73
@
R75
@
(Default)11 = Normal Operation
*
*
*
*
12
4.02K_0402_1%
12
4.02K_0402_1%
12
4.02K_0402_1%
*
*
+3VS
R76
@
@
@
@
@
R77
R78
R80
R82
R85
R87
12
2.21K_0402_1%
12
2.21K_0402_1%
12
2.21K_0402_1%
12
2.21K_0402_1%
12
2.21K_0402_1%
12
2.21K_0402_1%
12
2.21K_0402_1%
o f
1146Saturday, January 05, 2008
0.3
Solve 3G WWAN issue
LVDS_A CLK+<19>
LVDS_A CLK-<19>
LVDS_A0+<19>
LVDS_A0-<19>
LVDS_A1+<19>
LVDS_A1-<19>
LVDS_A2+<19>
AA
LVDS_A2-<19>
LVDS_A CLK+
LVDS_A CLKLVDS_A0+
LVDS_A0LVDS_A1+
LVDS_A1LVDS_A2+
LVDS_A2-
5
1
@
C60
0.1U_0402_10V6K
2
1
@
C61
0.1U_0402_10V6K
2
1
@
C62
0.1U_0402_10V6K
2
1
@
C63
0.1U_0402_10V6K
2
R79
@
CF G6<9>
CF G7<9>
CF G8<9>
CF G9<9>
CF G10<9>
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2007/08/282006/03/10
Compal Secret Data
Deciphered Date
2
12
2.21K_0402_1%
R81
12
2.21K_0402_1%
R83
@
12
2.21K_0402_1%
R84
@
12
2.21K_0402_1%
R86
@
12
2.21K_0402_1%
Title
Cantiga(3/6)-VGA/LVDS/TV
Size Do cument NumberRe v
Cu st om
Montev ina Blade UMA LA4101P
Da te:Sheet
CF G11<9>
CF G12<9>
CF G13<9>
CF G14<9>
CF G15<9>
CF G17<9>
CF G18<9>
Compal Electronics, Inc.
1
5
+3VS_DAC_BG
0.022U_0402_16V7K
12
@
0_0603_5%
C68
R89
DD
+3VS_DAC_CRT
C75
12
0_0603_5%
@
R92
+1.5VS
+VCCP
CC
BB
C69
1
2
0.022U_0402_16V7K
C76
1
2
+3VS
220 U_D2_4VM
R103
12
0_0603_5%
1U_0603_10V4Z
0.1U_0402_16V4Z
C70
1
1
2
2
R91
12
BLM18PG181SN1D_0603
0.1U_0402_16V4Z
1
2
R96
@
12
0_0603_5%
R97
12
0_0603_5%
1
C94
+
2
C102
+3VS
R88
12
BLM18PG181SN1D_0603
10U_0805_10V4Z
+3VS
1
C89
0.1 U_0402_16V4Z
2
R100
12
0_0805_5%
C95
1
2
+1.05VS_A_SM_CK
C103
1
1
2
2
Check Again!!!
+1.8V_TXLVDS
+1.5VS_PEG_BG
+1.05VS_A_SM
10U_0805_10V4Z
C96
4.7 U_0805_10V4Z
1U_0603_10V4Z
10U_0805_10V4Z
C104
1
2
**RED Mark: Means UMA & dis@ Power select**
~It check by INTEL Graphics Disable
Guidelines~
+3VS_DAC_CRT
+3VS_DAC_BG
+1.05VS_DPLLA
+1.05VS_DPLLB
+1.05VS_HPLL
+1.05VS_MPLL
1
C88
1000P_0402_50V7K
2
+1.05VS_PEGPLL
1
1
C97
2
2
1U_0603_10V4Z
0.1U_0402_16V4Z
C105
1
2
+3VS_TVDAC
+1.5VS
+1.5VS_TVDAC
+1.5VS_Q DAC
+1.05VS_HPLL
+1.05VS_PEGPLL
+1.8V_LVDS
4
U2 H
73mA
B27
VCCA_CRT_DAC
A26
VCCA_CRT_DAC
2.68mA
A25
VCCA_DAC_BG
B25
VSSA_DAC_BG
F47
VCCA_DPLLA
L48
VCCA_DPLLB
AD1
VCCA_HPLL
AE1
VCCA_MPLL
13.2mA
J48
VCCA_LVDS
J47
VSSA_LVDS
414uA
AD48
VCCA_PEG_BG
50mA
AA48
VCCA_PEG_PLL
AR20
VCCA_SM
AP20
VCCA_SM
AN20
VCCA_SM
AR17
VCCA_SM
AP17
VCCA_SM
AN17
VCCA_SM
AT16
VCCA_SM
AR16
VCCA_SM
AP16
VCCA_SM
AP28
VCCA_SM_CK
AN28
VCCA_SM_CK
AP25
VCCA_SM_CK
AN25
VCCA_SM_CK
AN24
VCCA_SM_CK
AM28
VCCA_SM_CK_NCTF
AM26
VCCA_SM_CK_NCTF
AM25
VCCA_SM_CK_NCTF
AL25
VCCA_SM_CK_NCTF
AM24
VCCA_SM_CK_NCTF
AL24
VCCA_SM_CK_NCTF
AM23
VCCA_SM_CK_NCTF
AL23
VCCA_SM_CK_NCTF
B24
VCCA_TV_DAC
A24
VCCA_TV_DAC
A32
VCC_HDA
M25
VCCD_TVDAC
L28
VCCD_QDAC
AF1
VCCD_HPLL
AA47
VCCD_PEG_PLL
M38
VCCD_LVDS
L37
VCCD_LVDS
60.31mA
CANT IGA ES_FCBGA1329
CRTPLLA PEGA SMTV
64.8mA
64.8mA
24mA
139.2mA
A LVDSHDA
720mA
26mA
26mA
TVA 2 4.15mA
TVB 3 9.48mA
TVX 2 4.15mA
50mA
58.67mA
48.363mA
157.2mA
50mA
LVDS
852mA
POWER
A CK
105.3mA
1732mA
D TV/CRT
DMI
456mA
VTT
321.35mA
VCC_AXF
VCC_AXF
VCC_AXF
AXF
124mA
VCC_SM_CK
VCC_SM_CK
VCC_SM_CK
VCC_SM_CK
SM CK
118.8mA
VCC_TX_LVDS
VCC_HV
VCC_HV
VCC_HV
HV
VCC_PEG
VCC_PEG
VCC_PEG
VCC_PEG
PEG
VCC_PEG
VCC_DMI
VCC_DMI
VCC_DMI
VCC_DMI
VTTLF
VTTLF
VTTLF
VTTLF
3
+VCCP
U13
VTT
T13
VTT
U12
VTT
T12
VTT
U11
VTT
T11
VTT
U10
VTT
T10
VTT
U9
VTT
T9
VTT
U8
VTT
T8
VTT
U7
VTT
T7
VTT
U6
VTT
T6
VTT
U5
VTT
T5
VTT
V3
VTT
U3
VTT
V2
VTT
U2
VTT
T2
VTT
V1
VTT
U1
VTT
B22
B21
A21
BF21
BH20
BG20
BF20
K47
C35
B35
A35
V48
U48
V47
U47
U46
AH48
AF48
AH47
AG47
A8
L1
AB2
C110
0.47U_0603_10V7K
+V1.05VS_AXF
+1.8V_SM_CK
+1.8V_TXLVDS
+VCC_PEG
+1. 05VS_DMI
0.47U_0603_10V7K
C111
1
2
1
C71
+
2
1
C80
2
C112
1
2
4.7U_0805_10V4Z
220U_6.3V_M
C72
1
2
4.7U_0805_10V4Z
0.47U_0603_10V7K
C81
+3VS_HV
C107
0.47U_0603_10V7K
1
2
2.2U_0805_16V4Z
1
1
C82
2
2
0.1U_0402_16V4Z
1
2
+1.05VS_DPLLA
@
220U_D2_4VM
1
C77
+
2
0.1U_0402_16V4Z
C86
1
2
0.1 U_0402_16V4Z
C73
1
2
C87
1
2
+1.05VS_PEGPLL
2
12
R90
10U_0805_10V4Z
0.1U_0402_16V4Z
10U_0805_10V4Z
+1.05VS_HPLL
+1.05VS_MPLL
C99
10U_FLC-453232-100K_0.25A_10%
C74
1
2
R94
12
10U_FLC-453232-100K_0.25A_10%
0.1U_0402_16V4Z
C90
C91
1
1
2
2
1
2
10U_0805_10V4Z
0.1U_0402_16V4Z
C106
1
2
+VCCP+1.05VS_DPLLB
R98
12
MBK2012121YZF_0805
10U_0805_10V4Z
R101
12
MBK2012121YZF_0805
1
C100
10U_0805_10V4Z
2
L1
12
BLM18PG121SN1D_0603
C108
1
2
+VCCP
+3VS
+VCCP
+VCCP
+VCCP
+VCCP
+VCCP_D
D3
21
CH751H-40PT_SO D323-2
@
C83
R105
12
10_0402_5%
+V1.05VS_AXF
10U_0805_10V4Z
+1.8V_SM_CK
10U_0805_10V4Z
C84
1
2
+1.5VS_TVDAC
C92
+VCC_PEG
C98
+1.05VS_DMI
C78
1
2
10U_0805_10V4Z
1
2
0.022U_0402_16V7K
1
2
220U_D2_4VM
1
+
2
C109
1
2
R106
12
0_0402_5%
1
C93
C101
R104
12
0_0603_5%
0.1U_0402_16V4Z
+VCCP
R93
12
1U_0603_10V4Z
0_0603_5%
C79
1
2
+1.8V
R95
0.1U_0402_16V4Z
12
0_0805_5%
C85
1
2
+1.5VS
R99
12
0.1U_0402_16V4Z
0_0805_5%
R102
12
0_0805_5%
+VCCP
+3VS_HV
+VCCP
1
2
10U_0805_10V4Z
1
2
+1.8V_LVDS
R107
12
1U_0603_10V4Z
10U_0805_10V4Z
@
R109
12
0_0603_5%
1
2
2
@
R114
12
0_0603_5%
+1.5VS_Q DAC
0.022U_0402_16V7K
C119
1
2
0.1U_0402_16V4Z
C120
@
220U_D2_4VM
1
1
2
C121
+
2
4
+3VS_TVDAC
@
AA
R113
0.022U_0402_16V7K
12
0_0603_5%
C117
1
2
0.1U_0402_16V4Z
C118
1
2
R111
12
BLM18PG181SN1D_0603
5
+3VS
R112
12
100_0603_1%
+1.5VS
Se curity Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Layout Note:
Place one cap close to every 2
pullup
resistors terminated to +0.9VS
+0.9V
0.1U_0402_16V4Z
1
2
C158
DDR_A_MA8
DDR_A_ MA5
DDR_A_ MA1
DDR_A_ MA3
DD R_A _RAS#
DDR_CS0_ DIMMA#
DDR_A_ BS0
DDR_A_MA 10
DD R_A _CAS#
DDR_A_WE#
DDR_CS1_ DIMMA#
M_ODT1
DDR_A_MA11
2.2U_0805_16V4Z
2.2U_0805_16V4Z
C154
1
2
510
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C162
RP256_ 040 4_4P2R_5%
RP456_ 040 4_4P2R_5%
RP656_ 040 4_4P2R_5%
RP856_ 040 4_4P2R_5%
RP10 56_ 040 4_4P2R_5%
RP12 56_ 040 4_4P2R_5%
RP13 56_ 040 4_4P2R_5%
C155
1
2
0.1U_0402_16V4Z
1
1
2
2
C164
C163
DDR_A_ BS2
14
DDR_CKE0_DIMMA
23
DDR_A_ MA7
14
DDR_A_MA6
23
DDR_A_MA 12
14
DDR_A_ MA9
23
DDR_A_ MA4
14
DDR_A_ MA2
23
DDR_A_ MA0
14
DDR_A_ BS1
23
M_ODT0
14
DDR_A_MA 13
23
DDR_CKE1_DIMMA
14
DDR_A_MA 14
23
0.1U_0402_16V4Z
C156
1
2
0.1U_0402_16V4Z
1
2
C165
0.1U_0402_16V4Z
4
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C166
C149
C148
1
1
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C167
330 U_D2E_2 .5VM_R7
0.1U_0402_16V4Z
1
2
C168
1
C157
1
+
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C170
C169
Layout Note:
Place these resistor
closely JP3,all
trace length Max=1.5"
C150
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SEC RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.