HP LA-4732P, Compaq Presario CQ35, Pavilion dv3 Schematic

A

1 1

2 2

B

C

D

E

Compal confidential

Schematics Document

Mobile Penryn uFCPGA with Intel
Cantiga_GM+ICH9-M core logic

3 3

2009-02-16

REV:1.0

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet of

Compal Electronics, Inc.

Cover Sheet

Montevina UMA

E

1 46Wednesday, February 18, 2009

0.1

A

B

C

D

E

Compal confidential

1 1

LVDS Panel
Interface

CRT

Support V1.3

2 2

HDMI

RTL8103EL
(10/100M)

P25

P19

P18

P35

Mini-Card

WLAN WWAN

RJ45/11 CONN

3 3

P25

Thermal Sensor
EMC1402

Fan conn

Mini-Card

Montevina Consumer UMA

Mobile Penryn

P06

P06

PCI-E BUS*4

New Card

P26P26

DMI X4

P26

uFCPGA-478 CPU

P6, 7, 8

H_A#(3..35)

H_D#(0..63)

FSB

667/800/1066 MHz 1.05V

Intel Cantiga MCH

FCBGA 1329
GM47

P9,10, 11, 12, 13, 14

C-Link

Intel ICH9-M

mBGA-676

P20,21,22,23

LPC BUS

CK505

Clock Generator
SLG8SP553V

DDR2 800MHz 1.8V

Dual Channel

USB2.0 X12

Azalia

SATA Master-1

SATA Slave

SATA Slave

72QFN

P17

DDR2 SO-DIMM X2

BANK 0, 1, 2, 3

USB conn x1

BT Conn

USB Camera

Finger print

CardReader

P15, 16

P30

P30

P19

P30

5 in1 Slot

P27

Audio CKT AMP & Audio Jack

Codec_IDT92HD75B

MDC

P28 P29

P28

TPA6047

P27

SATA HDD Connector

P24

ENE

KB926

RTC CKT.

P21

LED

P33

ACCELEROMETER-1
ST

4 4

P24

Touch Pad CONN.

P33

SPI ROM
SST25VF080

P31

P32

Int.KBD

SPI

P32

K/B backlight Conn

P33

DC/DC Interface CKT.

A

P36

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2006/02/13 2006/03/10

Compal Secret Data

Deciphered Date

SATA ODD Connector

e-SATA Connector

Custom

D

P24

P30

USB Board Conn
USB port x2

Capsense switch Conn

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Block Diagram

Montevina UMA

E

2 46Wednesday, February 18, 2009

P30

P33

0.1

A

Symbol Note :

Voltage Rails

power
plane

State

S0

S1

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

1 1

O MEANS ON X MEANS OFF

+B

O

O

O

O

O

+5VALW

+3VALW

O

O

O

O

X

XX

+1.5V

: means Digital Ground

: means Analog Ground

+5VS
+3VS
+1.5VS
+0.75V
+VCCP
+CPU_CORE
+2.5VS
+1.8V

O

O

O

X

X

X

O

O

X

X

X

X

@ : means just reserve , no build

45@ : means need be mounted when 45 level assy or rework stage.

DEBUG@ : means just reserve for debug.

BATT @ : means need be mounted when 45 level assy or rework stage.
CONN@ : means ME part

ESATA @ : means just reserve for ESATA

GS @ : means just reserve for G sensor
FP @ : means just reserve for Finger Print

Multi @ : means just reserve for Multi Bay
NewC@ : means just reserve for New card

Main@ : means just reserve for Main stream
OPP@ : means just reserve for OPP
2MiniC@ : means just reserve for 2nd Mini card slot

PA @ : means just reserve for PA
PR @ : means just reserve for PR

USB assignment:

USB-0 Right side(with eSATA)
USB-1 Left side
USB-2 Left side
USB-3 Cardreader
USB-4 Camera
USB-5 WLAN
USB-6 Bluetooth
USB-7 Finger Printer
USB-8 MiniCard(WWAN/TV)
USB-9 Express card
USB-10 X
USB-11 X

PCIe assignment:

PCIe-1 WWAN
PCIe-2 X
PCIe-3 WLAN

PCIe-4 GLAN (Realtek)

PCIe-5 X

PCIe-6 New Card

I2C / SMBUS ADDRESSING

HEX

A0

D2

ADDRESS

1 0 1 0 0 0 0 0
1 0 1 0 0 1 0 0A4
1 1 0 1 0 0 1 0

DEVICE

DDR SO-DIMM 0
DDR SO-DIMM 1
CLOCK GENERATOR (EXT.)

SMBUS Control Table

SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
SMB_CK_CLK1
SMB_CK_DAT1
LCD_CLK
LCD_DAT

SOURCE

KB926

KB926

ICH9

Cantiga

INVERTER

X
X
X
X

BATT

V

X
X
X

SERIAL
EEPROM

Thermal
Sensor

V

X
X
X

X

V

X
X

SODIMM CLK CHIP

X
X

X

X

V V V

X

X

MINI CARD

X
X

X

LCD

X
X
X

V

Cap sensor
board

V

X
X
X

NEW CARD G sensor

X X
X

X

V V

X

X

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

Custom

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

Notes List

Montevina UMA

3 46Wednesday, February 18, 2009

0.1

5

4

3

2

60mA

+3VAUX_BT

1

50mA

1A

0.3A

2A

+V_BATTERY

INVPWR_B+

B++

LVDS CON

1.7A

+3VALW

+1.5VS

+5VALW

177mA

300mA

ICH9

LAN

3.39A5.89A

+3VS

RT5158

657mA

2.2A0.3A

1.3A0.58A

1.56A

ICH_VCC1_5
ICH9

ICH9

+5VS

35mA

10mA

D D

VIN

AC

C C

B+

7A

25mA

20mA

10mA

1A

278mA

1.5A

250mA

1A

1A

+VDDA
IDT 9275B

+5VAMP

Finger printer

+3VS_DVDD
ALC268

+3VALW_EC

SPI ROM

New card

ICH9

+LCDVDD

LVDS CON

+3VS_CK505

Mini card (WLAN)

Mini card (TV tu/WWAN/Robeson)

1.8A

B B

3.7 X 3=11.1V

DC BATT

B+++

A A

5

CPU_B+ +VCC_CORE

12.11A1.9A

4.7A

10mA2A

+1.8V

1.05V_B+

34A/1.025V

4

3.7A

50mA

+VCCP

CPU

MCH

DDR2 800Mhz 4G x2

+0.9V

1.17A

1.26A

2.3A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

ICH9

MCH

CPU

2007/08/28 2006/03/10

700mA

50mA

Compal Secret Data

Deciphered Date

ODD

SATA

PC Camera(4.75V)

2

Compal Electronics, Inc.

Title

Size Document Number Rev

C

Montevina UMA

Date: Sheet of

Power delevry

1

4 46Wednesday, February 18, 2009

0.1

A

1 1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Notes List

Montevina UMA

5 46Wednesday, February 18, 2009

0.1

5

4

3

2

1

ITP-XDP Connector

+VCCP

XDP_TDI

D D

XDP_TMS

XDP_TDO

R2 54.9_0402_1%

1 2

R3 54.9_0402_1%

1 2

R4 54.9_0402_1%

1 2

H_A#[3..16]9

H_ADSTB#09

H_REQ#09
H_REQ#19
H_REQ#29
H_REQ#39
H_REQ#49

C C

B B

A A

H_A#[17..35]9

H_ADSTB#19

H_A20M#21

H_FERR#21

H_IGNNE#21

H_STPCLK#21
H_INTR21
H_NMI21
H_SMI#21

+VCCP

B

H_PROCHOT# OCP#

H_IERR#

E

3 1

Q1

@

MMBT3904_NL_SOT23-3

+VCCP

12

@

R17
56_0402_5%

2

C

R18
56_0402_5%

1 2

5

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1

H_A20M#
H_FERR#
H_IGNNE#

H_STPCLK#
H_INTR
H_NMI
H_SMI#

J4
L5
L4

K5

M3

N2

J1
N3
P5
P2

L2
P4
P1
R1

M1

K3
H2
K2

J3

L1

Y2
U5
R3

W6

U4
Y5
U1
R4
T5
T3

W2
W5

Y4
U2
V4

W3
AA4
AB2
AA3

V1

A6
A5
C4

D5
C6
B4
A3

M4

N5
T2
V3
B2
D2

D22

D3
F6

OCP# 22

JCPU1A

A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#

REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#

A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#

A20M#
FERR#
IGNNE#

STPCLK#
LINT0
LINT1
SMI#

RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]

Penryn

ADDR GROUP_0

ADDR GROUP_1

THERMAL

ICH

THERMTRIP#

RESERVED

ADS#
BNR#
BPRI#

DEFER#

DRDY#
DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

RESET#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HIT#

HITM#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#
PREQ#

TCK

TDO
TMS

TRST#

DBR#

XDP/ITP SIGNALS

PROCHOT#

THERMDA
THERMDC

H CLK

BCLK[0]
BCLK[1]

H_ADS#

H1

H_BNR#

E2

H_BPRI#

G5

H_DEFER#

H5

H_DRDY#

F21

H_DBSY#

E1

H_BR0#

F1

H_IERR#

D20

H_INIT#

B3

H_LOCK#

H4

H_RESET#

C1

H_RS#0

F3

H_RS#1

F4

H_RS#2

G3

H_TRDY#

G2

H_HIT#

G6

H_HITM#

E4

AD4
AD3
AD1
AC4
AC2
AC1

XDP_TCK

AC5

XDP_TDI

AA6

TDI

AB3
AB5
AB6
C20

D21
A24
B25

C7

A22
A21

XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#

H_PROCHOT#

H_THERMDC_R

H_THERMTRIP#

CLK_CPU_BCLK
CLK_CPU_BCLK#

H_ADS# 9
H_BNR# 9

H_BPRI# 9

H_DEFER# 9
H_DRDY# 9
H_DBSY# 9

H_BR0# 9

H_INIT# 21

H_LOCK# 9

H_RESET# 9

H_RS#0 9

H_RS#1 9

H_RS#2 9

H_TRDY# 9

H_HIT# 9
H_HITM# 9

R13 56_0402_1%

R14 0_0402_5%
R15 0_0402_5%

H_THERMTRIP# 9,21

CLK_CPU_BCLK 17
CLK_CPU_BCLK# 17

T1

Place TP with a
GND 0.1" away

XDP_DBRESET# 22

1 2

1 2
1 2

H_THERMDA, H_THERMDC routing
together, Trace width / Spacing = 10 / 10
mil

+VCCP

H_THERMDAH _THERMDA_R
H_THERMDC

+3VS

+3VS

0.1U_0402_16V4Z

C3

1 2

2200P_0402_50V7K

R16

1 2

10K_0402_5%

1

C2

2

H_THERMDA

H_THERMDC

THERM#

U1

1

VDD

2

DP

3

DN

4

THERM#

EMC1402-1-ACZL-TR_MSOP8

Address:100_1100

Fan Control circuit

SI-1 Change to voltage control circuit

+5VS

+3VS

R1209

10K_0402_5%

1 2

1000P_0402_50V7K

3

FAN_SPEED

1

C1510

2

2007/08/28 2006/03/10

FAN_SPEED32

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

9

Thermal Pad

8

GND

7

GND

6

GND

5

GND

G996RD1U_TDFN8_3X3

Compal Secret Data

VEN

VIN

VO

VSET

FAN_SET32

Deciphered Date

U51

1
2
3
4

1

C4 2.2U_0603_6.3V4Z

2

+5VS_FAN

1

C1509

2.2U_0603_6.3V4Z

2

2

XDP_TRST#

XDP_TCK

This shall place near CPU

SMCLK

SMDATA

ALERT#

GND

+5VS

Title

Size Document Number Rev

Custom

Date: Sheet of

R7 54.9_0402_1%

1 2

R8 54.9_0402_1%

1 2

SMB_EC_CK2

8

SMB_EC_DA2

7

R6 10K_0402_5%

6

1 2

5

1

C5

0.1U_0402_16V4Z

2

CONN@

JFAN1

1

1

2

2

3

3

ACES_85204-03001

D63

3

Vcc

2

Line to be protected

1

GND

DLPT05-7-F_SOT23-3

FAN_SPEED

Compal Electronics, Inc.

Penryn(1/3)-AGTL+/ITP-XDP

Montevina UMA

1

SMB_EC_CK2 32

SMB_EC_DA2 32

+3VS

4

G1

5

G2

6 46Wednesday, February 18, 2009

0.1

5

4

3

2

1

H_D#[0..15]9

D D

H_DSTBN#09
H_DSTBP#09
H_DINV#09
H_D#[16..31]9

C C

* Route the TEST3 and TEST5 signals through
a ground referenced Zo = 55-ohm trace that
ends in a via that is near a GND via and is
accessible through an oscilloscope
connection.

B B

CPU_BSEL CPU_BSEL2 CPU_BSEL1

R21 1K_0402_5%@
R22 1K_0402_5%@

166

H_DSTBN#19
H_DSTBP#19
H_DINV#19

1 2
1 2

CPU_BSEL017
CPU_BSEL117

T2
T3
T4
T5
T6

0 1

200

266

0 0

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1

+V_CPU_GTLREF

TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

10

JCPU1B

E22

D[0]#

F24

D[1]#

E26

D[2]#

G22

D[3]#

F23

D[4]#

G25

D[5]#

E25

D[6]#

E23

D[7]#

K24

D[8]#

G24

D[9]#

J24

D[10]#

J23

D[11]#

H22

D[12]#

F26

D[13]#

K22

D[14]#

H23

D[15]#

J26

DSTBN[0]#

H26

DSTBP[0]#

H25

DINV[0]#

N22

D[16]#

K25

D[17]#

P26

D[18]#

R23

D[19]#

L23

D[20]#

M24

D[21]#

L22

D[22]#

M23

D[23]#

P25

D[24]#

P23

D[25]#

P22

D[26]#

T24

D[27]#

R24

D[28]#

L25

D[29]#

T25

D[30]#

N25

D[31]#

L26

DSTBN[1]#

M26

DSTBP[1]#

N24

DINV[1]#

AD26

GTLREF

C23

TEST1

D25

TEST2

C24

TEST3

AF26

TEST4

AF1

TEST5

A26

TEST6

C3

TEST7

B22

BSEL[0]

B23

BSEL[1]

C21

BSEL[2]

Penryn

CPU_BSEL0

H_D#32

Y22

MISC

DATA GRP 0

DATA GRP 1

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#

DATA GRP 2DATA GRP 3

D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#

D[47]#
DSTBN[2]#
DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]#
DSTBN[3]#
DSTBP[3]#

DINV[3]#

COMP[0]
COMP[1]
COMP[2]
COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#
PSI#

AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

R26
U26
AA1
Y1

E5
B5
D24
D6
D7
AE6

H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3

COMP0
COMP1
COMP2
COMP3

H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGOOD
H_CPUSLP#
H_PSI#

1

0

0

H_D#[32..47] 9

H_DSTBN#2 9
H_DSTBP#2 9
H_DINV#2 9
H_D#[48..63] 9

H_DSTBN#3 9
H_DSTBP#3 9
H_DINV#3 9

H_DPRSTP# 9,21,42

H_DPSLP# 21
H_DPWR# 9
H_PWRGOOD 21

H_CPUSLP# 9
H_PSI# 42CPU_BSEL217

R23

12

54.9_0402_1%

Resistor placed within 0.5"
of CPU pin.Trace should be
at least 25 mils away from
any other toggling signal.
COMP[0,2] trace width is 18
mils. COMP[1,3] trace width
is 4 mils.

+V_CPU_GTLREF

27.4_0402_1%

12

+VCCP

12

54.9_0402_1%

12

R27
1K_0402_1%

12

R29
2K_0402_1%

R25

R24

27.4_0402_1%

+VCC_CORE +VCC_CORE

R26

12

AA10
AA12
AA13
AA15
AA17
AA18
AA20

AC10
AB10
AB12
AB14
AB15
AB17
AB18

JCPU1C

A7

VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]

Penryn

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

VCCA[01]
VCCA[02]

VCCSENSE

VSSSENSE

A9
A10
A12
A13
A15
A17
A18
A20

B7

B9
B10
B12
B14
B15
B17
B18
B20

C9
C10
C12
C13
C15
C17
C18

D9
D10
D12
D14
D15
D17
D18

E7

E9
E10
E12
E13
E15
E17
E18
E20

F7

F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9

AB9

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

AF20

+VCCPA

G21

+VCCPB

V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

AF7

AE7

.

1 2
1 2

VCCSENSE

VSSSENSE

R19

0_0402_5%
0_0402_5%

R20

CPU_VID0 42
CPU_VID1 42
CPU_VID2 42
CPU_VID3 42
CPU_VID4 42
CPU_VID5 42
CPU_VID6 42

VCCSENSE 42

VSSSENSE 42

Length match within 25 mils.
The trace width/space/other is 20/7/25.

+VCC_CORE

R28 100_0402_1%

1 2

R30 100_0402_1%

1 2

+VCCP

10U_0805_6.3V6M

VCCSENSE

VSSSENSE

1

+

C6
330U_D2E_2.5VM_R7

2

1

C7

2

0.01U_0402_16V7K

+1.5VS

1

C8

2

Near pin B26

Close to CPU pin within

A A

Close to CPU pin AD26
within 500mils.

500mils.

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet of

Compal Electronics, Inc.

Penryn(2/3)-AGTL+/ITP-XDP

Montevina UMA

1

7 46Wednesday, February 18, 2009

0.1

5

D D

JCPU1D

A4

VSS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

AF2

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

VSS[025]

D1

VSS[026]

D4

VSS[027]

D8

VSS[028]

D11

C C

B B

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080]
VSS[081]P3VSS[162]

Penryn

VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]

VSS[163]

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

.

4

Place these capacitors on
L8 (North side,Secondary
Layer)

Place these capacitors on
L8 (North side,Secondary
Layer)

Place these capacitors on
L8 (North side,Secondary
Layer)

Place these capacitors on
L8 (North side,Secondary
Layer)

Mid Frequence Decoupling

Near CPU CORE regulator

+VCC_CORE

C41

+VCCP

1

C45

0.1U_0402_10V6K

2

3

+VCC_CORE

1

2

+VCC_CORE

1

2

+VCC_CORE

1

2

+VCC_CORE

1

2

C9

10U_0805_6.3V6M

C17

10U_0805_6.3V6M

C25

10U_0805_6.3V6M

C33

10U_0805_6.3V6M

1

C10

10U_0805_6.3V6M

2

1

C18

10U_0805_6.3V6M

2

1

C26

10U_0805_6.3V6M

2

1

C34

10U_0805_6.3V6M

2

ESR <= 1.5m ohm
Capacitor > 1980uF

1

1

@

+

C42

2

2

330U_D2_2VY_R7M

Inside CPU center cavity in 2 rows

1

C46

0.1U_0402_10V6K

2

1

+

C43

330U_D2_2VY_R7M

1

2

+

C44

2

330U_D2_2VY_R7M

C47

0.1U_0402_10V6K

1

+

2

330U_D2_2VY_R7M

1

C11

10U_0805_6.3V6M

2

1

C19

10U_0805_6.3V6M

2

1

C27

10U_0805_6.3V6M

2

1

C35

10U_0805_6.3V6M

2

1

C48

0.1U_0402_10V6K

2

1

C12

10U_0805_6.3V6M

2

1

C20

10U_0805_6.3V6M

2

1

C28

10U_0805_6.3V6M

2

1

C36

10U_0805_6.3V6M

2

1

C49

0.1U_0402_10V6K

2

1

C13

10U_0805_6.3V6M

2

1

C21

10U_0805_6.3V6M

2

1

C29

10U_0805_6.3V6M

2

1

C37

10U_0805_6.3V6M

2

1

C50

0.1U_0402_10V6K

2

2

1

C14

10U_0805_6.3V6M

2

1

C22

10U_0805_6.3V6M

2

1

C30

10U_0805_6.3V6M

2

1

C38

10U_0805_6.3V6M

2

1

C15

10U_0805_6.3V6M

2

1

C23

10U_0805_6.3V6M

2

1

C31

10U_0805_6.3V6M

2

1

C39

10U_0805_6.3V6M

2

1

2

1

2

1

2

1

2

1

C16

10U_0805_6.3V6M

C24

10U_0805_6.3V6M

C32

10U_0805_6.3V6M

C40

10U_0805_6.3V6M

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet of

Compal Electronics, Inc.

Penryn(3/3)-AGTL+/ITP-XDP

Montevina UMA

1

8 46Wednesday, February 18, 2009

0.1

5

H_RCOMP

12

R54

AD14

AA13

AA11
AD11
AD10
AD13
AE12

AE14

AE11

U2A

F2

H_D#_0

G8

H_D#_1

F8

H_D#_2

E6

H_D#_3

G2

H_D#_4

H6

H_D#_5

H2

H_D#_6

F6

H_D#_7

D4

H_D#_8

H3

H_D#_9

M9

H_D#_10

M11

H_D#_11

J1

H_D#_12

J2

H_D#_13

N12

H_D#_14

J6

H_D#_15

P2

H_D#_16

L2

H_D#_17

R2

H_D#_18

N9

H_D#_19

L6

H_D#_20

M5

H_D#_21

J3

H_D#_22

N2

H_D#_23

R1

H_D#_24

N5

H_D#_25

N6

H_D#_26

P13

H_D#_27

N8

H_D#_28

L7

H_D#_29

N10

H_D#_30

M3

H_D#_31

Y3

H_D#_32
H_D#_33

Y6

H_D#_34

Y10

H_D#_35

Y12

H_D#_36

Y14

H_D#_37

Y7

H_D#_38

W2

H_D#_39

AA8

H_D#_40

Y9

H_D#_41
H_D#_42

AA9

H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48

AE9

H_D#_49

AA2

H_D#_50

AD8

H_D#_51

AA3

H_D#_52

AD3

H_D#_53

AD7

H_D#_54
H_D#_55

AF3

H_D#_56

AC1

H_D#_57

AE3

H_D#_58

AC3

H_D#_59
H_D#_60

AE8

H_D#_61

AG2

H_D#_62

AD6

H_D#_63

C5

H_SWING

E3

H_RCOMP

C12

H_CPURST#

E11

H_CPUSLP#

A11

H_AVREF

B11

H_DVREF

CANTIGA ES_FCBGA1329

+VCCP

12

221_0603_1%

12

100_0402_1%

H_ADSTB#_0
H_ADSTB#_1

H_BREQ#

H_DEFER#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

HOST

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

R47

+H_SWNG

1

C59

R55

2

0.1U_0402_16V4Z

H_D#[0..63]7

D D

C C

H_RESET#6

H_CPUSLP#7

B B

Layout note:

Route H_SCOMP and H_SCOMP# with trace
width, spacing and impedance (55 ohm) same as
FSB data traces

Layout Note:
H_RCOMP / H_VREF / H_SWNG
trace width and spacing is 10/20

+VCCP

12

R46

1K_0402_1%

A A

12

R52

2K_0402_1%

0.1U_0402_16V4Z

+H_VREF

1

C58

2

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

+H_SWNG
H_RCOMP

H_RESET#
H_CPUSLP#

+H_VREF

24.9_0402_1%

Near B3 pinwithin 100 mils from NB

5

4

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31

H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADS#

H_BNR#
H_BPRI#

H_DBSY#

H_HIT#

H_HITM#
H_LOCK#
H_TRDY#

H_RS#_0

H_RS#_1

H_RS#_2

H_A#4

C15

H_A#5

F16

H_A#6

H13

H_A#7

C18

H_A#8

M16

H_A#9

J13

H_A#10

P16

H_A#11

R16

H_A#12

N17

H_A#13

M13

H_A#14

E17

H_A#15

P17

H_A#16

F17

H_A#17

G20

H_A#18

B19

H_A#19

J16

H_A#20

E20

H_A#21

H16

H_A#22

J20

H_A#23

L17

H_A#24

A17

H_A#25

B17

H_A#26

L16

H_A#27

C21

H_A#28

J17

H_A#29

H20

H_A#30

B18

H_A#31

K17

H_A#32

B20

H_A#33

F21

H_A#34

K21

H_A#35

L20

H_ADS#

H12

H_ADSTB#0

B16

H_ADSTB#1

G17

H_BNR#

A9

H_BPRI#

F11

H_BR0#

G12

H_DEFER#

E9

H_DBSY#

B10

CLK_MCH_BCLK

AH7

CLK_MCH_BCLK#

AH6

H_DPWR#

J11

H_DRDY#

F9

H_HIT#

H9

H_HITM#

E12

H_LOCK#

H11

H_TRDY#

C9

H_DINV#0

J8

H_DINV#1

L3

H_DINV#2

Y13

H_DINV#3

Y1

H_DSTBN#0

L10

H_DSTBN#1

M7

H_DSTBN#2

AA5

H_DSTBN#3

AE6

H_DSTBP#0

L9

H_DSTBP#1

M8

H_DSTBP#2

AA6

H_DSTBP#3

AE5

H_REQ#0

B15

H_REQ#1

K13

H_REQ#2

F13

H_REQ#3

B13

H_REQ#4

B14

H_RS#0

B6

H_RS#1

F12

H_RS#2

C8

Layout Note: V_DDR_MCH_REF
trace width and spacing is 20/20.

H_A#3

A14

H_A#[3..35] 6

H_ADS# 6
H_ADSTB#0 6
H_ADSTB#1 6
H_BNR# 6
H_BPRI# 6
H_BR0# 6
H_DEFER# 6
H_DBSY# 6
CLK_MCH_BCLK 17
CLK_MCH_BCLK# 17
H_DPWR# 7
H_DRDY# 6
H_HIT# 6
H_HITM# 6
H_LOCK# 6
H_TRDY# 6

H_DINV#0 7
H_DINV#1 7
H_DINV#2 7
H_DINV#3 7

H_DSTBN#0 7
H_DSTBN#1 7
H_DSTBN#2 7
H_DSTBN#3 7

H_DSTBP#0 7
H_DSTBP#1 7
H_DSTBP#2 7
H_DSTBP#3 7

H_REQ#0 6
H_REQ#1 6
H_REQ#2 6
H_REQ#3 6
H_REQ#4 6

H_RS#0 6
H_RS#1 6
H_RS#2 6

PLT_RST#20,25,26

H_THERMTRIP#6,21

+V_DDR_MCH_REF generated by DC-DC

V_DDR_MCH_REF15,16

4

2.2U_0603_6.3V4Z

SMRCOMP_VOH

80% of 1.8V VCC_SM

20% of 1.8V VCC_SM

SMRCOMP_VOL

2.2U_0603_6.3V4Z

DPRSLPVR22,42

V_DDR_MCH_REF

1

C57

2

0.1U_0402_16V4Z

3

T7
T8
T9

+1.8V

1

1

C51

2

1

C53

2

PLT_RST#

+1.8V

C52

2

1

C54

2

R41
R42

12

R45
10K_0402_1%

12

R48
10K_0402_1%

12

R31
1K_0402_1%

0.01U_0402_25V7K

12

R32

3.01K_0402_1%

12

R33
1K_0402_1%

0.01U_0402_25V7K

PM_EXTTS#0

PM_EXTTS#1

CLKREQ#_7

1 2
1 2

R38 10K_0402_5%

1 2

R39 10K_0402_5%

1 2

R40 10K_0402_5%

1 2

MCH_CLKSEL017
MCH_CLKSEL117
MCH_CLKSEL217

PM_BMBUSY#22

H_DPRSTP#7,21,42
PM_EXTTS#015
PM_EXTTS#116
PM_PWROK22,32

CFG511
CFG611
CFG711
CFG811

CFG911
CFG1011
CFG1111
CFG1211
CFG1311
CFG1411
CFG1511
CFG1611
CFG1711
CFG1811
CFG1911
CFG2011

100_0402_5%
0_0402_5%

T85
T86

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20

T22
T23

T24

T25
T26
T27
T28

MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2

CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20

PM_BMBUSY#
H_DPRSTP#
PM_EXTTS#0
PM_EXTTS#1
PM_PWROK

THERMTRIP#
DPRSLPVR

@

1

C55

2

0.1U_0402_16V4Z

2007/08/28 2006/03/10

U2B

M36

RESERVED

N36

RESERVED

R33

RESERVED

T33

RESERVED

AH9

RESERVED

AH10

RESERVED

AH12

RESERVED

AH13

RESERVED

K12

RESERVED

AL34

RESERVED

AK34

RESERVED

AN35

RESERVED

AM35

RESERVED

T24

RESERVED

B31

RESERVED

B2

RESERVED

M1

RESERVED

AY21

RESERVED

BG23

RESERVED

BF23

RESERVED

BH18

RESERVED

BF18

RESERVED

+3VS

T25

CFG_0

R25

CFG_1

P25

CFG_2

P20

CFG_3

P24

CFG_4

C25

CFG_5

N24

CFG_6

M24

CFG_7

E21

CFG_8

C23

CFG_9

C24

CFG_10

N21

CFG_11

P21

CFG_12

T21

CFG_13

R20

CFG_14

M20

CFG_15

L21

CFG_16

H21

CFG_17

P29

CFG_18

R28

CFG_19

T28

CFG_20

R29

PM_SYNC#

B7

PM_DPRSTP#

N33

PM_EXT_TS#_0

P32

PM_EXT_TS#_1

AT40

PWROK

AT11

RSTIN#

T20

THERMTRIP#

R32

DPRSLPVR

BG48

NC

BF48

NC

BD48

NC

BC48

NC

BH47

NC

BG47

NC

BE47

NC

BH46

NC

BF46

NC

BG45

NC

BH44

NC

BH43

NC

BH6

NC

BH5

NC

BG4

NC

BH3

NC

BF3

NC

BH2

NC

BG2

NC

BE2

NC

BG1

NC

BF1

NC

BD1

NC

BC1

NC

F1

NC

A47

NC

CANTIGA ES_FCBGA1329

Compal Secret Data

Deciphered Date

RSVD

CFG

PM

NC

2

SM_RCOMP_VOH

SM_RCOMP_VOL

DDR CLK/ CONTROL/COMPENSATION

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

CLK

DMI

GRAPHICS VID

MEHDA

DDPC_CTRLDATA

SDVO_CTRLDATA

MISC

2

SA_CK_0
SA_CK_1
SB_CK_0
SB_CK_1

SA_CK#_0
SA_CK#_1
SB_CK#_0
SB_CK#_1

SA_CKE_0
SA_CKE_1
SB_CKE_0
SB_CKE_1

SA_CS#_0
SA_CS#_1
SB_CS#_0
SB_CS#_1

SA_ODT_0
SA_ODT_1
SB_ODT_0
SB_ODT_1

SM_RCOMP

SM_RCOMP#

SM_VREF

SM_PWROK

SM_REXT

SM_DRAMRST#

DPLL_REF_CLK

PEG_CLK

PEG_CLK#

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4

GFX_VR_EN

CL_CLK

CL_DATA

CL_PWROK

CL_RST#
CL_VREF

DDPC_CTRLCLK

SDVO_CTRLCLK

CLKREQ#

ICH_SYNC#

TSATN#

HDA_BCLK

HDA_RST#

HDA_SDI

HDA_SDO

HDA_SYNC

1

M_CLK_DDR0

AP24

M_CLK_DDR1

AT21

M_CLK_DDR2

AV24

M_CLK_DDR3

AU20

M_CLK_DDR#0

AR24

M_CLK_DDR#1

AR21

M_CLK_DDR#2

AU24

M_CLK_DDR#3

AV20

DDR_CKE0_DIMMA

BC28

DDR_CKE1_DIMMA

AY28

DDR_CKE2_DIMMB

AY36

DDR_CKE3_DIMMB

BB36

DDR_CS0_DIMMA#

BA17

DDR_CS1_DIMMA#

AY16

DDR_CS2_DIMMB#

AV16

DDR_CS3_DIMMB#

AR13

M_ODT0

BD17

M_ODT1

AY17

M_ODT2

BF15

M_ODT3

AY13

SMRCOMP

BG22

SMRCOMP#

BH21

SMRCOMP_VOH

BF28

SMRCOMP_VOL

BH28

V_DDR_MCH_REF

AV42

SM_PWROK

AR36

SM_REXT

BF17

TP_SM_DRAMRST#

BC36

CLK_MCH_DREFCLK

B38

CLK_MCH_DREFCLK#

A38

MCH_SSCDREFCLK

E41

MCH_SSCDREFCLK#

F41

CLK_MCH_3GPLL

F43

CLK_MCH_3GPLL#

E43

DMI_TXN0

AE41

DMI_TXN1

AE37

DMI_TXN2

AE47

DMI_TXN3

AH39

DMI_TXP0

AE40

DMI_TXP1

AE38

DMI_TXP2

AE48

DMI_TXP3

AH40

DMI_RXN0

AE35

DMI_RXN1

AE43

DMI_RXN2

AE46

DMI_RXN3

AH42

DMI_RXP0

AD35

DMI_RXP1

AE44

DMI_RXP2

AF46

DMI_RXP3

AH43

B33
B32
G33
F33
E33

C34

CL_CLK0

AH37

CL_DATA0

AH36

M_PWROK

AN36

CL_RST#

AJ35

+CL_VREF

AH34

0621 add CLK an d DAT for DVI

N28
M28

HDMICLK_NB

G36

HDMIDAT_NB

E36

CLKREQ#_7

K36

MCH_ICH_SYNC#

H36

TSATN#

B12

B28
B30

HDA_SDIN2_NB

B29
C29
A28

R737 56_0402_5 %

1 2

M_CLK_DDR0 15
M_CLK_DDR1 15
M_CLK_DDR2 16
M_CLK_DDR3 16

M_CLK_DDR#0 15
M_CLK_DDR#1 15
M_CLK_DDR#2 16
M_CLK_DDR#3 16

DDR_CKE0_DIMMA 15
DDR_CKE1_DIMMA 15
DDR_CKE2_DIMMB 16
DDR_CKE3_DIMMB 16

DDR_CS0_DIMMA# 15
DDR_CS1_DIMMA# 15
DDR_CS2_DIMMB# 16
DDR_CS3_DIMMB# 16

M_ODT0 15
M_ODT1 15
M_ODT2 16
M_ODT3 16

R34 80.6_0402_1%

1 2

R35 80.6_0402_1%

1 2

Follow Design Guide
For Cantiga: 80.6ohm

R36 0_0402_5%

1 2

R37 499_0402_1%

1 2

T29

CLK_MCH_DREFCLK 17
CLK_MCH_DREFCLK# 17
MCH_SSCDREFCLK 17
MCH_SSCDREFCLK# 17

CLK_MCH_3GPLL 17
CLK_MCH_3GPLL# 17

DMI_TXN0 22
DMI_TXN1 22
DMI_TXN2 22
DMI_TXN3 22

DMI_TXP0 22
DMI_TXP1 22
DMI_TXP2 22
DMI_TXP3 22

DMI_RXN0 22
DMI_RXN1 22
DMI_RXN2 22
DMI_RXN3 22

DMI_RXP0 22
DMI_RXP1 22
DMI_RXP2 22
DMI_RXP3 22

T30
T31

T35

CL_CLK0 22
CL_DATA0 22
M_PWROK 22,32
CL_RST# 22

0.1U_0402_16V4Z

T36
T37

HDMICLK_NB 3 4
HDMIDAT_NB 34

CLKREQ#_7 17
MCH_ICH_SYNC# 22

+VCCP

TSATN# 32

HDA_BITCLK_NB 21
HDA_RST#_NB 21

HDA_SDOUT_NB 21
HDA_SYNC_NB 21

1 2

33_0402_5%

C56

R210

+VCCP

1

2

*R44*Follow
Intel feedback

0830 Add pull-u p and pull-down resistor.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Cantiga(1/6)-AGTL/DMI/DDR

Montevina UMA

9 46Wednesday, February 18, 2009

1

+1.8V

12

R43
1K_0402_1%

12

R44
499_0402_1%

HDA_SDIN2 21

0.1

5

D D

DDR_A_D[0..63]15

C C

B B

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

U2D

AJ38

SA_DQ_0

AJ41

SA_DQ_1

AN38

SA_DQ_2

AM38

SA_DQ_3

AJ36

SA_DQ_4

AJ40

SA_DQ_5

AM44

SA_DQ_6

AM42

SA_DQ_7

AN43

SA_DQ_8

AN44

SA_DQ_9

AU40

SA_DQ_10

AT38

SA_DQ_11

AN41

SA_DQ_12

AN39

SA_DQ_13

AU44

SA_DQ_14

AU42

SA_DQ_15

AV39

SA_DQ_16

AY44

SA_DQ_17

BA40

SA_DQ_18

BD43

SA_DQ_19

AV41

SA_DQ_20

AY43

SA_DQ_21

BB41

SA_DQ_22

BC40

SA_DQ_23

AY37

SA_DQ_24

BD38

SA_DQ_25

AV37

SA_DQ_26

AT36

SA_DQ_27

AY38

SA_DQ_28

BB38

SA_DQ_29

AV36

SA_DQ_30

AW36

SA_DQ_31

BD13

SA_DQ_32

AU11

SA_DQ_33

BC11

SA_DQ_34

BA12

SA_DQ_35

AU13

SA_DQ_36

AV13

SA_DQ_37

BD12

SA_DQ_38

BC12

SA_DQ_39

BB9

SA_DQ_40

BA9

SA_DQ_41

AU10

SA_DQ_42

AV9

SA_DQ_43

BA11

SA_DQ_44

BD9

SA_DQ_45

AY8

SA_DQ_46

BA6

SA_DQ_47

AV5

SA_DQ_48

AV7

SA_DQ_49

AT9

SA_DQ_50

AN8

SA_DQ_51

AU5

SA_DQ_52

AU6

SA_DQ_53

AT5

SA_DQ_54

AN10

SA_DQ_55

AM11

SA_DQ_56

AM5

SA_DQ_57

AJ9

SA_DQ_58

AJ8

SA_DQ_59

AN12

SA_DQ_60

AM13

SA_DQ_61

AJ11

SA_DQ_62

AJ12

SA_DQ_63

CANTIGA ES_FCBGA1329

DDR SYSTEM MEMORY A

SA_BS_0
SA_BS_1
SA_BS_2

SA_RAS#
SA_CAS#

SA_WE#

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6

SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14

4

DDR_A_BS0

BD21
BG18
AT25

BB20
BD20
AY20

AM37
AT41
AY41
AU39
BB12
AY6
AT7
AJ5

AJ44
AT44
BA43
BC37
AW12
BC8
AU8
AM7
AJ43
AT43
BA44
BD37
AY12
BD8
AU9
AM8

BA21
BC24
BG24
BH24
BG25
BA24
BD24
BG27
BF25
AW24
BC21
BG26
BH26
BH17
AY25

DDR_A_BS1
DDR_A_BS2

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2

DDR_A_DQS#3

DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14

DDR_A_BS0 15
DDR_A_BS1 15
DDR_A_BS2 15

DDR_A_RAS# 15
DDR_A_CAS# 15
DDR_A_WE# 15

DDR_A_DM[0..7] 15

DDR_A_DQS[0..7] 15

DDR_A_DQS#[0..7] 15

DDR_A_MA[0..14] 15

3

DDR_B_D[0..63]16

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

U2E

AK47
AH46
AP47
AP46
AJ46
AJ48

AM48

AP48

AU47
AU46

BA48
AY48
AT47
AR47
BA47
BC47
BC46
BC44
BG43
BF43
BE45
BC41
BF40
BF41
BG38
BF38
BH35
BG35
BH40
BG39
BG34
BH34
BH14
BG12
BH11

BG8
BH12
BF11

BF8

BG7

BC5

BC6

AY3

AY1

BF6

BF5

BA1

BD3

AV2

AU3

AR3

AN2

AY2

AV1

AP3

AR1

AL1
AL2
AJ1

AH1

AM2
AM3

AH3

AJ3

CANTIGA ES_FCBGA1329

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

2

DDR_B_BS0

BC16

SB_BS_0
SB_BS_1
SB_BS_2

SB_RAS#

SB_CAS#

SB_WE#

SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6

SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14

DDR SYSTEM MEMORY B

BB17
BB33

AU17
BG16
BF14

AM47
AY47
BD40
BF35
BG11
BA3
AP1
AK2

AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6
AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5

AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33

DDR_B_BS1
DDR_B_BS2

DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14

1

DDR_B_BS0 16
DDR_B_BS1 16
DDR_B_BS2 16

DDR_B_RAS# 16
DDR_B_CAS# 16
DDR_B_WE# 16

DDR_B_DM[0..7] 16

DDR_B_DQS[0..7] 16

DDR_B_DQS#[0..7] 16

DDR_B_MA[0..14] 16

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet of

Compal Electronics, Inc.

Cantiga(2/6)-DDR2 A/B CH

Montevina UMA

1

10 46Wednesday, February 18, 2009

0.1

5

R148

1 2

100K_0402_5%

D D

C C

B B

ENBKL

NB_BKLT_CTRL19

ENBKL32

+3VS

DDC2_CLK19
DDC2_DATA19

Follow Intel DG &
Checklist

ENAVDD19

T48
T49
T50

Follow Intel DG &
Checklist

+3VS

M_BLUE18
M_GREEN18
M_RED18

Follow Intel DG &
Checklist

3VDDCCL18
3VDDCDA18

CRT_HSYNC18

CRT_VSYNC18

NB_BKLT_CTRL
ENBKL

R58 10K_0402_5%

1 2

R59 10K_0402_5%

1 2

DDC2_CLK
DDC2_DATA

ENAVDD

R60 4.75K_0402_1%

1 2

LVDS_ACLK­LVDS_ACLK+
LVDS_BCLK­LVDS_BCLK+

LVDS_A0­LVDS_A1­LVDS_A2­LVDS_A3-

T38

LVDS_A0+
LVDS_A1+
LVDS_A2+
LVDS_A3+

T39

LVDS_B0­LVDS_B1­LVDS_B2­LVDS_B3-

T40

LVDS_B0+
LVDS_B1+
LVDS_B2+
LVDS_B3+

T41

TV_COMPS
TV_LUMA
TV_CRMA

12

75_0402_1%

R61

R62

R64 2.2K_0402_5%@

1 2

R406 0_0402_5%

1 2

M_BLUE
M_GREEN
M_RED

3VDDCCL
3VDDCDA
CRT_HSYNC

R65

R68

30.1_0402_1%

R69

30.1_0402_1%

150_0402_1%

12

1 2

1 2

R66

12

75_0402_1%

R63

150_0402_1%

12

R67

HSYNC

VSYNCCRT_VSYNC

1.02K_0402_1%

12

12

R70

4

U2C

L32

L_BKLT_CTRL

G32

L_BKLT_EN

M32

L_CTRL_CLK

M33

L_CTRL_DATA

K33

L_DDC_CLK

J33

L_DDC_DATA

M29

L_VDD_EN

C44

LVDS_IBG

B43

LVDS_VBG

E37

LVDS_VREFH

E38

LVDS_VREFL

C41

LVDSA_CLK#

C40

LVDSA_CLK

B37

LVDSB_CLK#

A37

LVDSB_CLK

H47

LVDSA_DATA#_0

E46

LVDSA_DATA#_1

G40

LVDSA_DATA#_2

A40

LVDSA_DATA#_3

H48

LVDSA_DATA_0

D45

LVDSA_DATA_1

F40

LVDSA_DATA_2

B40

LVDSA_DATA_3

A41

LVDSB_DATA#_0

H38

LVDSB_DATA#_1

G37

LVDSB_DATA#_2

J37

LVDSB_DATA#_3

B42

LVDSB_DATA_0

G38

LVDSB_DATA_1

F37

LVDSB_DATA_2

K37

LVDSB_DATA_3

F25

TVA_DAC

H25

75_0402_1%

150_0402_1%

12

TVB_DAC

K25

TVC_DAC

H24

TV_RTN

C31

TV_DCONSEL_0

E32

TV_DCONSEL_1

E28

CRT_BLUE

G28

CRT_GREEN

J28

CRT_RED

G29

CRT_IRTN

H32

CRT_DDC_CLK

J32

CRT_DDC_DATA

J29

CRT_HSYNC

E29

CRT_TVO_IREF

L29

CRT_VSYNC

CANTIGA ES_FCBGA1329

LVDS

TV VGA

PCI-EXPRESS GRAPHICS

PEG_COMPI

PEG_COMPO

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8

PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8

PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9

PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

T37
T36

H44
J46
L44
L40
N41
P48
N44
T43
U43
Y43
Y48
Y36
AA43
AD37
AC47
AD39

H43
J44
L43
L41
N40
P47
N43
T42
U42
Y42
W47
Y37
AA42
AD36
AC48
AD40

J41
M46
M47
M40
M42
R48
N38
T40
U37
U40
Y40
AA46
AA37
AA40
AD43
AC46

J42
L46
M48
M39
M43
R47
N37
T39
U36
U39
Y39
Y46
AA36
AA39
AD42
AD46

3

R57

1 2

49.9_0402_1%

PEGCOMP trace width
and spacing is 20/25 mils.

TMDS_B_HPD#

TMDS_BDATA2#
TMDS_BDATA1#
TMDS_BDATA0#
TMDS_BCLK#

TMDS_BDATA2
TMDS_BDATA1
TMDS_BDATA0
TMDS_BCLK

C274 0.1U_0402_10V7K
C275 0.1U_0402_10V7K
C276 0.1U_0402_10V7K
C277 0.1U_0402_10V7K

C278 0.1U_0402_10V7K
C279 0.1U_0402_10V7K
C280 0.1U_0402_10V7K
C281 0.1U_0402_10V7K

1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2

+VCC_PEG

TMDS_B_HPD# 34

2

TMDS_B_DATA2# 34
TMDS_B_DATA1# 34
TMDS_B_DATA0# 34
TMDS_B_CLK# 34

TMDS_B_DATA2 34
TMDS_B_DATA1 34
TMDS_B_DATA0 34
TMDS_B_CLK 34

Strap Pin Table

CFG[2:0] FSB Freq
select

CFG[4:3]

CFG5 (DMI select)

CFG6

CFG7

(Intel Management
Engine Crypto strap)

CFG8

CFG9 (PCIE Graphics

Lane Reversal)

CFG10

(PCIE
Lookback
enable)

CFG11

CFG[13:12]
(XOR/ALLZ)

CFG[15:14]

CFG16 (FSB Dynamic ODT)

CFG[18:17]

CFG19 (DMI Lane Reversal)

CFG20

(PCIE/SDVO
concurrent)

+3VS

R71

@

4.02K_0402_1%

CFG59

CFG5

R74

@

2.21K_0402_1%

1

000 = FSB
1066MHz

010 = FSB
800MHz

011 = FSB
667MHz

Others =
Reserved
Reserved

0 = DMI x
1 = DMI x

2
4

0 = The iTPM Host Interface is
enable

1 = The iTPM Host Interface is
disable

0 =(TLS)chiper suite with no
confidentiality

1 =(TLS)chiper suite with
confidentiality

*

Reserved

0 = Reverse Lane,15->0,
14->1

1 = Normal Operation,Lane Number
in order

0 =
Enable

1 = Disable
Reserved
00 = Reserved

01 = XOR Mode
10 = All Z Mode

Enabled
Enabled
Operation

Reserved

0 =
1 =

Disabled
Enabled

Reserved

0 = Normal
Operation
1 = Reverse Lane

0 = Only PCIE or SDVO is
operational.

1 = PCIE/SDVO are operating
simu.

12

12

*

*

(Lane number in
Order)

CFG169

CFG199

CFG209

@

@

@

R72

R73

R75

(Default)11 = Normal

*

*

*

*

1 2

4.02K_0402_1%

1 2

4.02K_0402_1%

1 2

4.02K_0402_1%

*

*

+3VS

R76

@

@

@

@

@

@

@

R77

R78

R80

R82

R85

R87

1 2

2.21K_0402_1%

1 2

2.21K_0402_1%

1 2

2.21K_0402_1%

1 2

2.21K_0402_1%

1 2

2.21K_0402_1%

1 2

2.21K_0402_1%

1 2

2.21K_0402_1%

11 46Wednesday, February 18, 2009

0.1

For 3G

LVDS_ACLK+19

WWAN

LVDS_ACLK-19
LVDS_A0+19

LVDS_A0-19
LVDS_A1+19

LVDS_A1-19
LVDS_A2+19

A A

LVDS_A2-19

LVDS_ACLK+

LVDS_ACLK­LVDS_A0+

LVDS_A0­LVDS_A1+

LVDS_A1­LVDS_A2+

LVDS_A2-

5

1

@

C60

0.1U_0402_10V6K

2
1

@

C61

0.1U_0402_10V6K

2
1

@

C62

0.1U_0402_10V6K

2
1

@

C63

0.1U_0402_10V6K

2

For 3G

LVDS_BCLK+19

WWAN

LVDS_BCLK-19
LVDS_B0+1 9

LVDS_B0-19
LVDS_B1+1 9

LVDS_B1-19
LVDS_B2+1 9

LVDS_B2-19

4

LVDS_BCLK+

LVDS_BCLK­LVDS_B0+

LVDS_B0­LVDS_B1+

LVDS_B1­LVDS_B2+

LVDS_B2-

1

@

C1500

0.1U_0402_10V6K

2
1

@

C1501

0.1U_0402_10V6K

2
1

@

C1502

0.1U_0402_10V6K

2
1

@

C1503

0.1U_0402_10V6K

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

CFG69

CFG79

CFG89

CFG99

CFG109

2

R79

@

1 2

2.21K_0402_1%

R81

@

1 2

2.21K_0402_1%

R83

@

1 2

2.21K_0402_1%

R84

@

1 2

2.21K_0402_1%

R86

@

1 2

2.21K_0402_1%

Title

Cantiga(3/6)-VGA/LVDS/TV

Size Document Number Rev

Custom

Montevina UMA

Date: Sheet of

CFG119

CFG129

CFG139

CFG149

CFG159

CFG179

CFG189

Compal Electronics, Inc.

1

5

+3VS_DAC_BG

0.022U_0402_16V7K

C69

1

2

0.022U_0402_16V7K

C76

1

2

+3VS

220U_D2_4VM

R103

1 2

0_0603_5%

1U_0603_10V4Z

0.1U_0402_16V4Z

C70

1

2

R91

1 2

BLM18PG181SN1D_0603

0.1U_0402_16V4Z

1

2

R96

@

1 2

0_0603_5%

R97

1 2

0_0603_5%

1

C94

+

2

C102

1

2

C68

D D

+3VS_DAC_CRT

C75

+1.5VS

+VCCP

C C

B B

+3VS

R88

1 2

BLM18PG181SN1D_0603

10U_0805_10V4Z

+3VS

1

C89

0.1U_0402_16V4Z

2

R100

1 2

0_0805_5%

C95

1

2

+1.05VS_A_SM_CK

C103

1

1

2

2

+1.8V_TXLVDS

+1.5VS_PEG_BG

10U_0805_10V4Z

C96

4.7U_0805_10V4Z

10U_0805_10V4Z

C104

1

2

**RED Mark: Means UMA & dis@ Power select**
~It check by INTEL Graphics Disable Guidelines~

+3VS_DAC_CRT

+3VS_DAC_BG

+1.05VS_DPLLA

+1.05VS_DPLLB

+1.05VS_HPLL

+1.05VS_MPLL

1

C88

1000P_0402_50V7K

2

+1.05VS_PEGPLL

+1.05VS_A_SM

1

1

C97

2

2

1U_0603_10V4Z

0.1U_0402_16V4Z

1U_0603_10V4Z

C105

1

2

+3VS_TVDAC

+1.5VS

+1.5VS_TVDAC

+1.5VS_QDAC

+1.05VS_HPLL

+1.05VS_PEGPLL

+1.8V_LVDS

4

U2H

73mA

B27

VCCA_CRT_DAC

A26

VCCA_CRT_DAC

2.68mA

A25

VCCA_DAC_BG

B25

VSSA_DAC_BG

F47

VCCA_DPLLA

L48

VCCA_DPLLB

AD1

VCCA_HPLL

AE1

VCCA_MPLL

13.2mA

J48

VCCA_LVDS

J47

VSSA_LVDS

414uA

AD48

VCCA_PEG_BG

50mA

AA48

VCCA_PEG_PLL

AR20

VCCA_SM

AP20

VCCA_SM

AN20

VCCA_SM

AR17

VCCA_SM

AP17

VCCA_SM

AN17

VCCA_SM

AT16

VCCA_SM

AR16

VCCA_SM

AP16

VCCA_SM

AP28

VCCA_SM_CK

AN28

VCCA_SM_CK

AP25

VCCA_SM_CK

AN25

VCCA_SM_CK

AN24

VCCA_SM_CK

AM28

VCCA_SM_CK_NCTF

AM26

VCCA_SM_CK_NCTF

AM25

VCCA_SM_CK_NCTF

AL25

VCCA_SM_CK_NCTF

AM24

VCCA_SM_CK_NCTF

AL24

VCCA_SM_CK_NCTF

AM23

VCCA_SM_CK_NCTF

AL23

VCCA_SM_CK_NCTF

B24

VCCA_TV_DAC

A24

VCCA_TV_DAC

A32

VCC_HDA

M25

VCCD_TVDAC

L28

VCCD_QDAC

AF1

VCCD_HPLL

AA47

VCCD_PEG_PLL

M38

VCCD_LVDS

L37

VCCD_LVDS

60.31mA

CANTIGA ES_FCBGA1329

64.8mA

64.8mA

24mA

139.2mA

720mA

26mA

26mA

TVA 24.15mA
TVB 39.48mA
TVX 24.15mA

50mA

58.67mA

48.363mA

157.2mA

50mA

CRTPLLA PEGA SMTV

A LVDSHDA

POWER

A CK

105.3mA

1732mA

D TV/CRT

LVDS

852mA

SM CK

118.8mA

VCC_TX_LVDS

DMI

456mA

VTT

321.35mA

VCC_AXF
VCC_AXF
VCC_AXF

AXF

124mA

VCC_SM_CK
VCC_SM_CK
VCC_SM_CK
VCC_SM_CK

VCC_HV
VCC_HV
VCC_HV

HV

VCC_PEG
VCC_PEG
VCC_PEG
VCC_PEG
VCC_PEG

PEG

VCC_DMI
VCC_DMI
VCC_DMI
VCC_DMI

VTTLF

VTTLF
VTTLF
VTTLF

3

+VCCP

U13

VTT

T13

VTT

U12

VTT

T12

VTT

U11

VTT

T11

VTT

U10

VTT

T10

VTT

U9

VTT

T9

VTT

U8

VTT

T8

VTT

U7

VTT

T7

VTT

U6

VTT

T6

VTT

U5

VTT

T5

VTT

V3

VTT

U3

VTT

V2

VTT

U2

VTT

T2

VTT

V1

VTT

U1

VTT

B22
B21
A21

BF21
BH20
BG20
BF20

K47

C35
B35
A35

V48
U48
V47
U47
U46

AH48
AF48
AH47
AG47

A8
L1
AB2

C110

0.47U_0603_10V7K

+V1.05VS_AXF

+1.8V_SM_CK

+1.8V_TXLVDS

+VCC_PEG

+1.05VS_DMI

0.47U_0603_10V7K

C111

1

2

1

C71

2

1

C80

2

1

2

4.7U_0805_10V4Z

220U_D2_4VM

C72

1

+

2

4.7U_0805_10V4Z

0.47U_0603_10V7K

C81

+3VS_HV

C107

0.47U_0603_10V7K

C112

1

2

2.2U_0805_16V4Z

1

1

C82

2

2

0.1U_0402_16V4Z

1

2

0.1U_0402_16V4Z
C86

1

2

0.1U_0402_16V4Z

C73

C87

+1.05VS_PEGPLL

2

+1.05VS_DPLLA +VCCP

1 2

R90

10U_0805_10V4Z

0.1U_0402_16V4Z

1

2

10U_0805_10V4Z

1

2

+1.05VS_HPLL

+1.05VS_MPLL

C99

10U_FLC-453232-100K_0.25A_10%

C74

1

2

C91

1

2

10U_0805_10V4Z

10U_0805_10V4Z

1

C100

10U_0805_10V4Z

2

1

2

+VCCP+1.05VS_DPLLB

R98

1 2

MBK2012121YZF_0805

R101

1 2

MBK2012121YZF_0805

L1

1 2

BLM18PG121SN1D_0603

C108

+VCCP

R94

1 2

10U_FLC-453232-100K_0.25A_10%

0.1U_0402_16V4Z

C90

1

2

1

2

0.1U_0402_16V4Z

C106

1

2

2 1

+3VS

+VCCP

+VCCP

+VCCP

+VCCP_D

D3

CH751H-40PT_SOD323-2

@

C83

R105

1 2

10_0402_5%

+V1.05VS_AXF

+1.8V_SM_CK

10U_0805_10V4Z

1

2

+1.5VS_TVDAC

+VCC_PEG

C98

+1.05VS_DMI

10U_0805_10V4Z

1

2

C84

1

2

1

C92

2

1

+

2

1

2

R106

1 2

0_0402_5%

C78

10U_0805_10V4Z

0.022U_0402_16V7K

220U_D2_4VM

0.1U_0402_16V4Z

C109

1

1

C93

2

C101

1

2

R104

1 2

0_0603_5%

1U_0603_10V4Z

0.1U_0402_16V4Z

1

2

1

2

0.1U_0402_16V4Z

10U_0805_10V4Z

C79

C85

R99

1 2

0_0805_5%

R102

1 2

0_0805_5%

+VCCP

+3VS_HV

R93

1 2

0_0603_5%

R95

1 2

0_0805_5%

+VCCP

+VCCP

+1.8V

+1.5VS

+1.8V_LVDS

R107

1 2

1U_0603_10V4Z

10U_0805_10V4Z

+3VS_TVDAC

A A

0.022U_0402_16V7K

C117

1

2

C118

1

2

R111

1 2

BLM18PG181SN1D_0603

0.1U_0402_16V4Z

5

+3VS

+1.5VS_QDAC

C119

1

2

0.022U_0402_16V7K

0.1U_0402_16V4Z

C120

1

2

4

R112

1 2

100_0603_1%

+1.5VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

1

2

2

0_0603_5%

C114

C113

1

2

+1.8V

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Cantiga(4/6)-PWR

Montevina UMA

40 mils

+1.8V_TXLVDS

1000P_0402_50V7K

1

2

1

R108

1 2

0_0603_5%

C116

+1.8V

0.1

12 46Wednesday, February 18, 2009

5

4

3

2

1

W28
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16

AV44
BA37
AM40
AV21
AY5
AM10
BB13

+VCCP

VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7

0.1U_0402_16V4Z

1

C127

2

0.22U_0402_10V4Z

C139 0.1U_0402_16V4Z

1

2

4.7U_0603_6.3V6M

1

1

C128

C129

2

2

C140 0.1U_0402_16V4Z

C141 0.22U_0603_10V7K

1

1

1

2

2

2

C144 1U_0603_10V4Z

C143 0.47U_0402_6.3V6K

C142 0.22U_0603_10V7K

1

2

C145 1U_0603_10V4Z

1

1

2

2

U2G

3000mA

Extnal Graphic: 1210.34mA
integrated Graphic: 1930.4mA

+VCCP

D D

0.1U_0402_16V4Z

0.22U_0402_10V4Z

0.22U_0402_10V4Z

10U_0805_10V4Z

220U_D2_4VM

1

C124

C131

+

2

C C

B B

C132

1

1

2

2

C125

C133

1

1

2

2

U2F

AG34

VCC

AC34

VCC

AB34

VCC

AA34

VCC

Y34

VCC

V34

VCC

U34

VCC

AM33

VCC

AK33

VCC

AJ33

VCC

AG33

VCC

AF33

VCC

AE33

VCC

AC33

VCC

AA33

VCC

Y33

VCC

W33

VCC

V33

VCC

U33

VCC

AH28

VCC

AF28

VCC

AC28

VCC

AA28

VCC

AJ26

VCC

AG26

VCC

AE26

VCC

AC26

VCC

AH25

VCC

AG25

VCC

AF25

VCC

AG24

VCC

AJ23

VCC

AH23

VCC

AF23

VCC

T32

VCC

CANTIGA ES_FCBGA1329

VCC CORE

+VCCP

AM32

VCC_NCTF

AL32

VCC_NCTF

AK32

VCC_NCTF

AJ32

VCC_NCTF

AH32

VCC_NCTF

AG32

VCC_NCTF

AE32

VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF
VCC_NCTF

AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23

POWER

VCC NCTF

SI-1 Add C for GM47

+1.8V

1U_0603_10V4Z

330U_D2E_2.5VM_R7

1

1

C134

GM47@

+

C1508

2

2

22P_0402_25V8K

@

1

C1490

2

22P_0402_25V8K

@

1

C1493

2

Reserve for WWAN

330U_D2E_2.5VM_R7

1

+

2

10U_0805_10V4Z

330U_D2E_2.5VM_R7

1

+

C135

2

22P_0402_25V8K

1

2

22P_0402_25V8K

1

2

10U_0805_10V4Z

C126

C122

1

2

0317 change value

1

C136

2

10U_0805_10V4Z

22P_0402_25V8K

@

C1491

22P_0402_25V8K

@

C1494

10U_0805_10V4Z

C130

1

2

+VCCP

0.1U_0402_16V4Z

1

C137

2

@

1

C1492

2

@

1

C1495

2

0.01U_0402_16V7K

2

1

1

C138

2

T42PA D
T43PA D

AP33

VCC_SM

AN33

VCC_SM

BH32

VCC_SM

BG32

VCC_SM

BF32

VCC_SM

BD32

VCC_SM

BC32

C123

BB32
BA32
AY32

AW32

AV32
AU32
AT32
AR32
AP32
AN32
BH31
BG31
BF31
BG30
BH29
BG29
BF29
BD29
BC29
BB29
BA29
AY29

AW29

AV29
AU29
AT29
AR29
AP29

BA36
BB24

BD16

BB21
AW16
AW13

AT13

AE25

AB25

AA25

AE24

AC24

AA24

AE23

AC23

AB23

AA23

AJ21
AG21
AE21
AC21
AA21

AH20
AF20
AE20
AC20
AB20
AA20

AM15

AL15
AE15

AJ15

AH15
AG15

AF15
AB15
AA15

AN14
AM14

AJ14

AH14

Y26

Y24

Y21

T17
T16

Y15
V15
U15

U14
T14

VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM

VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC
VCC_SM/NC

6326.84mA

VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG

VCC_AXG_SENSE
VSS_AXG_SENSE

VCC SMVCC GFX

POWER

VCC GFX NCTF

VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF

VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF

VCC SM LF

A A

CANTIGA ES_FCBGA1329

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet of

Compal Electronics, Inc.

Cantiga(5/6)-PWR/GND

Montevina UMA

1

13 46Wednesday, February 18, 2009

0.1

5

4

3

2

1

U2I

AU48

VSS

AR48

VSS

AL48

VSS

BB47

VSS

AW47

VSS

AN47

VSS

AJ47

VSS

AF47

D D

C C

B B

A A

VSS

AD47

VSS

AB47

VSS

Y47

VSS

T47

VSS

N47

VSS

L47

VSS

G47

VSS

BD46

VSS

BA46

VSS

AY46

VSS

AV46

VSS

AR46

VSS

AM46

VSS

V46

VSS

R46

VSS

P46

VSS

H46

VSS

F46

VSS

BF44

VSS

AH44

VSS

AD44

VSS

AA44

VSS

Y44

VSS

U44

VSS

T44

VSS

M44

VSS

F44

VSS

BC43

VSS

AV43

VSS

AU43

VSS

AM43

VSS

J43

VSS

C43

VSS

BG42

VSS

AY42

VSS

AT42

VSS

AN42

VSS

AJ42

VSS

AE42

VSS

N42

VSS

L42

VSS

BD41

VSS

AU41

VSS

AM41

VSS

AH41

VSS

AD41

VSS

AA41

VSS

Y41

VSS

U41

VSS

T41

VSS

M41

VSS

G41

VSS

B41

VSS

BG40

VSS

BB40

VSS

AV40

VSS

AN40

VSS

H40

VSS

E40

VSS

AT39

VSS

AM39

VSS

AJ39

VSS

AE39

VSS

N39

VSS

L39

VSS

B39

VSS

BH38

VSS

BC38

VSS

BA38

VSS

AU38

VSS

AH38

VSS

AD38

VSS

AA38

VSS

Y38

VSS

U38

VSS

T38

VSS

J38

VSS

F38

VSS

C38

VSS

BF37

VSS

BB37

VSS

AW37

VSS

AT37

VSS

AN37

VSS

AJ37

VSS

H37

VSS

C37

VSS

BG36

VSS

BD36

VSS

AK15

VSS

AU36

VSS

CANTIGA ES_FCBGA1329

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
AD12
AY24
AT24
AJ24
AH24
AF24
AB24
R24
L24
K24
J24
G24
F24
E24
BH23
AG23
Y23
B23
A23
AJ6

U2J

BG21

VSS

L12

VSS

AW21

VSS

AU21

VSS

AP21

VSS

AN21

VSS

AH21

VSS

AF21

VSS

AB21

VSS

R21

VSS

M21

VSS

J21

VSS

G21

VSS

BC20

VSS

BA20

VSS

AW20

VSS

AT20

VSS

AJ20

VSS

AG20

VSS

Y20

VSS

N20

VSS

K20

VSS

F20

VSS

C20

VSS

A20

VSS

BG19

VSS

A18

VSS

BG17

VSS

BC17

VSS

AW17

VSS

AT17

VSS

R17

VSS

M17

VSS

H17

VSS

C17

VSS

BA16

VSS

AU16

VSS

AN16

VSS

N16

VSS

K16

VSS

G16

VSS

E16

VSS

BG15

VSS

AC15

VSS

W15

VSS

A15

VSS

BG14

VSS

AA14

VSS

C14

VSS

BG13

VSS

BC13

VSS

BA13

VSS

AN13

VSS

AJ13

VSS

AE13

VSS

N13

VSS

L13

VSS

G13

VSS

E13

VSS

BF12

VSS

AV12

VSS

AT12

VSS

AM12

VSS

AA12

VSS

J12

VSS

A12

VSS

BD11

VSS

BB11

VSS

AY11

VSS

AN11

VSS

AH11

VSS

Y11

VSS

N11

VSS

G11

VSS

C11

VSS

BG10

VSS

AV10

VSS

AT10

VSS

AJ10

VSS

AE10

VSS

AA10

VSS

M10

VSS

BF9

VSS

BC9

VSS

AN9

VSS

AM9

VSS

AD9

VSS

G9

VSS

B9

VSS

BH8

VSS

BB8

VSS

AV8

VSS

AT8

VSS

CANTIGA ES_FCBGA1329

VSS

AH8

VSS

Y8

VSS

L8

VSS

E8

VSS

B8

VSS

AY7

VSS

AU7

VSS

AN7

VSS

AJ7

VSS

AE7

VSS

AA7

VSS

N7

VSS

J7

VSS

BG6

VSS

BD6

VSS

AV6

VSS

AT6

VSS

AM6

VSS

M6

VSS

C6

VSS

BA5

VSS

AH5

VSS

AD5

VSS

Y5

VSS

L5

VSS

J5

VSS

H5

VSS

F5

VSS

BE4

VSS

BC3

VSS

AV3

VSS

AL3

VSS

R3

VSS

P3

VSS

F3

VSS

BA2

VSS

AW2

VSS

AU2

VSS

AR2

VSS

AP2

VSS

AJ2

VSS

AH2

VSS

AF2

VSS

AE2

VSS

AD2

VSS

AC2

VSS

Y2

VSS

M2

VSS

K2

VSS

AM1

VSS

AA1

VSS

P1

VSS

H1

VSS

U24

VSS

U28

VSS

U25

VSS

U29

VSS

AF32

VSS_NCTF

AB32

VSS_NCTF

V32

VSS_NCTF

AJ30

VSS_NCTF

AM29

VSS_NCTF

AF29

VSS_NCTF

AB29

VSS_NCTF

U26

VSS_NCTF

U23

VSS_NCTF

AL20

VSS_NCTF

V20

VSS_NCTF

AC19

VSS_NCTF

AL17

VSS_NCTF

AJ17

VSS_NCTF

VSS NCTF

VSS SCB

NC

VSS_NCTF
VSS_NCTF

VSS_SCB
VSS_SCB
VSS_SCB
VSS_SCB
VSS_SCB

AA17
U17

BH48
BH1
A48
C1
A3

E1

NC

D2

NC

C3

NC

B4

NC

A5

NC

A6

NC

A43

NC

A44

NC

B45

NC

C46

NC

D47

NC

B47

NC

A46

NC

F48

NC

E48

NC

C48

NC

B48

NC

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet of

Compal Electronics, Inc.

Cantiga(6/6)-PWR/GND

Montevina UMA

1

14 46Wednesday, February 18, 2009

0.1

5

DDR_A_DQS#[0..7]10

DDR_A_D[0..63]10

DDR_A_DM[0..7]10

DDR_A_DQS[0..7]10

DDR_A_MA[0..14]10

D D

C C

B B

A A

Layout Note:
Place near
JP3

+1.8V

2.2U_0805_16V4Z

2.2U_0805_16V4Z

2.2U_0805_16V4Z

C152

1

2

Layout Note:
Place one cap close to every 2
pullup
resistors terminated to +0.9VS

+0.9V

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C159

C158

DDR_A_BS2
DDR_CKE0_DIMMA
DDR_A_MA12
DDR_A_MA9

DDR_A_MA8
DDR_A_MA5
DDR_A_MA1
DDR_A_MA3

DDR_A_BS0
DDR_A_MA10
DDR_A_CAS#
DDR_A_WE#

DDR_CS1_DIMMA#
M_ODT1

DDR_A_MA11

5

C147

1

2

0.1U_0402_16V4Z

1

2

C160

56_8P4R_0.05

56_8P4R_0.05

56_8P4R_0.05

2 3
1 4

1 2

R117 56_0402_5%

C153

1

2

0.1U_0402_16V4Z

1

2

C161

RP29

1 8
2 7
3 6
4 5

RP31

1 8
2 7
3 6
4 5

RP33

1 8
2 7
3 6
4 5

RP1156_0404_4P2R_5%

2.2U_0805_16V4Z

2.2U_0805_16V4Z

C154

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C162

+0.9V

56_8P4R_0.05

56_8P4R_0.05

56_8P4R_0.05

+0.9V

C155

1

2

0.1U_0402_16V4Z

1

2

C163

RP30

1 8
2 7
3 6
4 5

RP32

1 8
2 7
3 6
4 5

RP34

1 8
2 7
3 6
4 5

0.1U_0402_16V4Z

1

2

0.1U_0402_16V4Z

1

1

2

2

C164

DDR_A_MA14
DDR_CKE1_DIMMA
DDR_A_MA6
DDR_A_MA7

DDR_A_MA2
DDR_A_MA4
DDR_A_BS1
DDR_A_MA0

DDR_A_MA13
M_ODT0
DDR_CS0_DIMMA#
DDR_A_RAS#

C156

0.1U_0402_16V4Z

C165

4

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C166

C149

C148

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C167

330U_D2E_2.5VM_R7

0.1U_0402_16V4Z

1

2

C168

1

C157

1

+

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C169

C170

Layout Note:
Place these resistor
closely JP3,all
trace length Max=1.5"

C150

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

+1.8V

DDR_A_D4
DDR_A_D1

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D9

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D11 DDR_A_D15
DDR_A_D10 DDR_A_D14

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA9

DDR_A_BS210

DDR_A_BS010

DDR_A_WE#10

DDR_A_CAS#10

DDR_CS1_DIMMA#9

M_ODT19

CLK_SMBDATA16,17,24
CLK_SMBCLK16,17,24

+3VS

3

DDR_CKE0_DIMMA

DDR_A_BS2

DDR_A_MA12
DDR_A_MA9 DDR_A_MA7
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1_DIMMA#

M_ODT1

DDR_A_D37
DDR_A_D36

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D39
DDR_A_D38

DDR_A_D45
DDR_A_D44

DDR_A_DM5

DDR_A_D47 DDR_A_D43
DDR_A_D46

DDR_A_D49
DDR_A_D48

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50

DDR_A_D61 DDR_A_D57
DDR_A_D60

DDR_A_DM7

DDR_A_D59
DDR_A_D58

CLK_SMBDATA
CLK_SMBCLK

1

2

2.2U_0603_6.3V4Z

2006/02/13 2006/03/10

C171

C172

Compal Secret Data

1

2

V_DDR_MCH_REF

JDIMM1

1
3
5
7
9

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

FOX_ASOA426-M4R-TR

CONN@

SO-DIMM A

0.1U_0402_16V4Z

Deciphered Date

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

VSS

203

DQ12
DQ13

CK0#

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3

DQ30
DQ31

NC/CKE1

NC/A15
NC/A14

RAS#

ODT0

NC/A13

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5

DQ46
DQ47

DQ52
DQ53

CK1#

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7

DQ62
DQ63

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS

VSS
DM1
VSS
CK0

VSS

VSS

VSS

VSS

DM2
VSS

VSS

VSS

VSS

VSS

VDD

VDD

VDD

VDD
BA1

VDD

VDD

VSS

VSS
DM4
VSS

VSS

VSS

VSS

VSS

VSS
CK1

VSS
DM6
VSS

VSS

VSS

VSS

VSS
SAO
SA1

2

+1.8V

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90

A11

92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110

S0#

112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

VSS

204

2

DDR_A_D5
DDR_A_D0

DDR_A_DM0

DDR_A_D6
DDR_A_D7

DDR_A_D13
DDR_A_D12

DDR_A_DM1

M_CLK_DDR0
M_CLK_DDR#0

DDR_A_D20
DDR_A_D21

DDR_A_DM2

DDR_A_D23
DDR_A_D22

DDR_A_D28DDR_A_D29
DDR_A_D25DDR_A_D24

DDR_A_DQS#3
DDR_A_DQS3

DDR_A_D31
DDR_A_D30

DDR_CKE1_DIMMA

DDR_A_MA14

DDR_A_MA11

DDR_A_MA6

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

DDR_A_BS1
DDR_A_RAS#
DDR_CS0_DIMMA#

M_ODT0
DDR_A_MA13

DDR_A_D32
DDR_A_D33

DDR_A_DM4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A_DQS#5
DDR_A_DQS5

DDR_A_D42

DDR_A_D52
DDR_A_D53

M_CLK_DDR1
M_CLK_DDR#1

DDR_A_DM6

DDR_A_D51DDR_A_D54
DDR_A_D55

DDR_A_D56

DDR_A_DQS#7
DDR_A_DQS7

DDR_A_D62
DDR_A_D63

12

R116

R115

10K_0402_5%

10K_0402_5%

12

2.2U_0805_16V4Z
C146

1

2

M_CLK_DDR0 9
M_CLK_DDR#0 9

PM_EXTTS#0 9

DDR_CKE1_DIMMA 9

DDR_A_BS1 10
DDR_A_RAS# 10
DDR_CS0_DIMMA# 9

M_ODT0 9

M_CLK_DDR1 9
M_CLK_DDR#1 9

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

DDRII-SODIMM SLOT1

Montevina UMA

1

C151

V_DDR_MCH_REF 9,16

15 46Wednesday, February 18, 2009

1

0.1

0.1U_0402_16V4Z

1

2

5

DDR_B_DQS#[0..7]10

DDR_B_D[0..63]10

DDR_B_DM[0..7]10

DDR_B_DQS[0..7]10

DDR_B_MA[0..14]10

D D

C C

B B

A A

Layout Note:
Place near
JP10

+1.8V

2.2U_0805_16V4Z

2.2U_0805_16V4Z

Layout Note:
Place one cap close to every 2
pullup
resistors terminated to +0.9VS

+0.9V

0.1U_0402_16V4Z

DDR_B_MA3
DDR_B_MA1

DDR_B_BS0
DDR_B_MA10

DDR_CS3_DIMMB#
M_ODT3

DDR_CKE3_DIMMB

C174

1

2

0.1U_0402_16V4Z

1

2

C184

C175

1

2

0.1U_0402_16V4Z

1

2

C185

1 4
2 3

1 4
2 3

2 3
1 4

1 2

R120 56_0402_5%

5

2.2U_0805_16V4Z

2.2U_0805_16V4Z

C176

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

2

2

C187

C186

+0.9V

RP1456_0404_4P2R_5%

RP1656_0404_4P2R_5%

RP2456_0404_4P2R_5%

2.2U_0805_16V4Z

C183

C177

1

1

2

2

0.1U_0402_16V4Z

1

2

C188

+0.9V

0.1U_0402_16V4Z

1

1

2

2

C189

RP35

1 8
2 7
3 6
4 5

56_8P4R_0.05

RP36

1 8
2 7
3 6
4 5

56_8P4R_0.05

RP37

1 8
2 7
3 6
4 5

56_8P4R_0.05

RP38

1 8
2 7
3 6
4 5

56_8P4R_0.05

RP39

1 8
2 7
3 6
4 5

56_8P4R_0.05

0.1U_0402_16V4Z

C190

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C178

1

2

0.1U_0402_16V4Z

1

1

2

2

C192

C191

DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2
DDR_B_BS1
DDR_B_MA0

DDR_B_RAS#
DDR_CS2_DIMMB#
M_ODT2
DDR_B_MA13

DDR_B_BS2
DDR_CKE2_DIMMB
DDR_B_MA9
DDR_B_MA12

DDR_B_MA8
DDR_B_MA5
DDR_B_WE#
DDR_B_CAS#

4

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C179

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C193

C181

C180

1

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

C194

1

1

2

2

C195

Layout Note:
Place these resistor
closely JP3,all
trace length Max=1.5"

C196

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

+1.8V

V_DDR_MCH_REF

JDIMM2

1

VREF

3

DDR_B_D0
DDR_B_D1

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D20

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D19
DDR_B_D18

DDR_B_D28

DDR_B_DM3

DDR_B_D30
DDR_B_D31

DDR_CKE2_DIMMB9

DDR_B_BS210

DDR_B_BS010

DDR_B_WE#10

DDR_B_CAS#10

DDR_CS3_DIMMB#9

M_ODT39

CLK_SMBDATA15,17,24
CLK_SMBCLK15,17,24

+3VS

3

DDR_CKE2_DIMMB

DDR_B_BS2

DDR_B_MA12
DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS0
DDR_B_WE#

DDR_B_CAS#
DDR_CS3_DIMMB#

M_ODT3

DDR_B_D32
DDR_B_D37

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41

DDR_B_DM5

DDR_B_D42
DDR_B_D43

DDR_B_D48
DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D54
DDR_B_D55

DDR_B_D60
DDR_B_D61 DDR_B_D57

DDR_B_DM7

DDR_B_D63
DDR_B_D58

CLK_SMBDATA
CLK_SMBCLK

1

C197

2

2.2U_0603_6.3V4Z

2006/02/13 2006/03/10

1

C198

2

Compal Secret Data

5

7

9

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97

99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

FOX_AS0A426-N8RN-7F

CONN@

0.1U_0402_16V4Z

SO-DIMM B

Deciphered Date

VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

VSS

201

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

VDD

VDD

RAS#

VDD

ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

CK0

A11

BA1

S0#

CK1

SA0
SA1

2

+1.8V

0.1U_0402_16V4Z

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110
112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

VSS

202

2

DDR_B_D5
DDR_B_D4

DDR_B_DM0

DDR_B_D6
DDR_B_D7

DDR_B_D12
DDR_B_D13

DDR_B_DM1

M_CLK_DDR2
M_CLK_DDR#2

DDR_B_D14
DDR_B_D15

DDR_B_D16DDR_B_D21
DDR_B_D17

DDR_B_DM2

DDR_B_D22
DDR_B_D23

DDR_B_D29
DDR_B_D24DDR_B_D25

DDR_B_DQS#3
DDR_B_DQS3

DDR_B_D26
DDR_B_D27

DDR_CKE3_DIMMB

DDR_B_MA14

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS1
DDR_B_RAS#
DDR_CS2_DIMMB#

M_ODT2
DDR_B_MA13

DDR_B_D36
DDR_B_D33

DDR_B_DM4

DDR_B_D39
DDR_B_D38

DDR_B_D44
DDR_B_D45

DDR_B_DQS#5
DDR_B_DQS5

DDR_B_D46
DDR_B_D47

DDR_B_D52
DDR_B_D53

M_CLK_DDR3
M_CLK_DDR#3

DDR_B_DM6

DDR_B_D50
DDR_B_D51

DDR_B_D56

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D59
DDR_B_D62

10K_0402_5%

12

R119

2.2U_0805_16V4Z

M_CLK_DDR2 9
M_CLK_DDR#2 9

PM_EXTTS#1 9

DDR_CKE3_DIMMB 9

1

1

C173

2

2

0612 add

DDR_B_BS1 10
DDR_B_RAS# 10
DDR_CS2_DIMMB# 9

M_ODT2 9

M_CLK_DDR3 9
M_CLK_DDR#3 9

R118

1 2

10K_0402_5%

Title

Size Document Number Rev

Date: Sheet of

+3VS

Compal Electronics, Inc.

DDRII-SODIMM SLOT2

Montevina UMA

1

V_DDR_MCH_REF 9,15

C182

1

16 46Wednesday, February 18, 2009

0.1

5

PCI

FSC

FSB

CLKSEL2

CLKSEL1

00

00

0

1

D D

0

1

0

1

0

1

1

1

1

1

FSA

CPU_BSEL07

C C

FSB

CPU_BSEL17

B B

FSC

CPU_BSEL27

FSA

CLKSEL0

0

1

0

1

0

1

0

1

R128

1 2

2.2K_0402_5%
R138

1 2

0_0402_5%

R154

1 2

0_0402_5%

R164

1 2

10K_0402_5%
R171

1 2

0_0402_5%

CPU
MHz

266

133

200

166

333

100

400

+VCCP

+VCCP

12

1 2

12

1 2

1 2

12

12

1 2

12

MHz

100

100

100

100

100

100

100

R123

1 2

56_0402_5%
CLRP1
NO SHORT PADS

R129
1K_0402_5%

@

R139
1K_0402_5%

@

R143
1K_0402_5%

R150
1K_0402_5%

@

R157
0_0402_5%

@

R163
1K_0402_5%

R165
1K_0402_5%

@

R174
0_0402_5%

SRC

REF

MHz

MHz

33.3

14.318 96.0 48.0

14.318

33.3

14.318

33.3

14.318

33.3

14.318

33.3

14.318

33.3

14.318

33.3

Reserved

+VCCP

MCH_CLKSEL0 9

MCH_CLKSEL1 9

MCH_CLKSEL2 9

DOT_96
MHz

CLK_DEBUG_PORT_126

NB
(UMA)

96.0

96.0

96.0

96.0

96.0

96.0

CLK_PCI_EC32

CLK_PCI_ICH20

NB
CPU

CLK_ENABLE#42

CLK_14M_ICH22

CK_PWRGD22

4

USB
MHz

+3VS

R121

1 2

0_0805_5%

+3VS_CK505

48.0

48.0

48.0

48.0

48.0

48.0

CLKREQ#_79

CLK_MCH_BCLK9
CLK_CPU_BCLK#6
CLK_CPU_BCLK6

VGATE22,42

CLK_SMBDATA15,16,24

CLK_SMBCLK15,16,24

Routing the trace at least
10mil

Y1

1 2

2

C213

18P_0402_50V8J

R141 0_0402_5%@

1 2

R142 0_0402_5%@

1 2

R140 0_0402_5%

1 2

R147 33_0402_1%

1 2

R393 39_0402_1%

1 2

R158 33_0402_1%

1 2

R161 33_0402_1%

1 2

1

R126 475_0402_1%

T44

T83

CLK_XTAL_OUT

CLK_XTAL_IN

14.318MHZ_16PF_7A14300083

2

C214
18P_0402_50V8J

1

1 2

R_CKPWRGD
FSB

CLK_XTAL_OUT
CLK_XTAL_IN

FSC
REF1
CLK_SMBDATA
CLK_SMBCLK

PCI2_1
PCI2_TME
27_SEL
PCI_CLK3
ITP_EN

+3VS_CK505

SI-1 Using USB_0 for CLK_48M_CR

R167 22_0402_1%

CLK_48M_ICH22
CLK_48M_CR27

CLK_MCH_DREFCLK9
CLK_MCH_DREFCLK#9

1 2

R1101 22_0402_1%

1 2

1

C199

10U_0805_10V4Z

2

R_CLKREQ#_7

U3

1

CKPWRGD/PD#

2

FS_B/TEST_MODE

3

VSS_REF

4

XTAL_OUT

5

XTAL_IN

6

VDD_REF

7

REF_0/FS_C/TEST_

8

REF_1

9

SDA

10

SCL

11

NC

12

VDD_PCI

13

PCI_1

14

PCI_2

15

PCI_3

16

PCI_4/SEL_LCDCL

17

PCIF_5/ITP_EN

18

VSS_PCI

73

thm_pad

+3VS_CK505

FSA

+1.05VS_CK505

3

1

C200

0.1U_0402_16V4Z

2

+VCCP

R122

1 2

0_0805_5%

+3VS_CK505

72

71

70

69

68

67

66

65

CPU_0

CPU_1

CPU_0#

CPU_1#

VSS_CPU

VDD_CPU

VDD_CPU_IO

VDD_4819USB_0/FS_A20USB_1/CLKREQ_A#21VSS_4822VDD_IO23SRC_0/DOT_9624SRC_0#/DOT_96#25VSS_IO26VDD_PLL327LCDCLK/27M28LCDCLK#/27M_SS29VSS_PLL330VDD_PLL3_IO31SRC_232SRC_2#33VSS_SRC34SRC_335SRC_3#

10U_0805_10V4Z

+1.05VS_CK505

64

63

62

61

60

SRC_7

CLKREQ_7#

VDD_SRC_IO

SRC_8/CPU_ITP

SRC_8#/CPU_ITP#

1

C201

0.1U_0402_16V4Z

2

+1.05VS_CK505

1

C206

2

59

58

57

56

SRC_6

SRC_7#

SRC_6#

VSS_SRC

CLKREQ_6#

+1.05VS_CK505

1

C202

0.1U_0402_16V4Z

2

Place close to U3

0.1U_0402_16V4Z

1

C207

2

0.1U_0402_16V4Z

R_CLKREQ#_6

+3VS_CK505

55

VDD_SRC

CPU_STOP#

VDD_SRC_IO

CLKREQ_10#

CLKREQ_11#

VDD_SRC_IO

SLG8SP553VTR_QFN72_10x10

36

PCI_STOP#

SRC_10#

SRC_10

SRC_11

SRC_11#

SRC_9#

SRC_9

CLKREQ_9#

VSS_SRC

CLKREQ_4#

SRC_4#

SRC_4

CLKREQ_3#

54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37

2

1

C203

0.1U_0402_16V4Z

2

10U_0805_10V4Z

1

1

2

C209

C208

2

+1.05VS_CK505

0.1U_0402_16V4Z

R133 475_0402_1%

1 2

H_STP_PCI#
H_STP_CPU#

R_CLKREQ#_10

R_CLKREQ#_9

R_CLKREQ#_4

R_CLKREQ#_C

1

C204

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

1

1

2

C211

C210

2

0.1U_0402_16V4Z

H_STP_PCI# 22
H_STP_CPU# 22

R146 475_0402_1%

1 2

R738 475_0402_1%

1 2

R156 475_0402_1%

1 2

R162 475_0402_1%

1 2

1

C205

0.1U_0402_16V4Z

2

47P_0402_50V8J

1

1

C212

C1506

2

2

47P_0402_50V8J

For WWAN

CLK_MCH_3GPLL 9
CLK_MCH_3GPLL# 9CLK_MCH_BCLK#9

CLKREQ#_6 26

CLK_PCIE_MCARD2 26
CLK_PCIE_MCARD2# 26

CLK_PCIE_SATA# 21
CLK_PCIE_SATA 21

CLK_PCIE_ICH# 22
CLK_PCIE_ICH 22

MCH_SSCDREFCLK# 9
MCH_SSCDREFCLK 9

1

1

C1496

47P_0402_50V8J

2

For WWAN

1

C1507

2

3G_PLL

MiniCard_2(WLAN)

CLK_PCIE_MCARD0# 26
CLK_PCIE_MCARD0 26

CLKREQ#_10 26

CLK_PCIE_LAN# 25
CLK_PCIE_LAN 25

CLKREQ#_9 25

CLKREQ#_4 26

CLK_PCIE_NCARD# 26
CLK_PCIE_NCARD 26

CLKREQ#_C 22

SATA

ICH

NB_SSC (UMA)

MiniCard_0

LAN

New Card

+3VS

R178

2.2K_0402_5%

2007/08/28 2006/03/10

R179

2.2K_0402_5%

CLK_SMBDATA

CLK_SMBCLK

Compal Secret Data

Deciphered Date

EMI

C1482

@

5P_0402_50V8C

C215

@

5P_0402_50V8C

C216

12P_0402_50V8J

C217

@

47P_0402_50V8J

C218

@

47P_0402_50V8J

C219

@

47P_0402_50V8J

Install C217,C218,C219 for WWAN
noise

Title

Size Document Number Rev

2

Date: Sheet of

Compal Electronics, Inc.

Clock Generator CK505

Montevina UMA

CLK_48M_CR

12

CLK_48M_ICH

12

CLK_14M_ICH

12

CLK_PCI_ICH

12

CLK_PCI_EC

12

CLK_DEBUG_PORT_1

12

1

17 46Wednesday, February 18, 2009

0.1

Q3A

6 1

5

2N7002DW-7-F_SOT363-6

4

+3VS

2

3

ITP_EN

PCI_CLK3

A A

0 =
SRC8/SRC8#

1 =
ITP/ITP#

0 = Enable DOT96 &
SRC1(UMA)

1 = Enable SRC0 &
27MHz(DIS)

+3VS +3VS

12

R180
10K_0402_5%

ITP_EN PCI_CLK3

12

@

R182
10K_0402_5%

5

12

@

R181
10K_0402_5%

12

R183
10K_0402_5%

+3VS

SB, MINI
PCI

ICH_SMBDATA22,26

ICH_SMBCLK22,26

Q3B

3

2N7002DW-7-F_SOT363-6

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

1 1

+5VS +5VS

C221

0.1U_0402_16V4Z

1 2

1

5

U4
SN74AHCT1G125GW_SOT353-5

2 2

CRT_HSYNC11

CRT_VSYNC11

CRT_HSYNC

CRT_VSYNC

P

A2Y

G

3

4

OE#

B

C222

0.1U_0402_16V4Z

1 2

HSYNC_G_A

1

5

P

A2Y

G

3

VSYNC_G_A D_VSYNC

4

OE#

U5
SN74AHCT1G125GW_SOT353-5

R184

1 2

R189

1 2

0_0603_5%

0_0603_5%

RED

GREEN

BLUE

D_HSYNC

@

1

C223

5P_0402_50V8C

2

C

D4

2 1

RB491D_SC59-3

@

1

C224

5P_0402_50V8C

2

F1

1.1A_6VDC_FUSE

2.2K_0402_5%

D_DDCDATA

D_DDCCLK

21

11

12

13

14

10
15

12

R185

+CRTVDD+RCRT_VCC+5VS

W=40mils

0.1U_0402_16V4Z

JCRT1

6

1
7

2
8

3
9

4

5

SUYIN_070546FR015S263ZR

CONN@

2.2K_0402_5%

C220

16
17

12

R186

2N7002DW-7-F_SOT363-6

1

2

6 1

D

+3VS+CRTVDD +CRTVDD

2

Q5A

2N7002DW-7-F_SOT363-6

E

BLUE
GREEN
RED

D5

@

+3VS

12

12

R187

2.2K_0402_5%

5

3

4

Q5B

1

2

3

DAN217T146_SC59-3

R188

2.2K_0402_5%

3VDDCDA

3VDDCCL

D6

@

1

2

3

D7

@

DAN217T146_SC59-3

3VDDCDA 11

3VDDCCL 11

Place close to
JCRT1

1

2

3

+CRTVDD

DAN217T146_SC59-3

CRT Termination/EMI Filter

3 3

M_RED11

M_GREEN11

M_BLUE11

4 4

12

12

R196

R195

150_0402_1%

C_RED

C_GRN

22P_0402_50V8J

12

R197

150_0402_1%

150_0402_1%

22P_0402_50V8J

1

1

2

2

C226

@

C225

@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

22P_0402_50V8J

1

2

C227

@

C

L2

1 2

HLC0603CSCCR11JT_0603

L3

1 2

HLC0603CSCCR11JT_0603

L4

1 2

HLC0603CSCCR11JT_0603

2007/08/28 2006/07/26

10P_0402_50V8J

1

1

2

2

C228

C229

Compal Secret Data

Deciphered Date

RED

GREEN

BLUEC_BLU

10P_0402_50V8J

10P_0402_50V8J

1

2

C230

Title

Size Document Number Rev

D

Date: Sheet of

Compal Electronics, Inc.

CRT Connector

Montevina UMA

18 46Wednesday, February 18, 2009

E

0.1

5

INVPWR_B++LCDVDD+3VS

C236

+5VALW

C235

12

680P_0402_50V7K

USB20_P422
USB20_N42 2

LVDS_BCLK+11

LVDS_BCLK-11

LVDS_B0+11

LVDS_B0-11

LVDS_B1+11

LVDS_B1-11

LVDS_B2+11

LVDS_B2-11

D61

4

VIN

3

IO2

PRTR5V0U2X_SOT143-4

D D

C C

USB20_P4

C237

1

12

2

680P_0402_50V7K

USB20_P4
USB20_N4

LVDS_BCLK+
LVDS_BCLK-

LVDS_B0+
LVDS_B0­LVDS_B1+
LVDS_B1­LVDS_B2+
LVDS_B2-

USB20_N4

2

IO1

1

GND

LVDS CONN & USB Camera + Dig Mic

680P_0402_50V7K

+3VS

JLVDS1

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39
GND41GND

ACES_88242-4001

CONN@

4

LVDS_A2-

2

2

LVDS_A2+

4

4

LVDS_A1-

6

6

LVDS_A1+

8

8

LVDS_A0-

10

10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

LVDS_A0+

12

LVDS_ACLK-

14

LVDS_ACLK+

16
18
20
22

DMIC_DAT

24

DMIC_CLK

26

+3V_LOGO

BKOFF#

DDC2_CLK
DDC2_DATA

R727

100_0805_5%

+USB_CAM

1 2

1

2

28
30
32
34
36
38
40
42

LVDS_A2- 11
LVDS_A2+ 11
LVDS_A1- 11
LVDS_A1+ 11
LVDS_A0- 11
LVDS_A0+ 11
LVDS_ACLK- 11
LVDS_ACLK+ 11

DMIC_DAT 28

DMIC_CLK 28

12

R1237 0_0402_5%@

DDC2_CLK 11
DDC2_DATA 11

R1238 0_0402_5%

C434
680P_0402_50V7K

12

+5VS

INV_PWM

BKOFF#

3

R245

@

10K_0402_5%

0.1U_0402_16V4Z

1 2

INV_PWM 32

BKOFF# 32

NB_BKLT_CTRL 11

+LCDVDD

C231

100_0805_5%

1

1

C232

0.1U_0402_16V4Z

2

2

Limited Current < 1A

2

+5VALW+LCDVDD

R199

1M_0402_5%

5

12

R200

100K_0402_5%

3

Q8B
2N7002DW-7-F_SOT363-6

4

12

R198

61

2

2N7002DW-7-F_SOT363-6
Q8A

ENAVDD11

100K_0402_5%

R201

12

Avoid Panel display garbage after power on.

C233

4.7U_0805_10V4Z

12

+LCDVDD

1

2

Q7

SI2301BDS-T1-E3_SOT23-3

1 3

D

C238

0.047U_0402_16V7K

1

+3VS

S

G

C234

1

2

4.7U_0805_10V4Z

2

EMI request.

LVDS_ACLK+
LVDS_ACLK­DDC2_CLK
DDC2_DATA
LVDS_BCLK+
LVDS_BCLK-

C1399 100P_0402_50V8J@

1 2

C1400 100P_0402_50V8J@

1 2

C1401 100P_0402_50V8J@

1 2

C1402 100P_0402_50V8J@

1 2

C1504 100P_0402_50V8J@

1 2

C1505 100P_0402_50V8J@

1 2

EMI request

R202

2.2K_0402_5%

DDC2_CLK
DDC2_DATA

+3VS

1 2

R203

2.2K_0402_5%

1 2

Must close JLVDS1pin 24、26

DMIC_CLK

DMIC_DAT

1

1

C302

@

220P_0402_25V8J

2

C303

@

220P_0402_25V8J

2

@

L5 0_ 0805_5%

1 2

L6

1 2

FBMA-L11-201209-221LMA30T_0805

INVPWR_B+B+

EMI reserver

B B

USB Camera

12

R1091
215K_0603_1%

12

R1093
100K_0402_1%

+USB_CAM

1

2

C1391

10U_0805_6.3V6M

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/07/26

Compal Secret Data

Deciphered Date

2

Date: Sheet of

Title

Size Document Number Rev

Compal Electronics, Inc.

LCD CONN.

Montevina UMA

19 46Wednesday, February 18, 2009

1

0.1

+5VS

U42

1

IN

2

GND

3

1

C1392

10U_0805_6.3V6M

A A

+USB_CAM is +3.9VS, R1091:215K; R1093:100Kohm

5

R440

0_0402_5%

2

1 2

SHDN

G916-390T1UF_SOT23-5

+USB_CAM=1.25(1+R1091/R10 93)

OUT

BYP

5

4

4

5

+3VS

R274 8.2K_0402_5%

1 2

R275 8.2K_0402_5%

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

RP28

1 8
2 7
3 6
4 5

12

R277 8.2K_0402_5%

R278 8.2K_0402_5%

D D

C C

R279 8.2K_0402_5%

+3VS

R281 8.2K_0402_5%

R283 8.2K_0402_5%

R284 8.2K_0402_5%

R286 8.2K_0402_5%

R288 8.2K_0402_5%

R292 8.2K_0402_5%

R293 8.2K_0402_5%

+3VS

R272 8.2K_0402_5%

R290 8.2K_0402_5%

R273 8.2K_0402_5%

R276 8.2K_0402_5%

8.2K_0804_8P4R_5%

PCI_TRDY#

PCI_FRAME#

PCI_IRDY#

PCI_SERR#

PCI_PERR#

PCI_PIRQA#

PCI_PIRQC#

PCI_PIRQD#

PCI_PIRQF#

PCI_PIRQH#

PCI_REQ2#

PCI_REQ3#

PCI_DEVSEL#

PCI_REQ1#

PCI_STOP#

PCI_PLOCK#

PCI_PIRQE#
PCI_PIRQB#
PCI_PIRQG#
PCI_REQ0#

4

U12B

D11

AD0

C8

AD1

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

D9

E12

E9
C9

E10

B7
C7
C5

G11

F8

F11

E7
A3
D2

F10

D5

D10

B3
F7
C3
F3
F4
C1

G7

H7
D1

G5

H6

G1

H3

J5

E1

J6

C4

ICH9-M ES_FCBGA676

PCI

AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

Interrupt I/F

PIRQA#
PIRQB#
PIRQC#
PIRQD#

REQ0#

GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55

C/BE0#

C/BE1#

C/BE2#

C/BE3#

IRDY#

PAR

PCIRST#

DEVSEL#

PERR#

PLOCK#

SERR#

STOP#

TRDY#

FRAME#

PLTRST#

PCICLK

PME#

PIRQE#/GPIO2
PIRQF#/GPIO3

PIRQG#/GPIO4

PIRQH#/GPIO5

3

PCI_REQ0#

F1

PCI_GNT0#

G4

PCI_REQ1#

B6
A7

PCI_REQ2#

F13
F12

PCI_REQ3#

E6

PCI_GNT3#

F6

D8
B4
D6
A5

PCI_IRDY#

D3
E3

PCI_RST#

R1

PCI_DEVSEL#

C6

PCI_PERR#

E4

PCI_PLOCK#

C2

PCI_SERR#

J4

PCI_STOP#

A4

PCI_TRDY#

F5

PCI_FRAME#

D7

PLT_RST#

C14

CLK_PCI_ICH

D4

PCI_PME#

R2

PCI_PIRQE#

H4

PCI_PIRQF#

K6

PCI_PIRQG#

F2

PCI_PIRQH#

G2

PCI_RST# 32

PCI_SERR# 32

PLT_RST# 9,25,26
CLK_PCI_ICH 17
PCI_PME# 32

1 2

R291 0_0402_5%

ACCEL_INT 24

2

Place closely pin D4

CLK_PCI_ICH

12

@

R280
10_0402_5%

1

@

C425

8.2P_0402_50V

2

1

B B

A A

A16 swap override Strap

PCI_GNT3#

PCI_GNT3#

Low= A16 swap override Enble
High= Default

R294

@

1 2

5

*

1K_0402_5%

Boot BIOS Strap

PCI_GNT0# SPI_CS#1

0

1

SPI_CS1#_R22

4

1

01

1

SPI_CS1#_R

PCI_GNT0#

Boot BIOS Location

SPI

PCI

LPC

*

R295

@

1 2

@

R296

1 2

1K_0402_5%

1K_0402_5%

+3VALW

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

ICH9(1/4)-PCI/INT

Montevina UMA

20 46Wednesday, February 18, 2009

1

0.1

5

+RTCVCC

HDA_SYNC_CODEC28

HDA_SYNC_NB9

HDA_RST#_CODEC28,32

HDA_RST#_NB9

1 2

1 2

1 2

1 2

SM_INTRUDER#

LAN100_SLP

ICH_INTVRMEN

ICH_SRTCRST#

C426

0.1U_0402_16V4Z

12

CLRP2
SHORT PADS

R312 33_0402_5%

R207 33_0402_5%

HDA_SDIN028

HDA_SDIN29

HDA_SDOUT_CODEC28
HDA_SDOUT_NB9

1

2

0_0402_5%

R307

1 2

20K_0402_5%

1U_0603_10V4Z

R316 33_0402_5%

R208 33_0402_5%
R317 33_0402_5%

R209 33_0402_5%

SATA_LED#33

SATA_RXN0_C24
SATA_RXP0_C24
SATA_TXN024
SATA_TXP024

12

@

R303

0_0402_5%

C427

1 2

1 2

12

@

R304

1

2

1 2

1 2
1 2

1 2

R321 33_0402_5%
R204 33_0402_5%

SATA_TXN0
SATA_TXP0

HDABITCLK

SI-1 Remove SSC

Reserve SSC for EMI

1 2

R297 1M_0402_5%

1 2

R299 330K_0402_5%

1 2

R300 330K_0402_5%

1 2

D D

C C

R302 180K_0402_5%

+RTCVCC

HDA_BITCLK_CODEC28

HDA_BITCLK_NB9

P- HDD

Add 12p on HDA_SDOUT and HDA_SDOUT

B B

Add 12p on HDA_BITCLK_CODE and HDA_BITCLK_NB

HDA_SDOUT_CODEC

HDA_SDOUT_NB

HDA_BITCLK_CODEC

HDA_BITCLK_NB

C312 12P_0402_50V8J

C66 12P_0402_50V8J

C316 12P_0402_50V8J

C67 12P_0402_50V8J

4

ICH9M Internal VR Enable Strap
(Internal VR for VccSus1.05, VccSus1.5, VccCL1.5)

ICH_INTVRMEN

ICH9M LAN100 SLP Strap
(Internal VR for VccLAN1.05 and VccCL1.05)

ICH_LAN100_SLP Low = Internal VR Disabled

+1.5VS

R311

24.9_0402_1%

1 2

R259

1 2

0_0402_5%

1 2
1 2

T55PA D
T56PA D

0.01U_0402_16V7K

C431

1 2

C433

1 2

0.01U_0402_16V7K

Low = Internal VR Disabled
High = Internal VR Enabled(Default)

High = Internal VR Enabled(Default)

ICH_RTCX1
ICH_RTCX2

ICH_RTCRST#
ICH_SRTCRST#
SM_INTRUDER#

ICH_INTVRMEN
LAN100_SLP

GLAN_COMP

HDA_BITCLK
HDA_SYNC

HDARST#

HDA_SDIN0

HDA_SDIN2

HDA_SDOUT

SATA_LED#

SATA_TXN0_C
SATA_TXP0_C

U12A

C23

RTCX1

C24

RTCX2

A25

RTCRST#

F20

SRTCRST#

C22

INTRUDER#

B22

INTVRMEN

A22

LAN100_SLP

E25

GLAN_CLK

C13

LAN_RSTSYNC

F14

LAN_RXD0

G13

LAN_RXD1

D14

LAN_RXD2

D13

LAN_TXD_0

D12

LAN_TXD_1

E13

LAN_TXD_2

B10

GPIO56

B28

GLAN_COMPI

B27

GLAN_COMPO

AF6

HDA_BIT_CLK

AH4

HDA_SYNC

AE7

HDA_RST#

AF4

HDA_SDIN0

AG4

HDA_SDIN1

AH3

HDA_SDIN2

AE5

HDA_SDIN3

AG5

HDA_SDOUT

AG7

HDA_DOCK_EN#/GPIO33

AE8

HDA_DOCK_RST#/GPIO34

AG8

SATALED#

AJ16

SATA0RXN

AH16

SATA0RXP

AF17

SATA0TXN

AG17

SATA0TXP

AH13

SATA1RXN

AJ13

SATA1RXP

AG14

SATA1TXN

AF14

SATA1TXP

ICH9-M ES_FCBGA676

3

LPC_AD0

K5

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

FWH4/LFRAME#

RTC

LPCCPU

LAN / GLAN

IHDA

SATA

LDRQ0#

LDRQ1#/GPIO23

A20GATE

A20M#

DPRSTP#

DPSLP#

FERR#

CPUPWRGD

IGNNE#

INIT#
INTR

RCIN#

SMI#

STPCLK#

THRMTRIP#

TP12

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

SATA_CLKN
SATA_CLKP

SATARBIAS#

SATARBIAS

LPC_AD1

K4

LPC_AD2

L6

LPC_AD3

K2

LPC_FRAME#

K3

J3
J1

GATEA20

N7

H_A20M#

AJ27

AJ25

H_DPSLP#

AE23

R_H_FERR#

AJ26

H_PWRGOOD

AD22

H_IGNNE#

AF25

H_INIT#

AE22

H_INTR

AG25

KB_RST#

L3

H_NMI

AF23

NMI

H_SMI#

AF24

H_STPCLK#

AH27

THRMTRIP_ICH#

AG26

AG27

AH11
AJ11

SATA_TXN4_C

AG12

SATA_TXP4_C

AF12

AH9
AJ9

SATA_TXN5_C

AE10

SATA_TXP5_C

AF10

CLK_PCIE_SATA#

AH18

CLK_PCIE_SATA

AJ18
AJ7

R322

AH7

1 2

24.9_0402_1%

Within 500 mils

2

LPC_AD[0..3] 26,32

LPC_FRAME# 26,32

T54 PAD

GATEA20 32
H_A20M# 6

R309

1 2

R310

R319 54.9_0402_1%

0.01U_0402_16V7K

0.01U_0402_16V7K

0_0402_5%

1 2

56_0402_5%

H_PWRGOOD 7

H_IGNNE# 6

H_INIT# 6
H_INTR 6

KB_RST# 32

H_NMI 6
H_SMI# 6

H_STPCLK# 6

1 2

C428

12

C429

12

0.01U_0402_16V7K
C430

12

C432

12

0.01U_0402_16V7K

SATA_TXN4
SATA_TXP4

SATA_TXN5
SATA_TXP5

H_DPRSTP#H_DPRSTP_R#

H_FERR#

GATEA20

KB_RST#

H_DPRSTP#

H_DPSLP#

H_DPRSTP# 7,9,42
H_DPSLP# 7

+VCCP

12

R315
56_0402_5%

placed within 2"
from ICH9M

SATA_RXN4_C 24
SATA_RXP4_C 24

SATA_TXN4 24

SATA_TXP4 24

SATA_RXN5_C 30
SATA_RXP5_C 30

SATA_TXN5 30

SATA_TXP5 30

CLK_PCIE_SATA# 17
CLK_PCIE_SATA 17

+3VS

R298

1 2

8.2K_0402_5%

R301

1 2

10K_0402_5%

+VCCP

R305

@

1 2

56_0402_5%

R306

@

1 2

56_0402_5%

+VCCP

R308
56_0402_5%

1 2

within 2" from R379

H_THERMTRIP# 6,9

ODD

e-SATA

De-feature disa ble

1

H_FERR# 6

Reserve cap on HDA_BITCLK for WWAN noise issue

BATT1

XOR CHAIN ENTRANCE STRAP:RSVD

+3VS

R325

@

1 2

R326

@

1 2

A A

ICH_RSVD HDA_SDOUT_CODEC

0
0

1
1 1

1K_0402_5%

1K_0402_5%

HDA_SDOUT_CODEC

ICH_RSVD

0
1

0

5

ICH_RSVD 22

C436

15P_0402_50V8J

R328

1 2

10M_0402_5%

1

2

Y2

1 4

2 3

32.768KHZ_12.5P_MC-146

4

ICH_RTCX1

ICH_RTCX2

1

C437

15P_0402_50V8J

2

R329

W=20mils

1 2

W=20mils

1

C438

2.2U_0603_6.3V4Z

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

0_0402_5%

Place near ICH9

2

1

DAN202U_SC70

+3VL+RTCVCC

D8

2

3

W=20mils

Title

Size Document Number Rev

Custom

Montevina UMA

Date: Sheet of

BATT1.1

R330

1 2

1K_0402_5%

C435

0.1U_0402_16V4Z

PV for ESD

Compal Electronics, Inc.

ICH9(2/4)_LAN,HD,IDE,LPC

W=20mils

1

2

@

CR2032 RTC BATT ERY

1

JBATT1

1

1

2

2

3

GND

4

GND

ACES_85205-02001

CONN@

21 46Wednesday, February 18, 2009

0.1

5

+3VS

1 2

R333 10K_0402_5%

1 2

R334 8.2K_0402_5%

1 2

R335 10K_0402_5%

1 2

R336 8.2K_0402_5%@

1 2

D D

C C

B B

A A

R337 10K_0402_5%

1 2

R338 8.2K_0402_5%@

1 2

R341 8.2K_0402_5%

1 2

R344 8.2K_0402_5%

1 2

R356 8.2K_0402_5%

1 2

R349 8.2K_0402_5%

1 2

R350 8.2K_0402_5%

1 2

R351 8.2K_0402_5%

1 2

R352 8.2K_0402_5%

1 2

R357 8.2K_0402_5%

1 2

R358 8.2K_0402_5%

1 2

R359 10K_0402_5%

1 2

R361 8.2K_0402_5%@

1 2

R362 8.2K_0402_5%

1 2

R365 10K_0402_5%@

+3VALW

1 2

R369 10K_0402_5%

1 2

R371 8.2K_0402_5%

1 2

R372 1K_0402_5%

1 2

R374 10K_0402_5%

1 2

R375 10K_0402_5%

1 2

R376 10K_0402_5%

1 2

R377 10K_0402_5%

1 2

R378 10K_0402_5%

1 2

R379 10K_0402_5%

1 2

R373 10K_0402_5%

1 2

R380 8.2K_0402_5%

1 2

R381 8.2K_0402_5%

+3VS +3VS

R745

@

10K_0402_5%

1 2

DIS/UMA

R746
10K_0402_5%

1 2

USB_OC#6
USB_OC#1
USB_OC#2
USB_OC#4

USB_OC#7
USB_OC#8
USB_OC#9
USB_OC#0

WXMIT_OFF#
USB_OC#5
USB_OC#10
USB_OC#11

SIRQ

PM_CLKRUN#

OCP#

THERM_SCI#

CLKREQ#_C

PM_BMBUSY#

EC_SCI#

CR_CPPE#

CR_WAKE#

GPIO18

HDDHALT_LED#

GPIO20

GPIO21

GPIO36

GPIO37

GPIO39

GPIO48

GPIO57

GPIO49

LINKALERT#

ICH_LOW_BAT#

ICH_PCIE_WAKE#

ICH_RI#

XDP_DBRESET#

S4_STATE#

ME_EC_CLK1

ME_EC_DATA1

GPIO10

EC_LID_OUT#

EC_SMI#

GPIO14

Board ID

R747

@

10K_0402_5%

1 2

17/14

R748
10K_0402_5%

1 2

1 2

R1179 10K_0402_5%

1 2

R1180 10K_0402_5%

1 2

R1181 10K_0402_5%

1 2

R1182 10K_0402_5%

1 2

R1183 10K_0402_5%

1 2

R1184 10K_0402_5%

1 2

R1185 10K_0402_5%

1 2

R1186 10K_0402_5%

1 2

R1187 10K_0402_5%

1 2

R1188 10K_0402_5%

1 2

R1189 10K_0402_5%

1 2

R1190 10K_0402_5%

5

+3VALW

+3VALW

10K_0402_5%

H_STP_PCI#17
H_STP_CPU#17

EC_SCI#32
EC_SMI#32

+3VS

WWAN

WLAN

LAN

New Card

R331 2.2K_0402_5%
R332 2.2K_0402_5%

ICH_SMBCLK17,26

ICH_SMBDATA17,26

+3VS

12

12

R339

@

VGATE17,42

R366
Low
High -->No

-->default
boot

R340

@

10K_0402_5%

R345 0_0402_5%

R353

100K_0402_5%

1 2

R364 8.2K_0402_5%

EXP_CPPE#26

+3VS

SB_SPKR28

SPI_CS1#_R20

4

1 2
1 2

T57PAD

XDP_DBRESET#6

PM_BMBUSY#9

EC_LID_OUT#32

1 2

ICH_PCIE_WAKE#25,26
SIRQ32
THERM_SCI#32

1 2

R225 0_0402_5%

1 2

R226 0_0402_5%@

1 2

R366 1K_0402_5% @

PCIE_RXN126
PCIE_RXP126
PCIE_TXN126

PCIE_TXP126

PCIE_RXN326
PCIE_RXP326
PCIE_TXN326

PCIE_TXP326

GLAN_RXN25
GLAN_RXP25
GLAN_TXN25

GLAN_TXP25

PCIE_RXN426
PCIE_RXP426
PCIE_TXN426

PCIE_TXP426

BT_OFF30

WXMIT_OFF#26

T59PA D

OCP#6

CLKREQ#_C17

R739

@

1 2

0_0402_5%

1 2

MCH_ICH_SYNC#9

ICH_RSVD21

C445 0.1U_0402_16V4Z
C444 0.1U_0402_16V4Z

C448 0.1U_0402_16V4Z
C449 0.1U_0402_16V4Z

C452 0.1U_0402_16V4Z
C453 0.1U_0402_16V4Z

C450 0.1U_0402_16V4Z
C451 0.1U_0402_16V4Z

R383 0_0402_5%

4

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2

ICH_SMBCLK
ICH_SMBDATA
LINKALERT#
ME_EC_CLK1
ME_EC_DATA1

ICH_RI#

SUS_STAT#
XDP_DBRESET#

PM_BMBUSY#

EC_LID_OUT#

H_STP_PCI#
R_STP_CPU#

PM_CLKRUN#

ICH_PCIE_WAKE#
SIRQ
THERM_SCI#

VGATE

OCP#
CR_CPPE#
EC_SCI#_SB
EC_SMI#
EC_SCI#_GPIO12

T46PA D

17/14
GPIO18
GPIO20
CR_WAKE#
DIS/UMA

T47PA D

CLKREQ#_C
GPIO38
GPIO39
GPIO48
GPIO49
GPIO57

SB_SPKR
MCH_ICH_SYNC#
ICH_RSVD

12

Within 500 mils

R384

22.6_0402_1%

3

U12C

G16

SMBCLK

A13

SMBDATA

E17

LINKALERT#/GPIO60/CLGPIO4

C17

SMLINK0

B18

SMLINK1

F19

RI#

R4

SUS_STAT#/LPCPD#

G19

SYS_RESET#

M6

PMSYNC#/GPIO0

A17

SMBALERT#/GPIO11

A14

STP_PCI#

E19

STP_CPU#

L4

CLKRUN#

E20

WAKE#

M5

SERIRQ

AJ23

THRM#

D21

VRMPWRGD

A20

TP11

AG19

GPIO1

AH21

GPIO6

AG21

GPIO7

A21

GPIO8

C12

GPIO12

C21

GPIO13

AE18

GPIO17

K1

GPIO18

AF8

GPIO20

AJ22

SCLOCK/GPIO22

A9

GPIO27

D19

GPIO28

L1

SATACLKREQ#/GPIO35

AE19

SLOAD/GPIO38

AG22

SDATAOUT0/GPIO39

AF21

SDATAOUT1/GPIO48

AH24

GPIO49

A8

GPIO57/CLGPIO5

M7

SPKR

AJ24

MCH_SYNC#

B21

TP3

AH20

TP8

AJ20

TP9

AJ21

TP10

ICH9-M ES_FCBGA676

PCIE_RXN1
PCIE_RXP1
PCIE_C_TXN1
PCIE_C_TXP1

PCIE_RXN3
PCIE_RXP3
PCIE_C_TXN3
PCIE_C_TXP3

GLAN_RXN
GLAN_RXP
GLAN_TXN_C
GLAN_TXP_C

PCIE_RXN4
PCIE_RXP4
PCIE_C_TXN4
PCIE_C_TXP4

SPI_CS1#_R

USB_OC#0
USB_OC#1
USB_OC#2
WXMIT_OFF#
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7
USB_OC#8
USB_OC#9
USB_OC#10
USB_OC#11

USBRBIAS

SMB

U12D

N29

PERN1

N28

PERP1

P27

PETN1

P26

PETP1

L29

PERN2

L28

PERP2

M27

PETN2

M26

PETP2

J29

PERN3

J28

PERP3

K27

PETN3

K26

PETP3

G29

PERN4

G28

PERP4

H27

PETN4

H26

PETP4

E29

PERN5

E28

PERP5

F27

PETN5

F26

PETP5

C29

PERN6/GLAN_RXN

C28

PERP6/GLAN_RXP

D27

PETN6/GLAN_TXN

D26

PETP6/GLAN_TXP

D23

SPI_CLK

D24

SPI_CS0#

F23

SPI_CS1#GPIO58/CLGPIO6

D25

SPI_MOSI

E23

SPI_MISO

N4

OC0#/GPIO59

N5

OC1#/GPIO40

N6

OC2#/GPIO41

P6

OC3#/GPIO42

M1

OC4#/GPIO43

N2

OC5#/GPIO29

M4

OC6#/GPIO30

M3

OC7#/GPIO31

N3

OC8#/GPIO44

N1

OC9#/GPIO45

P5

OC10#/GPIO46

P3

OC11#/GPIO47

AG2

USBRBIAS

AG1

USBRBIAS#

ICH9-M ES_FCBGA676

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

SATA0GP/GPIO21
SATA1GP/GPIO19
SATA4GP/GPIO36
SATA5GP/GPIO37

SATA

GPIO

clocks

SYS / GPIOGPIOMISC

Power MGT

GPIO10/SUS_PWR_ACK

GPIO14/AC_PRESENT

Controller Link

PCI - Express

SPI

USB

CLK14
CLK48

SUSCLK

SLP_S3#
SLP_S4#
SLP_S5#

S4_STATE#/GPIO26

PWROK

DPRSLPVR/GPIO16

BATLOW#

PWRBTN#

LAN_RST#

RSMRST#

CK_PWRGD

CLPWROK

SLP_M#

CL_CLK0
CL_CLK1

CL_DATA0
CL_DATA1

CL_VREF0
CL_VREF1

CL_RST0#
CL_RST1#

MEM_LED/GPIO24

WOL_EN/GPIO9

DMI0RXN
DMI0RXP

DMI0TXN
DMI0TXP

DMI1RXN
DMI1RXP

DMI1TXN
DMI1TXP

DMI2RXN
DMI2RXP

DMI2TXN
DMI2TXP

DMI3RXN
DMI3RXP

DMI3TXN
DMI3TXP

DMI_CLKN
DMI_CLKP

DMI_ZCOMP

Direct Media Interface

DMI_IRCOMP

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N

USBP9P
USBP10N
USBP10P
USBP11N
USBP11P

2007/08/28 2006/03/10

GPIO21

AH23

HDDHALT_LED#

AF19

GPIO36

AE21

GPIO37

AD20

CLK_14M_ICH

H1

CLK_48M_ICH

AF3

ICH_SUSCLK

P1

SLP_S3#

C16

SLP_S4#

E16

SLP_S5#

G17

S4_STATE#

C10

PM_PWROK

G20

R348 0_0402_5%

M2

ICH_LOW_BAT#

B13

PWRBTN_OUT#

R3

D20

R_EC_RSMRST#

D22

CK_PWRGD

R5

M_PWROK

R6

B16

CL_CLK0

F24
B19

CL_DATA0

F22
C19

CL_VREF0_ICH

C25

CL_VREF1_ICH

A19

CL_RST#

F21
D18

XMIT_OFF

A16

GPIO10

C18

GPIO14

C11

LAN_WOL_EN

C20

DMI_RXN0

V27

DMI_RXP0

V26

DMI_TXN0

U29

DMI_TXP0

U28

DMI_RXN1

Y27

DMI_RXP1

Y26

DMI_TXN1

W29

DMI_TXP1

W28

DMI_RXN2

AB27

DMI_RXP2

AB26

DMI_TXN2

AA29

DMI_TXP2

AA28

DMI_RXN3

AD27

DMI_RXP3

AD26

DMI_TXN3

AC29

DMI_TXP3

AC28

CLK_PCIE_ICH#

T26

CLK_PCIE_ICH

T25

AF29

DMI_IRCOMP

AF28

USB20_N0

AC5

USB20_P0

AC4

USB20_N1

AD3

USB20_P1

AD2

USB20_N2

AC1

USB20_P2

AC2

USB20_N3

AA5

USB20_P3

AA4

USB20_N4

AB2

USB20_P4

AB3

USB20_N5

AA1

USB20_P5

AA2

USB20_N6

W5

USB20_P6

W4

USB20_N7

Y3

USB20_P7

Y2

USB20_N8

W1

USB20_P8

W2

USB20_N9

V2

USB20_P9

V3
U5
U4
U1
U2

Compal Secret Data

1 2

R370

100K_0402_5%

R382 24.9_0402_1%

Deciphered Date

2

HDDHALT_LED# 33

CLK_14M_ICH 17
CLK_48M_ICH 17

T58 PAD

SLP_S3# 29,32
SLP_S4# 32
SLP_S5# 32

PM_PWROK 9,32

PWRBTN_OUT# 32

R354 100_0402_5%
R355 10K_0402_5%

CK_PWRGD 17

M_PWROK 9,32

CL_CLK0 9

CL_DATA0 9

CL_RST# 9

XMIT_OFF 26

12

+3VALW

DMI_RXN0 9
DMI_RXP0 9
DMI_TXN0 9
DMI_TXP0 9

DMI_RXN1 9
DMI_RXP1 9
DMI_TXN1 9
DMI_TXP1 9

DMI_RXN2 9
DMI_RXP2 9
DMI_TXN2 9
DMI_TXP2 9

DMI_RXN3 9
DMI_RXP3 9
DMI_TXN3 9
DMI_TXP3 9

CLK_PCIE_ICH# 17
CLK_PCIE_ICH 17

1 2

USB20_N0 30
USB20_P0 30
USB20_N1 30
USB20_P1 30
USB20_N2 30
USB20_P2 30
USB20_N3 27
USB20_P3 27
USB20_N4 19
USB20_P4 19
USB20_N5 26
USB20_P5 26
USB20_N6 30
USB20_P6 30
USB20_N7 30
USB20_P7 30
USB20_N8 26
USB20_P8 26
USB20_N9 26
USB20_P9 26

2

1 2
1 2

R346 10K_040 2_5%

1 2

DPRSLPVR 9,42

R_EC_RSMRST# 38

Within 500 mils

+1.5VS

C442

C443

EC_RSMRST# 32

1

2

0.1U_0402_16V4Z

1

2

0.1U_0402_16V4Z

PM_PWROK R_EC_RSMRST#

2 1

CH751H-40PT_SOD323-2

USB-0 Right side(with ESATA)
USB-1 Left side
USB-2 Left side
USB-3 Cardreader
USB-4 Camera
USB-5 WLAN
USB-6 Bluetooth
USB-7 Finger Printer
USB-8

MiniCard(WWAN/WiMAX)

USB-9 Express card

Title

Size Document Number Rev

Custom

Montevina UMA

Date: Sheet of

1

Place closely pin
AF3

CLK_48M_ICH

12

R342

@

10_0402_5%

1

C440

@

4.7P_0402_50V8C

2

R360

1 2

12

3.24K_0402_1%

R363
453_0402_1%

NA lead free

R367

1 2

3.24K_0402_1%

12

R368
453_0402_1%

D22

Place closely pin
H1

+3VS

+3VALW

CLK_14M_ICH

12

R343

@

10_0402_5%

1

C441

@

4.7P_0402_50V8C

2

Compal Electronics, Inc.

ICH9(3/4)_DMI,USB,GPIO,PCIE

22 46Wednesday, February 18, 2009

1

0.1

5

+RTCVCC

20 mils

1

2

0.1U_0402_16V4Z

+1.5VS_SB_B

1

+

C459

2

10U_0805_10V4Z

220U_D2_4VM

1

C477

2

1U_0603_10V4Z

1

C483

2

1

C487

2

10U_0805_10V4Z

1

C454

2

0.1U_0402_16V4Z

1

2

10U_0805_10V4Z

+1.5VS

1

C488

2

2.2U_0603_6.3V4Z

C462

40 mils

R387

1 2

+5VS +3VS

R386

100_0402_5%

R388

10_0402_5%

+1.5VS

0316 change design

+1.5VS

12

+3VALW+5VALW

12

R389

1 2

CHB1608U301_0603

+3VS

C485

0.1U_0402_16V4Z

CHB1608U301_0603

21

D9

CH751H-40PT_SOD323-2

ICH_V5REF_RUN

20 mils

1

C465

0.1U_0402_10V6K

2

21

D10

CH751H-40PT_SOD323-2

ICH_V5REF_SUS

20 mils

1

C472

0.1U_0402_10V6K

2

C476

+1.5VS

0.1U_0402_16V4Z

1

R390 CH B1608U301_0603

1 2

+1.5VS

2

5

C458

1

2

D D

C C

B B

A A

ICH_V5REF_RUN

ICH_V5REF_SUS

10U_0805_10V4Z

1

C456

C460

2

2.2U_0603_6.3V4Z

+1.5VS

C478

1U_0603_10V4Z

+1.5VS

C481

1U_0603_10V4Z

C484

0.1U_0402_16V4Z

VCC_LAN1_05_INT_ICH_1

T69

VCC_LAN1_05_INT_ICH_2

T70

R391

1 2

+1.5VS

CHB1608U301_0603

0316 change design

1

2

1

2

1

2

1

2

C489

4.7U_0805_10V4Z

1

+3VS

2

4

U12F

A23

VCCRTC

A6

V5REF

AE1

V5REF_SUS

AA24

VCC1_5_B[01]

AA25

VCC1_5_B[02]

AB24

VCC1_5_B[03]

AB25

VCC1_5_B[04]

AC24

VCC1_5_B[05]

AC25

VCC1_5_B[06]

AD24

VCC1_5_B[07]

AD25

VCC1_5_B[08]

AE25

VCC1_5_B[09]

AE26

VCC1_5_B[10]

AE27

VCC1_5_B[11]

AE28

VCC1_5_B[12]

AE29

VCC1_5_B[13]

F25

VCC1_5_B[14]

G25

VCC1_5_B[15]

H24

VCC1_5_B[16]

H25

VCC1_5_B[17]

J24

VCC1_5_B[18]

J25

VCC1_5_B[19]

K24

VCC1_5_B[20]

K25

VCC1_5_B[21]

L23

VCC1_5_B[22]

L24

VCC1_5_B[23]

L25

VCC1_5_B[24]

M24

VCC1_5_B[25]

M25

VCC1_5_B[26]

N23

VCC1_5_B[27]

N24

VCC1_5_B[28]

N25

VCC1_5_B[29]

P24

VCC1_5_B[30]

P25

VCC1_5_B[31]

R24

VCC1_5_B[32]

R25

VCC1_5_B[33]

R26

VCC1_5_B[34]

R27

VCC1_5_B[35]

T24

VCC1_5_B[36]

T27

VCC1_5_B[37]

T28

VCC1_5_B[38]

T29

VCC1_5_B[39]

U24

VCC1_5_B[40]

U25

VCC1_5_B[41]

V24

VCC1_5_B[42]

V25

VCC1_5_B[43]

U23

VCC1_5_B[44]

W24

VCC1_5_B[45]

W25

VCC1_5_B[46]

K23

VCC1_5_B[47]

Y24

VCC1_5_B[48]

Y25

VCC1_5_B[49]

AJ19

VCCSATAPLL

AC16

VCC1_5_A[01]

AD15

VCC1_5_A[02]

AD16

VCC1_5_A[03]

AE15

VCC1_5_A[04]

AF15

VCC1_5_A[05]

AG15

VCC1_5_A[06]

AH15

VCC1_5_A[07]

AJ15

VCC1_5_A[08]

AC11

VCC1_5_A[09]

AD11

VCC1_5_A[10]

AE11

VCC1_5_A[11]

AF11

VCC1_5_A[12]

AG10

VCC1_5_A[13]

AG11

VCC1_5_A[14]

AH10

VCC1_5_A[15]

AJ10

VCC1_5_A[16]

AC9

VCC1_5_A[17]

AC18

VCC1_5_A[18]

AC19

VCC1_5_A[19]

AC21

VCC1_5_A[20]

G10

VCC1_5_A[21]

G9

VCC1_5_A[22]

11mA

AC12

VCC1_5_A[23]

AC13

VCC1_5_A[24]

AC14

VCC1_5_A[25]

AJ5

VCCUSBPLL

AA7

VCC1_5_A[26]

AB6

VCC1_5_A[27]

AB7

VCC1_5_A[28]

AC6

VCC1_5_A[29]

AC7

VCC1_5_A[30]

A10

VCCLAN1_05[1]

A11

VCCLAN1_05[2]

A12

VCCLAN3_3[1]

B12

VCCLAN3_3[2]

23mA

A27

VCCGLANPLL

80mA

D28

VCCGLAN1_5[1]

D29

VCCGLAN1_5[2]

E26

VCCGLAN1_5[3]

E27

VCCGLAN1_5[4]

1mA

A26

VCCGLAN3_3

ICH9-M ES_FCBGA676

4

11mA

G3: 6uA

2mA

2mA

646mA

47mA

1342mA

VCCA3GP

ARX

212mA

ATX

USB CORE

1634mA

VCCP_CORE

11mA

GLAN POWER

VCC1_05[01]
VCC1_05[02]
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]

CORE

VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC1_05[20]
VCC1_05[21]
VCC1_05[22]
VCC1_05[23]
VCC1_05[24]
VCC1_05[25]
VCC1_05[26]

VCCDMIPLL

23mA

V_CPU_IO[1]

48mA

V_CPU_IO[2]

2mA

308mA

PCI

11mA

VCCSUSHDA

VCCSUS1_05[1]
VCCSUS1_05[2]

VCCSUS1_5[1]

VCCSUS1_5[2]

VCCSUS3_3[01]
VCCSUS3_3[02]
VCCSUS3_3[03]
VCCSUS3_3[04]

VCCPSUS

VCCSUS3_3[05]

VCCSUS3_3[06]
VCCSUS3_3[07]
VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]

VCCPUSB

VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]

19/73/73mA19/78/78mA

VCCCL3_3[1]
VCCCL3_3[2]

VCC_DMI[1]
VCC_DMI[2]

VCC3_3[01]
VCC3_3[02]
VCC3_3[07]

VCC3_3[03]
VCC3_3[04]
VCC3_3[05]
VCC3_3[06]

VCC3_3[08]
VCC3_3[09]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]
VCC3_3[14]

VCCHDA

VCCCL1_05

VCCCL1_5

3

A15
B15
C15
D15
E15
F15
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

R29

W23
Y23

AB23
AC23

AG29
AJ6
AC10

AD19
AF20
AG24
AC20

B9
F9
G3
G6
J2
J7
K7

AJ4

AJ3

AC8
F17

AD8

F18

A18
D16
D17
E22

AF1

T1
T2
T3
T4
T5
T6
U6
U7
V6
V7
W6
W7
Y6
Y7
T7

G22
G23

A24
B24

+VCCP

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

VCCSUS1_5_ICH_1

VCCSUS1_5_ICH_2

0.1U_0402_16V4Z

VCCCL1_05_ICH

+3VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

0.1U_0402_16V4Z

1

1

C457

C455

2

2

1

C464

2

+3VS

0.1U_0402_16V4Z

1 2

12

0.1U_0402_16V4Z

R385

1 2

CHB1608U301_0603

1

C463

10U_0805_10V4Z

2

+VCCP

0.1U_0402_16V4Z

1

C470

2

R212

@

0_0402_5%

1 2

R741
150_0402_1%

Compal Secret Data

1

C471

2

R740
180_0402_1%

+1.5VALW

+1.5VS

+3VALW

Deciphered Date

0.01U_0402_16V7K

1

C461

2

22U_0805_6.3VAM

0.1U_0402_16V4Z

1

C469

2

+3VS

C473

1

C475

T65
T66

2

T67

T68

+3VALW

1

C479

2

+3VALW

1

2

T71

@

C486
1U_0603_10V4Z

+1.5VS

C480

C482

4.7U_0603_6.3V6M

1

2

1

2

1

2

2007/08/28 2006/03/10

+VCCP

4.7U_0603_6.3V6M

C466

1

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C467

1

2

(DMI)

0.1U_0402_16V4Z

2

C468

1

2

+1.5VS

1

C474

2

U12E

AA26

VSS[001]

AA27

VSS[002]

AA3

VSS[003]

AA6

VSS[004]

AB1

VSS[005]

AA23

VSS[006]

AB28

VSS[007]

AB29

VSS[008]

AB4

VSS[009]

AB5

VSS[010]

AC17

VSS[011]

AC26

VSS[012]

AC27

VSS[013]

AC3

VSS[014]

AD1

VSS[015]

AD10

VSS[016]

AD12

VSS[017]

AD13

VSS[018]

AD14

VSS[019]

AD17

VSS[020]

AD18

VSS[021]

AD21

VSS[022]

AD28

VSS[023]

AD29

VSS[024]

AD4

VSS[025]

AD5

VSS[026]

AD6

VSS[027]

AD7

VSS[028]

AD9

VSS[029]

AE12

VSS[030]

AE13

VSS[031]

AE14

VSS[032]

AE16

VSS[033]

AE17

VSS[034]

AE2

VSS[035]

AE20

VSS[036]

AE24

VSS[037]

AE3

VSS[038]

AE4

VSS[039]

AE6

VSS[040]

AE9

VSS[041]

AF13

VSS[042]

AF16

VSS[043]

AF18

VSS[044]

AF22

VSS[045]

AH26

VSS[046]

AF26

VSS[047]

AF27

VSS[048]

AF5

VSS[049]

AF7

VSS[050]

AF9

VSS[051]

AG13

VSS[052]

AG16

VSS[053]

AG18

VSS[054]

AG20

VSS[055]

AG23

VSS[056]

AG3

VSS[057]

AG6

VSS[058]

AG9

VSS[059]

AH12

VSS[060]

AH14

VSS[061]

AH17

VSS[062]

AH19

VSS[063]

AH2

VSS[064]

AH22

VSS[065]

AH25

VSS[066]

AH28

VSS[067]

AH5

VSS[068]

AH8

VSS[069]

AJ12

VSS[070]

AJ14

VSS[071]

AJ17

VSS[072]

AJ8

VSS[073]

B11

VSS[074]

B14

VSS[075]

B17

VSS[076]

B2

VSS[077]

B20

VSS[078]

B23

VSS[079]

B5

VSS[080]

B8

VSS[081]

C26

VSS[082]

C27

VSS[083]

E11

VSS[084]

E14

VSS[085]

E18

VSS[086]

E2

VSS[087]

E21

VSS[088]

E24

VSS[089]

E5

VSS[090]

E8

VSS[091]

F16

VSS[092]

F28

VSS[093]

F29

VSS[094]

G12

VSS[095]

G14

VSS[096]

G18

VSS[097]

G21

VSS[098]

G24

VSS[099]

G26

VSS[100]

G27

VSS[101]

G8

VSS[102]

H2

VSS[103]

H23

VSS[104]

H28

VSS[105]

H29

VSS[106]

ICH9-M ES_FCBGA676

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

ICH9(4/4)_POWER&GND

Montevina UMA

1

VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]

VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]
VSS_NCTF[05]
VSS_NCTF[06]
VSS_NCTF[07]
VSS_NCTF[08]
VSS_NCTF[09]
VSS_NCTF[10]
VSS_NCTF[11]
VSS_NCTF[12]

1

H5
J23
J26
J27
AC22
K28
K29
L13
L15
L2
L26
L27
L5
L7
M12
M13
M14
M15
M16
M17
M23
M28
M29
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
P12
P13
P14
P15
P16
P17
P2
P23
P28
P29
P4
P7
R11
R12
R13
R14
R15
R16
R17
R18
R28
T12
T13
T14
T15
T16
T17
T23
B26
U12
U13
U14
U15
U16
U17
AD23
U26
U27
U3
V1
V13
V15
V23
V28
V29
V4
V5
W26
W27
W3
Y1
Y28
Y29
Y4
Y5
AG28
AH6
AF2
B25

A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29

23 46Wednesday, February 18, 2009

0.1

5

4

3

2

1

1

C713

2

CLK_SMBDATA

R570

0_0402_5%

1 2

+3VS_ACL

1

C714

2

0.1U_0402_16V4Z

10U_0805_6.3V6M

CLK_SMBCLK 15,16,17

0011101b

CLK_SMBDATA 15,16,17

ACCEL_INT 20

Pleace near HDD CONN (JP3)

HDD Connector

CONN@

JHDD

D D

24

GND

23

GND

OCTEK_SAT-22EH1G_RV

C C

CD-ROM Connector

JODD

GND

GND

GND

MD
GND
GND

SUYIN_127382FR013GX09ZR

CONN@

A+

A-

B-

B+

DP
V5
V5

GND

GND

GND

GND
GND
GND

GND

Reserved

GND

13
12
11
10
9
8
7

6
5
4
3
2
1

A+

A-

B-

B+

V33
V33
V33

V5
V5
V5

V12
V12
V12

1
2
3
4
5
6

0.01U_0402_16V7K

7

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

0.01U_0402_16V7K

SATA_RXN4
SATA_RXP4

0.01U_0402_16V7K

0.01U_0402_16V7K

SATA_RXN0
SATA_RXP0

+3VS

+5VS

Near CONN side.

+5VS

C494

12

C495

12

Near CONN side.

SATA_TXP4
SATA_TXN4

SATA_RXN4_C

C510

12

SATA_RXP4_C

C511

12

SATA_TXP0
SATA_TXN0

SATA_RXN0_C

SATA_RXP0_C

SATA_RXN0_C 21

SATA_RXP0_C 21

SATA_TXP4 21

SATA_TXN4 21

SATA_RXN4_C 21
SATA_RXP4_C 21

SATA_TXP0 21

SATA_TXN0 21

+5VS

1

1

C491

C490

2

10U_0805_10V4Z

+5VS

C492

2

0.1U_0402_16V4Z

Placea caps. near ODD CONN.

1

1

C513

C512

2

0.1U_0402_16V4Z

C514

2

1U_0603_10V4Z

1

1

C493

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

1

C515

2

2

10U_0805_10V4Z

10U_0805_10V4Z

ACCELEROMETER (ST)

D23

2 1

CH751H-40PT_SOD323-2

VDDIO absolute man
rating is VDD+0.1

+3VS_ACL_IO

+3VS_ACL

+3VS_ACL+3VS +3VS_ACL_IO

1 2

U29

1

R568

0_0402_5%

1 2

Vdd_IO

2

GND

3

Reserved

4

GND

5

GND

6

Vdd

R569 10K_0402_5%

12

R564

0_0603_5%

14

SCL / SPC

CS

LIS302DLTR_LGA14_3x5

7

CLK_SMBCLK

SDA / SDI / SDO

SDO

Reserved

GND

INT 2

INT 1

13

12

11

10

9

8

B B

PA@

ZZZ

PCB-MB

A A

5

PR@

ZZZ

PCB-MB

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/03/10

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet of

Compal Electronics, Inc.

HDD & CDROM

Montevina UMA

1

24 46Wednesday, February 18, 2009

0.1

5

4

3

2

1

LAN_DI

LAN_CS

9/17 RT suggestion: R696 change to 1K ohm

Place Close to Chip

C240 0.1U_0402_16V7K

12

C241 0.1U_0402_16V7K

12

GLAN_TXP22

GLAN_TXN22

CLK_PCIE_LAN17

CLK_PCIE_LAN#17

CLKREQ#_917

PLT_RST#9,20,26

R688 2.49K_0402_1%

ICH_PCIE_WAKE#22,26

+LAN_VDD12

12

R215
1K_0402_1%

R216
15K_0402_5%

GLAN_RXP22

GLAN_RXN22

ISOLATEB

LAN_POWER_OFF32

D D

+3VS

C C

B B

Close to Pin10,13,30,36

PCIE_PTX_IRX_P2

PCIE_PTX_IRX_N2

1 2

ISOLATEB

LAN_X1
LAN_X2

1 2

R218 10K_040 2_5%

Close to Pin1,37,29

+3VALW

@

C255

0.1U_0402_16V4Z

20

21

15

16

17
18

25

27

46

26
28

41
42

23
24

7
14
31
47

22

U44

HSOP

HSON

HSIP

HSIN

REFCLK_P
REFCLK_M

CLKREQB

PERSTB

RSET

LANWAKEB
ISOLATEB

CKXTAL1
CKXTAL2

NC
NC

GND
GND
GND
GND

GNDTX

RTL8103EL-GR_LQFP48_7X7

2

1

RTL8102EL

S

D

13

G

2

Q19
SI2301BDS-T1-E3_SOT23-3

+3V_LAN

LED3/EEDO

LED2/EEDI/AUX

LED1/EESK

VCTRL12A

DVDD12
DVDD12
DVDD12
DVDD12

VCTRL12D

AVDD33

40 mils

+3V_LAN

EECS

LED0

MDIP0
MDIN0
MDIP1
MDIN1

VDDTX

VDD33
VDD33

NC
NC
NC
NC

NC

NC

NC

NC
NC

LAN_DO

33

LAN_DI

34

LAN_SK_LAN_LINK#

35

LAN_CS

32

LAN_ACTIVITY#

38

LAN_MDI0+

2

LAN_MDI0-

3

LAN_MDI1+

5

LAN_MDI1-

6
8
9
11
12

4

VCTRL12

48

19
30
36
13
10

39

44
45

+3V_LAN_IC

29
37

1
40
43

1 2

R695 3.6K_0402_5%

12

R696 1K_0402 _1%

T82

+EVDD12
+LAN_VDD12

R1177 0_0603_5%

1 2

R1162 0_0603_5%

+3V_LAN

C247 0.01U_0402_16V7K

1 2

C248 0.01U_0402_16V7K

1 2

3

1 2

+3V_LAN

2

@

D20

PACDN042_SOT23~D

1

LAN_ACTIVITY#

LANLED_ACT#

LANLED_LINK#

LAN_SK_LAN_LINK#

+LAN_VDD12

LAN_MDI0+
LAN_MDI0­LAN_CT0

LAN_CT1
LAN_MDI1+
LAN_MDI1-

1

C268

0.1U_0402_16V4Z

2

2

C269

0.1U_0402_16V4Z

1

U46

1

RD+

2

RD-

3

CT

4

NC

5

NC

6

CT

7

TD+
TD-8TX-

X'FORM_ HD-024A

R697
300_0402_5%

16

RX+

15

RX-

14

CT

13

NC

12

NC

11

CT

10

TX+

9

12

12

R698
300_0402_5%

RJ45_MIDI0+
RJ45_MIDI0­RJ45_CT0

RJ45_CT1
RJ45_MIDI1+
RJ45_MIDI1-

+3V_LAN

LANLED_ACT#

RJ45_MIDI1-

RJ45_MIDI1+

RJ45_MIDI0-

RJ45_MIDI0+

+3V_LAN

LANLED_LINK#

13

14

8

7

6

5

4

3

2

1

11

12

1

C271

0.1U_0402_16V4Z

2

C257 0.01U_0603_100V7-M

1 2

C258 0.01U_0603_100V7-M

1 2

LAN Conn.

JRJ45

Yellow LED+

Yellow LED-

PR4-

PR4+

PR2-

PR3-

PR3+

PR2+

PR1-

PR1+

Green LED+

Green LED-

FOX_JM36113-P1122-7F

CONN@

SHLD1

DETECT PIN1

DETCET PIN2

SHLD1

1

C272

4.7U_0805_10V4Z

2

16

9

10

15

RJ45_CT0_C
RJ45_CT1_C

LANGND

R693

75_0402_1%

1 2
1 2

R694

75_0402_1%

RJ45_GND

C259

1000P_1206_2KV7K

1

2

2

2

1

C264

2

C252

1

0.1U_0402_16V4Z

+LAN_VDD12

1

2

2

1

0.1U_0402_16V4Z

@

C265

10U_0805_10V4Z

C251

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

2

C249

C250

1

0.1U_0402_16V4Z

Close to Pin19 Close to Pin45

+EVDD12

2

C266

A A

2

C267

1

1

1U_0402_6.3V4Z

1U_0402_6.3V4Z

C253

1

0.1U_0402_16V4Z

Close to Pin48

VCTRL12

@

1

C262

2

9/17 RT suggestion: C267 change to 1uF

5

10U_0805_10V4Z

C254

C263

C261

1

1

2

1

4

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Y3

LAN_X1

25MHz_20pF_6X25000017

1

C244

2

0.1U_0402_16V4Z

27P_0402_50V8J

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2007/08/28

LAN_X2

12

1

27P_0402_50V8J

C245

2

Compal Secret Data

Deciphered Date

2

2007/06/30

Compal Electronics, Inc.

Title

RTL8102EL LAN

Size Document Number Rev

Montevina UMA 0.1

Custom

Wednesday, February 18, 2009

Date: Sheet of

25 46

1

2

2

A

B

C

D

E

+3VALW

1

C568

2

1 1

0.1U_0402_16V4Z

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C572

4.7U_0805_10V4Z

+3VS_WLAN

1

1

2

C566

C567

2

@

1

C1497

47P_0402_50V8J

2

R432

0_0805_5%

Reserve for WWAN

0.01U_0402_16V7K

12

+3VS +1.5VS

1

C569

2

0.1U_0402_16V4Z

+1.5VS_WLAN+3VALW

4.7U_0805_10V4Z

1

1

C570

2

2

SIM card Connector

CONN@

JSIM

1
2
3
4
5
6

ACES_87212-06G0

R750

@

1 2

47K_0402_5%

4.7U_0805_10V4Z

PA@

1

C574

2

0.1U_0402_16V4Z

1
2
3
4
5

G1

6

G2

7
8

+3VS_WWAN

1

2

UIM_VPP
UIM_RST
UIM_CLK
UIM_DATA
UIM_PWR

UIM_PWR UIM_DATA

2 2

0.01U_0402_16V7K

PA@

1

C573

2

PA@

C575

UIM_CLK

1

C824
18P_0402_50V8J

2

WWAN_POW ER_OFF32

@

+3VALW

R11 10K_04 02_5%

1 2

+3VS

R10 10K_0402_5%

1 2

+3VS

R400

@

1 2

0_0603_5%

S

D

13

G

@

2

SI2301BDS-T1-E3_SOT23-3

Q52

+3VS_WWAN

@

1

C1499

47P_0402_50V8J

2

CLKREQ#_6

CLKREQ#_10

Reserve for WWAN

R431

12

0_0805_5%

1

@

C571

C1498
47P_0402_50V8J

2

SI-1 Connect PLT_RST# to JP7.A17

PCIE_RXN322
PCIE_RXP322

+3VS

R418

1 2

0_1206_5%

CLKREQ#_617

CLK_PCIE_MCARD2#17
CLK_PCIE_MCARD217

CLK_DEBUG_PORT_117

CLK_PCIE_MCARD0#17
CLK_PCIE_MCARD017

PCIE_RXN122
PCIE_RXP122

Reserve for WWAN

CH_DATA30

CH_CLK30

R423 0_0402_5%

1 2

R425 0_0402_5%

1 2

PCIE_TXN322

PCIE_TXP322

CLKREQ#_1017

R419

R421 0_0402_5%

PA@

PCIE_TXN122

PCIE_TXP122

+3VS_WWAN

Mini Card Slot ---WLAN,WWAN

ICH_PCIE_WAKE#
CH_DATA
CH_CLK
CLKREQ#_6

CLK_PCIE_MCARD2#
CLK_PCIE_MCARD2

PLT_RST#

PCIE_TXN3
PCIE_TXP3

+3VS_WLAN

ICH_PCIE_WAKE#
CH_DATA
CH_CLK
CLKREQ#_10

1 2
1 2

PCIE_TXN1
PCIE_TXP1

PCIE_C_RXN3
PCIE_C_RXP3

0_0402_5%PA@

PCIE_C_RXN1
PCIE_C_RXP1

JMINIA

A1

WAKE#

A3

COEX1

A5

COEX2

A7

CLKREQ#

A9

GND

A11

REFCLK-

A13

REFCLK+

A15

GND

A17

Reserved

A19

Reserved

A21

GND

A23

PERn0

A25

PERp0

A27

GND

A29

GND

A31

PETn0

A33

PETp0

A35

GND

A37

GND

A39

+3.3Vaux

A41

+3.3Vaux

A43

GND

A45

Reserved

A47

Reserved

A49

Reserved

A51

Reserved

A53

GND

QUASA_CA0416-092N21

JMINIB

B1

WAKE#

B3

COEX1

B5

COEX1

B7

CLKREQ#

GND

B11

REFCLK-

B13

REFCLK+

GND

B17

Reserved

B19

Reserved

GND

B23

PERn0

B25

PERp0

GND
GND

B31

PETn0

B33

PETp0

GND

B37

GND

B39

+3.3Vaux

B41

+3.3Vaux

B43

GND

B45

Reserved

B47

Reserved

B49

Reserved

B51

Reserved

QUASA_CA0416-092N21

+3.3Vaux

GND

+1.5V

UIM_PWR

UIM_DATA

UIM_CLK

UIM_RESET

UIM_VPP

GND

W_DISABLE#

PERST#

+3.3Vaux

+1.5V

SMB_CLK

SMB_DATA

USB_D-

USB_D+

LED_WWAN #

LED_WLAN#
LED_WPAN#

+1.5V

+3.3Vaux

+3.3Vaux

+1.5V

UIM_PWR

UIM_DATA

UIM_CLK

UIM_RESET

UIM_VPP

W_DISABLE#

PERST#

+3.3Vaux

+1.5V

SMB_CLK

SMB_DATA

USB_D-

USB_D+

LED_WWAN #

LED_WLAN#
LED_WPAN#

+1.5V

+3.3Vaux

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

A2

A6
A8
A10
A12
A14
A16

A20
A22
A24

A28
A30
A32

A36
A38

A42
A44
A46
A48

A52

A54

B2
B4
B6
B8
B10
B12
B14
B16
B18
B20
B22
B24
B26
B28
B30
B32
B34
B36
B38
B40
B42
B44
B46
B48
B50
B52

+3VS_WLAN

+1.5VS_WLAN

XMIT_OFF#

2 1

PLT_RST#

R424 0_0805_5%@

1 2

R426 0_0805_5%

1 2

ICH_SMBCLK
ICH_SMBDATA

+1.5VS_WLAN

+3VS_WLAN

+3VS_WWAN

+1.5VS_WLAN

UIM_PWR_R
UIM_DATA_R
UIM_CLK_R
UIM_RST_R
UIM_VPP_R

M_WXMIT_OFF#
PLT_RST#

R420 0_0805_5%@
R422 0_0805_5%

ICH_SMBCLK
ICH_SMBDATA

WW_LED#_R

+1.5VS_WLAN

+3VS_WWAN

D19 CH751H-40P T_SOD323-2

USB20_N5 22
USB20_P5 22

WL_LED# 33

D11 CH 751H-40PT_SOD323-2PA@

2 1

1 2
1 2

+1.5VS_WLAN

LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

+3VALW
+3VS_WLAN
+1.5VS_WLAN

UIM_PWR_R
UIM_DATA_R
UIM_CLK_R
UIM_RST_R
UIM_VPP_R

UIM_PWR_R
UIM_DATA_R
UIM_CLK_R
UIM_RST_R
UIM_VPP_R

USB20_N8 22
USB20_P8 22

WW_LED# 33

LPC_FRAME# 21,32
LPC_AD3 21,32
LPC_AD2 21,32
LPC_AD1 21,32
LPC_AD0 21,32

XMIT_OFF 22

SI-1 For PR

WL_LED# WW _LED#_R

1 2

R1225 0_0402_5%PR@

XMIT_OFF# M_WXMIT_OFF#

1 2

R1226 0_0402_5%PR@

1 2

R1227 0_0402_5%

1 2

R1228 0_0402_5%

1 2

R1229 0_0402_5%

1 2

R1230 0_0402_5%

1 2

R1231 0_0402_5%

1 2

R1232 0_0402_5%

1 2

R1233 0_0402_5%

1 2

R1234 0_0402_5%

1 2

R1235 0_0402_5%

1 2

R1236 0_0402_5%

WXMIT_OFF# 22

+3VALW
+3VS_WWAN

LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

UIM_PWR
UIM_DATA
UIM_CLK
UIM_RST
UIM_VPP

PR@
PR@
PR@
PR@
PR@

PA@
PA@
PA@
PA@
PA@

CONN@

3 3

C576

1 2

C579 0.1U_0402_16V4Z

1 2

C580 0.1U_0402_16V4Z

+3VALW

PLT_RST#9,20,25

SYSON32,35,40

SUSP#32,35,37,39

+3VALW

EXP_CPPE#22

4 4

internal pull high to 3.3Vaux-in
EC need setting at Hi-Z & output Low

A

1 2

PLT_RST#

SYSON

SUSP#

R439 100K_0402_5%@

EXP_CPPE#

1 2

0.1U_0402_16V4Z

New Card

Express Card Power Switch

+1.5VS

U16

12

+3VS

1.5Vin

14

1.5Vin

2

3.3Vin

4

3.3Vin

AUX_IN17AUX_OUT

6

SYSRST#

20

SHDN#

1

STBY#

10

CPPE#

9

CPUSB#

18

RCLKEN

ENE P2231NL E2 QFN 20P

B

1.5Vout

1.5Vout

3.3Vout

3.3Vout

OC#

PERST#

GND

R436 0_0402_5%

USB20_N922

USB20_P922

11
13

3
5

15

19

8

16

NC

7

+1.5VS_PEC

+3VS_PEC

+3V_PEC

PERST#

ICH_SMBCLK17,22

ICH_SMBDATA17,22

ICH_PCIE_WAKE#22,25

CLKREQ#_417

CLK_PCIE_NCARD#17
CLK_PCIE_NCARD17

PCIE_RXN422

PCIE_RXP422

PCIE_TXN422
PCIE_TXP422

1 2

R437 0_0402_5%

1 2

R438

1 2

0_0402_5%

+1.5VS_PEC
+1.5VS_PEC

+3V_PEC

+3VS_PEC

USB9­USB9+
EXP_CPPE#

ICH_SMBCLK
ICH_SMBDATA

PCIE_PME#_R

PERST#

CLKREQ#_4
EXP_CPPE#

Close to

R12

10K_0402_5%

Issued Date

CLKREQ#_4

C

2007/08/28 2006/07/26

Compal Secret Data

Deciphered Date

1 2

+3VS

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

JEXP

D

JEXP

1

GND

2

USB_D-

3

USB_D+

4

CPUSB#

5

RSV

6

RSV

7

SMB_CLK

8

SMB_DATA

9

+1.5V

10

+1.5V

11

WAKE#

12

+3.3VAUX

13

PERST#

14

+3.3V

15

+3.3V

16

CLKREQ#

17

CPPE#

18

REFCLK-

19

REFCLK+

20

GND

21

PERn0

22

PERp0

23

GND

24

PETn0

25

PETp0

26

GND

27

GND

28

GND

SANTA_130801-5_RT

Title

Size Document Number Rev

Date: Sheet of

Near to Express Card slot.

+3VS_PEC

1

1

C577

0.1U_0402_16V4Z

C581

0.1U_0402_16V4Z

C583

0.1U_0402_16V4Z

+1.5VS_PEC

+3V_PEC

2

2

1

1

2

2

1

1

2

2

Compal Electronics, Inc.

WLAN, WWAN, New Card

Montevina UMA

26 46Wednesday, February 18, 2009

E

C578

4.7U_0805_10V4Z

C582

4.7U_0805_10V4Z

C584

4.7U_0805_10V4Z

0.1

5

4

3

2

1

D D

C C

R1107

1 2

+5VS

1.2K_0402_5%

B B

+3VS

R1102

100K_0402_5%

1 2

1

C1405

1U_0402_6.3V6K

2

+3VS

C1410

4.7U_0603_6.3V6K

1

2

0.1U_0402_16V4Z

SI-1 Change LED type

PA@

D54

2 1

HT-110TW_WHITE

White

D64

2 1

HT-110TW_WHITE

PR@

R1103 0_0402_5%

R1105
499K_0402_1%~D

@

1 2

C1411

1

2

RST#

12

C1406

1U_0603_16V6K

R1115

0_0402_5%

CLK_48M_CR17

1 2

C1415

@

6P_0402_50V8J

SI-1 Delete Crystall layout location

CR_LED#

C1412

@

47P_0402_50V8J

+3VS

1

2

1

2

0.1U_0402_16V4Z

1

C1407

2

0.1U_0402_16V4Z

2

USB20_N322

USB20_P322

1

MODE SEL

@

10K_0402_5%

1 2

+VCC_4IN1

R1110

1

2

1

2

C1403

0.1U_0402_16V4Z

C1408

6.19K_0402_1%

RST#
MODE SEL

XTLI

USB20_N3
USB20_P3
CR_LED#

R1111

0.1U_0402_16V4Z
C1404

1 2

U47

1

AV_PLL

3

NC

7

NC

9

CARD_3V3

11

D3V3

33

D3V3

8

3V3_IN

44

RST#

45

MODE_SEL

47

XTLO

48

XTLI

4

DM

5

DP

14

GPIO0

12

2

RREF

12

DGND

32

DGND

6

AGND

46

AGND

RTS5159E-GR_LQFP48_7X7

1 2

R1104 0_0402_5%

SD_DAT2/XD_RE#_SP16

SD_DAT3/XD_WE#_SP15

SD_DAT4/XD_WP#/MS_D7_SP13

SD_DAT5/XD_D0/MS_D6_SP12

SD_CLK/XD_D1/MS_CLK_SP11

SD_DAT6/XD_D7/MS_D3_SP10

SD_DAT7/XD_D2/MS_D2_SP8
SD_DAT0/XD_D6/MS_D0_SP7
SD_DAT1/XD_D3/MS_D1_SP6

XD_D4/SD_DAT1_SP4

R1113
10_0402_5%@

10P_0402_50V8J

C1413

@

VREG

MS_D4

XD_CLE_SP19
XD_CE#_SP18

XD_ALE_SP17

XD_RDY_SP14

MS_INS#_SP9

XD_D5_SP5

SD_CD#_SP3
SD_WP_SP2
XD_CD#_SP1

EEDI

XTAL_CTR

MS_D5

EEDO
EECS

EESK

SD_CMD

MSCLK

NC

12

10
22
30

43
42
41
40
39
38
37
35
34
31
29
28
27
26
25
23
21
20
19
18

13
24

15
16
17
36

1

2

C1409
1U_0603_10V4Z

1 2

XD_CLE
XDCE#
XD_ALE
XD_RE#_SDD2
XDWE#_SDD3
XDRDY
XDWP#_SDD4
XDD0_SDD5
XDD1

XDD7_SDD6_MSD3

MSINS#

XDD2_SDD7_MSD2
XDD6_SDD0_MSD0

XDD3_MSD1
XDD5_MSBS
XDD4_SDD1
SDCD#
SDWP
XDCD#

R1112 0_0402_5%

1 2

SDCMD

SDCLK

R1114
10_0402_5%@

10P_0402_50V8J

C1414

@

+3VS

12

1

2

1 2

1 2

MSCLK

R11060_0402_5%

SDCLK

R11090_0402_5%

Card Reader Connector

CONN@

JREAD1

+VCC_4IN1 +VCC_4IN1

XDD0_SDD5
XDD1
XDD2_SDD7_MSD2
XDD3_MSD1
XDD4_SDD1
XDD5_MSBS
XDD6_SDD0_MSD0
XDD7_SDD6_MSD3

XDWE#_SDD3
XDWP#_SDD4
XD_ALE
XDCD#
XDRDY
XD_RE#_SDD2
XDCE#
XD_CLE

3

XD-VCC

32

XD-D0

10

XD-D1

9

XD-D2

8

XD-D3

7

XD-D4

6

XD-D5

5

XD-D6

4

XD-D7

34

XD-WE

33

XD-WP

35

XD-ALE

40

XD-CD

39

XD-R/B

38

XD-RE

37

XD-CE

36

XD-CLE

11

7IN1 GND

31

7IN1 GND

41

7IN1 GND

42

7IN1 GND

TAITW_R015-B10-LM

7 IN 1 CONN

SD-VCC

MS-VCC

SD_CLK
SD-DAT0
SD-DAT1
SD-DAT2
SD-DAT3
SD-DAT4
SD-DAT5
SD-DAT6
SD-DAT7

SD-CMD

SD-CD-SW

SD-WP-SW

MS-SCLK
MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3

MS-INS

MS-BS

21
28

SDCLK

20

XDD6_SDD0_MSD0

14

XDD4_SDD1

12

XD_RE#_SDD2

30

XDWE#_SDD3

29

XDWP#_SDD4

27

XDD0_SDD5

23

XDD7_SDD6_MSD3

18

XDD2_SDD7_MSD2

16

SDCMD

25

SDCD#

1

SDWP

2

MSCLK

26

XDD6_SDD0_MSD0

17

XDD3_MSD1

15

XDD2_SDD7_MSD2

19

XDD7_SDD6_MSD3

24

MSINS#

22

XDD5_MSBS

13

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/10/06

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

USB CardReader&CONN

Montevina UMA

1

27 46Wednesday, February 18, 2009

0.1

A

B

C

D

E

1 1

R1123

BLM18BD601SN1D_0603

+3VS

PV-1 ESD request

+1.5VS

2 2

3 3

4 4

12

R1239

4.7K_0402_5%

HDA_RST#_CODEC

1

C1516

2

0.01U_0402_16V7K

HDA_BITCLK_CODEC21

HDA_SDIN021

HDA_SDOUT_CODEC21

HDA_SYNC_CODEC21

HDA_RST#_CODEC21,32

SI-1 For EMI request

DMIC_CLK19

DMIC_DAT19

EAPD_CODEC32

C1478

1 2

1000P_0402_50V7K

C1479

1 2

1000P_0402_50V7K

C1480

1 2

1000P_0402_50V7K

C1481

1 2

1000P_0402_50V7K

R1174

1 2

R1175

1 2

R1176

1 2

+3VS_HDA

12

33_0402_5%

R1130

1 2

R1132 22_0603_1%

1 2
1 2

R1178 0_0603_5%

0_0402_5%

0_1206_5%

0_1206_5%

GNDAGND

C1425

C1424

0.1U_0402_16V7K

1

1

2

2

HDA_BITCLK_CODEC

HDA_SDIN0_CODEC

HDA_SDOUT_CODEC

HDA_SYNC_CODEC

HDA_RST#_CODEC

EAPD_CODEC

GNDA 29

1U_0603_10V4Z

CODEC POWER

SI-1 Delete CODEC POWER IC

C1426

10U_0805_10V4Z

2

1

U49

1

DVDD_LV

6

DVDD_CORE

3

HDA_BITCLK

5

HDA_SDI

2

HDA_SDO

7

HDA_SYNC

8

HDA_RST#

30

DMIC_CLK

29

DMIC0/GPIO1

32

SPDIF_OUT_0

28

SPDIF_OUT_1/GPIO7

31

EAPD/GPIO0/SPDIF_OUT 0 or 1

4

DVSS

92HD75B1X5NLGXYAX8 QFN 32P 1.5V CODEC

AVDD

SENSE_A
SENSE_B

PORT_A_L

PORT_A_R

PORT_B_L

PORT_B_R

VREFOUT_B

PORT_C_L

PORT_C_R

VREFOUT_C

PORT_D_L

PORT_D_R

PORT_E_L

PORT_E_R

PC_BEEP/MONO

CAP2

VREFFILT

AVSS
TPAD

+VDDA_CODEC

300mA(4.75V(4.56~4.94V))

R1122
0_0603_5%

+VDDA_CODEC_R

1 2

C1423

C1422

1U_0603_10V4Z

2

1

0.1U_0402_16V7K

1

2

17

10

R1128 100K_0402_5%

23

C1428 1000P_0402_50V7K@

26
27

MIC_EXTL

13

MIC_EXTR

14

VREFOUT_B

20

MIC_INL

15

MIC_INR

16

VREFOUT_C

21

24
25

11
12

MONO_INR M ONO_IN

9

22
19

C1436

18
33

1

2

1 2

2

1

10U_0805_10V4Z

C1437

1U_0603_10V4Z

SENSEA

12

C1430

1 2
1 2

C1431

HP_IN_L
HP_IN_R

LINE_OUT_L
LINE_OUT_R

12

C14340.1U_0402_16V7K

C1435

+VDDA_CODEC_R

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

0.1U_0402_16V7K

2

1

VREFOUT_B

10K_0402_5%

R1135

1 2

HP_IN_L 29
HP_IN_R 29

MIC_EXT_L
MIC_EXT_R

LINE_OUT_L 29

LINE_OUT_R 29

R1133 47K_0402_5%

R1116

0_0402_5%

4.7K_0402_5%

MIC_EXT_R

MIC_EXT_L

R1124 2.49K_0402_1%
R1125 39.2K_0402_1%
R1126 20K_0402_1%

C1429 1000P_0402_50V7K

12

12

R1118

1 2
1 2
1 2

1 2

C1418

12

1U_0603_10V4Z

R1119

4.7K_0402_5%

1 2

+VDDA_CODEC_R

VREFOUT_C

HP_DET# 29
EXTMIC_DET# 29

R1117

1K_0402_5%

4.7K_0402_5%

MIC_IN_R

MIC_IN_L

HP Jack

MIC_EXT_L 29
MIC_EXT_R 29 MIC_IN_L 29

Jack MIC

C1432 2.2U_0603_6.3V6K

1 2

MIC_IN_L

Internal MIC

Internal SPKR.

12

0.1U_0402_16V7K

SB_SPKR22

C1433 2.2U_0603_6.3V6K

R1134 10K_0402_5%

12

C1459

61

2

12

+VDDA_CODEC

Q10A
2N7002DW-7-F_SOT363-6

Q10B

5

MIC_IN_R

1 2

090212 For PC Beep Noise

12

R1120

MIC_IN_R 29

3

4

2N7002DW-7-F_SOT363-6

12

C1419

12

1U_0603_10V4Z

R1121

4.7K_0402_5%

1 2

PV-1 For EMI

3

MIC_EXTL

MIC_EXTR

2

D58
PSOT24C_SOT23-3

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2007/08/28 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet of

Codec_IDT9275B

Montevina UMA

28 46Wednesday, February 18, 2009

E

0.1

A

B

C

D

E

SPKR-

R1136 0_0603_5%

1 2

R1137 0_0603_5%

1 2

R1138 0_0603_5%

1 2

R1139 0_0603_5%

1 2

EC_MUTE# 32

SPKR+
SPKL­SPKL+

AMP. FOR INTERNAL SPEAKER

1 1

2 2

3 3

GAIN1 GAIN0 Av(inv)

0

0

1

1

LINE_OUT_R28

LINE_OUT_L28

0

1

0

1

C1448 0.47U_0402_6.3V6K

12

C1451 0.47U_0402_6.3V6K

12

10dB

12dB

15.6dB

V

21.6dB

R1148 0_0402_5%

C1450 0.47U_0402_6.3V6K

R1150 0_0402_5%

C1452 0.47U_0402_6.3V6K

+5VS

R1152
0_0805_5%

12

12

12

12

12

1

2

+5VS

1 2

R1141 100K_0402_5%@

1 2

R1142 100K_0402_5%

R1143 0_0402_5%@

R1145 0_0402_5%

LINE_R_OUTRLINE_C_OUTR

LINE_L_OUTRLINE_C_OUTL

SPKL+

SPKL-

C14571U_0603_10V4Z

C145610U_0805_10V4Z

1

2

GAIN1

1 2

GAIN0

1 2

2

SPKR_RIN+

1

SPKR_RIN-

3

SPKR_LIN+

4

SPKR_LIN-

5

SPGND

6

LOUT+

7

LOUT-

8

SPVDD

1 2

C1461 1U_0603_10V4Z

33

TML

GAIN1

GAIN0

32

GAIN031GAIN1

CPVDD

C1P

9

10

1 2

C1458
1U_0603_10V4Z

R1140
0_0805_5%

12

1 2

C1442 1U_0603 _10V4Z

30

VDD

CPGND

11

R1144

1 2

0_0603_5%

+VDDA_CODEC_IC

HP_INL

HP_INR

26

27

28

29

SGND

HP_INL

REG_OUT

C1N

HPVSS

CPVSS

12

14

15

13

+5VS

+VDDA_CODEC

TPA6047 LDO OUTPUT 4.7V

Close to Pin29

C1443 10U_0805_10V 4Z

1 2

C1444 1U_0603_10V 4Z

1 2

C1445 0.1U_0402_16V7K

1 2

1 2

C1446 2.2U_0805_10V6K

1 2

C1447 2.2U_0805_10V6K

R1147

@

1 2

REG_EN

BYPASS

SPKR_EN#

HP_EN

SPGND

ROUT+

ROUT-

SPVDD

HPVDD

HP_OUTL

100K_0402_5%

U50
TPA6047A4RHBR QFN 32P

C1449 1U_0603_10V4Z

24

23

22

21

SPKR+

20

SPKR-

19

18

17

HP_OUTL

HP_OUTR

25

HP_INR

HP_OUTR

16

1 2

1

C14541U_060 3_10V4Z

2

HP_IN_L
HP_IN_R

1

C145510U_0805_1 0V4Z

2

100K_0402_5%

C1453 0.1U_0402_16V4Z@

R1153
0_0805_5%

HP_IN_L 28
HP_IN_R 28

SLP_S3# 22,32

R1151

1 2

1 2

12

+3VS

+5VS

SPK_R­SPK_R+
SPK_L­SPK_L+

1

C1438

2

330P_0402_50V7K

D55

PSOT24C_SOT23-3

SPK_L­SPK_L+

SI-1 Add JSPK2 for PA

MIC_IN_L28

MIC_IN_R28

1

C1440

2

330P_0402_50V7K

1

C1441

2

330P_0402_50V7K

3

D56

2

1

C1439

330P_0402_50V7K

2

3

PSOT24C_SOT23-3

1

MV-1 For ESD request, close to JMIC2

1

D57

PSOT24C_SOT23-3

12

R1211
0_0402_5%

2

JSPK1

1

1

2

2

3

3

4

4

5

1

GND1

6

GND2

E&T_3806-F04N-02R

2

CONN@

9/20 SP02000CW0 0

CONN@

JSPK2

1

1

2

2

3

GND

4

GND

ACES_88231-02001

INTMIC IN

3

CONN@

JMIC2

1

1

2

2

3

GND

4

GND

ACES_88231-02001

SPEAKER

SI-1 Add Audio board connector

Audio connector

MIC_EXT_R28
MIC_EXT_L28

SI-1 Change IR1 to SCR00000E00

+5VL

12

4 4

CIR_IN32

CIR_IN

C1466

4.7U_0805_10V4Z

R1158
100_0805_5%

A

Consumer IR

IR1

1

Vout

2

VCC

3

GND

4

GND

IRM-V536/TR1_3P

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2007/08/28 2006/07/26

Compal Secret Data

Deciphered Date

EXTMIC_DET#28

HP_DET#28

D

MIC_EXT_R
MIC_EXT_L

HP_OUTL
HP_OUTR

EXTMIC_DET#
HP_DET#

Title

Size Document Number Rev

Custom

Date: Sheet of

JAUDIO

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

GND1

12

GND2

ACES_87213-1000G

CONN@

AMP & Audio Jack

Montevina UMA

E

29 46Wednesday, February 18, 2009

0.1

5

4

3

2

1

Right side USB Power Switch Right side ESATA/USB combination Connector

+5VALW

U41

1

GND

2

D D

C1381

4.7U_0805_10V4Z

C C

USB_EN#

1

2

IN

3

IN

4

EN#

TPS2061IDGNR_MSOP8

OUT
OUT
OUT
OC#

8

W=100mils

7
6
5

1

+

C1380

2

150U_B_6.3VM_R40M

R1083 10K_0402_5%

1

C1382

2

0.1U_0402_16V4Z

1 2

USB_VCCC

1

C1383

2

1000P_0402_50V7K

+5VALW

+5VALW

USB20_P0_R

USB20_N02 2
USB20_P022

SATA_TXP521
SATA_TXN521

SATA_RXN5_C21
SATA_RXP5_C21

@

D45

4

VIN

3

IO2

PRTR5V0U2X_SOT143-4

R1080 0_0402_5%
R1081 0_0402_5%

C1385 0.01U_0402_16V7K
C1384 0.01U_0402_16V7K

USB20_N0_R

2

IO1

1

GND

1 2
1 2

12
12

USB_VCCC

USB20_N0_R
USB20_P0_R

SATA_TXP5
SATA_TXN5

SATA_RXN5
SATA_RXP5

+5VALW

SATA_TXN5

JESAT

USB

1

VBUS

2

D-

3

D+

4

GND

5

GND

6

A+

ESATA

7

A-

8

GND

9

B-

10

B+

11

GND

12

GND

13

GND

14

GND

15

GND

TYCO_1759576-1

CONN@

@

D46

4

3

PRTR5V0U2X_SOT143-4

2

IO1

VIN

1

GND

IO2

SATA_TXP5

Finger printer

+3VS

R628
0_0805_5%

1 2

+3VS_FP

1

C756 0.1U_0402_1 6V4Z

B B

2

+5VALW

USB20_N722
USB20_P722

USB20_N7_R

R634 0_0402_5%
R635 0_0402_5%

D30

4

3

2

IO1

VIN

1

GND

IO2

PRTR5V0U2X_SOT143-4

1 2
1 2

USB20_P7_R

USB20_N7_R
USB20_P7_R

CONN@

JFPR

1

1

2

2

3

3

4

4

5

GND

6

GND

P-TWO_161011-04021

USB cable connector for Right side

JUSB

+5VALW

USB_EN#32

USB20_N222
USB20_P222

USB20_N122
USB20_P122

A A

USB_EN#

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

GND1

12

GND2

ACES_87213-1000G

CONN@

BT Connector

JBT

8

10

8

GND

7

7

USB20_P6_R

6

6

USB20_N6_R

5

5

4

4

3

3

2

2

1

9

1

GND

ACES_87213-0800G

CONN@

+3VS

R235

1 2

+3VALW +3VAUX_BT

0_0603_5%

R236

@

1 2

0_0603_5%

1

C1386

@

1U_0603_10V4Z

2

R1092 10K_0402_5%

BT_OFF22

1 2

R1084 0_0402_5%
R1085 0_0402_5%

R1086 1K_0402_5%@

1 2

R1087 1K_0402_5%@

1 2

12

R1090
100K_0402_5%

12
12

+5VALW

USB20_N6_R

Q105 SI2301BDS-T1-E3_SOT23-3

S

D

13

G

2

1

C1387

2

0.01U_0402_16V7K

C1390

1 2

0.1U_0402_16V4Z

+3VAUX_BT

@

4

3

PRTR5V0U2X_SOT143-4

0.1U_0402_16V4Z

1

C1388

2

4.7U_0805_10V4Z

USB20_P6 22
USB20_N6 22
BT_LED 33
CH_DATA 26

CH_CLK 26

D47

VIN

GND

IO2

1

2

IO1

C1389

2

1

USB20_P6_R

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet of

Compal Electronics, Inc.

USB, BT, eSATA

Montevina UMA

30 46Wednesday, February 18, 2009

1

0.1

5

4

3

2

1

D D

0.1U_0402_16V4Z

FSEL#32

SPI_CLK32

R230

SPI_FSEL#

33_0402_5%

R231

SPI_CLK_R

33_0402_5%

R232

C C

SPI_FWR#

33_0402_5%

12

12

12

C307

12

22P_0402_50V8J

C308

12

22P_0402_50V8J

C309

12

22P_0402_50V8J

+3VL

20mils

1

C712

2

1 2

R553 10_0402_5%

1 2

R554 10_0402_5%

1 2

R556 10_0402_5%

SP07000F500 S SOCKET WIESON G6179-100000 8P SPIFLASH
WIESO_G6179-100000_8P

SPI_FSEL#

SPI_CLK_R

SPI ROM

U27

8

VCC

VSS

3

W

7

HOLD

1

S

6

C

5

D

WIESON G6179 8P SPI

4

SPI_SOSPI_FWR#

2

Q

1 2

R555 0_0402_5%

FRD#

FRD# 32FWR#32

EMI request

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet of

Compal Electronics, Inc.

BIOS ROM

Montevina UMA

1

31 46Wednesday, February 18, 2009

0.1

+3VL_EC

1

C715

2

0.1U_0402_16V4Z

SMB_EC_DA1
SMB_EC_CK1
SMB_EC_DA2
SMB_EC_CK2

SYSON

R213

8.2K_0402_5%

1 2

PCI_PME#20

WL_BLUE_BTN33

EC_PME# PCI_RST#

1

C324

0.1U_0402_16V4Z

2

EMI request

LAN_POWER_OFF25

0.1U_0402_16V4Z

1

1

C716

2

+3VL

12

C717

2

1000P_0402_50V7K

R573 4.7K_0402_5%

1 2

R577 4.7K_0402_5%

1 2

R574 4.7K_0402_5%

1 2

R575 4.7K_0402_5%

1 2

CLK_PCI_EC17

1 2

R578 47K_0402_5%

C721 0.1U_0402_16V4Z

SUSP#

R581

8.2K_0402_5%

1

C325

0.1U_0402_16V4Z

2

EC DEBUG port

UTX

R233

@

1 2

0_0402_5%

0.1U_0402_16V4Z

1

2

12

PCI_RST#

12

R713
100K_0402_5%

R589

@

1 2

0_0402_5%

R190

1 2

12

0_0805_5%

R443

1000P_0402_50V7K

1

C719

C718

2

C722

@

1 2

15P_0402_50V8J

12

J1

JOPEN

+3VALW

12

R124

@

10K_0402_5%

+3VALW

12

R191
10K_0402_5%

0_0402_5%OPP@

ON/OFFBTN33

LAN_POWER_OFF_R

ESB_CLK33

ESB_DAT33

+3VL +3VS

R576

@

1 2

33_0402_5%

EC_SCI#22

+3VL

EC_PME#

+3VL

32.768KHZ_12.5PF_9H03200413

4.7K_0402_5%

12

R583
10K_0402_5%

LID_SW#

WWAN_POW ER_OFF26

R593

R1100

HDA_RST#_EC

+3VS

TSATN#9

FAN_SPEED6

1 2

4.7K_0402_5%

C723
15P_0402_50V8J

1 2

3

NC

2

NC

1 2

C725
15P_0402_50V8J

+3VL +3VL

12

12

Y5

GATEA2021
KB_RST#21
SIRQ22

LPC_FRAME#21,26

LPC_AD321,26
LPC_AD221,26
LPC_AD121,26
LPC_AD021,26

PCI_RST#20

R403 0_0402_5%

1 2

R721
10K_0402_5%

TP_BTN#

SMB_EC_CK133 ,36
SMB_EC_DA133 ,36
SMB_EC_CK26
SMB_EC_DA26

SLP_S3#22,29
SLP_S5#22
EC_SMI#22
LID_SW#33

R591 0_0603_5% @

1 2

FAN_SPEED
WWAN_POW ER_OFF
UTX
LAN_POWER_OFF_R

NUM_LED#33

12

4

OSC

1

OSC

R1099

4.7K_0402_5%

1 2

R731 0_0402_5%

1 2

R732 0_0402_5%

1 2

GATEA20
KB_RST#
SIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

CLK_PCI_EC

PCI_RST#
ECRST#

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2

SLP_S3#
SLP_S5#
EC_SMI#
LID_SW#
ESB_CLK_R
ESB_DAT_R
EC_PME#

ON/OFFBTN

NUM_LED#

CRY2

@

R595
20M_0402_5%

CRY1

+3VL +3VL_EC

R572

1 2

0_0805_5%

U30

1

GA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ#

4

LFRAME#

5

LAD3

7

LAD2

8

LAD1

10

LPC & MISC

LAD0

12

PCICLK

13

PCIRST#/GPIO05

37

ECRST#

20

SCI#/GPIO0E

38

CLKRUN#/GPIO1D

55

KSI0/GPIO30

56

KSI1/GPIO31

57

KSI2/GPIO32

58

KSI3/GPIO33

59

KSI4/GPIO34

60

KSI5/GPIO35

61

KSI6/GPIO36

62

KSI7/GPIO37

39

KSO0/GPIO20

40

KSO1/GPIO21

41

KSO2/GPIO22

42

KSO3/GPIO23

43

KSO4/GPIO24

44
45
46
47
48
49
50
51
52
53
54
81
82

77
78
79
80

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

122
123

+EC_AVCC

1

@

C315
10P_0402_25V8K

2

ESB_CLK_R
ESB_DAT_R

Int. K/B

KSO5/GPIO25

Matrix

KSO6/GPIO26
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

XCLK1
XCLK0

SM Bus

+3VL_EC

12

L30
0_0603_5%

1 2

C726 0.1U_0402_1 6V4Z

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

+EC_AVCC

9

22

33

96

111

125

VCC

VCC

VCC

VCC

VCC

VCC

PWM Output

AD Input

DA Output

PS2 Interface

SPI Device Interface

SPI Flash ROM

GPIO

GPIO

GND

GND

GND

GND

GND

11

24

35

94

113

Issued Date

67

AVCC

INVT_PWM/PWM 1/GPIO0F

BEEP#/PWM2/GPIO10

FANPWM1/GPIO12

ACOFF/FANPWM2/GPIO13

BATT_TEMP/AD0/GPIO38

BATT_OVP/AD1/GPIO39

ADP_I/AD2/GPIO3A

AD3/GPIO3B

AD4/GPIO42

SELIO2#/AD5/GPIO43

DAC_BRIG/DA0/GPIO3C

EN_DFAN1/DA1/GPIO3D

IREF/DA2/GPIO3E

DA3/GPIO3F

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C

PSDAT2/GPIO4D

TP_CLK/PSCLK3/GPIO4E

TP_DATA/PSDAT3/GPIO4F

SDICS#/GPXOA00
SDICLK/GPXOA01

SDIDO/GPXOA02

SDIDI/GPXID0

SPIDI/RD#

SPIDO/WR#

SPICLK/GPIO58

CIR_RX/GPIO40

CIR_RLC_TX/GPIO41

FSTCHG/SELIO#/GPIO50

BATT_CHGI_LED#/GPIO52

CAPS_LED#/GPIO53

BATT_LOW_LED#/GPIO54

SUSP_LED#/GPIO55

SYSON/GPIO56

VR_ON/XCLK32K/GPIO57

AC_IN/GPIO59

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04

EC_ON/GPXO05

EC_SWI#/GPXO06

ICH_PWROK/GPXO06

GPO

BKOFF#/GPXO08

WL_OFF#/GPXO09

PM_SLP_S4#/GPXID1

ENBKL/GPXID2

GPI

AGND

KB926QFD2_LQFP128_14X14

69

ECAGND

L31

1 2

+1.5VS

HDA level shift

B

E

HDA_RST#_CODEC21,28

INV_PWM

21
23

DIM_LED

26

ACOFF

27

BATT_TEMP

63

BATT_OVP

64

ADP_I

65

ADP_ID

66

TP_BTN#

75
76

FAN_SET

68

VCTRL

70

IREF

71

AC_SET

72

EC_MUTE#

83

USB_EN#

84

I2C_INT

85
86

TP_CLK

87

TP_DATA

88

97
98
99
109

119

R227 33_0402_5%

120
126
128

SPICS#

73
74
89
90
91
92
93
95
121
127

100
101
102
103
104
105
106
107

GPXO10

108

GPXO11

110
112
114

GPXID3

115

GPXID4

116

GPXID5

117

GPXID6

118

GPXID7

124

V18R

For C
Revision

0_0603_5%

2007/08/28 2006/07/26

1 2

R228 47_0402_5%

1 2

R229 33_0402_5%

1 2

CIR_IN
VCC1_PWRGD
FSTCHG
STD_ADP
CAPS_LED#
BAT_LED#
ON/OFFBTN_LED#
SYSON
VR_ON
AC_IN

EC_RSMRST#

R588

1 2

EC_ON

0_0402_5%

WL_BLUE_LED#
PM_PWROK_R
BKOFF#
M_PWROK
TP_LED#

SLP_S4#
ENBKL
EAPD_CODEC
THERM_SCI#
SUSP#
PWRBTN_OUT#
NMI_DBG#

1

C724

4.7U_0603_6.3V6K

2

NMI_DBG# PCI_SERR#

AC_IN ACIN

1 2

C791 100P_0402_50V8J

Vendor
Recommend

Compal Secret Data

INV_PWM 19

DIM_LED 35

ACOFF 37

C720

BATT_TEMP 36
BATT_OVP 36
ADP_I 37
ADP_ID 36
TP_BTN# 33

FAN_SET 6

VCTRL 37
IREF 37
AC_SET 37

EC_MUTE# 29

USB_EN# 30
I2C_INT 33

R582 0_0402_5%

1 2

R720 10K_0402_5%

1 2

CIR_IN 29

T84

FSTCHG 37
STD_ADP 3 7
CAPS_LED# 33
BAT_LED# 33
ON/OFFBTN_LED# 33

SYSON 26,35,40

VR_ON 42

EC_RSMRST# 22

EC_LID_OUT# 22
EC_ON 38
WL_BLUE_LED# 33

BKOFF# 19
M_PWROK 9,22
TP_LED# 33

SLP_S4# 22

ENBKL 11

EAPD_CODEC 28
THERM_SCI# 22

SUSP# 26,35,37,39

PWRBTN_OUT# 22

+3VL

12

R714

+3VL

12

12

10K_0402_5%

D14

R715
150K_0402_5%

2 1

R586 10K_0402_5%

Deciphered Date

3 1

Q21

MMBT3904_NL_SOT23-3

0.01U_0402_16V7K

ECAGND

1 2

R579 10K_0402_5%
R580 10K_0402_5%

FRD#
FWR#
SPI_CLK
FSEL#

100_0402_5%

21

CH751H-40PT_SOD323-2

D13

CH751H-40PT_SOD323-2

12

R250
56_0402_5%

2

C

1 2
1 2

FRD# 31
FWR# 31
SPI_CLK 31
FSEL# 31

+5VL

PV-1 For WWAN noise

R254

1 2

ADP_ID

CH751H-40PT_SOD323-2

PCI_SERR# 20

ACIN 37

+3VS

12

R251
10K_0402_5%

TP_CLK 33
TP_DATA 33

AC_LED# 36

SPI_CLK

1

C327
22P_0402_50V8J

2

HDA_RST#_EC

+5V_TP

PM_PWROK 9,22

BATT_OVP

EC recommend

KSO15

KSO10

KSO11

KSO14

KSO13

KSO12

KSO3

KSO6

KSO8

KSO7

KSO4

KSO2

KSI0

KSO1

KSO5

KSI3

KSI2

KSO0

KSI5

KSI4

KSO9

KSI6

KSI7

KSI1

14" INT_KBD

100P_0402_50V8J

For EMI

C792 100P_0402_50V8J@

1 2

C793 100P_0402_50V8J@

1 2

C794 100P_0402_50V8J@

1 2

C795 100P_0402_50V8J@

1 2

C796 100P_0402_50V8J@

1 2

C797 100P_0402_50V8J@

1 2

C798 100P_0402_50V8J@

1 2

C799 100P_0402_50V8J@

1 2

C800 100P_0402_50V8J@

1 2

C801 100P_0402_50V8J@

1 2

C802 100P_0402_50V8J@

1 2

C803 100P_0402_50V8J@

1 2

C804 100P_0402_50V8J@

1 2

C805 100P_0402_50V8J@

1 2

C806 100P_0402_50V8J@

1 2

C807 100P_0402_50V8J@

1 2

C808 100P_0402_50V8J@

1 2

C809 100P_0402_50V8J@

1 2

C810 100P_0402_50V8J@

1 2

C811 100P_0402_50V8J@

1 2

C812 100P_0402_50V8J@

1 2

C813 100P_0402_50V8J@

1 2

C814 100P_0402_50V8J@

1 2

C815 100P_0402_50V8J@

1 2

C301

CONN.( TYPE "D"
KB)

KSO15
KSO10
KSO11
KSO14

+3VL

D16

2 1

SI-1 Reverse KB connector

Title

Size Document Number Rev

Date: Sheet of

KSO13
KSO12
KSO3
KSO6
KSO8
KSO7
KSO4
KSO2
KSI0
KSO1
KSO5
KSI3
KSI2
KSO0
KSI5
KSI4
KSO9
KSI6
KSI7
KSI1

Compal Electronics, Inc.

EC KB926/KB Conn.

Montevina UMA

CONN@

JKB

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

G1

26

G2

ACES_85202-24051

12

0.1

32 46Wednesday, February 18, 2009

A

B

C

D

E

Power Button

SI-1 Delete SW2

1 1

System LED Conn Caps-Lock Conn

White

AMBER

2 2

+5VALW

+5VS

+3VS

BAT_LED#3 2

SATA_LED#21

HDDHALT_LED#22

ON/OFFBTN_LED#

SI-1 Change Cap board power rail to +3VL

SWITCH BOARD.

SMB_EC_CK132 ,36
SMB_EC_DA132 ,36

WL_BLUE_BTN32

ON/OFFBTN_LED#32

ESB_CLK32
ESB_DAT32
I2C_INT32

+5VALW

LID_SW#32

3 3

ON/OFFBTN32

NUM_LED#32

WL_BLUE_LED#

ENE@

R56 FBMA-11-100505-801T 0402

1 2

R149 FBMA-11-100505-801T 0402

1 2

ENE@

Close to JP59

main@

1 2

R169 1.8K_0402_5%

R1192 0_0402_5%

1 2

OPP@

CONN@

JLED

8

8

GND

7

7

6

6

5

5

4

4

3

3

2

2

1

1

GND

ACES_87213-0800G

Cypress@

R729 0_0402_5%

1 2

R730 0_0402_5%

1 2

Cypress@

R151 0_0402_5%OPP@

1 2

R1191 0_0402_5%OPP@

1 2

C1518 0.1U_0402_16V4Z

10

9

1 2

ESB_CLK_CAP

CONN@

JCAP

P-TWO_161011-04021

ENE@

C326
33P_0402_50V8K

12

ESB_CLK_CAP
ESB_DAT_CAP

R238 1K_0402_1%

1
2
3

4
GND
GND

1 2

+5VS

1
2
3
4
5
6

+3VL

+5VALW

12

R51
0_0805_5%

Main@

+5VS

2

3

D60 SM05_SOT23@

1

12

R53
0_0805_5%

OPP@

CAPS_LED# 32

1

4.7U_0603_6.3V6K

C313

2

JCSB

CONN@

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

GND

12

GND

P-TWO_161021-10021

Keyboard backlight Conn

+5VS_LED

1 2

0_0805_5%

MV-1 For ESD request, close to JCSB

for debug only

R205

P-TWO_161011-04021

MV-1 For ESD request, close to JTP

Mini card LED

+5V_TP

CONN@

JKBL

1

1

2

2

3

3

4

4

5

GND

6

GND

T/P Board Conn

+5VALW +5V_TP

R691 0_0603_5%

1 2

2

3

D67
SM05_SOT23

1

MV-1 For ESD request, close to JTPSW

TP_LED#

TP_BTN#

3

1

2

D65
SM05_SOT23

+5VS

3

2

1

D66
SM05_SOT23

T/P Board (Inculde T/P_ON/OFF)

CONN@

JTPSW

1

1

2

2

3

3

4

4

5

GND

6

GND

P-TWO_161011-04021

CONN@

JTP

1
2
3

4
GND
GND

P-TWO_161011-04021

BT_LED30

TP_LED#
TP_BTN#

1

TP_CLK

2

TP_DATA

3
4
5
6

2N7002_SOT23-3

R716

100K_0402_5%

+5V_TP

1

2

100P_0402_50V8J

Q11

2

G

12

+5VS

TP_LED# 32
TP_BTN# 32

TP_DATA
TP_CLK

C729

0.1U_0402_16V4Z

1

C730

@

2

+3VS

13

D

S

3

1

1

C731

@

100P_0402_50V8J

2

12

R193
10K_0402_5%

2

D28
SM05_SOT23

TP_CLK 32
TP_DATA 32

WL_BLUE_LED# 32

D24

WL_LED#26

WW_LED#26

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2007/08/28 2006/07/26

Compal Secret Data

Deciphered Date

2

3

PSOT24C_SOT23-3

D

1

Title

Size Document Number Rev

Date: Sheet of

WL_BLUE_LED#

Compal Electronics, Inc.

KBD, ON/OFF, SW, CIR

Montevina UMA

33 46Wednesday, February 18, 2009

E

0.1

5

4

3

2

1

+3VS_LS +3VS_LS

36

35

34

33

32

31

30

29

28

27

26

25

0.5P_0402_50V8B

0.5P_0402_50V8B

TMDS_B_DATA1 11
TMDS_B_DATA1# 11

TMDS_B_DATA0 11
TMDS_B_DATA0# 11

HDMI_DETECT

HDMIDAT

HDMICLK

+3VS_LS

R655 0_0402_5%

C770

@

C772

@

R1241 4.7K_0402_5%@

R1202 4.7K_0402_5%@

R1247 4.7K_0402_5%@

1 2

R1249 0_0402_5%

12

HDMI_DETECT

HDMI_TX_0-

HDMI_TX_0+HDMICLK+

HDMI_TX_1-

HDMI_TX_1+

12

12

12

12

12

+3VS_LS

+3VS_LS

R12030_0402_5%

R12050_0402_5%

R1245 0_0402_5%
R1246 0_0402_5%@
R651 4.7K_0402_5%
R652 0_0402_5%@

+3VS_LS

12

+3VS_LS

13

D

2

G

S

R654
10K_0402_5%

2N7002_SOT23-3

TMDS_B_DATA2#11
TMDS_B_DATA211

TMDS_B_CLK#11
TMDS_B_CLK11

4.7K_0402_5%

R1242

1 2

0_0402_5%

12

+3VS_LS

R1240

@

+3VS_LS

TMDS_B_HPD

C769

@

0.5P_0402_50V8B

C771

@

0.5P_0402_50V8B

48

47

46

45

44

43

42

41

40

39

38

12

U43

1

2

3

4

5

6

7

8

9

10

11

12

49

R656

@

1 2

68_0402_5%

R658

@

1 2

68_0402_5%

IN_D4-

IN_D4+

GND

VCC3V

PC0

FUNCTION1

PC1

FUCNTION2

GND

ANALOG1(REXT)

HPD_SOURCE

SDA_SOURCE

SCL_SOURCE

ANALOG2

VCC3V

GND

thm_pad

OUT_D4+13OUT_D4-14VCC3V15OUT_D3+16OUT_D3-17GND18OUT_D2+19OUT_D2-20VCC3V21OUT_D1+22OUT_D1-23GND

GND

IN_D3-

VCC3V

IN_D3+

IN_D2-

IN_D2+

+3VS_LS+3VS_LS

37

GND

IN_D1-

VCC3V

IN_D1+

GND

FUNCTION4

FUNCTION3

VCC3V

DDC_EN

GND

HPD_SINK

SDA_SINK

SCL_SINK

GND

VCC3V

OE*

24

S IC STHDLS101TQTR QFN 48P HDMI SHIFTER

R657

@

1 2

68_0402_5%

R659

@

1 2

68_0402_5%

EQUALIZATION SETTING:
[PC1,PC0]=00,8dB
[PC1,PC0]=01,4dB (Recommanded)

D D

[PC1,PC0]=10,12dB
[PC1,PC0]=11,0dB

+3VS_LS

12

12

R650

R649

2.2K_0402_5%

HDMIDAT_NB9

HDMICLK_NB9

C C

TMDS_B_HPD#11

2.2K_0402_5%

+3VS_LS

TMDS_B_HPD#

+3VS_LS

R1243

@

4.7K_0402_5%

1 2

R1244 0_0402_5%@

1 2

R1206 0_0402_5%

1 2

C1517 2.2U_0603_6.3V4Z @

12

R1207
20K_0402_5%

12

R1208

7.5K_0402_1%

12

R9

0_0402_5%

+3VS_LS

R1201

@

4.7K_0402_5%

1 2

R1204 4.7K_0402_5%

+3VS_LS

+3VS_LS

TMDS_B_HPD

12

12

R653 3.9K_0402_1%

R1248 0_0402_5%

1 2

R1250 4.7K_0402 _5%@

1 2

R1251 4.7K_0402 _5%@

1 2

1 2

R1252 0_0402_5%

HDMICLK-

HDMI_TX_2+

HDMI_TX_2-

R648

1 2

0_0603_5%

1

2

C321

1

12
12
12
12

Q108

+3VS_LS

+3VS_LS

1

C320

C319

2

2

0.1U_0402_10V6K

0.01U_0402_16V7K

+3VS_LS+3VS

1

2

C318

0.1U_0402_10V6K

10U_0805_6.3V6M

SI-1 Use ST only

R1212 0_0402_5%@

1 2

HDMICLK-

HDMICLK+

B B

HDMI_TX_0-

HDMI_TX_0+

HDMI_TX_1-

HDMI_TX_1+

A A

HDMI_TX_2-

HDMI_TX_2+

1

4

1

4

1

4

1

4

L38

1

4

1 2

R1213 0_0402_5%@

R1214 0_0402_5%@

1 2

L39

1

4

1 2

R1215 0_0402_5%@

R1216 0_0402_5%@

1 2

L41

1

4

1 2

R1217 0_0402_5%@

R1218 0_0402_5%@

1 2

L42

1

4

1 2

R1219 0_0402_5%@

5

2

2

WCM-2012-900T_0805

3

3

2

2

WCM-2012-900T_0805

3

3

2

2

WCM-2012-900T_0805

3

3

2

2

WCM-2012-900T_0805

3

3

HDMI_CLK-

HDMI_CLK+

HDMI_TX0-

HDMI_TX0+

HDMI_TX1-

HDMI_TX1+

HDMI_TX2-

HDMI_TX2+

To option use ST or Parade

Parade

ST

R1240

R1242

R1201

R1204

4.7K ohm

R1243

R1244

R653

3.9K ohm 499 ohm

R1206

8101T

X X X

0 ohm

0 ohm 4.7K ohm

4.7K ohmX

X

X

0 ohmXX X

C1517

R1248

0 ohm 0 ohm X

R1250

R1251

R1252

R1247

R1249

R1245

R1246

R1203

R1241

R1205

R1202

X X 4.7K ohm

X X 4.7K ohm

0 ohm 0 ohm

X XX4.7K ohm

0 ohm 0 ohm

0 ohm 0 ohm

X XX4.7K ohm

0 ohm 4.7K ohm

X X X

0 ohm

X X 4.7K ohm

C773 0.1uF 1uF

R1207

R1208

V

V

4

Parade
8171

X 4.7K ohm

X

4.7K ohm

X X

499 ohm

X 2.2uF

X

X X

1uF

X

X

+5VS

HDMI Connector

X

12

12

R49

3.9K_0402_1%

HDMIDAT

HDMI_DETECT

X

Security Classification

X

X

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

SKS10-04AT_TSMA

3

D32

2007/08/28 2006/03/10

R665

1 2

1K_0402_1%

2 1

Compal Secret Data

L40

1 2

FBML10160808121LMT_0603

Deciphered Date

C774

330P_0402_50V7K

2

HDMICLK

HDMI_CLK-

1

HDMI_CLK+
HDMI_TX0­HDMI_TX0+

2

HDMI_TX1­HDMI_TX1+
HDMI_TX2­HDMI_TX2+

Title

Size Document Number Rev

Custom

Date: Sheet

C273

@

1 2

21

2200P_0402_25V7K

RB411D T146 _SOT23-3
D31

+5VS_HDMI

1

0.1U_0402_16V4Z
C773

3.9K_0402_1%

18
16
15
19

12
10

2

JHDMI1

+5V
SDA

Reserved

SCL
HP_DET

CK­CK+

9

D0-

7

D0+

6

D1-

4

D1+

3

D2-

1

D2+

DDC/CEC_GND

SUYIN_100042MR019S153ZL

CONN@

CEC

GND
GND
GND
GND
GND
GND
GND
GND

R50

Compal Electronics, Inc.

HDMI LS & Conn.

Montevina UMA

1

1

C314
2200P_0402_25V7K

2

13
14

2
5
8
11
20
21
22
23
17

34 46Wednesday, February 18, 2009

@

0.1

of

5

4

3

2

1

+5VALW to +5VS

+5VALW

C760

R223

330K_0402_5%

Q34A

Transfer

1

2

2

B+

D D

12

SUSP

2N7002DW-7-F_SOT363-6

+1.8V to +1.8VS
Transfer

C C

1

C766

@

2

10U_0805_10V4Z

SI7326DN-T1-E3_PAK1212-8

U32

10U_0805_10V4Z

RUNON

61

SI7326DN-T1-E3_PAK1212-8

U34

@

RUNON

4

4

12

470_0402_5%

1

4700P_0402_25V7K

2

1
2
35

+5VS

1
2
35

1

C761

2

R224

C65

+1.8VS+1.8V

1

@

C767

@

2

0.1U_0402_16V4Z

C768

1

C762

2

0.1U_0402_16V4Z

10U_0805_10V4Z

1

2

10U_0805_10V4Z

+3VALW to +3VS
Transfer

12

R636

330K_0402_5%

SUSP

5

Q34B

2N7002DW-7-F_SOT363-6

SYSON#41 SUSP 41

SYSON26,32,40

SI7326DN-T1-E3_PAK1212-8

+3VALWB+

1

C759

10U_0805_10V4Z

2

RUNON_3VS

3

4

U33

100K_0402_5%

SYSON#

SYSON

4

12

1

2

R639

Q13A

2

+3VS

1
2
35

C763

R638

470_0402_5%

C765

0.01U_0402_16V7K

+3VL

+3VL

12

61

2N7002DW-7-F_SOT363-6

1

2

0.1U_0402_16V4Z

12

R640

100K_0402_5%

3

Q13B

4

2N7002DW-7-F_SOT363-6

C764

1

2

10U_0805_10V4Z

SUSP

SUSP#

5

SUSP# 26,32,37,39

DIM LED

DIM_LED32

C1512

Q15

SI2301BDS-T1-E3_SOT23-3

S

DIM_LED#

Q35
2N7002_SOT23-3

C1514

0.1U_0402_16V4Z

G

1

2

12

R637

10K_0402_5%

13

DIM_LED

1

2

D

2

G

S

SI-1 For EMI DDR issue
SI-R 2 caps and change to GND

1

C1513

2

0.1U_0402_16V4Z

+5VS_LED+5VS

D

13

1

1

2

2

0.1U_0402_16V4Z

C294

0.1U_0402_16V4Z

+1.8V

2

C1515

0.1U_0402_16V4Z

H1

1

HOLEA

1

H10
HOLEA

1

FM1

Discharge circuit

+VCCP +0.9V +1.8VS

12

R645

470_0402_5%

3

Q9B

SUSP

5

4

2N7002DW-7-F_SOT363-6

470_0402_5%

Q9A

SUSP

2

R644

+1.5VS

12

61

2N7002DW-7-F_SOT363-6

4

B B

A A

5

+5VS +3VS

12

R641

470_0402_5%

61

Q6A

SUSP SYSON#

2

SUSP SUSP

2N7002DW-7-F_SOT363-6

R642

470_0402_5%

Q6B

5

12

3

4

2N7002DW-7-F_SOT363-6

+1.8V

12

R643

470_0402_5%

61

Q12A

2

2N7002DW-7-F_SOT363-6

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

12

R646

470_0402_5%

3

Q12B

5

4

SUSP

2N7002DW-7-F_SOT363-6

2007/08/28 2006/07/26

12

R647

@

470_0402_5%

13

D

Q44

@

2

G

S

2N7002_SOT23-3

Compal Secret Data

Deciphered Date

2

H3

H2

HOLEA

HOLEA

1

1

H12

H11

HOLEA

HOLEA

1

FM3

FM2

1

1

T21
T33
T45
T52
T60
T62
T64
T73
T75

Title

Size Document Number Rev

Date: Sheet of

H5

H4

HOLEA

HOLEA

1

1

H13
HOLEA

1

1

FM4

1

T32
T34
T51
T53
T61

For ICT

T63
T72
T74
T76

H6
HOLEA

1

H7
HOLEA

1

Compal Electronics, Inc.

DC/DC Interface

Montevina UMA

1

H8
HOLEA

1

H9
HOLEA

1

35 46Wednesday, February 18, 2009

0.1

A

B

C

D

+3VALW

PQ3
TP0610K -T1-E3_SOT23-3

1 2

100K_04 02_5%

1 1

2

1 3

PR8
2K_0402 _5%

JDC1

6

GND

5

GND

4

4

3

3

2

2

1

1

ACES_87 302-0441

2 2

<BOM Struc ture>

1 2

ADP_SIGNA L

ADPINADPIN

2

3

PD1

PJSOT24 C_SOT23-3

1

1 2

PR3
10K_040 2_5%

PR9

<BOM Struc ture>

12

+3VL

PC2

connect to KBC pin97

12

PR2
10K_040 2_5%

HCB2012 KF-121T50_080 5

1 2

HCB2012 KF-121T50_080 5

1 2

12

PC3
1000P_0 402_50V7K

100P_0402_50V8J

AC_LED# 32

12

PD4

RLZ3.6B_ LL34

PL1

PL2

12

12

PC4

100P_0402_50V8J

PC12

@1000P_ 0402_50V7K

VIN

12

PC5

1000P_0402_50V7K

ADP_ID 32

BATT

12

+5VALW

PR1

340K_0402_1%

12

PR4

499K_0402_1%

12

PC6

0.01U_0402_25V7K

12

PR6

105K_0402_1%

12

PC1

0.01U_0402_25V7K

3

2

PU1A

LM358AD T_SO8

8

P

+

1

0

-

G

PR5

10K_040 2_5%

12

BATT_OVP 32

4

VMB

PL3

JBATT

1

1

2

2

3

3

4

4

5

5

6

6

7

GND

8

GND

SUYIN_200045 MR006G101ZR

3 3

PR16

6.49K_04 02_1%

1 2

12

PR17
1K_0402 _5%

4 4

EC_SMD
EC_SMC

PD3

3

1

2

PJSOT24 C_SOT23-3

PR13

100_040 2_5%

BAT_ID 37

+3VL

12

3

2

12

PR14
100_040 2_5%

BATT_TE MP 32

PD2

1

PJSOT24 C_SOT23-3

SMB_EC_ DA1

SMB_EC_ CK1

HCB2012 KF-121T50_080 5

1 2

PL4

HCB2012 KF-121T50_080 5

1 2

12

PC8
1000P_0 402_50V7K

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

BATT

12

PC9

0.01U_04 02_50V4Z

SMB_EC_ DA1 32,3 3

SMB_EC_ CK1 32,3 3

0.22U_06 03_10V7K

PH1 under CPU botten side :

CPU thermal protection at 90 +-3 degree C

+5VS

CPU

12

PH1
10K_TH1 1-3H103FT_060 3_1%

PR10

200K_04 02_1%

1 2

+5VALW

12

PR12

2.49K_04 02_1%

PC10

12

2007/05/ 29 2008 /05/29

1 2

PR11

150K_04 02_1%

PR15

150K_04 02_1%

Compal Secret Data

Deciphered Date

C

12

604K_04 02_1%

1 2

5

+

6

-

12

PC11
1000P_0 402_50V7K

PR7

8

P

0

G

PU1B

4

LM358AD T_SO8

13

D

7

Title

Size Document Number Rev

Date: Sheet of

2

Compal Electronics, Inc.

DC Connector/CPU_OTP

PQ1

G

SSM3K70 02FU_SC70-3

S

Montevina Consumer Discrete

D

EN0 38

0.1

36 46Wednesd ay, February 18, 2009

A

VIN

PQ101
AO4433

8
7

PR101

1 1

PR107
47K_0402_1%

1 2

SSM3K7002FU_SC70-3

PQ107

2

G

47K_0402_5%

1 2

12

PC101

47P_0402_50V8J

2

13

2

PQ105

13

DTC115EUA_SC70-3

D

S

5

PQ104

DTA144EUA_SC70-3

1 3

PACIN_1 38

PR111

3K_0402_1%

PACIN

1 2

ACOFF#

2 2

PD101

1 2

1SS355_SOD323-2

<BOM Structure>

2

G

PQ109

13

D

SSM3K7002FU_SC70-3

S

VCTRL32

4

1 2

1U_0603_10V6K

1
2
36

12

PC106

<BOM Structure>

0.47U_0603_16V7K

PR114
@0_0402_5%

PC117

P2

12

12

PR109
150K_0402_5%

12

PR106

143K_0402_1%

PQ103

AO4433

1
2
3 6

4

AC_SET32

200K_0402_5%

12

PR113

12

PR115
100K_0402_1%

8
7

5

SUSP#26,32,35,39

PR104
0_0402_5%

1 2

@0.01U_0402_16V7K

PR110
0_0402_5%

1 2

PC112

1 2

1U_0603_6.3V6M

15K_0402_1%

ADP_I32

Charge Detector

VIN

PD104
1SS355_SOD323-2

PR123

1 2

1M_0402_5%

1 2

VIN_1

3 3

12

PR125

47_1206_5%

VIN

12

PR131
133K_0402_1%

12

PR135
10K_0603_0.1%

12

PC125

0.1U_0603_25V7K

8

3

P

+

1

O

2

-

G

PU102A
LM393DG_SO8

4

1.24VREF

4 4

+3VL

12

PR129

10K_0402_1%

STD_ADP 32

2

G

+3VL

PR128

10K_0402_5%

FSTCHG32

12

CHGEN#

13

D

PQ112
SSM3K7002FU_SC70-3

S

FSTCHG#

1 2

PR137
20K_0402_1%

PC120

0.22U_0603_10V7K

+3VL

12

PR132

100K_0402_5%

13

D

2

G

S

ACDET

12

PR138

100K_0402_1%

12

PC107

BQ24740VREF

+3VL

12

PR116

PR118

10K_0402_5%

1 2

12

PQ113
SSM3K7002FU_SC70-3

B

ACSET

ACSET

12

PR140
100K_0402_5%

<BOM Structure>

8

IADSLP

9

AGND

10

VREF

11

VDAC

12

VADJ

13

EXTPWR

14

ISYNSET

PC121

100P_0402_50V8J

PC123

0.1U_0402_10V7K

ACDET

6

7

LPREF

ACSET

PU101
BQ24740RHDR_QFN28_5X5

IADAPT

SRSET

15

16

IADAPT

12

12

5

17

BATT

PC108

ACDET

BAT

P4

PR102

1

2

1U_0603_6.3V6M

12

0.1U_0603_25V7K

4

LPMD

SRN

18

12

PR121
200K_0402_1%

1 2

PC102

ACP

ACN

3

2

ACP

SRP

19

20

PR120

133K_0402_1%

B+

PL101

4

HCB2012KF-121T50_0805

1 2

3

0.012_2512_1%

CHGEN#

1

ACN

TP

CHGEN

PVCC

BTST

HIDRV

PH

REGN

LODRV

PGND

DPMDET

CELLS

21

SSM3K7002FU_SC70-3

12

29

28

27

26

25

24

23

22

PQ111

BST_CHG

DH_CHG

LX_CHG

REGNVADJ

DL_CHG

IREF 32

12

PC103

PR108
10_1206_5%

1 2

PC110
1U_0805_25V6K

1 2

PR142
0_0402_5%

1 2

PR139
0_0402_5%

1 2

PD102

1SS355_SOD323-2

<BOM Structure>

12

PC119

1U_0603_10V6K

100K_0402_5%

1 2

13

D

2

G

S

12

4.7U_0805_25V6-K

12

S TR AO4468 1N SO8

PR117

12

PC104

4.7U_0805_25V6-K

PC111

1 2

0.1U_0402_10V7K

BQ24740VREF

12

47K_0402_5%
PR119

PC124

0.1U_0603_25V7K

PC105

PQ110

C

D

BATT

PQ102
AO4433 1P SO8

1
2

CHG_B+

3 6

4.7U_0805_25V6-K

CHG_B+

578

578

AO4466_SO8

3 6

241

12

@4.7_1206_5%

1 2

3 6

241

PQ108

PL102
10U_LF919AS-100M-P3_4.5A_20%

1 2

PR141

12

PC135
@470P_0603_50V8J

PR112

0.015_1206_1%

1 2

12

PC113

PC114

1 2

4.7U_0805_25V6-K

4.7U_0805_25V6-K

PC118

0.1U_0402_10V7K

BAT_ID 36

12

VIN

12

PR126

PC126

0.047U_0402_16V7K

100K_0402_1%

12

PR130

2.15K_0402_1%

1 2

12

PR133
10K_0603_0.1%

22P_0402_50V8J

PC127

12

4

PR122
681K_0402_1%

1 2

5

+

6

-

8
7

5

ACOFF#

BATT

12

PC115

4.7U_0805_25V6-K

8

PU102B

P

7

O

G

LM393DG_SO8

4

PR136

60.4K_0402_1%

1 2

<BOM Structure>

4

REF

5

ANODE

LMV431ACM5X_SOT23-5

12

PC116

4.7U_0805_25V6-K

PD103

RLZ4.3B_LL34

CATHODE

PU104

VIN_1

NC

NC

12

PC128

4.7U_0805_25V6-K

VIN

12

PR127
10K_0402_1%

12

3

2

1

PR103

47K_0402_5%

1 2

12

PR105
10K_0402_5%

13

2

PQ106
DTC115EUA_SC70-3

PR124
1K_0402_5%

1 2

PACIN

12

PR134
10K_0402_5%

1.24VREF

VIN

ACOFF 32

ACIN 32

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

2007/05/29 2008/05/29

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Charger

LA-4481P

D

37 46Wednesday, February 18, 2009

0.1

A

B

C

D

E

2VREF_51125

12

PC302

0.22U_0603_10V7K

1 1

PR301

13.7K_0402_1%

1 2

20K_0402_1%

115K_0402_1%

BST_3V

UG_3V

PR311

PR303

1 2

PR305

1 2

25

7

8

9

10

11

12

12

P PAD

VO2

VREG3

VBST2

DRVH2

LL2

DRVL2

ENTRIP2

3

4

5

6

VFB2

TONSEL

ENTRIP2

GND

SKIPSEL

EN0

15

16

14

13

12

B++

12

PC316

0.1U_0402_25V6

+3VALWP

B++

+3VLP

12

12

PQ301

PC301

PC303

2200P_0402_50V7K

4.7U_0805_25V6-K

PL302

4.7UH_SIQB74B-4R7PF_4A_20%

1

PC309

+

2

150U 6.3V B2 R45M

12

12

PR315

@4.7_1206_5%

12

PC314

@680P_0603_50V8J

S TR AON7408L 1N DFN

3 5

241

PQ303
S TR AON7406L

3 5

241

10U_0805_6.3V6M

UG1_3V

PR309

0_0402_5%

1 2

PC306

12

1 2

1 2

0_0402_5%

PC307

0.1U_0402_10V7K

LX_3V

B++

EN036

PR307

LG_3V

PR312

1M_0402_5%

1 2

<BOM Structure>

191K_0402_1%

B+

2 2

PL301

HCB2012KF-121T50_0805

1 2

2VREF_51125

PQ305

ENTRIP1

13

D

2

G

S

PQ308

13

D

2

G

12

D

S

S

2

G

PQ307

13

SSM3K7002FU_SC70-3

2

G

ENTRIP2

13

D

S

PR313
100K_0402_5%

1 2

PQ306
SSM3K7002FU_SC70-3

VL

12

PR314
100K_0402_5%

EC_ON 32

+5VALWP

+3VALWP

PJP302

1 2

PAD-OPEN 4x4m
PJP303

1 2

PAD-OPEN 4x4m

3 3

SSM3K7002FU_SC70-3

@SSM3K7002FU_SC70-3

PACIN_137

1 2

PR318
604K_0402_1%

<BOM Structure>

PC318

0.047U_0603_16V7K

PR302

30.9K_0402_1%

1 2

PR304
20K_0402_1%

1 2

PR306

90.9K_0402_1%

ENTRIP1

1 2

1

2

VFB1

VREF

ENTRIP1

24

VO1

23

PGOOD

VBST1

DRVH1

DRVL1

VREG5

VIN

VCLK

PU301

17

18

RT8205AGQW WQFN 24P

BST_5V

22

UG_5V

21

LX_5V

20

LL1

LG_5V

19

VL

12

PC311
10U_0805_10V6K

PC312

0.1U_0603_25V7K

(4.5A,180mils ,Via NO.= 9)

+5VALW

(3A,120mils ,Via NO.= 6)

+3VALW

PR308

2.2_0402_5%

1 2

PR317

1 2

0_0402_5%

B++

PC304

2200P_0402_50V7K

PC308

0.1U_0402_10V7K

1 2

R_EC_RSMRST# 22

12

12

PR310
0_0402_5%

1 2

12

PC305

PC313

0.1U_0402_25V6

10U_1206_25V6M

3 5

241

3 5

241

PQ304

S TR AON7702L 1N DFN

+3VLP

VL

PQ302

S TR AON7408L 1N DFN

PL303

4.7UH_PCMC063T-4R7MN_5.5A_20%

1 2

12

PR316

@4.7_1206_5%

12

PC315

@680P_0603_50V8J

PJP301

2 1

PAD-OPEN 2x2m

PJP304

2 1

PAD-OPEN 2x2m

+3VL

+5VL

1

+

PC310
150U 6.3V B2 R45M

2

+5VALWP

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet of

Compal Electronics, Inc.

3.3VALWP/5VALWP

LA-4481P

38 46Wednesday, February 18, 2009

E

0.1

5

4

3

2

1

25

7

8

9

10

11

12

15.8K_04 02_1%

1 2

PC514

PR502

75K_040 2_1%

1 2

PR505

0_0402_ 5%

PU501

P PAD

PGOOD2

EN2

VBST2

DR VH2

LL2

DR VL2

PR510

1 2

3.3_0402 _5%

12

6

VO2

PGND2

13

PR514

5

VFB2

TRIP2

14

1 2

3

4

GND

TONSEL

V5FILT

V5IN

15

16

12

PC515

4.7U_080 5_10V6K

2

VFB1

TRIP1

17

1 2

PR503

10.2K_06 03_0.1%

1 2

1

VO1

24

PGOOD1

23

EN1

BST_1.5V

22

VBST1

21

DR VH1

DR VL1

PGND1

TPS5112 4RGER_QFN24_ 4x4

18

PR511

9.53K_04 02_1%

+5VALW

LX_1.5V

20

LL1

LG_1.5V

19

PR504

10.2K_06 03_0.1%

1 2

0_0402_ 5%

12

PC512
@0.1U_04 02_16V7K

+1.5VSP

PR507

12

PR509

0_0402_ 5%

PR512

0_0402_ 5%

1 2

12

PC507

0.1U_040 2_10V7K

1 2

UG1_1.5V

12

PR516
@4.7_120 6_5%

12

PC519

@680P_0 603_50V7K

PQ501

578

5

4

SUSP# 26,32,35,37

B+++

3 6

241

3.3UH 30% MSCDRI-7030AB-3R3 N 4.1A

786

123

PL502

HCB2012 KF-121T50_080 5

12

12

PC516

PC504

4.7U_0805_25V6-K

@4.7U_0805_25V6-K

AO4466_ SO8

PL501

1 2

PQ503

PC510

4.7U_080 5_6.3V6K

AO4468_ SO8

B+

12

12

12

PC521

PC505

2200P_0402_50V7K

0.1U_0402_25V6

+1.5VSP

1

+

PC508

220U_B2

1 2

2

PR501

29.4K_04 02_1%

PR506
0_0402_ 5%

12

PR5080_0402_ 5%

PC518

820P_06 03_50V7K

12

1 2

12

12

12

PC513
@0.1U_04 02_16V7K

BST_1.05 V

UG_1.05V

LX_1.05V

LG_1.05V

1U_0603 _10V6K

D D

+1.05V_VCCP

C C

B+++

12

12

PC503

PC501

4.7U_0805_25V6-K

2.2UH_PC MC063T-2R2MN_ 8A_20%

1

12

+

PC517

2

220U 2.5V B2

<BOM Structure>

PC509

4.7U_080 5_6.3V6K

PC502

2200P_0402_50V7K

4.7U_0805_25V6-K

AO4466_ SO8

PL503

12

12

0.1U_0402_25V6
PC520

PQ502

578

3 6

241

12

786

5

PQ504

123

<BOM Struc ture>

IRF8707TR PBF_SO8

+1.05V_V CCP

PC506

0.1U_040 2_10V7K

UG1_1.05 V UG_1.5V

12

PR515

4.7_1206 _5%

4

12

PR513

0_0402_ 5%

SUSP#26,32,35,37

B B

PJP501

+1.5VSP

+1.05V_V CCP

A A

1 2

PAD-OPEN 4x4m

PJP502

1 2

PAD-OPEN 4x4m

5

(7A,280mils ,Via NO.=14)

+1.5VS

(6A,240mils ,Via NO.= 12)

+VCCP

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/05/ 29 2008 /05/29

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet of

Compal Electronics, Inc.

1.5VP/1.05V_VCCP

Montevina Consumer Discrete

39 46Wednesd ay, February 18, 2009

1

0.1

A

1 1

PR401

0_0402_ 5%

SYSON26,32,35

2 2

1 2

@1000P_ 0402_50V7K

PC401

+1.8VP

12

PR405

0_0402_ 5%

PR403

316_040 2_1%

12

+5VALW

12

12

PC409
1U_0603 _10V6K

+1.8VP

PR408

1 2

14.3K_06 03_0.1%

PR404
255K_04 02_1%

1 2

B

C

D

PL401

12

12

PC404

4.7U_0805_25V6-K

PL402

1 2

HCB1608 KF-121T30_060 3

1 2

PC405

2200P_0402_50V7K

1

+

PC408

2

220U_2.5V _B2

12

PC406
@680P_0 402_50V7K

12

12

PC407

4.7U_0805_6.3V6K

B+

+1.8VP

220P_0603_50V8J

PC410

2

3

4

5

6

PU401

TON

VOUT

V5FILT

VFB

PGOOD

1

EN_PSV

GND7PGND

1 2

PR402

0_0402_ 5%

14TP15

TRIP

DH_1.8V

13

LX_1.8V

12

LL

11

10

9

VBST

DRVH

V5DRV

DRVL

TPS5111 7RGYR_QFN14_3.5x3.5

8

BST1_1.8 VBST_1.8V

0.1U_040 2_10V7K

+5VALW

12

4.7U_080 5_10V6K

1 2

PC402

1 2

PR406
10K_040 2_1%

PC415

S TR AON7 408L 1N DFN

PQ401

PR411

1 2

0_0402_ 5%

DH1_1.8V

DL_1.8V

3 5

241

3 5

241

12

PQ402

S TR AON7 702L

1.8V_B+

12

PC403

PC414

0.1U_0402_25V6

4.7U_0805_25V6-K

2.2UH_PC MC063T-2R2MN_ 8A_20%

12

PR407

4.7_1206 _5%

PC412
180P_04 02_50V8J

1 2

12

PR409

10K_060 3_0.1%

3 3

PJP401

+1.8VP

4 4

1 2

PAD-OPEN 4x4m

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2007/05/ 29 2008 /05/29

(7A,280mils ,Via NO.=14)

+1.8V

Compal Secret Data

Deciphered Date

C

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

+1.8VP

Montevina Consumer Discrete

D

40 46Wednesd ay, February 18, 2009

0.1

5

D D

C C

4

10U_0805_10V4Z

SYSON#35

SUSP35

@0_0402_5%

0_0402_5%

+1.8V

12

PC601

1 2

PR602

SSM3K7002FU_SC70-3

1 2

PR604

3

12

PC602

@10U_0805_10V4Z

PQ601

13

2

G

12

PC606
@0.1U_0402_16V7K

2

PU601

VIN1VCNTL

2

0.1U_0402_16V7K

PC604

GND

3

VREF

4

VOUT

S IC RT9173DPSP SO 8P

12

PC605
10U_0805_6.3V6M

12

PR601

1K_0402_1%

12

PR603

D

1K_0402_1%

S

12

+0.9VP

6

5

NC

7

NC

8

NC

9

TP

12

PC603
1U_0603_16V6K

+5VALW

1

PJP601

B B

+0.9VP

A A

5

1 2

PAD-OPEN 3x3m

(2A,80mils ,Via NO.= 4)

+0.9V

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2006/11/23 2007/11/23

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

0.9VP

Montevina Consumer Discrete

1

41 46Wednesday, February 18, 2009

0.1

5

4

3

2

1

+5VS

7

7

32

CPU_VID57CPU_VID37CPU_VID4

D D

PR201 499_0402_1%

DPRSLPVR9,22

H_DPRSTP#7, 9,21

CLK_ENABLE#17

PR206 0_0402_5%

12

PR216

PR215

@499_0402_1%

+3VS

+3VS

1 2

VGATE17,22

H_PSI#7

PR221

1 2

C C

@0_0402_5%

PR226 13K_0402_1%

PR247

PR222 147K_0402_1%

1 2

VR_TT#

PC2150.022U_0603_25V7K

1 2

1 2

1 2

PC2161000P_0402_50V7K

PR228 13K_0402_1%

1 2

12

0_0402_5%

1 2

PR203 0_0402_5%

PR204 0_0402_5%

1 2

1 2

PC201

1U_0603_6.3V6M

1.91K_0402_1%

1

PSI#

2

3

4

5

6

7

8

9

10

11

12

1 2

1 2

12

46

47

48

49

3V3

GND

PGOOD

CLK_EN#

PSI#

PMON

RBIAS

VR_TT#

NTC

SOFT

S IC ISL6266AHRZ-T Q FN 48P PWM

OCSET

VW

COMP

FB

FB2

VDIFF13VSEN14RTN15DROOP16DFB17VO18VSUM19VIN20GND21VDD22ISEN223ISEN1

CPU_VID6

VR_ON

PR211

PR210

PR208

PR209

PR207

12

0_0402_5%

44

45

VR_ON

DPRSTP#

DPRSLPVR

12

12

12

12

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

43

PC218 1000P_0402_50V 7K

PR235 97.6K_0402 _1%

1 2

B B

PC222 100P_0402_50V8J

100_0402_1%

VCCSENSE7

270P_0402_50V7K

1 2

1 2

PR238

1 2

PR240 1K_0402_1%

VSSSENSE7

PC220

12

PC224 2200P_0402_50V 7K

1 2

VCC_PRM

PC226 330P_0603_50V 8

1 2

12

PC227
330P_0603_50V8

PC229 180P_0402_50V 8J

1 2

PR243 1K_0402_1%

PC231

0.22U_0603_10V7K

12

PR237

1K_0402_1%

1 2

1 2

PR244 3.57K_0402 _1%

12

PC228
1000P_0603_50V7K

PC230 0.1U_0402 _16V7K

1 2

PC232 0.22U_040 2_6.3V6K

12

12

12

PC225

0.1U_0603_25V7K

12

PR242

11K_0402_1%

7

CPU_VID07CPU_VID17CPU_VID2

PR205

PR213

PR212

12

12

12

0_0402_5%

0_0402_5%

0_0402_5%

VID037VID138VID239VID340VID441VID542VID6

BOOT1

UGATE1

PHASE1

PGND1

LGATE1

PVCC

LGATE2

PGND2

PHASE2

UGATE2

BOOT2

NC

24

1 2

12

PR234 1_0603_5%
PC221
1U_0402_6.3V6K

PR239

10_0603_5%

1 2

VSUM

12

PR241

2.61K_0402_1%
10KB_0603_5%_ERTJ1VR 103J

PH201

1 2

36

35

34

33

32

31

30

29

28

27

26

25

PU201

ISEN1
ISEN2

0.022U_0402_16V7K

BOOT_CPU1

UGATE_CPU1-1

PHASE_CPU1

LGATE_CPU1

LGATE_CPU2

PHASE_CPU2

UGATE_CPU2-1

BOOT_CPU2

1 2

PR227

2.2_0603_5%

+5VS

CPU_B+

12

PC202

2.2_0603_5%
PR214

1 2

1 2

0_0603_5%

PR217

PR225

1 2

0_0603_5%

1 2

PC217

0.22U_0603_10V7K

PR202
1_0603_5%

1 2

12

PC203

2.2U_0603_6.3V6K

IRF8714TRPBF 1N SO8

0.22U_0603_10V7K
PC209

1 2

TPCA8036-H 1N SO P-ADV

IRF8714TRPBF 1N SO8

PQ201

UGATE_CPU1-2

PQ203

PQ204

UGATE_CPU2-2

PQ206

TPCA8036-H 1N SO P-ADV

578

3 6

3 5

578

12

12

PC242

470P_0402_50V7K

12

PC233

PC234

4.7U_0805_25V6-K

4.7U_0805_25V6-K

241

0.36UH +-20% PC MC104T-R36MN1R17

12

12

PR245

PR218

2.2_1206_5%

12

@4.7_1206_5%

241

PC210

680P_0603_50V7K

12

PC241

3 6

241

12

PR229

2.2_1206_5%

12

3 5

241

12

PR219

3.65K_0805_1%

VSUM

12

PC213

PC212

2200P_0402_50V7K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

12

PR246

12

PR230

@4.7_1206_5%

3.65K_0805_1%

PC219

VSUM

680P_0603_50V7K

CPU_B+

12

12

12

PC206

PC205

4.7U_0805_25V6-K

PC207

4.7U_0805_25V6-K
2200P_0402_50V7K

PL202

PR224

@0_0603_5%

1 2

PC211

1 2

12

12

VCC_PRM

12

PR220

10K_0402_1%

ISEN1

0.22U_0603_10V7K

12

12

12

12

PC235

PC214

0.36UH +-20% PC MC104T-R36MN1R17

PC236

1000P_0402_50V7K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

12

PL203

12

PR231

10K_0402_1%

PR233 @0_0603_5%

1 2

PC223

1 2

0.22U_0603_10V7K

ISEN2

PL201

SMB3025500YA_2P

12

PC237

1000P_0402_50V7K

PR223

1_0402_5%

12

PC238

2200P_0402_50V7K

12

PR232

1_0402_5%

VCC_PRM

12

PC243

@47P_0402_50V8J

PC244

47P_0402_50V8J

CPU_B+

PC245

47P_0402_50V8J

1

12

1

+

+

100U_25V_M

PC204

PC239

@100U_25V_M

2

2

+VCC_CORE

12

<BOM Structure>

12

<BOM Structure>

B+

12

12

PC208

PC240

@1000P_0402_50V7K

@2200P_0402_50V7K

A A

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

3

2

+CPU_CORE

Size Document Numb er Rev

Custom

Date: Sheet of

42 46Wednesday, February 18, 2009

1

0.1

A

Version Change List ( P. I. R. List ) for Power Circuit

Version Change List ( P. I. R. List ) for Power Circuit

Version Change List ( P. I. R. List ) for Power CircuitVersion Change List ( P. I. R. List ) for Power Circuit

Request

Request

Page#

Page#

Item

Page#Page#

ItemItem

1 1

2 2

Title

Title

TitleTitle

Date

Date

DateDate

RequestRequest
Owner

Owner

OwnerOwner

B

Issue DescriptionItem

Issue DescriptionIssue Description

C

Solution Description

Solution Description

Solution DescriptionSolution Description

D

E

Rev.

Rev.Issue Description

Rev.Rev.

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2007/08/02 2008/08/02

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet of

Compal Electronics, Inc.

Power Changed-List History-1

LA-4111P

43 46Wednesday, February 18, 2009

E

0.1

5

4

3

2

1

Item (Reason for change)Fixed Issue PAGE Modify List Date

17

CardReader clock issue Using USB_0 for CLK_48M_CR

CardReader clock issueCardReader clock issue

1

Debug Card issue

Debug Card issue 26

Debug Card issueDebug Card issue

2

SMT issue

SMT issue

SMT issueSMT issue

3

D D

Add Audio board Add JAUDIO for audio board

Add Audio boardAdd Audio board

4

SW2 is for DB1 debug

SW2 is for DB1 debug

SW2 is for DB1 debugSW2 is for DB1 debug

5

Cap board issue

Cap board issue

Cap board issueCap board issue

6

Support GM47 Add C1503 for GM47

Support GM47Support GM47

7

Change FAN control circuit to voltage control 2008/10/08

Change FAN control circuit to voltage controlChange FAN control circuit to voltage control

8

Delete HDA SSC Remove U8 for layout spacing

Delete HDA SSCDelete HDA SSC

9

For PR mini card connector Add R1225 -- R1236

For PR mini card connectorFor PR mini card connector

10

PA/PR CardReader LED D54 for PA, D64 for PR

PA/PR CardReader LEDPA/PR CardReader LED

11

C C

EMI request Change R1132 to bead

EMI requestEMI request

12

Use audio board Add audio board connector, change MIC to 2pin and add SPK connector

Use audio boardUse audio board

13

Change JFPR to 6 pin connector Add Q109, C1518, R1210

Change JFPR to 6 pin connectorChange JFPR to 6 pin connector

14

EMI request Add C1512 -- C1517

EMI requestEMI request

15

Change JFPR to 4 pin connector Delete Q109, C1518, R1210

Change JFPR to 4 pin connectorChange JFPR to 4 pin connector

16

Delete resistor for Debug card Delete R1220-R1224

Delete resistor for Debug cardDelete resistor for Debug card

17

EMI request 2008/11/21

EMI requestEMI request

18

For Intel DPST Add R1237,R1238

For Intel DPSTFor Intel DPST

19

B B

EMI and WWAN request

EMI and WWAN requestEMI and WWAN request

20

Audio board connector

Audio board connector 29

Audio board connectorAudio board connector

21

ST and Parade level shift Add R for Parade

ST and Parade level shiftST and Parade level shift

22

ESD request Add C1518,D65,D66,D67

ESD requestESD request

23

ESD/ EMI request

ESD/ EMI request

ESD/ EMI requestESD/ EMI request

24

AUDIO issue

AUDIO issueAUDIO issue

25

PC Beep issue

PC Beep issue 28

PC Beep issuePC Beep issue

26

17CardReader clock issue

1717

26

2626

29

29

2929

29

29Add Audio board

2929

33

33

3333

33

33

3333

13

13Support GM47

1313

6666Change FAN control circuit to voltage control

21

21Delete HDA SSC

2121

26

26For PR mini card connector

2626

27

27PA/PR CardReader LED

2727

28

28EMI request

2828

29

29Use audio board

2929

30

30Change JFPR to 6 pin connector

3030

35

35EMI request

3535

30Change JFPR to 4 pin connector

3030

26

26Delete resistor for Debug card

2626

35

35 Delete C1516,C1517 and connect to GND

3535

19

19For Intel DPST

1919

17

17

1717
21

2121
28

28

2828

29 Change pin define

2929

34

34ST and Parade level shift

3434

33ESD request

3333

17

17

25

25

1717

2525

18

32

32

1818

3232

30

30

3030

29AUDIO issue

2929

28 change to analog GND and add separate diode

2828

Using USB_0 for CLK_48M_CR 2008/10/08

Using USB_0 for CLK_48M_CRUsing USB_0 for CLK_48M_CR

Connect PLT_RST# to JP7.A17

Connect PLT_RST# to JP7.A17

Connect PLT_RST# to JP7.A17Connect PLT_RST# to JP7.A17

Change IR1 to SCR00000E00

Change IR1 to SCR00000E00

Change IR1 to SCR00000E00Change IR1 to SCR00000E00

Add JAUDIO for audio board

Add JAUDIO for audio boardAdd JAUDIO for audio board

Delete SW2

Delete SW2

Delete SW2Delete SW2

Change Cap board power rail to +3VL

Change Cap board power rail to +3VL

Change Cap board power rail to +3VLChange Cap board power rail to +3VL

Add C1503 for GM47 2008/10/08

Add C1503 for GM47Add C1503 for GM47

Add U51,D63

Add U51,D63Add U51,D63

Remove U8 for layout spacing 2008/10/08

Remove U8 for layout spacingRemove U8 for layout spacing

Add R1225 -- R1236 2008/10/08

Add R1225 -- R1236Add R1225 -- R1236

D54 for PA, D64 for PR 2008/10/08

D54 for PA, D64 for PRD54 for PA, D64 for PR

Change R1132 to bead 2008/10/08

Change R1132 to beadChange R1132 to bead

Add audio board connector, change MIC to 2pin and add SPK connector 2008/10/08

Add audio board connector, change MIC to 2pin and add SPK connectorAdd audio board connector, change MIC to 2pin and add SPK connector

Add Q109, C1518, R1210 2008/10/08

Add Q109, C1518, R1210Add Q109, C1518, R1210

Add C1512 -- C1517 2008/10/08

Add C1512 -- C1517Add C1512 -- C1517

Delete Q109, C1518, R1210

Delete Q109, C1518, R1210Delete Q109, C1518, R1210

Delete R1220-R1224 2008/11/21

Delete R1220-R1224Delete R1220-R1224

Delete C1516,C1517 and connect to GNDEMI request

Delete C1516,C1517 and connect to GNDDelete C1516,C1517 and connect to GND

Add R1237,R1238 2008/11/25

Add R1237,R1238Add R1237,R1238

Install C217, C218, C219, C435, C312, C316, C66, C67, C1478, C1479, C1480, C1481, D58, C1516, R1239, C327

Install C217, C218, C219, C435, C312, C316, C66, C67, C1478, C1479, C1480, C1481, D58, C1516, R1239, C32721

Install C217, C218, C219, C435, C312, C316, C66, C67, C1478, C1479, C1480, C1481, D58, C1516, R1239, C327Install C217, C218, C219, C435, C312, C316, C66, C67, C1478, C1479, C1480, C1481, D58, C1516, R1239, C327

Change pin define

Change pin defineChange pin define

Add R for Parade

Add R for ParadeAdd R for Parade

Add C1518,D65,D66,D67

Add C1518,D65,D66,D67Add C1518,D65,D66,D67

C217-C219, D5-D7, D45-D47, D20, C792-C815 no stuff

C217-C219, D5-D7, D45-D47, D20, C792-C815 no stuff18

C217-C219, D5-D7, D45-D47, D20, C792-C815 no stuffC217-C219, D5-D7, D45-D47, D20, C792-C815 no stuff

C1446, C1447 change to 0805 size

C1446, C1447 change to 0805 size29

C1446, C1447 change to 0805 sizeC1446, C1447 change to 0805 size

change to analog GND and add separate diode

change to analog GND and add separate diodechange to analog GND and add separate diode

2008/10/08 SI-1

2008/10/082008/10/08

2008/10/08

2008/10/08 SI-1

2008/10/082008/10/08

2008/10/08

2008/10/08

2008/10/082008/10/08

2008/10/08

2008/10/08

2008/10/082008/10/08

2008/10/08

2008/10/08 SI-1

2008/10/082008/10/08

2008/10/08

2008/10/08 SI-1

2008/10/082008/10/08

2008/10/08 SI-1

2008/10/082008/10/08

2008/10/08 SI-1

2008/10/082008/10/08

2008/10/08 SI-1

2008/10/082008/10/08

2008/10/08 SI-1

2008/10/082008/10/08

2008/10/08 SI-1

2008/10/082008/10/08

2008/10/08 SI-1

2008/10/082008/10/08

2008/10/08 SI-1

2008/10/082008/10/08

2008/10/08 SI-1

2008/10/082008/10/08

2008/10/08 SI-1

2008/10/082008/10/08

2008/11/2130

2008/11/212008/11/21

2008/11/21 SI-R

2008/11/212008/11/21

2008/11/21 SI-R

2008/11/212008/11/21

2008/11/25 SI-R

2008/11/252008/11/25

2008/12/18

2008/12/18 PV-1

2008/12/182008/12/18

2008/12/18

2008/12/18

2008/12/182008/12/18

2008/12/18

2008/12/18

2008/12/182008/12/18

2008/1/19

2008/1/19 MV-1

2008/1/192008/1/19

2008/2/13

2008/2/13 MV-1

2008/2/132008/2/13

2008/2/13

2008/2/13 MV-1

2008/2/132008/2/13

2008/2/13

2008/2/13 MV-1

2008/2/132008/2/13

Phase

SI-1

SI-1SI-1

SI-1

SI-1SI-1

SI-1

SI-1

SI-1SI-1

SI-1

SI-1

SI-1SI-1

SI-1

SI-1SI-1

SI-1

SI-1SI-1

SI-1

SI-1SI-1

SI-1Add U51,D63

SI-1SI-1

SI-1

SI-1SI-1

SI-1

SI-1SI-1

SI-1

SI-1SI-1

SI-1

SI-1SI-1

SI-1

SI-1SI-1

SI-1

SI-1SI-1

SI-1

SI-1SI-1

SI-R

SI-R2008/11/21

SI-RSI-R

SI-R

SI-RSI-R

SI-R

SI-RSI-R

SI-R

SI-RSI-R

PV-1EMI and WWAN request

PV-1PV-1

PV-1

PV-1

PV-1PV-1

PV-1

PV-1

PV-1PV-1

MV-133

MV-1MV-1

MV-1

MV-1MV-1

MV-1

MV-1MV-1

MV-1

MV-1MV-1

27

A A

28

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet of

Compal Electronics, Inc.

PIR

Montevina UMA

1

44 46Wednesday, February 18, 2009

0.1

5

4

3

2

1

Item (Reason for change)Fixed Issue PAGE Modify List Date

Phase

29

30

31

D D

32

33

34

35

36

37

38

39

C C

40

41

42

43

44

45

46

47

B B

48

49

50

51

52

53

54

55

A A

56

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet of

Compal Electronics, Inc.

PIR 2

Montevina UMA

1

45 46Wednesday, February 18, 2009

0.1

5

4

3

2

1

Item (Reason for change)Fixed Issue PAGE Modify List Date

Phase

57

58

59

D D

60

61

62

63

64

65

66

67

C C

68

69

70

71

72

73

74

75

B B

76

77

78

79

80

81

82

83

A A

84

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2007/08/28 2006/07/26

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet of

Compal Electronics, Inc.

HW PIR 3

Montevina UMA

1

46 46Wednesday, February 18, 2009

0.1