HP CHROMEBOOK 14-X Schematics

5

www.schematic-x.blogspot.com

4

3

2

1

Baileys Tegra5 Logan Platform Block Diagram

D D

WLAN/BT

SDIO

Marvell 88w8897

PG.15

eMMC 16GB

SDMMC4

SDIN8DE4-16G

PG.22

Memory 2G DDR3L-1600

DDR3L

4PCs 4Gb(x16)

G.10 11

P

G.26

P

PG.16

USB3.0 port 0

USB2.0 port 0

USB2.0 port 1

PG.18

12Mhz

I2C

Interrupts

SDMMC3

C C

TPM

Infineon SLB9645TT1.2FW

USB 3.0 Conn

(Lefe side)

USB Camera

PG.12

B B

Micro SD

USB2.0 Hub

1 to 4

GL850G-OHG31

NVIDIA Logan

23 x 23 mm

eDP 1ch

I2C

Interrupts

I2S(DAP2) Gen1_I2C

HDMI

SPI

I2C

Interrupts

eDP panel

PG.12

Thermal Sensor

TI TMP451

Maxim

MAX98090

Speaker

PG.20

HDMI conn

P

G.14

SPI ROM

4MB

PG.22

KBC

ST STM32L100RBT6

PG.27

KBC recover/reset

Silego SLG4K4215VTR

PG.27

Touch Pad

PG.16

PG.19

KB

PG.24

MGRL / GMRLAudio Codec

audio headset switch

TI

TS3A225E_RTE

PG.28

PG.20

1

Touch Panel

SIM Card

A A

WWAN

Huawei ME936 or ME206 module

USB 2.0 * 2

Conn

(Right side)

Daughter Board

5

USB 2.0 port 2

4

PG.2~9

12Mhz

3

ELAN 3915

SERVO DEBUG CONN

PG.24

2

PG.21

PROJECT : Baileys

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev Custom

Custom

NB5

NB5 HW

HW

Block Diagram

Date: Sheet of

1

1A

1 41Tuesday, June 10, 2014

CD580M: CH0 MEMORY I/F

2

U18E

GA

B

DDR_DQ[0..31]10

BYTE 0

BYTE 2

BYTE 1

BYTE 3

DDR_DQS0P10 DDR_DQS0N10

DDR_DM010

DDR_DQS2P10 DDR_DQS2N10

DDR_DM210

DDR_DQS1P10 DDR_DQS1N10

DDR_DM110

DDR_DQS3P10 DDR_DQS3N10

DDR_DM310

0 1 2 3 4 5 6 7

16 17 18 19 20 21 22 23

8

9 10 11 12 13 14 15

24 25 26 27 28 29 30 31

DDR_DQ0 DDR_DQ1 DDR_DQ2 DDR_DQ3 DDR_DQ4 DDR_DQ5 DDR_DQ6 DDR_DQ7

DDR_DQ16 DDR_DQ17 DDR_DQ18 DDR_DQ19 DDR_DQ20 DDR_DQ21 DDR_DQ22 DDR_DQ23

DDR_DQ8 DDR_DQ9 DDR_DQ10 DDR_DQ11 DDR_DQ12 DDR_DQ13 DDR_DQ14 DDR_DQ15

DDR_DQ24 DDR_DQ25 DDR_DQ26 DDR_DQ27 DDR_DQ28 DDR_DQ29 DDR_DQ30 DDR_DQ31

DDR_DQS0P DDR_DQS0N DDR_DM0

DDR_DQS2P DDR_DQS2N DDR_DM2

DDR_DQS1P DDR_DQS1N DDR_DM1

DDR_DQS3P DDR_DQS3N DDR_DM3

D11 A11 E11 B11 F11 G12 A10 H12

H11 G11 C11

B5 B2 A5 C2 B3 C3 A4 A3

E9 A9 G8 C9 E8 F9 F8 D9

B8 C6 A8 A6 F6 D6 A7 E6

C5 D5 C1

G9 H9 B9

C8 D8

B6

DDR_DQ0 DDR_DQ1 DDR_DQ2 DDR_DQ3 DDR_DQ4 DDR_DQ5 DDR_DQ6 DDR_DQ7

DDR_DQ8 DDR_DQ9 DDR_DQ10 DDR_DQ11 DDR_DQ12 DDR_DQ13 DDR_DQ14 DDR_DQ15

DDR_DQ16 DDR_DQ17 DDR_DQ18 DDR_DQ19 DDR_DQ20 DDR_DQ21 DDR_DQ22 DDR_DQ23

DDR_DQ24 DDR_DQ25 DDR_DQ26 DDR_DQ27 DDR_DQ28 DDR_DQ29 DDR_DQ30 DDR_DQ31

DDR_DQS0P DDR_DQS0N DDR_DM0

DDR_DQS1P DDR_DQS1N DDR_DM1

DDR_DQS2P DDR_DQS2N DDR_DM2

DDR_DQS3P DDR_DQS3N DDR_DM3

I5

CD580M

SEC 5 OF 8

DDR_CLK

DDR_CLK_N

DDR_CLKB

DDR_CLKB_N

DDR_A0 DDR_A1 DDR_A2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9

DDR_A10 DDR_A11 DDR_A12 DDR_A13 DDR_A14 DDR_A15

DDR_A_B3 DDR_A_B4 DDR_A_B5

DDR_BA0 DDR_BA1 DDR_BA2

DDR_CAS_N DDR_RAS_N

DDR_WE_N

DDR_RESET_N

DDR_CS0_N DDR_CS1_N

DDR_CS_B0_N DDR_CS_B1_N

DDR_CKE0 DDR_CKE1

DDR_CKE_B0 DDR_CKE_B1

DDR_ODT0 DDR_ODT1

DDR_ODT_B0 DDR_ODT_B1

G14 H14

H18 G18

C14 D12 E14 G15 E12 D14 B12 F14 C12 F12

H15 D20 F18 D18 C20 A16

G17 E20 H17

E17 E18 F17

C15 D15 E15

F15 A12

B14 A19

A18

A13 A14

A20 B20

A15 B15

C18 B18

PLACE <100 MILS FROM TEGRA

C228 2.2p/50V_4

C226 2.2p/50V_4

DDR_A0 DDR_A1 DDR_A2 DDR_AA3 DDR_AA4 DDR_AA5 DDR_A6 DDR_A7 DDR_A8 DDR_A9

DDR_A10 DDR_A11 DDR_A12 DDR_A13 DDR_A14 DDR_A15

DDR_AA13 DDR_AA14 DDR_AA15

DDR_BA0 DDR_BA1 DDR_BA2

DDR_CAS_L DDR_RAS_L

DDR_WE_L DDR_RESET

DDR0_CS0_L DDR0_CS1_L

DDR1_CS0_L DDR1_CS1_L

DDR0_CKE0 DDR0_CKE1

DDR1_CKE0 DDR1_CKE1

DDR0_ODT0 DDR0_ODT1

DDR1_ODT0 DDR1_ODT1

DDR_A[0:15] 10,11

DDR_BA0 10,11 DDR_BA1 10,11 DDR_BA2 10,11

DDR_CAS_L 10,11 DDR_RAS_L 10,11

DDR_WE_L 10,11

DDR_RESET 10,11

DDR0_CS0_L 10 DDR0_CS1_L 10

DDR1_CS0_L 11 DDR1_CS1_L 11

DDR0_CKE0 10 DDR0_CKE1 10

DDR1_CKE0 11 DDR1_CKE1 11

DDR0_ODT0 10 DDR0_ODT1 10

DDR1_ODT0 11 DDR1_ODT1 11

DDR_AA[5:3] 10

DDR_AA1[5:3] 11

R227

45.3/F_4

R228

45.3/F_4

R234

45.3/F_4

DDR1_CLK_TERM DDR0_CLK_TERM

C189

0.01uF/10V_2

PLACE AT "T" BRANCH

GNDGND

DDR0_CLKP DDR0_CLKN

DDR1_CLKP DDR1_CLKN

R233

45.3/F_4

C199

0.01uF/10V_2

DDR0_CLKP 10 DDR0_CLKN 10

DDR1_CLKP 11 DDR1_CLKN 11

NB5

NB5 HW

HW

PROJECT : Baileys

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev Custom

Custom

Custom Date: Sheet of

Date: Sheet of

CH0 MEMORY I_F

layout

2 41Tuesday, June 10, 2014

1A

3

CD580M: CH1 MEMORY I/F

+1.35V_LP0

R243 R010_8

+1.35V_LP0_VDDIO_DDR_AP

+1.05V_RUN_AVDD

C220

2.2U/6.3V_4

C37

2.2U/6.3V_4

C241 1uF_2

+1.05V_RUN_AVDD

C230

10uF/6.3V_4

C217

10uF/6.3V_4

C244

10uF/6.3V_4

C216

4.7UF_4

C218

4.7UF_4

C223 *4.7UF_4

U18F

GA

B

DDR_DQ[32..63]11

DDR_DQ32

BYTE 4

BYTE 6

BYTE 5

BYTE 7

DDR_DQS4P11

DDR_DQS4N11

DDR_DM411

DDR_DQS6P11 DDR_DQS6N11

DDR_DM611

DDR_DQS5P11 DDR_DQS5N11

DDR_DM511

DDR_DQS7P11 DDR_DQS7N11

+1.35V_LP0_VDDIO_DDR_AP3,41

DDR_DM711

R244 34_4

DDR_DQ33 DDR_DQ34 DDR_DQ35 DDR_DQ36 DDR_DQ37 DDR_DQ38 DDR_DQ39

DDR_DQ48 DDR_DQ49 DDR_DQ50 DDR_DQ51 DDR_DQ52 DDR_DQ53 DDR_DQ54 DDR_DQ55

DDR_DQ40 DDR_DQ41 DDR_DQ42 DDR_DQ43 DDR_DQ44 DDR_DQ45 DDR_DQ46 DDR_DQ47

DDR_DQ56 DDR_DQ57 DDR_DQ58 DDR_DQ59 DDR_DQ60 DDR_DQ61 DDR_DQ62 DDR_DQ63

DDR_DQS4P DDR_DQS4N DDR_DM4

DDR_DQS6P DDR_DQS6N DDR_DM6

DDR_DQS5P DDR_DQS5N DDR_DM5

DDR_DQS7P DDR_DQS7N DDR_DM7

DDR_COMP_PU+1.35V_LP0_VDDIO_DDR_AP DDR_COMP_PD

R52 34_4

E21 B21 G21 A21 G20 D21 F20 C21

B26 C24 A26 A24 E26 D24 E27 A25

B23 G23 A23 H23 C23 F24 A22 E24

C31 C27 C30 A27 C29 D27 A29 A28

H21 H20 F21

C26 D26 B24

E23 D23 F23

B30 B29 B27

C17 D17

DDR_DQ32 DDR_DQ33 DDR_DQ34 DDR_DQ35 DDR_DQ36 DDR_DQ37 DDR_DQ38 DDR_DQ39

DDR_DQ40 DDR_DQ41 DDR_DQ42 DDR_DQ43 DDR_DQ44 DDR_DQ45 DDR_DQ46 DDR_DQ47

DDR_DQ48 DDR_DQ49 DDR_DQ50 DDR_DQ51 DDR_DQ52 DDR_DQ53 DDR_DQ54 DDR_DQ55

DDR_DQ56 DDR_DQ57 DDR_DQ58 DDR_DQ59 DDR_DQ60 DDR_DQ61 DDR_DQ62 DDR_DQ63

DDR_DQS4P DDR_DQS4N DDR_DM4

DDR_DQS5P DDR_DQS5N DDR_DM5

DDR_DQS6P DDR_DQS6N DDR_DM6

DDR_DQS7P DDR_DQS7N DDR_DM7

DDR_COMP_PU DDR_COMP_PD

I18

CD580M

SEC 6 OF 8

(1.05V)

AVDD_PLL_APC2C3

VDDIO_DDR_HS

(1.2 - 1.5V)

VDDIO_DDR 10

VDDIO_DDR_MCLK

AVDD_PLL_M

VDDIO_DDR 1 VDDIO_DDR 2 VDDIO_DDR 3 VDDIO_DDR 4 VDDIO_DDR 5 VDDIO_DDR 6 VDDIO_DDR 7 VDDIO_DDR 8 VDDIO_DDR 9

K16 B17

A17

J9 J12 J14 J11 J17 J18 J20 J21 K10 K11

J15

C222

0.1uF_2

C38

0.1uF_2

C242 1uF_2

+1.35V_LP0_VDDIO_DDR_AP

C237

C219

1uF_2

*4.7UF_4

NB5

NB5 HW

HW

+1.35V_LP0_VDDIO_DDR_AP 3,41

C238

0.1uF_2

Size Document Number Rev

Size Document Number Rev Custom

Custom

Custom Date: Sheet of

Date: Sheet of

C235

C229

0.1uF_2

C236

C239

1uF_2

PROJECT : Baileys

Quanta Computer Inc.

CH1 MEMORY I_F

3 41Tuesday, June 10, 2014

1A

+1.8V_VDDIO

C258

4.7UF_4

0.1uF_2

+1.8V_VDDIO

+VDDIO_SDMMC3

R245

33.2/F_4

R246

33.2/F_4

R248

33.2/F_4

+VDDIO_SDMMC3

C225

4.7UF_4

+1.8V_VDDIO

C253

4.7UF_4

C224

0.1uF_2

PV Modified 0606

SDMMC3_COMP_PU/PD change from 49.9 ohm to 33ohm Improve SDR104 mode performance

AC14

AF15 AH15 AD17

AJ15

AJ18 AH17

AK18

AL17

AK17

AL18 AG15

AL16

AF17

AE17

AE15

AJ17 AG17

AD15

P9

L2 L3 L1 J8 L7 L8 L5

J7 L6

K1

L4

E1

H2 H1 F1

G1

F5 F2

V24

F4 F3 E2 E5

F31

F29 F30 E28 H31 D31 E30 E29 F28 G31 E31

H30 H29

U18A

GA

B

(1.8V-3.3V)

VDDIO_BB

ULPI_DATA0 ULPI_DATA1 ULPI_DATA2 ULPI_DATA3 ULPI_DATA4 ULPI_DATA5 ULPI_DATA6 ULPI_DATA7

ULPI_CLK ULPI_DIR ULPI_NXT ULPI_STP

DAP3_DIN DAP3_DOUT DAP3_FS

DAP3_SCLK

GPIO_PV0 GPIO_PV1

(1.8V-3.3V)

VDDIO_SDMMC1

SDMMC1_DAT0 SDMMC1_DAT1 SDMMC1_DAT2 SDMMC1_DAT3

SDMMC1_CLK SDMMC1_CMD SDMMC1_WP_N

SDMMC1_COMP_PU SDMMC1_COMP_PD

CLK2_OUT CLK2_REQ

(1.8V-3.3V)

VDDIO_SDMMC3

SDMMC3_DAT0 SDMMC3_DAT1 SDMMC3_DAT2 SDMMC3_DAT3

SDMMC3_CLK SDMMC3_CMD SDMMC3_CD_N SDMMC3_CLK_LB_OUT SDMMC3_CLK_LB_IN SDMMC3_COMP_PU SDMMC3_COMP_PD

(1.2V-1.8V)

VDDIO_SDMMC4

SDMMC4_DAT0 SDMMC4_DAT1 SDMMC4_DAT2 SDMMC4_DAT3 SDMMC4_DAT4 SDMMC4_DAT5 SDMMC4_DAT6 SDMMC4_DAT7

SDMMC4_CLK SDMMC4_CMD

SDMMC4_COMP_PU SDMMC4_COMP_PD

*I23

CD580M

SEC 1 OF 8

(1.8V-3.3V)

VDDIO_SYS

VDDIO_SYS_2

(0.9-1.1V)

PWR_I2C_SCL

PWR_I2C_SDA

CORE_PWR_REQ

CPU_PWR_REQ

CLK_32K_IN

CLK_32K_OUT

PWR_INT_N

SYS_RESET_N

RESET_OUT_N

THERM_DP

THERM_DN

(1.8V)

JTAG_RTCK

JTAG_TRST_N

TEST_MODE_EN

(1.8V - 3.3V)

AVDD_OSC

KB_COL0 KB_COL1 KB_COL2 KB_COL3 KB_COL4 KB_COL5 KB_COL6 KB_COL7

KB_ROW0 KB_ROW1 KB_ROW2 KB_ROW3 KB_ROW4 KB_ROW5 KB_ROW6 KB_ROW7 KB_ROW8

KB_ROW9 KB_ROW10 KB_ROW11 KB_ROW12 KB_ROW13 KB_ROW14 KB_ROW15 KB_ROW16 KB_ROW17

VDD_RTC

OWR

VPP_FUSE

JTAG_TCK

JTAG_TDI JTAG_TDO JTAG_TMS

XTAL_IN

XTAL_OUT

V23 L10

AD30

ONKEY_L

AC28

HOLD_R

AD28

SERVO_DBG_GPIO

AD31

BD_ID_STRAP0

AF28

SDMMC3_WP_L

AA27 AD29

GOOG_DEV_MODE

AA25

GOOG_RECOVERY_MODE

W31

EN_VDD_SD

Y26

AP_WP_L

AF30 AC31 Y29

LID_CLOSED_L LID_OPEN

Y31 AB31 Y30

HEAD_DET_L

AA29 AA28

BR_UART1_TXD

AA31

BR_UART1_RXD

V28

AP_MDEM_RESET_L

Y27

MODEM_ENMODEM_WAKE_AP

AF29 AC30 Y25

IGPU_PWRGD

AA26 AC29

BD_ID_STRAP1

R275 10K_2

TP14

GOOG_DEV_MODE 21 GOOG_RECOVERY_MODE 21

EN_VDD_SD 32 AP_WP_L 22

D19 RB501V-40

2 1

BR_UART1_TXD 21,26 BR_UART1_RXD 21

AP_MDEM_RESET_L 26

IGPU_PWRGD 33 BD_ID_STRAP1 23

AB12

J4 J3

Y28 V25

CLK_32KHZ_PMU

H3

J6

V30 AA30 Y24

CPU_OC_INT

PMU_INT_L

SYS_RESET_L

RESET_OUT_L

CLK_32KHZ_PMU 33

CPU_OC_INT 33

PMU_INT_L 33 SYS_RESET_L 16,21,22,33

AA7 U28

U29 R10

J2 H6 H5 J1 J5 H4

H7

D1 E3 E4

THERMD_P THERMD_N

JTAG_RTCK JTAG_TCK_AP JTAG_TDI JTAG_TDO JTAG_TMS_AP JTAG_TRSTR_L

TEST_MODE_EN

R247 0_4

R62 *0_4/S

R76 *0_4

R74

R58

100K_2

10K_2

THERMD_P 16

THERMD_N 16

R63 *0_4/S

+1.8V_VDDIO

KBC_SPI_MOSI27

KBC_SPI_MISO27 KBC_SPI_SCK27 KBC_SPI_CS27

EN_VDD_BL13

+1.8V_VDDIO

KBC_SPI_MOSI KBC_SPI_MISO KBC_SPI_SCK KBC_SPI_CS

EN_VDD_BL

C305

4.7UF_4

C301

0.1uF_2

MODEM_WAKE_AP26 MODEM_EN 26

SDMMC1_CLK15

SDMMC1_CMD15

SD_MMC1_DAT[3..0]15

R249

33.2/F_4

SDMMC1_CLK SDMMC1_CMD

SDMMC1_COMP_PU SDMMC1_COMP_PD

SD_MMC1_DAT0 SD_MMC1_DAT1 SD_MMC1_DAT2 SD_MMC1_DAT3

TO BE FIXED IN FAB

C232

0.1uF_2

*0_4/S R192

SD_MMC4_DAT[7..0]22

SDMMC4_CLK22 SDMMC4_CMD22

SDMMC3_CLK26

SD_MMC3_DAT[3..0]26

SDMMC3_CMD26

SDMMC3_CD21,26

C335 *22pF_2

SI Modified 0418

+1.8V_VDDIO

R84

49.9/F_2

SDMMC4_CLK SDMMC4_CMD

SD_MMC3_DAT0 SD_MMC3_DAT1 SD_MMC3_DAT2 SD_MMC3_DAT3

SDMMC3_CLK SDMMC3_CMD SDMMC3_CD

SDMMC3_CLK_LB_OUT SDMMC3_CLK_LB_IN SDMMC3_COMP_PU SDMMC3_COMP_PD

SD_MMC4_DAT0 SD_MMC4_DAT1 SD_MMC4_DAT2 SD_MMC4_DAT3 SD_MMC4_DAT4 SD_MMC4_DAT5 SD_MMC4_DAT6 SD_MMC4_DAT7

R296 *0_2/S

SI Modified 0418

SDMMC4_COMP_PU SDMMC4_COMP_PD

R81

49.9/F_2

R295 0_2

SI Modified 0418

ONKEY_L 23 HOLD_R 27 SERVO_DBG_GPIO 21 BD_ID_STRAP0 23

GND

VIL=0.45

R109 *0_4/S

PWR_I2C_SCL PWR_I2C_SDA

CORE_PWR_REQ CPU_PWR_REQ

+1.8V_RUN_VPP_FUSE

JTAG_RTCK 21 JTAG_TCK 21,27 JTAG_TDI 21

JTAG_TDO 21

JTAG_TMS 21,27 JTAG_TRST_L 21

MIC_PRSNT_L

+1.00V_LP0_VDD_RTC

+1.8V_VDDIO

C294

0.1uF_2

+1.8V_VDDIO

R117 *100K/F_4

R118 *0_4

R254 10K_2

XTAL_OUT

C46

18p/50V/C0G_4

+1.8V_VDDIO

C269

4.7UF_4

C255

4.7UF_4

C270

0.1uF_2

C252

0.1uF_2

LID_OPEN 21,27,29

MIC_PRSNT_L 20

+1.00V_LP0_VDD_RTC

R65

R64

1K/F_4C256

1K/F_4

PMIC_WARM_RESET_L

+1.8V_RUN_VPP_FUSE

C264

0.1uF_2

+1.8V_LP0_AVDD_OSC_AP_F

R77 2M_2

Y2

1 2

TITLE

XTAL 12MHZ

S

I Modified 0418

GND GND

R106 *100K_2

XTAL_IN

34

PWR_I2C_SCL 33 PWR_I2C_SDA 33

CORE_PWR_REQ 21,27,33,35 CPU_PWR_REQ 21,35

R266 *100K_2

PMIC_WARM_RESET_L 6,27,33

+1.8V_VDDIO

L25

BLM15PX330SN1D(33,3000MA)_4

SI Modified 0418

C221

4.7UF_4

C47 18p/50V/C0G_4

4

PROJECT : Baileys

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev Custom

Custom

NB5

NB5 HW

HW

Date: Sheet of

SDMMC_ULPI_JTAG

1A

4

41Tuesday, June 10, 2014

+1.8V_VDDIO

C311

4.7UF_4

C307

0.1uF_2

TPM_I2C_SCL16

TPM_I2C_SDA16

+1.2V_GEN_AVDD

CAD NOTE: PLACE NEAR TEGRA

C313

4.7UF_4

C314

0.1uF_2

TPM_I2C_SCL TPM_I2C_SDA

R273 *0_4

R153 *1K/F_4

HSIC_REXT

AK14

AL13 AL14

AK9 AE9

AD9 AE11 AD11

AK8

AH9

AH8

AG9 AK11

AL11 AD14 AE14

AL15 AK15 AG14

AF14

AJ14 AH14

AH12

AJ12 AE12 AD12

AL12 AK12

AF12 AG12

AJ11 AH11

AL10

AF11 AG11

AC11

AK5 AK6 AH6 AH5

AG8

AC15

AF18 AE18 AH18

AG18

AD18

AL9

AL8 AJ9

AJ8 AF9

AJ6 AL7

AL6 AJ5

AF8

AL5

U18B

GA

B

(1.2V)

AVDD_DSI_CSI 1 AVDD_DSI_CSI 2 AVDD_DSI_CSI 3

CSI_A_D0_N CSI_A_D0_P CSI_A_D1_N CSI_A_D1_P

CSI_A_CLK_N

CSI_A_CLK_P

CSI_B_D0_N CSI_B_D0_P CSI_B_D1_N CSI_B_D1_P

CSI_E_CLK_N CSI_E_CLK_P CSI_E_D0_N CSI_E_D0_P

DSI_A_D0_N DSI_A_D0_P DSI_A_D1_N DSI_A_D1_P DSI_A_D2_N DSI_A_D2_P DSI_A_D3_N DSI_A_D3_P

DSI_A_CLK_N DSI_A_CLK_P

DSI_B_D0_N DSI_B_D0_P DSI_B_D1_N DSI_B_D1_P DSI_B_D2_N DSI_B_D2_P DSI_B_D3_N DSI_B_D3_P

DSI_B_CLK_N DSI_B_CLK_P

CSI_DSI_TEST_OUT CSI_DSI_RUP CSI_DSI_RDN

(1.8V - 3.3V)

VDDIO_CAM

GPIO_PCC1 GPIO_PCC2 GPIO_PBB0 GPIO_PBB3 GPIO_PBB4 GPIO_PBB5 GPIO_PBB6 GPIO_PBB7

CAM_I2C_SCL CAM_I2C_SDA

CAM_MCLK

(1.2V)

VDDIO_HSIC

HSIC1_DATA HSIC_STROBE HSIC_REXT

HSIC2_DATA HSIC2_STROBE

I85

CD580M

SEC 2 OF 8

(1.05V.. 1.2V?)

AVDD_HDMI_PLL

HDMI_TXD0N

HDMI_TXD1N

HDMI_TXD2N

HDMI_PROBE

(1.05V)

AVDD_LVDS0_IO

(1.05V)

AVDD_PLL_UD2DPD

(1.8V)

AVDD_LVDS0_PLL

LVDS0_TXD0N LVDS0_TXD0P LVDS0_TXD1N LVDS0_TXD1P LVDS0_TXD2N LVDS0_TXD2P LVDS0_TXD3N LVDS0_TXD3P LVDS0_TXD4N LVDS0_TXD4P

LVDS0_PROBE

DP_AUX_CH0_P DP_AUX_CH0_N

(1.8V)

AVDD_PLL_UTMIP

(3.3V)

USB_VBUS_EN0 USB_VBUS_EN1

(3.3V)

AVDD_HDMI AVDD_HDMI

HDMI_TXD0P

HDMI_TXD1P

HDMI_TXD2P

HDMI_TXCN

HDMI_TXCP

HDMI_CEC

HDMI_INT

HDMI_RSET

DDC_SCL DDC_SDA

DP_HPD

LVDS0_RSET

AVDD_USB

USB0_DN USB0_DP USB1_DN USB1_DP USB2_DN USB2_DP

USB0_VBUS

USB0_ID

USB_REXT

AA9 AA10

AH1

AD5 AD6 AD4 AD3 AD2 AD1 AF5 AF6

AD7 AC3 AF2 AE1

AC7 AC8

AJ1

AL4

AF1

AJ2 AJ3 AG3 AG4 AG5 AG6 AG1 AG2 AF3 AF4

AC2 AK3 AL3

AC6 AC5

AB15

AC12

AH20 AJ20 AF20 AG20 AE20 AD20

AB1 AC1

AL20 AK20 AL19

+3.3V_AVDD_HDMI_AP_GATED

C299

0.1uF_2

+1.05V_RUN_AVDD_HDMI_PLL_AP_GATE

C72

0.1uF_2

HDMI_TXD_0N HDMI_TXD_0P HDMI_TXD_1N HDMI_TXD_1P HDMI_TXD_2N HDMI_TXD_2P HDMI_TXC_N HDMI_TXC_P

HDMI_CEC HDMI_INT

R46 R39

+1.05V_RUN_AVDD

DP_TXD1_N DP_TXD1_P DP_TXD0_N DP_TXD0_P

EDP_HPD

DP_AUX_P DP_AUX_N

+1.8V_RUN_AVDD_PLL_UTMIP_AP_F

USB0D_N

USB0D_P HUB_USBD_N HUB_USBD_P

USB2D_N

USB2D_P

USB_VBUS_EN0 USB_VBUS_EN1

USB_REXT

R149 1K/F_4

33_4 33_4

C321

0.1uF_2

DP_TXD1_N 12 DP_TXD1_P 12 DP_TXD0_N 12 DP_TXD0_P 12

EDP_HPD 12

DP_AUX_P 12 DP_AUX_N 12

USB0D_N 17 USB0D_P 17 HUB_USBD_N 18 HUB_USBD_P 18 USB2D_N 26 USB2D_P 26

USB_VBUS_EN0 17 USB_VBUS_EN1 26

+3.3V_AVDD_HDMI_AP_GATED

C283

4.7UF_4

+1.05V_RUN_AVDD_HDMI_PLL_AP_GATE

C73

2.2U/6.3V_4

HDMI_TXD_0N 14 HDMI_TXD_0P 14 HDMI_TXD_1N 14 HDMI_TXD_1P 14 HDMI_TXD_2N 14 HDMI_TXD_2P 14 HDMI_TXC_N 14 HDMI_TXC_P 14

HDMI_CEC 14

HDMI_INT 14,21

HDMI_DDC_SCLHDMI_DDC_SCL_AP HDMI_DDC_SDAHDMI_DDC_SDA_AP

+1.05V_RUN_AVDD

C318

2.2U/6.3V_4

+AVDD_LVDS0_PLL_AP_F

NOTE: CH3 USED FOR LVDS

LVDS_RSET

USB0_VBUS_AP

R148 1K/F_4

C303

0.1uF_2

+3.3V_LP0

HDMI_DDC_SCL 14

HDMI_DDC_SDA 14

C316

0.1uF_2

C308

4.7UF_4

C319

0.1uF_2

C295

0.1uF_2

+3.3V_LP0

HDMI_REST

+1.05V_RUN_AVDD

C320

2.2U/6.3V_4

BLM15PX330SN1D(33,3000MA)_4

SI Modified 0418

C317

4.7UF_4

LVDS TO EDP MUX

LVDS EDP

CH0 CH1 CH2 CH3

BLM15PX330SN1D(33,3000MA)_4

SI Modified 0418

C322

4.7UF_4

R278 *0_4/S

L28

3.3V FOR DP MODE

CH2 CH1 CH0

--CH3CH4

L27

+1.8V_VDDIO_LP0_OFF32

+1.05V_RUN_AVDD

+3.3V_RUN

+3.3V_LP06,7,12,14,15,17,18,24,26,32,34,41

+3.3V_RUN6,9,12,16,22,28,32,34,41

+1.2V_GEN_AVDD19,34,41

+1.8V_VDDIO4,6,10,12,13,15,16,19,20,21,22,23,24,26,27,32,33,34,35,41

R151 1K/F_4

+1.8V_VDDIO_LP0_OFF

5

+3.3V_LP0

+3.3V_RUN

+1.2V_GEN_AVDD

+1.8V_VDDIO_LP0_OFF

+1.8V_VDDIO

PROJECT : Baileys

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev Custom

Custom

NB5

NB5 HW

HW

Date: Sheet of

CSI_DSI_HDMI_USB

1A

5 41Tuesday, June 10, 2014

+1.8V_VDDIO

+3.3V_SYS

C243

4.7UF_4

R9322/J_4

DAP2_SCLK

+3.3V_SYS

+3.3V_LP0

+1.8V_VDDIO

C227

0.1uF_2

C60 *4.7pF_4

+3.3V_LP0

+1.8V_VDDIO

EC_IN_RW27 WF_WAKE_L15 BT_IRQ_L15

DAP2_DIN19 DAP2_DOUT19 DAP2_FS19

EN_VDD_HDMI9,14

R10022/J_4

+3.3V_SYS12,13,18,22,31,32,34

+3.3V_LP05,7,12,14,15,17,18,24,26,32,34,41

+1.8V_VDDIO

R86

R83

1K/F_4

DAP2_SCLK19

GEN1_I2C_SCL GEN1_I2C_SDA

+1.8V_VDDIO

GEN1_I2C_SCL16,19

GEN1_I2C_SDA16,19

DAP_MCLK119

SI Modified 0418

DAP_MCLK1

C61

10P/50V_4

C276

4.7UF_4

DAP_MCLK1_L

DAP2_SCLK_R

EC_IN_RW WF_WAKE_L BT_IRQ_L

DAP2_DIN DAP2_DOUT DAP2_FS

EN_VDD_HDMI

C275

0.1uF_2

M10

M31

M29

AA8 AC4

U10

K31

H28

P31

R30

L9 M8 M1

P4

M3 M2

R8

R9

P3

P5

P1

N1

P7 M7

R7

P2

P8 M9 M4 M5

P6 M6

L28 J28

L29

L30 J29

U18C

GA

B

(1.8V-3.3V)

VDDIO_UART

UART2_RXD UART2_TXD UART2_CTS_N UART2_RTS_N

UART3_RXD UART3_TXD UART3_CTS_N UART3_RTS_N

DAP4_DIN DAP4_DOUT DAP4_FS

DAP4_SCLK

CLK3_OUT CLK3_REQ

GPIO_PU0 GPIO_PU1 GPIO_PU2 GPIO_PU3 GPIO_PU4 GPIO_PU5 GPIO_PU6

GEN1_I2C_SCL GEN1_I2C_SDA

(1.8V-3.3V)

VDDIO_AUDIO

DAP1_DIN DAP1_DOUT DAP1_FS

DAP1_SCLK

DAP_MCLK1 DAP_MCLK1_REQ

DAP2_DIN DAP2_DOUT DAP2_FS

DAP2_SCLK

SPDIF_IN SPDIF_OUT

I190

CD580M

SEC 3 OF 8

(2.8V-3.3V)

VDDIO_HV

(1.8V-3.3V)

VDDIO_GMI 1 VDDIO_GMI 2

GPIO_PB0 GPIO_PB1 GPIO_PC7 GPIO_PG0 GPIO_PG1 GPIO_PG2 GPIO_PG3 GPIO_PG4 GPIO_PG5 GPIO_PG6 GPIO_PG7 GPIO_PH0 GPIO_PH1 GPIO_PH2 GPIO_PH3 GPIO_PH4 GPIO_PH5 GPIO_PH6 GPIO_PH7

GPIO_PI0 GPIO_PI1 GPIO_PI2 GPIO_PI3 GPIO_PI4 GPIO_PI5 GPIO_PI6

GPIO_PI7 GPIO_PJ0 GPIO_PJ2 GPIO_PJ7

GPIO_PK0 GPIO_PK1 GPIO_PK2 GPIO_PK3 GPIO_PK4 GPIO_PK7

GEN2_I2C_SCL GEN2_I2C_SDA

SDMMC2_COMP_PU SDMMC2_COMP_PD

GPIO_X1_AUD GPIO_X3_AUD GPIO_X4_AUD GPIO_X5_AUD GPIO_X6_AUD

GPIO_X7_AUD GPIO_W2_AUD GPIO_W3_AUD

DVFS_PWM

DVFS_CLK

Y10

U9 V10

U4 V9 U1 V2 V6 Y7 AA5 Y3 AA3 Y8 V3 Y6 U3 AA4 V8 R5 R4 U8 U2 Y5 AA6 V1 V7 Y9 U7 R1 Y4 U6 W1 V4 AA1 R3 Y1 R2 T1 V5

Y2 AA2

U5 R6

P29 M30 R28 R31 N31 P28 M28 J30

P30 R29

KBC_IRQ_L BOOT_SEL0 BOOT_SEL1

BOOT_SEL2

BOOT_SEL3 RAM_CODE0 SPI4_SCK SPI4_MOSI SPI4_MISO

LCD_BL_PWM LCD_BL_EN

CODEC_IRQ_L

TPM_DAVINT_L GPIO_PH7 GPIO_PI0 AP_FORCE_RECOVERY_L

SPI4_CS0_L

SOC_WARM_RESET_L TEMP_ALERT_L

HDSET_SW_SOCR_L

AC_OK_AP_L

ARM_JTAG0

MODEM_PWR_RPT TS_SHDN_L TS_IRQ_L

TS_RESET_L

ARM_JTAG1

BD_ID_STRAP2

BD_ID_STRAP3

MODEM_SAR0

WF_EN

TOUCH_IRQ_L

DVFS_PWM DVFS_CLK

+3.3V_LP0

C297

4.7UF_4

C282

0.1uF_2

KBC_IRQ_L 27

BOOT_SEL0 23 BOOT_SEL1 23

BOOT_SEL2 23

BOOT_SEL3 23 RAM_CODE0 10 SPI4_SCK 10,22 SPI4_MOSI 10,22

SPI4_MISO 10,22

LCD_BL_PWM 13 LCD_BL_EN 13

CODEC_IRQ_L 19

TPM_DAVINT_L 16 GPIO_PH7 9 GPIO_PI0 23

AP_FORCE_RECOVERY_L 23

SPI4_CS0_L 22

TEMP_ALERT_L 16

ARM_JTAG0 23 MODEM_PWR_RPT 26

TS_SHDN_L 12 TS_IRQ_L 12

TS_RESET_L 12 ARM_JTAG1 23

BD_ID_STRAP2 23 BD_ID_STRAP3 23

MODEM_SAR0 26 WF_EN 15

TOUCH_IRQ_L 24

DVFS_PWM 35 DVFS_CLK 35

SHARE DECOUPLING

WITH VDDIO_UART

STRAPS

+1.8V_VDDIO

R257 *100K/F_4

R263 51_4

POR L POR H

+3.3V_RUN

R95 1K/F_4

SET E_OD PAD = 1 WHEN PU VALUE DIFFERS FROM VDD SOURCE

PMIC_WARM_RESET_L

R92 *0_4/S

R94 1K/F_4

GEN2_I2C_SCL_3.3V

GEN2_I2C_SDA_3.3V

+1.8V_VDDIO

HDSET_SW_SOC_L

3

2

AC_OK

Q8

DMN601WK

1

6

PMIC_WARM_RESET_L 4,27,33

HDSET_SW_SOC_L 20

AC_OK 30,33

C39

12

*Clamp-Diode

GEN2_I2C_SCL_3.3V 12,24 GEN2_I2C_SDA_3.3V 12,24

NB5

NB5 HW

HW

PROJECT : Baileys

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev Custom

Custom

Custom Date: Sheet of

Date: Sheet of

UART_GMI_DAP_SPI

6 41Tuesday, June 10, 2014

1A

AF31

AK30

AH31

AL27

AK27

AJ27

AH27

AG27

AF27

AL25

U18D

GA

B

(3.3V)

HVDD_SATA

(1.05V)

VDDIO_SATA

(1.05V)

AVDD_SATA_PLL

SATA_L0_TXP SATA_L0_TXN SATA_L0_RXP SATA_L0_RXN

SATA_TESTCLKP SATA_TESTCLKN SATA_TERMP

CD580M

SEC 4 OF 8

(1.05V)

AVDDIO_PEX AVDDIO_PEX AVDDIO_PEX

(1.05V)

DVDDIO_PEX DVDDIO_PEX DVDDIO_PEX

(3.3V)

HVDD_PEX_PLL_E

(3.3V)

HVDD_PEX

(1.05V)

AVDD_PEX_PLL

(1.05V)

AVDD_PLL_EREFE

(1.05V)

AVDD_PLL_X

AVDD_PLL_CG

AB17 AC17 AC18

AB20 AC20 AB18

AL28 AL29

AC21

AG31

L31 J31

C298

0.1uF_2

C323

0.1uF_2

C302

0.1uF_2

C310 1U/6.3V_4

+1.05V_RUN

C304

4.7UF_4

+3.3V_LP0

C324

4.7UF_4

+1.05V_RUN_AVDD_PEX_PLL_AP_F

C309

4.7UF_4

+1.2V_GEN_AVDD5,19,34,41

+3.3V_LP05,6,12,14,15,17,18,24,26,32,34,41

L26

BLM15PX330SN1D(33,3000MA)_4

SI Modified 0418

+1.05V_RUN_AVDD

C315

0.1uF_2

+1.05V_RUN

C312

2.2U/6.3V_4

+1.2V_GEN_AVDD

+1.05V_RUN

+1.05V_RUN_AVDD

+3.3V_LP0

+1.2V_GEN_AVDD

+3.3V_LP0

7

+1.05V_RUN_AVDD

C267

0.1uF_2

C265

2.2U/6.3V_4

AD27 AD25

AB22 AD24

AD23 AD26 AC23 AC24 AC25

AA24

P10

U24 U23 U31 V31 V26 V29

H27 F26

F27

U30 H25 H26

K25

J25

J27 J24

J26

(1.05V)

AVDD_PLL_C4

DIRECTDC_CLK DIRECTDC_IN DIRECTDC_OUT0 DIRECTDC_OUT1 DIRECTDC_OUT2 DIRECTDC_OUT3

NC 1 NC 2 NC 3 NC 4 NC 5 NC 6 NC 7 NC 8 NC 9 NC 10 NC 11 NC 12 NC 13 NC 14 NC 15 NC 16 NC 17 NC 18 NC 19 NC 20 NC 21

I405

USB3_TX0N USB3_TX0P USB3_RX0N

USB3_RX0P PEX_USB3_TX1N PEX_USB3_TX1P PEX_USB3_RX1N PEX_USB3_RX1P

PEX_TX2N PEX_TX2P PEX_RX2N PEX_RX2P

PEX_TX3N PEX_TX3P PEX_RX3N PEX_RX3P

PEX_TX4N PEX_TX4P PEX_RX4N PEX_RX4P

PEX_CLK1P

PEX_CLK1N

PEX_CLK2P

PEX_CLK2N

PEX_REFCLKP PEX_REFCLKN

PEX_TESTCLKN PEX_TESTCLKP

PEX_TERMP

(1.8V - 3.3V)

VDDIO_PEX_CTL

PEX_L0_RST_N

PEX_L1_RST_N PEX_L0_CLKREQ_N PEX_L1_CLKREQ_N

PEX_WAKE_N

GPIO_PFF2

USB_VBUS_EN2

AJ21 AH21 AL21 AK21 AG21 AF21 AL23 AK23 AJ23 AH23 AE21 AD21

AG23 AF23 AK24 AL24

AH26 AJ26 AL26 AK26

AF26 AG26

AC26 AC27

AH24 AJ24

AF24 AG24 AL22

AE31

AJ29 AJ31 AK29 AJ30

AG28 AG30

AG29

USBSS_TX0_N USBSS_TX0_P

USBSS_RX0_N

USBSS_RX0_P

PEX_TERMP

USBSS_TX0_N 17 USBSS_TX0_P 17

R150

2.49K/F_4

USBSS_RX0_N 17 USBSS_RX0_P 17

C234

0.1uF_2

NB5

NB5 HW

HW

C56

2.2U/6.3V_4

PROJECT : Baileys

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev Custom

Custom

Custom Date: Sheet of

Date: Sheet of

SATA,USB 3.0,PEX

7 41Tuesday, June 10, 2014

1A

8

C284

10uF/6.3V_4

C277

10uF/6.3V_4

C254 *0.1uF_2

+VDD_GPU_AP36,41

+VDD_CPU_AP37,41

+VDD_CORE

C281

4.7UF_4

C285

C287

4.7UF_4

+VDD_CPU_AP

C248 *0.1uF_2

C262

4.7UF_4

+VDD_CPU_AP

MAY BE NEEDED FOR MIN VR LOADING

C286

4.7UF_4

C257

4.7UF_4

+VDD_CPU_AP

C261 1uF_2

C233 10uF/6.3V_4

C245

4.7UF_4

+VDD_GPU_AP

R253 *10K/F_4

C240

0.1uF_2

C288

4.7UF_4

C247 1uF_2

C250 10uF/6.3V_4

C231

4.7UF_4

R274 *10K/F_4

C251

4.7UF_4

C289

4.7UF_4

C246 1uF_2

C259

4.7UF_4

C263

4.7UF_4

+VDD_CORE

R270 *10K/F_4

C266

4.7UF_4

C292

4.7UF_4

C260 1uF_2

C249

4.7UF_4

AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA22

K12 K14 K15 K17 K18 K20 K21 M12 N12 P12 R12 T12 U12 V12

W12

Y12 Y22

R23

M13 M14 M15 M16 M17 M18 M19 M20 M22 M23 M24 M25 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 N25 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 R17 R18 R19 R20 R21 R22

M26 M27

P23

L23 L24

L25 L26

L27

U18G

GA

B

VDD_CORE 1 VDD_CORE 2 VDD_CORE 3 VDD_CORE 4 VDD_CORE 5 VDD_CORE 6 VDD_CORE 7 VDD_CORE 8 VDD_CORE 9 VDD_CORE 10 VDD_CORE 11 VDD_CORE 12 VDD_CORE 13 VDD_CORE 14 VDD_CORE 15 VDD_CORE 16 VDD_CORE 17 VDD_CORE 18 VDD_CORE 19 VDD_CORE 20 VDD_CORE 21 VDD_CORE 22 VDD_CORE 23 VDD_CORE 24 VDD_CORE 25

VDD_CPU 1 VDD_CPU 2 VDD_CPU 3 VDD_CPU 4 VDD_CPU 5 VDD_CPU 6 VDD_CPU 7 VDD_CPU 8 VDD_CPU 9 VDD_CPU 10 VDD_CPU 11 VDD_CPU 12 VDD_CPU 13 VDD_CPU 14 VDD_CPU 15 VDD_CPU 16 VDD_CPU 17 VDD_CPU 18 VDD_CPU 19 VDD_CPU 20 VDD_CPU 21 VDD_CPU 22 VDD_CPU 23 VDD_CPU 24 VDD_CPU 25 VDD_CPU 26 VDD_CPU 27 VDD_CPU 28 VDD_CPU 29 VDD_CPU 30 VDD_CPU 31 VDD_CPU 32 VDD_CPU 33 VDD_CPU 34 VDD_CPU 35 VDD_CPU 36 VDD_CPU 37 VDD_CPU 38 VDD_CPU 39 VDD_CPU 40 VDD_CPU 41 VDD_CPU 42 VDD_CPU 43 VDD_CPU 44 VDD_CPU 45 VDD_CPU 46 VDD_CPU 47 VDD_CPU 48

I185

CD580M

SEC 7 OF 8

VDD_GPU 1 VDD_GPU 2 VDD_GPU 3 VDD_GPU 4 VDD_GPU 5 VDD_GPU 6 VDD_GPU 7 VDD_GPU 8

VDD_GPU 9 VDD_GPU 10 VDD_GPU 11 VDD_GPU 12 VDD_GPU 13 VDD_GPU 14 VDD_GPU 15 VDD_GPU 16 VDD_GPU 17 VDD_GPU 18 VDD_GPU 19 VDD_GPU 20 VDD_GPU 21 VDD_GPU 22 VDD_GPU 23 VDD_GPU 24 VDD_GPU 25 VDD_GPU 26 VDD_GPU 27

VDD_GPU_SENSE

VVDD_GPU_PROBE

GND_GPU_SENSE

VDD_CPU_SENSE

VVDD_CPU_PROBE

GND_CPU_SENSE

VDD_CORE_SENSE

VVDD_CORE_PROBE

GND_CORE_SENSE

AA23 U17 U18 U19 U20 V13 V14 V15 V16 V17 V18 V19 V20 W13 W14 W15 W16 W17 W18 W19 W20 W21 Y19 Y20 Y23 U21 V21

U26 U25 U27

R26 R25 R27

P25 P27 P26

C291 1uF_2

C279

4.7UF_4

VVDD_GPU_PROBE

VVDD_CORE_PROBE

C272 1uF_2

C293

4.7UF_4

VVDD_CPU_PROBE

C273 1uF_2

C290

4.7UF_4

R255 *0_4

R265 *0_4

R261 *0_4

C306

4.7UF_4

C300

4.7UF_4

+VDD_GPU_AP

C280

10uF/6.3V_4

C268

4.7UF_4

VDD_GPU_SENSE_P VDD_GPU_SENSE_N

VDD_CPU_SENSE_P VDD_CPU_SENSE_N

VDD_CORE_SENSE_P VDD_CORE_SENSE_N

+VDD_GPU_AP

C274

10uF/6.3V_4

C271

4.7UF_4

VDD_GPU_SENSE_P 35 VDD_GPU_SENSE_N 35

VDD_CPU_SENSE_P 35 VDD_CPU_SENSE_N 35

VDD_CORE_SENSE_P 35 VDD_CORE_SENSE_N 35

Size Document Number Rev

Size Document Number Rev Custom

Custom

NB5

NB5 HW

HW

Custom Date: Sheet of

Date: Sheet of

C296

C278

4.7UF_4

PROJECT : Baileys

Quanta Computer Inc.

POWER RAILS

8 41Tuesday, June 10, 2014

1A

AB21

N10 N11 N28

AB25

N30 P11 R11 R13 R14 R15 R16

AB28

AB30

U11 U13 U14 U15 U16 AC9 U22 V11 V22

W10 W11 W22 W25

AD8 W28 W30

AK2

AE8

AB11 AB14

P24

R24

V27

AE23

AE2

AE4

AE7

AE10 AE13

U18H

GA

B

CD580M

GND 1 GND 10 GND 100 GND 101 GND 102 GND 103 GND 104 GND 105 GND 106 GND 107 GND 108 GND 109 GND 11 GND 110 GND 111 GND 112 GND 113 GND 114 GND 115 GND 116 GND 117 GND 118 GND 119 GND 12 GND 120 GND 121 GND 122 GND 123 GND 124 GND 125 GND 126 GND 127 GND 128 GND 129 GND 13 GND 130 GND 131 GND 132 GND 133 GND 134 GND 135 GND 136 GND 137 GND 138 GND 139 GND 14 GND 140 GND 141 GND 142 GND 143 GND 144 GND 145 GND 146 GND 147 GND 148 GND 149 GND 15 GND 150 GND 151 GND 152 GND 153 GND 154 GND 155 GND 156 GND 157 GND 158 GND 159 GND 160 GND 161 GND 162 GND 163 GND 164 GND 165 GND 166 GND 167 GND 16 GND 17 GND 18 GND 19 GND 2 GND 20 GND 96 GND 97 GND 98 GND 99

I103

SEC 8 OF 8

GND 21 GND 22 GND 23 GND 24 GND 25 GND 26 GND 27 GND 28 GND 29

GND 3 GND 30 GND 31 GND 32 GND 33 GND 34 GND 35 GND 36 GND 37 GND 38 GND 39

GND 4 GND 40 GND 41 GND 42 GND 43 GND 44 GND 45 GND 46 GND 47 GND 48 GND 49

GND 5 GND 50 GND 51 GND 52 GND 53 GND 54 GND 55 GND 56 GND 57 GND 58 GND 59

GND 6 GND 60 GND 61 GND 62 GND 63 GND 64 GND 65 GND 66 GND 67 GND 68 GND 69

GND 7 GND 70 GND 71 GND 72 GND 73 GND 74 GND 75 GND 76 GND 77 GND 78 GND 79

GND 8 GND 80 GND 81 GND 82 GND 83 GND 84 GND 85 GND 86 GND 87 GND 88 GND 89

GND 9 GND 90 GND 91 GND 92 GND 93 GND 94 GND 95

AE16 AE19 AE22 AE28 AE30 AH2 AH4 AH7 AH10 AB2 AH13 AH16 AH19 AH22 AH25 AH28 AH30 AK1 AK4 AK7 AB4 AK10 AK13 AK16 AK19 AK22 AK25 AK28 AK31 AL2 AL30 AB7 B1 B4 B7 B10 B13 B16 B19 B22 B25 B28 AB10 B31 D2 D4 D7 D10 D13 D16 D19 D22 D25 AB13 D28 D30 G2 G4 G7 G10 G13 G16 G19 G22 AB16 G24 G25 G28 G30 H8 H24 J23 K2 K4 K7 AB19 K13 AE24 K19 K22 AE25 K28

+1.05V_RUN_AVDD_HDMI_PLL_AP_GATE

P-MOSFET TO POWER GATE AVDD_HDMI_PLL

P-MOSFET TO PREVENT BACKDRIVE ON AVDD_HDMI

+3.3V_AVDD_HDMI_AP_GATED

ADD HEATSINK AND HEATSINK MOUNT HERE

A2

L16 L17 L18 L19

N2 N4 N7

T2 T4 T7

T10 T11 T13 T14 T15 T16 T17 T18 T19 T20

T21 T22 T25 T28 T30

W2 W4 W7

Y13 Y14 Y15 Y16 Y17 Y18

T31

L22

A30 K30

L13 L14 L15

P-MOSFET TO POWER GATE AVDD_HDMI_PLL

R181 *0_4

Q14

AO3413

3

2

3

Q15

VGTH(MAX)=0.9V

*DMG1012T-7(SOT523)

1

R174 1M_4

1

Q10 AO3413

2

3

DMG1012T-7(SOT523)

1

3

Q11

EN_AVDD_HDMI

2

VGTH(MAX)=0.9V

+3.3V_RUN

R185 *0_4

R180 0_4

SI Modified 0418

1

R188 1M_4

1.05V_RUN_AVDD_HDMI_PLL_AP_EN_L

2

EN_AVDD_HDMI_PLL EN_VDD_HDMI

R179 *0_4/S

R184 *0_4

EN_VDD_HDMI

+1.05V_RUN

R187 0_4

+1.2V_GEN_AVDD5,19,34,41

+3.3V_RUN5,6,12,16,22,28,32,34,41

EN_VDD_HDMI 6,9,14

+1.05V_RUN

GPIO_PH7

NB5

NB5 HW

HW

GPIO_PH7 6

EN_VDD_HDMI 6,9,14

+1.2V_GEN_AVDD

+3.3V_RUN

+1.05V_RUN

PROJECT : Baileys

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev Custom

Custom

Custom Date: Sheet of

Date: Sheet of

GND,HEATSPREADER

9

9 41Tuesday, June 10, 2014

1A

1

2

3

4

5

6

7

8

10

M_VREF_M1_DQ M_VREF_M1_CA

R239

5.49K/F_4

R230

5.49K/F_4

DDR_RESET 2,10,11DDR0_ODT12,10

DDR_DQ[0:31] 2,10

BYTE 1

BYTE 3

DDR_DQS3P 2 DDR_DQS1P 2 DDR_DQS3N 2 DDR_DQS1N 2

DDR_DM3 2 DDR_DM1 2

+VDDIO_DRAM+VDDIO_DRAM

R205

5.49K/F_4

R210

5.49K/F_4

R222 240R/F_2

DDR_DQ[0..31] 2,10

BYTE 0

B

YTE 2

DDR_DQS2P 2 DDR_DQS0P 2 DDR_DQS2N 2 DDR_DQS0N 2

DDR_DM2 2 DDR_DM0 2

DDR_RESET 2,10,11

+VDDIO_DRAM

GND

+VDDIO_DRAM

C156

4.7UF_4

GND

C192

0.1uF_2

C163

4.7UF_4

DDR_BA02,10,11 DDR_BA12,10,11 DDR_BA22,10,11

DDR0_CS0_L2,10

DDR0_CLKP2,10 DDR0_CLKN2,10 DDR0_CKE02,10 DDR_CAS_L2,10,11 DDR_RAS_L2,10,11 DDR_WE_L2,10,11

DDR0_ODT02,10

C212

0.1uF_2

C188

0.1uF_2

M_VREF_M1_DQ

C168

0.1uF_2

DDR_AA[5:3]2,10

C194

0.1uF_2

C214

0.1uF_2

DDR_A[0:15]2,10,11

DDR_A0 DDR_A1

DDR_A2 DDR_AA3 DDR_AA4 DDR_AA5

DDR_A6

DDR_A7

DDR_A8

DDR_A9

DDR_A10 DDR_A11 DDR_A12

DDR_A13 DDR_A14 DDR_A15

DDR_BA0 DDR_BA1 DDR_BA2 DDR0_CS0_L DDR0_CLKP DDR0_CLKN DDR0_CKE0 DDR_CAS_L DDR_RAS_L DDR_WE_L

DDR0_ODT0

C173

C203

0.1uF_2

C178

C206

0.1uF_2

R225

DDR0_ODT1 DDR0_CS1_L DDR0_CKE1

DDR0_ODT12,10

DDR0_CS1_L2,10

DDR0_CKE12,10

240R/F_2

U6

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

L2

CS#

J7

CK

K7

CK#

K9

CKE

K3

CAS#

J3

RAS#

L3

WE#

K1

ODT

B2

VDD#B2

D9

VDD#D9

G7

VDD#G7

K2

VDD#K2

K8

VDD#K8

N1

VDD#N1

N9

VDD#N9

R1

VDD#R1

R9

VDD#R9

A1

VDDQ#A1

A8

VDDQ#A8

C1

VDDQ#C1

C9

VDDQ#C9

D2

VDDQ#D2

E9

VDDQ#E9

F1

VDDQ#F1

H2

VDDQ#H2

H9

VDDQ#H9

H1

VREFDQ

M8

VREFCA

J1

NC#J1

L1

NC#L1

J9

NC#J9

L9

NC#L9

96-BALL

SDRAM DDR3

Memory-Down _DDRL3

AKD5JGETW07

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6

DQL7 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

DQSU

DQSL

DQSU#

DQSL#

DMU

DML

VSS#A9 VSS#B3 VSS#E1

VSS#G8

VSS#J2

VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9

VSS#T1

VSS#T9

VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8

VSSQ#F9 VSSQ#G1 VSSQ#G9

RESET#

E3

DDR_DQ8

F7

DDR_DQ9

F2

DDR_DQ10

F8

DDR_DQ11

H3

DDR_DQ12

H8

DDR_DQ13

G2

DDR_DQ14

H7

DDR_DQ15

D7

DDR_DQ24

C3

DDR_DQ25

C8

DDR_DQ26

C2

DDR_DQ27

A7

DDR_DQ28

A2

DDR_DQ29

B8

DDR_DQ30

A3

DDR_DQ31

C7

DDR_DQS3P

F3

DDR_DQS1P

B7

DDR_DQS3N

G3

DDR_DQS1N

D3

DDR_DM3

E7

DDR_DM1

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

T2

DDR_RESETDDR0_ODT1

L8

ZQ

R219 240R/F_2

DDR_A[0:15]2,10,11

DDR_A0

DDR_AA[5:3]2,10

A A

R240 R010_8

+VDDIO_DRAM

B B

C155

4.7UF_4

GND

+VDDIO_DRAM

C159

4.7UF_4

GND

C C

C171

0.1uF_2

+VDDIO_DRAM+1.35V_LP0

C177

0.1uF_2

C202

0.1uF_2

DDR_BA0 DDR_BA1 DDR_BA2 DDR0_CS0_L DDR0_CLKP DDR0_CLKN DDR0_CKE0 DDR_CAS_L DDR_RAS_L DDR_WE_L

DDR0_ODT0

R218

240R/F_2

DDR_BA02,10,11 DDR_BA12,10,11 DDR_BA22,10,11

DDR0_CS0_L2,10

DDR0_CLKP2,10 DDR0_CLKN2,10 DDR0_CKE02,10 DDR_CAS_L2,10,11 DDR_RAS_L2,10,11 DDR_WE_L2,10,11

DDR0_ODT02,10

C210

C184

0.1uF_2

C196

C182

0.1uF_2

M_VREF_M1_DQ M_VREF_M1_CA M_VREF_M1_CA

DDR0_CS1_L2,10

DDR0_CKE12,10

C166

0.1uF_2

DDR_A1

DDR_A2 DDR_AA3 DDR_AA4 DDR_AA5

DDR_A6

DDR_A7

DDR_A8

DDR_A9

DDR_A10 DDR_A11 DDR_A12

DDR_A13 DDR_A14 DDR_A15

C187

0.1uF_2

C209

0.1uF_2

DDR0_CS1_L DDR0_CKE1

DDR_ZQ1 DDR_ZQ3

D0 D1

U5

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

L2

CS#

J7

CK

K7

CK#

K9

CKE

K3

CAS#

J3

RAS#

L3

WE#

K1

ODT

B2

VDD#B2

D9

VDD#D9

G7

VDD#G7

K2

VDD#K2

K8

VDD#K8

N1

VDD#N1

N9

VDD#N9

R1

VDD#R1

R9

VDD#R9

A1

VDDQ#A1

A8

VDDQ#A8

C1

VDDQ#C1

C9

VDDQ#C9

D2

VDDQ#D2

E9

VDDQ#E9

F1

VDDQ#F1

H2

VDDQ#H2

H9

VDDQ#H9

H1

VREFDQ

M8

VREFCA

J1

NC#J1

L1

NC#L1

J9

NC#J9

L9

NC#L9

Memory-Down _DDRL3

96-BALL

SDRAM DDR3

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6

DQL7 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

DQSU

DQSL

DQSU#

DQSL#

DMU

DML

VSS#A9 VSS#B3 VSS#E1 VSS#G8 VSS#J2

VSS#J8 VSS#M1 VSS#M9

VSS#P1

VSS#P9

VSS#T1

VSS#T9

VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8 VSSQ#F9 VSSQ#G1 VSSQ#G9

RESET#

E3

DDR_DQ0

F7

DDR_DQ1

F2

DDR_DQ2

F8

DDR_DQ3

H3

DDR_DQ4

H8

DDR_DQ5

G2

DDR_DQ6

H7

DDR_DQ7

D7

DDR_DQ16

C3

DDR_DQ17

C8

DDR_DQ18

C2

DDR_DQ19

A7

DDR_DQ20

A2

DDR_DQ21

B8

DDR_DQ22

A3

DDR_DQ23

C7 F3 B7 G3

D3 E7

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

T2 L8

ZQ

DDR_DQS2P DDR_DQS0P DDR_DQS2N DDR_DQS0N

DDR_DM2 DDR_DM0

DDR_RESET

DDR_ZQ0 DDR_ZQ2

AKD5JGETW07

+1.8V_VDDIO

RAMCODE[3:0]

R281 *100K/F_4

R282 100K/F_4

R288 *100K/F_4

RAM_CODE0

RAM_CODE1

RAM_CODE2

RAM_CODE3

R287 100K/F_4

3

R267 *100K/F_4

RAM_CODE0 RAM_CODE1 RAM_CODE2 RAM_CODE3

D D

NOTE: RAM_CODE[1:0]:SELECTS SDRAM CONFIGURATION FROM BCT

RAM_CODE[3:2]:SELECTS SECONDARY BOOT DEVICE FROM BCT

1

2

R268 100K/F_4

R280 *100K/F_4

R279 100K/F_4

RAM CODE

RAM_CODE0

SPI4_SCK

SPI4_MOSI

SPI4_MISO

RAM_CODE0 6

SPI4_SCK 6,22 SPI4_MOSI 6,22 SPI4_MISO 6,22

4

0000 0001 0010 0011

RAMCODE[3:0]

1000 1001 1010 1011

5

TOPBSQ

AKD5JGST412 AKD5JGST413

TOPBSQ

AKD5FGSTL05 AKD5FGSTL06 AKD5QGST503

DDR3L 4Gb

QBCON

AKD5JGETW08AKD5JGETW07 AKD5JGSTL07AKD5JGSTL06

DDR3L 8Gb

QBCON

AKD5FGSTW05AKD5FGSTW04

AKD5QGST504

+1.35V_LP03,34,35,41

QCI PN HWVender PN

AKD5JGETW00 H5TC4G63AFR-PBA Hynix (default) AKD5JGSTL02 MT41K256M16HA-125:E Micron AKD5PGST500AKD5PGST508 AKD5PGST509 K4B4G1646Q-HYK0 Samsung AKD5JGST403 EDJ4216EFBG-GN-F

CI PN Vender PN

Q

AKD5FGSTW01 H5TC8G63AMR-PBA Hynix (default) AKD5FGSTL00 MT41K512M16TNA-125:E AKD5QGST502 K4B8G1646Q-MYK0 AKD5FGST402AKD5FGST409 AKD5FGST410 EDJ8416E6MB-GN-F

+1.35V_LP0

6

HUMA, A V80A/E

Q

F

1600MHz 1600MHz 1600MHz 1600MHz

FW SupplierHW

HUMA, A V80A/E

Q

F

Size Document Number Rev

Size Document Number Rev Custom

Custom

NB5

NB5 HW

HW

Date: Sheet of

7

1600MHz 1600MHz 1600MHz 1600MHz

PROJECT : Baileys

Quanta Computer Inc.

DDR3L SDRAM(A)

Elpida

Micron Samsung Elpida

8

SupplierFW

10 41Tuesday, June 10, 2014

1A

1

2

3

4

5

6

7

8

DDR_A[0:15]2,10,11 DDR_A[0:15]2,10,11

DDR_A0

C170

0.1uF_2

C200

0.1uF_2

DDR_A1

DDR_A2 DDR_AA13 DDR_AA14 DDR_AA15

DDR_A6

DDR_A7

DDR_A8

DDR_A9

DDR_A10 DDR_A11 DDR_A12

DDR_A13 DDR_A14 DDR_A15

DDR1_ODT1 DDR1_CS1_L DDR1_CKE1

DDR_ZQ5

DDR1_CS0_L2,11

C197

0.1uF_2

C165

0.1uF_2

DDR_AA1[5:3]2,11

DDR_BA02,10,11 DDR_BA12,10,11 DDR_BA22,10,11

DDR1_CLKP2,11 DDR1_CLKN2,11 DDR1_CKE02,11 DDR_CAS_L2,10,11 DDR_RAS_L2,10,11 DDR_WE_L2,10,11

DDR1_ODT02,11

C211

0.1uF_2

C191

0.1uF_2

DDR1_ODT12,11

DDR1_CS1_L2,11

DDR1_CKE12,11

DDR_BA0 DDR_BA1 DDR_BA2 DDR1_CS0_L DDR1_CLKP DDR1_CLKN DDR1_CKE0 DDR_CAS_L DDR_RAS_L DDR_WE_L

DDR1_ODT0

C205

0.1uF_2

C175

0.1uF_2

M_VREF_M2_DQ M_VREF_M2_CA

R216

240R/F_2

A A

+VDDIO_DRAM

B B

C160

4.7UF_4

GND

+VDDIO_DRAM

C207

C158

0.1uF_2

4.7UF_4

GND

C C

C185

0.1uF_2

D2 D3

U7

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

L2

CS#

J7

CK

K7

CK#

K9

CKE

K3

CAS#

J3

RAS#

L3

WE#

K1

ODT

B2

VDD#B2

D9

VDD#D9

G7

VDD#G7

K2

VDD#K2

K8

VDD#K8

N1

VDD#N1

N9

VDD#N9

R1

VDD#R1

R9

VDD#R9

A1

VDDQ#A1

A8

VDDQ#A8

C1

VDDQ#C1

C9

VDDQ#C9

D2

VDDQ#D2

E9

VDDQ#E9

F1

VDDQ#F1

H2

VDDQ#H2

H9

VDDQ#H9

H1

VREFDQ

M8

VREFCA

J1

NC#J1

L1

NC#L1

J9

NC#J9

L9

NC#L9

Memory-Down _DDRL3

96-BALL

SDRAM DDR3

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6

DQL7 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

DQSU

DQSL

DQSU#

DQSL#

DMU

DML

VSS#A9 VSS#B3 VSS#E1

VSS#G8

VSS#J2

VSS#J8 VSS#M1 VSS#M9

VSS#P1

VSS#P9

VSS#T1

VSS#T9

VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8 VSSQ#F9 VSSQ#G1 VSSQ#G9

RESET#

E3

DDR_DQ48

F7

DDR_DQ49

F2

DDR_DQ50

F8

DDR_DQ51

H3

DDR_DQ52

H8

DDR_DQ53

G2

DDR_DQ54

H7

DDR_DQ55

D7 C3 C8 C2 A7 A2 B8 A3

C7 F3 B7 G3

D3 E7

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

T2 L8

ZQ

DDR_DQ32 DDR_DQ33 DDR_DQ34 DDR_DQ35 DDR_DQ36 DDR_DQ37 DDR_DQ38 DDR_DQ39

DDR_DQS4P DDR_DQS6P DDR_DQS4N DDR_DQS6N

DDR_DM4 DDR_DM6

DDR_RESET DDR_RESET

AKD5JGETW07

+VDDIO_DRAM

DDR_DQ[32..63] 3,11 DDR_DQ[32..63] 3,11

DDR_A0

C201

0.1uF_2

C204

0.1uF_2

DDR_A1

DDR_A2 DDR_AA13 DDR_AA14 DDR_AA15

DDR_A6

DDR_A7

DDR_A8

DDR_A9

DDR_A10 DDR_A11 DDR_A12

DDR_A13 DDR_A14 DDR_A15

DDR_ZQ7

BYTE 6

DDR_AA1[5:3]2,11

BYTE 4

C179

0.1uF_2

DDR1_ODT12,11

DDR1_CS1_L2,11

DDR1_CKE12,11

C208

0.1uF_2

DDR_BA0 DDR_BA1 DDR_BA2 DDR1_CS0_L DDR1_CLKP DDR1_CLKN DDR1_CKE0 DDR_CAS_L DDR_RAS_L DDR_WE_L

DDR1_ODT0

R224

240R/F_2

DDR_DQS4P 3 DDR_DQS6P 3 DDR_DQS4N 3 DDR_DQS6N 3

DDR_DM4 3 DDR_DM6 3

+VDDIO_DRAM

C161

4.7UF_4

GND

+VDDIO_DRAM

C162

4.7UF_4

GND

DDR_RESET 2,10,11 DDR_RESET 2,10,11

C172

R221 240R/F_2

+VDDIO_DRAM

0.1uF_2

C198

0.1uF_2

C195

0.1uF_2

DDR_BA02,10,11 DDR_BA12,10,11 DDR_BA22,10,11

DDR1_CS0_L2,11

DDR1_CLKP2,11 DDR1_CLKN2,11 DDR1_CKE02,11 DDR_CAS_L2,10,11 DDR_RAS_L2,10,11 DDR_WE_L2,10,11

DDR1_ODT02,11

C167

0.1uF_2

C193

0.1uF_2

C213

0.1uF_2

M_VREF_M2_DQ M_VREF_M2_CA

N2

R8 R2

R3 R7

N7

M7

M2 N8 M3

D9 G7

N1 N9 R1 R9

C1 C9 D2

H2 H9

H1 M8

DDR1_ODT1 DDR1_CS1_L DDR1_CKE1

A0

P7

A1

P3

A2 A3

P8

A4

P2

A5 A6 A7

T8

A8 A9

L7

A10/AP A11 A12/BC

T3

A13

T7

A14 A15

BA0 BA1 BA2

L2

CS#

J7

CK

K7

CK#

K9

CKE

K3

CAS#

J3

RAS#

L3

WE#

K1

ODT

B2

VDD#B2 VDD#D9 VDD#G7

K2

VDD#K2

K8

VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9

A1

VDDQ#A1

A8

VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2

E9

VDDQ#E9

F1

VDDQ#F1 VDDQ#H2 VDDQ#H9

VREFDQ VREFCA

J1

NC#J1

L1

NC#L1

J9

NC#J9

L9

NC#L9

96-BALL

SDRAM DDR3

Memory-Down _DDRL3

AKD5JGETW07

U8

N3

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6

DQL7 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

DQSU

DQSL

DQSU#

DQSL#

DMU

DML

VSS#A9 VSS#B3 VSS#E1 VSS#G8

VSS#J2

VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9

VSS#T1

VSS#T9

VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8

VSSQ#F9 VSSQ#G1 VSSQ#G9

RESET#

E3

DDR_DQ56

F7

DDR_DQ57

F2

DDR_DQ58

F8

DDR_DQ59

H3

DDR_DQ60

H8

DDR_DQ61

G2

DDR_DQ62

H7

DDR_DQ63

D7

DDR_DQ40

C3

DDR_DQ41

C8

DDR_DQ42

C2

DDR_DQ43

A7

DDR_DQ44

A2

DDR_DQ45

B8

DDR_DQ46

A3

DDR_DQ47

C7

DDR_DQS5P

F3

DDR_DQS7P

B7

DDR_DQS5N

G3

DDR_DQS7N

D3

DDR_DM5

E7

DDR_DM7

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

T2 L8

DDR_ZQ6DDR_ZQ4

ZQ

R223 240R/F_2

BYTE 7

BYTE 5

DDR_DQS5P 3 DDR_DQS7P 3 DDR_DQS5N 3 DDR_DQS7N 3

DDR_DM5 3 DDR_DM7 3

11

R208

5.49K/F_4

M_VREF_M2_DQ

R215

D D

1

2

5.49K/F_4

3

R213

5.49K/F_4

R214

5.49K/F_4

4

M_VREF_M2_CA

PROJECT : Baileys

+1.35V_LP03,10,34,35,41

5

+1.35V_LP0

6

NB5

NB5 HW

HW

7

PROJECT : Baileys

Quanta Computer Inc.

Size Document Number Rev

DDR3L SDRAM(B)

Date: Sheet of

11 41Tuesday, June 10, 2014

8

+3.3V_LP0

+3.3V_SYS

10u/6.3V/X5R_6

EN_AVDD_LCD33

TS_IRQ*_3V3

+3.3V_SYS

+3.3V_LP0

C11 1U/10V_4

TS_SHDN_L6,12

+3.3V_RUN

+2.8V_RUN_CAM

C25

VDD_3V3_TS_F

R42 100K_2

R11 0_6 R12 *0_6

VDD_3V3_LCD_TS

R35 *0_4/S

R25 *0_6

C23

1U/6.3V/X5R_4

EN_AVDD_LCD

R23 100K/F_4

VDD_3V3_TS_F

R49 100K_2

TS_IRQ*_Q

61

2

Q4B PJ4N3KDW

R41 *0R_2

*BLM15PX330SN1D(33,3000MA)_4

R6 100K/F_2

C28

2.2U/6.3V_4

R24 0_6

5 4 3

+1.8V_VDDIO

5

L1

U9

5

IN

4

IN

3

ON/OFF

IC(5P) G5243AT11U

U11

bga4-texas-tps22902

COMMON

A2

VIN

B2

ON

AL022902T00 IC OTHER (4P)TPS22902YFPR(DSBGA)

R30 *0_4

U10

IN IN ON/OFF

IC(5P) G5243AT11U

OUT GND

TS INT and RST Level Shift

R40 10K_2

34

Q4A PJ4N3KDW

VDD_3V3_TS_F

1

OUT

2

GND

R33 *0_6

VOUT

GND

1 2

TS_RESET_L6

C10

4.7U/6.3V_4

A1

B1

+3.3V_PANEL

C19 4.7UF_4 C27 1U/6.3V/X5R_4 C26 0.1U/10V/X5R_4

TS_IRQ_L 6

VDD_3V3_TS_F

C5

0.1uF_2

GND

+3.3V_USBCAM

C9

0.1U/10V/X5R_4

+3.3V_PANEL_R

R37 R020_8/P

+1.8V_VDDIO

1

Q7

MESS138-G

SI Modified 0418

DP_AUX_N5

DP_AUX_P5

c lose to CPU

2

DMIC_DATA19

DMIC_CLK19

VDD_3V3_TS_F

3

DP_AUX_N DP_AUX_P

+1.8V_VDDIO

0.1uF_2

R50 10K_4

TS_RESET_3.3V

R61 *0_2/S

C41

R271

100K/F_4

DP_TXD1_N5 DP_TXD1_P5

DP_TXD0_N5 DP_TXD0_P5

DP_AUX_P_C DP_AUX_N_C

GEN2_I2C_SCL_3.3V6,24 GEN2_I2C_SDA_3.3V6,24

To Camera Level Shift

U13

1

VCCA

2

A1

3

A2

4

GND

TXS0102DQER

AL000102010

SI Modified 0418

+3.3V_PANEL

R272

100K/F_4

R29 100K/F_4

C21 0.1U/10V/X7R_4 C20 0.1U/10V/X7R_4

DP_TXD1_N DP_TXD1_P

DP_TXD0_N DP_TXD0_P DP_LN0_P

CCD

8

VCCB

B1

7

B2

6

OE

5

C15 0.1U/10V/X7R_4 C16 0.1U/10V/X7R_4

C17 0.1U/10V/X7R_4 C18 0.1U/10V/X7R_4

R21 *0_4/S

VDD_3V3_TS_F

C181

4.7U/6.3V_4

GND GND

TS_RESET_3.3V

+3.3V_USBCAM

R54 *0_2/S

*7.5K/F_4

DMIC_CLK_C DMIC_DATA_C

C42

0.1uF_2

*Clamp-Diode

+3.3V_PANEL_R

R15 *0_4/S R16 *0_4/S

CAM_USBD_N CAM_USBD_P

DMIC_DATA_C DMIC_CLK_C

R47

C29

R22 *0_4/S

GEN2_I2C_SCL_3.3V

GEN2_I2C_SDA_3.3V TS_GEN2_I2C_SDA

TS_IRQ*_3V3

CAM_USBD_N18 CAM_USBD_P18

DMIC

VDD_3V3_SYS_1VDD_1V8_PMU_1

DP_AUX_N_C DP_AUX_P_C

R28

100K/F_4

R17 *0_4/S

R18 *0_4/S R19 *0_4/S

R20 *0_4/S

C176

0.1uF_2

+3.3V_USBCAM

12

C12 1000p/50V/X7R_4 C8 4.7UF_4 C13 10p/50V/C0G_4

MCM2012B900GBE

1

2

443

R51

*7.5K/F_4

12

C35 *Clamp-Diode

EDP_HPD5

LCD_BL_EN_R3.3V13 LCD_BL_PWM_R3.3V13

+VDD_LED13

+VDD_LED

TS_SHDN_L6,12

2 3

R235 600,0.3A

L2

R229 600,0.3A

DP_AUX_P_C1 DP_AUX_N_C1

EDP_HPD

R217 *0_4

TS_GEN2_I2C_SCL

CAM_USBD_N_R CAM_USBD_P_R

DMIC_DATA_L DMIC_CLK_L

C186

*150p/50V/NPO_4

NB5

NB5 HW

HW

DP_LN1_N DP_LN1_P

DP_LN0_N

C183 0.01U/10V/X7R_4

LCD_BL_EN_R3.3V LCD_BL_PWM_R3.3V

+VDD_LED

C169 2.2U/25V_6 C174 2.2U/25V_6

+3.3V_USBCAM

DMIC_DATA_L DMIC_CLK_L

C180

*150p/50V/NPO_4

Size Document Number Rev

Date: Sheet of

Date: Sheet

12

eDP connector

CN1

4241 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

DFFC40FR063

51519-04041-001-40p-l

NOTE: THIS CONNECTOR REPRESENTS VARIOUS PANEL CONNECTOR OPTIONS DEFAULT CONNECTIONS ASSUME THE BACKLIGHT BOOST IS ON THE PANEL USING THE 40PIN CONNECTOR

+3.3V_LP0

+3.3V_LP05,6,7,14,15,17,18,24,26,32,34,41

+3.3V_RUN5,6,9,16,22,28,32,34,41

PROJECT : Baileys

Quanta Computer Inc.

eDP CONN/DMIC/CAMERA

+3.3V_LP0

+3.3V_RUN

12 41Tuesday, June 10, 2014

+3.3V_RUN

of

R48*0_8

13

Q3 AO3409

+VDD_MUX30,31,33,41 +VDD_LED 12

EN_VDD_BL4

EC_BL_OVERRIDE27

R71 1K/F_4

LCD_BL_EN6

LCD_BL_PWM6

+VDD_MUX

C40

1U/25V/X5R_6

R72 10K/F_4

LCD_BL_EN

LCD_BL_PWM

12

EN_VDD_BL_GATE

C44

0.1uF_2

1

R57 100K/F_4

Q6

2

VTH 0.9V MAX

ID 300MA

+1.8V_VDDIO

8

7 6 5

3

2

R53 75K/F_4

3

DMG1012T-7(SOT523)

1

+3.3V_PANEL

R44 0_4

BGA8_R

VCCB

B1

B2

DIR

SN74LVC2T45 LEVEL_SHIFTER_2BIT

SI Modified 0418

DIR 0| B->A(rx) 1| A->B(tx)

U14

VCCA

GND

A1

A2

I51

+3.3V_SYS

1 2 3 4

R34 R020_8/P

R43 *0_4

UNNAMED_15_CAP_I47_A

C31

0.1uF_2

LCD_BL_EN_R3.3V

LCD_BL_PWM_R3.3V

+VDD_LED

LCD_BL_EN_R3.3V 12 LCD_BL_PWM_R3.3V 12

NB5

NB5 HW

HW

+3.3V_SYS12,18,22,31,32,34

+1.8V_VDDIO4,5,6,10,12,15,16,19,20,21,22,23,24,26,27,32,33,34,35,41

PROJECT : Baileys

Quanta Computer Inc.

Size Document Number Rev

BACKLIGHT MISC AND GATE

Date: Sheet of

+3.3V_SYS

+1.8V_VDDIO

+3.3V_SYS

+1.8V_VDDIO

13 41Tuesday, June 10, 2014

HP CHROMEBOOK 14-X Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual