HP CHROMEBOOK 11 G4 EE Schematics

5

www.schematic-x.blogspot.com

4

3

2

1

Peach2.0

01

Intel Bay Trail-M Platform Block Diagram

D D

DDR3L 1333
Memory down

DDR3L

2 Channel 1Rx16

MMC

32.768KHz
PAGE 6

PAGE 11,12

eMMC

SDIN8DE2-16G

PAGE 21

C C

SKUA QC N2920
AJ0QFW3UT05--CPU (1170P)N2920 1.86G QFW3(FCBGA)

SKUB DC N2820
AJ0QFW4UT02--CPU (1170P)N2820 2.13G QFW4(FCBGA)

X4 LANES

Intel Bay Trail-M

DDI 1

DDI 0

I2C Interface

Power : TDP 7.5 Watt

Package : FCBGA 1170

25 Mhz
PAGE 6

Size : 25 x 27 (mm)

eDP

PAGE 17

HDMI Conn PAGE 19

Port0

Track Pad

PAGE 26

BQ24715

Batery Charger

NB670/NB671

PP3300_DSW/PP5000

ISL95833HRTZ-T

+VCC_CORE/+VCC_GFX

Discharger

SDIO

USB 3.0 Interface

Port0

1.8V BIOS+TXE
SPI ROM(64Mb)

W25Q64FWSSIG

PAGE 6

SPI Interface

USB Chargerx 2

Port0

Int

PAGE 2~10

USB 2.0 Interface

TPS2546

PAGE 25

I2S+I2C(PORT1)

USB3.0 Port x 1

PAGE 25

Port3

Port2

Daughter Board

Port1

TPS51216

PP1350

TLV62150ARGTR

PP1050_PCH

TLV62130ARGTR

PP1000_PCH_S5

B B

PCIE Gen 2 x 1 LaneLPC Interface

NGFF M.2 2230-E

WLAN / BT Combo

TPM

SLB9655TT1.2
FW4.32GOOG

TI KBC

TM4E1G31H6ZRB

Audio Codec

MAX98090

NGFF M.2 2230-E

PAGE 20

WLAN / BT Combo

PAGE 26

Package : TQFN-40

Size : 5 x 5 (mm)

PAGE 24

Speaker

MIC SW

TS3A225E

PAGE 24

DMIC

CCD Integrated

4

PAGE 24

Combo Jack
Headphone + MIC

PAGE 24

PCIE CLK PORT 0

PAGE 20

LTE UART COEXISTENCE

PAGE 24

3

Package : BGA-157

Size : 9.1 x 9.1 (mm)

PAGE 22

Thermal IC

PAGE 27

Keyboard

TMP432A

A A

PAGE 26

5

CCD

PAGE 17

USB Hub -2

USB2.0 Port x 1

USB Hub

GL852G-OHG12

PAGE 25

USB Hub -3

USB Hub -1

NGFF M.2 3042-B

LTE

2

SD card

BOM value option:
CHB@-==>DDR Single channel or dual channel
EDP@ =>4 Lane eDP
TS@ =>Touch screen
SX@ => S0IX
NSX@=> Non S0ix
VC@ =>Video codec
LTE@ => LTE
GD@ =>Google debug

PROJECT : Peach

PROJECT : Peach

PROJECT : Peach

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom

NB5

NB5

NB5
HW

HW

HW

Intel Block Diagram

Intel Block Diagram

Intel Block Diagram

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

1A

1A

1A

1 40Friday, July 25, 2014

1 40Friday, July 25, 2014

1 40Friday, July 25, 2014

5

M_A_A[15:0]12

D D

M_A_DM012
M_A_DM112
M_A_DM212
M_A_DM312
M_A_DM412
M_A_DM512
M_A_DM612
M_A_DM712

M_A_RAS#12
M_A_CAS#12
M_A_WE#12

M_A_BS012
M_A_BS112
M_A_BS212

M_A_CS#012

C C

1023 unstuff R28 by
Intel request

1121 remove R28,R25,C35

M_A_DRAMRST#12

PP1350

B B

A A

R344

4.7K/F_4

CPU_VREF

R348

4.7K/F_4

GND GND

SLP_S4#6,14

C242

0.1U/10V_4

SLP_S4#

PP3300_PCH_S5

R151

4.7K_4

DRM_PWOK_C1

34

5

Q40A
PJ4N3KDW

GND

5

R195
10K_4

2

PP1350

GND

GND

DRAM_PWROK

61

Q40B

PJ4N3KDW

M_A_CKE012

M_A_ODT012

M_A_CLKP012
M_A_CLKN012

R15 100K/F_4
R16 100K/F_4

R23 23.2/F_4
R19 29.4/F_4
R18 162/F_4

R178 *0_4/S

GND

4

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7

M_A_RAS#
M_A_CAS#
M_A_WE#

M_A_BS0
M_A_BS1
M_A_BS2

M_A_CS#0

M_A_CKE0

M_A_ODT0

M_A_CLKP0
M_A_CLKN0

M_A_DRAMRST#

CPU_VREF

ICLK_DRAM_TERMN_0
ICLK_DRAM_TERMN_1

SOC_DRAM_PWROK
SOC_VCCA_PWROK

DRAM_RCOMP0
DRAM_RCOMP1
DRAM_RCOMP2

SOC_DRAM_PWROK

C102
*1u/10V_4

4

K45
H47
L41
H44
H50
G53
H49
D50
G52
E52
K48
E51
F47
J51
B49
B50

G36
B36
F38
B42
P51
V42
Y50
Y52

M45
M44

H51
K47

K44
D52

P44
P45

C47
D48

F44
E46

T41
P42

M50
M48

P50
P48

P41

AF44

AH42

AF42

AD42
AB42

AD44

AF45

AD45

AF40

AF41
AD40
AD41

R191 *0_4/S

U14A

DRAM0_MA_00
DRAM0_MA_11
DRAM0_MA_22
DRAM0_MA_33
DRAM0_MA_44
DRAM0_MA_55
DRAM0_MA_66
DRAM0_MA_77
DRAM0_MA_88
DRAM0_MA_99
DRAM0_MA_1010
DRAM0_MA_1111
DRAM0_MA_1212
DRAM0_MA_1313
DRAM0_MA_1414
DRAM0_MA_1515

DRAM0_DM_00
DRAM0_DM_11
DRAM0_DM_22
DRAM0_DM_33
DRAM0_DM_44
DRAM0_DM_55
DRAM0_DM_66
DRAM0_DM_77

DRAM0_RAS
DRAM0_CAS
DRAM0_WE

DRAM0_BS_00
DRAM0_BS_11
DRAM0_BS_22

DRAM0_CS_0
DRAM0_CS_2

DRAM0_CKE_00
RESERVED_D48
DRAM0_CKE_22
RESERVED_E46

DRAM0_ODT_0
DRAM0_ODT_2

DRAM0_CKP_0
DRAM0_CKN_0

DRAM0_CKP_2
DRAM0_CKN_2

DRAM0_DRAMRST

DRAM_VREF

ICLK_DRAM_TERMN
ICLK_DRAM_TERMN_AF42

DRAM_VDD_S4_PWROK
DRAM_CORE_PWROK

DRAM_RCOMP_00
DRAM_RCOMP_11
DRAM_RCOMP_22

RESERVED_AF40
RESERVED_AF41
RESERVED_AD40
RESERVED_AD41

VLV_M_D/BGA

REV = 1.15

ph

PP1350_PGOOD 31

+1.35V_SUS
+1.35V_SUS

EC_PWROK27

?
VLV_M_D

1 OF 13

EC_PWROK

3

3

DRAM0_DQ09_C32

DRAM0_DQ_1010
DRAM0_DQ_1111
DRAM0_DQ_1212
DRAM0_DQ_1313
DRAM0_DQ_1414
DRAM0_DQ_1515
DRAM0_DQ_1616
DRAM0_DQ_1717
DRAM0_DQ_1818
DRAM0_DQ_1919
DRAM0_DQ_2020
DRAM0_DQ_2121
DRAM0_DQ_2222
DRAM0_DQ_2323
DRAM0_DQ_2424
DRAM0_DQ_2525
DRAM0_DQ_2626
DRAM0_DQ_2727
DRAM0_DQ_2828
DRAM0_DQ_2929
DRAM0_DQ_3030
DRAM0_DQ_3131
DRAM0_DQ_3232
DRAM0_DQ_3333
DRAM0_DQ_3434
DRAM0_DQ_3535
DRAM0_DQ_3636
DRAM0_DQ_3737
DRAM0_DQ_3838
DRAM0_DQ_3939
DRAM0_DQ_4040
DRAM0_DQ_4141
DRAM0_DQ_4242
DRAM0_DQ_4343
DRAM0_DQ_4444
DRAM0_DQ_4545
DRAM0_DQ_4646
DRAM0_DQ_4747
DRAM0_DQ_4848
DRAM0_DQ_4949
DRAM0_DQ_5050
DRAM0_DQ_5151
DRAM0_DQ_5252
DRAM0_DQ_5353
DRAM0_DQ_5454
DRAM0_DQ_5555
DRAM0_DQ_5656
DRAM0_DQ_5757
DRAM0_DQ_5858
DRAM0_DQ_5959
DRAM0_DQ_6060
DRAM0_DQ_6161
DRAM0_DQ_6262
DRAM0_DQ_6363

DRAM0_DQSP_00
DRAM0_DQSN_00
DRAM0_DQSP_11
DRAM0_DQSN_11
DRAM0_DQSP_22
DRAM0_DQSN_22
DRAM0_DQSP_33
DRAM0_DQSN_33
DRAM0_DQSP_44
DRAM0_DQSN_44
DRAM0_DQSP_55
DRAM0_DQSN_55
DRAM0_DQSP_66
DRAM0_DQSN_66
DRAM0_DQSP_77
DRAM0_DQSN_77

PP3300_PCH_S5

4.7K_4

DRM_PWOK_C2

34

5

Q28A

PJ4N3KDW

GND

DRAM0_DQ_00
DRAM0_DQ_11
DRAM0_DQ_22
DRAM0_DQ_33
DRAM0_DQ_44
DRAM0_DQ_55
DRAM0_DQ_66
DRAM0_DQ_77
DRAM0_DQ_88

R205
10K_4R147

?

PP1350

2

M36
J36
P40
M40
P36
N36
K40
K42
B32
C32
C36
A37
C33
A33
C37
B38
F36
G38
F42
J42
G40
C38
G44
D42
A41
C41
A45
B46
C40
B40
B48
B47
K52
K51
T52
T51
L51
L53
R51
R53
T47
T45
Y40
V41
T48
T50
Y42
AB40
V45
V47
AD48
AD50
V48
V50
AB44
Y45
V52
W51
AC53
AC51
W53
Y51
AD52
AD51

J38
K38
C35
B34
D40
F40
B44
C43
N53
M52
T42
T44
Y47
Y48
AB52
AA51

61

PJ4N3KDW

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

M_A_DQSP0
M_A_DQSN0
M_A_DQSP1
M_A_DQSN1
M_A_DQSP2
M_A_DQSN2
M_A_DQSP3
M_A_DQSN3
M_A_DQSP4
M_A_DQSN4
M_A_DQSP5
M_A_DQSN5
M_A_DQSP6
M_A_DQSN6
M_A_DQSP7
M_A_DQSN7

Q28B

M_A_DQ[63:0] 12

M_A_DQSP0 12
M_A_DQSN0 12
M_A_DQSP1 12
M_A_DQSN1 12
M_A_DQSP2 12
M_A_DQSN2 12
M_A_DQSP3 12
M_A_DQSN3 12
M_A_DQSP4 12
M_A_DQSN4 12
M_A_DQSP5 12
M_A_DQSN5 12
M_A_DQSP6 12
M_A_DQSN6 12
M_A_DQSP7 12
M_A_DQSN7 12

SOC_VCCA_PWROK

C90
*0.1U/10V_4

GND

1128 place C90 to close SoC ball

2

1

2

PROJECT : Peach

PROJECT : Peach

PROJECT : Peach

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom

NB5

NB5

NB5
HW

HW

2

HW

Valley 1/9 (DDRA)

Valley 1/9 (DDRA)

Valley 1/9 (DDRA)

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

1A

1A

1A

2 40Friday, July 25, 2014

2 40Friday, July 25, 2014

2 40Friday, July 25, 2014

5

4

3

2

1

?
VLV_M_D

2 OF 13

DRAM1_DQ_00
DRAM1_DQ_11
DRAM1_DQ_22
DRAM1_DQ_33
DRAM1_DQ_44
DRAM1_DQ_55
DRAM1_DQ_66
DRAM1_DQ_77
DRAM1_DQ_88

DRAM1_DQ_99
DRAM1_DQ_1010
DRAM1_DQ_1111
DRAM1_DQ_1212
DRAM1_DQ_1313
DRAM1_DQ_1414
DRAM1_DQ_1515
DRAM1_DQ_1616
DRAM1_DQ_1717
DRAM1_DQ_1818
DRAM1_DQ_1919
DRAM1_DQ_2020
DRAM1_DQ_2121
DRAM1_DQ_2222
DRAM1_DQ_2323
DRAM1_DQ_2424
DRAM1_DQ_2525
DRAM1_DQ_2626
DRAM1_DQ_2727
DRAM1_DQ_2828
DRAM1_DQ_2929
DRAM1_DQ_3030
DRAM1_DQ_3131
DRAM1_DQ_3232
DRAM1_DQ_3333
DRAM1_DQ_3434
DRAM1_DQ_3535
DRAM1_DQ_3636
DRAM1_DQ_3737
DRAM1_DQ_3838
DRAM1_DQ_3939
DRAM1_DQ_4040
DRAM1_DQ_4141
DRAM1_DQ_4242
DRAM1_DQ_4343
DRAM1_DQ_4444
DRAM1_DQ_4545
DRAM1_DQ_4646
DRAM1_DQ_4747
DRAM1_DQ_4848
DRAM1_DQ_4949
DRAM1_DQ_5050
DRAM1_DQ_5151
DRAM1_DQ_5252
DRAM1_DQ_5353
DRAM1_DQ_5454
DRAM1_DQ_5555
DRAM1_DQ_5656
DRAM1_DQ_5757
DRAM1_DQ_5858
DRAM1_DQ_5959
DRAM1_DQ_6060
DRAM1_DQ_6161
DRAM1_DQ_6262
DRAM1_DQ_6363

DRAM1_DQSP_00
DRAM1_DQSN_00
DRAM1_DQSP_11
DRAM1_DQSN_11
DRAM1_DQSP_22
DRAM1_DQSN_22
DRAM1_DQSP_33
DRAM1_DQSN_33
DRAM1_DQSP_44
DRAM1_DQSN_44
DRAM1_DQSP_55
DRAM1_DQSN_55
DRAM1_DQSP_66
DRAM1_DQSN_66
DRAM1_DQSP_77
DRAM1_DQSN_77

?REV = 1.15

BG38
BC40
BA42
BD42
BC38
BD36
BF42
BC44
BH32
BG32
BG36
BJ37
BG33
BJ33
BG37
BH38
AU36
AT36
AV40
AT40
BA36
AV36
AY42
AY40
BJ41
BG41
BJ45
BH46
BG40
BH40
BH48
BH47
AY52
AY51
AP52
AP51
AW51
AW53
AR51
AR53
AP47
AP45
AK40
AM41
AP48
AP50
AK42
AH40
AM45
AM47
AF48
AF50
AM48
AM50
AH44
AK45
AM52
AL51
AG53
AG51
AL53
AK51
AF52
AF51

BF40
BD40
BG35
BH34
BA38
AY38
BH44
BG43
AU53
AV52
AP42
AP44
AK47
AK48
AH52
AJ51

M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

M_B_DQSP0
M_B_DQSN0
M_B_DQSP1
M_B_DQSN1
M_B_DQSP2
M_B_DQSN2
M_B_DQSP3
M_B_DQSN3
M_B_DQSP4
M_B_DQSN4
M_B_DQSP5
M_B_DQSN5
M_B_DQSP6
M_B_DQSN6
M_B_DQSP7
M_B_DQSN7

M_B_A[15:0]13

D D

M_B_DM013
M_B_DM113
M_B_DM213
M_B_DM313
M_B_DM413
M_B_DM513
M_B_DM613
M_B_DM713

M_B_RAS#13
M_B_CAS#13
M_B_WE#13

M_B_BS013
M_B_BS113
M_B_BS213

C C

1023 unstuff R29 by
Intel request

M_B_CS#013

M_B_CKE013

M_B_ODT013

M_B_CLKP013
M_B_CLKN013

1121 remove R29,R26,C36

M_B_DRAMRST#13

B B

M_B_A0 M_B_DQ0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7

M_B_RAS#
M_B_CAS#
M_B_WE#

M_B_BS0
M_B_BS1
M_B_BS2

M_B_CS#0

M_B_CKE0

M_B_ODT0

M_B_CLKP0
M_B_CLKN0

M_B_DRAMRST#

AY45
BB47

AW41

BB44
BB50

BC53

BB49
BF50

BC52

BE52
AY48
BE51

BD47

BA51
BH49
BH50

BD38
BH36
BC36
BH42

AT51
AM42

AK50

AK52

AV45

AV44

BB51

AY47

AY44

BF52

AT44

AT45

BG47

BE46

BD44

BF48

AP41

AT42

AV50

AV48

AT50

AT48

AT41

U14B

DRAM1_MA_00
DRAM1_MA_11
DRAM1_MA_22
DRAM1_MA_33
DRAM1_MA_44
DRAM1_MA_55
DRAM1_MA_66
DRAM1_MA_77
DRAM1_MA_88
DRAM1_MA_99
DRAM1_MA_1010
DRAM1_MA_1111
DRAM1_MA_1212
DRAM1_MA_1313
DRAM1_MA_1414
DRAM1_MA_1515

DRAM1_DM_00
DRAM1_DM_11
DRAM1_DM_22
DRAM1_DM_33
DRAM1_DM_44
DRAM1_DM_55
DRAM1_DM_66
DRAM1_DM_77

DRAM1_RAS
DRAM1_CAS
DRAM1_WE

DRAM1_BS_00
DRAM1_BS_11
DRAM1_BS_22

DRAM1_CS_0
DRAM1_CS_2

DRAM1_CKE_00
RESERVED_BE46
DRAM1_CKE_22
RESERVED_BF48

DRAM1_ODT_0
DRAM1_ODT_2

DRAM1_CKP_0
DRAM1_CKN_0

DRAM1_CKP_2
DRAM1_CKN_2

DRAM1_DRAMRST

VLV_M_D/BGA

M_B_DQ[63:0] 13

M_B_DQSP0 13
M_B_DQSN0 13
M_B_DQSP1 13
M_B_DQSN1 13
M_B_DQSP2 13
M_B_DQSN2 13
M_B_DQSP3 13
M_B_DQSN3 13
M_B_DQSP4 13
M_B_DQSN4 13
M_B_DQSP5 13
M_B_DQSN5 13
M_B_DQSP6 13
M_B_DQSN6 13
M_B_DQSP7 13
M_B_DQSN7 13

3

A A

PROJECT : Peach

PROJECT : Peach

PROJECT : Peach

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom

NB5

NB5

NB5
HW

HW

5

4

3

2

HW

Valley 2/9 (DDRB)

Valley 2/9 (DDRB)

Valley 2/9 (DDRB)

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

1A

1A

1A

3 40Friday, July 25, 2014

3 40Friday, July 25, 2014

3 40Friday, July 25, 2014

5

4

3

2

1

U14C

INT_HDMITX2P19 EDP_TXP0 17
INT_HDMITX2N19
INT_HDMITX1P19
INT_HDMITX1N19

D D

C C

B B

INT_HDMITX0P19
INT_HDMITX0N19
INT_HDMICLK+19
INT_HDMICLK-19

INT_HDMI_HPD19

HDMI_DDCDATA_SW19

HDMI_DDCCLK_SW19

R442
402/F_4

R184 *0_4/S
R183 *0_4/S

GND GND

TP5
TP4

INT_HDMITX2P
INT_HDMITX2N
INT_HDMITX1P
INT_HDMITX1N
INT_HDMITX0P
INT_HDMITX0N
INT_HDMICLK+
INT_HDMICLK-

INT_HDMI_HPD
HDMI_DDCDATA_SW

HDMI_DDCCLK_SW

SOC_DDIO_RCOMP
SOC_DDIO_RCOMP_P

SOC_PIN_AM3
SOC_PIN_AM2

GPIO_NC13
GPIO_NC14

INTD_DSI_TE

BTM Strapping Table

Pin Name Strap description

GPIO_SO_SC_56

LPE_I2S2_FRM

GPIO_SO_SC_65

A A

DDI0_DDCDATA

DDI1_DDCDATA

Top Swap (A16 Override)

BIOS Boot Selection

ecurity Flash Descriptors

S

DDI0 Detect

DDI1 Detect

Sampled

PWROK

PWROK

PWROK

PWROK

PWROK

AV3
AV2
AT2
AT3
AR3
AR1
AP3
AP2

AL3
AL1

D27
C26

C28
B28

C27
B26

AK13

AK12
AM14
AM13

AM3
AM2

T2

T3
AB3
AB2

Y3

Y2

W3
W1

V2

V3

R3

R1
AD6
AD4
AB9
AB7

Y4

Y6

V4

V6
A29
C29

AB14

B30
C30

0 = Top address bit is unchanged

+1.0V_SX

DDI0_TXP_0

+1.0V_SX

DDI0_TXN_0

+1.0V_SX

DDI0_TXP_1

+1.0V_SX

DDI0_TXN_1

+1.0V_SX

DDI0_TXP_2

+1.0V_SX

DDI0_TXN_2

+

VLV_M_D/BGA

REV = 1.15

1.0V_SX

+1.0V_SX
+1.0V_SX

+1.0V_SX

+1.8V

+1.8V
+1.8V

+1.8V
+1.8V
+1.8V

DDI0_TXP_3
DDI0_TXN_3

DDI0_AUXP
DDI0_AUXN

DDI0_HPD
DDI0_DDCDATA

DDI0_DDCCLK
DDI0_VDDEN

DDI0_BKLTEN
DDI0_BKLTCTL

DDI0_RCOMP
DDI0_RCOMP_P
RESERVED_AM14
RESERVED_AM13
VSS_AM3
VSS_AM2

RESERVED_T2
RESERVED_T3
RESERVED_AB3
RESERVED_AB2
RESERVED_Y3
RESERVED_Y2
RESERVED_W3
RESERVED_W1
RESERVED_V2
RESERVED_V3
RESERVED_R3
RESERVED_R1
RESERVED_AD6
RESERVED_AD4
RESERVED_AB9
RESERVED_AB7
RESERVED_Y4
RESERVED_Y6
RESERVED_V4
RESERVED_V6
GPIO_S0_NC13
GPIO_S0_NC14_C29
RESERVED_AB14
GPIO_S0_NC12
RESERVED_C30

Configuration Note

1 = Top address bit is inverted

0 = LPC

1 = SPI

0 = Override

1 = Normal operation

0 = DDI0 not detected

1 = DDI0 detected

0 = DDI0 not detected

1 = DDI0 detected

GPIO_SO_NC_13

5

4

?
VLV_M_D

+1.0V_SX
+1.0V_SX

+1.8V

+1.8V

DDI1_DDCDATA

+1.8V

DDI1_DDCCLK

+1.8V
+1.8V

DDI1_BKLTEN

+1.8V

DDI1_BKLTCTL

RESERVED_AH14
RESERVED_AH13
RESERVED_AF14
RESERVED_AF13

VGA_DDCCLK

VGA_DDCDATA
RESERVED_T7

RESERVED_T9
RESERVED_AB13
RESERVED_AB12

RESERVED_Y12
RESERVED_Y13
RESERVED_V10

RESERVED_V9

RESERVED_T12
RESERVED_T10
RESERVED_V14
RESERVED_V13
RESERVED_T14
RESERVED_T13

RESERVED_T6

RESERVED_T4

RESERVED_P14

RESERVED_K34

GPIO_S0_NC26

GPIO_S0_NC25

GPIO_S0_NC24

GPIO_S0_NC23

GPIO_S0_NC22

GPIO_S0_NC21

GPIO_S0_NC20

GPIO_S0_NC18

GPIO_S0_NC17

GPIO_S0_NC16

3 OF 13

GPIO_S0_NC15

GPIO_S0_SC_567

I2S_LRCLK5

SOC_OVERRIDE#27

Pull up +1.8V at HDMI side

AG3
AG1
AF3
AF2
AD3
AD2
AC3
AC1

AK3
AK2

K30
P30

G30
N30

J30
M30

AH14
AH13
AF14
AF13
AH3
AH2

BA3
AY2
BA1
AW1
AY3

BD2
BF2

BC1
BC2

T7
T9
AB13
AB12
Y12
Y13
V10
V9
T12
T10
V14
V13
T14
T13
T6
T4
P14

K34
D32
N32
J34
K28
F28
F32
D34
J28
D28
M32
F34

GPIO_S0_SC_56

R128 *10K_4

I2S_LRCLK

R372 10K_4

I2S_DOUT5

DDI1_DDCDATA

R386 2.2K_4

GPIO_NC13

R62 *10K_4

EDP_TXP0
EDP_TXN0
EDP_TXP1
EDP_TXN1

EDP_AUXP
EDP_AUXN

EDP_HPD_L
DDI1_DDCDATA

SOC_DISP_ON_C
SOC_EDP_BLON_C
SOC_DPST_PWM_C

SOC_PIN_AH3
SOC_PIN_AH2

VGA_DDCCLK
VGA_DDCDATA

XDP_GPIO_S0_NC19

XDP_GPIO_S0_NC23
XDP_GPIO_S0_NC22
XDP_GPIO_S0_NC21
XDP_GPIO_S0_NC20
XDP_GPIO_S0_NC18
XDP_GPIO_S0_NC17
XDP_GPIO_S0_NC16
XDP_GPIO_S0_NC15

R434 *10K_4

R369 *10K_4

I2S_DOUT

SOC_OVERRIDE_NM

R76 *10K_4

R388 *10K_4

R63 10K_4

EDP_TXN0 17
EDP_TXP1 17
EDP_TXN1 17

EDP_AUXP 17
EDP_AUXN 17

SOC_DISP_ON_C 15
SOC_EDP_BLON_C 15
SOC_DPST_PWM_C 15

R452 *0_4/S
R457 *0_4/S

R180 *0_4/S
R197 *0_4/S

3

2

1

DDI1_TXP_0
DDI1_TXN_0
DDI1_TXP_1
DDI1_TXN_1
DDI1_TXP_2
DDI1_TXN_2
DDI1_TXP_3
DDI1_TXN_3

DDI1_AUXP
DDI1_AUXN

DDI1_HPD

DDI1_VDDEN

VSS_AH3
VSS_AH2

VGA_RED

VGA_BLUE

VGA_GREEN

VGA_IREF
VGA_IRTN

VGA_HSYNC
VGA_VSYNC

?

PP1800_PCH GND

R58 *0_4/S

HDMI_DDCDATA_SW

PP1800_PCH GND

PP1800_PCH GND

3

XDP_GPIO_S0_NC19 11

XDP_GPIO_S0_NC23 11
XDP_GPIO_S0_NC22 11
XDP_GPIO_S0_NC21 11
XDP_GPIO_S0_NC20 11
XDP_GPIO_S0_NC18 11
XDP_GPIO_S0_NC17 11
XDP_GPIO_S0_NC16 11
XDP_GPIO_S0_NC15 11

GNDPP1800_PCH

Q6

2N7002K

GND

1029 unstuff R128, using SoC internal PU

029 unstuff R372, using SoC internal PU

1
1115 stuff R372, system can't boot if un-stuff R372 on

proto1.5 board, need intel double confirm before proto2

GND

1029 unstuff R386, using SoC internal PU
1115 stuff R386, it is required for eDP to be detected

HPD output high
SOC active Low

2

EDP_HPD_L

PP1800_PCH

R146

10K_4

3

2

Q32

2N7002K

NB5

NB5

NB5
HW

HW

HW

GND GND

EDP_HPD

1

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom
Date: Sheet of

Date: Sheet of

Date: Sheet of

R459
100K/F_4

PROJECT : Peach

PROJECT : Peach

PROJECT : Peach

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Valley 3/9 (Display)

Valley 3/9 (Display)

Valley 3/9 (Display)

1

EDP_HPD 17

4

4 40Friday, July 25, 2014

4 40Friday, July 25, 2014

4 40Friday, July 25, 2014

1A

1A

1A

5

4

3

2

1

1025 Delete complete SSD(connector and caps), unstuf

PP1800_PCH

R215 *10K_4

R198 *10K_4

D D

C C

B B

SATA_DEVSLP_C

SATA_LED_R_N

and add test points on SATA signals

SOC_KBC_SCI14

R408
402/F_4

EMMC_CLK21

EMMC_D021
EMMC_D121
EMMC_D221
EMMC_D321
EMMC_D421
EMMC_D521
EMMC_D621
EMMC_D721

EMMC_CMD21

EMMC_RST#21

SD3_CLK23

SD3_D123
SD3_D223
SD3_D323
SD3_CD#18,23
SD3_CMD23

TP23

SDIO3_PWR_EN#23

GND

R409 49.9/F_4

GND

R403 49.9/F_4

GND

R131 *0_4/S
R139 *0_4/S

R204 *0_4/S

SD3_CLK
SD3_D0
SD3_D1
SD3_D2
SD3_D3
SD3_CD#
SD3_CMD
SDMMC3_1P8_EN
SDIO3_PWR_EN#

f R215

ICLK_SATA_TERMP
ICLK_SATA_TERMN

SATA_GP0
SATA_DEVSLP_C
SATA_LED_R_N

SATA_RCOMP_DP
SATA_RCOMP_DN

EMMC_CLK
EMMC_D0

EMMC_D1
EMMC_D2
EMMC_D3
EMMC_D4
EMMC_D5
EMMC_D6
EMMC_D7

EMMC_CMD
EMMC_RST#

EMMC_RCOMP

SDIO3_RCOMP

U14D

BF6

SATA_TXP_0

BG7

SATA_TXN_0

AU16

SATA_RXP_0

AV16

SATA_RXN_0

BD10

SATA_TXP1

BF10

SATA_TXN_1

AY16

SATA_RXP_1

BA16

SATA_RXN_1

BB10

ICLK_SATA_TERMP

BC10

ICLK_SATA_TERMN

BA12

SATA_GP0

AY14

SATA_GP1

AY12

SATA_LED

AU18

SATA_RCOMP_P_AU18

AT18

SATA_RCOMP_N_AT18

AT22

MMC1_CLK

AV20

MMC1_D0

AU22

MMC1_D1

AV22

MMC1_D2

AT20

MMC1_D3

AY24

MMC1_D4

AU26

MMC1_D5

AT26

MMC1_D6

AU20

MMC1_D7

AV26

MMC1_CMD

BA24

MMC1_RST

AY18

MMC1_RCOMP

BA18

SD2_CLK

AY20

SD2_D0

BD20

SD2_D1

BA20

SD2_D2

BD18

SD2_D3_CD

BC18

SD2_CMD

AY26

SD3_CLK

AT28

SD3_D0

BD26

SD3_D1

AU28

SD3_D2

BA26

SD3_D3

BC24

SD3_CD#

AV28

SD3_CMD

BF22

SD3_1P8EN

BD22

SD3_PWREN

BF26

SD3_RCOMP

V

LV_M_D/BGA

+1.8V/+3.3V
+1.8V/+3.3V
+1.8V/+3.3V
+1.8V/+3.3V
+1.8V
+1.8V/+3.3V

REV = 1.15

+1.8V
+1.8V
+1.8V

+1.8V

+1.8V
+1.8V

?
VLV_M_D

+1.0V
+1.0V

+1.8V
+1.8V
+1.8V
+1.8V

PCIE_RCOMP_P_AP14_AP14
PCIE_RCOMP_N_AP13_AP13

+1.8V/1.5V
+1.8V/1.5V
+1.8V/1.5V
+1.8V/1.5V
+1.8V/1.5V
+1.8V/1.5V
+1.8V/1.5V+1.8V/+3.3V
+1.8V/1.5V

+1.8V

4 OF 13

+1.8V

RESERVED_AV10

HDA_LPE_RCOMP

LPE_I2S2_DATAOUT

LPE_I2S2_DATAIN

+1.0V

PCIE_TXP_0
PCIE_TXN_0

PCIE_RXP_0
PCIE_RXN_0

PCIE_TXP_1
PCIE_TXN_1

PCIE_RXP_1
PCIE_RXN_1

PCIE_TXP_2
PCIE_TXN_2

PCIE_RXP_2
PCIE_RXN_2

PCIE_TXP_3
PCIE_TXN_3

PCIE_RXP_3
PCIE_RXN_3

VSS_BB7
VSS_BB5

PCIE_CLKREQ_0
PCIE_CLKREQ_1
PCIE_CLKREQ_2
PCIE_CLKREQ_3

SD3_WP_BD5

RESERVED_BB4
RESERVED_BB3

RESERVED_AV9

HDA_RST

HDA_SYNC

HDA_CLK
HDA_SDO
HDA_SDI0
HDA_SDI1

HDA_DOCKRST

HDA_DOCKEN
LPE_I2S2_CLK

LPE_I2S2_FRM

RESERVED_P34
RESERVED_N34

RESERVED_AK9
RESERVED_AK7

PROCHOT

AY7

PCIE_TX0+_WLAN_C

AY6

PCIE_TX0-_WLAN_C

AT14

PCIE_RX0+_WLAN

AT13

PCIE_RX0-_WLAN

AV6
AV4

AT10
AT9

AT7
AT6

AP12
AP10

AP6
AP4

1213 swap CLKREQ_WLAN and CLKREQ_IMAGE for

AP9

CLKREQ and CLK pins are aligned

AP7
BB7

VSS_BB7

BB5

VSS_BB5

BG3

PCIE_CLKREQ_WLAN#

BD7

PCIE_CLKREQ_IMAGE#

BG5

PCIE_CLKREQ_LAN#

BE3

PCIE_CLKREQ3#

BD5

SD3_WP

AP14

SOC_PCIE_COMP

AP13

SOC_PCIE_COMN

BB4
BB3
AV10
AV9

BF20

HDA_RCOMP

BG22

ACZ_RST#

BH20

ACZ_SYNC

BJ21

ACZ_BCLK

BG20

ACZ_SDOUT

BG19

PCH_AZ_CODEC_SDIN0

BG21
BH18

DET_TRIGGER

BG18

HDA_DOCKEN#

BF28

I2S_BCLK

BA30

I2S_LRCLK

BC30

I2S_DOUT

BD28

I2S_DIN

P34
N34

AK9
AK7

C24

SOC_PROCHOT#

?

C8883

0.1uF_2

C336 0.1U/10V_4
C341 0.1U/10V_4

R123 *0_4/S

R96 71.5/F_4
R103 0_4

R414 *0_4/S

R455 *0_4/S
R462 *0_4/S

TP18
TP15

SD3_WP 23

R410 49.9/F_4

TP6
TP10
TP7
TP8
TP9

R383 *0_4/S
R375 *0_4/S
R381 *0_4/S
R379 *0_4/S

H_PROCHOT#

R553 *0_4

1021 un-stuff R553

PCIE_TX0+_WLAN 20
PCIE_TX0-_WLAN 20

PCIE_RX0+_WLAN 20
PCIE_RX0-_WLAN 20

PCIE_CLKREQ_WLAN# 20

GND

DET_TRIGGER 24
AJACK_MICPRES_L 24SD3_D023

PP1000_PCH

H_PROCHOT# 18,27,33
IMVP7_PROCHOT# 28
ALERT# 23

GND

R431
402/F_4

I2S_BCLK_R 24
I2S_LRCLK_R 24
I2S_DOUT_R 24
I2S_DIN_R 24

PCIE_CLKREQ_IMAGE#
PCIE_CLKREQ_WLAN#

I2S_DOUT

1029 unstuff R364,
using SoC internal PU

0 = LPC
1 = SPI

I2S_LRCLK
I2S_DOUT

Security Flash Descriptors
0 = Override
1 = Normal Operation

Need check to see if MOSFET
isolation needed or not

5

R8903 *10K_4
R148 10K_4

R364 *10K_4

I2S_LRCLK 4
I2S_DOUT 4

PP1800_PCH

GND

A A

PROJECT : Peach

PROJECT : Peach

PROJECT : Peach

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom

NB5

NB5

NB5
HW

HW

5

4

3

2

HW

Valley 4/9 (SD/PCIE/SATA)

Valley 4/9 (SD/PCIE/SATA)

Valley 4/9 (SD/PCIE/SATA)

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

1A

1A

1A

5 40Friday, July 25, 2014

5 40Friday, July 25, 2014

5 40Friday, July 25, 2014

R188
1M_4

5

XTAL25_IN
XTAL25_OUT

R466 4.02K/F_4
R467 47.5/F_4

GND

CLK_PCIE_WLANN20
CLK_PCIE_WLANP20

ICLK_ICOMP
ICLK_RCOMP

CLK_PCIE_WLANN
CLK_PCIE_WLANP

C105 12P/50V_4

GND

GND

C106 12P/50V_4

1121 by X'tal vender suggestion,

D D

change C105/C106 from 15pF to 12pF

XTAL25_OUT

1

2

Y3

25MHZ +-10PPM

4

3

XTAL25_IN

1031 remove R417, PRDY should
be direct connection between
SoC and XDP by intel request

2'nd : HHE BG625000121

1128 add a connection and name to

PP1800_PCH

KBD_IRQ#, besides add pulled high resistor

R150 10K_4

C C

PP1800_PCH_S5

R117 *10K_4
R108 10K_4
R122 10K_4

1025 add level shifter for
LTE SUSCLK

B B

SOC_JTAG2_TDO
PCH_WAKE#
TRACKPAD_INT#

I2S_MCLK24

KBD_IRQ#27
SRT_CRST#

XDP_H_TCK11

XDP_H_TRST#11

XDP_H_TMS11
XDP_H_TDI11

XDP_H_TDO11

XDP_H_PRDY#11

XDP_H_PREQ#_C11

MUX_AUD_INT1#24

R107 *0_4/S

R424 *0_4/S

WIFI_DISABLE#15

GND

PCH_WAKE_L27

TRACKPAD_INT#26

LTE_WAKE#15

PMC_SUSCLK115

SOC_KBC_SMI14

I2S_MCLK

KBD_IRQ#KBD_IRQ#
SRT_CRST#

XDP_H_TCK
XDP_H_TRST#
XDP_H_TMS
XDP_H_TDI
XDP_H_TDO
XDP_H_PRDY#
XDP_H_PREQ#

SOC_SPI_CS#
SOC_SPI_MISO

SOC_SPI_MOSI
SOC_SPI_CLK

PCH_WAKE#
TRACKPAD_INT#

LTE_WAKE#
SOC_JTAG2_TDO
PMC_SUSCLK1
PCH_SPI_WP_D
SOC_GPOI7

MUX_AUD_INT1#
WIFI_DISABLE#

R402 49.9/F_4

RTC Clock 32.768KHz

RTC Circuitry(RTC)

PP3300_RTC

A A

R116 0_6

30mils

+3V_RTC

R138

20K/F_4

R130

20K/F_4

C85
1u/6.3V_4

GND

5

GND

GND

C89
1u/6.3V_4

C84
1u/6.3V_4

SOC_RTEST#

SRT_CRST#

4

SOC_GPIO_RCOMP

RTC_X1

R161

10M_4

RTC_X2

4

AH12
AH10

AD14
AD13

AD10
AD12

AM10

AT34

AD9

AF6
AF4

AF9
AF7

AK4
AK6

AM4
AM6

AM9

BH7
BH5
BH4
BH8
BH6

BJ9

C12
D14

G12

F14

F12
G16
D18

F16

C23
C21
B22
A21
C22

B18
B16
C18
A17
C17
C16
B14
C15

C13
A13
C19

N26

U14E

ICLK_OSCIN
ICLK_OSCOUT

RESERVED_AD9
ICLK_ICOMP

ICLK_RCOMP
RESERVED_AD10

RESERVED_AD12
PCIE_CLKN_00

PCIE_CLKP_00
PCIE_CLKN_11

PCIE_CLKP_11

PCIE_CLKN_22
PCIE_CLKP_22

PCIE_CLKN_33
PCIE_CLKP_33

RESERVED_AM10
RESERVED_AM9

PMC_PLT_CLK_00
PMC_PLT_CLK_11
PMC_PLT_CLK_22
PMC_PLT_CLK_33
PMC_PLT_CLK_44
PMC_PLT_CLK_55
ILB_RTC_RST

TAP_TCK
TAP_TRST
TAP_TMS
TAP_TDI
TAP_TDO
TAP_PRDY
TAP_PREQ
RESERVED

PCU_SPI_CS_00
PCU_SPI_CS_11
PCU_SPI_MISO
PCU_SPI_MOSI
PCU_SPI_CLK

GPIO_S5_0
GPIO_S5_1
GPIO_S5_2
GPIO_S5_3
GPIO_S5_4
GPIO_S5_5
GPIO_S5_6
GPIO_S5_7

GPIO_S5_8
GPIO_S5_9
GPIO_S5_10

GPIO_RCOMP

VLV_M_D/BGA

REV = 1.15

12

Y2

32.768KHZ

?
VLV_M_D

+1.8V
+1.8V
+1.8V
+1.8V

+1.8V
+1.8V
+1.8V
+1.8V

+1.8V_S5
+1.8V_S5

+1.8V_S5
+1.8V_S5
+1.8V_S5

+1.8V_S5
+1.8V_S5

+1.8V_S5
+1.8V_S5
+1.8V
+1.8V_S5

+1.8V_S5

+1.8V
+1.8V
+1.8V
+1.8V
+1.8V
+1.8V

+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5 +1.0V

+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5

+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5

SPI ROM needs power in S3/S5 for the TXE (Trusted execution engine).

C9115P/50V_4

C9215P/50V_4

GND

+3V_RTC

+3V_RTC
+3V_RTC

5 OF 13

PP1800_PCH
PP1800_PCH_S5

+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5

+1.8V
+1.8V
+1.8V
+1.8V

R158 *0_6
R157 *0_6/S

PP3300_PCH_S5

3

SIO_UART1_RXD
SIO_UART1_TXD
SIO_UART1_RTS
SIO_UART1_CTS

SIO_UART2_RXD
SIO_UART2_TXD
SIO_UART2_RTS
SIO_UART2_CTS

PMC_SUSPWRDNACK

PMC_SUSCLK0_G24

PMC_SLP_S0IX

PMC_SLP_S4
PMC_SLP_S3

GPIO_S514_J20

PMC_ACPRESENT

PMC_WAKE_PCIE_0

PMC_BATLOW
PMC_PWRBTN

PMC_RSTBTN
PMC_PLTRST

GPIO_S517_J24

PMC_SUS_STAT

ILB_RTC_TEST

PMC_RSMRST

PMC_CORE_PWROK

ILB_RTC_X1
ILB_RTC_X2

ILB_RTC_EXTPAD

SVID_ALERT

+1.0V

SVID_DATA

+1.0V

SVID_CLK

SIO_PWM_00
SIO_PWM_11

GPIO_S5_22
GPIO_S5_23
GPIO_S5_24
GPIO_S5_25
GPIO_S5_26
GPIO_S5_27
GPIO_S5_28
GPIO_S5_29
GPIO_S5_30

SIO_SPI_CS
SIO_SPI_MISO
SIO_SPI_MOSI

SIO_SPI_CLK

PP1800_PCH_S5

3

AU34
AV34
BA34
AY34

BF34
BD34
BD32
BF32

D26
G24
F18
F22
D22
J20
D20
F26
K26
J26
BG9
F20
J24
G18

C11

B10
B7

C9
A9
B8

B24
A25
C25

AU32
AT32

K24
N24
M20
J18
M18
K18
K20
M22
M24

AV32
BA28
AY28
AY30

Q29 PJA138K

1

2

R136 10K_4

SPI_WP_ME

SPI_HOLD_ME

SIO_UART2_RXD
SIO_UART2_TXD

PMC_SUSPWRDNACK
PMC_SUSCLK0
SLP_S0IX#
SLP_S4#
SLP_S3#

ACPRESENT
SOC_PMC_WAKE#
PMC_BATLOW#
SOC_PWRBTN#
SOC_REST_BTN#
SOC_PLTRST#

PMC_SUS_STAT#

SOC_RTEST#

SOC_RSMRST#
CORE_PWROK

RTC_X1
RTC_X2
BRTC_EXTPAD

SVID_ALERT#_SOC
SVID_DATA_SOC
SVID_CLK_SOC

SIO_PWM1

XDP_GPIO_DFX0
XDP_GPIO_DFX1
XDP_GPIO_DFX2
XDP_GPIO_DFX3
XDP_GPIO_DFX4
XDP_GPIO_DFX5
XDP_GPIO_DFX6
XDP_GPIO_DFX7
XDP_GPIO_DFX8

SIO_SPI_CS#
SIO_SPI_MISO
SIO_SPI_MOSI
SIO_SPI_CLK

PP1800_PCH_ME

3

PCH_SPI_WP_D

R133 *0_4/S
R513 *0_4/S

1

2

TP31
TP33

SUS STAT OUTPUT PORT

SOC_RTEST# 11

R448 *0_4/S

C101 0.1U/10V_4

SPEC 512177 INPUT PORT

R90 20/F_4
R84 16.9/F_4
R81 0_4

TP69
TP56
TP57
TP70

R488 *3.3K/F_4

R500 3.3K/F_4

near SPI ROM as possible

Q272N7002K

3

PCH_SPI_WP_D

SPI_WP_ME

VR_SVID_ALERT#
VR_SVID_DATA
VR_SVID_CLK

TP32

PP1800_PCH_ME

C355

0.1U/10V_4

SPI_WP_ME_ROM

SPI_HOLD_ME

PP1800_PCH_ME

GPIO_SPI_WP 18,20
SPI_HOLD#_BIOS 18,20

o PCH

T

PCH_SPI_WP_D connect to GPIO58 at GRB

SPI_WP_ME 25,27

2

PMC_SUSPWRDNACK 14
PMC_SUSCLK0 15
SLP_S0IX# 14
SLP_S4# 2,14
SLP_S3# 14

ACPRESENT 15
SOC_PMC_WAKE# 15

SOC_PWRBTN# 14
SOC_REST_BTN# 11,18

SOC_PLTRST# 11,14
PMC_SUS_STAT# 14

SOC_RSMRST# 11,14
CORE_PWROK_R 11,27

GND

XDP_GPIO_DFX0 11
XDP_GPIO_DFX1 11
XDP_GPIO_DFX2 11
XDP_GPIO_DFX3 11
XDP_GPIO_DFX4 11
XDP_GPIO_DFX5 11
XDP_GPIO_DFX6 11
XDP_GPIO_DFX7 11
XDP_GPIO_DFX8 11

8

Default PD

GND

3

R501 3.3K/F_4

To debug header

From Screw/EC

2

O_1.8VA

CORE_PWROK

C8887

0.1uF_2

DATA, CLK CLOSE TO VR

VR_SVID_ALERT# 33
VR_SVID_DATA 33

VR_SVID_CLK 33

SPI_WP_ME

U22

SPI_SI

VCC

SPI_SO

CS#

SPI_SCK

WP#

SPI_HOLD7GND

SPI_FLASH

soic8-7_9-1_27

AKE5EZN0N00

IC FLASH (8P) W25Q64FWSSIG (SOIC)

9/6 Add EC_RCIN_L for warm boot,
EC side is OD type

SOC_REST_BTN#

R165 *0_4/S

5

SOC_SPI_MOSI_R

2

SOC_SPI_MISO_R

1

SOC_SPI_CS#_R

6

SOC_SPI_CLK_R

4

GND

SOC_SPI_CS#

PMC_SUSPWRDNACK
SOC_PMC_WAKE#
ACPRESENT
PMC_BATLOW#

SOC_REST_BTN#

GND

SPI_WP_ME_ROM_Q

R413 10K_4
R412 10K_4
R397 2.2K_4
R399 10K_4

R441 10K_4

VR_SVID_DATA
VR_SVID_ALERT#
VR_SVID_CLK

R468 *0_4/S

LAYOUT CLOSE TO SPI ROM

3.3V

R472 22/F_4
R487 22/F_4
R503 22/F_4
R480 22/F_4

LAYOUT CLOSE TO SPI ROM

R471 *0_4/S
R479 *0_4/S
R470 *0_4/S
R481 *0_4/S

SPI NOR FLASH

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom

NB5

NB5

NB5
HW

HW

HW

Date: Sheet of

Date: Sheet of

Date: Sheet

1

PP1800_PCH_S5

6

PP1800_PCH

PP1000_PCH

R88

R374

73.2/F_4

73.2/F_4

ALERT Close to SOC

EC_REST_L 27

PP1800_PCH_ME

C115 0.1u/10V_4

2
1

PROJECT : Peach

PROJECT : Peach

PROJECT : Peach

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

4

U1974LVC1G34

3 5

SOC_SPI_MOSI
SOC_SPI_MISO
SOC_SPI_CS#
SOC_SPI_CLK

PCH_SPI_SI_R 18,20
PCH_SPI_SO_R 18,20
PCH_SPI_CS0#_R 18,20

PCH_SPI_CLK_R 18,20

Valley 5/9 (SPI/GPIO/CLK)

Valley 5/9 (SPI/GPIO/CLK)

Valley 5/9 (SPI/GPIO/CLK)

1

73.2/F_4

SPI_WP_ME_ROM

R179
100K_4

R360

6 40Friday, July 25, 2014

6 40Friday, July 25, 2014

6 40Friday, July 25, 2014

of

1A

1A

1A

5

4

3

2

RAM ID

R186 *1K_4
R187 1K_4
R196 1K_4

R623 *1K_4

RAM_ID0
RAM_ID1
RAM_ID2

RAM_ID3

1

R202 1K_4
R203 *1K_4
R192 *1K_4

R624 *1K_4

PP1800_PCH_S5

7

2CH
2CH

2CH
1CH
1CHHynix AKD5JGETW11 H5TC4G63AFR-PBA

R422 10K_4
R433 10K_4

Freq. 1600MHz

PP1800_PCH

PP1800_PCH

7 40Friday, July 25, 2014

7 40Friday, July 25, 2014

7 40Friday, July 25, 2014

Size

4GB
4GB

2GB
2GB
2GB

1A

1A

1A

D D

LTE_DISABLE#15

LTE_DISABLE#
RAM_ID0

RAM_ID1
RAM_ID2

RAM_ID3

C2-test add RAM_ID3

PORT 1 USB CONN
PORT 2

LTE HUB1
PORT 3
PORT 4

C C

1101 add option BOM R446,R449 for
EC CLK for power saving by Intel
request

PCLK_TPM22

B B

CLK_PCI_EC27

PP1800_PCH

R446
*0_4

LPC_CLKRUN_L27

R120 2.2K_4
R125 2.2K_4
R141 2.2K_4

MB USB3.0

CCD

BT

GND

PP1800_PCH_S5

GND

GND

R185 45.3/F_4
R415 49.9/F_4

PCLK_TPM
CLK_PCI_EC SOC_CLKOUT_1
LPC_CLKRUN_L

SMB_SOC_DATA
SMB_SOC_CLK
SMB_SOC_ALERTB

USBP0+25
USBP0-25

USBP1+25
USBP1-25

USBP2+17
USBP2-17

USBP3+20

USBP3-20

R437 1K/F_4
R425 1K/F_4

R443 45.3/F_4

LPC_LAD022,27
LPC_LAD122,27
LPC_LAD222,27
LPC_LAD322,27

LPC_LFRAME#22,27

SOC_SERIRQ14

SMB_SOC_DATA11

SMB_SOC_CLK11

R97 10K_4
R189 10K_4

GND

USB_OC0#14,25

USB_OC1#14,25

R436 *0_4

R17660 BLM15BB121SN1D_4

R112 22/F_4
R109 0_4

SMB_SOC_DATA
SMB_SOC_CLK
SMB_SOC_ALERTB

ICLK_USB_TERMN_0
ICLK_USB_TERMN_1

USB_OC0#
USB_OC1#

USB_RCOMP

USB_PLL_MON

USB_HSIC_RCOMP

LPC_RCOMP
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
SOC_CLKOUT_0

SOC_CLKRUN#
SOC_SERIRQ

2014_0528_RF suggest

A A

GND

C8894 *22pF_2

C8895 *22pF_2

C8896 *22pF_2

R17668 *0_4

R17669 *0_4

R17670 *0_4

5

PCLK_TPM

CLK_PCI_EC

LPC_CLKRUN_L

GND

C8893 12P/50V_4

C386 *12P/50V_4

C387 *12P/50V_4

4

U14F

G2

GPIO_S5_31

M3

GPIO_S5_32

L1

GPIO_S5_33

K2

GPIO_S5_34

K3

GPIO_S5_35

M2

GPIO_S5_36

N3

GPIO_S5_37

P2

GPIO_S5_38

L3

GPIO_S5_39

J3

GPIO_S5_40

P3

GPIO_S5_41

H3

GPIO_S5_42

B12

GPIO_S5_43

M16

USB_DP0

K16

USB_DN0

J14

USB_DP1

G14

USB_DN1

K12

USB_DP2

J12

USB_DN2

K10

USB_DP3

H10

USB_DN3

D10

ICLK_USB_TERMN_D10

F10

ICLK_USB_TERMN

C20

USB_OC_00

B20

USB_OC_11

D6

USB_RCOMPO

C7

USB_RCOMPI

M13

USB_PLL_MON

B4

USB_HSIC0_DATA

B5

USB_HSIC0_STROBE

E2

USB_HSIC1_DATA

D2

USB_HSIC1_STROBE

A7

USB_HSIC_RCOMP

BF18

LPC_RCOMP

BH16

ILB_LPC_AD_00

BJ17

ILB_LPC_AD_11

BJ13

ILB_LPC_AD_22

BG14

ILB_LPC_AD_33

BG17

ILB_LPC_FRAME

BG15

ILB_LPC_CLK_00

BH14

ILB_LPC_CLK_11

BG16

ILB_LPC_CLKRUN

BG13

ILB_LPC_SERIRQ

BG12

PCU_SMB_DATA

BH10

PCU_SMB_CLK

BG11

PCU_SMB_ALERT

VLV_M_D/BGA

PCLK_TPM

CLK_PCI_EC

LPC_CLKRUN_L

REV = 1.15

+1.8V_S5
+

1.8V_S5

+1.8V/+3.3V
+1.8V/+3.3V
+1.8V/+3.3V
+1.8V/+3.3V
+1.8V/+3.3V
+1.8V/+3.3V
+1.8V/+3.3V
+1.8V/+3.3V
+1.8V

+1.8V
+1.8V
+1.8V

?
VLV_M_D

6 OF 13

+1.8V
+1.8V
+1.8V
+1.8V
+1.8V
+1.8V
+1.8V

+1.8V

+1.8V
+1.8V

+1.8V
+1.8V

+1.8V
+1.8V

+1.8V
+1.8V

+1.8V
+1.8V

+1.8V
+1.8V

+1.8V
+1.8V

3

RESERVED_M10

RESERVED_M9

RESERVED_P7
RESERVED_P6

RESERVED_M7

USB3_REXT0

RESERVED_P10
RESERVED_P12

RESERVED_M4
RESERVED_M6

USB3_RXP0
USB3_RXN0

USB3_TXP0
USB3_TXN0

RESERVED_H8
RESERVED_H7

RESERVED_H5
RESERVED_H4

GPIO_S0_SC_55
GPIO_S0_SC_56
GPIO_S0_SC_57
GPIO_S0_SC_58
GPIO_S0_SC_59
GPIO_S0_SC_60
GPIO_S0_SC_61

ILB_8254_SPKR

SIO_I2C0_DATA

SIO_I2C0_CLK

SIO_I2C1_DATA

SIO_I2C1_CLK

SIO_I2C2_DATA

SIO_I2C2_CLK

SIO_I2C3_DATA

SIO_I2C3_CLK

SIO_I2C4_DATA

SIO_I2C4_CLK

SIO_I2C5_DATA

SIO_I2C5_CLK

SIO_I2C6_DATA

SIO_I2C6_CLK

GPIO_S0_SC_092
GPIO_S0_SC_093

M10

RAM_IDVender Channel

M9
P7

P6

M7
M12

USB3_P0_REXT

P10
P12

M4
M6

D4
E3

K6
K7

H8
H7

H5
H4

BD12
BC12
BD14
BC14
BF14
BD16
BC16

BH12

BH22
BG23

BG24
BH24

BG25
BJ25

BG26
BH26

BF27
BG27

BH28
BG28

BJ29
BG29

BH30
BG30

?

R440 1.24K/F_4

USB3_RXP0
USB3_RXN0

USB3_TXP0
USB3_TXN0

TRACKPAD_INT_DX
GPIO_S0_SC_56
SOC_UART_TX
SIM_DET_C
EC_IN_RW_C

SOC_UART_RX SOC_UART_TX SOC_UART_RX

I2C_0_SDA_C

R102 22/F_4

I2C_0_SCL_C

R95 22/F_4

I2C_1_SDA_C

R89 22/F_4

I2C_1_SCL_C

R83 22/F_4

Light sensor(01/27 delete)

Touch panel(01/27 delete)

I2C_NFC_SDA
I2C_NFC_SCL

C-test sku2
C-test sku4
C-test sku3

GND

C-test sku1

USB3_RXP0 25
USB3_RXN0 25

USB3_TXP0 25

USB3_TXN0 25

I2C_0_SDA_R 15
I2C_0_SCL_R 15

I2C_1_SDA_R 24
I2C_1_SCL_R 24

2

Hynix
Elpida
Hynix 011 AKD5JGETW14 2CH 4GB
Micron 010
Elpida AKD5JGST410 EDJ4216EFBG-GNL-F

Hynix AKD5JGETW14 2GB1CH110

TRACKPAD_INT_DX 26
GPIO_S0_SC_56 4

SOC_UART_TX 18

SIM_DET_C 15

EC_IN_RW_C 15

SOC_UART_RX 18

Touch pad

udio Codec

A

Q PN Mfr. PN

001
000

AKD5JGETW11
AKD5JGST410

H5TC4G63AFR-PBA
EDJ4216EFBG-GNL-F
H5TC4G63AFR-PBR

AKD5DGSTL07 MT41K128M16JT-125M:K
100
101

H5TC4G63AFR-PBR

SIM_DET_C
TRACKPAD_INT_DX

Un-Stuff for Test Only

I2C_0_SDA_R
I2C_0_SCL_R

I2C_1_SDA_R
I2C_1_SCL_R

I2C_NFC_SDA
I2C_NFC_SCL

PROJECT : Peach

PROJECT : Peach

PROJECT : Peach

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom

NB5

NB5

NB5

HW

HW

HW

Date: Sheet of

Date: Sheet of

Date: Sheet of

R420
*0_4

Valley 6/9 (USB/LPC/I2C)

Valley 6/9 (USB/LPC/I2C)

Valley 6/9 (USB/LPC/I2C)

R438 4.7K_4
R432 4.7K_4

R421 4.7K_4
R416 4.7K_4

R368 *4.7K_4
R367 *4.7K_4

1

5

4

3

2

1

8

1031 for layout suggestion by
intel, VSS_AXG_SENSE didn't

D D

+VCC_CORE

+VCC_GFX

connect to VSS_SENSE, will
connect the GND via near
VCC_AXG_SENSE

1031 for layout, add 0hm between
GND and VSS_AXG_SENSE

R458

R373

100/F_4

100/F_4

VCC_SENSE

VSS_SENSE

R382
100/F_4

C C

B B

GND

1030 for core power, change
C271,C281,C280,C278,C273 to 10uF

1206 change C271,C273,C280 to
0603 22uF for ACLL issue

1204 for z-height issue, change
C72,C75,C81 to 0.85mm cap

VSS_AXG_SENSE33

PP1350

GND

PP1350

+VCC_CORE

VCC_SENSE33

VCC_AXG_SENSE33

VSS_SENSE33

GND

R385 *0_4/S

C231 1U/6.3V_4
C251 1U/6.3V_4
C38 0.1U/10V_4

C271 22uF/6.3VT_6
C281 22uF/6.3VT_6
C280 22uF/6.3VT_6
C278 10uF/6.3V_4
C273 10u/6.3V_4

C72 22u/6.3V_8
C83 22u/6.3V_8
C75 22u/6.3V_8
C81 22u/6.3V_8
C79 22u/6.3V_8
C80 22u/6.3V_8
C76 22u/6.3V_8

GND

VCC_SENSE
VCC_AXG_SENSE
VSS_SENSEVCC_AXG_SENSE

U14G

P28

CORE_VCC_SENSE_P28

BB8

UNCORE_VNN_SENSE

N28

CORE_VSS_SENSE_N28

AD38

DRAM_VDD_S4_AD38

AF38

DRAM_VDD_S4_AF38

A48

DRAM_VDD_S4

AK38

DRAM_VDD_S4_AK38

AM38

DRAM_VDD_S4_AM38

AV41

DRAM_VDD_S4_AV41

AV42

DRAM_VDD_S4_AV42

BB46

DRAM_VDD_S4_BB46

AA27

CORE_VCC_S0IX_AA27

AA29

CORE_VCC_S0IX_AA29

AA30

CORE_VCC_S0IX_AA30

AC27

CORE_VCC_S0IX_AC27

AC29

CORE_VCC_S0IX_AC29

AC30

CORE_VCC_S0IX_AC30

AD27

CORE_VCC_S0IX_AD27

AD29

CORE_VCC_S0IX_AD29

AD30

CORE_VCC_S0IX_AD30

AF27

CORE_VCC_S0IX_AF27

AF29

CORE_VCC_S0IX_AF29

AG27

CORE_VCC_S0IX_AG27

AG29

CORE_VCC_S0IX_AG29

AG30

CORE_VCC_S0IX_AG30

P26

CORE_VCC_S0IX_P26

P27

CORE_VCC_S0IX_P27

U27

CORE_VCC_S0IX_U27

U29

CORE_VCC_S0IX_U29

V27

CORE_VCC_S0IX_V27

V29

CORE_VCC_S0IX_V29

V30

CORE_VCC_S0IX_V30

Y27

CORE_VCC_S0IX_Y27

Y29

CORE_VCC_S0IX_Y29

Y30

CORE_VCC_S0IX_Y30

AF30

TP_CORE_V1P05_S4

VLV_M_D/BGA

REV = 1.15

?
VLV_M_D

7 OF 13

DRAM_VDD_S4_BD49
DRAM_VDD_S4_BD52
DRAM_VDD_S4_BD53
DRAM_VDD_S4_BF44
DRAM_VDD_S4_BG51

DRAM_VDD_S4_BJ48

DRAM_VDD_S4_C51
DRAM_VDD_S4_D44
DRAM_VDD_S4_F49
DRAM_VDD_S4_F52
DRAM_VDD_S4_F53
DRAM_VDD_S4_H46
DRAM_VDD_S4_M41
DRAM_VDD_S4_M42
DRAM_VDD_S4_V38
DRAM_VDD_S4_Y38

UNCORE_VNN_S3_AA24
UNCORE_VNN_S3_AC22
UNCORE_VNN_S3_AC24
UNCORE_VNN_S3_AD22
UNCORE_VNN_S3_AD24
UNCORE_VNN_S3_AF22

UNCORE_VNN_S3_AF24
UNCORE_VNN_S3_AG22
UNCORE_VNN_S3_AG24

UNCORE_VNN_S3_AJ22

UNCORE_VNN_S3_AJ24

UNCORE_VNN_S3_AK22

UNCORE_VNN_S3_AK24

UNCORE_VNN_S3_AK25

UNCORE_VNN_S3_AK27

UNCORE_VNN_S3_AK29

UNCORE_VNN_S3_AK30

UNCORE_VNN_S3_AK32
UNCORE_VNN_S3_AM22

TP2_CORE_VCC_S0IX

1031 remove TP44 and TP35 for GND vias adding

BD49
BD52
BD53
BF44
BG51
BJ48
C51
D44
F49
F52
F53
H46
M41
M42
V38
Y38

AA24
AC22
AC24
AD22
AD24
AF22
AF24
AG22
AG24
AJ22
AJ24
AK22
AK24
AK25
AK27
AK29
AK30
AK32
AM22

AA22

?

PP1350

+VCC_GFX

GND

C69
10uF/6.3V_4

C63

22uF/6.3VT_6

C235

1U/6.3V_4

C65
10U/6.3V_6

C70

22uF/6.3VT_6

C240

1U/6.3V_4

C68
10U/6.3V_6

C236

1U/6.3V_4

C266
22u/6.3V_6

1030 for Gfx power, change C266,C289,C290

to 10uF and add 2 caps 10uF

1206 change C266,C311,C315 to
0603 22uF for ACLL issue

C64

22uF/6.3VT_6

C237

1U/6.3V_4

C289
10u/6.3V_4

1030 change C60 power netname
for layout

+VCC_GFX

1U/6.3V_4

C290
10u/6.3V_4

C60

22u/6.3V_8

C238

GND

C311
22u/6.3V_6

C239

1U/6.3V_4

C315
22u/6.3V_6

A A

PROJECT : Peach

PROJECT : Peach

PROJECT : Peach

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom

NB5

NB5

NB5
HW

HW

5

4

3

2

HW

Valley 7/9 (Power 1)

Valley 7/9 (Power 1)

Valley 7/9 (Power 1)

Date: Sheet of

Date: Sheet of

Date: Sheet

1

1A

1A

1A

of

8 40Friday, July 25, 2014

8 40Friday, July 25, 2014

8 40Friday, July 25, 2014

5

C299 1U/6.3V_4

GND

C329 1U/6.3V_4

PP1000_PCH
PP1000_PCH_SX

PP1000_PCH_SX

D D

PP1000_PCH_SX

PP1000_PCH

PP1000_PCH
PP1000_PCH_SX

PP1000_PCH

C C

PP1000_PCH_S5

PP1050_PCH

PP1350_PCH_SX

PP1350_PCH

PP1350_PCH

GND

C295 1U/6.3V_4
C306 1U/6.3V_4

C314 1U/6.3V_4

R54 *0_4/S

R456 *0_4/S

R354 *0_8/S
R384 *0_8/S

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

C256 1U/6.3V_4

C258 1U/6.3V_4
C255 1U/6.3V_4
C254 1U/6.3V_4

USB3_V1P0_G3
VIS_V1P0_S0IX_PW

C338 0.01U/25V_4
C305 10u/6.3V_4

C308 1U/6.3V_4
C287 10u/6.3V_4

CORE_V1P05
VIS_V1P0_S0IX_PW

C286 1U/6.3V_4
C284 10u/6.3V_4

C313 10u/6.3V_4
C279 1U/6.3V_4

USB3_V1P0_G3

C334 1U/6.3V_4

C324 1U/6.3V_4

CORE_V1P05
UNCORE_V1P35_S0IX

C262 1U/6.3V_4

C259 1U/6.3V_4

UNCORE_V1P35_S0IX

C297 1U/6.3V_4

C253 1U/6.3V_4

C339 1U/6.3V_4

C349 1U/6.3V_4

GND

AD35

AF35
AF36

AA36

AJ36
AK35
AK36

AK19
AK21

AJ18
AM16

AN29
AN30

AF16

AF18

AM21
AN21

AN18
AN19
AA33

AF21
AG21

AN25

AC32

AA25
AG32

AF19
AG19

AJ19

AG18
AN16

V32
BJ6

Y35
Y36

U22
V22

Y18

G1

V24
Y22

Y24
M14
U18
U19

Y19

Y32
U36

V36
BD1

U16

4

U14H

SVID_V1P0_S3_V32
VGA_V1P0_S3_BJ6
DRAM_V1P0_S0IX_AD35
DRAM_V1P0_S0IX_AF35
DRAM_V1P0_S0IX_AF36
DRAM_V1P0_S0IX_AA36
DRAM_V1P0_S0IX_AJ36
DRAM_V1P0_S0IX_AK35
DRAM_V1P0_S0IX_AK36
DRAM_V1P0_S0IX_Y35
DRAM_V1P0_S0IX_Y36
DDI_V1P0_S0IX_AK19
DDI_V1P0_S0IX_AK21
DDI_V1P0_S0IX_AJ18
DDI_V1P0_S0IX_AM16
UNCORE_V1P0_G3_U22
UNCORE_V1P0_G3_V22
VIS_V1P0_S0IX_AN29
VIS_V1P0_S0IX_AN30
UNCORE_V1P0_S3_AF16
UNCORE_V1P0_S3_AF18
UNCORE_V1P0_S3_Y18
UNCORE_V1P0_S3_G1
PCIE_V1P0_S3_AM21
PCIE_V1P0_S3_AN21

PCIE_GBE_SATA_V1P0_S3_AN18
SATA_V1P0_S3_AN19
CORE_V1P05_S3_AA33
UNCORE_V1P0_S0IX_AF21
UNCORE_V1P0_S0IX_AG21
VIS_V1P0_S0IX_V24
VIS_V1P0_S0IX_Y22
VIS_V1P0_S0IX_Y24
USB_V1P0_S3_M14
USB_V1P0_S3_U18
USB_V1P0_S3_U19
GPIO_V1P0_S3_AN25
USB3_V1P0_G3_Y19

C3

USB3_V1P0_G3_C3

C5

UNCORE_V1P0_G3_C5

B6

UNCORE_V1P0_G3_B6
CORE_V1P05_S3_AC32
CORE_V1P05_S3_Y32
UNCORE_V1P35_S0IX_F4_U36
UNCORE_V1P35_S0IX_F5_AA25
UNCORE_V1P35_S0IX_F2_AG32
UNCORE_V1P35_S0IX_F3_V36
VGA_V1P35_S3_F1_BD1
UNCORE_V1P35_S0IX_F6
UNCORE_V1P35_S0IX_F1_AG19
ICLK_V1P35_S3_F1_AJ19

ICLK_V1P35_S3_F2
VSSA_AN16
USB_VSSA_U16

REV = 1.15

VLV_M_D/BGA

?
VLV_M_D

8 OF 13

DRAM_V1P35_S0IX_F1_AD36

HDA_LPE_V1P5V1P8_S3_AM32

UNCORE_V1P8_S3_AM30

UNCORE_V1P8_S3_AN32

LPC_V1P8V3P3_S3_AM27

UNCORE_V1P8_G3_U24

USB_V3P3_G3_N18
USB_V3P3_G3_P18

UNCORE_V1P8_S3_U38

VGA_V3P3_S3_AN24

PCU_V1P8_G3_V25

3V_S5

PCU_V3P3_G3_N22

SD3_V1P8V3P3_S3_AN27

VSS_AD16

USB_HSIC_V1P24_G3_V18

VSS_AD18

UNCORE_V1P8_G3_AA18

RTC_VCC_P22

USB_V1P8_G3_N20

PMU_V1P8_G3_U25
CORE_V1P05_S3_AF33
CORE_V1P05_S3_AG33
CORE_V1P05_S3_AG35

CORE_V1P05_S3_U33
CORE_V1P05_S3_U35
CORE_V1P05_S3_V33

VSS_A3_A3

VSS_A49_A49

VSS_A5_A5
VSS_A51_A51
VSS_A52_A52

VSS_A6_A6

VSS_B2_B2
VSS_B52_B52
VSS_B53_B53

VSS_BE1_BE1

VSS_BE53_BE53

VSS_BG1_BG1

VSS_BG53_BG53

VSS_BH1_BH1

VSS_BH2_BH2
VSS_BH52_BH52
VSS_BH53_BH53

VSS_BJ2_BJ2
VSS_BJ3_BJ3

VSS_BJ5_BJ5
VSS_BJ49_BJ49
VSS_BJ51_BJ51
VSS_BJ52_BJ52

VSS_C1_C1

VSS_C53_C53

VSS_E1_E1

VSS_E53_E53

RESERVED_F1

PCIE_V1P0_S3_AK18

PCIE_V1P0_S3_AM18

3

AD36
AM32
AM30
AN32
AM27
U24
N18
P18
U38
AN24
V25
N22
AN27
AD16
AD18
V18
AA18
P22
N20
U25
AF33
AG33
AG35
U33
U35
V33
A3
A49
A5
A51
A52
A6
B2
B52
B53
BE1
BE53
BG1
BG53
BH1
BH2
BH52
BH53
BJ2
BJ3
BJ5
BJ49
BJ51
BJ52
C1
C53
E1
E53
F1
AK18
AM18

?

GND

UNCORE_V1P35_S0IX
UNCORE_V1P8_AN32_PWR
LPC_V3P3_PWR

V1P8_S5_PWR
PCU_V3P3_G3_PWR

UNCORE_V1P8_AN32_PWR
LPC_V3P3_PWR
PCU_V1P8_G3_V25
PCU_V3P3_G3_PWR
+VSDIO

VSS_AD18_AD16_PWR
USB_HSIC_V1P24_G3
V1P8_AA18_PEW
RTC_VCC_P22_PWR

V1P8_S5_PWR

CORE_V1P05

C263 1U/6.3V_4
C248 1U/6.3V_4
C260 1U/6.3V_4
C247 1U/6.3V_4
C268 1U/6.3V_4

C249 1U/6.3V_4
R395 *0_4/S
R114 *0_4/S

R555 *0_6/S
R554 *0_6
R407 *0_4/S
R121 *0_4/S

R464 *0_4/S
R453 *0_4/S

R110 *0_4/S
R400 *0_4/S

C270 1U/6.3V_4

C267 1u/6.3V_4
C264 1u/6.3V_4
C261 1u/6.3V_4
C265 0.47u/6.3V_4

C291 1U/6.3V_4
C304 1U/6.3V_4

2

GND

GND
PP1800_PCH

PP3300_PCH

PP1800_PCH_S5
PP1800_PCH
PP3300_PCH_S5
PP3300_PCH

GND
PP1800_PCH_S5

+3V_RTC
PP1800_PCH_S5

GND

GND

PP1000_PCH
GND

R460 *0_4/S
C346 1U/6.3V_4

PP1000_PCH_S5
GND

1

9

B B

A A

PP1350_PCH

GND

C296
1U/6.3V_4

PP1000_PCH

VIS_V1P0_S0IX_PW

C62
22U/6.3V_6

GND

5

C288
1uF/6.3_2

C59
22U/6.3V_6

GND

C303
1uF/6.3_2

C300
1uF/6.3_2

C61
22uF/6.3VT_6

C301
1uF/6.3_2

C298
1uF/6.3_2

1031 remove C285

USB3_V1P0_G3 LPC_V3P3_PWR

C269

C337

1uF/6.3_2

1uF/6.3_2

V1P8_S5_PWR RTC_VCC_P22_PWR

GND

4

C276
1U/6.3V_4

C309
1U/6.3V_4

C277
1U/6.3V_4

GND

C323
1U/6.3V_4

C272
1U/6.3V_4

C292

0.01U/25V_4

C275

0.01U/25V_4

3

GND

C74
*1U/6.3V_4

V1P8_AA18_PEW

VSS_AD18_AD16_PWR

GND

C332
1U/6.3V_4

GND

+VSDIO

C350
*1U/6.3V_4

PCU_V3P3_G3_PWR

C302

1U/6.3V_4

GND

UNCORE_V1P8_AN32_PWR

C282

C283

1U/6.3V_4

1U/6.3V_4

GND

2

1U/6.3V_4C307

GND

C274

C252

1U/6.3V_4

1U/6.3V_4

PROJECT : Peach

PROJECT : Peach

PROJECT : Peach

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom

NB5

NB5

NB5
HW

HW

HW

Valley 8/9 (Power 2)

Valley 8/9 (Power 2)

Valley 8/9 (Power 2)

Date: Sheet of

Date: Sheet of

Date: Sheet

1

GND

C293
1U/6.3V_4

9 40Monday, July 28, 2014

9 40Monday, July 28, 2014

9 40Monday, July 28, 2014

C294

0.1U/10V_4

of

1A

1A

1A

5

4

3

2

1

10

D D

?

U14I

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35

VLV_M_D/BGA

VLV_M_D

9 OF 13

VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70

AC36
AC38
AD19
AD21
AD25
AD32
AD33
AD47
AD7
AE1
AE11
AE12
AE14
AE3
AE4
AE40
AE42
AE43
AE45
AE46
AE48
AE50
AE51
AE53
AE6
AE8
AE9
AF10
AF12
AF25
AF32
AF47
AG16
AG25
AG36

?

AG38
AH41

AH45

AJ16
AJ21
AJ25
AJ27
AJ29

AJ30
AJ32
AJ33
AJ35
AJ38

AJ53
AK10
AK14
AK16
AK33
AK41
AK44
AM12
AM19
AM24
AM25
AM29
AM33
AM35
AM36
AM40

AH4

AH7
AH9

AJ1

AJ3

M28

REV = 1.15

A11
A15
A19
A23
A27
A31
A35
A39
A43
A47

AA1
AA16
AA19
AA21

AA3
AA32
AA35
AA38
AA53
AB10

AB4
AB41
AB45
AB47

C C

AB48
AB50
AB51

AC16
AC18
AC19
AC21
AC25
AC33
AC35

AB6

REV = 1.15

U14J

VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105

VLV_M_D/BGA

?
VLV_M_D

10 OF 13

VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140

AH47
AH48
AH50
AH51
AH6
AM44
AM51
AM7
AN1
AN11
AN12
AN14
AN22
AN3
AN33
AN35
AN36
AN38
AN40
AN42
AN43
AN45
AN46
AN48
AN49
AN5
AN51
AN53
AN6
AN8
AN9
AP40
AT12
AT16
AT19

?

AT24
AT27
AT30
AT35
AT38

AT47

AT52
AU24
AU30

AU38
AU51
AV12
AV13
AV14
AV18
AV19
AV24
AV27
AV30
AV35
AV38
AV47
AV51

AW13
AW19
AW27

AW3

AW35

AY10
AY22
AY32

AT4

AU1
AU3

AV7

REV = 1.15

U14K

VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175

VLV_M_D/BGA

?

VLV_M_D

11 OF 13

VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210

?

U14L

AY36
AY4
AY50
AY9
BA14
BA19
BA22
BA27
BA32
BA35
BA40
BA53
BB19
BB27
BB35
BC20
BC22
BC26
BC28
BC32
BC34
BC42
BD19
BD24
BD27
BD30
BD35
BE19
BE2
BE35
BE8
BF12
BF16
BF24
BF38

?

BF30
BF36

BG31
BG34
BG39
BG42
BG45
BG49

BJ11
BJ15
BJ19
BJ23
BJ27
BJ31
BJ35
BJ39
BJ43
BJ47

BF4

BJ7
C14
C31
C34
C39
C42
C45
C49
D12
D16
D24
D30
D36
D38
E19
E35

REV = 1.15

VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245

VLV_M_D/BGA

VLV_M_D

12 OF 13

VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280

E8
F19
F2
F24
F27
F30
F35
F5
F7
G10
G20
G22
G26
G28
G32
G34
G42
H19
H27
H35
J1
J16
J19
J22
J27
J32
J35
J40
J53
K14
K22
K32
K36
K4
K50

?

K9
L13
L19
L27
L35

M19
M26
M27
M34
M35
M38
M47
M51

N1

N16
N38
N51

P13
P16
P19
P20
P24
P32
P35
P38

P4
P47
P52

P9
T40

U1

U11
U12
U14
U21

U14M

VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
VSS291
VSS292
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315

VLV_M_D/BGA

REV = 1.15

?
VLV_M_D

13 OF 13

VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337
VSS338
VSS339
VSS340
VSS341
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350

U3
U30
U32
U40
U42
U43
U45
U46
U48
U49
U5
U51
U53
U6
U8
U9
V12
V16
V19
V21
V35
V40
V44
V51
V7
Y10
Y14
Y16
Y21
Y25
Y33
Y41
Y44
Y7
Y9

?

B B

A A

PROJECT : Peach

PROJECT : Peach

PROJECT : Peach

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom

NB5

NB5

NB5
HW

HW

5

4

3

2

HW

Valley 9/9 (GND)

Valley 9/9 (GND)

Valley 9/9 (GND)

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

1A

1A

1A

10 40Friday, July 25, 2014

10 40Friday, July 25, 2014

10 40Friday, July 25, 2014

5

INTEL Debug Port

4

3

2

1

PP1800_PCH_S5 PP1800_XDP_AB

D D

XDP_H_PREQ#

R89111K_2

R89121K_2

XDP_H_PRDY#
XDP_GPIO_DFX1

XDP_GPIO_DFX2
XDP_GPIO_DFX3

XDP_GPIO_DFX4

XDP_GPIO_DFX5
XDP_GPIO_DFX6

XDP_GPIO_DFX7
XDP_GPIO_DFX8

XDP_PMU_PWRBTN#PCH_PWRBTN_L

XDP_COREPW ROKCORE_PWROK_R

XDP_RTEST#XDP_RTEST_L
SMB_XDP_SDASMB_SOC_DATA

SMB_XDP_SCLSMB_SOC_CLK

XDP_H_TCK

XDP_H_PRDY#6

XDP_GPIO_DFX16
XDP_GPIO_DFX26

XDP_GPIO_DFX36
XDP_GPIO_DFX46

XDP_GPIO_DFX56
XDP_GPIO_DFX66

XDP_GPIO_DFX76
XDP_GPIO_DFX86

SOC_RSMRST#6,14

C199
*0.1uF_2

R528
*100K_4

3

1

PCH_PWRBTN_L14,27
CORE_PWROK_R6,27

*2N7002K
Q54

SMB_SOC_DATA7

SMB_SOC_CLK7

XDP_H_TCK6

3

2

1

PP1800_XDP_AB PP1800_XDP_CD

C C

PP3300_PCH_S5

C-test un-stuff

B B

XDP_RTEST_L

2

SOC_RSMRST# XDP_RSMRST#

R8910 *0_2/S

R8909 *0_2/S
R8908 *0_2/S

R8907 *0_2/S

C2-test change to short pad

SOC_RTEST# 6

*2N7002K
Q55

XDP_H_PREQ#_C6

APS(01/27 delete)

CN13

31

31

32

32

33

33

34

34

35

35

36

36

37

37

38

38

39

39

40

40

41

41

42

42

43

43

44

44

45

45

46

46

47

47

48

48

49

49

50

50

51

51

52

52

53

53

54

54

55

55

56

56

57

57

58

58

59

59

60

60

*SEC_BSH-030-01-L-D-A-TR

XDP_H_PREQ#_C

GND

1

OBSFN_A0

3

OBSFN_A1

5

GND

7

OBSDATA_A_0

9

OBSDATA_A_1

11

GND

13

OBSDATA_A_2

15

OBSDATA_A_3

17

GND

19

OBSFN_B0

21

OBSFN_B1

23

GND

25

OBSDATA_B_0

27

OBSDATA_B_1

29

GND

31

OBSDATA_B_2

33

OBSDATA_B_3

35

GND

37

HOOK0

39

HOOK1

41

VCC_OBS_AB VCC_OBS_CD

43

HOOK2

45

HOOK3

47

GND

49

SDA

51

SCL

53

TCK1

55

TCK0

57

GND

59

*74AUP1G34GW

OBSDATA_C_0
OBSDATA_C_1

OBSDATA_C_2
OBSDATA_C_3

OBSDATA_D_0
OBSDATA_D_1

OBSDATA_D_2
OBSDATA_D_3

ITPCLK/HOOK4

ITPCLK#/HOOK5

RESET#/HOOK6

GND_XDP_PRESENT

4

U10

R8915 *0R_2

GND
OBSFN_C0
OBSFN_C1

GND

GND

GND

OBSFN_D_0
OBSFN_D_1

GND

GND

GND

DBR#/HOOK7

GND

TDO

TRSTn

TDI

TMS

PP1800_PCH_S5

2
1

3 5

2

30

30

4

29

29

6

28

28

8

27

27

10

26

26

12

25

25

14

24

24

16

23

23

18

22

22

20

21

21

22

20

20

24

19

19

26

18

18

28

17

17

30

16

16

32

15

15

34

14

14

36

13

13

38

12

12

40

11

11

42

10

10

44

9

9

46

8

8

48

7

7

50

6

6

52

5

5

54

4

4

56

3

3

58

2

2

60

1

1

C8879
*0.1uF_2

XDP_H_PREQ#

C8878
*0.1uF_2

XDP_GPIO_S0_NC15
XDP_GPIO_DFX0

XDP_GPIO_S0_NC16
XDP_GPIO_S0_NC17

XDP_GPIO_S0_NC18
XDP_GPIO_S0_NC19

XDP_GPIO_S0_NC20
XDP_GPIO_S0_NC21

XDP_GPIO_S0_NC22
XDP_GPIO_S0_NC23

XDP_PMU_PLTRST# SOC_PLTRST#
XDP_PMU_RSTBTN#

XDP_H_TDO
XDP_H_TRST#
XDP_H_TDI
XDP_H_TMS
XDP_PRESENT_N

PP1000_PCH_S5

PP1800_PCH PP1800_XDP_CD

XDP_GPIO_S0_NC15 4

XDP_GPIO_DFX0 6

XDP_GPIO_S0_NC16 4
XDP_GPIO_S0_NC17 4

XDP_GPIO_S0_NC18 4
XDP_GPIO_S0_NC19 4

XDP_GPIO_S0_NC20 4
XDP_GPIO_S0_NC21 4

XDP_GPIO_S0_NC22 4
XDP_GPIO_S0_NC23 4

R89051K_2

R8914 *0_2/S

R8913 *0_2/S

C2-test change to short pad

R17654 *0_4
R17655 *0_4

SOC_REST_BTN#

R333 *short_4

C-test un-stuff

C2-test change to short pad

SOC_PLTRST# 6,14
SOC_REST_BTN# 6,18

XDP_H_TDO 6
XDP_H_TRST# 6
XDP_H_TDI 6
XDP_H_TMS 6

GND

PLACE C6601 closed to XDP HOOK PIN 54

GND

PLACE C6866 closed to XDP HOOK PIN48

C8882
*0.1uF_2

XDP_RTEST#

C88810.1uF_2

PLACE R6572 WITHIN 0.25" FROM XDP PIN

XDP_H_TDO

XDP_H_TMS
XDP_H_TDI

XDP_H_TCK

XDP_H_TRST#
XDP_PMU_PWRBTN#

PLACE R6866 closed to XDP

PLACE R6572 WITHIN 1.1" OF BUFFER PIN

XDP_H_PREQ#

XDP_PMU_RSTBTN#

C88800.1uF_2

PP3300_PCH_S5

R89041K_2

PP1800_XDP_AB

R295 51/F_4

R273 51/F_4
R286 51/F_4

R318 51/F_4

R289 51/F_4
R321 *30K/F_4

PP1800_PCH_S5

R323 200/F_4

PP1800_PCH

R8906*1K_2

GND

11

A A

PROJECT : Peach

PROJECT : Peach

PROJECT : Peach

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

NB5

NB5

NB5
HW

HW

5

4

3

2

HW

Custom
Date: Sheet of

Date: Sheet of

Date: Sheet of

CPU/PCH XDP

CPU/PCH XDP

CPU/PCH XDP

1

1A

1A

1A

11 40Friday, July 25, 2014

11 40Friday, July 25, 2014

11 40Friday, July 25, 2014

1

<DDR>

+SMDDR_VREF_DIMM +SMDDR_VREF_DIMM

M_A_A[15:0]2

A A

M_A_BS[2:0]2

M_A_CLKP02
M_A_CLKN02
M_A_CKE02

M_A_ODT02

M_A_CS#02
M_A_RAS#2
M_A_CAS#2
M_A_WE#2

M_A_DQSP12 M_A_DQSP32

M_A_DM22 M_A_DM02

M_A_DQSN12

B B

endor

M_A_DRAMRST#2

P/NV

Hynix

AKD5JGST400

Elpida

C C

DDR3L 1333Mhz 4 Gb

DDR3L 1600Mhz 4 GbAKD5JGST404

PP1350

C8

C10

10uF/6.3V_4

10uF/6.3V_4

Place these Caps near each X16 Memory Down

C154
1uF/6.3_2

+SMDDR_VREF_DQ0

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_BS0
M_A_BS1
M_A_BS2

M_A_CLKP0
M_A_CLKN0
M_A_CKE0

M_A_ODT0
M_A_CS#0
M_A_RAS#
M_A_CAS#
M_A_WE#

M_A_DQSP1

M_A_DM2 M_A_DM0

M_A_DQSN1

M_A_DRAMRST# M_A_DRAMRST#

R315
240/F_4

1 2

Distributed around all DRAM devices (CHA and CHB)

C7

C9

10uF/6.3V_4

10uF/6.3V_4

1uF/6.3_2

1uF/6.3_2

2

U2

C12

10uF/6.3V_4

C161
1uF/6.3_2

M8
H1

N3
P7
P3
N2
P8
P2
R8
R2

T8

R3

L7
R7
N7

T3

T7
M7

M2
N8
M3

J7
K7
K9

K1

L2

J3
K3

L3

F3
C7

E7
D3

G3
B7

T2

L8

J1

L1

J9

L9

DQL0

VREFCA

DQL1

VREFDQ

DQL2
DQL3

A0

DQL4

A1
A2

DQL5

A3

DQL6

A4

DQL7
A5
A6
A7

DQU0

A8

DQU1

A9

DQU2

A10/AP

DQU3

A11

DQU4

A12/BC

DQU5
DQU6

A13

DQU7

A14
A15

BA0

VDD#B2

BA1

VDD#D9
VDD#G7

BA2

VDD#K2
VDD#K8
VDD#N1

CK

VDD#N9

CK

VDD#R1

CKE

VDD#R9

VDDQ#A1

ODT
CS

VDDQ#A8

RAS

VDDQ#C1

CAS

VDDQ#C9

WE

VDDQ#D2
VDDQ#E9
VDDQ#F1

DQSL

VDDQ#H2

DQSU

VDDQ#H9

VSS#A9

DML

VSS#B3

DMU

VSS#E1

VSS#G8

DQSL

VSS#J2

DQSU

VSS#J8
VSS#M1
VSS#M9

VSS#P1

RESET

VSS#P9

VSS#T1

ZQ

VSS#T9

VSSQ#B1
VSSQ#B9
VSSQ#D1

VSSQ#D8

VSSQ#E2

NC#J1

VSSQ#E8

NC#L1

VSSQ#F9

NC#J9

VSSQ#G1
VSSQ#G9

NC#L9

100-BALL
SDRAM DDR3

R

AM _DDR3L

Hynix AKD5JGETW00--H5TC4G63AFR-PBA

C11

10uF/6.3V_4

C178

C155

1uF/6.3_2

1uF/6.3_2

BYTE2_16-23
BYTE1_8-15

E3

M_A_DQ20

F7

M_A_DQ23

F2

M_A_DQ17

F8

M_A_DQ22

H3

M_A_DQ21

H8

M_A_DQ18

G2

M_A_DQ16

H7

M_A_DQ19

D7

M_A_DQ10

C3

M_A_DQ13

C8

M_A_DQ11

C2

M_A_DQ12

A7

M_A_DQ14

A2

M_A_DQ8

B8

M_A_DQ15

A3

M_A_DQ9

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

C188
1uF/6.3_2

3

U3

M_A_DQ20 2
M_A_DQ23 2
M_A_DQ17 2
M_A_DQ22 2
M_A_DQ21 2
M_A_DQ18 2
M_A_DQ16 2
M_A_DQ19 2

M_A_DQ10 2
M_A_DQ13 2
M_A_DQ11 2
M_A_DQ12 2
M_A_DQ14 2
M_A_DQ8 2
M_A_DQ15 2
M_A_DQ9 2

PP1350 PP1350 PP1350 PP1350

M_A_DQSP02M_A_DQSP22

M_A_DM32 M_A_DM72M_A_DM12

M_A_DQSN02M_A_DQSN22
M_A_DQSN32 M_A_DQSN72

C218
1uF/6.3_2

+SMDDR_VREF_DQ0

M_A_DQSP0M_A_DQSP2
M_A_DQSP3 M_A_DQSP7

M_A_DQSN0M_A_DQSN2
M_A_DQSN3

1 2

1205 add 0.1uFx2 on
PP1350 for EMI request

C325

0.1uF_2

M8

VREFCA

H1

VREFDQ

N3

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_BS0
M_A_BS1
M_A_BS2

M_A_CLKP0
M_A_CLKN0
M_A_CKE0 M_A_CKE0 M_A_CKE0

M_A_ODT0
M_A_CS#0 M_A_CS#0 M_A_CS#0
M_A_RAS#
M_A_CAS#
M_A_WE#

M_A_ZQ2M_A_ZQ1

R311
240/F_4

C326

0.1uF_2

P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

M2
N8
M3

J7
K7
K9

K1
L2

K3

F3
C7

E7
D3

G3
B7

T2
L8

J1
L1
J9
L9

J3
L3

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15

BA0
BA1
BA2

CK
CK
CKE

ODT
CS
RAS
CAS
WE

DQSL
DQSU

DML
DMU

DQSL
DQSU

RESET
ZQ

NC#J1
NC#L1
NC#J9
NC#L9

R

AM _DDR3L

100-BALL
SDRAM DDR3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B2
VDD#D9
VDD#G7

VDD#K2

VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VDDQ#A1

VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

VSS#A9
VSS#B3
VSS#E1
VSS#G8

VSS#J2

VSS#J8
VSS#M1
VSS#M9

VSS#P1
VSS#P9
VSS#T1
VSS#T9

VSSQ#B1
VSSQ#B9
VSSQ#D1

VSSQ#D8

VSSQ#E2
VSSQ#E8

VSSQ#F9
VSSQ#G1
VSSQ#G9

4

BYTE0_0-7
BYTE3_24-31

E3

M_A_DQ6

F7

M_A_DQ5

F2

M_A_DQ3

F8

M_A_DQ0

H3

M_A_DQ7

H8

M_A_DQ4

G2

M_A_DQ2

H7

M_A_DQ1

D7

M_A_DQ24

C3

M_A_DQ26

C8

M_A_DQ28

C2

M_A_DQ27

A7

M_A_DQ25

A2

M_A_DQ30

B8

M_A_DQ29

A3

M_A_DQ31

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

5

U4

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_BS0
M_A_BS1
M_A_BS2

M_A_CLKP0
M_A_CLKN0

M_A_ODT0
M_A_RAS#

M_A_CAS#
M_A_WE#

M_A_ZQ3

R4
240/F_4

M8
H1

N3
P7
P3
N2
P8
P2
R8
R2

R3
R7

N7

M7

M2
N8
M3

K7
K9

K1

K3

C7

E7
D3

G3
B7

T8
L7

T3
T7

J7

L2
J3

L3

F3

T2
L8

J1
L1
J9
L9

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15

BA0
BA1
BA2

CK
CK
CKE

ODT
CS
RAS
CAS
WE

DQSL
DQSU

DML
DMU

DQSL
DQSU

RESET
ZQ

NC#J1
NC#L1
NC#J9
NC#L9

R

AM _DDR3L

100-BALL
SDRAM DDR3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

VSS#A9
VSS#B3
VSS#E1

VSS#G8

VSS#J2

VSS#J8
VSS#M1
VSS#M9

VSS#P1

VSS#P9

VSS#T1

VSS#T9

VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9

M_A_DQ6 2
M_A_DQ5 2
M_A_DQ3 2
M_A_DQ0 2
M_A_DQ7 2
M_A_DQ4 2
M_A_DQ2 2
M_A_DQ1 2

M_A_DQ24 2
M_A_DQ26 2
M_A_DQ28 2
M_A_DQ27 2
M_A_DQ25 2
M_A_DQ30 2
M_A_DQ29 2
M_A_DQ31 2

M_A_DQSP62
M_A_DQSP42

M_A_DM62 M_A_DM52
M_A_DM42

M_A_DQSN42

+SMDDR_VREF_DIMM
+SMDDR_VREF_DQ0

M_A_DQSP6
M_A_DQSP4

M_A_DM6 M_A_DM5
M_A_DM4

M_A_DQSN4

M_A_DRAMRST#

1 2

6

BYTE4_32-39
BYTE6_48-55

E3

M_A_DQ53

F7

M_A_DQ55

F2

M_A_DQ49

F8

M_A_DQ54

H3

M_A_DQ48

H8

M_A_DQ50

G2

M_A_DQ52

H7

M_A_DQ51

D7

M_A_DQ35

C3

M_A_DQ37

C8

M_A_DQ34

C2

M_A_DQ33

A7

M_A_DQ39

A2

M_A_DQ32

B8

M_A_DQ38

A3

M_A_DQ36

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

M_A_DQ53 2
M_A_DQ55 2
M_A_DQ49 2
M_A_DQ54 2
M_A_DQ48 2
M_A_DQ50 2
M_A_DQ52 2
M_A_DQ51 2

M_A_DQ35 2
M_A_DQ37 2
M_A_DQ34 2
M_A_DQ33 2
M_A_DQ39 2
M_A_DQ32 2
M_A_DQ38 2
M_A_DQ36 2

M_A_DQSP52
M_A_DQSP72

M_A_DQSN52M_A_DQSN62

+SMDDR_VREF_DIMM
+SMDDR_VREF_DQ0

M_A_DQSP5

M_A_DM7M_A_DM3M_A_DM1

M_A_DQSN5M_A_DQSN6
M_A_DQSN7

M_A_DRAMRST#

1 2

M_A_RAS#
M_A_CAS#
M_A_WE#
M_A_BS0
M_A_BS1
M_A_BS2
M_A_CKE0
M_A_CS#0
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_BS0
M_A_BS1
M_A_BS2

M_A_CLKP0
M_A_CLKN0

M_A_ODT0
M_A_RAS#

M_A_CAS#
M_A_WE#

M_A_ZQ4

R309
240/F_4

7

M8
H1

N3
P7
P3
N2
P8
P2
R8
R2

T8

R3

L7
R7
N7

T3

T7
M7

M2
N8
M3

J7

K7

K9

K1

L2

J3

K3

L3

F3
C7

E7
D3

G3

B7

T2

L8

J1

L1

J9

L9

R270 36/F_4
R269 36/F_4
R250 36/F_4
R278 36/F_4
R260 36/F_4
R283 36/F_4
R301 36/F_4
R261 36/F_4
R276 36/F_4
R275 36/F_4
R256 36/F_4
R272 36/F_4
R284 36/F_4
R277 36/F_4
R259 36/F_4
R248 36/F_4
R252 36/F_4
R262 36/F_4
R271 36/F_4
R265 36/F_4
R290 36/F_4
R249 36/F_4
R255 36/F_4C209
R296 36/F_4

U5

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15

BA0
BA1
BA2

CK
CK
CKE

ODT
CS
RAS
CAS
WE

DQSL
DQSU

DML
DMU

DQSL
DQSU

RESET
ZQ

NC#J1
NC#L1
NC#J9
NC#L9

R

AM _DDR3L

100-BALL
SDRAM DDR3

+DDR_VTT_RUN

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B2
VDD#D9
VDD#G7

VDD#K2

VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

VSS#A9
VSS#B3
VSS#E1

VSS#G8

VSS#J2

VSS#J8
VSS#M1
VSS#M9

VSS#P1
VSS#P9
VSS#T1
VSS#T9

VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8

VSSQ#F9
VSSQ#G1
VSSQ#G9

BYTE5_40-47
BYTE7_56-63

E3

M_A_DQ43

F7

M_A_DQ44

F2

M_A_DQ46

F8

M_A_DQ40

H3

M_A_DQ47

H8

M_A_DQ45

G2

M_A_DQ42

H7

M_A_DQ41

D7

M_A_DQ61

C3

M_A_DQ59

C8

M_A_DQ56

C2

M_A_DQ58

A7

M_A_DQ60

A2

M_A_DQ63

B8

M_A_DQ57

A3

M_A_DQ62

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

1024 change ODT PU to VTT
by Intel request

M_A_ODT0

M_A_CLKP0

R279 39/F_4

M_A_CLKN0

R280 39/F_4

1023 change cap from

0.2pF to 3.3pF

M_A_DQ43 2
M_A_DQ44 2
M_A_DQ46 2
M_A_DQ40 2
M_A_DQ47 2
M_A_DQ45 2
M_A_DQ42 2
M_A_DQ41 2

M_A_DQ61 2
M_A_DQ59 2
M_A_DQ56 2
M_A_DQ58 2
M_A_DQ60 2
M_A_DQ63 2
M_A_DQ57 2
M_A_DQ62 2

R305 36/F_4

C230 3.3p/50V_4C187

8

C146

0.1u/10V_4

+DDR_VTT_RUN_A

M_A_CLKN0M_A_CLKP0

12

+DDR_VTT_RUN

+DDR_VTT_RUN

C210

C162

C179

1uF/6.3_2

1uF/6.3_2

C163
1uF/6.3_2

C181
1uF/6.3_2

D D

+DDR_VTT_RUN

1

C145
1uF/6.3_2

C152
1uF/6.3_2

C156
1uF/6.3_2

C221
1uF/6.3_2

C144
1uF/6.3_2

C180
1uF/6.3_2

C148
1uF/6.3_2

1uF/6.3_2

C190
1uF/6.3_2

2

C142
1uF/6.3_2

C219
1uF/6.3_2

C220
1uF/6.3_2

+SMDDR_VREF_DIMM

C4
10uF/6.3V_4

C169
1uF/6.3_2

C212
1uF/6.3_2

12

C171

0.047u/25V_4

+SMDDR_VREF_DQ0

12

C189

C211

1uF/6.3_2

1uF/6.3_2

C164
1uF/6.3_2

12

C13

0.047u/25V_4

12

C175

0.047u/25V_4

12

C173

0.047u/25V_4

Place these Caps near Memory Down CA & DQ pin

12

12

C196

0.047u/25V_4

3

12

C195

0.047u/25V_4

C204

0.047u/25V_4

C200

0.047u/25V_4

M1 solution

PP1350

R314

4.7K/F_4

R304

4.7K/F_4

4

5

Vref_CA

+SMDDR_VREF_DIMM

12

C153

0.047u/25V_4

6

NB5

NB5

NB5
HW

HW

7

HW

M1 solution

PP1350

Vref_DQ

R330

+SMDDR_VREF_DQ0

4.7K/F_4

12

R327

4.7K/F_4

PROJECT : Peach

PROJECT : Peach

PROJECT : Peach

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Docum ent Number Rev

Size Docum ent Number Rev

Size Docum ent Number Rev
Custom

Custom

Custom

DDR3L MEMORY DOWNx16 A

DDR3L MEMORY DOWNx16 A

DDR3L MEMORY DOWNx16 A

Date: Sheet of

Date: Sheet of

Date: Sheet of

C202

0.047u/25V_4

12 40Friday, July 25, 2014

12 40Friday, July 25, 2014

12 40Friday, July 25, 2014

8

1A

1A

1A

5

<DDR>

+SMDDR_VREF_DIMM

+SMDDR_VREF_DIMM

M_B_A[15:0]3

D D

M_B_BS[2:0]3

M_B_CLKP03
M_B_CLKN03

M_B_CKE03

M_B_ODT03
M_B_CS#03
M_B_RAS#3
M_B_CAS#3
M_B_WE#3

M_B_DQSP33
M_B_DQSP23

M_B_DM33
M_B_DM23

M_B_DQSN33
M_B_DQSN23

C C

M_B_DRAMRST#3

M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

M_B_DQSP3
M_B_DQSP2

M_B_DRAMRST#

+SMDDR_VREF_DQ1

M_B_BS0
M_B_BS1
M_B_BS2

M_B_CLKP0
M_B_CLKN0

M_B_ODT0
M_B_RAS#

M_B_CAS#
M_B_WE#

M_B_DM3
M_B_DM2

M_B_DQSN3
M_B_DQSN2

M_B_ZQ1

R5
CHB@240/F_4

1 2

P/NVendor

Micron

AKD5JGSTL02 MT41K256M16H A-125:E

AKD5JGST400

Elpida

AKD5JGST404

PP1350

C159

10uF/6.3V_4

B B

Place these Caps near each X16 Memory Down

C168

C183
1uF/6.3_2

C185

10uF/6.3V_4

C184
1uF/6.3_2

10uF/6.3V_4

10uF/6.3V_4

U8

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ

J1

NC#J1

L1

NC#L1

J9

NC#J9

L9

NC#L9

100-BALL
SDRAM DDR3

C

HB@RAM _DDR3L

Hynix AKD5JGETW00--H5TC4G63AFR-PBA

C216

C194

C225
1uF/6.3_2

10uF/6.3V_4

C224
1uF/6.3_2

10uF/6.3V_4

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

VSS#G8

VSS#M1
VSS#M9

VSSQ#B1

VSSQ#B9
VSSQ#D1
VSSQ#D8

VSSQ#E2

VSSQ#E8

VSSQ#F9
VSSQ#G1
VSSQ#G9

C166

C165
1uF/6.3_2

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VSS#A9
VSS#B3
VSS#E1

VSS#J2
VSS#J8

VSS#P1
VSS#P9
VSS#T1
VSS#T9

BYTE2_16-23
BYTE3_24-31

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7
C3
C8
C2
A7
A2
B8
A3

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

M_B_DQ31
M_B_DQ24
M_B_DQ27
M_B_DQ28
M_B_DQ26
M_B_DQ29
M_B_DQ30
M_B_DQ25

M_B_DQ21
M_B_DQ22
M_B_DQ17
M_B_DQ19
M_B_DQ20
M_B_DQ18
M_B_DQ16
M_B_DQ23

4

BYTE0_0-7

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B2
VDD#D9
VDD#G7

VDD#K2

VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

VSS#A9

VSS#B3

VSS#E1

VSS#G8

VSS#J2

VSS#J8
VSS#M1
VSS#M9

VSS#P1
VSS#P9
VSS#T1
VSS#T9

VSSQ#B1

VSSQ#B9
VSSQ#D1
VSSQ#D8

VSSQ#E2

VSSQ#E8

VSSQ#F9
VSSQ#G1
VSSQ#G9

BYTE1_8-15

E3

M_B_DQ12

F7

M_B_DQ10

F2

M_B_DQ13

F8

M_B_DQ11

H3

M_B_DQ9

H8

M_B_DQ15

G2

M_B_DQ8

H7

M_B_DQ14

D7

M_B_DQ3

C3

M_B_DQ0

C8

M_B_DQ2

C2

M_B_DQ1

A7

M_B_DQ6

A2

M_B_DQ5

B8

M_B_DQ7

A3

M_B_DQ4

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

U9

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

M_B_ZQ2

R310
CHB@240/F_4

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ

J1

NC#J1

L1

NC#L1

J9

NC#J9

L9

NC#L9

C

HB@RAM _DDR3L

100-BALL
SDRAM DDR3

M_B_DQ31 3
M_B_DQ24 3
M_B_DQ27 3
M_B_DQ28 3
M_B_DQ26 3
M_B_DQ29 3
M_B_DQ30 3
M_B_DQ25 3

M_B_DQ21 3
M_B_DQ22 3
M_B_DQ17 3
M_B_DQ19 3
M_B_DQ20 3
M_B_DQ18 3
M_B_DQ16 3
M_B_DQ23 3

PP1350 PP1350 PP1350 PP1350

M_B_DQSP13
M_B_DQSP03

M_B_DM13
M_B_DM03

M_B_DQSN13
M_B_DQSN03

+SMDDR_VREF_DIMM
+SMDDR_VREF_DQ1

M_B_BS0
M_B_BS1
M_B_BS2

M_B_CLKP0
M_B_CLKN0

M_B_ODT0
M_B_CS#0M_B_CS#0 M_B_CS#0
M_B_RAS#
M_B_CAS#
M_B_WE#

M_B_DQSP1
M_B_DQSP0

M_B_DM1
M_B_DM0

M_B_DQSN1
M_B_DQSN0

M_B_DRAMRST# M_B_DRAMRST#

1 2

3

M_B_DQ12 3
M_B_DQ10 3
M_B_DQ13 3
M_B_DQ11 3
M_B_DQ9 3
M_B_DQ15 3
M_B_DQ8 3
M_B_DQ14 3

M_B_DQ3 3
M_B_DQ0 3
M_B_DQ2 3
M_B_DQ1 3
M_B_DQ6 3
M_B_DQ5 3
M_B_DQ7 3
M_B_DQ4 3

2

BYTE6_48-55

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

BYTE4_32-39

E3

M_B_DQ37

F7

M_B_DQ39

F2

M_B_DQ36

F8

M_B_DQ38

H3

M_B_DQ33

H8

M_B_DQ34

G2

M_B_DQ32

H7

M_B_DQ35

D7

M_B_DQ50

C3

M_B_DQ52

C8

M_B_DQ51

C2

M_B_DQ48

A7

M_B_DQ55

A2

M_B_DQ49

B8

M_B_DQ54

A3

M_B_DQ53

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

M_B_DQ37 3
M_B_DQ39 3
M_B_DQ36 3
M_B_DQ38 3
M_B_DQ33 3
M_B_DQ34 3
M_B_DQ32 3
M_B_DQ35 3

M_B_DQ50 3
M_B_DQ52 3
M_B_DQ51 3
M_B_DQ48 3
M_B_DQ55 3
M_B_DQ49 3
M_B_DQ54 3
M_B_DQ53 3

M_B_DQSP53
M_B_DQSP73

M_B_DM53
M_B_DM73

M_B_DQSN53
M_B_DQSN73

+SMDDR_VREF_DIMM
+SMDDR_VREF_DQ1

M_B_BS0
M_B_BS1
M_B_BS2

M_B_CLKP0
M_B_CLKN0

M_B_RAS#
M_B_CAS#
M_B_WE#

M_B_DQSP5
M_B_DQSP7

M_B_DM5
M_B_DM7

M_B_DQSN5
M_B_DQSN7

1 2

M_B_RAS#
M_B_CAS#
M_B_WE#
M_B_BS0
M_B_BS1
M_B_BS2
M_B_CKE0
M_B_CS#0
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

M_B_ZQ4

R316
CHB@240/F_4

U7

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

M_B_ZQ3

R312
CHB@240/F_4

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ

J1

NC#J1

L1

NC#L1

J9

NC#J9

L9

NC#L9

C

HB@RAM _DDR3L

100-BALL
SDRAM DDR3

VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

VSS#A9
VSS#B3
VSS#E1

VSS#G8

VSS#J2

VSS#J8
VSS#M1
VSS#M9

VSS#P1

VSS#P9

VSS#T1

VSS#T9

VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9

+SMDDR_VREF_DIMM
+SMDDR_VREF_DQ1

M_B_BS0
M_B_BS1
M_B_BS2

M_B_CLKP0
M_B_CLKN0
M_B_CKE0 M_B_CKE0M_B_CKE0 M_B_CKE0

M_B_ODT0 M_B_ODT0
M_B_CS#0
M_B_RAS#
M_B_CAS#
M_B_WE#

M_B_DQSP43
M_B_DQSP63

M_B_DM43
M_B_DM63

M_B_DQSN43
M_B_DQSN63

M_B_DQSP4
M_B_DQSP6

M_B_DM4
M_B_DM6

M_B_DQSN4
M_B_DQSN6

M_B_DRAMRST#

1 2

M8
H1

N3

M_B_A0M_B_A0

P7

M_B_A1

P3

M_B_A2

N2

M_B_A3

P8

M_B_A4

P2

M_B_A5

R8

M_B_A6

R2

M_B_A7

T8

M_B_A8

R3

M_B_A9

L7

M_B_A10

R7

M_B_A11

N7

M_B_A12

T3

M_B_A13

T7

M_B_A14

M7

M_B_A15

M2
N8
M3

J7
K7
K9

K1

L2

J3
K3

L3

F3
C7

E7
D3

G3
B7

T2

L8

J1

L1

J9

L9

R297 CHB@36/F_4
R302 CHB@36/F_4
R298 CHB@36/F_4
R292 CHB@36/F_4
R267 CHB@36/F_4
R288 CHB@36/F_4
R300 CHB@36/F_4
R291 CHB@36/F_4
R287 CHB@36/F_4
R264 CHB@36/F_4
R281 CHB@36/F_4
R282 CHB@36/F_4
R299 CHB@36/F_4
R293 CHB@36/F_4
R251 CHB@36/F_4
R247 CHB@36/F_4
R254 CHB@36/F_4
R266 CHB@36/F_4
R303 CHB@36/F_4
R258 CHB@36/F_4
R274 CHB@36/F_4
R257 CHB@36/F_4
R253 CHB@36/F_4
R294 CHB@36/F_4

U6

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15

BA0
BA1
BA2

CK
CK
CKE

ODT
CS
RAS
CAS
WE

DQSL
DQSU

DML
DMU

DQSL
DQSU

RESET
ZQ

NC#J1
NC#L1
NC#J9
NC#L9

100-BALL
SDRAM DDR3

C

HB@RAM _DDR3L

+DDR_VTT_RUN

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B2
VDD#D9
VDD#G7

VDD#K2

VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9

VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9

VSS#A9

VSS#B3

VSS#E1

VSS#G8

VSS#J2

VSS#J8
VSS#M1
VSS#M9

VSS#P1
VSS#P9
VSS#T1
VSS#T9

VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8

VSSQ#F9
VSSQ#G1
VSSQ#G9

1

BYTE5_40-47
BYTE7_56-63

E3

M_B_DQ43

F7

M_B_DQ40

F2

M_B_DQ46

F8

M_B_DQ44

H3

M_B_DQ47

H8

M_B_DQ45

G2

M_B_DQ42

H7

M_B_DQ41

D7

M_B_DQ58

C3

M_B_DQ61

C8

M_B_DQ57

C2

M_B_DQ62

A7

M_B_DQ60

A2

M_B_DQ63

B8

M_B_DQ56

A3

M_B_DQ59

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

1024 change ODT PU to VTT
by Intel request

M_B_ODT0

M_B_CLKP0
M_B_CLKN0

1023 change cap from

0.2pF to 3.3pF

M_B_DQ43 3
M_B_DQ40 3
M_B_DQ46 3
M_B_DQ44 3
M_B_DQ47 3
M_B_DQ45 3
M_B_DQ42 3
M_B_DQ41 3

M_B_DQ58 3
M_B_DQ61 3
M_B_DQ57 3
M_B_DQ62 3
M_B_DQ60 3
M_B_DQ63 3
M_B_DQ56 3
M_B_DQ59 3

R313 CHB@36/F_4

+DDR_VTT_RUN_B

R268 CHB@39/F_4
R285 CHB@39/F_4

C228 CHB@3.3p/50V_4

13

+DDR_VTT_RUN

+DDR_VTT_RUN

C147

CHB@0.1u/10V_4

M_B_CLKN0M_B_CLKP0

C223
1uF/6.3_2

C158

C222

1uF/6.3_2

1uF/6.3_2

+DDR_VTT_RUN

A A

C150
1uF/6.3_2

C141
1uF/6.3_2

C149
1uF/6.3_2

5

C143
1uF/6.3_2

C167
1uF/6.3_2

C182
1uF/6.3_2

C151
1uF/6.3_2

C193
1uF/6.3_2

C215
1uF/6.3_2

C1
10uF/6.3V_4

C192
1uF/6.3_2

C213
1uF/6.3_2

+SMDDR_VREF_DIMM

+SMDDR_VREF_DQ1

C157
1uF/6.3_2

12

C172
CHB@0.047u/25V_4

12

C197
CHB@0.047u/25V_4

C191
1uF/6.3_2

12

C174
CHB@0.047u/25V_4

12

C205
CHB@0.047u/25V_4

C170
1uF/6.3_2

12

C14
CHB@0.047u/25V_4

12

4

C214
1uF/6.3_2

12

C201
CHB@0.047u/25V_4

C176
CHB@0.047u/25V_4

12

C198
CHB@0.047u/25V_4

M1 solution

PP1350

Vref_DQ

R331

+SMDDR_VREF_DQ1

CHB@4.7K/F_4

12

C203
R328
CHB@4.7K/F_4

PROJECT : Peach

PROJECT : Peach

PROJECT : Peach

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Docum ent Number Rev

Size Docum ent Number Rev

Size Docum ent Number Rev
Custom

Custom

Custom

NB5

NB5

NB5
HW

HW

3

2

HW

DDR3L MEMORY DOWNx16 B

DDR3L MEMORY DOWNx16 B

DDR3L MEMORY DOWNx16 B

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

CHB@0.047u/25V_4

1A

1A

1A

13 40Friday, July 25, 2014

13 40Friday, July 25, 2014

13 40Friday, July 25, 2014

5

PWRON SEQUENCE

9/6 EC table says SERIRQ is OD pin, reserve for debugging
1128 remove R166, because SERIQR of TPM needs 3V
1128 reserve 0 ohm R387/R391 on VCCA and VCCB for debugging

D D

R166 *0_4

4

PWRON SEQUENCE

PP1800_PCH_S5

SOC_PWRBTN#6 PCH_PWRBTN_L 11,27

R515 10K_4

SOC_PWRBTN#

SOC_RSMRST#6,11

3

SOC_RSMRST#

R439

100K/F_4

GND

PP1800_PCH_S5

2

1

Q34 PJA138K

R445 *0_4/S

1022 un-stuff R182 for S5
leakage issue

R182 *30K/F_4

3

PP3300_PCH_S5

PCH_RSMRST_L 27

2

1

14

0220 remove SPI_SIO Interface,
Q35,Q36,Q37,Q44,R486,R484,R485,
R483,R426,R429,R427,R428

PP3300_PCH_S5PP1800_PCH_S5

U20

VCCA1VCCB

SOC_SERIRQ7

C C

PMC_SUS_STAT#6

USB OC

B B

SOC_SERIRQ

PP1800_PCH
SOC_KBC_SCI5
SOC_KBC_SMI6

PP1800_PCH_S5

USB_OC0#7,25

USB_OC1#7,25

3

A

2

GND

GND

PMC_SUS_STAT# PCH_SUS_STAT_L

*G2129TL1U

R159 10K_4

R170 10K_4

USB_OC0#

USB_OC1#

6

4

IRQ_SERIRQ

B

5

SWITCH_EN

OE

R171 *0_4/S

U21

6

A1

Y1

5

GND

VCC

4

A23Y2

*74LVC2G07GW

R174 *0_4/S

PP1800_PCH_S5

2

1

Q23 *PJA138K

PP1800_PCH_S5

1

Q20 PJA138K

PP1800_PCH_S5

1

Q17 PJA138K

3

2

2

R156 *10K_4

1
2

GNDPP3300_EC

R465 *10K_4

R99 10K_4

3

R86 10K_4

3

IRQ_SERIRQ 22,27

PP1800_PCH_S5

EC_SCI_L 27
EC_SMI_L 27

PP3300_EC
PCH_SUS_STAT_L 27

PP3300_EC
USB_OC0_L 27

PP3300_EC
USB_OC1_L 27

SLP_S3#6

PMC_SUSPWRDNACK

SLP_S3#

SLP_S0IX#

Stuffing for notifying EC

SOC_PLTRST#6,11

A A

PP1800_PCH_S5

1

Q49A PJ4N3KDW

SLP_S4#

Q49B PJ4N3KDW

SOC_PLTRST#

2

Q46 PJA138K

34

5

2

61

PP1800_PCH_S5

2

1

Q45 PJA138K

PP1800_PCH_S5

1

Q30 PJA138K

R491 *10K_4

3

PCH_SLP_S3_L

R517 *10K_4
R523 *10K_4

PCH_SLP_S4_L

R492 *10K_4

3

2

R143 10K_4

3

R142
*100K_4

PP3300_EC

PCH_SUSPWRDNACK 27PMC_SUSPWRDNACK6

PCH_SLP_S3_L 27

PP3300_ECPP1800_PCH_S5

PCH_SLP_S4_L 27SLP_S4#2,6

PP3300_EC
PCH_SLP_SX_L 27SLP_S0IX#6

PP3300_PCH

PLTRST# 20,22,27

PROJECT : Peach

PROJECT : Peach

PROJECT : Peach

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom

NB5

NB5

NB5
HW

HW

HW

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet

Level Shfiter (SOC_EC)

Level Shfiter (SOC_EC)

Level Shfiter (SOC_EC)

1

1A

1A

1A

of

14 40Friday, July 25, 2014

14 40Friday, July 25, 2014

14 40Friday, July 25, 2014

5

PP1800_PCH_S5

5

12

C389

0.1u/10V_4

4

R521
3G@10K_4

34

Q53A
3G@PJ4N3KDW

R214 3G@10K_4

2

Q48B

SIM_DETSIM_DET_C

LTE_SIM DET

12

C390

PP3300_WLAN

R113
10K_4

34

Q25A
PJ4N3KDW

R53 *10K_4

2

Q16B

+3V_LTE

R163
3G@10K_4

LTE SUSCLK

LTE_DISABLE_L 23

LTE_DISABLE

LTE_WAKE_L 23

LTE_WAKE

C2-test change

+3V_LTE

SIM_DET 23SIM_DET_C7

PP3300_WLAN

R45
10K_4

WIFI SUSCLK

RF_EN# 20

WIFI_DISABLE

PP3300_WLAN

WLAN_WAKE_L 20

WIFI WAKE

C2-test change

WIFI_SUSCLK 20

3G@10K_4

3G@PJ4N3KDW

R200

Q48A

PP1800_PCH

1

Q41 PJA138K

Q16A

U28

NC1VCC

2

A

GND3Y

3G@74AUP1G07GW

+3V_LTE +3V_LTE

R618
3G@10K_4

2

61

Q53B

R619

3G@10K_4

34

5

2

U29

NC1VCC

2

A

GND3Y

74AUP1G07GW

PP3300_WLAN

2

61

Q25B

PJ4N3KDW

R622

*10K_4

34

5

R59 0_4

5

+3V_LTEPP1800_PCH_S5

6 1

3G@PJ4N3KDW

R529 10K_4

3

PP1800_PCH_S5

5

0.1u/10V_4

4

R621
10K_4

5

PP3300_WLAN

6 1

*PJ4N3KDW

LTE

PP1800_PCH_S5

D D

C C

R167 3G@10K_4

PMC_SUSCLK16

PP1800_PCH_S5

R496 3G@10K_4

LTE_DISABLE#7

LTE_WAKE#6

3G@PJ4N3KDW

R620 *3G@0_4

LTE_WAKE# LTE_WAKE_L

WIFI

PMC_SUSCLK06

R49 10K_4

PP1800_PCH_S5

R80 10K_4

WIFI_DISABLE#6

SOC_PMC_WAKE#6

*PJ4N3KDW

SOC_PMC_WAKE# WLAN_WAKE_L

PP1800_PCH_S5

B B

LTE_SUSCLK 23

+3V_LTE

4

HW RESET

PP1800_PCH

R447 10K_4

EC_IN_RW_C

1023 EC_IN_RW is OD,
remove level shift and PU
to PP1800_PCH

Touch Screen(01/27 delete)

S0

S5

SATA

Track Pad

I2C_0_SDA_R7

1025 Delete complete SSD(connector and caps)

I2C_0_SDA_R

I2C_0_SCL_R7

I2C_0_SCL_R I2C_0_SCL

PP1800_PCH

1

Q26 *PJA138K

R137 *0_4/S

PP1800_PCH

2

1

Q47 FDV301N_G

R17658 *0_4

PP1800_PCH

1

Q62 FDV301N_G

R17659 *0_4

3

2

3

EC_IN_RW

3

I2C_0_SDA

2

3

R17657 2.2K_4

C8884
*10p/50V_4

R17656 2.2K_4

C8885
*10p/50V_4

EC_IN_RW 26EC_IN_RW_C7

TP_PWR

I2C_0_SDA 26

TP_PWR

I2C_0_SCL 26

S5 Power Good(+3V_S5)

0830 A24

S0iX Power Good

for proto type only, can remove at MP stage if S0ix is not needed

PP1000_PCH_SX

PP1350_PCH_SX

AC Detect

2

R48 SX@4.7K_4

R34 SX@4.7K_4

ACPRESENT6

PP3300_PCH_S5

1VS0IX_PG_1

1.35VS0IX_PG_1

2

C47
*SX@1000P/50V_4

2

C54
*SX@1000P/50V_4

3

2

1

1VS0IX_PG_2

Q5
SX@MMBT3904-7-F

1 3

1.35VS0IX_PG_2

Q9
SX@MMBT3904-7-F

1 3

PP1800_PCH_S5

1

Q22 PJA138K

R129

4.7K_4

Q21

2N7002K

2

2

PP3300_DSW

R134

4.7K_4

PP3300_PCH_S5_PG

3

Q24

2N7002K

1

R33
SX@4.7K_4

C49
SX@1000P/50V_4

R35
SX@4.7K_4

C55
SX@1000P/50V_4

3

ACINACPRESENT

1

PP3300_PCH_S5_PG 27

9/9

PP3300_DX

R31
SX@4.7K_4

PP1000_PCH_SX_PG 27

2

Q8

1 3

SX@DTC144EUA

9/9

PP3300_DX

R36
SX@4.7K_4

PP1350_PCH_SX_PG 34

2

Q7

1 3

SX@DTC144EUA

ACIN 26,27,28

15

eDP control pin

PP3300_DX

PP1800_PCH

R556

4.7K_4

SOC_EDP_BLON 17

3

Q43

2

2N7002K

1

R357

100K_4

2

5

R548

4.7K_4

SOC_EDP_BLON_C_Q

3

Q59
PJA138K

1

A A

SOC_EDP_BLON_C4

SOC_DISP_ON_C4

PP1800_PCH

SOC_DPST_PWM_C4

1205 To prevent the backlight flash, add a pull down on SoC_EDP_BLON_C and using
double inverting OD FETs structure

4

R350 *10K_4

SOC_DISP_ON_C

R351 *10K_4

SOC_DPST_PWM_C

Q4A PJ4N3KDW

34

5

R347 10K_4
R346 10K_4

2

61

Q4B PJ4N3KDW

SOC_DISP_ON 17

PP3300_DXPP1800_PCH

SOC_DPST_PWM 17

PROJECT : Peach

PROJECT : Peach

PROJECT : Peach

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom

Level Shfiter (SOC_DEV)

Level Shfiter (SOC_DEV)

NB5

NB5

NB5
HW

HW

3

2

HW

Level Shfiter (SOC_DEV)

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

1A

1A

1A

15 40Friday, July 25, 2014

15 40Friday, July 25, 2014

15 40Friday, July 25, 2014

5

Power management Board

4

3

2

1

16

D D

C8903
*0.1U/25V_4

C C

B B

Power Button Rest

EC_CD_RST

C8901

0.047UF_4

GND

1

2

3

Stuff while the EC no stuff

EC_MRDLY_RST

GND

C8904

0.047U/10V_4

U59

MRDLY

GND

RESET#

CD

G677L308A31U

VCC

MR#

6

5

3VPCU_RST#

4

BUTTON_ONKEY_R

PP3300_RTC

C8902

0.1U/10V_2

R17685 0_4

PP3300_RTC

R1768347K/F_4

R17684 0_4

R17682 *100K/F_4

2

Q64

3

DMG1012T-7(SOT523)

R17680 10K_2

1

PP3300_RTC

GND

PP3300_RTC

PWR_BTN_L 18,26,27

PD15

1N4448WS-7-F

R17686

21

1K/F_4

PP3300_DSW_EN 27,29

A A

PROJECT : Peach

PROJECT : Peach

PROJECT : Peach

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom

NB5

NB5

NB5
HW

HW

5

4

3

2

HW

PM Board/Reset PBT

PM Board/Reset PBT

PM Board/Reset PBT

Date: Sheet of

Date: Sheet of

Date: Sheet

1

1A

1A

1A

of

16 40Tuesday, July 29, 2014

16 40Tuesday, July 29, 2014

16 40Tuesday, July 29, 2014

1

eDP Power(VGA)

A A

SOC_DISP_ON15

R20 *0_4/S

C217

1u/6.3V_4

PP3300_DX

EDP_ON

R21

100K_4

U11

5
4
3

G5243AT11U

eDP panel control(VGA)

B B

C C

SOC_DPST_PWM15

SOC_EDP_BLON15

EC_BL_DISABLE_L27

Camera level shift(05/13)

R17661
*0_2/S

VDD_1V8_PMU_1

DMIC_CLK_L24

DMIC_DAT_L24

D D

C8888

0.1uF_2

1

To Camera Level Shift

3
5
4

2

IN
IN
ON/OFF

D2 RB500V-40

U57

VCCA
A1
A2

GND

TXS0102DCUR

AL000102K00

2

1

OUT

2

GND

R341 *0_4/S

R340 2.2K_4

EC_BL_DISABLE#

R17666 *0_4
R17667 *0_4

7

VDD_3V3_SYS_1

VCCB

B1

8

B2

1

OE

6

2

3

4

5

6

eDP(VGA)

C227

0.01u/16V_4

LCDVCC

C34

22u/6.3V_8

CCD power(CCD)

PP3300_DX

10uF/6.3V_4

4

CCD

DMIC(ADO)

DMIC_CLK_C
DMIC_DATA_C

C208

*150p/50V_4

EDP_HPD4

C207
47P/50V_4

R326 *0_4/S

EDP_AUXP4

EDP_AUXN4

EDP_TXP04
EDP_TXN04

EDP_TXP14
EDP_TXN14

VIN

1029 eDP power
change to PIC fuse

eDP

CCD USB(CCD)

CCD_PWR

R14 *0_6/S

C33

C30
*10p/50V_4

5

C29

0.1U/10V_4

C8891

10uF/6.3V_4

0.5A

6

LCDVCC_1

EC_BL_PWM_CONN

EC_BL_EN_CONN

R339 *0_4/S

R17 *0_8/S

DMIC_CLK_CDMIC_CLK_L
DMIC_DATA_CDMIC_DAT_L

C226
*0.1u/10V_4

R338

*100K_4

R17664
*0_2/S

*7.5K/F_4

DMIC_CLK_C
DMIC_DATA_C

C8889

0.1uF_2

*Clamp-Diode

C28
*2.2u/6.3V_6

R17663

C8890

3

C31
*0.1u/10V_4

R342

*100K_4 C27 0.1u/10V_4

CCD_PWRPP1800_PCH

CCD_PWR

12

C229

0.1u/10V_4

R17662

*7.5K/F_4

12

C35
*Clamp-Diode

CCD_PWR

R7 600,0.3A
R6 600,0.3A

C20 0.1u/10V_4
C19 0.1u/10V_4

C18 0.1u/10V_4
C17 0.1u/10V_4

C26 0.1u/10V_4

EDP_HPD_CONN

1 2

F1 KMC5S150RY24

LCD_VIN

C25

4.7u/25V_8

USBP2+7
USBP2-7

7

CN33

LVDS_CONN_30P

Max 1.5A

LCDVCC

DMIC_CLK
DMIC_DAT

EC_BL_PWM_CONN
EC_BL_EN_CONN

EDP_AUXP_C
EDP_AUXN_C

EDP_TXP0_C
EDP_TXN0_C

EDP_TXP1_C
EDP_TXN1_C

LCD_VIN

150mA

USBH2-_R
USBH2+_R

Max 1.5A

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

51519-0304n-001-30p-l

DFFC30FR149

C206
1000p/50V_4

R8 *0_4/S

USBH2+_R
USBH2-_R

R9 *0_4/S

PROJECT : Peach

PROJECT : Peach

PROJECT : Peach

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom

NB5

NB5

NB5
HW

HW

HW

7

EDP/CCD/DMIC/TS

EDP/CCD/DMIC/TS

EDP/CCD/DMIC/TS

Date: Sheet of

Date: Sheet of

Date: Sheet of

31 32

8

17

17 40Friday, July 25, 2014

17 40Friday, July 25, 2014

17 40Friday, July 25, 2014

8

1A

1A

1A

5

4

3

2

1

PIN7 OD
PIN14 OD

GOOGLE Debug Port(MPC)

PIN19 OD
PIN22 OD
PIN28 OD

50 pin BTB is MUST, don't use 42 pin

D D

PCH_SPI_CS0#_R6,20 PCH_SPI_SI_R 6,20

PCH_SPI_SO_R6,20

SPI_HOLD#_BIOS6,20

C C

EC_JTAG_TCK20,27 PWR_BTN_L 16,26,27
EC_JTAG_TMS20,27 EC_JTAG_TDI 20,27

B B

SD3_CD#5,23

EC_JTAG_TDO20,27

PP3300_EC

EC_UART0_TX20,27

PP3300_INA

HDMI_MB_HP19

H_PROCHOT#5,27,33

R540 *0_4/S

R536 *0_4/S
R545 *0_4/S
R208 *0_4/S R216 *0_4/S

R537 GD@10_4
R522 *GD@10_4

Socket part number AXK750147G

CN9

1

1

PCH_SPI_CS0#_R
PCH_SPI_SO_R
SPI_HOLD#_BIOS

SOC_UART_TX_R

GPIO_SD_DECT

EC_JTAG_TCK
EC_JTAG_TMS EC_JTAG_TDI

EC_JTAG_TDO EC_JTAG_RTCK

EC JTAG

EC UART

EC_UART_TXD
PP3300_INA_R
I2C_SDA_INA I2C_SCL_INA
GPO_HPD GPIO_SPI_WP
GPIO_PROC_HOT#

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

25

25

27

27

29

29

31

31

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

GD@AXK750147G

10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

2

2

4

4

6

6

8

8

10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

PIN30 OD
PIN37 OD
PIN38 OD

SOC SPI

PCH_SPI_CLK_R
PCH_SPI_SI_R

GPIO_EC_RST#
SOC_UART_RX_R
SOC_UART_PWR

GPIO_PWR_BTN#

SYS_RESET#
EC_UART_RXD

SOC UART

PIN39 OD
PIN41 OD
PIN43 OD
PIN44 OD
PIN45 OD
PIN46 OD
PIN47 OD
PIN48 OD

R544 GD@10_4

R506 GD@10_4
R525 *GD@0_4

R524 *0_4/S
R538 *0_4/S

PIN49 OD
PIN50 OD

PP1800_PCH_ME

EC_JTAG_TCK

PP3300_EC

18

PCH_SPI_CLK_R 6,20

A130828

EC_RST# 20,26,27

SOC_REST_BTN# 6,11

EC_UART0_RX 20,27

I2C_SCL_INA_RI2C_SDA_INA_R

GPIO_SPI_WP 6,20
LID_OPEN_L 22,27

1021 change footprint and PN

SOC_UART_TX7
PCH_UART_TXD20,27
SOC_UART_RX7
PCH_UART_RXD20,27

SOC_UART_PWR

A A

R505 *0_4/S
R532 *GD@0_4
R499 *0_4/S
R504 *GD@0_4

R543 *GD@0_4
R535 *0_4/S

SOC_UART_TX_R

SOC_UART_RX_R

PP3300_EC
PP1800_PCH

9/6 using optional instead of
level shifted, defult is from
SoC

5

4

3

9/13 add pull up

PP3300_INA

R207 GD@4.7K_4
R199 GD@4.7K_4

NB5

NB5

NB5
HW

HW

HW

I2C_SCL_INA_R
I2C_SDA_INA_R

PROJECT : Peach

PROJECT : Peach

PROJECT : Peach

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom
Date: Sheet of

Date: Sheet of

Date: Sheet

2

Google Debug

Google Debug

Google Debug

of

18 40Friday, July 25, 2014

18 40Friday, July 25, 2014

18 40Friday, July 25, 2014

1

1A

1A

1A

5

4

3

2

1

HDMI Cost Reduced level shift (HDM) HDMI connector (HDM)

1128 change HDMI CMC L2, this part

INT_HDMITX2N4
INT_HDMITX2P4

INT_HDMITX1N4
INT_HDMITX1P4

INT_HDMITX0N4
INT_HDMITX0P4

D D

INT_HDMICLK+4
INT_HDMICLK-4

Layout Notes:
Place decoupling CAPs
close to Connector

PP3300_DX

C C

C42 0.1u/10V_4
C44 0.1u/10V_4

C56 0.1u/10V_4
C57 0.1u/10V_4

C40 0.1u/10V_4
C41 0.1u/10V_4

C53 0.1u/10V_4
C48 0.1u/10V_4

R74 *SHORT_4

1115 remove R60 and change
R74 to Short PAD and size
to 0402

PP3300_HDMI

INT_HDMITX0N_C
INT_HDMITX0P_C

INT_HDMICLK+_C
INT_HDMICLK-_C

3

2

1

Q15

2N7002K

INT_HDMITX2N_C
INT_HDMITX2P_C

INT_HDMITX1N_C
INT_HDMITX1P_C

R349

R345

510/F_4

510/F_4

R362 510/F_4

R359 510/F_4

R366

R371

510/F_4

510/F_4

INT_HDMICLK+_CONN

INT_HDMICLK-_CONN

R356
510/F_4

R352
510/F_4

is recommended by Intel
1202 change HDMI CMC L2 to

DLP11TB800UL2L as Intel's recommendation
1205 L2 change back to DLP11SA900HL2

INT_HDMICLK+_C
INT_HDMICLK-_C

PP5000

Q2

3

IN

AP2331SA-7

OUT

GND

R41 *0_4/S

R37 *0_4/S

1
2

C32
*220p/50V_4

INT_HDMICLK-_CONN

D1
*14V/38V/100P_4

INT_HDMITX2P_C
INT_HDMITX2N_C

INT_HDMITX1P_C
INT_HDMITX1N_C

INT_HDMITX0P_C
INT_HDMITX0N_C

INT_HDMICLK+_CONN
INT_HDMICLK-_CONN

HDMI_DDCCLK_MB
HDMI_DDCDATA_MB

HDMI_5V
HDMI_MB_HP

RV1

*5V/0.2p_4

1115 change R22
to short PAD

1121 remove R22

12

C39

*1000p/50V_4

CN16

1

D2+

2

D2 Shield

3

D2-

4

D1+

5

D1 Shield

6

D1-

7

D0+

8

D0 Shield

9

D0-

10

CK+

11

CK Shield

12

CK-

13

CE Remote

14

NC

15

DDC CLK

16

DDC DATA

17

GND

18

+5V

19

HP DET

HDMI_CONN_19P

C37
*1000p/50V_4

hdmi-c128j4-k1903-l-19p

SHELL1
SHELL3

SHELL4
SHELL2

20
22

23
21

DFHD19MR397

1021 change footprint for
HDMI,need check layout file
again

19

HDMI DDC (HDM)

󵚩󵚩󵚩󵚩󴼚

EMI

1115 change R72/R73
to short PAD

PP1800_PCH

1030 HDMI DDC
pulled up to
HDMI_5V by intel
request

1121 remove R72/R73

PP1800_PCH

HDMI_DDCCLK_SW4

B B

HDMI_DDCDATA_SW4

PP1800_PCH

HDMI_DDCDATA_SW

HDMI-detect (HDM)

R66 4.7K_4

R64 4.7K_4

PP1800_PCH

R27
10K_4

2

1

Q13 FDV301N_G

2

1

Q12 FDV301N_G

R50 4.7K_4

3

R52 4.7K_4

3

D4

RB500V-40

HDMI_DDCCLK_MBHDMI_DDCCLK_SW

D3

RB500V-40

HDMI_DDCDATA_MB

HDMI_5V

HDMI_5V

INT_HDMITX2P_C

R8882 100/F_4

INT_HDMITX2N_C

INT_HDMITX1P_C

R8880 100/F_4

INT_HDMITX1N_C

INT_HDMITX0P_C

R8883 100/F_4

INT_HDMITX0N_C

INT_HDMICLK+_CONN

R8881 100/F_4

INT_HDMICLK-_CONN

󴼚HDMI CONNECTOR(CN16)ESD

󴼚󴼚

INT_HDMITX2P_C
INT_HDMITX2N_C
INT_HDMITX1P_C
INT_HDMITX1N_C

INT_HDMITX0P_C
INT_HDMITX0N_C
INT_HDMICLK+_CONN
INT_HDMICLK-_CONN

HDMI_DDCCLK_MB
HDMI_DDCDATA_MB
HDMI_5V
HDMI_MB_HP

D44 *5V/0.2p_4

1 2

D47 *5V/0.2p_4

1 2

D48 *5V/0.2p_4

1 2

D45 *5V/0.2p_4

1 2

D49 *5V/0.2p_4

1 2

D52 *5V/0.2p_4

1 2

D51 *5V/0.2p_4

1 2

D50 *5V/0.2p_4

1 2

D54 *5V/0.2p_4

1 2

D55 *5V/0.2p_4

1 2

D53 *5V/0.2p_4

1 2

D56 *5V/0.2p_4

1 2

INT_HDMI_HPD4

3

A A

5

1

2

HDMI_MB_HP

Q3
2N7002K

R24
100K/F_4

4

HDMI_MB_HP 18

PROJECT : Peach

PROJECT : Peach

PROJECT : Peach

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

NB5

NB5

NB5
HW

HW

3

2

HW

Custom
Date: Sheet of

Date: Sheet of

Date: Sheet of

HDMI

HDMI

HDMI

19 40Friday, July 25, 2014

19 40Friday, July 25, 2014

1

19 40Friday, July 25, 2014

1A

1A

1A

1

2

3

4

5

6

7

8

WIFI/BT COMBO (NGFF E KEY)

+WL_VDDPP1800_PCH

R615

R616

*0_4

*0_4

+WL_VIO

C385

A A

WLAN_OFF_L POWER DOWN LAN CHIP from EC?
WIFI_DISABLE_L disable Antenna from PCH?

EC_JTAG_TMS18,27
EC_JTAG_TCK18,27
EC_JTAG_TDI18,27

EC_RST#18,26,27

EC_UART0_TX18,27

PCH_UART_TXD18,27
PCH_UART_RXD18,27

RF_EN#15
WLAN_OFF_L27

R47 *10K_4

EC_UART0_RX18,27

WIFI_SUSCLK15

LTE_SOUT23
LTE_SIN23

(Low Active)

+WL_VDD

B B

NFC pin list

1.pin68-->NFC_ANT_N

2.pin66-->NFC_ANT_P

3.pin42-->NFC_WI_IN (1.8V)

4.pin40-->NFC_SWP2_IO (1.8V)

5.pin38-->NFC_ACTIVE (3.3V)

5.pin73-->NFC_NOT_ALLOWED (3.3V)

LTE Coexistence pin list (based on V0.2 spec

1.pin48-->LTE_SOUT (3.3V)

2.pin46-->LTE_SIN (3.3V)

*0.1u/10V_4

NFC_ANT_N

TP27

NFC_ANT_P

TP26

NFC_VDDANT

TP25

+WL_VIO

RF_EN#

R55 *0_4/S

PDN#

R46 *0_4/S

R8901 *0_2
R8900 *0_2
R8902 *0_2

R8889 *0_2
R8890 *0_2
R8891 *0_2
R8892 *0_2

TP29
TP1

TP28

TP30

TP3

TP2

PLTRST#14, 22,27

PIN54: disable Antenna

PDN#
WLAN_RST

PIN52: power down CHIP

LTE_SOUT
LTE_SIN

NFC Security

NFC_WI_IN
NFC_SWP2_IO
EC_JTAG_JTMS_R
EC_JTAG_JTCK_R
EC_JTAG_JTDI_R
WIFI_UART_RX

WIFI_UART_TX

EC_RST#_NGFF

BT_LED

WLAN_LED1# USBP3-

+WL_VDD

1023 change NGFF E key footprint and PN

+WL_VDD

CN3

74

3.3Vaux

72

3.3Vaux

70

NC

68

NFC_ANT_N

66

NFC_ANT_P

64

NFC_VDDANT

62

ALERT

60

I2C_CLK

58

I2C_DATA

56

W_DISA BLE

54

PDN#

52

PERST0#

50

SUSCLK_3 2KHz

48

LTE_SOUT

46

LTE_SIN

44

NC

42

NFC_WI_IN

40

NFC_SWP 2_IO

38

NC

36

UART_CTS

34

UART_RTS

32

UART_Rx

30

KEY

28

KEY

26

KEY

24

KEY

22

UART_Tx

20

UART_Wake

18

GND

16

LED#2

14

PCM_IN

12

PCM_OUT

10

PCM_SYNC

8

PCM_CLK

6

LED#1

4

3.3Vaux

2

3.3Vaux

0829 A20

NGFF

RESERVED
RESERVED

PERn1
PERp1

PEWake0#

CLKREQ0#
REFCLKN0

REFCLKP0

PERn0
PERp0

SLOT A-SD

SDIO_RESET

SDIO_WAKE

SDIO_DAT3
SDIO_DAT2
SDIO_DAT1
SDIO_DAT0

SDIO_CMD

SDIO_CLK

USB_D-

USB_D+

GND76GND

77

WLAN_NGFF CONN(Type 2230)_80152-1721

PETn1
PETp1

PETn0
PETp0

75

GND

73
71
69

GND

67
65
63

GND

61
59

WAKE/REQ 53, 55 OD

57

GND

55

WLAN_WAKE_L

53
51

GND

49
47
45

GND

43
41
39

GND

37
35
33

GND

31

KEY

29

KEY

27

KEY

25

KEY

23

EC_JTAG_JTDO_R

21

DEBUG_SPI_WP_ME_ROM_R

19

DEBUG_SPI_HOLD_ME_R

17

DEBUG_SPI_CS#_R

15

DEBUG_SPI_SCLK_R

13

DEBUG_SPI_MISO_R

11

DEBUG_SPI_MOSI_R

9
7

GND

5
3
1

GND

USBP3+

WLAN_WAKE_L 15

CLK_PCIE_WLANN 6

CLK_PCIE_WLANP 6

PCIE_RX0-_WLAN 5

PCIE_RX0+_WLAN 5

PCIE_TX0-_WLAN 5
PCIE_TX0+_WLAN 5

R8894 *0_2
R8893 *0_2
R8895 *0_2R8797 *0_2
R8896 *0_2
R8898 *0_2
R8897 *0_2
R8899 *0_2

USBP3- 7
USBP3+ 7

PP3300_WLAN

+WL_VDD

R42
10K_4

BT

R39 *0_8/S

2

Q10 PJA138K

3

R44 *0_4

EC_JTAG_TDO 18,27
GPIO_SPI_WP 6,18
SPI_HOLD#_BIOS 6,18
PCH_SPI_CS0#_R 6,18

PCH_SPI_CLK_R 6,18

PCH_SPI_SO_R 6,18

PCH_SPI_SI_R 6,18

1

C52
10u/6.3V_6

PP1800_PCH

PCIE_CLKREQ_WLAN#PCIE_CLKREQ_WLAN#_Q

C244

0.1u/10V_4

+WL_VDD

C50
*0.1u/10V_4

PCIE_CLKREQ_WLAN# 5

C51
*0.1u/10V_4

20

Video Codec (M.2 LGA 1216-S3) (VGA)
(0213 delete VP8/VP9)

C C

D D

PROJECT : Peach

PROJECT : Peach

PROJECT : Peach

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom

NB5

NB5

NB5
HW

HW

1

2

3

4

5

6

HW

7

WIFI / BT / Image Codec

WIFI / BT / Image Codec

WIFI / BT / Image Codec

Date: Sheet of

Date: Sheet of

Date: Sheet

8

1A

1A

1A

of

20 40Friday, July 25, 2014

20 40Friday, July 25, 2014

20 40Friday, July 25, 2014

5

4

3

2

1

21

D D

1025 Delete complete SSD(connector and caps)

C C

EMMC (CBS)

B B

U27

EMMC_CMD5
EMMC_CLK5

EMMC_D05
EMMC_D15
EMMC_D25
EMMC_D35

EMMC_D45
EMMC_D55
EMMC_D65
EMMC_D75

EMMC_RST#5

1029 change R358 to 0

m by intel request

oh
1121 remove R365

1029 remove pulled up resistors for eMMC data and cmd

A A

1211 add back pulled up resistors
1212 all Pulled up resistors of eMMC data/cmd to be un-stuffed,

and R361 change to 47K ohm as well

5

PP1800_PCH

R396 *47K_4
R401 *47K_4
R469 *47K_4
R393 *47K_4
R406 *47K_4
R405 *47K_4
R404 *47K_4
R417 *47K_4
R361 *47K_4

EMMC_D0
EMMC_D1
EMMC_D2
EMMC_D3
EMMC_D4
EMMC_D5
EMMC_D6
EMMC_D7
EMMC_CMD

4

push-pull mode

1128 remove R358 by
intel requst and has
confirmed with EMI

EMMC_CMD
EMMC_CLK

EMMC_D0
EMMC_D1
EMMC_D2
EMMC_D3

EMMC_D4
EMMC_D5
EMMC_D6
EMMC_D7

EMMC_RST#

IC FLASH(153P) SDIN8DE4-64G(BGA)TOPBSQ

W5

CMD

W6

CLK

H3

DAT0

H4

DAT1

H5

DAT2

J2

DAT3

J3

DAT4

J4

DAT5

J5

DAT6

J6

DAT7

U5

RST

SDIN8DE4-64G

fbga169-samsung-kmhog0000m-0_5s

3

VCCQ
VCCQ
VCCQ
VCCQ
VCCQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VDDI

K6
AA5
W4
Y4
AA3

T10

VCC

U9

VCC

M6

VCC

N5

VCC

K2
R10

VSS

U8

VSS

M7

VSS

P5

VSS

AA6
Y5
Y2
AA4
K4

for host interface

VCCQ_EMMC

C8874

0.1U/10V_4

VCC_EMMC

EMMC_VDDI

iNAND's internal power node

C8877

0.1U/10V_4

C8873

0.1U/10V_4

C8876

0.1U/10V_4

2

R8888 *0_4/S

C8875

4.7U/6.3V_4

R8887 *0_6/S

C8872

4.7U/6.3V_4

PP1800_PCH

PP3300_PCH

PROJECT : Peach

PROJECT : Peach

PROJECT : Peach

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom

NB5

NB5

NB5
HW

HW

HW

SSD NGFF/ EMMC

SSD NGFF/ EMMC

SSD NGFF/ EMMC

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

1A

1A

1A

21 40Friday, July 25, 2014

21 40Friday, July 25, 2014

21 40Friday, July 25, 2014

TPM (CLG)

1

2

4 x100nF (place close to device VDD/GND pins)

3

PP3300_DX

4

TPM_VDD

TPM_VDD

A A

TPM_VDD

0411 FAE : install R342 value is 4K7,
and PIN7 wo an internal PD

B B

12

R38
*9655@20K_4

TPM_GPIO

R51 9655@0_4

R43 *9655@4.7K_4

TPM_PP

PROG IC OTHER(28P)SLB9655TT1.2FW4.32GOOG

C58
9655@0.1U/10V_4

pin5,6,9,19,25,28 are difference between both

13

14

6
2

7

U13

GPIO/NC6
NC2

PP
NC13

NC14

TPM SLB9655

8

NC8

12

NC12

3

NC3

1

NC1

GND[1]4GND[2]11GND[3]18GND[4]/NC25

C45
9655@0.1U/10V_4

LRESET#[2]/NC9

25

R57 9655@0_4

10

VDD[4]

VDD[3]/NC5

VDD[1]/NC19

NC28/LPCPD#

LRESET#[1]

5
24

VDD[2]

19

21

LCLK

22

LFRAME#

17

LAD3

20

LAD2

23

LAD1

26

LAD0

28
16

9
27

SERIRQ

15

NC15

1211 co-layout ST and Infineon TPM, if change to ST,
R56,R57,R60,R72,R38, ST PN is ST33ZP24AR28PVSM

C245

0.1U/10V_4

R60 *0_4/S
R72 *0_4/S

TPM_RST_R

C250
SP@0.1U/10V_4

If stuff ST TPM,C250
change to 10uF
(CH6101M9B02)

near pin 21 as possible

C246 10p/50V_4

0411 FAE : a 0ohm between pin9 to LRESET signals

R56 *0_4/S

R28 10K_4

SERIRQ_R

R353 *0_4

1128 add pullup 10K on
SERIRQ_R to TPM_VDD

R61

2.2_6

PCLK_TPM 7

LPC_LFRAME# 7,27

LPC_LAD3 7,27
LPC_LAD2 7,27
LPC_LAD1 7,27
LPC_LAD0 7,27

PLTRST# 14,20,27

TPM_VDD

IRQ_SERIRQ 14,27

22

LED(UIF)

PP3300_RTC

C C

C8006

0.1U/10V_4

D D

LID SENSOR

2

1

OUT

VDD

S

N

GND

U32

APX9132H

3

1

LID_OPEN_R

D23

1

1

2

*3301D-ESD

2

LED3

LID_OPEN_L

R83921K/F_4

2

PP3300_RTC

2 1

3P WHITE LED

C8871 *TVM0G5R5M261R_4

NB5

NB5

NB5
HW

HW

3

HW

R8852 360/J_4

PWR_LED#

PROJECT : Peach

PROJECT : Peach

PROJECT : Peach

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom
Date: Sheet of

Date: Sheet of

Date: Sheet of

TPM SLB9655 / LED

TPM SLB9655 / LED

TPM SLB9655 / LED

PWR_LED# 27LID_OPEN_L 18,27

22 40Friday, July 25, 2014

22 40Friday, July 25, 2014

4

22 40Friday, July 25, 2014

1A

1A

1A

PWR LED

A

Thermal Sensor(THM)

PP3300_ THM

C43 0.1 u/10V_4

1022 change thermal IC
solution

OVERT#

EC_RST#_R27

2

U12 TMP432ADG SR

10

SCLK

9

SDA

8

ALERT#

7

OVERT#
GND6DN2

ADDR=0x4C

Place oo PCB BOT
Local Temp.

3

1

VCC

2

DP1

3

DN1

4

DP2

5

1030 Thermal IC VDD has two option, ome is PP3300_DSW(
=PP3300_EC), another is PP3300_DX, default is stuffing to
DSW rail

PP3300_ THM

R370 *0_ 4/S

R77 10K_4

USB2_ILIM_SEL

PP3300_ DSW

R67 *0_ 4/S

C46
2200p/50V_4

C86
2200p/50V_4

H_THRMDA

H_THRMDC
H_THRMDA2

H_THRMDC2

R376 *0_4
R377 *0_4/ S

OVERT#EC_RST#_R

USB3_STATUS_L 25

4 4

3 3

EC_SMB2_ CLK27
EC_SMB2_ DATA27

ALERT#5

ALERT#

1025 remove Q31 becasue PU to PP3300_DSW at EC side already

USB Switch Current Control

2 2

USB_ILIM_ SEL25,27

1

Q18 2N700 2K

B

Place oo PCB TOP
Remote Temp.

Base: PIN 1
Emitter: PIN 2
Collector: PIN 3

Q52

1

MMBT3904LP-7

2 3

Q56

1

MMBT3904LP-7

2 3

Place oo PCB ?
Remote Temp.

PP3300_ DX
PP3300_ DSW

FUNCTION DB

LTE(MNC)

PP3300_ DSW

C122

1U/6.3V_4

PP3300_ LTE_EN27

SDIO3_PW R_EN#5

U23
TPS22965DSGR

1

VIN_01
VIN_022VOUT_01

C104

R154
*4.7K_4

3

ON

4

VBIAS

R194 *0_ 4/S

R175
100K_4

PP3300_ DXPP1800_ PCH

3

2

1

R539
*4.7K_4

LTE_PWREN_R

PP5000_ DSW

2200p/50V_4

1025 add level shifter for
LTE SUSCLK

C

VOUT_02

PAD

9

1202 add
C285 for
U18 input
inrush
current

SDIO3_PW R_EN

Q58
*PJA138K

8
7
6

CT

5

GND

LTE_PWREN_R

12

C112
*0.047u/25V_4

C285

1u/6.3V_ 4

MAX 3A

C121

0.1u/10V _4

C113
470p/50V_4

USBH1+25
USBH1-25

LTE

PP1800_ PCH

PP3300_ DX

U18

5

IN

4

IN

3

ON/OFF

*G5243AT11U

115 U18 footprint

1
change to 5 pin which
is same as eDP power
switch

+3V_LTE

R8884
10K_4

SD3_CD#

R17665 *0_ 6/S

OUT

GND

Cardreader

R8848 *0_2/S

R8849 *0_2/S

PP1800_ PCH

1

2

SD3_D05
SD3_D15
SD3_D25
SD3_D35
SD3_CLK5
SD3_CMD5
SD3_CD#5,18

SD3_WP5

R8864
10K_4

SD3_WP

1A

*0.1U/10V _4

C342

D

C8860

C8861

10uF/6.3V_4

0.1uF_2

SD3_D0
SD3_D1
SD3_D2
SD3_D3
SD3_CLK
SD3_CMD
SD3_CD#
SD3_WP

USBH3+25

USBH3-25

VCC_SD

USBH3+
USBH3- USBH3-_Card

USB_WW AN_DP1_L
USB_WW AN_DM1 _L

LTE_SOUT20
LTE_SIN20
SIM_DET15

LTE_SUSCLK15
LTE_DISABLE_L15
LTE_WAK E_L1 5

+3V_LTE

1101 correct C351 footprint

C351
*4.7U/6.3V_4

VCC_SD

3A

R8885 *0_2/S

R8886 *0_2/S

LTE_SOUT
LTE_SIN
SIM_DET
LTE_SUSCLK
LTE_DISABLE_L
LTE_WAK E_L

C8862
10uF/6.3V_4

C8892
10uF/6.3V_4

USBH3+_Card

E

PP3300_ DX

23

CN31

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

DFFC30FR099

50501-0300n-001-30p-l

1 1

PROJECT : Peach

PROJECT : Peach

PROJECT : Peach

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom

NB5

NB5

NB5
HW

HW

A

B

C

D

HW

DB/ALS/Thermal sensor

DB/ALS/Thermal sensor

DB/ALS/Thermal sensor

Date: Sheet of

Date: Sheet of

Date: Sheet of

E

1A

1A

1A

23 40Friday, July 25, 2 014

23 40Friday, July 25, 2 014

23 40Friday, July 25, 2 014

5

AUDIO CODEC (ADO)

BOM Change to 0_4 due to material shortage

C359

I2S_BCLK_R5

I2S_LRCLK_R5

I2S_DIN_R5

I2C_1_SDA_R7

I2C_1_SCL_R7

MUX_AUD_INT1#6

PP1800_CODEC_AVDD

DMIC_DAT_L17
DMIC_CLK_L17

10mils

R220 *0_4

R236 10K_4
R233 10K_4

L13 60ohm@100MHz_4

C358

C364

1U/16V_4

1U/16V_4

I2S_MCLK6

I2S_DOUT_R5

R219 *0_4/S
R225 10K_4

RCVN

C138
1U/10V_4

PP3300_ADO_SW

MICBIAS

RCVP

RCVN

R230 10K_4

AGND

I2C_MIC_SW_SDA
I2C_MIC_SW_SCL

AJACK_MICPRES_L

5

C135
1U/10V_4

PP1800_PCH

D D

C C

B B

A A

R217 *0_6/S

0.1U/10V_4

Audio Headset Switch

PP3300_RTC

L14 100ohm@100MHz

C368

0.1U/10V_4

1209 reserve R220
connection from RCVP to
MIC_DET as back up in
case driver needs to be
through codec using
JACKSNS pin

MIC_DET

PP3300_RTC

C357
1U/16V_4

R228 *0_4/S

C120 1U/10V_4
C119 1U/10V_4

C133
1U/16V_4

R234

2.2K_4

PP1800_CODEC_AVDD

Close to PIN38Close to PIN26

C360

0.1U/10V_4

AGND

CODEC_CLK_IN

CODEC_INT_OD_L

CODEC_MIC_L_PRCVP
CODEC_MIC_L_N

CODEC_C1P

CODEC_C1N

13

16

U26

VDD1

VDD2

11

MICP

12

MICN

TS3A225E

2

SDA

1

SCL

TS3A225ERTER (QFN)

C363
10u/6.3V_4

35
33

32
30
31

37
36

34

19
18
20
21

39

40

4

U25

MCLK
BCLK

LRCLK
SDIN
SDOUT

SDA
SCL

IRQ_L

IN1/DMD
IN2/DMC
IN3
IN4

C1P

C1N

3

CPVDD

2

CPVSS

AGND

15

14

SLEEVE_SENSE

28

27

DVDD

DVDDIO

MAX98090AETL+T

R8497 *0_8/S

6

7

RING2

SLEEVE

TIP_SENSE

RING2_SENSE

DET_TRIGGER

GND13PGND

AGNDAGND

26

AVDD

9

5

GND210/MIC_PRESENT8ADDR_SEL

17

38

HPVDD

RCVP/LOUTL

RCVN/LOUTR

SLEEVE_SENSE
RING2_SENSE
SLEEVE
RING2

HPL

13

14

SPKLVDD

SPKRVDD

SPKLP
SPKLN
SPKRP
SPKRN

MICBIAS

HPSNS

JACKSNS

DGND29AGND25HPGND1SPKRGND10SPKLGND

4

+5VA

C365

0.1U/10V_4

AGND

C116
1U/10V_4

C118
1U/10V_4

C367
10U/6.3V_4

AGNDAGNDAGND

R238 5.6_4
R239 5.6_4

C117

2.2U/6.3V_4

R223 *0_4/S

HPL
HPR

R240
*4.7K_4

AGND

R237
*4.7K_4

MICBIAS

AGND

C366
1U/16V_4

16

L_SPK+

15

L_SPK-

12

R_SPK+

11

R_SPK-

22

8
9

5

RCVN

7

MIC_DET

4

HPOUT-L

HPL

6

HPOUT-R

HPR

23

REF

24

BIAS

17

3

R17671; R17672
for ESD

C8854 1000p/50V/X7R_4
C8853 1000p/50V/X7R_4
C8855 1000p/50V/X7R_4
C8857 1000p/50V/X7R_4
C8856 1000p/50V/X7R_4

R17671 0_4
R17672 0_4

R176
330K_4

2

Q38
2N7002K

C99
1U/6.3V_4

HP_JD_L

2

SOC DET

DET_TRIGGER5 AJACK_MICPRES_L5

PP1800_PCH

3

1

AGND

HEADPHONE/Mic combo(ADO)

SLEEVE SLEEVE_R
SLEEVE_SENSE

RING2_SENSE

HPR

L9 80ohm@100MHz
R231 0_4

L8 80ohm@100MHz
R222 0_4

L11 0_6

L10 0_6

10P/50V_4

C132

C137
10P/50V_4

RING2_RRING2

*100P/50V_4

1

24

PP1800_PCH

AJACK_MICPRES_LDET_TRIGGER

R124 10K_4

combo jack
Normal open

1025 change
headphone footprint
and PN, need check
pin out again

1025 remove pin7

CN37

SLEEVE_R
HPL_SYSHPL

HP_JD_L
HPR_SYS
RING2_R

C130

C124
*100P/50V_4

SLEEVE

AGNDAGND

HPR_SYS
HPL_SYS
RING2

ESD 2'nd CY00G050B00
ESD 2'nd CY00G050B00

1
4

5
6

3
2

audio-ajrb5-6kk000-6p
DFTJ06FR671

Audio Jack

1 2

D21 *14V/38V/100P_4

1 2

D22 *14V/38V/100P_4

1 2

D20 *14V/38V/100P_4

1 2

D19 *14V/38V/100P_4

AGND

PIN1 --> MIC
PIN2 --> AGND
PIN3 --> R
PIN4 --> L
PIN5 --> TRANSFER
PIN6 --> HPD

0206 change jack
same as peach1.0

Codec PWR 5V(ADO)

CN14

AVDD1

+5VA

C369
10u/6.3V_4

AGNDAGND

Ramp add

1 2

L_SPK+_1

D25 *5V/0.2p_4

1 2

L_SPK-_1

1
2
345

6

R_SPK-_1
R_SPK+_1

D26 *5V/0.2p_4

1 2

D27 *5V/0.2p_4

1 2

D28 *5V/0.2p_4

PROJECT : Peach

PROJECT : Peach

PROJECT : Peach

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom

NB5

NB5

NB5
HW

HW

HW

MAX98090/HP/SPK

MAX98090/HP/SPK

MAX98090/HP/SPK

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

1A

1A

1A

24 40Thursday, July 31, 2014

24 40Thursday, July 31, 2014

24 40Thursday, July 31, 2014

PP5000

C125

C126
*10U/6.3V_6

*0.1u/10V_4

PP3300_RTC PP3300_RTC

R243 330K_4

HP_JDDET_TRIGGER_SW

R244 *0_4/S

C140
1U/6.3V_4

AGNDAGND

4

R242
330K_4

3

2

Q51
2N7002K

1

HP_JD_L

3

Internal Speaker

40mil for each signal

L_SPK+

R229 *0_6/S

L_SPK-

R232 *0_6/S

R_SPK+

R235 *0_6/S

R_SPK-

R241 *0_6/S

C128

10P/50V_4

C134
10P/50V_4

DIGITAL

C136
10P/50V_4

2

ANALOG

L12 PBY160808T-181Y-N_2A_6

C370

0.1u/10V_4

L_SPK+_1
L_SPK-_1
R_SPK+_1
R_SPK-_1

C139
10P/50V_4

SPK_CONN_4P

DFHD04MR293

88266-040xx-xxx-4p-l

follow 0c1 pin define

5

USB3.0(USB)

USB3PWR

80 mils (Iout=2A)

Ramp add D29,change C78 220u

D D

USB3_RXN07
USB3_RXP07

USB3_TXN07
USB3_TXP07

C71 0.1u/ 10V_4
C67 0.1u/ 10V_4

1121 change USB3 CMC L5,L3, this part

s recommended by Intel

i
1202 change USB3 CMC L5,L3 to

DLP11TB800UL2L as Intel's recommendation
1205 Swap L3,L5 pin for layout smoothly

TVM0G5R5M261R_4

USBP0-_L
USBP0+_L

USB3_RXN0
USB3_RXP0

USB3_TXN0_C
USB3_TXP0_C

D29

HOLE(OTH)

1204 change Hole1 to be battery

C C

enablefunction

HOLE1
*O-Y07A-1

1 3

HOLE8
*O-Y07A-1

1 3

2

5

HOLE14

HOLE15

*H-C315D98P2

*H-C315D98P2

B B

1

HOLE20
*H-O217X177D138X98P2

R625 *0_4

BATT_EN#

2

BATT_EN# 26,28

ROM WP#

SPI_WP_R

HOLE16
*H-C315D98P2

1

R519 1K_4

HOLE17
*H-C315D98P2

4

1

SPI_WP_ME 6,27

HOLE18

HOLE19

*H-C315D98P2

*H-C315D98P2

1

1

1

USB3PWR

C66

C78

+

220U/6.3V/ESR35_3528

R93 *0_4/S

R87 *0_4/S
R106 *0_4/S

R101 *0_4/S

R82 *0_4/S

R78 *0_4/S

1000p/50V_4

USB HUB

1021 3G@HUB@ means HUB will be stuffed if 3G/LTE exists

USBP1-7
USBP1+7

3G@HUB@18P/50V_4

1021 change footprint
for USB3,need check
layout file again

USBP0-_C
USBP0+_C

USB3_RXN0_R
USB3_RXP0_R

USB3_TXN0_R
USB3_TXP0_R

USBP0-_C
USBP0+_C
USB3_RXN0_R
USB3_RXP0_R
USB3_TXN0_R
USB3_TXP0_R

USBP1­USBP1+

XIN

4

USB 3.0 Connector

USB3.0_CONN_9P

1
2
3
4
5
6
7
8
9

D8 *5V/0.2p_4

1 2

D9 *5V/0.2p_4

1 2

D10 *5V/0.2p_4

1 2

D7 *5V/0.2p_4

1 2

D6 *5V/0.2p_4

1 2

D5 *5V/0.2p_4

1 2

R566 *0_4/S
R570 *0_4/S

1 2

C6

D30
BZT52-B5V6S(5.6V)

USB_OC0#
USB3_ILIM_SEL

USB3_PWR_EN

USB3_CTL2
USB3_CTL3

R100
100K_4

TP64

+3V_USB

U1

27

28

VREG

DD-0
DD+0
DD-1

GL852G-OHG12

DD+1
VCC_A_5
DD-2
DD+2

RREF8VCC_A_99XIN10XOUT11DD-312DD+313VCC_A_14

QFN28

+3V_USB

USBH_RREF

R571
3G@HUB@10K/F_4

3

U15

1

IN

9

STATUS

13

FAULT

4

ILIM_SEL

5

EN

6

CTL1

7

CTL2
CTL38DP_OUT

TPS2546RTER/GL887T-OCGO

USB_ILIM_SEL23,27

EEPROM_SDA

PGANG

PSELF

nOVRP2

nOVRP1

23

24

22

26

VCC

GANG

OVR#[1]25OVR#[2]

I2C_SDA

VCC_D
SELFPWR

OVR#[3]
OVR#[4]

TEST

RESET#

DD+4

DD-4

GND

14

29

+3V_USB

XOUT

XIN

GND

USBH3+
USBH3-

R565
*3G@HUB@47K_4

12

OUT

15

ILIM_LO

16

ILIM_HI

17

GND_PAD

14

GND

11

DM_IN

10

DP_IN

2

DM_OUT

3

1

Q14 2N7002K

52.4mA

21

+3V_USB_D

20

nOVRP3

19

nOVRP4

18

EEPROM_SCL

17

RESET#_USB

16
15

3G@HUB@GL852G-OHG12

USBH3+ 23

USBH3- 23

Cardreader

80 mils (Iout=2A)

USB3PWR
ILIM_LO

ILIM_HI

(RILIM_HI 1.96A)

USBP0-_L
USBP0+_L

USBP0­USBP0+

2

3

IOS_typ(mA) = 50,250/{RILIM_XX(KΩ)+0.1}

Follow vendor's suggestion(Close to pin 21)

R1 3G@HUB@0_4

TP63

change 619 ohm for eye diagram

USB Charger

PP5000

C73

0.1U/10V_4

USB3_STATUS_L23

USB3_PWR_EN27

USB_CTL127

CN17

VBUS

1

D-

2

D+

3

GND

4

SSRX-

5
6

SSRX+

7

GND

8

SSTX­SSTX+

9

12

3G@HUB@12MHz

PP3300_EC

11111010131312

DFHS09FS035

usb-c19090-90905-l-9p

RILIM_LO is optional and the ILIM_LO pin may be left unconnected if the following conditions are met:

1. ILIM_SEL is always set high

2. Load Detection - Port Power Management is not used

3. Mouse / Keyboard wake function is not used
If conditions 1 and 2 are met but the mouse / keyboard wake function is also desired, it is recommended to use
RILIM_LO < 80.6 kΩ.
The following equation programs the typical current limit:
(1)
RILIM_XX corresponds to either RILIM_HI or RILIM_LO as appropriate.

USB_H1_N3
USB_H1_P3

USBH1-23

LTE

USBH1+23

USBH2-25

USB2.0

USBH2+25

Y1

34

XOUT

C3
3G@HUB@18P/50V_4

GNDGND

12

C392

*100U/6.3V_3528

USB_OC0#7,14

R69 10K_4
R68 10K_4

USB_H1_N3
USB_H1_P3
USBH1­USBH1+

+3V_USB
USBH2­USBH2+

3G@HUB@0.1U/10V_4

80 mils (Iout=2A)

TP65

RESET#_USB

2 1

USB_HUB_5V

1
2
3
4
5
6
7

+3V_USB

C383

GND

USB3PWR

R105

25.5K/F_4

USBP0- 7

USBP0+ 7

25

(RILIM_LO 1.07A)

R104
47K_4

Touch Screen(01/27 delete)

R70 10K_4

USB3_ILIM_SEL

nOVRP1
nOVRP2
nOVRP3
nOVRP4
PSELF

PGANG
USBH_RREF

PP3300_EC

USB2_STATUS_L

R390 *0_4/S

1021 If USB2 external IO has wake up feature, HUB
power need to be available in S5

PP3300_PCH_S5

R573 *0_6/S

PP3300_DX

R567 *3G@HUB@0_6

+3V_USB

C377
3G@HUB@0.1U/10V_4

1 2

GND

+3V_USB

R22 3G@HUB@10K_4
R568 3G@HUB@10K_4
R2 3G@HUB@10K_4
R3 3G@HUB@10K_4
R564 3G@HUB@10K_4

R569 3G@HUB@100K/F_4
R572 3G@HUB@619/F_4

GND

2

TP66

+3V_USB

Follow vendor's suggestion(Close to GL850G-31)

15 mil

C379
3G@HUB@0.1U/10V_4

1 2

GND

+3V_USB

C382
3G@HUB@10UF/6.3V_4

GND

Follow vendor's suggestion(Close to pin 28)

C378
3G@HUB@0.1U/10V_4

1 2

C381
3G@HUB@0.1U/10V_4

1 2

C5
3G@HUB@1U/6.3V_4

1

C380
3G@HUB@1U/6.3V_4

C384
3G@HUB@0.1U/10V_4

1 2

1

HOLE21
*H-O185X177D106X98P2

1

HOLE22
*H-C177D98P2

1

HOLE23
*H-O138X98B217X177D138X98PB

A A

1

5

USB 2.0

USB2_PWR_EN27

R8839
*100K/F_4

R8840
*100K/F_4

PP3300_PCH

USB_OC1#7,14

USB2_PWR_EN

4

USB_OC1#

100 mils (Iout=2.1A)

PP5000 USB2PWR

R8855 *0_4/S

*TVM0G5R5M261R_4

USB_OC1#_R

VC12

5
3

C793

4.7U/6.3V_6

Vin
OC
EN4GND

G524A1T11U

U30

1

Vout

2

Active High

USB2PWR

USB2PWR

C741 470p/50V/X7R_4
C5648 0.1U/10V/X5R_4
C791 470p/50V/X7R_4

+

C782 220U/6.3V/ESR35_3528

VC13 TVM0G5R5M261R_4

3

60mil

USBH2-25

USBH2+25

2

USBH2­USBH2+

0713
R574 , R575 -->10 ohm

USB2PWR

R574 10/F_4

R575 10/F_4

*EGA-0402

NB5

NB5

NB5
HW

HW

HW

1021 change footprint for USB2
1022 SWAP pin1~pin4

CN38

1

VDD

GND6

2

USBP1-_C

D-

GND5

3

USBP1+_C

D+

4

GND1

GND7

12

12

RV2

RV3

*EGA-0402

Close to USB CONN

PROJECT : Peach

PROJECT : Peach

PROJECT : Peach

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom
Date: Sheet of

Date: Sheet of

Date: Sheet of

GND8

USB_CONN

ub2-c14763-10403-l-4p-l

DFHS04FR781

USB3/UB2/Charger/Hole

USB3/UB2/Charger/Hole

USB3/UB2/Charger/Hole

1

6
5

7
8

1A

1A

1A

25 40Friday, July 25, 2014

25 40Friday, July 25, 2014

25 40Friday, July 25, 2014

5

K/B (KBC)

KB_ROW1227
KB_ROW0827
KB_ROW0927
KB_ROW1127
KB_ROW1027

KB_ROW0527

6
5
4

6
5
4

KB_ROW0627
KB_ROW0327

KB_COL0027

KB_ROW0127
KB_ROW0427

KB_COL0327

KB_ROW0027
KB_COL0527
KB_COL0427

KB_ROW0727
KB_COL0627
KB_COL0727
KB_COL0127

R213 *0_4/S

KB_ROW09

KB_ROW11

KB_ROW06

KB_ROW03

D D

PWR_BTN_L16,18,27

KB_ROW12

C8800*15pF_2

KB_ROW08

C8801*15pF_2

KB_ROW09

C8802*15pF_2

KB_ROW11

C8803*15pF_2

KB_ROW10

C8804*15pF_2

KB_ROW05

KB_ROW12

KB_ROW08

KB_ROW10

KB_ROW05

C8805*15pF_2
C8806*15pF_2
C8807*15pF_2

KB_ROW06
KB_ROW03

U54

1

I/O 1

2

GND
I/O 23I/O 3

U52

1

I/O 1

2

GND
I/O 23I/O 3

I/O 4
VDD

AZC099

I/O 4
VDD

AZC099

C C

KB_ROW12
KB_ROW08
KB_ROW09
KB_ROW11
KB_ROW10

KB_ROW05
KB_ROW06

KB_ROW03
KB_ROW02_SW
KB_COL00
KB_ROW01
KB_ROW04
KB_COL03
KB_COL02_SW
KB_ROW00
KB_COL05
KB_COL04
KB_ROW07
KB_COL06
KB_COL07
KB_COL01
KB_PWR_ON_L

51510-03001-001-30p-l

KB_ROW02_SW

C8812*15pF_2

KB_COL00

C8813*15pF_2

KB_ROW01

C8814*15pF_2

KB_ROW04

C8815*15pF_2

KB_COL03

C8808*15pF_2

KB_COL02_SW

C8810*15pF_2

KB_ROW00

C8809*15pF_2

KB_COL05

C8811*15pF_2

PP5000_DSW PP5000_DSW

PP5000_DSW

KB_ROW02_SW

KB_COL02_SW

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

KB_CONN_30P

DFFC30FR058

KB_COL00

KB_COL03

CN24

4

32
31

U55

1

I/O 1

2

GND
I/O 23I/O 3

U53

1

I/O 1

2

GND
I/O 23I/O 3

3

2

1

Track PAD BOARD CONN (TPD)

26

TP_SHDN_L27

1 2

D18 5V/0.2p_4

1 2

D17 5V/0.2p_4

I2C_0_SDA15
I2C_0_SCL15

TRACKPAD_INT_L_CONN

U24

A2

A1

IN

OUT

B2

B1

EN

GND

TPS22930

R227 *0_4/S

30mil

+TPVDD
I2C_0_SDA
I2C_0_SCL

C108
*10p/50V_4

TOUCHPANEL_PWR_R

CN21

1

1

2

2

3

3

4

4

5

5

6

6

TP_CONN_6P

DFFC06FR058

88501-0601-6p-l-smt

R206 *0_6/S
C114
1000p/50V_4

R226
100K_4

8
7

TP_PWR

0.5A

I2C_0_SDA
I2C_0_SCL

TP_PWR

L7 *0_6/S

C123

0.1u/10V_4

Track Pad interrupt

DSW

TRACKPAD_INT#6

TRACKPAD_INT_DX7

KB_COL04

C8820*15pF_2

KB_ROW07

C8821*15pF_2

KB_COL06

C8822*15pF_2

KB_COL07

C8823*15pF_2

KB_COL01

C8816*15pF_2

PWR_BTN_L

C8818*15pF_2

6

KB_ROW01

I/O 4

5

VDD

4

KB_ROW04

AZC099

6

KB_ROW00

I/O 4
VDD

AZC099

5
4

KB_COL05

PP5000_DSW

DX

D12

RB501V-40

VF = 0.34V

R546 *0_4/S

PP3300_DSW

C362

1U/6.3V_4

TOUCHPANEL_PWR_R

U51

1

KB_COL04

B B

KB_ROW07

I/O 1

2

GND
I/O 23I/O 3

I/O 4
VDD

AZC099

6

KB_COL06

5
4

KB_COL07

KB_COL01

KB_PWR_ON_L

HOLELESS RESET
2-CHIP(KBC)

U56

1

I/O 1

2

GND
I/O 23I/O 3

I/O 4
VDD

AZC099

6
5
4

PP5000_DSWPP5000_DSW

PP3300_RTC

5/15 modify,PU already at EC side

PP3300_RTC

R454

R144

*4.7K_4

1M_4

C391

2.2U/6.3V_4

2

5

BATT_ENABLE

A A

3

1

Q33

2N7002K

BATT_EN#

BATT_EN# 25,28

ACIN15,27,28

R498 *0_4/S

if not use ACIN, should tied to GND

PP3300_RTC

Pin 3,5,8,11 Open Drain

R476 4. 7K_4
R451 * 4.7K_4
R450 * 4.7K_4

1023 EC_IN_RW is OD,
remove level shift and PU
to PP1800_PCH

*100K/F_4

4

PWR_BTN_L
BATT_ENABLE
ACPRESENT_4137

R475

KB_COL02_SW

KB_ROW02_SW
KB_COL02
EC_IN_RW

R474

10K_4

U17

2

PWR_BTN_ L

3

BATT_ENABLE

4

AC_PRESE NT

5

KSO_SW

6

KSI_SW

SLG4K4213VTR(TDFN-12)

1

VDD

EC_ENTERING_RW

GND

PAD_GND

7

13

C345

0.1u/10V_4

12

EC_RST_L
EC_IN_RW

KSO_INV

EC_RST#

11

EC_IN_RW

10

EC_ENTERING_RW

9

KB_ROW02KB_ROW02_SW

8

KB_COL02

KSI

co-layout 4K4108 and 4K4137
SLG4K4108 (AL004108000)
SLG4K4137 (AL004137000)
4K4137 PIN3 is BATT_ENABLE
4K4137 PIN4 is AC_PRESENT

3

EC_RST# 18,20,27
EC_IN_RW 15
EC_ENTERING_RW 27

KB_ROW02 27

KB_COL02 27

Connect to EC reset pin
Connect to GPIO on CPU

with PU to GPIO power
well

Connect to EC pin C5 (must
be low when EC IN RESET)

2

PROJECT : Peach

PROJECT : Peach

PROJECT : Peach

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom

NB5

NB5

NB5
HW

HW

HW

KB/TP/FAN/HW Reset

KB/TP/FAN/HW Reset

KB/TP/FAN/HW Reset

Date: Sheet of

Date: Sheet of

Date: Sheet

1

1A

1A

1A

of

26 40Friday, July 25, 2014

26 40Friday, July 25, 2014

26 40Friday, July 25, 2014

5

EC(KBC)

D D

1023 SWAP RP1 pin for layout

C C

SPI_WP_ME6,25

B B

PP3300_ EC

A A

PP3300_ EC

KB_COL06
KB_COL05

R520

100K_4

R497

*100K_4

PP3300_ EC

R126 *0_ 4

RP1 10K_1 0P8R

10

9
8
7 4

PP3300_ EC

R514

100K_4

R493

*100K_4

C327

C77

1u/6.3V_ 4

1u/6.3V_ 4

EC_LPCPD#PCH_SUS _STAT_L

1

KB_COL01

2

KB_COL02KB_COL07

3

KB_COL00
KB_COL03KB_COL04

56

R518
100K_4

0711 add the R17673

PWR_BTN_ L16,18,26

R495100 K_4

TP_SHDN_L26
BAT_LED028
PP3300_ DX_EN30

WLAN_O FF_L20
PP3300_ PCH_PG35
IMVP_PW RGD_3V33,34,35

SUSP_VR_ EN32

PP1050_ PCH_PG32,3 4,35

PP1000_ PCH_SX_PG15

PP5000_ PGOOD29

PP3300_ DSW_E N16,29

PP3300_ LTE_EN23
USB2_PW R_EN25

EC_ENTERING_RW26

USB3_PW R_EN25

EC_RST#18,20 ,26

EC_RST#_R23

R516

*100K_4

EC_BRD_ID1
EC_BRD_ID2
EC_BRD_ID3

R490

100K_4

5

C340

C333

0.1U/10V_4

0.1U/10V_4

CLK_PCI_EC7

LPC_LFRAME#7,22

EC_SCI_L14

PWR_BTN_ L PWR_BTN_ L_R

TEMP_MBAT28

AD_TYPE28

TP68
TP67

TP46

VCORE_EN33

PP1350_ EN31

PP5000_ EN29

TP61
TP62

USB_OC1_ L14

ICMNT28

USB_ILIM_ SEL23,25
USB_CTL125

USB_OC0_ L14

R164 *0_ 4/S

C320

0.1U/10V_4

LPC_LAD07,22
LPC_LAD17,22
LPC_LAD27,22
LPC_LAD37,22

PLTRST#14,20,22

IRQ_SERIRQ14,2 2

KB_COL0026
KB_COL0126
KB_COL0226
KB_COL0326
KB_COL0426
KB_COL0526
KB_COL0626
KB_COL0726

KB_ROW 0026
KB_ROW 0126
KB_ROW 0226
KB_ROW 0326
KB_ROW 0426
KB_ROW 0526
KB_ROW 0626
KB_ROW 0726
KB_ROW 0826
KB_ROW 0926
KB_ROW 1026
KB_ROW 1126
KB_ROW 1226

R17673 1 K_4

TP60 TP21
TP59

R173 *0_ 4/S
R169 *0_ 4/S

R162 *0_ 4/S

TP55
TP54

TP14
TP13

C96 0.1 U/10V_4

C321

C335

1000p/50V_4

0.1U/10V_4

EC_LPCPD#

KB_COL00
KB_COL01
KB_COL02
KB_COL03
KB_COL04
KB_COL05
KB_COL06
KB_COL07

KB_ROW 00
KB_ROW 01
KB_ROW 02
KB_ROW 03
KB_ROW 04
KB_ROW 05
KB_ROW 06
KB_ROW 07
KB_ROW 08
KB_ROW 09
KB_ROW 10
KB_ROW 11
KB_ROW 12

LID_OPEN_R
EC_SPI_W P_D
EC_PA5
EC_PB0
TEMP_MBAT
AD_TYPE
PROCHOT_EC
SIO_SPI_ MOSI_EC
SIO_SPI_ MISO_EC

TP_SHDN_L
BAT_LED0
PP3300_ DX_EN
PJ3_T2CCP1 _U5TX
WLAN_O FF_L

PP3300_ PCH_PG

VCORE_EN_R

IMVP_PW RGD_3V_ R
SUSP_VR_ EN
PP1050_ PCH_PG
PP1350_ EN

PP1000_ PCH_SX_PG_R
PP5000_ EN
PP5000_ PGOOD
PP3300_ DSW_E N

SIO_SPI_CLK_EC
SIO_SPI_CS_L
PP3300_ LTE_EN
USB2_PW R_EN
EC_ENTERING_RW

USB_OC1_ L
EC_PE1
EC_PE2
ICMNT
USB3_PW R_EN
USB_ILIM_ SEL
USB_CTL1
USB_OC0_ L

EC_BRD_ID1
EC_BRD_ID2
EC_BRD_ID3

EC_RST#_R

stage

Proto
EVT
DVT
Ramp

4

C344
1000p/50V_4

D7

E6

E8

E9

J10

U16

B13

PL3/LPC0AD0/T1CCP1/WT1CCP1

A13

PL2/LPC0AD1/T1CCP0/WT1CCP0

C12

PL1/LPC0AD2/T0CCP1/WT0CCP1

D11

PL0/LPC0AD3/T0CCP0/WT0CCP0

H12

PM5/LPC0CLK

D12

PL4/LPC0FRAME_L/T2CCP0/WT2CCP0

F13

PM0/LPC0PD_L/T4CCP0/WT4CCP0

C13

PL5/LPC0RESET_L/T2CCP1/WT2CCP1

F12

PM1/LPC0SCI_L/T4CCP1/WT4CCP1

H13

PM4/LPC0SERIRQ

G2

PK0/AIN16/SSI3CLK

G1

PK1/AIN17/SSI3FSS

H1

PK2/AIN18/SSI3RX

H2

PK3/AIN19/SSI3TX

B11

PK4/RTCCLK/U7RX

B12

PK5/U7TX

C11

PK6/FAN0PWM1/WT1CCP0

A12

PK7/FAN0TACH1/WT1CCP1

M13

PP0/T4CCP0

L12

PP1/T4CCP1

M5

PP2/T5CCP0

J12

PP3/T5CCP1

J13

PP4/WT0CCP0

L5

PP5/WT0CCP1

D8

PP6/WT1CCP0

K6

PP7/WT1CCP1

D4

PQ0/WT2CCP0

E4

PQ1/WT2CCP1

F5

PQ2/WT3CCP0

N5

PQ3/WT3CCP1

N6

PQ4/WT4CCP0

M2

PA2/SSI0CLK

M3

PA3/SSI0FSS

L4

PA4/SSI0RX

N1

PA5/SSI0TX

F11

PB0/T2CCP0/U1RX

E11

PB1/T2CCP1/U1TX

B6

PB4/AIN10/SSI2CLK/T1CCP0

A6

PB5/AIN11/SSI2FSS/T1CCP1

C2

PD2/AIN13/SSI1RX/SSI3RX/WT3CCP0

C1

PD3/AIN12/SSI1TX/SSI3TX/WT3CCP1

B8

PN1/AIN22

N11

PN6/FAN0PWM4/WT4CCP0

A9

PJ2/T2CCP0/U5RX

C8

PJ3/T2CCP1/U5TX

D5

PJ4/C2_P/T3CCP0/U6RX

L2

PC4/C1_M/U1RX/U4RX/WT0CCP0

L1

PC5/C1_P/U1TX/U4TX/WT0CCP1

K1

PC6/C0_P/U3RX/WT1CCP0

K2

PC7/C0_M/U3TX/WT1CCP1

J3

PH4/SSI2CLK/WT3CCP0

H4

PH5/SSI2FSS/WT3CCP1

H3

PH6/SSI2RX/WT4CCP0

G4

PH7/SSI2TX/WT4CCP1

A8

PN0/AIN23

M12

HIB_L

B2

PD0/AIN15/I2C3SCL/SSI1CLK/SSI3CLK/WT2CCP0

B1

PD1/AIN14/I2C3SDA/SSI1FSS/SSI3FSS/WT2CCP1

A4

PD4/AIN7/U6RX/WT4CCP0

B4

PD5/AIN6/U6TX/WT4CCP1

A3

PD6/AIN5/U2RX/WT5CCP0

B3

PD7/AIN4/NMI/U2TX/WT5CCP1

F1

PE0/AIN3/U7RX

F2

PE1/AIN2/U7TX

E1

PE2/AIN1

E2

PE3/AIN0

A5

PE4/AIN9/I2CSCL/U5RX

B5

PE5/AIN8/I2CSDA/U5TX

A7

PE6/AIN21

B7

PE7/AIN20

K5

PQ5/WT4CCP1

M6

PQ6/WT5CCP0

L6

PQ7/WT5CCP1

G12

OSC0

G13

OSC1

G10

RST_L

TM4E1G31H6 ZRBI

F10

VDD1

VDD2

VDD3

VDD4

VDD6

VDD5

PERIPHERAL INTF

J9

J7

D3

VDD8

VDD7

LPC

VDDA

SMBUS INTF

TO PCH

KB

FAN

PECI

LOAD SW

UNUSED

UART

VR CTRL

JTAG

USB CHARGE CTRL

BRD ID

PM2/LPC0CLKRUN_L/T5CCP0/WT5CCP0

C343

C348

2.2U/6.3V _4

10u/6.3V _4

K13

VDDC1D6VDDC2J1VDDC3J6VDDC4

PB6/I2C5SCL/SSI2RX/T0CCP0
PB7/I2C5SDA/SSI2TX/T0CCP1

PF0/NMI/SSI1RX/T0CCP0/TRD2

PF2/NMI/SSI1CLK/T1CCP0/TRD0

PF3/SSI1FSS/T1CCP1/TRCLK

PG4/I2C1SCL/U2RX/WT0CCP0
PG5/I2C1SDA/U2TX/WT0CCP1

PG7/I2C5SDA/U2TX/WT1CCP0

PH2/FAN0PWM5/SSI3RX/WT5CCP0
PH3/FAN0TACH5/SSI3TX/WT5CCP1

PN3/FAN0TACH2/WT2CCP1
PN5/FAN0TACH3/WT3CCP1

PM7/FAN0TACH0/WT0CCP1
PN7/FAN0TACH4/WT4CCP1

VREFA_P
VREFA_M

PB2/I2C0SCL/T3CCP0

PB3/I2C0SDA/T3CCP1

PA6/I2C1SCL
PA7/I2C1SDA

PF1/SSI1TX/T0CCP1/TRD1

PF4/T2CCP0/TRD3

PF5/T2CCP1

PF6/I2C2SCL/T3CCP0
PF7/I2C2SDA/T3CCP1
PG0/I2C3SCL/T4CCP0

PG1/I2C3SDA/T4CCP1

PG2/I2C4SCL/T5CCP0

PG3/I2C4SDA/T3CCP1

PG6/I2C5SCL/WT1CCP0
PH0/SSI3CLK/WT2CCP0

PH1/SSI3FSS/WT2CCP1

PL6/T3CCP0/WT3CCP0
PL7/T3CCP1/WT3CCP1

PN2/FAN0PWM2/WT2CCP0
PN4/FAN0PWM3/WT3CCP0

PJ7/PECI0RX
PJ6/PECI0TX

PM3/T5CCP1/WT5CCP1

PM6/FAN0PWM0/WT0CCP0

PJ0/T1CCP0/U4RX
PJ1/T1CCP1/U4TX

PJ5/C2_M/T3CCP1/U6TX

PA0/U0RX

PA1/U0TX

PC0/SWCLK/T4CCP0/TCK
PC1/SWDIO/T4CCP1/TMS

PC3/SWO/T5CCP0/TDO

PC2/T5CCP1/TDI

VBAT

WAKE_L

XOSC1
XOSC0

GNDX

GNDA1
GNDA2

GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9

GND10

1212 change part number of EC ,which has a trial firmware inside

1211 add Test points on unused pins, need check layout to
see if all points are ok

MB ID

EC_BRD_ID3 EC_BRD_ID2 EC_BRD_ID1

0 0 0
0 0 1
0 01

1 10

4

3

C347

0.1U/10V_4

D2
D1

E10
D13

M4
N2

F4
F3

M9
N9
L10
K10
L9
K9
N8
M8
L8
K8
N7
M7
K7
L7
N4
N3
K3
K4
J4
J2
G11
E12
E13

G3
D10
L11
N12

C4
C6

H10
H11
L13
M11
C9
B9
C5

L3
M1

C10
A10
A11
B10

A2

NC

K12
N13

N10
M10
K11

C3
E3

A1
C7
D9
E5
F9
H5
H9
J11
J5
J8

EC_SLP_SX_L
SUSP_VR_ EN
VCORE_EN
PP1350_ EN
PP5000_ EN
PP3300_ DSW_E N

3

BLM18AG121SN1D/0.2A/120 ohm_6

C318
1u/6.3V_ 4

EC_SMB0_ CLK
EC_SMB0_ DATA

EC_PA6
EC_PA7

EC_SMB2_ CLK
EC_SMB2_ DATA

PCH_WAKE_L
PCH_RSMRST_L
EC_PF2
EC_REST_L
EC_SMI_L
CORE_PW ROK_R
EC_PF6
EC_PF7
HWPG_S 5
SOC_OVERRIDE#
PCH_SUSPWRDNACK
PCH_SLP_ SX_L
PCH_UART_RXD
PCH_UART_TXD
PCH_SUS_STAT_L
PCH_SLP_ S3_L
PCH_PWRBTN_L
PCH_SLP_ S4_L
EC_PH2
EC_ACIN
LPC_CLKRUN_L
EC_SLP_SX_L
EC_PL7

EC_PN2
EC_PN3
BAT_LED1
PMU_BATLOW _L

EC_PECI_RX
EC_PECI_TX

KBD_IRQ#
EC_BL_DISABLE_L
PP3300_ WLAN_ EN

EC_PWROK
PP3300_ PGOOD

EC_UART0_RX
EC_UART0_TX

EC_JTAG_TCK
EC_JTAG_TMS
EC_JTAG_TDO
EC_JTAG_TDI

PP3300_ RTC
EC_WAK E_L

R444 0_4

ECGND

R177
100K_4

PP3300_ ECPP3 300_EC_ ANA

L6

PP3300_ EC_ANA

C312
1u/6.3V_ 4

C310

C319

0.01U/16V_4

0.1U/10V_4

PWR_LE D#

ECGND

ECGND

EC_SMB0_ CLK 28

TP50
TP47

TP44

TP43
TP42

TP41

TP40

TP12
TP24

TP11
TP45

PP3300_ RTC

1121 by X'tal vender suggestion,
c

EC_SMB0_ DATA 28

EC_SMB2_ CLK 23

EC_SMB2_ DATA 2 3

PCH_WAKE_L 6
PCH_RSMRST_L 14

EC_REST_L 6
EC_SMI_L 14

CORE_PW ROK_R 6,11

SOC_OVERRIDE# 4

PCH_SUSPWRDNACK 14
PCH_SLP_ SX_L 14

PCH_UART_RXD 18,20

PCH_UART_TXD 18,20

PCH_SUS_STAT_L 14
PCH_SLP_ S3_L 14
PCH_PWRBTN_L 1 1,14
PCH_SLP_ S4_L 14

LPC_CLKRUN_L 7
EC_SLP_SX_L 34

BAT_LED1 28

1128 add a connection and name
to KBD_IRQ#, beside add pulled
high resistor at SoC side

KBD_IRQ# 6

PWR_LE D# 22

EC_BL_DISABLE_L 17

PP3300_ WLAN_ EN 30

EC_PWROK 2

PP3300_ PGOOD 29

0713 For PP3300_PGOOD

EC_UART0_RX 18 ,20

EC_UART0_TX 18,20

EC_JTAG_TCK 18 ,20
EC_JTAG_TMS 18,20

EC_JTAG_TDO 18 ,20

EC_JTAG_TDI 18,20

EC32K_X1

EC32K_X2

R201
20M_4

12

hange C107/C109 from 15pF to 18pF

SM BUS ARRANGEMENT TABLE

SM Bus 0

BATT and CHARGER

SM Bus 1 NA

SM Bus 2

THERMAL SENSOR

R149

R153
100K_4

R190
100K_4

100K_4

12

R1192.2_6

C316

0.1U/10V_4

C107 18p/5 0V_4

Y4

32.768KHZ
C109 18p/5 0V_4

R461

R435

100K_4

100K_4

ECGND

2

PP3300_ DSW

C317

0.01U/16V_4

0830

2

EC_ACIN
EC_RST#

EC_LPCPD#
LID_OPEN_R

LID_OPEN_R

ACIN15,26,28

SM BUS/I2C PU(KBC)

1

030 Thermal IC VDD has two option, ome is
PP3300_DSW( =PP3300_EC), another is
PP3300_DX, default is stuffing to DSW rail

PROCHOT_EC

EC HIB WAKE SOURCES

PWR_BTN_ L

TP51

ACIN

C361 0.1U/10V_4

HWPG(KBC)

PP3300_ PCH_S5_PG15

OD pin list

EC_REST_L
BAT_LED0
BAT_LED1
PCH_RSMRST_L
SMBUS
IRQ_SERIRQ
EC_BL_DISABLE_L

PP3300_ EC

R482 10 K_4
R155 10 K_4

R135 10 K_4

Add diode for leakage issue

BATT and CHARGER / LCD BL

THERMAL SENSOR

R534 10 K_4

LID_OPEN_L

D15RB500 V-40

LID_OPEN_L18,22

ACIN EC_ACIN

D11 RB5 00V-40

C356

0.1U/10V_4

EC_SMB0_ CLK
EC_SMB0_ DATA

EC_SMB2_ CLK
EC_SMB2_ DATA

2

R98
100K_4

D14 RB5 00V-40

3

2

R527
47K_4

1

For testing only

NB5

NB5

NB5
HW

HW

HW

R477 10K_4

R419 4.7K_4
R423 4.7K_4

R140 4.7K_ 4
R132 4.7K_ 4

3

Q19

2N7002K

1

LID_OPEN_L

Q50
PJA138K

C354 0.01U/16V_4

R145 *0_ 4/S

0714 delete Power BTN

PROJECT : Peach

PROJECT : Peach

PROJECT : Peach

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom

KBC TI TM4E1G31H6ZRBI

KBC TI TM4E1G31H6ZRBI

KBC TI TM4E1G31H6ZRBI

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

PP3300_ RTC

PP3300_ EC

PP3300_ THM

H_PROCHOT# 5,18,33

EC_WAK E_L

HWPG_S 5

1

R494
47K_4

27

PP3300_ RTC

2

R463
1K_4

3

Q39
PJA138K

1

1A

1A

1A

27 40Friday, July 25, 2 014

27 40Friday, July 25, 2 014

27 40Friday, July 25, 2 014

5

DC_JACK

19.5V~45W

CN1

1

VDD
VDD

5

GND

8

WLED
ALED

DC-IN_CONN_8 P

D D

ALED

C C

WLED

WLED

7

ALED

PC26
*0.1U/25V_4

2.43K/F_6

PC39
*0.1U/25V_4

PR28

GND
GND
GND
GND

AD_ID

6

PC8
100P/50V_4

PP5000_DSW

1 3

PP5000_DSW

PR14

2.43K/F_6

1 3

2

3
4
9
10

PR2
100/F_4

PQ9
DRC5144E0L

2

2

PQ13
DRC5144E0L

+VA_AC VA

PC1

0.1U/25V_4

PR6

12.1K/F_4

BAT_LED0 27

BAT_LED1 27

PL1
*0_8/S

PL2
*0_8/S

PR5
2K_4

PC9

0.1U/10V_4

21

PR17641

*100K/F_4

1 3

PC3

2200P/50V_4

3

2

1

PQ33

*METR3904-G

PR17

576K/F_4

PR21

100K/F_4

*2N7002K

PQ1
TPCA8056-H

5

PQ31

VA

PC2

PD1

P4SMAFJ20A

0.1U/25V_4

PD2

PDZ5.6B

2 1

2 1

AD_TYPE 27

BAT-V

PD11

*1N4448WS-7- F

PR17643
*1M_4

VIN

PR17642

*1M_4

VA

PR17644

2

*750K/F_4

PR17645
*127K/F_4

battery cell option

2-cell 3-cell

PR27

PQ14

2N7002K

PP5000

3
2

84

+

-

3

1

un-stuff stuff

PC42

0.01U/16V_4

1

PU21A

LMV393IDR

PC51

0.01U/16V_4

2

PC54

0.1U/25V_4

PR45
220K/F_4

7

6
5

10ms one-shot circuit

B B

PP5000

PR34

PR39 25.5 K/F_4

ICMNT

PR33

100K/F_4

PC44

0.01U/16V_4

PC50

*100P/50V_4

PC46

0.01U/16V_4

1.5M_4

PC47
*100P/50V_4

IMVP7_PROCHOT#5

A A

D

VA

G

4

21

set VA=17V

24715LDO

3

S

2
1

PD5

*1N4448WS-7- F

2 1

PD10
1N4448WS-7- F

PR17635 *0_4/S

ACIN15,26,27

ICMNT27

PP5000

84

4

PC6

0.1U/25V_4

PC25 1U/25V_6

*0.01U/25V_4

EC_SMB0_DATA

EC_SMB0_CLK

PR29 10K/F_4

PU4
NL27WZ00USG

*0.01U/25V_4

PC27

1
2

3

PC4

PR10

4.02K/F_6

PR25 *0_2/S

PR26 *0_2/S

PR27 4.7K_4

PR31

12.4K/F_4

PR32
10/F_4

PC40

0.01U/50V_4

PP5000

+DC_IN_SS

PR41

100K_4

PC5

*0.1U/25V_4

+DC_IN_SS

24715_CMSRC

24715_ACDRV

24715_VCC

24715_ACDET

IOUT

PD8

1N4448WS-7- F

2 1

2 1

1N4448WS-7- F

PD9

PC41

PR11

4.02K/F_6

PC12

0.1U/25V_4

3

4

20

6

8

9

10

5

7

100P/50V_4

CMSRC

ACDRV

VCC

ACDET

SDA

SCL

CELL

ACOK

IOUT

1
2
3

PQ2

EMB20N03V

4

24715ACP

24715ACN

1

2

ACP

PU1

BQ24715RGRR

GND21GND22GND23GND24GND

ACN

25

5
6
7
8

REGN

HIDRV

PHASE

LODRV

BATDRV#

LMV393IDR

PU21B

3

2

1

28

PR1

+DC_IN

RC1206-R010

21

PR4

PR3

*0_2/S

*0_2/S

PC10

0.1U/25V_4

PC13

0.1U/25V_4

24715LDO

16

24715LDO

18

24715DHI

17

24715BST

BTST

19

24715LX

15

24715DLO

14

GND

13

24715SRP

SRP

12

24715SRN

SRN

11

24715BATDRV

7

PR42

1.5M_4

PC52
100P/50V_4

PR15 0_6

-

6

+

5

PC53
100P/50V_4

PC23
1U/10V_4

PD6
RB500V-40

0.047U/50V_6

24715LDO

PC24

EMB20N03V

PQ10

MDV1595SURH

PR43

150K/F_4

678

35241

PQ6

678

35241

PC37

0.1U/25V_4

PR30 4.02K/F_6

PR40

100K/F_4

*0.1U/25V_4

PP5000

PC17

*0.1U/25V_4

PC48

VCHGR_IN

PC18

2200P/50V_4

PL5

2.2uH_7X7X1.8/6A

PR22
*2.2_6

PC34
*2200P/50V_4

IN+

IN-

PR37
*0_4/S

6

OUT

INA199B1DCKR

REF

1

PU3

5

2

IN-

VCHGR_IN2

PC45

*0.1U/16V_4

PC19

4.7U/25V_8

PC28

10U/25V_8

PR38
*0_4/S

4

IN+

V+3GND

PC29

PD13

RB500V-40

PC55

0.1U/10V_4

PC20

4.7U/25V_8

10U/25V_8

PC49

*0.1U/25V_4

EC21
*4.7U/25V_8PR13 10_ 8

VIN

PC31

PC30

*10U/25V_8

PC36 0.1U /25V_4

PC38 0.1U /25V_4

PR44 *0_ 6/S

*10U/25V_8

EC22
*4.7U/25V_8

PP5000

BAT-V

PL3
*0_8/S

PL4
*0_8/S

PR7
330_4

PD3

PDZ5.6B

PC14

*100P/50V_4

PD7 *SS3040HE

PQ7

EMB20P03V

1 5
2
3

4

PC7

0.1U/25V_4
PR8

330_4

2 1

2 1

21

6
7
8

PC6269

0.1U/25V_4

EC_SMB0_DATA27

EC_SMB0_CLK27

PR19

RC1206-R010

21

BAT-V_P2

+

PC33

PR24

PR23

PC243

*0_2/S

*0_2/S

0.1U/25V_4

10U/25V_8

BATT+

SMD
SMC

PD4

PDZ5.6B

PC15

*100P/50V_4

3S1P~36W

7
6

4
5
3

B_TEMP_MBAT

2
1

PP3300_RTC

PR17654
200K_4

PR17655 *0_4

PR20

RC1206-R010

IN- IN+

CN2

Pack+
Pack+

I2C_DAT
I2C_CLK
B/I
GND

GND

BATTERY_7P

PR17653
1K/F_4

PC5336

0.01U/25V_4

21

GND
GND

TEMP_MBAT

PC5335

0.01U/25V_4

8
9

BATT_EN# 25,26

BAT-V

TEMP_MBAT 27

BAT-V BATT+ B_TEMP_MBAT TEM P_MBAT

EC25

EC26

56P/50V_4

56P/50V_4

EC23

EC24

56P/50V_4

56P/50V_4

For EMI

+VA_AC

EC40

EC39

EC41

EC42

10U/25V_8

10U/25V_8

10U/25V_8

10U/25V_8

For EMI ISN

PROJECT : Peach

PROJECT : Peach

PROJECT : Peach

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom

NB5

NB5

NB5
HW

HW

5

4

3

2

HW

Charger(BQ24715)

Charger(BQ24715)

Charger(BQ24715)

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

1A

1A

1A

28 40Friday, July 25, 2014

28 40Friday, July 25, 2014

28 40Friday, July 25, 2014

5

4

3

2

1

DC/DC +3VS5/+5VS5

D D

PP3300_PGOOD27

PP3300_DSW

3VPCU_VIN

3VPCU_VIN

PP3300_DSW_EN16,27

C C

PP3300_RTC

PC56

PR53

*665K/F_4

PR56

*330K/F_4

PR57
*499K/F_4

10U/6.3V_6

PR17656 *0_4

PR50 *100K/F_4

PR58 *0_4/S

PU5

6

LDO

3

NC

5

CLK

4

NB670PG

PGOOD

12

NB670ENLDO

NB670EN NB670VOUT

PC71
*0.1U/10V_4

ENLDO

13

EN

NB670

AGND
PGND

BST

VCC

VOUT

1

VIN

14
2

10

8

NB670SW

SW

9

SW

15

SW

16

SW

11

7

PC69
1U/6.3V_4

PC72

*0.1U/10V_4

PR49

PC57

0_6

3VPCU_VIN

PC58

PC59

4.7U/25V_8

0.1U/25V_4

NB670BST_SNB670BST

4.7U/25V_8

PC62

0.1U/25V_4

PR52
*2.2_6

PC70

*2200P/50V_4

PC60

2200P/50V_4

PR46 *0_8/S

PL6

2.2uH_7X7X1.8

PR54
*0_2/S

VIN

3.3 Volt +/- 5%

PC61

+

0.1U/25V_4

PC63

PP3300_DSW_SRC

PC68

0.1U/10V_4

*100uF/6.3V_7343

PC64

PC65

22U/6.3V_8

22U/6.3V_8

TDC : 6A
PEAK : 8A
Width : 240mil

PR51 *0_8/S

PC66

PC67

22U/6.3V_8

G3/DSW

PP3300_DSW

22U/6.3V_8

EC27

*0.1U/10V_4

+3VS5
+5VS5

For EMI reserve

29

PP5000_DSW

PU8

6

PC90

NC

3

NC

5

NC

4

PGOOD

11

VCC

1U/6.3V_4

13

EN

NB669

5VPCU_VIN

4

PP5000_EN27

PR59 *0_4/S

PP5000_PGOOD27

NB671_VCC

PR64 100K/F_4

PC77

PR63 *0_4

10U/6.3V_6

PR71 *0_4/S

NB671PG

PR66
200K/F_4

NB671_VCC

NB671EN

PC92
*0.1U/10V_4

B B

Reserve for NB670 5V version.

A A

5

AGND
PGND

BST

VOUT

VIN

SW
SW
SW
SW

FB

1

14
2

10

8
9
15
16

7

12

PR17636

*665K/F_4

NB671SW

NB671VOUT

NB671FB

PC81

0.1U/25V_4

PR65

0_6

PR72

*82K/F_4

PR73
*11K/F_4

NB671BST_SNB671BST

PC78

4.7U/25V_8

NB671FB_1

5VPCU_VIN

PC79

4.7U/25V_8

PC83

0.1U/25V_4

PC80

2200P/50V_4

PR68
*2.2_6

PC91
*2200P/50V_4

PR60 *0_8/S

PL7

3.3uH_7X7X1.8

3

PC82

PR69
*0_2/S

VIN

0.1U/25V_4

PP5000_SRC

PR67 *0_8/S

+

PC84

PC85

0.1U/10V_4

*100uF/6.3V_7343

PC86

PC87

22U/6.3V_8

22U/6.3V_8

2

PC88

PC89

22U/6.3V_8

S3

PP5000

EC28

22U/6.3V_8

NB5

NB5

NB5
HW

HW

HW

For EMI reserve

*0.1U/10V_4

PROJECT : Peach

PROJECT : Peach

PROJECT : Peach

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom
Date: Sheet of

Date: Sheet of

Date: Sheet of

3V/5V (NB670/NB669)

3V/5V (NB670/NB669)

3V/5V (NB670/NB669)

1

29 40Friday, July 25, 2014

29 40Friday, July 25, 2014

29 40Friday, July 25, 2014

1A

1A

1A

5

4

3

2

1

30

7

VIN26VIN2

CT2

10

PC110
*1000P/50V_4

OUT2
OUT2

GND
GND

ON2

PP3300_DSW

PC94

0.1U/10V_4

8
9

11
15

5

PC108
*0.1U/10V_4

PP3300_DX_1PP3300_PCH_S5_1PP3300_PCH_S5 PP3300_DX

PR78

PC99

0.1U/10V_4

PR82 *0_4/S

*0_6/S

PC100
*10U/6.3V_6

EC29

or EMI reserve

F

*0.1U/10V_4

PP3300_DX_EN 27

TDC : 0.026A
PEAK : 0.035A
Width : 20mil

PP1350_PCH_PG34

PP1350_PCH_PG

PP1800_PCH

PR79
*0_6/S

PP5000_DSW

PR85 *0_4/S

PR90 4.7K_4

PC101
*10U/6.3V_6

PC106

0.1U/10V_4

PP1800_PCH_S5

PC95

0.1U/10V_4

13
14

PC102

0.1U/10V_4

4

3

PC111
*0.1U/10V_4

PP1800_PCH_PG_1

PC116
*1000P/50V_4

VOUT1
VOUT1

VBIAS

ON1

PC113

1500P/50V_4

2

PP3300_DSW

1

VIN12VIN1

PU10

APL3523A

CT1

12

PP1800_PCH_PG_2

PQ16
MMBT3904-7-F

1 3

7

VIN26VIN2

CT2

10

PC114
1000P/50V_4

OUT2
OUT2

GND
GND

ON2

PC96

0.1U/10V_4

8
9

11
15

5

PR89

4.7K_4

PC115
1000P/50V_4

PR77 *0_8

PP3300_WLAN_1PP1800_PCH_1PP1800_PCH PP3300_WLAN

PC103

0.1U/10V_4

PR86 *0_4/S

PC112
*0.1U/10V_4

PP3300_PCH_S5

2

PR88

4.7K_4

PP1800_PCH_PG

PQ15

1 3

DTC144EUA

PR80
*0_6/S

PC104
*10U/6.3V_6

PP3300_WLAN_EN 27

EC30

For EMI reserve

*0.1U/10V_4

PP1800_PCH_PG 35

PP3300_DSW

PC93

0.1U/10V_4

1

D D

PP1800_PCH_S5_PG35

C C

PR76

*0_6/S

PP5000_DSW

PP1800_PCH_S5_PG

PR81 *0_4/S

PC97
*10U/6.3V_6

PC105

0.1U/10V_4

PC98

0.1U/10V_4

PC107
*0.1U/10V_4

13

VOUT1

14

VOUT1

4

VBIAS

3

ON1

PC109

*1000P/50V_4

VIN12VIN1

PU9

APL3523A

CT1

12

B B

A A

PROJECT : Peach

PROJECT : Peach

PROJECT : Peach

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom

NB5

NB5

NB5
HW

HW

HW

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Load Switch

Load Switch

Load Switch

1

1A

1A

1A

30 40Friday, July 25, 2014

30 40Friday, July 25, 2014

30 40Friday, July 25, 2014

5

4

3

2

1

31

PR514

499K/F_4

VCC

VTT
VTTSNS

VTTGND
VTTGND
VTTGND

POK

S3

S5

PU11

UP1740S

VTTREF

1

PC515

0.1U/10V_4

7

13

VIN

23

VIN

TON/NC

BOOT

PHASE
PHASE

CS

PGND

GND

NC

FB

VDDQ

VTTIN

17

PP1350

PC514
*1U/6.3V_4

16

1740BST

12

1740PHASE

14

10

1740CS

11
21

15
3

1740FB

2

PC503

0.1U/25V_4

PR101

3.3_6

PC502

*0.01U/25V_4

PR510

6.81K/F_4

PC504

1740BST_S

1740VCC

D D

PP1350_PGOOD2

VSFR_EN34

C C

VSFR_EN

PP1350_EN27

PP5000_DSW

TDC : 0.75A
PEAK : 1A
Width : 40mil

PP3300_PCH_S5

*100K/F_4

PR505 *0_4/S

1740S5

PR506 *0_4/P

PR504

PR503 *0_4/S

PR502

2.2_6

( VTT/2A )

+DDR_VTT_RUN +1.35VSUS_S

PR106 *0_4/S

1740VCC

PC117
1U/6.3V_4

PC124
10U/6.3V_6

1740PG

1740S3

PC6268
*0.1U/10V_4

1740S5

PC6263
*0.1U/10V_4

9

18
20

4
19
22

8

5

6

( 3mA )

PP1350_VREF

TDC : 0.38A
PEAK : 0.5A
Width : 20mil

PR102

100/F_4

PC516

0.1U/10V_4

4.7U/25V_8

PC505

4.7U/25V_8

PC125

0.1U/25V_4

1740VCC

+VIN_DDR

PR509
*2.2_6

PC501

PC506

2200P/50V_4

PC500

*150P/25V_4

*2200P/50V_4

PR507

8.06K/F_4

PR508

R2

10K/F_4

VO=(0.75(R1+R2)/R2)

PR511 *0_8/S

PL14

1uH_7X7X1.8

1740FB_S

R1

PR17616
*0_2/S

VIN

PC513

0.1U/25V_4

PC507

0.1U/10V_4

PC508

22U/6.3V_8

1.35 Volt +/- 5%
TDC : 3.55A
PEAK : 4.73A
OCP : 8A
Width : 160mil

PC509

PC510

22U/6.3V_8

22U/6.3V_8

PC511

*22U/6.3V_8

+

PC512

*220u/2V_7343

PP1350

S3

PR17634
*0_8/S

EC31

For EMI reserve

*0.1U/10V_4

S3 S5

S0

S3 (mainon off)

B B

A A

5

4

3

S4/S5

1
0

1
1

ON
ON ON
OFF

2

ON ON

OFF OFF0 0

VTTREF+1.35VSUS

OFF

PROJECT : Peach

PROJECT : Peach

PROJECT : Peach

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom

NB5

NB5

NB5
HW

HW

HW

Date: Sheet of

Date: Sheet of

Date: Sheet of

DDR 1.35V(UP1740S)

DDR 1.35V(UP1740S)

DDR 1.35V(UP1740S)

1

1A

1A

1A

31 40Friday, July 25, 2014

31 40Friday, July 25, 2014

31 40Friday, July 25, 2014

5

PP1050_PCH_PG27,34,35

D D

PP1000_PCH_PG35

PP3300_DSW

PP3300_DX

PP1050_PCH_PG 8002LX1.05V

PR118 *0_4/S

PR114
10K/F_4

PR115 *0_4/S

PC142

1000p/50V_4

PR111 *0_6/S

5

1

APW8824

PU13

PG

EN

R2

PP1000_PCH_S5_PG

PC153

0.01U/50V_4

PR122 100K/F_4

PR124 *0_4/S

PR131

10_6

PC154

10U/6.3V_6

554PG_1.0V
554PVIN_1.0V

554SVIN_1.0V

PC155

1U/6.3V_4

C C

PP3300_DSW

PP1000_PCH_S5_PG35

PR126 *0_6/S

PP5000

PP3300_DSW

PR127 *0_6

4

PC139

4.7U/6.3V_6

4

3

VIN

LX

2

GND

FB

6

R1

PR119

11.3K/F_4

PR120
15K/F_4

VO=(0.6(R1+R2)/R2)

PC147

*2200P/50V_4

PU15

4

PG

9

PVIN

10

PVIN

RT8068A

8

SVIN

11

GND

PL9

1uH/2.6A_2520

PR121

*2.2_6

1

NC

2

LX

3

LX

7

NC

6

FB

5

EN

PC156

1000p/50V_4

PR117
*0_2/S

554LX_1.0V

554NC_1.0V
554FB_1.0V
554EN_1.0V

PP1050_PCH_SRC

PC143

PC144

10U/6.3V_6

PL10

1uH/3.42A

PC150

*22P/50V_4

PC149

*68P/50V_4

PR132 *0_4/S

10U/6.3V_6

PR116 *0_6/S

PC145

0.1U/10V_4

554FB_1.0V_S

R1

R2

6.81K/F_4

10K/F_4

3

1.05Volt +/- 5%
TDC : 0.75A
PEAK : 1A
Width : 40mil

PP1050_PCH

EC32

For EMI reserve

*0.1U/10V_4

PP1000_PCH_S5_SRC

PR125

PR130

PR133

*0_2/S

PC151

0.1U/10V_4

V0=0.6*(R1+R2)/R2

SUSP_VR_EN 27

1.0Volt +/- 5%
TDC : 2.07A
PEAK : 2.75A
Width : 100mil

PP1000_PCH_S5

PR123
*0_8/S

PC152

22U/6.3V_8

EC33

For EMI reserve

*0.1U/10V_4

2

1

32

B B

A A

PROJECT : Peach

PROJECT : Peach

PROJECT : Peach

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
C

C

C

NB5

NB5

NB5
HW

HW

5

4

3

2

HW

+1.05V/+1V

+1.05V/+1V

+1.05V/+1V

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

1A

1A

1A

32 40Monday, July 28, 2014

32 40Monday, July 28, 2014

32 40Monday, July 28, 2014

5

4

3

2

1

33

D D

12

PC159

4.7u/25V_8

PR149 3.65K/F_4

PR152

11K/F_4

PR147 1/F_4

Core

12

PC188

4.7u/25V_8

*2.2_6

PR167

PC196

*2200P/50V_4

PR170 3.65K/F_4

2

VIN_VCC_GT

PC167

PC166

4.7u/25V_8

0.33uH

PR17646

*0_2/S

95833_ISUMPG_1

VIN_VCC_CORE

PC186

4.7u/25V_8

PC189

PR17651

*0_2/S

11K/F_4

PR175

PR171 1/F_4

PR135 *0_8/S

PC160

2200p/50V_4

PL11

PR17647
*0_2/S

95833_ISUMNG_1

PR162 *0_8/S

2200p/50V_4

PL12

0.33uH

95833_ISUMP_1

*100u/16V_7343

12

+

PR17652
*0_2/S

95833_ISUMN_1

12

+

PC161

*100u/16V_7343

+VCC_GFX

PC173*22u/6.3V_6

PC176*10U/6.3V_6

PC1720.1u/10V_4

VIN

+VCC_CORE

PC190*10U/6.3V_6

PC1910.1u/10V_4

PC195*22u/6.3V_6

NB5

NB5

NB5
HW

HW

HW

VIN

PC168

12

+

*15U_25V_3528

PC174*22u/6.3V_6

PC170

+

*220u/2V_7343

GFX_CORE Load Line :

-5.9mV/A for SDP=4.5W

PC193220u/2V_7343

PC192*22u/6.3V_6

+

+

VCORE Load Line :

-5.9mV/A for SDP=4.5W

PROJECT : Peach

PROJECT : Peach

PROJECT : Peach

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom

+VCC_CORE(ISL95833)

+VCC_CORE(ISL95833)

+VCC_CORE(ISL95833)

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

PC177

+

220u/2V_7343

PC194220u/2V_7343

+VCC_GFX

For EMI reserve

EC34

+VCC_GFX
PEAK : 14A
OCP : 18A

*0.1U/10V_4

Width : 600mil

+VCC_CORE

For EMI reserve

EC35

+VCC_CORE
PEAK : 12A

*0.1U/10V_4

OCP : 18A
Width : 500mil

33 40Friday, July 25, 2014

33 40Friday, July 25, 2014

33 40Friday, July 25, 2014

1A

1A

1A

PC157

PR134

*330p/50V_4

*2K/F_4

PR138

PR137

PC169

*330p/50V_4

PC171
*0.01u/50V_4

2

VR_ON

15

PGOOD

27

PGOODG

6

VR_HOT#

3

SCLK

4

ALERT#

5

SDA

VCC_AXG_SENSE_SRC
VSS_AXG_SENSE_SRC

ISEN28ISEN1

PR169
*0_2/S

PP5000

PC206

*0.01u/50V_4

PC205
*330p/50V_4

95833_ISUMNG

PR148

*649/F_4

PC178*4700P/25V_4

PR150 1.47K/F_4

95833_NTCG

95833_ISUMPG

32

1

33

PAD

NTCG

NTC

7

9

95833_NTC

95833_ISUMN

31

ISUMPG

ISUMNG

PU17

ISL95833HRTZ-T

ISUMP10ISUMN11RTN12FB13COMP

95833_ISUMP

PC199

*4700P/25V_4

PR174

1.27K/F_4
PR176

*649/F_4

VSS_SENSE_SRC
VCC_SENSE_SRC

4

VCC_AXG_SENSE8
VSS_AXG_SENSE8

PR143 *0_4/S
PR144 *0_4/S

Parallel

C C

PP3300_DX

PR159

PR186

27.4K/F_4

*100K/F_4

PR182 *0_4/S
PR181 *0_4/S

VCORE_EN27

IMVP_PWRGD_3V27,34,35

PP3300_DX

PR158 1.91K/F_4

95833_NTC

PR188

3.83K/F_4

PC184

43p/50V_4

PR184

27.4K/F_4

PP1000_PCH

H_PROCHOT#5,18,27

B B

VR_SVID_CLK6

VR_SVID_ALERT#6

VR_SVID_DATA6

PR183

470K_4 NTC

A A

PP3300_DX

VR_SVID_CLK

VR_SVID_ALERT#

VR_SVID_DATA

PR185

470K_4 NTC

VSS_SENSE8
VCC_SENSE8

PR160 *0_4/S

PR157 *1.91K/F_4
PR161 *0_4

PR156 *499/F_4

PR164 20/F_4

PR166 *0_4/S

PR168 16.9/F_4

95833_NTCG

PR189

3.83K/F_4

Parallel

5

2K/F_4

PC163

PR141

470p/50V_4

499/F_4

95833_COMPG

29

FBG

PR172

499/F_4

PR177 2K/F_4

28

VCCP

COMPG

BOOTG

UGATEG

PHASEG

LGATEG

PWM2

LGATE1

PHASE1

UGATE1

BOOT1

14

470p/50V_4

22

21

VDD

26

25

24

23

20

19

18

17

16

PC197

30

RTNG

24.9K/F_4

PC164

100P/50V_4

95833_BOOTG

95833_UGATEG

95833_PHASEG

95833_LGATEG

95833_LGATE1

95833_PHASE1

95833_UGATE1

95833_BOOT1

95833_COMP

100P/50V_4
PC198

PR178

24.9K/F_4

PR179
*2K/F_4

1000P/50V_4

PR154
*0_4/S

PC182

1u/10V_4

1000P/50V_4

*330p/50V_4

PC158

PP5000

PC202

PC203

PR155
*0_4/S

PC183

1u/10V_4

PC162

0.22u/25V_6

PC185

0.22u/25V_6

PR139

21K/F_4

PR173

64.9K/F_4

3

95833_UGATEG

95833_UGATE1

PR17638

1_6

95833_LGATEG

95833_ISUMPG

PC179

*0.1u/25V_4

95833_ISUMNG

PR17637

1_6

95833_LGATE1

95833_ISUMP

PC200

*0.1u/25V_4

95833_ISUMN

95833_UGATEG_1

PQ19
FDMS3664S

PC181

0.1u/25V_4

95833_UGATE1_1

PQ20
FDMS3669S

PC204

0.1u/25V_4

G1

1

S1/D2

8

G2

PC6270

*4.7n/25V_4

G1

1

S1/D2

8

G2

VIN_VCC_GT

PC165

0.1U/25V_4

95833_PHASEG

PR17648

2.61K/F_4

12

10K/F_4 NTC

PC187

0.1U/25V_4

95833_PHASE1

PC201

33n/25V_4

PR145

PC175

*2.2_6

*2200P/50V_4

PR146

12

12

VIN_VCC_CORE

12

PR17649

2.61K/F_4

PR17650

10K/F_4 NTC

2

D1D1D1

9

S2S2S2

567

PC180

33n/25V_4

2

D1D1D1

9

S2S2S2

567

PC6271

*4.7n/25V_4

1

2

3

4

5

PP1350PP1000_PCH_S5

PC207

0.1U/10V_4

1

A A

IMVP_PWRGD_3V27,33,35

PP1350_PCH_SX_PG15

B B

TDC : 1.43A
PEAK : 1.9A
Width : 80mil

IMVP_PWRGD_3V

PP1350_PCH_SX_PG

PR190
*0_6/S

PP5000_DSW

PR206 *0_4/S

PP1350_PCH

PC209
*10U/6.3V_6

PC213

0.1U/10V_4

PR209*0_4/P

PR200 4.7K_4

PC210

0.1U/10V_4

PC214
*0.1U/10V_4

13

VOUT1

14

VOUT1

4

VBIAS

3

ON1

PC216

2200P/50V_4

1.35V_PG_1

PC219
*1000P/50V_4

VIN12VIN1

PU18

APL3523A

CT1

12

2

7

VIN26VIN2

CT2

10

PC217
2200P/50V_4

PQ22
MMBT3904-7-F

1 3

OUT2
OUT2

GND
GND

ON2

1.35V_PG_2

PC208

0.1U/10V_4

PP1350_PCH_SX_1PP1000_PCH_SX_1PP1000_PCH_SX PP1350_PCH_SX

8
9

11
15

5

PC211

0.1U/10V_4

VSFR_EN EC_SLP_SX_L

PC215
*0.1U/10V_4

PR199

4.7K_4

2

PC218
1000P/50V_4

PR191
*0_6/S

PC212
*10U/6.3V_6

PR194 *0_4/S

PR196 *0_4/P

PP3300_PCH_S5

PR198

4.7K_4

PP1350_PCH_PG

PQ21

1 3

DTC144EUA

EC36

For EMI reserve

*0.1U/10V_4

PP1050_PCH_PG

PP1350_PCH_PG 30

TDC : 0.28A
PEAK : 0.375A
Width : 20mil

EC_SLP_SX_L 27

PP1000_PCH

PP1350_PCH_SX

PR300 *0_8

PP1350_PCH_SX PP1350_PCH

PR301 *0_6

VSFR_EN31

SUSP_VR_EN27,32

PP1050_PCH_PG27,32,35

PP1000_PCH_SX

PP1350_PCH

VSFR_EN

34

C C

D D

PROJECT : Peach

PROJECT : Peach

PROJECT : Peach

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom

NB5

NB5

NB5
HW

HW

HW

Date: Sheet of

Date: Sheet of

1

2

3

4

Date: Sheet of

LDO (1V/1.35V/1.5V/1.8V)

LDO (1V/1.35V/1.5V/1.8V)

LDO (1V/1.35V/1.5V/1.8V)

5

1A

1A

1A

34 40Thursday, July 31, 2014

34 40Thursday, July 31, 2014

34 40Thursday, July 31, 2014

1

2

3

4

5

1.0V_PG_2

PQ24
MMBT3904-7-F

1 3

PP3300_DSW

PC234

0.1U/10V_4

PC240

1U/6.3V_4

PP1800_PCH_PG30

3

VIN

2

EN
VDD4GND

1

PGOOD

R2

PR208

4.7K_4

2

PC231
1000P/50V_4

NC

PU20
G9661

VOUT

GND

ADJ

7

R1

PR218
100K/F_4

VO=(0.8(R1+R2)/R2)
R2<120Kohm

PP3300_PCH_S5

PR204

4.7K_4

PQ23

1 3

DTC144EUA

5

6

8
9

PR217

127K/F_4

PP1000_PCH_PG

PC236

10U/6.3V_6

PP1000_PCH_PG 32

TDC : 0.049A
PEAK : 0.065A
Width : 20mil

PP1800_PCH_S5_S

PC237

*10U/6.3V_6

PP1800_PCH_S5

PR214

*0_6/S

PC238

0.1U/10V_4

EC38

For EMI reserve

35

*0.1U/10V_4

7

VIN26VIN2

OUT2
OUT2

CT2

10

PC230
2200P/50V_4

PP3300_PCH

GND
GND

ON2

PP1350

PC221

0.1U/10V_4

8

PP1350_PCH_1PP1000_PCH_1PP1000_PCH PP1350_PCH

9

11
15

5

VIN

3

2

1

PR213
1M_4

PQ28

2N7002K

PC228
*0.1U/10V_4

PC224

0.1U/10V_4

PC239
*2.2n/50V_4

PR202
*0_6/S

PC225
*10U/6.3V_6

PR195 *0_4/S

PR197

*100K/F_4

PP3300_DSWVIN

3

2

PQ25
AO3404

1

TDC : 0.025A
PEAK : 0.033A
Width : 20mil

EC37

For EMI reserve

TDC : 0.315A
PEAK : 0.42A

*0.1U/10V_4

Width : 20mil

PP1050_PCH_PG

PP1000_PCH_S5_PG32

PP3300_PCH

PP1050_PCH_PG 27,32,34

PP1000_PCH

PR210 4.7K_4

PP1000_PCH_S5_PG

1.0V_PG_1

PR215
*0_4/S

PC235

*0.1U/10V_4

PP1800_PCH_S5_PG30

PP3300_DSW

2

PC232
*1000P/50V_4

PC233

10U/6.3V_6

PP5000_DSW

PR219 100K_4

PP1000_PCH_S5

TDC : 2.07A
PEAK : 2.75A
Width : 100mil

PR203 *0_4/P

PR205 *0_4/S

IMVP_PWRGD_3V

2

1 3

PQ26

DTC144EU

PR201
*0_6/S

PC222
*10U/6.3V_6

PR207 *0_4/S

PR211
1M_4

PR216
1M_4

A A

PP5000
PP5000_DSW

IMVP_PWRGD_3V27,33,34

B B

PP1800_PCH_PG

C C

PC226

0.1U/10V_4

2

PC220

0.1U/10V_4

PC223

0.1U/10V_4

PC227
*0.1U/10V_4

3

1

13

VOUT1

14

VOUT1

4

VBIAS

3

ON1

PC229

2200P/50V_4

PQ27
2N7002K

1

VIN12VIN1

PU19

APL3523A

CT1

12

PR212

22_8

PP3300_PCH_S5

PR220

4.7K_4

PR221

4.7K_4

PC241
1000P/50V_4

2

2

3.3V_PG_2

PC242
*1000P/50V_4

2

PQ30
MMBT3904-7-F

1 3

PP3300_PCH

D D

PR222 4.7K_4

1

3.3V_PG_1

PQ29

1 3

DTC144EUA

PP3300_PCH_PG 27

PROJECT : Peach

PROJECT : Peach

PROJECT : Peach

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom

NB5

NB5

NB5
HW

HW

HW

Date: Sheet of

Date: Sheet of

3

4

Date: Sheet of

LDO(1.2V/3.3V/1.8V)

LDO(1.2V/3.3V/1.8V)

LDO(1.2V/3.3V/1.8V)

5

1A

1A

1A

35 40Tuesday, July 29, 2014

35 40Tuesday, July 29, 2014

35 40Tuesday, July 29, 2014

1

2

3

4

5

3VPCU_VIN 5VPCU_VIN +VIN_DDR

A A

RFC6272
*2200P/50V_4

RFC6273
*2200P/50V_4

RFC6274
*2200P/50V_4

VIN_VCC_GT VIN_VCC_CORE

RFC6275
*2200P/50V_4

RFC6276
*2200P/50V_4

VIN_VCC_CORE

VIN_VCC_GT

VIN_VCC_CORE 33

VIN_VCC_GT 33

36

TOP

PAD1
*EMIPAD-RE118X79NP

B B

1

PAD2
*EMIPAD-RE118X79NP

1

PAD3
*EMIPAD-RE118X79NP

1

PAD5
*EMIPAD-RE118X79NP

1

PAD7
*EMIPAD-RE118X79NP

1

BOTTOM

PAD8
*EMIPAD-RE118X79NP

PAD9
*EMIPAD-RE118X79NP

PAD11
*EMIPAD-RE118X79NP

PAD10
*EMIPAD-RE118X79NP

C C

1

D D

1

1

1

2

1

PROJECT : Peach

PROJECT : Peach

PROJECT : Peach

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

NB5

NB5

NB5
HW

HW

3

HW

4

Custom
Date: Sheet of

Date: Sheet of

Date: Sheet of

EMI/RF

EMI/RF

EMI/RF

36 40Friday, July 25, 2014

36 40Friday, July 25, 2014

36 40Friday, July 25, 2014

5

1A

1A

1A

5

Support S0iX

1

BAT-VVIN

EC_ACIN

ACPRESENT

D D

PP3300_RTC

2

5

PP3300_DSW

PP3300_DSW_EN PP5000_EN

4

VIN

1

V1P0A
TLV62130A

C C

B B

EN

PP3300_DSW

5

V1P8A
G9661-25

EN

PP1000_PCH_S5_PGD

PP3300_DSW

5

V3P3A
TPS22930

EN

PP1800_PCH_S5_PGD

S5 PWR

VIN

1

DDR VDDQ
VR

S5 PG

S3

S5

PP1000_PCH_SX_PG

A A

3V/5V

EN2

VOUT

PG

SUSP_VR_EN

VOUT

PG

VOUT

PP1350_EN

5

CHARGER

1

VIN

VR

PP1350

PP1350_VREF

+DDR_VTT_RUN

PP1350_PGOOD

PP5000_DSW

PP5000

EN1

PG

8

PP1000_PCH_S5

PP1000_PCH_S5_PGD

7

10

PP1800_PCH_S5

PP1800_PCH_S5_PGD

9

12

PP3300_PCH_S5

MOS

PP3300_PCH_S5_PGD

11

48

22

20

PP5000_PGOOD

23

24

49

25

S0IX
S3 PWR

Battery

5

19

21

49

+DDR_VTT_RUN

9

VCC can follow in the CORE rail sequence
or at the same time

11

13

S3
S3
S0IX

S3

S0 PWR

4

PWR
BTN

6

PP3300_PCH_S5_PGD

13

PP3300_PCH_PG (ALL_S0_PGD)

42

PP1350_PGOOD

25

PP5000_PGOOD

18

VCORE_PGOOD

29

44

EC_SLP_SX_L

VTT_PWRGD

S0IX

MOS

please PP3300_DX_EN
early than VCORE_EN

VIN

1

IMVP
VR

SVID

CPU

4

+V1P0S

AON7400AL

ENENENENEN

+V1P05S

TLV62150ARGTR

+V1P35S

AO3404

+V1P8S

G9661-25

+V3P3S

AO3404

8

1

23

5

PP3300_DSW

5

50

S0 PWR

VCC

VNN

PG

EN

PG

PG

PG

PG

PG

PWR_BTN_L

HWPG_S5

HWPG_S0

EC_SLP_SX_L

S0IX_PGD

VCORE_EN

29

31

+VCORE

+VGFX

30

VCORE_PGOOD

VCORE_EN

PP1000_PCHPP1000_PCH_S5

PP1000_PCH_PG
MOS

IMVP_PWRGD_3V

35

PP1050_PCH_PG

36

PP1000_PCH_PG

34

PP1350_PCHPP1350

PP1350_PCH_PG

MOS

PP1050_PCH_PG

PP1800_PCHPP3300_DSW

PP1800_PCH_PG

PP1500_PCH_PG

PP3300_PCH

PP3300_PCH_PG

MOS

PP1800_PCH_PG

3

EC_ACIN

PCH_RSMRST_L

EC

14

16 PMC_SUSPWRDNACK

PCH_SLP_S4_L

18

PCH_SLP_S3_L

CORE_PWROK

EC_PWROK

PP5000_EN

PP1350_EN

SUSP_VR_EN

PP3300_DX_EN

7

28

32

29

33

34

32

PP1050_PCHVIN

PP3300_DSW_EN

2

192

4

PP1350

23

+VSFR
MOS AO3404

33

+V1P0SX
MOS AO3404

VOUT

EN

EC_SLP_SX_L

PP1000_PCH

VOUT

EN

PP1350_PCH_SX_PG

t1 : RTC_VCC to ILB_RTC_TEST# de-assertion 9ms -min (2-3)

t1 : RTC_VCC to PMC_RSMRST# de-assertion 9ms-min (2-11)

27

45

PP1350_PCH_SX

MOS

PP1350_PCH_SX_PG

44

47

PP1000_PCH_SX

MOS

PP1000_PCH_SX_PG

46

2

ILB_RTC_RST#

3

ILB_RTC_TEST#

3

ACPRESENT

PMC_SUSCLK[0]

15

PCH_PWRBTN_L

17

PMC_CORE_PWROK

52

PMC_SUS_STAT#

53

PLTRST#

54

CH_SLP_SX_L

43

P

ILB_RTC_RST#

ILB_RTC_TEST#

ACPRESENT

RSMRST#

PMC_SUSCLK[0]

SUSACK

PWRBTN#

SLP_S4#

SLP_S3#

PMC_CORE_
PWROK

PMC_SUS_
STAT#

PLTRST#

SLP_S0IX#

PCH

CPU

51

PP1350_PGOOD

25

DRAM_CORE_PWROK

46

DRAM_VDD_
S4_PWROK

DRAM_CORE_
PWROK

SVID

SVID

2

PP3300_RTC

VRTC

V1P0A

V1P24A

V1P8A

V3P3A

V1P0S

V1P05S

V1P35S

VAUD

V1P8S

VSDIO
VLPC
V3P3S

CORE PWR

VDDQ PWR

GPU PWR

1

37

PP1000_PCH_S5

PP1200_PCH_S5

PP1800_PCH_S5

PP3300_PCH_S5

PP1000_PCH

PP1050_PCH

PP1350_PCH

PP1500_PCH_TS

PP1800_PCH

PP3300_PCH

+VCORE

PP1350

+VGFX

S0IX

48

S0IX

t2 : V3P3A valid to PMC_RSMRST# de-assertion 10us -min (8-11)

37

38

36

39

40

38

t3 : PMC_RSMRST# to Internal RTC clock stable 100ms -max (11- RTC clock)
t4 : Internal RTC clock stable to PMC_SUSCLK[0] toggling 5ms -min (RTC clock - 12)
t5 : PMC_SLP_S4# de-assertion to PMC_SLP_S3# de-assertion 30us -min (15-25)
t6a : Core Well stable to DRAM_CORE_PWROK and PMC_CORE_PWROK assertion

(no PCIE device) 10ms -min (43-45)

t6b : Core Well stable to DRAM_CORE_PWROK and PMC_CORE_PWROK assertion
(for power rails needed by pcie device) 99ms -min (43-45)

t7 : DRAM/PMC_CORE_PWROK to PMC_SUS_STAT# 1ms -min (45-46)
t8 : PMC_SUS_STAT# de-assertion to PMC_PLTRST# de-assertion 60us -min (46-47)

a 10us to 2000us delay is required between rails to avoid inrush current caused by multiple loads
turning on simultaneously and fast charging of VR output decoupling

41

PROJECT : Peach

PROJECT : Peach

42

40

3

2

NB5

NB5

NB5
HW

HW

HW

PROJECT : Peach

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Docum ent Number Rev

Size Docum ent Number Rev

Size Docum ent Number Rev
Custom

Custom

Custom

Power Sequence

Power Sequence

Power Sequence

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

37 40Friday, July 25, 2014

37 40Friday, July 25, 2014

37 40Friday, July 25, 2014

1A

1A

1A

1

2

3

4

5

6

7

8

PP1800_PCH

38

2.2K2.2K

A A

SMBUS

AP2BH10
BG12

SMB_SOC_CLK
SMB_SOC_DAT

PP1800_PCH

XDP

Bay-trail M

BH22
BG23

I2C_0_SDA_C
I2C_0_SCL_C

4.7K4.7K

TRACK PAD

0x4bh

PP1800_PCH

4.7K4.7K

I2C_1_SDA_C

BG24

I2C_1_SCL_C

BH24

I2C

I2C_4_SDA_C

B B

BF27
BG27

I2C_4_SCL_C

Audio Codec

0x20h

PP1800_PCH

4.7K4.7K

ALS

0x44h

PP1800_PCH

4.7K4.7K

BH28
BG28

I2C_5_SDA_C
I2C_5_SCL_C

TOUCH SCREEN

0x4ah

PP3300_EC

C C

100

4.7K4.7K

Battery

100

EC_SMB0_CLK

E10

EC_SMB0_DATA

D3

Charger

PP3300_DX

KBC
TI

SMBUS

D D

1

F4

EC_SMB2_CLK

F3 EC_SMB2_DATA

2

3

4

4.7K4.7K

Thermal sensor

0x4ch

PROJECT : Peach

PROJECT : Peach

PROJECT : Peach

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom

NB5

NB5

NB5
HW

HW

HW

Date: Sheet of

Date: Sheet of

5

6

Date: Sheet of

7

SMBUS_I2C

SMBUS_I2C

SMBUS_I2C

8

1A

1A

1A

38 40Friday, July 25, 2014

38 40Friday, July 25, 2014

38 40Friday, July 25, 2014

5

4

3

2

1

(G3/DSW)

I

EC

D D

PP3300_DSW_EN

EC

VREG5

EN1

PP3300_DSW
PP5000

EN2

Vin

PP5000_PGOOD

PWRGDPP5000_EN

TPS5122

VREG3

VIN

II

SUSP_VR_EN

EC

C C

III

EC

PP1350_EN

VSFR_EN

PP1000_PCH_S5

Vout

V1P0A

EN

TLV62130A

S5 EN

S3 EN

PWRGD

Vin

PP1350_PGOOD

PP1350 PWRGD

+VSM

TPS51216

Vin

PP5000_DSW

PP5000

S5_Vout

S3_Vout

(S3)

PP5000

(G3/DSW)

PP3300_DSW

(ALW)

PP3300_RTC

(S5) (S5)

PP1000_PCH_S5_PG PP1800_PCH_S5_PG

PP3300_DSWVIN

EC

S5_Vout

S3_Vout

PP1800_PCH_S5

Vout

V1P8A

EN

G9661-25

Vin

PP1350

(S3)

PP1350_VREF

+DDR_VTT_RUN

(S0IX)

(S3)

PWRGD

PP3300_PCH_S5_PG
HWPG_S5

PP3300_PCH_PG
ALL_S0_PG

PP1000_PCH_SX_PG
ALL_S0IX_PG

PP3300_DSW

VIN

EC_SLP_SX_L

(USB Charger)

EC

USB1_PWR_EN

EC

USB2_PWR_EN

V3P3A

EN Vout

TPS22930

Vin

PG0

EC_PWROK(PH2) DRAM_CORE_PWROK

EC

PC4

CORE_PWROK(PF5)

PL6

TPS2546

TPS2546

(S5)

PP3300_PCH_S5

PG3

USBPWR1

USBPWR2

HW_circuit
HWPG

PP3300_PCH_S5_PG

SOC

PMC_CORE_PWROK

PCH_SLP_SX_L

PP3300_DSW

PP3300_DX

EC

PCH

PCH

EC

EC

PP3300_DX_EN

PP3300_WLAN_EN

PP3300_LTE_EN

TP_SHDN_L

EC_EDP_VDD_EN

TPS22964CYZPR

TPS22930

TPS22965DSGR

TPS22930

G5243AT11U

39

(S0)

PP3300_DX

PP3300_WLAN

+3V_LTE

(S3)

TP_PWR

(S0)

LCDVCC

Vout

ISL95833

Vin

+VCORE

PGOODG

Vout

(S0)

IMVP_PWRGD_3V

+VGFX

PP1000_PCH

Vout

EN EN

+V1P0S

AON7400AL

(S0)

Vin

PP1000_PCH_S5

PWRGD

(S0)

PP1000_PCH_PG

VIN

PP1050_PCH

Vout

+V1P05S

TLV62150ARGTR

Vin

PWRGD

(S0)

PP1050_PCH_PG

PP1350

EN

PP1350_PCH

Vout

+V1P35S

AO3404

Vin

PWRGD

(S0)

PP1350_PCH_PG

PP3300_DSW

EN

PP1800_PCH

Vout

+V1P8S

G9661-25

Vin

PWRGD

(S0)

PP1800_PCH_PG

B B

IV

+VCORE / +VGFX

EC

VR_EN

EN

VIN

PP3300_PCH

A A

PP1800_PCH_PG

Vout

EN

+V3P3S

AO3404

PWRGD

Vin

PP3300_DSW

5

(S0)

PP3300_PCH_PG
ALL_S0_PG

EC

V

PP1050_PCH_PG

EC_SLP_SX_L

R

VSFR_EN

R

4

PP1350_PCH_SX

(S0iX)

EN

PP1350

Vout

+VSFR

MOS AO3404

Vin

HW_circuit
HWPG

VCORE_PWRGD

PP1350_PCH_SX_PG

3

R
R

V1P0SX_EN

PP1000_PCH

PP1000_PCH_SX

(S0iX)

Vout

EN

+V1P0SX

MOS AO3404

Vin

HW_circuit
HWPG

R

PROJECT : Peach

PROJECT : Peach

PP1000_PCH_SX_PG

NB5

NB5

NB5
HW

HW

2

HW

PROJECT : Peach

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom

BTM PWR CONTROL

BTM PWR CONTROL

BTM PWR CONTROL

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

39 40Friday, July 25, 2014

39 40Friday, July 25, 2014

39 40Friday, July 25, 2014

1A

1A

1A

5

Version

Model

10/11

1A

0CX

D D

C C

B B

A A

DOC NO.

Change PU9 VCC, CLK, PG (Page 29)B01

B02

Change PU4 VCC, PG (Page 29)
Change PR29 from 100K/F_4 to 10K/F_4 (Page 32)B03

B04 Remove 15V, PR17. Mount PR16 (Page 34)

Remove 15V, PR72. Mount PR73 (Page 35)B05

10/14

Change U11 LVDS power switch footprint to sot23-5 (Page 17)B06

B07 Unstuff PR188 due to PP5000_PGOOD (PN0) is 5V to lerant input pin (Page 29)

10/16

B08

Change PJ1 from DFPJ06MR007 t o DFHD05MR080 (Page 28)

10/17

Change C126 from *10U/6.3V_8 to *10U/6.3V_6 due to height l imit (Page 24)B09
Change USB3.0 ESD D8,D9 route (Page 24)B10
Change R384 from 0_4 to 0_8, remove R376,R377. Merge UNCORE _V1P35_S0IX_A, UNCORE_V1P35_S 0IX_B & UNCORE_V1P35_S0IX (Pag e 9)B11

B12 Change R354 from 0 _4 to 0_8, remove R357. Merge CORE_V1P05_S3_PW, & CORE_V1P0 5. They are of the same power state and rail (Page 9)

10/18

B13

Correct BIOS Strap, mount R12 8 and dismount R434 (Page 4)

B14

Add R553 0_4, connect U12 pin 6 ALERT# to H_PROCHOT# (Page 5, 23)

B15 Change Y2 from BG3 32768224 to BG332768111 due to height limit, change C91,C92 from 18pf to 15pf (Page 6)

Add R554,R555 0_6 option S0 & S5 for PCU_V1P8_G3_V25 (Page 9)B16

B17 Change R469, EC_RS T#_Q pull up from PP3300_DX to PP3300_DSW (Page 23)

Swap L4 vertically (Page 25)B18

B19 Power modified:

Change PD1 from BCMAJ22AZ00 t o BCAFJ20AZ00 (Page 28)

10/21

B20

un-stuff R553 (Page 5)

B21

change SEL debugf footprint a nd PN(Page 18)

B22

change footprint and PN for H DMI (Page 19)

B23

change footprint and PN for U SB3(Page 25)

B24

change footprint for Hole3,4, 5,7 and add hole11(Page 25)

10/22

B25

un-stuff R182 for S5 leakage issue (Page 14)

B26

change thermal IC (Page 23)

B27

PJ1 pin1 change to VA (Page 2 8)

10/23

B28

unstuff R28 by Intel reques ( Page 2)

B29

unstuff R29 by Intel reques ( Page 3)

B30

RAM ID strap pin resistor cha nge to 1K, would be stronger ( Page 7)

B31

change cap C230 from 0.2pF to 3.3pF (Page 12)

B32

change cap C228 from 0.2pF to 3.3pF (Page 13)

B33

EC_IN_RW is OD,remove level s hift and PU to PP1800_PCH (Pag e 15,26)
change NGFF E key footprint a nd PN (Page 20)

B34

change footprint for Hole3,4, 5 and add 2 PAD for BATT_EN re serve (Page 25)

B35

SWAP L4 pin for layout (Page 25)

B36

SWAP RP1 pin for layout (Page 27)

B37

10/24

B38

change M_A_ODT0 PU to VTTby I ntel request (Page 12)

B39

change M_B_ODT0 PU to VTTby I ntel request (Page 13)

B40

correct schematic for R469 PU power rail (Page 23)

B41

SWAP L4 pin again for layout (Page 25)

B42

change footprint for Hole1,7, 9 (Page 25)

10/25

B43

Delete complete SSD(connector and caps), unstuff R215 and a dd test points on SATA signal s (Page 5,15,21)

B44

1025 add LTE SUSCLK feature ( Page 6,15,23)

B45

the damping of SDIO change to 0 ohm by Intel request Page 1 6)

B46

add PU for SDIO WP by Intel r equest (Page 16)

B47

remove Q31 becasue PU to PP33 00_DSW at EC side already (Pag e 23)

B48

change headphone CN6 footprin t and PN (Page 24)

B49

stuff PR188 due to 3.3V to EC is more safe(Page 29)

B50

PR135 change from 300 to 348 ohm for proto1 issue (Page 33)

B51

PR155 change from 300 to 340 ohm for proto1 issue (Page 33)

B52

PC57 change from 68p to 120p PC50 change from 150p to 2200p for proto1 issue (Page 33)

B53 PC99 change from 6 8p to 120p PC106 change from 1 50p to 2200p for proto1 issue (Page 33)

10/29

B54

unstuff R128,R372,R386,R364 u sing SoC internal PU (Page 4,5 )

B55

eDP power change to PIC fuse (Page 17)

B56

change R358 to 0 ohm by intel request( Page 21)

B57

remove pulled up resistors fo r eMMC data and cmd (Page 21)

10/30

B58

change C60 power netname for layout (Page 8)

B59

U10 change to 74AUP1G34 and s tuff it (Page 11)

B60

remove PREQ# pulled up resist or R323( Page 11)

B61

stuff Q47,R531,R530 and un-st uff R533,R542 for Track Pad I2 C (Page 15)

B62

HDMI DDC pulled up to HDMI_5V by intel request (Page 19)

B63

add Power LED for Intel testi ng (Page 22)

B64

Thermal IC VDD has two option , ome is PP3300_DSW(=PP3300_EC ), another is PP3300_DX, defa ult is stuffing to DSW rail( P age 23,27)

B65

add Power BTN for Intel testi ng(Page 27)

B66

for Gfx power, change C266,C2 89,C290 to 10uF and add 2 caps 10uF (Page 8)

B67

for core power, change C271,C 281,C280,C278,C273 to 10uF( Pa ge 8)

B68

for VR compensation, PR26 cha nge to 16.9K,PR23 change 10 oh m,PC50 change 1200pF,PC40 cha nge to 270pF,un-stuff PR22,PC5 4(Page 33)

B69 for VR compensatio n, PR76 change to 16.9K,PR86 c hange 10 ohm,PC106 change 120 0pF,PC114 change to 270pF,un-s tuff PR80,PC101(Page 33)

10/31

B70

remove TP44 and TP35 for GND vias adding (Page 8)

B71

remove C285( Page 9)

B72

N.C U10 pin1(Page 11)

B73

un-stuff PR129,PC37,PR158,PC1 18(Page 33)
stuff R273,R286,R289,R323 for Intel request(Page 11)

B74
B75

for layout suggestion by inte l, VSS_AXG_SENSE didn't connec t to VSS_SENSE, will connect the GND via near VCC_AXG_SENSE (Page 8)

B76

add 0.1u on PP1000_PCH for po wer request(Page 33)

B77

remove R417, PRDY should be d irect connection between SoC a nd XDP by intel request (Page 6)

B78

for layout, add 0hm between G ND and VSS_AXG_SENSE (Page 8)

11/1

B79

add option BOM R446,R449 for EC CLK for power saving by Int el request (Page 7)

B80

stuff C16(Page 11)
B81 correct C351 footp rint(Page 16)
B82 change Hole4 footp rint (Page 25)

11/4

Change PR135 from 348/F_4 to 340/F_4 (Page 33)B83

11/11

C01 Remove CH@ USB ch arge option,eMMC@ eMMC option (Page 25)
C02 Add CHB@ option fo r single channel SKU (Page 13)

11/15

C03 stuff R372, system can't boot if un-stuff R372 o n proto1.5 board, need intel double confirm before proto2 ( Page 4)
C04 stuff R386, it is required for eDP (Page4)
C05 U18 footprint chan ge to 5 pin which is same as e DP power switch (Page 16)
C06 correct U11 orcad symbol, pin5 needs connect to power input (Page 17)
C07 remove R60 and cha nge R74 to Short PAD and size to 0402 (Page 19)
C08

change R72/R73/R22 to short P AD(Page 19)
C09

PR128 change to 1.62K (Page 3 3)
C10 Revising block dia gram (Page 1)

11/18

C11 add TP on pin38/73 for NFC function (Page 20)

11/21

C12 remove R28,R25,C35 (Page2)
C13 remove R29,R26,C36 (Page 3)
C14 by X'tal vender su ggestion,change C105/C106 from 15pF to 12pF (Page 6)
C15 remove R22/R72/R73 (Page 19)
C16

remove R365(Page 21)
C17

remove R91,R92,R94,R85 for ca ncelling non USB charger SKU ( Page 25)
C18 change USB3 CMC L5 ,L3, this part is recommended by Intel (Page 25)
C19 by X'tal vender su ggestion, change C107/C109 fro m 15pF to 18pF (Page 27)

11/28

C20 add a connection a nd name to KBD_IRQ#, besides a dd pulled high resistor (Page 6)
C21 remove R29,R26,C36 (Page 3)
C22 by X'tal vender su ggestion,change C105/C106 from 15pF to 12pF (Page 6)
C23 remove R166, becau se SERIQR of TPM needs 3V (Pag e 14)
C24

reserve 0 ohm R387/R391 on VC CA and VCCB for debugging(Page 14)
C25

change HDMI CMC L2, this part is recommended by Intel (Page 19)
C26 remove HDMI EMI so lution R30,R32,R40,R57 (Page 1 9)
C27 remove R358 by int el requst and has confirmed wi th EMI (Page 21)
C28 add pullup 10K on SERIRQ_R to TPM_VDD (Page 22)

11/29

C29 change PQ1,PQ2 par t number (Page28)
C30 add and stuff 470p F on PC7 and reserve 4700pF on PC18 for EMI solution (Page 28)
C31 because of power s ource of PU24,PU25 change to V IN, so that need change sensi ng power net (Page 32)

PQ29 change MOSFET with lower Rdson(Page 32)

C32
C33

change solutions of PP1050_PC H and P1000_PCH_S5 ,which powe r sources are VIN, it is bett er for power efficiency (Page 32)

PP1000_PCH changes from conve rt to power MOSFET type for po wer efficiency improvement(Pa ge 32)

C34

PP1350_PCH change from LDO to power MOSFET (Page 34)

C35

PP3300_PCH change from LDO to power MOSFET(Page 35)

C36
C37 Revising block dia gram,power sequence, and power tree for power changes by In tel suggestion(Page 1,37,39)

12/02

add C285 for U18 input inrush current (Page16)C38
C39

PJ2 changes footprint for lay out (Page 28)

change PC65 and PC39 from 4.7 uF to 10uF (Page 32)C40

add PR169,PR49 for Intel requ est,stuff PR169 as default(Pag e 32)C41
C42 add PR166,PR46 for Intel request,stuff PR166 as default(Page 32)

PQ29 change back AO3404(Page 32)C43
C44 PQ13 change to low er Rdson part, besides source of PQ13 changes to PP1000_PCH _S5 (Page 32)
C45 revising pull up p ower rail of PR169 and PR166(P age 32)
C46 change L2,(HDMI C MC),L3,L5(USB3)to DLP11TB800UL 2L as Intel's recommendation (Page 19,25)

12/04

for z-height issue, change C7 2,C75,C81 to 0.85mm cap (Page8 )C47
C48

reserve 3x1000pF cap for EMI( Page 25)

change Hole1 to be battery en able function (Page 25)C49

for z-height issue changePC48 ,PC49 to 0.85mm cap(Page 29)C50
C51 del PAD1 and PAD2( Page 25)

12/05

add 0.1uFx2 on PP1350 for EMI request (Page12)C52
C53

To prevent the backlight flas h, add a pull down on SoC_EDP_ BLON_C and using double inver ting OD FETs structure(Page 15 )

R551 changes to 1K to isolate SD socket and servo/SoC (Page 16)C54

SD3_WP is 1.8V power rail in SoC,change external Pulled up power well of SD3_WP to 1.8V power(Page 16)C55
C56 L2 change back to DLP11SA900HL2(Page 19)
C57 Swap L3,L5 pin for layout smoothly(Page 25)

12/06

change PU16,PU17 part number( Page 28)

C58
C59 change C271,C273,C 280,C266,C311,C315 to 0603 22u F for ACLL issue(Page 8)

12/09

reserve R220connection from R CVP to MIC_DET as back up in c ase driver needs to be throug h codec using JACKSNS pinr(Pag e 24)

C60
C61 remove JP9,JP13 fo r ACLL improvement(Page 33)

12/11

add pulled up resistors on SD IO data/cmd lines (Page16)C62
C63

add back pulled up resistors for eMMC I/F(Page 21)

co-layout ST and Infineon TPM , if change to ST,R56,R57,R60, R72,R38, ST PN is ST33ZP24AR2 8PVSM(Page 22)C64

change footprint for Hole9(Pa ge 25)C65
C66 move EC_PWROK from PH2 to PJ1(Page 27)
C67 add Test points on unused pins, need check layou t to see if all points are ok (Page 27)

12/12

add new RAMID 101 for single channel SKU (Page7)C68
C69

all Pulled up resistors of SD IO data/cmd to be un-stuffed(P age 16)

all Pulled up resistors of eM MC data/cmd to be un-stuffed,a nd R361 change to 47K ohm as well(Page 21)C70

add 2 holes , leave N.C(Page 25)C71

Stuff NUT on Hole4,5(Page 25)C72

change part number of EC ,whi ch has a trial firmware inside (Page 27)C73

reserve PR170 for battery cel l selection(Page 28)C74
C75 stuff PC211(Page 2 8)

12/13

swap CLKREQ_WLAN and CLKREQ_I MAGE for CLKREQ and CLK pins a re aligned (Page5)C76
C77

change pull up power of PP330 0_PCH_PG to PP3300_EC (Page 35 )

Board ID of proto2 change to 001 (Page27)

C78
C79

un-stuff PR176,PC202 as snubb er isnt needed (Page 28)

un-stuff PR74,PC104,PR81,PC11 5 as snubber isnt needed (Page 33)C80

PROJECT MODEL
:

PART NUMBER: DRAWING BY: REVISON:

5

4

Chrome APPROVED BY:

4

CHANGE LIST

3

2

1

40

PROJECT : Peach

PROJECT : Peach

DATE:

3

2

PROJECT : Peach

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size Docume nt Numb er Rev

Size Docume nt Numb er Rev

Size Docume nt Numb er Rev
Custom

Custom

Custom

Change list-1

Change list-1

Change list-1

NB5

NB5

NB5
HW

HW

HW

Date: Sheet o f

Date: Sheet o f

Date: Sheet o f

1

40 40Frid ay, July 25, 20 14

40 40Frid ay, July 25, 20 14

40 40Frid ay, July 25, 20 14

1A

1A

1A