HP AT-32063-TR1, AT-32063-BLK Datasheet

Low Current, High Performance
NPN Silicon Bipolar Transistor

Technical Data

AT-32063

Features

• High Performance Bipolar
Transistor Optimized for
Low Current, Low Voltage
Operation

• 900 MHz Performance:

1.1␣ dB NF, 14.5␣ dB G

A

• Characterized for End-of­Life Battery Use (2.7 V)

• SOT-363 (SC-70) Plastic
Package

• Tape-and-Reel Packaging
Option Available

[1]

Surface Mount Package SOT-363 (SC-70)

I I

Pin Connections and Package Marking

Description

The AT-32063 contains two high
performance NPN bipolar transis­tors in a single SOT-363 package.
The devices are unconnected,
allowing flexibility in design. The
pin-out is convenient for cascode
amplifier designs. The SOT-363
package is an industry standard
plastic surface mount package.

The 3.2 micron emitter-to-emitter
pitch and reduced parasitic design
of the transistor yields extremely
high performance products that
can perform a multiplicity of
tasks. The 20 emitter finger
interdigitated geometry yields a
transistor that is easy to match to
and extremely fast, with moderate
power, low noise resistance, and
low operating currents.

Optimized performance at 2.7 V
makes this device ideal for use in
900 MHz, 1.8 GHz, and 2.4 GHz
battery operated systems as an

LNA, gain stage, buffer, oscillator,
or active mixer. Typical amplifier
designs at 900 MHz yield 1.3 dB
noise figures with 12 dB or more
associated gain at a 2.7 V, 5 mA
bias, with noise performance
being relatively insensitive to
input match. High gain capability
at 1 V, 1 mA makes this device a
good fit for 900 MHz pager appli­cations. Voltage breakdowns are
high enough for use at 5 volts.

The AT-3 series bipolar transistors
are fabricated using an optimized
version of Hewlett-Packard’s
10␣ GHz ft , 30 GHz f

max

Self­Aligned-Transistor (SAT) process.
The die are nitride passivated for
surface protection. Excellent
device uniformity, performance
and reliability are produced by the
use of ion-implantation, self­alignment techniques, and gold
metallization in the fabrication of
these devices.

1

B

1

2

E

1

3

C

2

6

C

1

5

E

2

4

B

2

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5965-8921E

AT-32063 Absolute Maximum Ratings

[1]

Absolute

Symbol Parameter Units Maximum

Thermal Resistance

θjc = 370°C/W

[2]

:

V

EBO

V

CBO

V

CEO

I

C

P

T

T

j

T

STG

Electrical Specifications, T

Emitter-Base Voltage V 1.5
Collector-Base Voltage V 11
Collector-Emitter Voltage V 5.5
Collector Current mA 40
Power Dissipation

[2,3]

m W 150

Junction Temperature °C 150
Storage Temperature °C -65 to 150

= 25° C

A

Notes:

1. Permanent damage may occur if

any of these limits are exceeded.

2. T

Mounting Surface

Derate at 2.7 mW/°C for TC > 94.5°C.

3.

= 25°C.

4. 150 mW per device.

Symbol Parameters and Test Conditions Units Min. Typ. Max.

14.5

[2]

1.4

[2]

NF Noise Figure; VCE = 2.7 V, IC = 5 mA f = 0.9 GHz dB 1.1

G

h

I

I

FE

CBO

EBO

Associated Gain; VCE = 2.7 V, IC = 5 mA f = 0.9 GHz dB 12.5

A

Forward Current Transfer Ratio; VCE = 2.7 V, IC = 5 mA — 50 270

Collector Cutoff Current; V

Noise Figure; V

= 1 V µA 1.5

EB

= 3 V µA 0.2

CB

Notes:

1. All data is per individual transistor.

2. Test circuit, Figure 1. Numbers reflect device performance de-embedded from circuit losses. Input loss = 0.2 dB;
output␣ loss = 0.3␣ dB.

[2]

[2]

50 Ω

W = 10
L = 450

TEST CIRCUIT
BOARD MATERIAL = 0.047 GETEK (ε = 4.3)

DIMENSIONS IN MILS
NOT TO SCALE

W = 20
L = 60

W = 10
L = 100

50 Ω

Figure 1. Test circuit for Noise Figure and Associated Gain.
This circuit is a compromise match between best noise figure, best gain,
stability, and a practical synthesizable match.

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AT-32063 Characterization Information, T

= 25° C

A

Symbol Parameters and Test Conditions Units Typ.

P

G

IP

1 dB

Power at 1 dB Gain Compression (opt tuning); VCE = 2.7 V, IC = 20 mA f = 0.9 GHz dBm 12

Gain at 1 dB Gain Compression (opt tuning); VCE = 2.7 V, IC = 20 mA f = 0.9 GHz dB 16

1 dB

Output Third Order Intercept Point (opt tuning); VCE = 2.7 V, IC = 20 mA f = 0.9 GHz dBm 24

3

Typical Performance, T

2.00

1.50

(dB)

1.00

NOISE FIGURE

0.50

2.7V/2 mA

2.7V/5 mA

2.7V/20 mA

0

0.9 1.8 2.4
FREQUENCY (GHz)

Figure 2. Minimum Noise Figure vs.
Frequency and Current at VCE = 2.7 V.

18

15

12

(dBm)

9

G1 dB

6

3

0

0.9 1.8 2.4
FREQUENCY (GHz)

Figure 5. 1 dB Compressed Gain vs.
Frequency at VCE = 2.7 V and
IC=20mA.

= 25° C

A

20.0

15.0

(dB)

10.0

Ga

5.0

2.7V/2 mA

2.7V/5 mA

2.7V/20 mA

0

0.9 1.8 2.4
FREQUENCY (GHz)

Figure 3. Associated Gain at
Optimum Noise Match vs. Frequency
and Current at VCE = 2.7 V.

25

20

15

(dBm)

3

IP

10

2 mA

5

5 mA
10 mA
20 mA

0

0 0.5 1.0 1.5 2.0 2.5

FREQUENCY (GHz)

Figure 6. Third Order Intercept vs.
Frequency and Bias at VCE = 2.7 V, with
Optimal Tuning.

15

14

13

(dBm)

12

P1 dB

11

10

0.9 1.8 2.4
FREQUENCY (GHz)

Figure 4. Power at 1 dB Gain
Compression vs. Frequency at
VCE=2.7V and IC = 20 mA.

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