HP an1354 schematic

Practical Noise-Figure Measurement and
Analysis for Low-Noise Amplifier Designs

Application Note 1354

Table of contents

Introduction

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

The design process . . . . . . . . . . . . . . . . . . . . . . . . .3

Software modeling . . . . . . . . . . . . . . . . . . . . . . . .3

Functional requirements . . . . . . . . . . . . . . . . . . . .3

Selecting a device . . . . . . . . . . . . . . . . . . . . . . . . .4

Raw device modeling . . . . . . . . . . . . . . . . . . . . . .4

Device matching . . . . . . . . . . . . . . . . . . . . . . . . . .5

Design completion . . . . . . . . . . . . . . . . . . . . . . . .5

Design verification . . . . . . . . . . . . . . . . . . . . . . . . .6

Performance simulation . . . . . . . . . . . . . . . . . . . .6

Layout and prototype . . . . . . . . . . . . . . . . . . . . . .6

Design fine-tuning . . . . . . . . . . . . . . . . . . . . . . . . .7

Performance measurements . . . . . . . . . . . . . .7

Network measurements . . . . . . . . . . . . . . . . .7

Narrow band NF measurements . . . . . . . . . . . . .8

Receiver sensitivity . . . . . . . . . . . . . . . . . . . . .8

Why measure narrow band NF? . . . . . . . . . . .8

Narrow band example . . . . . . . . . . . . . . . . . . .9

Measuring narrow band NF . . . . . . . . . . . . . .9

Microwave NF measurements . . . . . . . . . . . . . .10

Swept LO . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Swept IF . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Mixer and receiver NF measurements . . . . . . . .12

Measurement uncertainty . . . . . . . . . . . . . . . . .13

Extraneous signals . . . . . . . . . . . . . . . . . . . . . . .13

Nonlinearities . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Instrumentation uncertainty . . . . . . . . . . . . . . . .14

Excess noise ratio (ENR) uncertainty . . . . . . . .15

Mismatch uncertainty . . . . . . . . . . . . . . . . . . . . .15

Instrument architecture uncertainty . . . . . . . . .16

Instrument NF . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Unwanted in-band power . . . . . . . . . . . . . . . . . .16

Overall uncertainty . . . . . . . . . . . . . . . . . . . . . . .17

Understanding and accurately measuring noise figure
(NF) in low-noise elements has become particularly
important to the development of next-generation
communications systems. This application note
examines the process of making practical noise­figure (NF) measurements of low-noise amplifiers
(LNAs) – a capability that can have a significant
impact on cost, performance, and required design
time for wireless receivers.

The examination begins by looking at a representative
LNA block design. Software simulation is leveraged
as a vehicle for demonstration and provides a bench­mark for subsequent NF measurement and analysis.
The design example reveals the typical steps required
to take an LNA block from concept to production. At
the prototype stage, actual NF measurements can be
taken, and the data compared with simulated perfor­mance.

For nearly 20 years, standard techniques and methods
for measuring the NF in LNAs for wireless receivers
served the emerging commercial industry well, and
have remained relatively unchanged. But over the
past few years, the performance of RF systems has
improved significantly, placing tighter limits on NF
specifications and greater measurement accuracy.
Some of the important features available in contem­porary NF analyzers are presented.

Going a step further, narrow bandwidth NF measure­ment concepts and requirements are introduced.
For instance, a bandpass filter is combined with an
amplifier block to yield a suitable method for making
a practical narrow-band measurement. Further, NF
measurements for frequency-conversion devices and
systems are explored, as well as consideration of
various options for measuring NF at microwave fre­quencies.

As the performance of RF devices continues to improve,
assessing NF measurement uncertainty becomes
increasingly valuable. The primary components
affecting ambiguity in measurement are presented,
as well as a useful methodology for approximating
the overall effect of measurement uncertainty.

2

The design process

Functional requirements

LNA design typically begins by assessing functional
requirements for the application. Candidate devices
are then selected based on specifications including
NF, stability, unilateral gain, and dynamic range. The
actual design work starts with S-parameters and
choice of an appropriate bias technique for the device,
followed by synthesis of matching networks. Layout
includes choosing vendor-specific parts, adding inter­connections and pads, followed by floor planning.
The performance is then analyzed, and the design is
optimized to assure requirements can be met using
specific vendor parts. Finally, the overall design is
reviewed.

Software modeling

The development of cost-effective amplifier designs
for wireless communications systems would be
virtually impossible without the use of advanced
software-based modeling technology. Today’s high­caliber tools typically provide an easy-to-use hierar­chical, windows-based user interface as illustrated in
Figure 1.

For illustration, the example amplifier is intended for
a handheld phone application, and will require a gen­eral low-noise receiver front-end to cover the 1.8GHz
and 2.3GHz mobile phone bands. Additional functional
requirements are listed below.

• Frequency range: 1.5-2.5GHz

• NF: <1dB

• Gain: >10dB

• VSWR: <2.0:1

• Supply voltage: 3V

The sub 1dB NF is important in this application, taking
on even greater importance than voltage standing wave
ratio (VSWR). However, a VSWR of 2.0:1 or better is
still highly desirable. Since the design is intended for
a portable device, low voltage operation using a 3-volt
battery is required. Cost is also a key constraint,
while space is slightly less critical. A distributed,
microstrip matching circuit will therefore be used to
minimize component count.

Figure 1. Tools such as Agilent’s Advanced Design System (ADS) provide an intuitive,
windows-based interface. Throughout this document, ADS is utilized to demonstrate
all models, schematics and simulation results. The Main window in ADS, shown at
the upper left, serves as a file manager and a portal to other ADS windows such as
the Layout or Schematic & Test Bench windows. The Graphic Server window (upper
right) offers a visual means of viewing, printing, and analyzing data from completed
simulations.

3

Selecting a device

Although an array of process and device technologies
may be suitable for the intended application, the
selected device for this example is an ultra low-noise
amplifier fabricated in a pseudomorphic high-electron
mobility transistor (PHEMT) gallium arsenide (GaAs)
process. The device features 0.5dB NF, +14dBm third­order intercept point, and 17.5dB gain at 2GHz, 4V,
60mA. The transistor is optimized for 0.9GHz to 2.5GHz
cellular PCS low-noise amplifiers (LNAs). The wide
gate width of the this device exhibits impedances
that are relatively easy to match, and the 1dB NF
requirement should also be easy to meet. The S-para­meters and noise parameters for this device are
shown in Figure 2.

Figure 3. This is the basic schematic of the amplifier using the ultra­low-noise ATF-34143 transistor. The model represents the raw device
with source resistance indicated for a self-biased condition.

The model accounts for through-hole vias and selected
source inductances produced by the printed circuit
board. Some source inductance can be beneficial,
because of its impact on input impedance and low­frequency stability. On the other hand, too much
inductance can cause high-frequency gain peaking,
which results in oscillations. With an 800 micron gate
width, the device in the example design exhibits rea­sonable tolerance to these effects. However, these
parasitics need to be included in the model since
they affect input and output impedance, which must
be matched.

Figure 2. S-parameters and noise parameters for the ultra-low noise
transistor in the design example (the Agilent ATF-34143). The file, as
shown, is downloadable from the Agilent website formatted for use
directly with ADS.

Raw device modeling

The schematic of the amplifier device, shown in
Figure 3, reveals some source resistance for self bias.
This configuration forces the gate negative with
respect to the source, allowing the drain current to
be set with the source resistor (Rs=Vgs/Id). This
simple biasing technique is very appealing, since it
reduces the overall parts count. The source resistor
is AC bypassed, using a low-impedance capacitor
with the desired operating frequency.

The Smith chart in Figure 4 provides a convenient
way to examine the various impedances for the tar­get device, which in turn can be leveraged to synthe­size an appropriate matching network.

Figure 4. Simulated noise and S-parameters for the transistor model,
with S11, S22 and NFmin plotted on a Smith chart.

4

Device matching

Design completion

From the Smith chart it is clear that the device exhibits
some capacitive behavior. Therefore, the matching
network can be a simple high-pass impedance circuit
fashioned from a series capacitor and shunt inductor
as seen in Figure 5.

Figure 5. Since the device is capacitive, a simple high-pass impedance
circuit can be used for the matching network.

The high-pass topology is especially well suited for
personal communications services (PCS) and wireless
LAN applications since it offers sufficient low-frequency
gain reduction, which can minimize the amplifier’s
susceptibility to cellular and pager transmitter over­load. A similar high-pass structure is used for the
output impedance matching network, which is opti­mized for best-return loss and output power.

There are a number of options to determine component
parameters for the matching network. Manual calcu­lation using the device’s impedances represents the
most basic approach. Alternately, while most engineers
are reluctant to use the Smith chart, it provides a
simple, intuitive way of manipulating impedance, and
therefore developing matching networks. Modeling
software is another method of synthesizing and opti­mizing matching networks based on input and output
impedances.

After the initial optimization, finishing touches can be
made to the amplifier model. Inductors are replaced
with distributed elements and discrete components
are replaced with parts from vendor libraries as seen
in Figure 6.

Figure 6. Here are the synthesized matching circuits for the ultra-low­noise transistor example. After requirements for input and output return
loss, NF and gain are entered, the software optimizes matching circuit
parameters for best results. Inductances are substituted with distributed
elements and discrete components are replaced with behavioral models
of actual parts from vendor libraries.

The 50Ω resistor between the input inductor and
ground provides a DC return for the gate terminal of
the device. This also supplies an effective low-frequency
resistive termination for the device, which is necessary
for stable device operation. In addition to being part
of the matching network, the output inductor
doubles as a way of decoupling the power supply.

With all components defined and the effects of
through-hole vias included in the model, the circuit
is once again optimized and its performance is
assessed. At this point, parameters and components
can be re-tuned if required.

5

Design verification

Layout and prototype

Performance simulation

When the finished design is simulated, it looks like
the effort is on track so far. NF for the amplifier easily
meets the requirement of less than 1dB, peaking at
around 0.85dB as seen in Figure 7. The design also
supplies adequate gain. Input and output VSWRs are
also entirely respectable, although they do peak at
the specified upper limit of 2.0:1.

No matter how good simulations look, the ultimate
goal is a working circuit. Simulations are wholly
dependent on the accuracy of device models – they
cannot replace actual measurements on real circuits.
Simulation is merely a tool that speeds up the design
process. The real ‘proof of the pudding’ is in the pro­totype circuit.

Creating the prototype starts by generating a layout
for the amplifier as shown in Figure 8. Once the schemat­ic is imported into a layout tool, such as the Layout
module in ADS, components, grounding planes, and
transmission lines are placed. The distributed inductors,
which can clearly be seen in Figure 8, were inten­tionally made longer than required to enable later
modification.

Layouts created in one software modeling tool can
usually be ported to other tools. This simplifies the
task of developing sub-systems of a design indepen­dently, for later integration. The layout shown in
Figure 8 was used to build the finished prototype in
Figure 9.

Figure 7. These plots show simulated NF as well as gain and match for
the finished amplifier design.

Figure 8. This layout was generated in a layout tool directly from the
schematic. The layout was printed on high-quality film using a standard
inkjet printer, which was then used to produce the PCB from Rogers
4350 material for the prototype.

Figure 9. The prototype amplifier.

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