HP 5F2510P-Quanta-OT2 Schematics
5
4
3
2
1
CK505
P16
14.318MHz
P17
Cable Docking
1 TO 4 USB HUB
LINE IN
LINE OUT
RJ45
CRT PORT
SVIDEO OUT
POWER JACK
Sapporo 1.0 BLOCK DIAGRAM
CPU Thermal
Sensor
MAX6657
P04
DDR2-SODIMM1
Clock Generator
P33
P35
P34
P38
P37
Ambient Light Sensor
P36
LCD Panel
P39
CRT port
P18
P27
LVDS
R.G,B
Merom
478Pins
(Micro-FCBGA)
667/800 MHz FSB
Crestline
1299 uFCBGA
P7,P8,P9,P10,P11
DMI
P4,P5
Singal Channel DDR2
CPU CORE
DD
+1.05V/+1.5V
/+1.25V/+1.25VM
3VPCU/5VPCU
1.8V/SMDDR_VTERM/SMDR_VREF
BATT CHARGER
MAX8724/1908
DISCHARGE
+3VM_LAN_SW/3V_S5/+3V_CK505/3VSUS/+3V
CC
+5V/5VSUS
P35
PCI-E
HDD (1.8 inch)
DVD-ROM
BB
SIM CARD
P19
AA
P28
P28
USB PORT 0
USB PORT 1(POWER
USB)
Bluetooth Module
FingerPrint(AES2501B)
WWAN MiniCard
USB for Docking
P30
P30
P30
P30
P19
P32
PATA
USB 2.0
Accelerometer
TPM (1.2)
SLB9635
SMBUS
LIS3LV02DL
3.3V LPC, 33MHz
ICH8M
P12,P13,P14,P15
SMSC KBC1070
PCI-E
PCI BUS
PCMCIA /SMART CARD
Azalia
SPI
SYSTEM
BIOS
P31
P26
SATA/PATA
WLAN MiniCard
PCMCIA Controller
Ricoh 5C847
P20,P21
P20
P19
Intel Nineveh-MM
1394
P21
Audio
CODEC
AD1981
MODEM
MDC 1.5JACK
P22,P23
RJ11
P30P30
LAN
P24,P25
RJ45
P25
AMP
TPA6211A
P23
AMP
TLV2462CDGKR
P23
AUDIO
JACK
P23
MIC
JACK
P23
FAN
P29P29P29
5
4
Track
Point
3
Keyboard
SizeDocument NumberRev
2
Date:Sheet of
PROJECT : OT2
Quanta Computer Inc.
System Block Diagram
1
142Thursday, March 22, 2007
1ACustom
5
4
3
2
1
INDEXPower & Ground
Description
1
Schematic Block Diagram
2
DD
CC
BB
System Information
3
System Power Block Diagram
4-5
Merom CPU/THERMAL SENSOR
7-11
Crestline_
12-15
ICH8_M
16
DDR II SO-DIMM
17
CLOCK GEN
18
LCD CONNECTOR / LCD PWR
19
WAN/WWAN /SIM CARD connector
20-21
CARDBUS CONTROLLER
22-23
AUDIO CODEC / AUDIO JACK
24-25
LAN/TRANSFORMER
26
KBC
27
CRT PORT
28
HDD / CD-ROM
29
FAN,KB,LEDs,TRACK POINT
30
USB,BLUE TOOTH,FINGER PRINT, MDC,TPM
31
POWER SEQUENCE,BIOS
32
CABLE DOCKING
33
DISCHARGE
34
-CHARGER(MAX1908/8724)
35
MAX1999(3VPCU/5VPCU)
36
MAX1992(1.8VSUS/DDR_VTERM)
37
MAX1540 (+1.05V/+1.5V)
38
--MAX8736
39
+3VM/+3V_S5/1.25V_M
40
POWER SEQUENCE
NOTEPg#
Label
VIN
MBAT
VCCRTC
+15V
CPU_CORE
+1.05V
+1.05VMM0.M1IAMT_ON
+3V
3VSUS
3V_S5S5_ONS0, S3, S4, S5
3VPCU
+5V
5VSUS
5VPCU
+1.5VS0
+1.5VM
1.8VSUS
+2.5VMAINONS0
SMDDR_VREF
VDDA
+3V_CK505M0.M1IAMT_ON
+3V_LAN_SWM0.M1IAMT_ON
+1.25VS0MAIND
+1.25VMM0.M1IAMT_ON
ACTIVE
S0, S3, S4, S5.M0.M1.Moff
S0, S3, S4, S5.M0.M1.Moff
S0, S3, S4, S5.M0.M1.Moff
S0, S3, S4, S5.M0.M1.Moff
S0
S0
S0
S0, S3
S0, S3, S4, S5.M0.M1.Moff
S0
S0, S3
S0, S3, S4, S5.M0.M1.Moff
M0.M1
S0, S3SUSON
S0
S0, S3
S0MAINON
+15V
DDR COMMAND & CONTROL PULL UP POWER
DDR REF POWER
AUDIO ANALOG POWER (5V)
Description
AC ADAPTER (19V)
MAIN BATTERY + (10~17V)
RTC & KBC POWER
CPU CORE POWER (1.25/1.15V)
FSB POWER (1.05V)
ALWAYS POWER (3V)
ALWAYS POWER (5V)
DDR CORE POWER
(3_3V)
Control
Signal
VRON
MAIND
MAIND
SUSON
MAIND
SUSON
S5_ONS0, S3, S4, S55V_S5
MAIND
IAMT_ON
MAINONSMDDR_VTERM
SUSON
PCB STACK UPPCI DEVICES IRQ ROUTING
PCI_INTDEVICEREQ/GNT #IDSEL #
AA
5
LAYER 1 : TOP
LAYER 2 : GND
LAYER 3 : IN1
LAYER 4 : IN2
LAYER 5 : VCC
LAYER 6 : IN3
LAYER 7 : GND
LAYER 8 : BOT
4
SM BUS
CLOCK GENERATOR
DDR II
Accelemter sensor
CHARGER
CPU THERMAL SENSOR
3
ADDRESSDEVICEBUS
PROJECT : OT2
SizeDocument NumberRev
2
Date:Sheet of
Quanta Computer Inc.
System Information
1
242Thursday, March 22, 2007
1ACustom
5
4
3
S5_ON
2
1
SYSTEM POWER BLOCK DIAGRAM
IAMT_ON
DD
Adaptor
VIN
CC
CHARGER
S.W
MOS-FET
VIN
3VPCU
ALWAYS
MAX1999
MAIND
S.W
MOS-FET
S.W
MOS-FET
IAMT_ON
S.W
MOS-FET
IAMT_ON
SC4215+1.25VM
S.W
MOS-FET
SUSD
3V_S5
+3V_CK505
+3VM_LAN_SW
+3V
3VSUS
MAX8724/1908
+15V
MAIND
SUSD
S.W
MOS-FET
+5V
5VSUS
5VPCU
ALWAYS
BATTERY
BB
S.W
MOS-FET
SUSON
MAX1992
MAINON
1.8VSUS
MAINON
MAINON
TPS51100
SMDDR_VTERM
SMDDR_VREF
VIN
1.5V
MAX1540
1.05V_M
VIN
VRON
AA
CPU_VID[0..5]
HWPG
DPRSLPVR
STP_CPU#
5
MAX1907
4
IAMAT_ON
KBC_PW_ON
SLP_S5#
SLP_S3#
CPU_CORE
3
SC4215
MAIND
S.W
MOS-FET
TC7SH08FU
TC7SH08FU
TC7SH08FU
S5_ON
+1.25V
+1.05V
MAINON
DISCHARGE
DISCHARGE
DISCHARGE
2
S5_OND
SUSDSUSON
MAIND
PROJECT : OT2
SizeDocument NumberRev
Date:Sheet of
Quanta Computer Inc.
System pwr block diagram
1
342Thursday, March 22, 2007
1ACustom
1
2
3
4
5
6
7
8
R11256
H_IERR#
1 2
XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#
R10575
H_PROCHOT#
H_THERMDA
H_THERMDC
OBSFN_C0
OBSFN_C1
OBSDATA_C0
OBSDATA_C1
OBSDATA_C2
OBSDATA_C3
OBSFN_D0
OBSFN_D1
OBSDATA_D0
OBSDATA_D1
OBSDATA_D2
OBSDATA_D3
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
3
H_ADS#(6)
T25PAD
H_BNR#(6)
H_BPRI#(6)
H_DEFER#(6)
H_DRDY#(6)
H_DBSY#(6)
H_BR0#(6)
H_INIT#(12)
H_LOCK#(6)
H_RESET#(6)
H_RS#0(6)
H_RS#1(6)
H_RS#2(6)
H_TRDY#(6)
H_HIT#(6)
H_HITM#(6)
XDP_DBRESET#(14,31)
12
+1.05V
PM_THRMTRIP#(7,12)
CLK_CPU_BCLK(17)
CLK_CPU_BCLK#(17)
2
GND1
4
6
8
GND3
10
12
14
GND5
16
18
20
GND7
22
24
26
GND9
28
30
32
GND11
34
36
38
GND13
40
42
44
46
48
50
GND15
52
TDO
54
TRSTn
56
TDI
58
TMS
60
GND17
+1.05V
Layout Note:
Place voltage
divider within
0.5" of GTLREF
pin
+1.05V
R62
1K/F
H_PROCHOT#(39)
layout note for H_THERMDA/H_THERMDC - Trace width/Spacing
should be 10/10 mils
SI stage:no install to avoid leakage current
CLK_CPU_XDP(17)
CLK_CPU_XDP#(17)
XDP_DBRESET#
XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
DB1A stage:change for change list
1 2
R54
2K/F
1 2
XDP_DBRESET#(14,31)
+1.05V
R471K/F
R46*1K/F
R41*54.9/F
R40680
R36150
R3939
4
H_D#[0..63](6)
H_DSTBN#0(6)
H_DSTBP#0(6)
H_DINV#0(6)
H_D#[0..63](6)
H_DSTBN#1(6)
H_DSTBP#1(6)
H_DINV#1(6)
CPU_BSEL0(17)
CPU_BSEL1(17)
CPU_BSEL2(17)
DB1A:change for intel
schematic
R124
1 2
R119
1 2
C49
R125
1 2
Place C close to the
CPU_TEST4 pin. Make sure
CPU_TEST4 routing is
reference to GND and away
from other noisy signal.
*1K/F
*1K/F
12
*0.1U/10V
*0
H_RESET#
+3V
CPU_TEST1
CPU_TEST2
CPU_TEST4
CPU_TEST6
C50
0.1U
SYS_SHDN#(35)
C39
0.1U
C420
0.1U
C422
2200P
+1.05V
5
+3V
H_D#[0..63]
H_D#[0..63]
R350
100R
6657VCC
H_THERMDA
H_THERMDC
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
V_CPU_GTLREF
CPU_TEST1
CPU_TEST2
CPU_TEST3
CPU_TEST4
CPU_TEST5
CPU_TEST6
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
T92
PAD
T6
PAD
For the purpose of testability, route these signals
through a ground referenced Z0 = 55ohm trace that
ends in a via that is near a GND via and is
accessible through an oscilloscope connection.
U21B
E22
D[0]#
F24
D[1]#
E26
D[2]#
G22
D[3]#
F23
D[4]#
G25
D[5]#
E25
D[6]#
E23
D[7]#
K24
D[8]#
G24
D[9]#
J24
D[10]#
J23
D[11]#
H22
D[12]#
F26
D[13]#
K22
D[14]#
H23
D[15]#
J26
DSTBN[0]#
H26
DSTBP[0]#
H25
DINV[0]#
N22
D[16]#
K25
D[17]#
P26
D[18]#
R23
D[19]#
L23
D[20]#
M24
D[21]#
L22
D[22]#
M23
D[23]#
P25
D[24]#
P23
D[25]#
P22
D[26]#
T24
D[27]#
R24
D[28]#
L25
D[29]#
T25
D[30]#
N25
D[31]#
L26
DSTBN[1]#
M26
DSTBP[1]#
N24
DINV[1]#
AD26
GTLREF
C23
TEST1
D25
TEST2
C24
TEST3
AF26
TEST4
AF1
TEST5
A26
TEST6
B22
BSEL[0]
B23
BSEL[1]
C21
BSEL[2]
Merom Ball-out Rev 1a
CPU_TEST3
CPU_TEST5
DATA GRP 0 DATA GRP 1
MISC
DATA GRP 2DATA GRP 3
DSTBN[2]#
DSTBP[2]#
DINV[2]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
COMP[0]
COMP[1]
COMP[2]
COMP[3]
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
SLP#
H_D#33
AB24
H_D#34
V24
H_D#35
V26
H_D#36
V23
H_D#37
T22
H_D#38
U25
H_D#39
U23
H_D#40
Y25
H_D#41
W22
H_D#42
Y23
H_D#43
W24
H_D#44
W25
H_D#45
AA23
H_D#46
AA24
H_D#47
AB25
Y26
AA26
U22
H_D#48
AE24
H_D#49
AD24
H_D#50
AA21
H_D#51
AB22
H_D#52
AB21
H_D#53
AC26
H_D#54
AD20
H_D#55
AE22
H_D#56
AF23
H_D#57
AC25
H_D#58
AE21
H_D#59
AD21
H_D#60
AC22
H_D#61
AD23
H_D#62
AF22
H_D#63
AC23
AE25
AF24
AC20
COMP0
R26
COMP1
U26
COMP2
AA1
COMP3
Y1
E5
B5
D24
D6
D7
AE6
PSI#
Comp0,2 connect with Zo=27.4ohm,Comp1,3
connect with Zo=55ohm, make those traces
length shorter than 0.5".Trace should be
at least 25 mils away from any other
toggling signal.
H_D#32
Y22
H/W MONITOR
U28
1
VCC
2
DXP
3
DXN
4 5
-OVTGND
SMCLK
SMDATA
-ALT
MAX6657/GMT-781
6
SMBCK
8
SMBDT
7
THERM_ALERT#
6
SMBCK(17,19,27)
SMBDT(17,19,27)
THERM_ALERT#(14)
SizeDocument NumberRev
Date:Sheet of
(HOST BUS)/THERMAL
7
H_D#[0..63]
H_D#[0..63]
COMP0
COMP1
COMP2
COMP3
R78
54.9/F
1 2
H_D#[0..63](6)
H_DSTBN#2(6)
H_DSTBP#2(6)
H_DINV#2(6)
H_D#[0..63](6)
H_DSTBN#3(6)
H_DSTBP#3(6)
H_DINV#3(6)
H_DPRSTP#(7,12)
H_DPSLP#(12)
H_DPWR#(6)
H_PWRGOOD(12)
H_CPUSLP#(6)
PSI#(39)
R83
R67
54.9/F
27.4/F
1 2
1 2
1 2
PROJECT : OT2
Quanta Computer Inc.
442Thursday, March 22, 2007
8
R87
27.4/F
1ACustom
XDP_BPM#3
H_PWRGOOD
+1.05V
1
H_A#[3..16]
H_REQ#[0..4]
H_A#[17..35]
H_ADSTB#1(6)
+1.05V
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
T11
R760
R69*0
R710
R63*56/F
R660
R560
R571K/F
R4254.9/F
L_CLKCTLB(7)
L_CLKCTLA(7)
R3827/F
DB1A stage:change for change list
H_A#[3..16](6)
AA
H_ADSTB#0(6)
H_REQ#[0..4](6)
H_A#[17..35](6)
BB
H_A20M#(12)
H_FERR#(12)
H_IGNNE#(12)
H_STPCLK#(12)
H_INTR(12)
H_NMI(12)
H_SMI#(12)
CC
XDP_BPM#2
XDP_BPM#1
XDP_BPM#0
DD
U21A
J4
A[3]#
L5
A[4]#
L4
A[5]#
K5
A[6]#
M3
A[7]#
N2
A[8]#
J1
A[9]#
N3
A[10]#
P5
A[11]#
P2
A[12]#
L2
A[13]#
P4
A[14]#
P1
A[15]#
R1
A[16]#
M1
ADSTB[0]#
K3
REQ[0]#
H2
REQ[1]#
K2
REQ[2]#
J3
REQ[3]#
L1
REQ[4]#
Y2
A[17]#
U5
A[18]#
R3
A[19]#
W6
A[20]#
U4
A[21]#
Y5
A[22]#
U1
A[23]#
R4
A[24]#
T5
A[25]#
T3
A[26]#
W2
A[27]#
W5
A[28]#
Y4
A[29]#
U2
A[30]#
V4
A[31]#
W3
A[32]#
AA4
A[33]#
AB2
A[34]#
AA3
A[35]#
V1
ADSTB[1]#
A6
A20M#
A5
FERR#
C4
IGNNE#
D5
STPCLK#
C6
LINT0
B4
LINT1
A3
SMI#
M4
RSVD[01]
N5
RSVD[02]
T2
RSVD[03]
V3
RSVD[04]
B2
RSVD[05]
C3
RSVD[06]
D2
RSVD[07]
D22
RSVD[08]
D3
RSVD[09]
F6
RSVD[10]
Merom Ball-out Rev 1a
XDP_BPM#5
XDP_BPM#4
XDP_OBS0
XDP_OBS1
XDP_OBS2
XDP_OBS3
H_PWRGD_XDP
L_CLKCTLB
L_CLKCTLA
XDP_TCK
2
ADDR GROUP
0
ADDR GROUP
1
THERMAL
ICH
THERMTRIP#
RESERVED
T5
T2
ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#
BR0#
IERR#
INIT#
LOCK#
CONTROLXDP/ITP SIGNALS
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
HIT#
HITM#
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDO
TMS
TRST#
DBR#
PROCHOT#
THERMDA
THERMDC
H CLK
BCLK[0]
BCLK[1]
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
H1
E2
G5
H5
F21
E1
F1
D20
B3
H4
C1
F3
F4
G3
G2
G6
E4
AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
TDI
AB3
AB5
AB6
C20
D21
A24
B25
C7
A22
A21
JITP1
GND0
OBSFN_A0
OBSFN_A1
GND2
OBSDATA_A0
OBSDATA_A1
GND4
OBSDATA_A2
OBSDATA_A3
GND6
OBSFN_B0
OBSFN_B1
GND8
OBSDATA_B0
OBSDATA_B1
GND10
OBSDATA_B2
OBSDATA_B3
GND12
PWRGD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
GND14
SDA
SCL
TCK1
TCK0
GND16
*CONN60_ITP-XDP
1
2
3
4
5
6
7
8
VCC_CORE VCC_CORE
VCC_CORE
AA
VCC_CORE
All use 22U 6.3V(+-20%,X5R,0805)Pb-Free.
12
C44
22U/6.3V
12
C86
22U/6.3V
12
12
C173
22U/6.3V
C85
22U/6.3V
12
C172
22U/6.3V
12
C168
22U/6.3V
12
C171
22U/6.3V
12
C167
22U/6.3V
12
C169
22U/6.3V
12
C174
22U/6.3V
8 inside cavity, north side, secondary layer.
VCC_CORE
12
BB
VCC_CORE
12
C81
22U/6.3V
C143
22U/6.3V
12
C80
22U/6.3V
12
C142
22U/6.3V
12
12
C84
22U/6.3V
C79
22U/6.3V
12
C83
22U/6.3V
12
C145
22U/6.3V
12
C82
22U/6.3V
12
C144
22U/6.3V
8 inside cavity, south side, secondary layer.
VCC_CORE
12
C45
22U/6.3V
12
C170
22U/6.3V
12
C138
22U/6.3V
12
C139
22U/6.3V
12
C140
22U/6.3V
12
C141
22U/6.3V
6 inside cavity, north side, primary layer.
VCC_CORE
CC
12
C48
22U/6.3V
12
C47
22U/6.3V
12
C46
22U/6.3V
12
C43
22U/6.3V
12
C42
22U/6.3V
12
C41
22U/6.3V
6 inside cavity, south side, primary layer.
+1.05V
12
Layout out:
Place these
DD
inside
socket
cavity on
North side
secondary.
C98
0.1U/10V
12
C87
0.1U/10V
12
C105
0.1U/10V
12
C117
0.1U/10V
12
C96
0.1U/10V
12
C123
0.1U/10V
U21C
A7
VCC[001]
A9
VCC[002]
A10
VCC[003]
A12
VCC[004]
A13
VCC[005]
A15
VCC[006]
A17
VCC[007]
A18
VCC[008]
A20
VCC[009]
B7
VCC[010]
B9
VCC[011]
B10
VCC[012]
B12
VCC[013]
B14
VCC[014]
B15
VCC[015]
B17
VCC[016]
B18
VCC[017]
B20
VCC[018]
C9
VCC[019]
C10
VCC[020]
C12
VCC[021]
C13
VCC[022]
C15
VCC[023]
C17
VCC[024]
C18
VCC[025]
D9
VCC[026]
D10
VCC[027]
D12
VCC[028]
D14
VCC[029]
D15
VCC[030]
D17
VCC[031]
D18
VCC[032]
E7
VCC[033]
E9
VCC[034]
E10
VCC[035]
E12
VCC[036]
E13
VCC[037]
E15
VCC[038]
E17
VCC[039]
E18
VCC[040]
E20
VCC[041]
F7
VCC[042]
F9
VCC[043]
F10
VCC[044]
F12
VCC[045]
F14
VCC[046]
F15
VCC[047]
F17
VCC[048]
F18
VCC[049]
F20
VCC[050]
AA7
VCC[051]
AA9
VCC[052]
AA10
VCC[053]
AA12
VCC[054]
AA13
VCC[055]
AA15
VCC[056]
AA17
VCC[057]
AA18
VCC[058]
AA20
VCC[059]
AB9
VCC[060]
AC10
VCC[061]
AB10
VCC[062]
AB12
VCC[063]
AB14
VCC[064]
AB15
VCC[065]
AB17
VCC[066]
AB18
VCC[067]
Merom Ball-out Rev 1a
VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]
VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]
VCCA[01]
VCCA[02]
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
VCCSENSE
VSSSENSE
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
B26
C26
AD6
AF5
AE5
AF4
AE3
AF3
AE2
AF7
AE7
.
DB1A stage:change
to 330u
VCCSENSE
VSSSENSE
+1.05V
12
+
H_VID0(39)
H_VID1(39)
H_VID2(39)
H_VID3(39)
H_VID4(39)
H_VID5(39)
H_VID6(39)
VCCSENSE(39)
VSSSENSE(39)
C106
330U/4V
12
C156
0.01U/25V
Layout Note:
Place C156 near
PIN B26.
VCC_CORE
VCCSENSE
VSSSENSE
Route VCCSENSE and VSSSENSE
traces at 27.4ohms and
length matched to within 25
mil. Place PU and PD within
2 inch of CPU.
+1.5V
12
C163
10U/4V
12
R45
100/F
12
R44
100/F
U21D
A4
A8
A11
A14
A16
A19
A23
AF2
B6
B8
B11
B13
B16
B19
B21
B24
C5
C8
C11
C14
C16
C19
C2
C22
C25
D1
D4
D8
D11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
E19
E21
E24
F5
F8
F11
F13
F16
F19
F2
F22
F25
G4
G1
G23
G26
H3
H6
H21
H24
J2
J5
J22
J25
K1
K4
K23
K26
L3
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
P3 A25
VSS[082]
VSS[001]
VSS[002]
VSS[083]
VSS[003]
VSS[084]
VSS[004]
VSS[085]
VSS[005]
VSS[086]
VSS[006]
VSS[087]
VSS[007]
VSS[088]
VSS[008]
VSS[089]
VSS[009]
VSS[090]
VSS[010]
VSS[091]
VSS[011]
VSS[092]
VSS[012]
VSS[093]
VSS[013]
VSS[094]
VSS[014]
VSS[095]
VSS[015]
VSS[096]
VSS[016]
VSS[097]
VSS[017]
VSS[098]
VSS[018]
VSS[099]
VSS[019]
VSS[100]
VSS[020]
VSS[101]
VSS[021]
VSS[102]
VSS[022]
VSS[103]
VSS[023]
VSS[104]
VSS[024]
VSS[105]
VSS[025]
VSS[106]
VSS[026]
VSS[107]
VSS[027]
VSS[108]
VSS[028]
VSS[109]
VSS[029]
VSS[110]
VSS[030]
VSS[111]
VSS[031]
VSS[112]
VSS[032]
VSS[113]
VSS[033]
VSS[114]
VSS[034]
VSS[115]
VSS[035]
VSS[116]
VSS[036]
VSS[117]
VSS[037]
VSS[118]
VSS[038]
VSS[119]
VSS[039]
VSS[120]
VSS[040]
VSS[121]
VSS[041]
VSS[122]
VSS[042]
VSS[123]
VSS[043]
VSS[124]
VSS[044]
VSS[125]
VSS[045]
VSS[126]
VSS[046]
VSS[127]
VSS[047]
VSS[128]
VSS[048]
VSS[129]
VSS[049]
VSS[130]
VSS[050]
VSS[131]
VSS[051]
VSS[132]
VSS[052]
VSS[133]
VSS[053]
VSS[134]
VSS[054]
VSS[135]
VSS[055]
VSS[136]
VSS[056]
VSS[137]
VSS[057]
VSS[138]
VSS[058]
VSS[139]
VSS[059]
VSS[140]
VSS[060]
VSS[141]
VSS[061]
VSS[142]
VSS[062]
VSS[143]
VSS[063]
VSS[144]
VSS[064]
VSS[145]
VSS[065]
VSS[146]
VSS[066]
VSS[147]
VSS[148]
VSS[067]
VSS[068]
VSS[149]
VSS[069]
VSS[150]
VSS[070]
VSS[151]
VSS[071]
VSS[152]
VSS[072]
VSS[153]
VSS[073]
VSS[154]
VSS[074]
VSS[155]
VSS[075]
VSS[156]
VSS[076]
VSS[157]
VSS[077]
VSS[158]
VSS[078]
VSS[159]
VSS[079]
VSS[160]
VSS[080]
VSS[161]
VSS[081]VSS[162]
VSS[163]
Merom Ball-out Rev 1a
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
AF25
.
PROJECT : OT2
SizeDocument NumberRev
1
2
3
4
5
6
Date:Sheet of
Quanta Computer Inc.
Merom(POWER/NC)
7
542Thursday, March 22, 2007
8
1ACustom
1
2
3
4
5
6
7
8
H_A#[3..35]
H_ADS#(4)
H_ADSTB#0(4)
H_ADSTB#1(4)
H_BNR#(4)
H_BPRI#(4)
H_BR0#(4)
H_DEFER#(4)
H_DBSY#(4)
CLK_MCH_BCLK(17)
CLK_MCH_BCLK#(17)
H_DPWR#(4)
H_DRDY#(4)
H_HIT#(4)
H_HITM#(4)
H_LOCK#(4)
H_TRDY#(4)
H_DINV#0(4)
H_DINV#1(4)
H_DINV#2(4)
H_DINV#3(4)
H_DSTBN#0(4)
H_DSTBN#1(4)
H_DSTBN#2(4)
H_DSTBN#3(4)
H_DSTBP#0(4)
H_DSTBP#1(4)
H_DSTBP#2(4)
H_DSTBP#3(4)
H_REQ#0(4)
H_REQ#1(4)
H_REQ#2(4)
H_REQ#3(4)
H_REQ#4(4)
H_RS#0(4)
H_RS#1(4)
H_RS#2(4)
H_A#[3..35](4)
W10
AD12
AC14
AD11
AC11
AJ14
AE11
AH12
AH13
M10
N12
AE3
AD9
AC9
AC7
AB2
AD7
AB1
AC6
AE2
AC5
AG3
AH8
AE9
AH5
AE7
AE5
AH2
E2
G2
G7
M6
H7
H3
G4
F3
N8
H2
N9
H5
P13
K9
M2
Y8
V4
M3
J1
N5
N3
W6
W9
N2
Y7
Y9
P4
W3
N1
Y3
AJ9
AJ5
AJ6
AJ7
AJ2
AJ3
B3
C2
W1
W2
B6
E5
B9
A9
U30A
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
H_SWING
H_RCOMP
H_SCOMP
H_SCOMP#
H_CPURST#
H_CPUSLP#
H_AVREF
H_DVREF
CRESTLINE_1p0
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35
H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
HOST
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
H_RS#_0
H_RS#_1
H_RS#_2
H_D#[0..63]
H_RESET#(4)
H_CPUSLP#(4)
12
C186
0.1U/10V
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_SWING
H_RCOMP
H_SCOMP
H_SCOMP#
H_REF
C189
0.1U/10V
1 2
+1.05V
H_D#[0..63](4)
R132
1K/F
1 2
12
R136
2K/F
AA
+1.05V
12
R134
221/F
H_SWING
12
R141
100/F
BB
+1.05V
12
12
R175
R174
54.9/F
54.9/F
H_SCOMP
H_SCOMP#
12
CC
H_RCOMP
R142
24.9/F
Layout Note:
H_RCOMP trace should be
10-mil wide with 20-mil
spacing.
J13
B11
C11
M11
C15
F16
L13
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
B15
E17
C18
A19
B19
N19
G12
H17
G20
C8
E8
F12
D6
C10
AM5
AM7
H8
K7
E4
C6
G10
B7
K5
L2
AD13
AE13
M7
K3
AD2
AH11
L7
K2
AC2
AJ10
M14
E13
A11
H13
B12
E12
D7
D8
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
Layout Note:
Place the 0.1 uF
DD
decoupling capacitor
within 100 mils from
GMCH pins.
PROJECT : OT2
SizeDocument NumberRev
1
2
3
4
5
6
Date:Sheet of
Quanta Computer Inc.
Crestline_1(HOST)
7
642Thursday, March 22, 2007
8
1ACustom
1
SM_RCOMP_VOH
12
C280
0.01U/25V
SM_RCOMP_VOL
AA
12
C286
0.01U/25V
BB
Layout Note:
Location of all MCH_CFG strap
resistors needs to be close to
minmize stub.
MCH_BSEL0(17)
MCH_BSEL1(17)
MCH_BSEL2(17)
CC
+3V
PM_BMBUSY#(14)
DELAY_VR_PWRGOOD(14,31,39)
PM_THRMTRIP#(4,12)
PM_DPRSLPVR(14,39)
DD
1K/F
12
C279
2.2U/10V
12
C283
2.2U/10V
T18
PAD
T100
PAD
R159*4.02K/F
T33
PAD
T21
PAD
T23
PAD
R148*4.02K/F
T38
PAD
T26
PAD
R165*4.02K/F
R152*4.02K/F
T19
PAD
T27
PAD
R168*4.02K/F
T34
PAD
T30
PAD
R171*4.02K/F
R161*4.02K/F
H_DPRSTP#(4,12)
PM_EXTTS#0(16)
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PLT_RST-R#(13)
1
12
R210
PAD
PAD
PAD
PAD
12
PAD
PAD
R209
PAD
3.01K/F
PAD
PAD
PAD
PAD
PAD
12
PAD
PAD
R208
1K/F
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
12
12
12
12
12
12
12
PM_EXTTS#0
PM_EXTTS#1
PLTRST#_R
PM_THRMTRIP#
1 2
R1540
T109
T111
T120
T118
T113
T116
T115
T110
T108
T103
T98
T105
T107
T101
T99
T112
1.8VSUS
T36
T35
T37
T31
T49
T48
T46
T45
T29
T43
T44
T42
T47
T17
T22
T104
T58
T114
T55
T59
T119
T56
T54
T57
T52
T53
T117
T50
T60
T106
T20
T97
T24
T96
T102
T95
T94
T93
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
TP_NC1
TP_NC2
TP_NC3
TP_NC4
TP_NC5
TP_NC6
TP_NC7
TP_NC8
TP_NC9
TP_NC10
TP_NC11
TP_NC12
TP_NC13
TP_NC14
TP_NC15
TP_NC16
2
U30B
P36
RSVD1
P37
RSVD2
R35
RSVD3
N35
RSVD4
AR12
RSVD5
AR13
RSVD6
AM12
RSVD7
AN13
RSVD8
J12
RSVD9
AR37
RSVD10
AM36
RSVD11
AL36
RSVD12
AM37
RSVD13
D20
RSVD14
H10
RSVD20
B51
RSVD21
BJ20
RSVD22
BK22
RSVD23
BF19
RSVD24
BH20
RSVD25
BK18
RSVD26
BJ18
RSVD27
BF23
RSVD28
BG23
RSVD29
BC23
RSVD30
BD24
RSVD31
BH39
RSVD34
AW20
RSVD35
BK20
RSVD36
C48
RSVD37
D47
RSVD38
B44
RSVD39
C44
RSVD40
A35
RSVD41
B37
RSVD42
B36
RSVD43
B34
RSVD44
C34
RSVD45
P27
CFG_0
N27
CFG_1
N24
CFG_2
C21
CFG_3
C23
CFG_4
F23
CFG_5
N23
CFG_6
G23
CFG_7
J20
CFG_8
C20
CFG_9
R24
CFG_10
L23
CFG_11
J23
CFG_12
E23
CFG_13
E20
CFG_14
K23
CFG_15
M20
CFG_16
M24
CFG_17
L32
CFG_18
N33
CFG_19
L35
CFG_20
G41
PM_BM_BUSY#
L39
PM_DPRSTP#
L36
PM_EXT_TS#_0
J36
PM_EXT_TS#_1
AW49
PWROK
AV20
RSTIN#
N20
THERMTRIP#
G36
DPRSLPVR
BJ51
NC_1
BK51
NC_2
BK50
NC_3
BL50
NC_4
BL49
NC_5
BL3
NC_6
BL2
NC_7
BK1
NC_8
BJ1
NC_9
E1
NC_10
A5
NC_11
C51
NC_12
B50
NC_13
A50
NC_14
A49
NC_15
BK2 R32
NC_16TEST_2
CRESTLINE_1p0
R182100
PLTRST#_R
12
2
CFGRSVD
PM
NC
SM_CK#_0
SM_CK#_1
SM_CK#_3
SM_CK#_4
SM_CKE_0
SM_CKE_1
SM_CKE_3
SM_CKE_4
SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3
SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3
SM_RCOMP
DDR MUXINGCLKDMI
SM_RCOMP#
SM_RCOMP_VOH
SM_RCOMP_VOL
SM_VREF_0
SM_VREF_1
DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
PEG_CLK#
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VR_EN
GRAPHICS VIDME
CL_PWROK
SDVO_CTRL_CLK
SDVO_CTRL_DATA
CLK_REQ#
ICH_SYNC#
MISC
3
SM_CK_0
SM_CK_1
SM_CK_3
SM_CK_4
PEG_CLK
CL_CLK
CL_DATA
CL_RST#
CL_VREF
TEST_1
3
AV29
BB23
BA25
AV23
AW30
BA23
AW25
AW23
BE29
AY32
BD39
BG37
BG20
BK16
BG16
BE13
BH18
BJ15
BJ14
BE16
BL15
BK14
BK31
BL31
AR49
AW4
B42
C42
H48
H47
K44
K45
AN47
AJ38
AN42
AN46
AM47
AJ39
AN41
AN45
AJ46
AJ41
AM40
AM44
AJ47
AJ42
AM39
AM43
E35
A39
C38
B39
E36
AM49
AK50
AT43
AN49
AM50
H35
K36
G39
G40
A37
GFX_VR_EN
M_CLK_DDR0(16)
M_CLK_DDR1(16)
M_CLK_DDR#0(16)
M_CLK_DDR#1(16)
DDR_CKE0_DIMMA(16)
DDR_CKE1_DIMMA(16)
DDR_CS0_DIMMA#(16)
DDR_CS1_DIMMA#(16)
M_ODT0(16)
M_ODT1(16)
SMRCOMPP
SMRCOMPN
SM_RCOMP_VOH
SM_RCOMP_VOL
SMDDR_VREF_MCH
HP request
MCH_CLVREF
CLKREQ#_B(17)
MCH_ICH_SYNC#(14)
R172
20K
1 2
1 2
4
MCH_DREFCLK(17)
MCH_DREFCLK#(17)
DREF_SSCLK(17)
DREF_SSCLK#(17)
CLK_MCH_3GPLL(17)
CLK_MCH_3GPLL#(17)
DMI_MRX_ITX_N0(13)
DMI_MRX_ITX_N1(13)
DMI_MRX_ITX_N2(13)
DMI_MRX_ITX_N3(13)
DMI_MRX_ITX_P0(13)
DMI_MRX_ITX_P1(13)
DMI_MRX_ITX_P2(13)
DMI_MRX_ITX_P3(13)
DMI_MTX_IRX_N0(13)
DMI_MTX_IRX_N1(13)
DMI_MTX_IRX_N2(13)
DMI_MTX_IRX_N3(13)
DMI_MTX_IRX_P0(13)
DMI_MTX_IRX_P1(13)
DMI_MTX_IRX_P2(13)
DMI_MTX_IRX_P3(13)
R139
<check lisr & CRB>
For Calero : 255
For Cresstline:1.3K/F
For external VGA:0
ohm
DFGT_VID_0(38)
DFGT_VID_1(38)
DFGT_VID_2(38)
DFGT_VID_3(38)
R144
12
0
CL_CLK0(14)
CL_DATA0(14)
MPWROK(14,31)
ICH_CL_RST0#(14)
R137
0
4
L_IBG
R167
2.4K
1 2
UMA
SMRCOMPP
SMRCOMPN
TV_Y/G(32)
TV_C/R(32)
CRT_HSYNC(27)
DFGT_VR_EN(38)
CFG5
CFG9
CFG
[12:13]
CFG16
CFG19
CFG20
1.8VSUS
12
R198
20/F
12
R199
20/F
R166150/F
R163150/F
+3V
R15675/F
R16275/F
R14975/F
CRT_B(27)
CRT_G(27)
CRT_R(27)
DDCCLK(27)
DDCDATA(27)
CRT_VSYNC(27)
DMI X2 Select
PCI Express
Graphic Lane
XOR/ALLZ/Clock
Un-gating
FSB Dynamic
ODT
DMI Lane
Reversal
SDVO/PCIE
Concurrent
Operation
5
R160
100K
L_IBG
DPST_PWM
LCD_BLON
L_CLKCTLA
L_CLKCTLB
EDIDCLK
EDIDDATA
DISP_ONDISP_ON
L_VBG
L_VREFH
L_VREFL
TXLCLKOUTTXLCLKOUT+
TXLOUT0TXLOUT1TXLOUT2-
TXLOUT0+
TXLOUT1+
TXLOUT2+
R155*150/F
TV_Y/G
TV_C/R
DPST_PWM(18)
LCD_BLON(18)
L_CLKCTLA(4)
L_CLKCTLB(4)
EDIDCLK(18)
EDIDDATA(18)
DISP_ON(18)
TXLCLKOUT-(18)
TXLCLKOUT+(18)
TXLOUT0-(18)
TXLOUT1-(18)
TXLOUT2-(18)
TXLOUT0+(18)
TXLOUT1+(18)
TXLOUT2+(18)
LCD_BLON
T32
PAD
R9562.2K
R9572.2K
DB1A Stage: ADD
CRT_B
CRT_G
CRT_R
DDCCLK
R15039/F
R1391.3K/F
+1.25VM
MCH_CLVREF
C237
0.1U/10V
1 2
5
DDCDATA
CRTIREFCRTIREF
R14539/F
12
R179
1K/F
12
R180
392/F
Low=DMIx2
High=DMIx4(Default)
Low= Reveise Lane
High=Normal operation
00=Reserved.
01=XOR Mode Enabled.
10=ALL-Z Node Enabled.
11=Clock gating Enabled(default).
Low=Dynamic ODT Disable
High=Dynamic ODT Enable(default).
Low=Normal(default).
High=Lane Reversed
Low=Only SDVO or PCIEx1 is operational
(defaults)
High=SDVO and PCIEx1 are operating
simultaneously via PEG port
VSYNC
DB1A :install
+3V
R15110K
1 2
R15310K
1 2
R143*10K
1 2
DB1A:change to
10k
6
U30C
J40
L_BKLT_CTRL
H39
L_BKLT_EN
E39
L_CTRL_CLK
E40
L_CTRL_DATA
C37
L_DDC_CLK
D35
L_DDC_DATA
K40
L_VDD_EN
L41
LVDS_IBG
L43
LVDS_VBG
N41
LVDS_VREFH
N40
LVDS_VREFL
D46
LVDSA_CLK#
C45
LVDSA_CLK
D44
LVDSB_CLK#
E42
LVDSB_CLK
G51
LVDSA_DATA#_0
E51
LVDSA_DATA#_1
F49
LVDSA_DATA#_2
G50
LVDSA_DATA_0
E50
LVDSA_DATA_1
F48
LVDSA_DATA_2
G44
LVDSB_DATA#_0
B47
LVDSB_DATA#_1
B45
LVDSB_DATA#_2
E44
LVDSB_DATA_0
A47
LVDSB_DATA_1
A45
LVDSB_DATA_2
E27
TVA_DAC
G27
TVB_DAC
K27
TVC_DAC
F27
TVA_RTN
J27
TVB_RTN
L27
TVC_RTN
M35
TV_DCONSEL_0
P33
TV_DCONSEL_1
H32
CRT_BLUE
G32
CRT_BLUE#
K29
CRT_GREEN
J29
CRT_GREEN#
F29
CRT_RED
E29
CRT_RED#
K33
CRT_DDC_CLK
G35
CRT_DDC_DATA
F33
CRT_HSYNC
C32
CRT_TVO_IREF
E33
CRT_VSYNC
CRESTLINE_1p0
6
L_CLKCTLA
L_CLKCTLB
DFGT_VR_EN
LVDS
TV VGA
PCI-EXPRESS GRAPHICS
UMA
+3V
SMDDR_VREF_MCH
C633
0.1U/10V
1 2
DB2 stage:add
7
PEG_COMPI
PEG_COMPO
PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
R17010K
1 2
R16410K
1 2
1.8VSUS
R192
*10K/F
R1870
R191
*10K/F
PM_EXTTS#1
N43
M43
J51
L51
N47
T45
T50
U40
Y44
Y40
AB51
W49
AD44
AD40
AG46
AH49
AG45
AG41
J50
L50
M47
U44
T49
T41
W45
W41
AB50
Y48
AC45
AC41
AH47
AG49
AH45
AG42
N45
U39
U47
N51
R50
T42
Y43
W46
W38
AD39
AC46
AC49
AC42
AH39
AE49
AH44
M45
T38
T46
N50
R51
U43
W42
Y47
Y39
AC38
AD47
AC50
AD43
AG39
AE50
AH43
DB2 stage:R164 installPV stage:install for
SMDDR_VREF
R158*0
PM_EXTTS#0
PM_EXTTS#1
8
R16924.9/F
1 2
SMDDR_VREF(16,37)
PM_DPRSLPVR(14,39)
PROJECT : OT2
SizeDocument NumberRev
Date:Sheet of
Quanta Computer Inc.
Crestline(VGA,DMI)
7
742Thursday, March 22, 2007
8
+VCC_PEG
1ACustom
1
2
3
4
5
6
7
8
AA
DDR_A_D[0..63](16)
BB
CC
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
AR43
AW44
BA45
AY46
AR41
AR45
AT42
AW47
BB45
BF48
BG47
BJ45
BB47
BG50
BH49
BE45
AW43
BE44
BG42
BE40
BF44
BH45
BG40
BF40
AR40
AW40
AT39
AW36
AW41
AY41
AV38
AT38
AV13
AT13
AW11
AV11
AU15
AT11
BA13
BA11
BE10
BD10
BD8
AY9
BG10
AW9
BD7
BB9
BB5
AY7
AT5
AT7
AY6
BB7
AR5
AR8
AR9
AN3
AM8
AN10
AT9
AN9
AM9
AN11
U30D
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
CRESTLINE_1p0
DDR_A_BS0
BB19
SA_BS_0
SA_BS_1
SA_BS_2
SA_CAS#
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
SA_RAS#
SA_RCVEN#
DDR SYSTEM MEMORY A
SA_WE#
BK19
BF29
BL17
AT45
BD44
BD42
AW38
AW13
BG8
AY5
AN6
AT46
BE48
BB43
BC37
BB16
BH6
BB2
AP3
AT47
BD47
BC41
BA37
BA16
BH7
BC1
AP2
BJ19
BD20
BK27
BH28
BL24
BK28
BJ27
BJ25
BL28
BA28
BC19
BE28
BG30
BJ16
BJ29
BE18
AY20
BA19
DDR_A_BS1
DDR_A_BS2
DDR_A_CAS#
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_RAS#
DDR_A_WE#
*PAD
T51
DDR_A_BS0(16)
DDR_A_BS1(16)
DDR_A_BS2(16)
DDR_A_CAS#(16)
DDR_A_DM[0..7](16)
DDR_A_DQS[0..7](16)
DDR_A_DQS#[0..7](16)
DDR_A_MA[0..14](16)
BJ29 renamed to
SA_MA14 pin for intel
update 6/9
DDR_A_RAS#(16)
DDR_A_WE#(16)
AP49
AR51
AW50
AW51
AN51
AN50
AV50
AV49
BA50
BB50
BA49
BE50
BA51
AY49
BF50
BF49
BJ50
BJ44
BJ43
BL43
BK47
BK49
BK43
BK42
BJ41
BL41
BJ37
BJ36
BK41
BJ40
BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12
BG12
BJ10
BK10
BH5
BG1
BC2
BK3
BE4
BD3
BA3
BB3
AR1
AT3
AY2
AY3
AU2
AT2
BL9
BK5
BL5
BK9
BJ8
BJ6
BF4
BJ2
U30E
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
CRESTLINE_1p0
AY17
SB_BS_0
BG18
SB_BS_1
BG36
SB_BS_2
BE17
SB_CAS#
AR50
SB_DM_0
BD49
SB_DM_1
BK45
SB_DM_2
BL39
SB_DM_3
BH12
SB_DM_4
BJ7
SB_DM_5
BF3
SB_DM_6
AW2
SB_DM_7
AT50
SB_DQS_0
BD50
SB_DQS_1
BK46
SB_DQS_2
BK39
SB_DQS_3
BJ12
SB_DQS_4
BL7
SB_DQS_5
BE2
SB_DQS_6
AV2
SB_DQS_7
AU50
SB_DQS#_0
BC50
SB_DQS#_1
BL45
SB_DQS#_2
BK38
SB_DQS#_3
BK12
SB_DQS#_4
BK7
SB_DQS#_5
BF2
SB_DQS#_6
AV3
SB_DQS#_7
BC18
SB_MA_0
BG28
SB_MA_1
BG25
SB_MA_2
AW17
SB_MA_3
BF25
SB_MA_4
BE25
SB_MA_5
BA29
SB_MA_6
BC28
SB_MA_7
AY28
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
SB_RAS#
SB_RCVEN#
SB_WE#
BD37
BG17
BE37
BA39
BG13
BE24
AV16
AY18
BC17
BE24 renamed to
SB_MA14 pin for intel
update 6/9
DDR SYSTEM MEMORY B
DD
PROJECT : OT2
SizeDocument NumberRev
1
2
3
4
5
6
Date:Sheet of
Quanta Computer Inc.
Crestline(DDR2)
7
842Thursday, March 22, 2007
8
1ACustom
5
+1.05V
DD
1.8VSUS
CC
+VCCGFX
BB
AA
AT35
AT34
AH28
AC32
AC31
AK32
AJ31
AJ28
AH32
AH31
AH29
AF32
AU32
AU33
AU35
AV33
AW33
AW35
AY35
BA32
BA33
BA35
BB33
BC32
BC33
BC35
BD32
BD35
BE32
BE33
BE35
BF33
BF34
BG32
BG33
BG35
BH32
BH34
BH35
BJ32
BJ33
BJ34
BK32
BK33
BK34
BK35
BL33
AU30
W13
W14
AA20
AA23
AA26
AA28
AB21
AB24
AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28
AF21
AF26
AA31
AH20
AH21
AH23
AH24
AH26
AD31
AJ20
AN14
R30
R20
T14
Y12
U30G
VCC_1
VCC_2
VCC_3
VCC_5
VCC_4
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36
VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
VCC CORE
POWER
VCC SMVCC GFX
VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC GFX NCTF
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_61
VCC_AXG_NCTF_62
VCC_AXG_NCTF_63
VCC_AXG_NCTF_64
VCC_AXG_NCTF_65
VCC_AXG_NCTF_66
VCC_AXG_NCTF_67
VCC_AXG_NCTF_68
VCC_AXG_NCTF_69
VCC_AXG_NCTF_70
VCC_AXG_NCTF_71
VCC_AXG_NCTF_72
VCC_AXG_NCTF_73
VCC_AXG_NCTF_74
VCC_AXG_NCTF_75
VCC_AXG_NCTF_76
VCC_AXG_NCTF_77
VCC_AXG_NCTF_78
VCC_AXG_NCTF_79
VCC_AXG_NCTF_80
VCC_AXG_NCTF_81
VCC_AXG_NCTF_82
VCC_AXG_NCTF_83
VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7
VCC SM LF
T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31
AW45
BC39
BE39
BD17
BD4
AW8
AT6
VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7
4
Layout Note:
370 mils
from edge.
12
+
C429
330U/6.3V
Layout Note:
Inside GMCH
cavity for
VCC_AXG.
12
C216
0.1U/10V
12
C251
0.1U/10V
+
12
C204
330U/6.3V
12
C233
0.1U/10V
12
C258
0.1U/10V
Layout Note:
370 mils from edge.
+VCCGFX
12
C227
0.47U/10V
12
C269
0.22U/10V
+1.05V
12
C212
1U/10V
12
C270
0.22U/10V
+VCCGFX
12
C210
10U/6.3V
12
C276
0.47U/10V
12
+
C425
220U/2.5V
3
12
C223
22U/4V
Layout Note:
Inside GMCH cavity.
12
C228
22U/4V
+1.05VM
12
12
C267
1U/10V
+3V
R15710
+VCC_GMCH_L
1 2
12
*SHORT PAD
B2_DET(11)
BL1_DET(11)
BL51_DET(11)
A51 _DET(11)
Layout Note:
Place close to GMCH edge.
C259
1U/10V
12
C217
0.22U/10V
+VCCGFX
JP2
1 2
Layout Note:
Inside GMCH cavity.
12
C238
0.1U/10V
12
C442
22U/4V
C214
0.22U/10V
12
12
D10
CH751H-40HPT
12
C225
0.1U/10V
+1.05V
B2_DET
BL1_DET
BL51_DET
A51 _DET
12
C234
0.1U/10V
12
C249
0.22U/10V
1.8VSUS
Layout Note:
Place C2630 where
LVDS and DDR2 taps.
C243
0.1U/10V
C253
0.22U/10V
12
C461
0.1U/10V
2
21
U30F
AB33
VCC_NCTF_1
AB36
VCC_NCTF_2
AB37
VCC_NCTF_3
AC33
VCC_NCTF_4
AC35
VCC_NCTF_5
AC36
VCC_NCTF_6
AD35
VCC_NCTF_7
AD36
VCC_NCTF_8
AF33
VCC_NCTF_9
AF36
VCC_NCTF_10
AH33
VCC_NCTF_11
AH35
VCC_NCTF_12
AH36
VCC_NCTF_13
AH37
VCC_NCTF_14
AJ33
VCC_NCTF_15
AJ35
VCC_NCTF_16
AK33
VCC_NCTF_17
AK35
VCC_NCTF_18
AK36
VCC_NCTF_19
AK37
VCC_NCTF_20
AD33
VCC_NCTF_21
AJ36
VCC_NCTF_22
AM35
VCC_NCTF_23
AL33
VCC_NCTF_24
AL35
VCC_NCTF_25
AA33
VCC_NCTF_26
AA35
VCC_NCTF_27
AA36
VCC_NCTF_28
AP35
VCC_NCTF_29
AP36
VCC_NCTF_30
AR35
VCC_NCTF_31
AR36
VCC_NCTF_32
Y32
VCC_NCTF_33
Y33
VCC_NCTF_34
Y35
VCC_NCTF_35
Y36
VCC_NCTF_36
Y37 A3
VCC_NCTF_37VSS_SCB1
T30
VCC_NCTF_38
T34
VCC_NCTF_39
T35
VCC_NCTF_40
U29
VCC_NCTF_41
U31
VCC_NCTF_42
U32
VCC_NCTF_43
U33
VCC_NCTF_44
U35
VCC_NCTF_45
U36
VCC_NCTF_46
V32
VCC_NCTF_47
V33
VCC_NCTF_48
V36
VCC_NCTF_49
V37
VCC_NCTF_50
AL24
VCC_AXM_NCTF_1
AL26
VCC_AXM_NCTF_2
AL28
VCC_AXM_NCTF_3
AM26
VCC_AXM_NCTF_4
AM28
VCC_AXM_NCTF_5
AM29
VCC_AXM_NCTF_6
AM31
VCC_AXM_NCTF_7
AM32
VCC_AXM_NCTF_8
AM33
VCC_AXM_NCTF_9
AP29
VCC_AXM_NCTF_10
AP31
VCC_AXM_NCTF_11
AP32
VCC_AXM_NCTF_12
AP33
VCC_AXM_NCTF_13
AL29
VCC_AXM_NCTF_14
AL31
VCC_AXM_NCTF_15
AL32
VCC_AXM_NCTF_16
AR31
VCC_AXM_NCTF_17
AR32
VCC_AXM_NCTF_18
AR33
VCC_AXM_NCTF_19
CRESTLINE_1p0
12
+
C313
330U/6.3V
VCC NCTF
POWER
VCC AXM NCTF
12
C288
22U/4V
Layout Note:
Place on the edge.
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS NCTF
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_SCB2
VSS_SCB3
VSS_SCB4
VSS_SCB5
VSS_SCB6
VSS SCBVCC AXM
VCC_AXM_1
VCC_AXM_2
VCC_AXM_3
VCC_AXM_4
VCC_AXM_5
VCC_AXM_6
VCC_AXM_7
12
C287
22U/4V
1
T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28
B2_DET
B2
C1
BL1_DET
BL1
BL51_DET
BL51
A51 _DET
A51
+1.05VM
AT33
AT31
AK29
AK24
AK23
AJ26
AJ23
CRESTLINE_1p0
5
PROJECT : OT2
SizeDocument NumberRev
4
3
2
Date:Sheet of
Quanta Computer Inc.
Crestline_D(VCC,NCTF)
1
942Thursday, March 22, 2007
1ACustom
5
FB_180ohm+-25%_100mHz_1500mA_0.09ohm DC
+3V
DD
+1.25VM
L30
BLM11A121S
L31
BLM11A121S
R186
0.5/F/0603
1 2
+VCCA_MPLL_L
12
C255
22U/10V
CC
+1.25V
FB_220ohm+-25%_100MHz
_2A_0.1ohm DC
BB
22nF & 0.1uF for
VCC_TVDACA:C_R should
be placed with in 250
mils from Crestline.
+VCC_TVBG_R
AA
+1.5V
TV DAC Voltage Follower Circuit -700 mV.
L17
1 2
BLM18PG181SN1
45mA MAx.
FB_120ohm+-25%_100mHz
_200mA_0.2ohm DC
+VCCA_HPLL
12
12
12
+VCCA_MPLL
12
BLM21PG221SN1D
D9
2 1
*CH751H-40HPT
C245
C250
0.1U/10V
22U/10V
12
C244
0.1U/10V
L29
1 2
FB_180ohm+-25%_100mHz_1500mA_0.09ohm DC
L16
+3V
1 2
BLM18PG181SN1
R1210
1 2
+VCC_TVDAC_L
5
+VCCA_CRTDAC
+1.25VM
+VCCA_PEG_PLL
12
R177
1/F/0603
12
C219
10U/6.3V
+VCC_TVBG
12
C154
C149
0.1U/10V
*22nF
R128*10
1 2
12
C185
0.1U/10V
+1.25V
0.1Caps should be
placed 200 mils
with in its pins.
+1.25VM
R1180/F
+3V
L26
10uH/100MA
R1890
12
C220
0.1U/10V
12
C181
10U/4V
12
40mA MAx.
10uH+-20%_100mA
12
L28
12
10uH/100MA
12
C454
+
100U/6.3V
12
C271
22U/4V
+1.25VM
12
C242
0.1U/10V
+VCC_TVDACA
12
C160
0.1U/10V
+VCC_TVDACB
12
C162
0.1U/10V
+VCC_TVDACC
12
C165
0.1U/10V
R1350
+VCCA_DPLLA
12
C201
+
470U/4V
+VCCA_DPLLB
12
C273
+
470U/4V
12
4
+VCCA_CRTDAC_R
C190
*22nF
1 2
12
C197
0.1U/10V
12
C207
0.1U/10V
C241
4.7U/6.3V
1 2
12
C260
1U/10V
1.8VSUS
C215
0.1U/10V
R1230
R1290
R1310
4
+3V
12
C176
0.1U/10V
+3V
12
12
C261
22U/4V
12
C272
1U/10V
R1380
+VCC_TVDACA_R
C166
*22nF
1 2
+VCC_TVDACB_R
C175
*22nF
1 2
+VCC_TVDACC_R
C183
*22nF
1 2
C191
1000P/50V
C202
0.1U/10V
12
C264
22U/4V
12
C278
0.1U/10V
+VCCA_CRTDAC_R
+VCC_TVBG_R
+VCCA_DPLLA
+VCCA_DPLLB
+VCCA_HPLL
+VCCA_MPLL
+VCC_TX_LVDS
12
+VCCA_PEG_PLL
12
C240
1U/10V
+VCCA_SM_CK
+VCC_TVDACA_R
+VCC_TVDACB_R
+VCC_TVDACC_R
+VCCD_TVDAC_R
+VCCQ_TVDAC_R
+VCCA_PEG_PLL
12
C205
1U/10V
+1.5V
L18
1 2
BLM18PG181SN1
FB_180ohm+-25%_
100mHz_1500mA_
0.09ohm DC
U30H
J32
A33
B33
A30
B32
B49
H49
AL2
AM2
A41
B41
K50
K49
U51
AW18
AV19
AU19
AU18
AU17
AT22
AT21
AT19
AT18
AT17
AR17
AR16
BC29
BB29
C25
B25
C27
B27
B28
A28
M32
L29
N28
AN2
U48
J41
H42
12
C187
10U/6.3V
+VCCQ_TVDAC
3
VCCSYNC
VCCA_CRT_DAC_1
VCCA_CRT_DAC_2
VCCA_DAC_BG
VSSA_DAC_BG
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL
VCCA_LVDS
VSSA_LVDS
VCCA_PEG_BG
VSSA_PEG_BG
VCCA_PEG_PLL
VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
VCCA_SM_7
VCCA_SM_8
VCCA_SM_9
VCCA_SM_10
VCCA_SM_11
VCCA_SM_NCTF_1
VCCA_SM_NCTF_2
VCCA_SM_CK_1
VCCA_SM_CK_2
VCCA_TVA_DAC_1
VCCA_TVA_DAC_2
VCCA_TVB_DAC_1
VCCA_TVB_DAC_2
VCCA_TVC_DAC_1
VCCA_TVC_DAC_2
VCCD_CRT
VCCD_TVDAC
VCCD_QDAC
VCCD_HPLL
VCCD_PEG_PLL
VCCD_LVDS_1
VCCD_LVDS_2
+VTTLF1
+VTTLF2
+VTTLF3
12
C164
0.1U/10V
12
C182
0.1U/10V
3
CRTPLLA PEGA SMTV
POWER
A CK A LVDS
D TV/CRTLVDS
C232
0.47U/10V
R1300
C659
.1U
1 2
12
C200
0.47U/10V
C177
*22nF
12
R133100
SI stage:change R133 to 100ohm and
C658,C659,C184 install
VTT
VCC_AXD_1
VCC_AXD_2
VCC_AXD_3
VCC_AXD_4
VCC_AXD_5
VCC_AXD_6
AXD
VCC_AXD_NCTF
VCC_AXF_1
VCC_AXF_2
VCC_AXF_3
AXF
VCC_DMI
VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4
SM CK
VCC_TX_LVDS
VCC_HV_1
VCC_HV_2
HV
VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5
PEG
VCC_RXR_DMI_1
VCC_RXR_DMI_2
DMI
VTTLF
CRESTLINE_1p0
12
+VCCD_TVDAC_R
+VCCQ_TVDAC_R
C658
1U
C184
22nF
1 2
VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTTLF1
VTTLF2
VTTLF3
C196
0.47U/10V
U13
U12
U11
U9
U8
U7
U5
U3
U2
U1
T13
T11
T10
T9
T7
T6
T5
T3
T2
R3
R2
R1
AT23
AU28
AU24
AT29
AT25
AT30
AR29
B23
B21
A21
AJ50
BK24
BK23
BJ24
BJ23
A43
C40
B40
AD51
W50
W51
V49
V50
AH50
AH51
A7
F2
AH1
+VCC_AXF
+VCC_SM_CK
+VCC_TX_LVDS
+VCC_RXR_DMI
+VTTLF1
+VTTLF2
+VTTLF3
2
12
C221
2.2U/6.3V
12
C188
4.7U/10V
Place on the edge.
12
C226
0.47U/6.3V
12
C231
4.7U/10V
Place on the edge.
+VCC_AXD_L
12
C257
1U/10V
+3V
12
C199
0.1U/10V
2
1 2
12
C457
22U/10V
Place caps close
to VCC_AXD.
12
C195
1000P/50V
+VCC_PEG
12
+
C282
220U/4V
12
+
C447
220U/4V
+VCC_SM_CK
12
C456
22U/10V
1
+1.05V
21
+VCC_HV_L
12
R127
*10
+3V
+1.25V
R140
+VCC_AXF
C193
1U/10V
1.8VSUS
12
C194
10U/6.3V
1.8VSUS
12
Place caps close
to VCC_AXF
0
+1.05V
12
+
C198
220U/4V
L320
Reserved L2612 pad
for inductor.
+1.25V
12
C224
0.1U/10V
1uH+-20%_300mA
L25
12
1uH/300MA
12
+
C192
220U/4V
L38
12
91nH/1.5A
91uH+-20%_1.5A
12
C222
10U/6.3V
L34
12
91nH/1.5A
91uH+-20%_1.5A
12
C229
10U/6.3V
L39
1uH/300mA
12
1uH+-20%_300mA
C281
0.1U/10V
R196
1/F/0603
+VCC_SM_CK_L
12
C285
10U/6.3V
12
+1.05V
+1.25VM
12
VCC_HV
D8
*CH751H-40HPT
+1.05V
PROJECT : OT2
SizeDocument NumberRev
Date:Sheet of
Quanta Computer Inc.
Crestline_E(POWER)
1
1042Thursday, March 22, 2007
1ACustom
5
4
3
2
1
SI stage: add test pin
U30I
A13
VSS_1
A15
VSS_2
A17
VSS_3
A24
VSS_4
AA21
VSS_5
AA24
VSS_6
AA29
VSS_7
DD
CC
BB
AA
AB20
AB23
AB26
AB28
AB31
AC10
AC13
AC3
AC39
AC43
AC47
AD1
AD21
AD26
AD29
AD3
AD41
AD45
AD49
AD5
AD50
AD8
AE10
AE14
AE6
AF20
AF23
AF24
AF31
AG2
AG38
AG43
AG47
AG50
AH3
AH40
AH41
AH7
AH9
AJ11
AJ13
AJ21
AJ24
AJ29
AJ32
AJ43
AJ45
AJ49
AK20
AK21
AK26
AK28
AK31
AK51
AM11
AM13
AM3
AM4
AM41
AM45
AN1
AN38
AN39
AN43
AN5
AN7
AP4
AP48
AP50
AR11
AR2
AR39
AR44
AR47
AR7
AT10
AT14
AT41
AT49
AU1
AU23
AU29
AU3
AU36
AU49
AU51
AV39
AV48
AW1
AW12
AW16
AL1
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
CRESTLINE_1p0
VSS
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41
U30J
C46
VSS_199
C50
VSS_200
C7
VSS_201
D13
VSS_202
D24
VSS_203
D3
VSS_204
D32
VSS_205
D39
VSS_206
D45
VSS_207
D49
VSS_208
E10
VSS_209
E16
VSS_210
E24
VSS_211
E28
VSS_212
E32
VSS_213
E47
VSS_214
F19
VSS_215
F36
VSS_216
F4
VSS_217
F40
VSS_218
F50
VSS_219
G1
VSS_220
G13
VSS_221
G16
VSS_222
G19
VSS_223
G24
VSS_224
G28
VSS_225
G29
VSS_226
G33
VSS_227
G42
VSS_228
G45
VSS_229
G48
VSS_230
G8
VSS_231
H24
VSS_232
H28
VSS_233
H4
VSS_234
H45
VSS_235
J11
VSS_236
J16
VSS_237
J2
VSS_238
J24
VSS_239
J28
VSS_240
J33
VSS_241
J35
VSS_242
J39
VSS_243
K12
VSS_245
K47
VSS_246
K8
VSS_247
L1
VSS_248
L17
VSS_249
L20
VSS_250
L24
VSS_251
L28
VSS_252
L3
VSS_253
L33
VSS_254
L49
VSS_255
M28
VSS_256
M42
VSS_257
M46
VSS_258
M49
VSS_259
M5
VSS_260
M50
VSS_261
M9
VSS_262
N11
VSS_263
N14
VSS_264
N17
VSS_265
N29
VSS_266
N32
VSS_267
N36
VSS_268
N39
VSS_269
N44
VSS_270
N49
VSS_271
N7
VSS_272
P19
VSS_273
P2
VSS_274
P23
VSS_275
P3
VSS_276
P50
VSS_277
R49
VSS_278
T39
VSS_279
T43
VSS_280
T47
VSS_281
U41
VSS_282
U45
VSS_283
U50
VSS_284
V2
VSS_285
V3
VSS_286
CRESTLINE_1p0
VSS
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
W11
W39
W43
W47
W5
W7
Y13
Y2
Y41
Y45
Y49
Y5
Y50
Y11
P29
T29
T31
T33
R28
AA32
AB32
AD32
AF28
AF29
AT27
AV25
H50
BL1_DET(9)
B2_DET(9)
A51 _DET(9)
BL51_DET(9)
+3V
R202
100K
R203
100K
BL1_DETBL1_DETBL1_DETBL1_DET
R206
T162
*0
+3V
R204
100K
R207
100K
B2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DET
R205
T163
*0
+3V
R200
100K
R193
100K
A51 _DET
R194
T164
*0
+3V
R201
R216
100K
BL51_DET
R217
T165
*0
3
2
Q142N7002E
1
3
2
Q132N7002E
1
BGA_MON_DET(14,26)
3
2
Q122N7002E
1
100K
3
2
Q152N7002E
1
PROJECT : OT2
SizeDocument NumberRev
5
4
3
2
Date:Sheet of
Quanta Computer Inc.
Crestline(VSS)
1
1142Thursday, March 22, 2007
1ACustom
1
AA
3VPCU
VCCRTC_2
R415
1K
CN32
1
2
BAT_CONN
BB
ACZ_BITCLK_ADI(22)
ACZ_SYNC_ADI(22)
ACZ_RST_ADI#(22,23)
ACZ_SDIN0(22)
ACZ_SDIN1(30)
ACZ_SDOUT_ADI(22)
ACZ_BITCLK_MDC(30)
ACZ_SYNC_MDC(30)
ACZ_RST_MDC#(30)
CC
ACZ_SDOUT_MDC(30)
VCCRTC
D19
CH500H-40
D18
CH500H-40
C514
*10P
C521
*10P
VCCRTC
R414
20K
R420
1M/F
C526
*10P
C517
*10P
C340
*10P
2
C341
*10P
C4821U
C337
*10P
C485
1U
C339
*22P
12
G1
SHORT_ PAD1
INTRUDER#
R24233
R24433
R47633
R47133
R24033
R24333
R47033
R46433
C335
18P
Y5
32.768KHZ
C336
18P
3
+1.5V_PCIE_ICH
ACZ_SDIN0
ACZ_SDIN1
ACZ_SDOUTACZ_SDOUT
G_BATLED#(29)
CLK_32KX1
R238
10M
2 1
CLK_32KX2
GLAN_CLK(24)
LAN_RSTSYNC(24)
LAN_RXD0(24)
LAN_RXD1(24)
LAN_RXD2(24)
LAN_TXD0(24)
LAN_TXD1(24)
LAN_TXD2(24)
ENERGY_DET(25)
*SHORT PAD
ACZ_BCLK
ACZ_SYNC
ACZ_RST#
JP5
R40124.9/F
1 2
T68
T131
12
R518*24.9/F
4
ICH_INTVRMEN
ICH_LAN100_SLP
GLAN_COMP
T129
T132
T158
T159
T160
T161
T73
T75
T144
T78
T171
T172
SATABIAS
12
+3V
5
VCCRTC VCCRTC
12
R407
332K/F
ICH_INTVRMEN
12
R413
*0
U17A
AG25
RTCX1
AF24
RTCX2
AF23
RTCRST#
AD22
INTRUDER#
AF25
INTVRMEN
AD21
LAN100_SLP
B24
GLAN_CLK
D22
LAN_RSTSYNC
C21
LAN_RXD0
B21
LAN_RXD1
C22
LAN_RXD2
D21
LAN_TXD0
E20
LAN_TXD1
C20
LAN_TXD2
AH21
GLAN_DOCK#/GPIO13
D25
GLAN_COMPI
C25
GLAN_COMPO
AJ16
HDA_BIT_CLK
AJ15
HDA_SYNC
AE14
HDA_RST#
AJ17
HDA_SDIN0
AH17
HDA_SDIN1
AH15
HDA_SDIN2
AD13
HDA_SDIN3
AE13
HDA_SDOUT
AE10
HDA_DOCK_EN#/GPIO33
AG14
HDA_DOCK_RST#/GPIO34
AF10
SATALED#
AF6
SATA0RXN
AF5
SATA0RXP
AH5
SATA0TXN
AH6
SATA0TXP
AG3
SATA1RXN
AG4
SATA1RXP
AJ4
SATA1TXN
AJ3
SATA1TXP
AF2
SATA2RXN
AF1
SATA2RXP
AE4
SATA2TXN
AE3
SATA2TXP
AB7
SATA_CLKN
AC6
SATA_CLKP
AG1
SATARBIAS#
AG2
SATARBIAS
ICH8M REV 1.0
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
FWH4/LFRAME#
RTCLAN / GLANIHDASATA
LPC
LDRQ1#/GPIO23
CPUPWRGD/GPIO49
CPU
THRMTRIP#
IDE
LDRQ0#
A20GATE
A20M#
DPRSTP#
DPSLP#
FERR#
IGNNE#
INIT#
INTR
RCIN#
SMI#
STPCLK#
DD10
DD11
DD12
DD13
DD14
DD15
DCS1#
DCS3#
DIOR#
DIOW#
DDACK#
IDEIRQ
IORDY
DDREQ
NMI
TP8
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DA0
DA1
DA2
E5
F5
G8
F6
C4
G9
E6
AF13
AG26
AF26
AE26
AD24
AG29
AF27
AE24
AC20
AH14
AD23
AG28
AA24
AE27
AA23
V1
U2
V3
T1
V4
T5
AB2
T6
T3
R2
T4
V6
V5
U1
V2
U6
AA4
AA1
AB3
Y6
Y5
W4
W3
Y2
Y3
Y1
W5
LAD0/FWH0
LAD1/FWH1
LAD2/FWH2
LAD3/FWH3
LFRAME#/FWH4
H_FERR#
KBCCPURST#
THERMTRIP#_ICH
PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15
PDA0
PDA1
PDA2
PDCS1#
PDCS3#
6
12
R421
332K/F
ICH_LAN100_SLP
12
R424
*0
T136PAD
T141PAD
GATEA20
R3930/F
R3960/F
R1260/F
T121PAD
LFRAME#/FWH4(26,30)
GATEA20(26)
H_A20M#(4)
H_DPRSTP#
H_DPSLP#
H_FERR#(4)
H_PWRGOOD(4)
H_IGNNE#(4)
H_INIT#(4)
H_INTR(4)
H_NMI(4)
H_SMI#(4)
H_STPCLK#(4)
R38424.9/F
PDIOR#(28)
PDIOW#(28)
PDDACK#(28)
IRQ14(28)
PDIORDY(28)
PDDREQ(28)
7
LAD0/FWH0(26,30)
LAD1/FWH1(26,30)
LAD2/FWH2(26,30)
LAD3/FWH3(26,30)
H_DPRSTP#(4,7)
H_DPSLP#(4)
KBCCPURST#(26)
PDD[15:0](28)
PDA[2:0](28)
PDCS1#(28)
PDCS3#(28)
H_DPRSTP#
H_DPSLP#
H_FERR#
GATEA20
KBCCPURST#
R383
1 2
56
+3V
R958
8.2K
R959
4.7K
1 2
R390
*56
+1.05V
8
+1.05V
R395
*56
R417
56
1 2
1 2
+3V
R468
R466
10K
10K
1 2
1 2
PM_THRMTRIP#(4,7)
DD
1
2
3
R462
*1K
1 2
ACZ_SDOUT
R239
*1K
1 2
4
ICH_RSVD(14)
PROJECT : OT2
SizeDocument NumberRev
5
6
Date:Sheet of
Quanta Computer Inc.
ICH8(CPU,SATA,IDE)
7
PDIORDY
IRQ14
1242Thursday, March 22, 2007
8
1ACustom
1
MINI CARD PCI-E
AA
SPI_CLK(31)
SPI_CS0#(31)
SPI_CS1#(14,26)
SI2 stage:Change power source to avoid leakage
current
BB
USBOC#3
USBOC#4
3V_S5
CC
DD
USBOC#0
USBOC#6
SI stage:Change power source to avoid leakage current
USBOC#9
AD[31..0](20)
RP31
6
7
8
9
10
8.2KX8
3V_S5
R241
8.2K
INTC#(20)
INTD#(20)
1
5
4
3
2
1
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
2
PCIE_RXN2(19)
PCIE_RXP2(19)
PCIE_TXN2(19)
PCIE_TXP2(19)
3
C4660.1U
C4650.1U
Intel LAN
PCIE_RXN6(24)
PCIE_RXP6(24)
PCIE_TXN6(24)
PCIE_TXP6(24) USBP1-(30)
PV stage:change R399 to 15 ohm for intel request
SPI_SI(31)
SPI_SO(31)
BT_OFF(30)
3V_S5
USBOC#7
USBOC#2
USBOC#1
USBOC#8
WWAN_OFF#(19)
USBOC#0
USBOC#2
USBOC#4
USBOC#6
USBOC#7
USBOC#8
USBOC#9
SI stage:add to avoid WWAN Noise
U17B
D20
AD0
E19
D19
A20
D17
A21
A19
C19
A18
B16
A12
E16
A14
G16
A15
B6
C11
A9
D11
B12
C12
D10
C7
F13
E11
E13
E12
D8
A6
E8
D6
A3
INTA#
F9
INTB#
B5
INTC#
C5
INTD#
A10 B3
2
PCI
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
Interrupt I/F
PIRQA#
PIRQB#
PIRQC#
PIRQD#PIRQH#/GPIO5
ICH8M REV 1.0
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
C4680.1U
C4670.1U
R39815
R40315
R41015
R39915
R4090/F
R4560/F
R4550/F
C6440.1U/10V
C6460.1U/10V
C6470.1U/10V
C6490.1U/10V
C6500.1U/10V
C6510.1U/10V
C6520.1U/10V
A4
REQ0#
D7
GNT0#
E18
C18
B19
F18
A11
C10
C17
C/BE0#
E15
C/BE1#
F16
C/BE2#
E17
C/BE3#
C8
IRDY#
D9
PAR
G6
PCIRST#
D16
DEVSEL#
A7
PERR#
B7
PLOCK#
F10
SERR#
C16
STOP#
C9
TRDY#
A17
FRAME#
AG24
PLTRST#
B10
PCICLK
G7
PME#
F8
G11
F12
1 2
1 2
1 2
1 2
1 2
1 2
1 2
REQ0#
GNT0#GNT0#
REQ1#
GNT1#
REQ2#
GNT2#
REQ3#
GNT3#
CLK_PCI_ICH
3
C/BE0#
C/BE1#
C/BE2#
C/BE3#
IRDY#
PAR
PCI_RST#_G
DEVSEL#
PERR#
LOCK#
SERR_1#
STOP#
TRDY#
FRAME#
PCI_PME#
INTE#
INTF#
INTG#
SES_INT
PCIE_RXN2
PCIE_RXP2
PCIE_TXN2_C
PCIE_TXP2_C
PCIE_RXN6
PCIE_RXP6
PCIE_TXN6_C
PCIE_TXP6_C
SPI_CS1_R#
USBOC#0
USBOC#1
USBOC#2
USBOC#3
USBOC#4
USBOC#5
USBOC#6
USBOC#8
USBOC#9
PLT_RST-R#
T74PAD
T140PAD
T127PAD
T123PAD
T70PAD
T134PAD
C/BE0#(20)
C/BE1#(20)
C/BE2#(20)
C/BE3#(20)
IRDY#(20)
PAR(20)
DEVSEL#(20)
PERR#(20)
SERR_1#(20)
STOP#(20)
TRDY#(20)
FRAME#(20)
INTE#(20)
U17D
P27
P26
N29
N28
M27
M26
L29
L28
K27
K26
J29
J28
H27
H26
G29
G28
F27
F26
E29
E28
D27
D26
C29
C28
C23
B23
E22
D23
F21
AJ19
AG16
AG15
AE15
AF15
AG17
AD12
AJ18
AD14
AH18
ICH8M REV 1.0
REQ2#(20)
GNT2#(20)
CLK_PCI_ICH(17)
PCI_PME#(20)
SES_INT(27)
4
PERN1
PERP1
PETN1
PETP1
PERN2
PERP2
PETN2
PETP2
PERN3
PERP3
PETN3
PETP3
PERN4
PERP4
PETN4
PETP4
PERN5
PERP5
PETN5
PETP5
PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP
SPI_CLK
SPI_CS0#
SPI_CS1#
SPI_MOSI
SPI_MISO
OC0#
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31
OC8#
OC9#
Short F2 and F3 at the package
and keep length to less than
500mils. Trace Impedance
should be 60ohms +/- 15%.
SPI_CS1_R#
GNT0#
PCI-Express
SPI
USB
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
DMI_CLKN
DMI_CLKP
Direct Media Interface
DMI_ZCOMP
DMI_IRCOMP
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBRBIAS#
USBRBIAS
R501
1K
1 2
1 2
PCI DEVICES IRQ ROUTING
DEVICEREQ/GNT #
PLT_RST-R#(7)
4
R411
*1K
5
V27
V26
U29
U28
Y27
Y26
W29
W28
AB26
AB25
AA29
AA28
AD27
AD26
AC29
AC28
T26
T25
Y23
Y24
G3
G2
H5
H4
H2
H1
J3
J2
K5
K4
K2
K1
L3
L2
M5
M4
M2
M1
N3
N2
F2
F3
DMI_COMP
USBP0USBP0+
USBP1+
USBP2USBP2+
USBP3USBP3+
USBP5USBP5+
USBP6USBP6+
USBP7USBP7+
USBP8USBP8+
USBP9-USBOC#7
USBP9+
USBRBIAS
T155PAD
T156PAD
1 2
DMI_MTX_IRX_N0(7)
DMI_MTX_IRX_P0(7)
DMI_MRX_ITX_N0(7)
DMI_MRX_ITX_P0(7)
DMI_MTX_IRX_N1(7)
DMI_MTX_IRX_P1(7)
DMI_MRX_ITX_N1(7)
DMI_MRX_ITX_P1(7)
DMI_MTX_IRX_N2(7)
DMI_MTX_IRX_P2(7)
DMI_MRX_ITX_N2(7)
DMI_MRX_ITX_P2(7)
DMI_MTX_IRX_N3(7)
DMI_MTX_IRX_P3(7)
DMI_MRX_ITX_N3(7)
DMI_MRX_ITX_P3(7)
CLK_PCIE_ICH#(17)
CLK_PCIE_ICH(17)
R41224.9/F
12
USBP1+(30)
T77PAD
T76PAD
T149PAD
T145PAD
USBP7-(32)
USBP7+(32)
USBP8-(19)
USBP8+(19)
T146PAD
T79PAD
R512
22.6/F
Boot BIOS Strap
GNT0#SPI_CS1#
No stuff
No stuff
Stuff
No stuff
Stuff
No stuff
11LPC
PCI
SPI1001
IDSEL #
AD22CardBus2
CLK_PCI_ICH
Reserved for EMI.
Place resister and cap
close to ICH.
5
6
+1.5V_PCIE_ICH
USBP0-(30)
USBP0+(30)
FINGER PRINT
DB1A stage:change for HP
request
USBP5-(30)
USBP5+(30)
USBP6-(30)
USBP6+(30)
Docking
Place within 500mils of ICH8
SYSTEM(RIGHT)
SYSTEM(LEFT)
Bluetooth Module
WWAN
PCI_INT
C,D,E
R479
*10
1 2
C525
*8.2P/16V
1 2
6
7
D33
SERR_1#SERR#
2 1
CH751H-40HPT
SERR#(26)
SI stage:add to avoid leakage currurt
+3V
PCI_RST#_G
PLT_RST-R#
3V_S5
+3V
+3V
C539
1 2
0.047U/10V
C490
1 2
0.047U/10V
R4488.2K
SI stage:Change power source to avoid leakage current
USBOC#5(30)
STOP#
INTF#
INTG#
REQ3#
INTD#
IRDY#
INTA#
INTE#
LOCK#
+3V
5
U36
2
1
7SH32
R489*0
+3V
5
U32
2
1
7SH32
USBOC#5
+3V
RP30
6
7
8
9
10
8.2KX8
RP32
6
7
8
9
10
8.2KX8
RP33
6
7
8
9
10
8.2KX8
Add Buffers as needed for
Loading and fanout concerns.
5
REQ2#
4
REQ1#
3
FRAME#
2
DEVSEL#
1
+3V
5
4
3
TRDY#
2
SERR_1#
1
+3V
5
REQ0#
4
INTB#
3
INTC#
2
PERR#
1
4
R990
100K
DB1A stage:add
4
R991
100K
PLTRST#(19,26,28,30)
PROJECT : OT2
SizeDocument NumberRev
Date:Sheet of
Quanta Computer Inc.
ICH8(USB,PCIE,DMI)
7
1342Thursday, March 22, 2007
8
PCIRST#(20)
1ACustom
8
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