HP 15-CS 1016ur Schematics
5
4
3
2
1
01
G7BD 1SPD
D D
DDR4 2400MHz SODIMM1
8GB Max.
DDR4 2400MHz SODIMM2
8GB Max. DDR CHB
SATA HDD
2.5" 7.2/9.5mm
Power :
C C
M.2 2280-S3 SSD
B B
G-Sensor
HP2DCTR PAGE32
Keyboard
PAGE 31
Touch Pad
PAGE 31
FAN
PAGE 31
A A
Intel WLH-U Platform Block Diagram
DDR4 2400MHz
DDR4 2400MHz
6GB/s
6GB/s
PCI-E
X4 Lane
PAGE 32TPM
SLB9665TT2.0 FW 5.6
SLB9670TT2.0 FW 5.6
PAGE 35
DDR CHA
WHL U4+2
Processor
Processor : Daul Core
SATA
PCIE
PCIE/SATA
GSPI
SPI
LPC
Power : 15 (Watt)
Package : BGA1356
Size : 40 X 24 (mm)
HDA
Audio Codec
ALC3258-CG
Power :
Package : MQFN
Size : 6 x 6 (mm)
PAGE 2~16
Azalia
PAGE 26
PAGE 33
PAGE 34
System BIOS
SPI ROM
PAGE 17
PAGE 18
PAGE 10
Embedded Controller
iTE 8987
Power :
Package : LQPF128
Size : 14 x 14 (mm)
DIS/UMA 15"
N16S-GTR/N17S
25W, 23x23mm
LCD Connector
HDMI V1.4
PAGE 29
LAN Controller
RTL8111HSH(Giga)
Power :
Package : OFN32
USB3.0
USB2.0
D/B CONN
PAGE 29
Port 3
Camera
PAGE 25
PAGE 28
RJ45 Conn
PAGE 28
PAGE 19~22
PCIE
eDP
DDI
USB3.0
USB2.0
PCIE
PCIE Gen 1 x 1 Lane
PCI-E
X4 Lane
eDP x2
Port 1 Port 2 Port 3
USB3.0
USB2.0
DB CONN
Port 1 Port 2 Port 4
Port 5
IR Camera
PAGE 25
PAGE 25
PAGE 27
VRAM GDDR5
16bit x 4pcs
PAGE 23~24
www.laptoprepairsecrets.com
Type C
USB2.0
PAGE 30
Port 8
Touch Screen
PAGE 25
M.2 Card
WLAN / BT Combo
USB2.0
PAGE 34
Speaker
Port 7
PAGE 26
Port 6
Card Reader
AK6485RB63-GLF-GR
DB
PCB 6L STACK UP
LAYER 1 : TOP
LAYER 2 : SGND
LAYER 3 : IN1
LAYER 4 : IN2
LAYER 5 : SVCC
LAYER 6 : IN3
LAYER 7 : SGND
LAYER 8 : BOT
PAGE 29
Combo Jack
Digital MIC
5
4
3
PAGE 27
PAGE 26
2
PROJECT : G7BD
PROJECT : G7BD
PROJECT : G7BD
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Block Diagram
Block Diagram
Block Diagram
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
1 49Wednesday, December 26, 2018
1 49Wednesday, December 26, 2018
1 49Wednesday, December 26, 2018
1A
1A
1A
5
+3V <4,10,11,12,13,14,15,17,18,22,25,26,27,28,29,31,32,33,34,35,42,45,46,47>
+1.05V <6,35,41>
+VCCSTPLL <4,5,6,41,42>
HDMI
D D
DISP_RCOMP signals should be shorted near balls
and routed with typical impedance <20 mohms
C C
+VCCSTPLL
R30250 *49.9/F_4
+1.05V
B B
CATERR#
R30218 *1K_5%_4
R30266 51_5%_4
R30220 51_5%_4
R30268 100_1%_4
R30269 *51_5%_4
Close to Chipset
H_PROCHOT#<35,42>
JTAGX_PCH
JTAG_TMS_PCH
JTAG_TDI_PCH
JTAG_TDO_PCH
JTAG_TCK_PCH
IN_D2#<27>
IN_D2<27>
IN_D1#<27>
IN_D1<27>
IN_D0#<27>
IN_D0<27>
IN_CLK#<27>
IN_CLK<27>
+VCCIO
SDVO_CLK<27>
SDVO_DATA<27>
4
IN_D2#
IN_D2
IN_D1#
IN_D1
IN_D0#
IN_D0
IN_CLK#
IN_CLK
R30233 24.9_1%_4
R30247 499_1%_4
EDP_RCOMP
EC_PECI<35>
PM_THRMTRIP#<35>
XDP_BPM0<16>
XDP_BPM1<16>
R30083 49.9_1%_4
R30241 49.9_1%_4
R30265 49.9_1%_4
U30015A
AL5
DDI1_TXN_0
AL6
DDI1_TXP_0
AJ5
DDI1_TXN_1
AJ6
DDI1_TXP_1
AF6
DDI1_TXN_2
AF5
DDI1_TXP_2
AE5
DDI1_TXN_3
AE6
DDI1_TXP_3
AC4
DDI2_TXN_0
AC3
DDI2_TXP_0
AC1
DDI2_TXN_1
AC2
DDI2_TXP_1
AE4
DDI2_TXN_2
AE3
DDI2_TXP_2
AE1
DDI2_TXN_3
AE2
DDI2_TXP_3
GPP_E13/DDPB_HPD0/DISP_MISC0
GPP_E14/DDPC_HPD1/DISP_MISC1
GPP_E15/DPPD_HPD2/DISP_MISC2
GPP_E16/DPPE_HPD3/DISP_MISC3
GPP_E17/EDP_HPD/DISP_MISC4
AM6
DISP_RCOMP
CC8
GPP_E18/DPPB_CTRLCLK/CNV_BT_HOST_W AKE#
CC9
GPP_E19/DPPB_CTRLDATA
CH4
GPP_E20/DPPC_CTRLCLK
CH3
GPP_E21/DPPC_CTRLDATA
CP4
GPP_E22/DPPD_CTRLCLK
CN4
GPP_E23/DPPD_CTRLDATA
CR26
GPP_H16/DDPF_CTRLCLK
CP26
GPP_H17/DDPF_CTRLDATA
*CFL_U_43E_IL_IP_DDR4
CATERR#
EC_PECI
PROCHOT#
PM_THRMTRIP#
PROC_POPIRCOMP
PCH_OPI_RCOMP
EDRAM_OPIO_RCOMP
EOPIO_RCOMP
AR1
CE9
CN3
CB34
CC35
BP27
BW25
AA4
BJ1
1 of 20
Y4
U1
U2
U3
U4
N5
L5
CATERR#
PECI
PROCHOT#
THRMTRIP#
BPM#_0
BPM#_1
BPM#_2
BPM#_3
GPP_E3/CPU_GP0
GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3
PROC_POPIRCOMP
PCH_OPIRCOMP
OPCE_RCOMP
OPC_RCOMP
3
EDP_TXN_0
EDP_TXP_0
EDP_TXN_1
EDP_TXP_1
EDP_TXN_2
EDP_TXP_2
EDP_TXN_3
EDP_TXP_3
EDP_AUX
EDP_AUX_P
DISP_UTILS
DDI1_AUX
DDI1_AUX_P
DDI2_AUX
DDI2_AUX_P
DDI3_AUX
DDI3_AUX_P
EDP_BKLTEN
EDP_VDDEN
EDP_BKLTCTL
U30015D
PROC_TCK
PROC_TDI
PROC_TDO
PROC_TMS
PROC_TRST#
PCH_TRST#
PCH_JTAGX
PROC_PREQ#
PROC_PRDY#
4 of 20
*CFL_U_43E_IL_IP_DDR4
AG4
AG3
AG2
AG1
AJ4
AJ3
AJ2
AJ1
AH4
AH3
AM7
AC7
AC6
AD4
AD3
AG7
AG6
CN6
CM6
CP7
CP6
CM7
CK11
CG11
CH11
PCH_TCK
PCH_TDI
PCH_TDO
PCH_TMS
INT_EDP_TXN0
INT_EDP_TXP0
INT_EDP_TXN1
INT_EDP_TXP1
INT_EDP_AUXN
INT_EDP_AUXP
HDMI_HPD_CON
ULT_EDP_HPD
PCH_LVDS_BLON
PCH_DISP_ON
PCH_DPST_PWM
XDP_TCK0
T6
XDP_TDI_CPU
U6
XDP_TDO_CPU
Y5
XDP_TMS_CPU
T5
PROC_TRST#
AB6
JTAG_TCK_PCH
W6
JTAG_TDI_PCH
U5
JTAG_TDO_PCH
W5
JTAG_TMS_PCH
P5
XDP_TRST#_CPU
Y6
JTAGX_PCH
P6
W2
W1
2
INT_EDP_TXN0 <25>
INT_EDP_TXP0 <25>
INT_EDP_TXN1 <25>
INT_EDP_TXP1 <25>
INT_EDP_AUXN <25>
INT_EDP_AUXP <25>
HDMI_HPD_CON <27>
ULT_EDP_HPD <25>
PCH_LVDS_BLON <25>
PCH_DISP_ON <25>
PCH_DPST_PWM <25>
JTAG_TDI_PCH
JTAG_TDO_PCH
JTAG_TMS_PCH
XDP_TRST#_CPU
R30244 *0_4/S
R30245 *0_4/S
R30243 *0_4/S
R30232 *0_4/S
JTAGX_PCH XDP_TCK0
R124543 *0_4/S
DCI Debug
XDP_TCK0 <16>
XDP_TDI_CPU <16>
XDP_TDO_CPU <16>
XDP_TMS_CPU <16>
PROC_TRST# <16>
JTAG_TCK_PCH <16>
JTAG_TDI_PCH <16>
JTAG_TDO_PCH <16>
JTAG_TMS_PCH <16>
XDP_PRDY#_CPU <16>
XDP_PREQ#_CPU <16>
PCH_DPST_PWM
PCH_LVDS_BLON
XDP_TDI_CPU
XDP_TDO_CPU
XDP_TMS_CPU
PROC_TRST#
1
Reserve EDP_HPD opposites circuit!
ULT_EDP_HPD
R30274
100K_5%_4
C91187
0.033u/16V_4
close SOC
C91188
0.033u/16V_4
Close to EC
PM_THRMTRIP#
Processor pull-up (CPU)
PLACE NEAR CPU
XDP_TMS_CPU
XDP_TDI_CPU
XDP_TDO_CPU
R30249 1K_5%_4
R30219 *51_4
R30267 51_4R30131 49.9_1%_4
R30221 100_1%_4
02
+VCCSTPLL
+1.05V
H_PROCHOT#
XDP_TCK0
XDP_TRST#_CPU
A A
PROJECT : G7BD
PROJECT : G7BD
PROJECT : G7BD
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
R30222 1K_5%_4
R30242 51_5%_4
R30231 *51_5%_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
KBL-U 1/15 eDP/DDI/MISC
KBL-U 1/15 eDP/DDI/MISC
KBL-U 1/15 eDP/DDI/MISC
1
+1.05V
1A
1A
2 49Wednesday, December 26, 2018
2 49Wednesday, December 26, 2018
2 49Wednesday, December 26, 2018
1A
5
M_A_DQSN[7:0]<17>
M_A_DQSP[7:0]<17>
M_B_DQSN[7:0]<18>
M_B_DQSP[7:0]<18>
M_A_DQ[63:0]<17>
M_B_DQ[63:0]<18>
?
WHL ULT Processor (MEM-A) WHL ULT Processor (MEM-B)
D D
C C
B B
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
U30015B
A26
DDR0_DQ_0/DDR0_DQ_0
D26
DDR0_DQ_1/DDR0_DQ_1
D28
DDR0_DQ_2/DDR0_DQ_2
C28
DDR0_DQ_3/DDR0_DQ_3
B26
DDR0_DQ_4/DDR0_DQ_4
C26
DDR0_DQ_5/DDR0_DQ_5
B28
DDR0_DQ_6/DDR0_DQ_6
A28
DDR0_DQ_7/DDR0_DQ_7
B30
DDR0_DQ_8/DDR0_DQ_8
D30
DDR0_DQ_9/DDR0_DQ_9
B33
DDR0_DQ_10/DDR0_DQ_10
D32
DDR0_DQ_11/DDR0_DQ_11
A30
DDR0_DQ_12/DDR0_DQ_12
C30
DDR0_DQ_13/DDR0_DQ_13
B32
DDR0_DQ_14/DDR0_DQ_14
C32
DDR0_DQ_15/DDR0_DQ_15
H37
DDR0_DQ_16/DDR0_DQ_32
H34
DDR0_DQ_17/DDR0_DQ_33
K34
DDR0_DQ_18/DDR0_DQ_34
K35
DDR0_DQ_19/DDR0_DQ_35
H36
DDR0_DQ_20/DDR0_DQ_36
H35
DDR0_DQ_21/DDR0_DQ_37
K36
DDR0_DQ_22/DDR0_DQ_38
K37
DDR0_DQ_23/DDR0_DQ_39
N36
DDR0_DQ_24/DDR0_DQ_40
N34
DDR0_DQ_25/DDR0_DQ_41
R37
DDR0_DQ_26/DDR0_DQ_42
R34
DDR0_DQ_27/DDR0_DQ_43
N37
DDR0_DQ_28/DDR0_DQ_44
N35
DDR0_DQ_29/DDR0_DQ_45
R36
DDR0_DQ_30/DDR0_DQ_46
R35
DDR0_DQ_31/DDR0_DQ_47
AN35
DDR0_DQ_32/DDR1_DQ_0
AN34
DDR0_DQ_33/DDR1_DQ_1
AR35
DDR0_DQ_34/DDR1_DQ_2
AR34
DDR0_DQ_35/DDR1_DQ_3
AN37
DDR0_DQ_36/DDR1_DQ_4
AN36
DDR0_DQ_37/DDR1_DQ_5
AR36
DDR0_DQ_38/DDR1_DQ_6
AR37
DDR0_DQ_39/DDR1_DQ_7
AU35
DDR0_DQ_40/DDR1_DQ_8
AU34
DDR0_DQ_41/DDR1_DQ_9
AW35
DDR0_DQ_42/DDR1_DQ_10
AW34
DDR0_DQ_43/DDR1_DQ_11
AU37
DDR0_DQ_44/DDR1_DQ_12
AU36
DDR0_DQ_45/DDR1_DQ_13
AW36
DDR0_DQ_46/DDR1_DQ_14
AW37
DDR0_DQ_47/DDR1_DQ_15
BA35
DDR0_DQ_48/DDR1_DQ_32
BA34
DDR0_DQ_49/DDR1_DQ_33
BC35
DDR0_DQ_50/DDR1_DQ_34
BC34
DDR0_DQ_51/DDR1_DQ_35
BA37
DDR0_DQ_52/DDR1_DQ_36
BA36
DDR0_DQ_53/DDR1_DQ_37
BC36
DDR0_DQ_54/DDR1_DQ_38
BC37
DDR0_DQ_55/DDR1_DQ_39
BE35
DDR0_DQ_56/DDR1_DQ_40
BE34
DDR0_DQ_57/DDR1_DQ_41
BG35
DDR0_DQ_58/DDR1_DQ_42
BG34
DDR0_DQ_59/DDR1_DQ_43
BE37
DDR0_DQ_60/DDR1_DQ_44
BE36
DDR0_DQ_61/DDR1_DQ_45
BG36
DDR0_DQ_62/DDR1_DQ_46
BG37
DDR0_DQ_63/DDR1_DQ_47
DDR0_CKN_0/DDR0_CKN_0
DDR0_CKP_0/DDR0_CKP_0
DDR0_CKN_1/DDR0_CKN_1
DDR0_CKP_1/DDR0_CKP_1
DDR0_CKE_0/DDR0_CKE_0
DDR0_CKE_1/DDR0_CKE_1
DDR0_CKE_2/NC
DDR0_CKE_3/NC
DDR0_CS#_0/DDR0_CS#_0
DDR0_CS#_1/DDR0_CS#_1
DDR0_ODT_0/DDR0_ODT_0
NC/DDR0_ODT_1
DDR0_CAB_9/DDR0_MA_0
DDR0_CAB_8/DDR0_MA_1
DDR0_CAB_5/DDR0_MA_2
NC/DDR0_MA_3
NC/DDR0_MA_4
DDR0_CAA_0/DDR0_MA_5
DDR0_CAA_2/DDR0_MA_6
DDR0_CAA_4/DDR0_MA_7
DDR0_CAA_3/DDR0_MA_8
DDR0_CAA_1/DDR0_MA_9
DDR0_CAB_7/DDR0_MA_10
DDR0_CAA_7/DDR0_MA_11
DDR0_CAA_6/DDR0_MA_12
DDR0_CAB_0/DDR0_MA_13
DDR0_CAB_2/DDR0_MA_14
DDR0_CAB_1/DDR0_MA_15
DDR0_CAB_3/DDR0_MA_16
DDR0_CAB_4/DDR0_BA_0
DDR0_CAB_6/DDR0_BA_1
DDR0_CAA_5/DDR0_BG_0
DDR0_CAA_8/DDR0_ACT#
DDR0_CAA_9/DDR0_BG_1
DDR0_DQSN_0/DDR0_DQSN_0
DDR0_DQSP_0/DDR0_DQSP_0
DDR0_DQSN_1/DDR0_DQSN_1
DDR0_DQSP_1/DDR0_DQSP_1
DDR0_DQSN_2/DDR0_DQSN_4
DDR0_DQSP_2/DDR0_DQSP_4
DDR0_DQSN_3/DDR0_DQSN_5
DDR0_DQSP_3/DDR0_DQSP_5
DDR0_DQSN_4/DDR1_DQSN_0
DDR0_DQSP_4/DDR1_DQSP_0
DDR0_DQSN_5/DDR1_DQSN_1
DDR0_DQSP_5/DDR1_DQSP_1
DDR0_DQSN_6/DDR1_DQSN_4
DDR0_DQSP_6/DDR1_DQSP_4
DDR0_DQSN_7/DDR1_DQSN_5
DDR0_DQSP_7/DDR1_DQSP_5
NC/DDR0_ALERT#
NC/DDR0_PAR
DDR_VREF_CA
DDR0_VREF_DQ_0
DDR0_VREF_DQ_1
DDR1_VREF_DQ
DDR_VTT_CNTL
*CFL_U_43E_IL_IP_DDR4
2 of 20
4
V32
V31
T32
T31
U36
U37
U34
U35
AE32
AF32
AE31
AF31
M_A_A0
AC37
M_A_A1
AC36
M_A_A2
AC34
M_A_A3
AC35
M_A_A4
AA35
M_A_A5
AB35
M_A_A6
AA37
M_A_A7
AA36
M_A_A8
AB34
M_A_A9
W36
M_A_A10
Y31
M_A_A11
W34
M_A_A12
AA34
M_A_A13
AC32
AC31
AB32
Y32
W32
AB31
V34
V35
W35
M_A_DQSN0
C27
M_A_DQSP0
D27
M_A_DQSN1
D31
M_A_DQSP1
C31
M_A_DQSN2
J35
M_A_DQSP2
J34
M_A_DQSN3
P34
M_A_DQSP3
P35
M_A_DQSN4
AP35
M_A_DQSP4
AP34
M_A_DQSN5
AV34
M_A_DQSP5
AV35
M_A_DQSN6
BB35
M_A_DQSP6
BB34
M_A_DQSN7
BF34
M_A_DQSP7
BF35
M_A_ALERT#
W37
M_A_PARITY
W31
SM_VREF
F36
D35
D37
SMDDR_VREF_DQ1_M3
E36
DDR_VTT_CNTL
C35
3
WHL ULT Processor (DDR4)
?
M_A_CLKN0 <17>
M_A_CLKP0 <17>
M_A_CLKN1 <17>
M_A_CLKP1 <17>
M_A_CKE0 <17>
M_A_CKE1 <17>
M_A_CS#0 <17>
M_A_CS#1 <17>
M_A_DIM0_ODT0 <17>
M_A_DIM0_ODT1 <17>
M_A_A0 <17>
M_A_A1 <17>
M_A_A2 <17>
M_A_A3 <17>
M_A_A4 <17>
M_A_A5 <17>
M_A_A6 <17>
M_A_A7 <17>
M_A_A8 <17>
M_A_A9 <17>
M_A_A10 <17>
M_A_A11 <17>
M_A_A12 <17>
M_A_A13 <17>
M_A_WE# <17>
M_A_CAS# <17>
M_A_RAS# <17>
M_A_BS#0 <17>
M_A_BS#1 <17>
M_A_BG#0 <17>
M_A_ACT# <17>
M_A_BG#1 <17>
M_A_ALERT# <17>
M_A_PARITY <17>
TP30088
SM_VREF <17>
SMDDR_VREF_DQ1_M3 <18>
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
U30015C
J22
DDR1_DQ_0/DDR0_DQ_16
H25
DDR1_DQ_1/DDR0_DQ_17
G22
DDR1_DQ_2/DDR0_DQ_18
H22
DDR1_DQ_3/DDR0_DQ_19
F25
DDR1_DQ_4/DDR0_DQ_20
J25
DDR1_DQ_5/DDR0_DQ_21
G25
DDR1_DQ_6/DDR0_DQ_22
F22
DDR1_DQ_7/DDR0_DQ_23
D22
DDR1_DQ_8/DDR0_DQ_24
C22
DDR1_DQ_9/DDR0_DQ_25
C24
DDR1_DQ_10/DDR0_DQ_26
D24
DDR1_DQ_11/DDR0_DQ_27
A22
DDR1_DQ_12/DDR0_DQ_28
B22
DDR1_DQ_13/DDR0_DQ_29
A24
DDR1_DQ_14/DDR0_DQ_30
B24
DDR1_DQ_15/DDR0_DQ_31
G31
DDR1_DQ_16/DDR0_DQ_48
G32
DDR1_DQ_17/DDR0_DQ_49
H29
DDR1_DQ_18/DDR0_DQ_50
H28
DDR1_DQ_19/DDR0_DQ_51
G28
DDR1_DQ_20/DDR0_DQ_52
G29
DDR1_DQ_21/DDR0_DQ_53
H31
DDR1_DQ_22/DDR0_DQ_54
H32
DDR1_DQ_23/DDR0_DQ_55
L31
DDR1_DQ_24/DDR0_DQ_56
L32
DDR1_DQ_25/DDR0_DQ_57
N29
DDR1_DQ_26/DDR0_DQ_58
N28
DDR1_DQ_27/DDR0_DQ_59
L28
DDR1_DQ_28/DDR0_DQ_60
L29
DDR1_DQ_29/DDR0_DQ_61
N31
DDR1_DQ_30/DDR0_DQ_62
N32
DDR1_DQ_31/DDR0_DQ_63
AJ29
DDR1_DQ_32/DDR1_DQ_16
AJ30
DDR1_DQ_33/DDR1_DQ_17
AM32
DDR1_DQ_34/DDR1_DQ_18
AM31
DDR1_DQ_35/DDR1_DQ_19
AM30
DDR1_DQ_36/DDR1_DQ_20
AM29
DDR1_DQ_37/DDR1_DQ_21
AJ31
DDR1_DQ_38/DDR1_DQ_22
AJ32
DDR1_DQ_39/DDR1_DQ_23
AR31
DDR1_DQ_40/DDR1_DQ_24
AR32
DDR1_DQ_41/DDR1_DQ_25
AV30
DDR1_DQ_42/DDR1_DQ_26
AV29
DDR1_DQ_43/DDR1_DQ_27
AR30
DDR1_DQ_44/DDR1_DQ_28
AR29
DDR1_DQ_45/DDR1_DQ_29
AV32
DDR1_DQ_46/DDR1_DQ_30
AV31
DDR1_DQ_47/DDR1_DQ_31
BA32
DDR1_DQ_48/DDR1_DQ_48
BA31
DDR1_DQ_49/DDR1_DQ_49
BD31
DDR1_DQ_50/DDR1_DQ_50
BD32
DDR1_DQ_51/DDR1_DQ_51
BA30
DDR1_DQ_52/DDR1_DQ_52
BA29
DDR1_DQ_53/DDR1_DQ_53
BD29
DDR1_DQ_54/DDR1_DQ_54
BD30
DDR1_DQ_55/DDR1_DQ_55
BG31
DDR1_DQ_56/DDR1_DQ_56
BG32
DDR1_DQ_57/DDR1_DQ_57
BK32
DDR1_DQ_58/DDR1_DQ_58
BK31
DDR1_DQ_59/DDR1_DQ_59
BG29
DDR1_DQ_60/DDR1_DQ_60
BG30
DDR1_DQ_61/DDR1_DQ_61
BK30
DDR1_DQ_62/DDR1_DQ_62
BK29
DDR1_DQ_63/DDR1_DQ_63
3 of 20
DDR1_CKN_0/DDR1_CKN_0
DDR1_CKP_0/DDR1_CKP_0
DDR1_CKN_1/DDR1_CKN_1
DDR1_CKP_1/DDR1_CKP_1
DDR1_CKE_0/DDR1_CKE_0
DDR1_CKE_1/DDR1_CKE_1
DDR1_CKE_2/NC
DDR1_CKE_3/NC
DDR1_CS#_0/DDR1_CS#_0
DDR1_CS#_1/DDR1_CS#_1
DDR1_ODT_0/DDR1_ODT_0
NC/DDR1_ODT_1
DDR1_CAB_9/DDR1_MA_0
DDR1_CAB_8/DDR1_MA_1
DDR1_CAB_5/DDR1_MA_2
NC/DDR1_MA_3
NC/DDR1_MA_4
DDR1_CAA_0/DDR1_MA_5
DDR1_CAA_2/DDR1_MA_6
DDR1_CAA_4/DDR1_MA_7
DDR1_CAA_3/DDR1_MA_8
DDR1_CAA_1/DDR1_MA_9
DDR1_CAB_7/DDR1_MA_10
DDR1_CAA_7/DDR1_MA_11
DDR1_CAA_6/DDR1_MA_12
DDR1_CAB_0/DDR1_MA_13
DDR1_CAB_2/DDR1_MA_14
DDR1_CAB_1/DDR1_MA_15
DDR1_CAB_3/DDR1_MA_16
DDR1_CAB_4/DDR1_BA_0
DDR1_CAB_6/DDR1_BA_1
DDR1_CAA_5/DDR1_BG_0
DDR1_CAA_9/DDR1_BG_1
DDR1_CAA_8/DDR1_ACT#
DDR1_DQSN_0/DDR0_DQSN_2
DDR1_DQSP_0/DDR0_DQSP_2
DDR1_DQSN_1/DDR0_DQSN_3
DDR1_DQSP_1/DDR0_DQSP_3
DDR1_DQSN_2/DDR0_DQSN_6
DDR1_DQSP_2/DDR0_DQSP_6
DDR1_DQSN_3/DDR0_DQSN_7
DDR1_DQSP_3/DDR0_DQSP_7
DDR1_DQSN_4/DDR1_DQSN_2
DDR1_DQSP_4/DDR1_DQSP_2
DDR1_DQSN_5/DDR1_DQSN_3
DDR1_DQSP_5/DDR1_DQSP_3
DDR1_DQSN_6/DDR1_DQSN_6
DDR1_DQSP_6/DDR1_DQSP_6
DDR1_DQSN_7/DDR1_DQSN_7
DDR1_DQSP_7/DDR1_DQSP_7
NC/DDR1_ALERT#
NC/DDR1_PAR
DRAM_RESET#
DDR_COMP_0
DDR_COMP_1
DDR_COMP_2
*CFL_U_43E_IL_IP_DDR4
2
+1.2VSUS <3,6,17,18,39,41>
AF28
AF29
AE28
AE29
T28
T29
V28
V29
AL37
AL35
AL36
AL34
M_B_A0
AG36
M_B_A1
AG35
M_B_A2
AF34
M_B_A3
AG37
M_B_A4
AE35
M_B_A5
AF35
M_B_A6
AE37
M_B_A7
AC29
M_B_A8
AE36
M_B_A9
AB29
M_B_A10
AG34
M_B_A11
AC28
M_B_A12
AB28
M_B_A13
AK35
AJ35
AK34
AJ34
AJ37
AJ36
W29
Y28
W28
M_B_DQSN0
H24
M_B_DQSP0
G24
M_B_DQSN1
C23
M_B_DQSP1
D23
M_B_DQSN2
G30
M_B_DQSP2
H30
M_B_DQSN3
L30
M_B_DQSP3
N30
M_B_DQSN4
AL31
M_B_DQSP4
AL30
M_B_DQSN5
AU31
M_B_DQSP5
AU30
M_B_DQSN6
BC31
M_B_DQSP6
BC30
M_B_DQSN7
BH31
M_B_DQSP7
BH30
M_B_ALERT#
Y29
M_B_PARITY
AE34
BU31
SM_RCOMP_0
BN28
SM_RCOMP_1
BN27
BN29
Layout: DDR Rcomp need follow Intel Spec
15 mil trance length
M_B_CLKN0 <18>
M_B_CLKP0 <18>
M_B_CLKN1 <18>
M_B_CLKP1 <18>
M_B_CKE0 <18>
M_B_CKE1 <18>
M_B_CS#0 <18>
M_B_CS#1 <18>
M_B_DIM0_ODT0 <18>
M_B_DIM0_ODT1 <18>
M_B_A0 <18>
M_B_A1 <18>
M_B_A2 <18>
M_B_A3 <18>
M_B_A4 <18>
M_B_A5 <18>
M_B_A6 <18>
M_B_A7 <18>
M_B_A8 <18>
M_B_A9 <18>
M_B_A10 <18>
M_B_A11 <18>
M_B_A12 <18>
M_B_A13 <18>
M_B_WE# <18>
M_B_CAS# <18>
M_B_RAS# <18>
M_B_BS#0 <18>
M_B_BS#1 <18>
M_B_BG#0 <18>
M_B_BG#1 <18>
M_B_ACT# <18>
M_B_ALERT# <18>
M_B_PARITY <18>
R30087 121_1%_4
R30086 80.6_1%_4
R30095 100_1%_4
+1.2VSUS
R30143
470_1%_4
R30144 *0_4/S
1
03
DDR4_DRAMRST# <17,18>
DDR4_DRAMRST#SM_RCOMP_2
C30265
0.1u/16V_4
A A
PROJECT : G7BD
PROJECT : G7BD
PROJECT : G7BD
Quanta Computer Inc.
Quanta Computer Inc.
+1.2VSUS <3,6,17,18,39,41>
+3V_DEEP_SUS <4,10,11,13,14,15,16,32>
5
4
3
2
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
KBL-U 2/15(DDR4 I/F)
KBL-U 2/15(DDR4 I/F)
KBL-U 2/15(DDR4 I/F)
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
3 49Wednesday, December 26, 2018
3 49Wednesday, December 26, 2018
3 49Wednesday, December 26, 2018
1A
1A
1A
5
+3V_DEEP_SUS<10,11,13,14,15,16,32>
+3V<10,11,12,13,14,15,17,18,22,25,26,27,28,29,31,32,33,34,35,42,45,46,47>
+3VS5<12,13,15,29,32,33,34,35,38,39,40,41,45,48>
+VCCSTPLL<2,5,6,41,42>
+1.05V<2,6,35,41>
+BAT_RTC<13,15,31,36,49>
D D
RSMRST#<35>
EC30037
220p/50V_4
PCIE_WAKE#<28,34>
EC_PWROK<35>
TP30027
TP30083
R30234 *1K_5%_4
C30394 0.1u/16V_4
PLTRST#
SYS_RESET#
RSMRST#
PROCPWRGD
H_VCCST_PWRGD
SYS_PWROK
PCH_PWROK
DSWROK_EC_R
SUSWARN#
R304060_4
SUSACK#
PCIE_WAKE#
LAN_WAKE#
4
?
U30015K
BJ35
GPP_B13/PLTRST#
CN10
SYS_RESET#
BR36
RSMRST#
AR2
PROCPWRGD
BJ2
VCCST_PWRGOOD
CR10
SYS_PWROK
BP31
PCH_PWROK
BP30
DSW_PW ROK
BV34
GPP_A13/SUSW ARN#/SUSPW RDACK
BY32
GPP_A15/SUSACK#
BU30
WAKE#
BU32
GPD2/LAN_WAKE#
BU34
GPD11/LANPHYPC
*CFL_U_43E_IL_IP_DDR4
11 of 20
GPP_B12/SLP_S0#
GPD4/SLP_S3#
GPD5/SLP_S4#
GPD10/SLP_S5#
SLP_SUS#
SLP_LAN#
GPD9/SLP_WLAN#
GPD6/SLP_A#
GPD3/PWRBTN#
GPD1/ACPRESENT
GPD0/BATLOW #
GPP_B11/EXT_PW R_GATE#
INTRUDER#
GPP_B2/VRALERT#
INPUT3VSEL
3
PCH_SLP_S0_N
BJ37
BU36
BU27
SLP_S5#
BT29
SLP_SUS#_EC
BU29
SLP_LAN#
BT31
BT30
GPD9
SLP_A#
BU37
BU28
DNBSWON#
AC_PRESENT_EC
BU35
RF_OFF_PCH
BV36
INTRUDER#_R
BR35
EXT_PWR_GATE#
CC37
CC36
BT27
SLP_SUS#_EC
SUSB#
SUSC#
TP30087
TP30031
R30398 1M_5%_4
3V SELECT STRAP
R124546
LOW-> 3.3V
4.7K_5%_4
C91182
0.47u/6.3V_2
TP30026
TP30030
TP30024
C91183
0.47u/6.3V_2
SUSB# <35>
SUSC# <35>
SLP_SUS#_EC <35>
DNBSWON# <35>
AC_PRESENT_EC <35>
+BAT_RTC
2
C91184
0.47u/6.3V_2
1
PCH Pull-high/low(CLG)
+3V_DEEP_SUS
SUSWARN#
SUSACK#
PCIE_WAKE#
AC_PRESENT_EC
LAN_WAKE#
RF_OFF_PCH
PCH_SLP_S0_N
EXT_PWR_GATE#
DSWROK_EC
SYS_RESET#
RSMRST#
DSWROK_EC_R
R124596 *10K_5%_4
R30403 *10K_5%_4
+3VS5
R30356 8.2K_5%_4
R30411 *10K_4
R30355 *10K_4
R124555 8.2K_5%_4
R124553 100K_1%_4
R124554 100K_1%_4
R124574 100K_1%_4
+3V
R30285 10K_5%_4
R30378 10K_5%_4
R30409 1M_5%_4
04
C C
For DS3 Sequence
For DS3 -->Ra
Non-DS3 -->Rb
SI
RSMRST#
DSWROK_EC<35>
PLTRST#(CLG)
Check Rise/Fall time less than 100ns
R30382
+3V
100K_1%_4
R124545
*100K_1%_4
B B
System PWR_OK(CLG)
A A
Rb
R30395 0_4
R30408 *0_5%_4
Ra
PLTRST# <19,28,32,33,34,35>
EC_PWROKSYS_PWROK
R124544
0_4
DSWROK_EC_R
C91181
0.01u/50V_4
+3V
R124573
*100K_1%_4
R124547
100K_1%_4
+VCCSTPLL
R30212
1K_5%_4
HWPG<16,35,38,39,40>
D30010 RB500V-40
2
1
Ra close to CPU side
H_VCCST_PWRGD trace 0.3" - 1.5"
H_VCCST_PWRGD_R
C30363
*10P/50V_4
Ra
R30211 60.4_1%_4
H_VCCST_PWRGD
+1.8V +3VS5+5VS5
R30042
15K_1%_4
+1.8V_PWRGD_G1
C30060
0.1u/16V_4
R30043
100K_5%_4
2
1 3
R30044
100K_5%_4
+1.8V_PWRGD_G2
Q30001
METR3904-G
R30075
10K_5%_4
HWPG
3
2
1
Q30004
2N7002K
R30076
100K_5%_4
PROJECT : G7BD
PROJECT : G7BD
PROJECT : G7BD
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
KBL-U 3/15(PowerManger)
KBL-U 3/15(PowerManger)
KBL-U 3/15(PowerManger)
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
1
4 49Wednesday, December 26, 2018
4 49Wednesday, December 26, 2018
4 49Wednesday, December 26, 2018
1A
1A
1A
5
+VCC_CORE<7,42,43>
+1.05V<2,6,35,41>
+VCCSTG<6>
+VCCSTPLL<2,4,6,41,42>
Under CPU
C30107
C30102
22u/6.3V_6
D D
C C
*10U/6.3V_4
10u/6.3V_4
C30031
*22u/6.3V_6
C30100
10u/6.3V_4
C30029
*22U/6.3V_6
10u/6.3V_4
C30101
10u/6.3V_4
C30033
*22u/6.3V_6
C30121
10u/6.3V_4
C30077
10u/6.3V_4
C30034
*22U/6.3V_6
C30074
*22U/6.3V_6
C30076
10u/6.3V_4
C30084
*22u/6.3V_6
C30111
10u/6.3V_4
C30032
*22U/6.3V_6
C30028
*22u/6.3V_6
22u/6.3V_6
C30050
10u/6.3V_4
C30064
*22u/6.3V_6
Close CPU
+VCC_CORE
C30341
47U/6.3VS_6
4
+VCC_CORE +VCC_CORE
C30088
22u/6.3V_6
C30085
*22u/6.3V_6
C30030
22u/6.3V_6
C30340
47U/6.3VS_6
AN9
AN10
AN24
AN26
AN27
AP2
AP9
AP24
AP26
AR5
AR6
AR7
AR8
AR10
AR25
AR27
AT9
AT24
AT26
AU5
AU6
AU7
AU8
AU9
AU24
AU25
AU26
AU27
AV2
AV5
AV7
AV10
AV27
AW5
AW6
AW7
AW8
AW9
AW10
BB9
BC24
AY9
BB24
C30364
*47U/6.3VS_6
?
U30015L
VCCCORE5
VCCCORE1
VCCCORE2
VCCCORE3
VCCCORE4
VCCCORE6
VCCCORE9
VCCCORE7
VCCCORE8
VCCCORE13
VCCCORE14
VCCCORE15
VCCCORE16
VCCCORE10
VCCCORE11
VCCCORE12
VCCCORE19
VCCCORE17
VCCCORE18
VCCCORE24
VCCCORE25
VCCCORE26
VCCCORE27
VCCCORE28
VCCCORE20
VCCCORE21
VCCCORE22
VCCCORE23
VCCCORE30
VCCCORE32
VCCCORE33
VCCCORE29
VCCCORE31
VCCCORE39
VCCCORE40
VCCCORE41
VCCCORE42
VCCCORE43
VCCCORE34
RSVD3
RSVD4
RSVD1
RSVD2
C30351
47U/6.3VS_6
VCCCORE35
VCCCORE36
VCCCORE37
VCCCORE38
VCCCORE44
VCCCORE45
VCCCORE48
VCCCORE49
VCCCORE50
VCCCORE46
VCCCORE47
VCCCORE51
VCCCORE52
VCCCORE56
VCCCORE57
VCCCORE58
VCCCORE59
VCCCORE53
VCCCORE54
VCCCORE55
VCCCORE63
VCCCORE64
VCCCORE60
VCCCORE61
VCCCORE62
VCCCORE69
VCCCORE65
VCCCORE66
VCCCORE67
VCCCORE68
VCCCORE70
VCCCORE73
VCCCORE71
VCCCORE72
VCCCORE74
VCC_SENSE
VSS_SENSE
VIDALERT#
*CFL_U_43E_IL_IP_DDR4
12 of 20
C30402
47U/6.3VS_6
VIDSCK
VIDSOUT
RSVD5
VCCSTG1
C30399
47U/6.3VS_6
AW24
AW25
AW26
AW27
AY24
AY26
BA5
BA7
BA8
BA25
BA27
BB2
BB26
BC5
BC6
BC7
BC9
BC10
BC26
BC27
BD5
BD8
BD10
BD25
BD27
BE9
BE24
BE25
BE26
BE27
BF2
BF9
BF24
BF26
BG27
AN6
AN5
AA3
AA1
BOM
AA2
Y3
BG3
47U/6.3VS_6
H_CPU_SVIDALRT#
VR_SVID_CLK_R
H_CPU_SVIDDAT
C30339
C30395
47U/6.3VS_6
3
C30051
1u/6.3V_4
C30108
1u/6.3V_4
R30259 100_1%_4
R30260 100_1%_4
+VCCSTG
1/22WHL PART
C30120
1u/6.3V_4
C30040
1u/6.3V_4
C30130
C30122
1u/6.3V_4C30106
1u/6.3V_4
C30039
C30090
1u/6.3V_4C30089
1u/6.3V_4
+VCC_CORE
VCC_SENSE <42>
VSS_SENSE <42>
C30131
1u/6.3V_4
C30053
1u/6.3V_4
Close CPU
2
1
Under CPU
+
VCCEOPIO1
VCCEOPIO2
VCCEOPIO3
VCCEOPIO4
VCCEOPIO5
VCCEOPIO6
VCCEOPIO7
VCCEOPIO8
C9101
*330u/2.5V_3528H1.9
100- ±1%
pull-up to VCC
near processor.
+VCC_CORE
AA24
AA26
AB25
AC24
AC25
AC26
AD24
AD26
V25
T25
+VCCSTPLL
C30118
1u/6.3V_4
C30061
1u/6.3V_4
C30035
22u/6.3V_6
C30041
1u/6.3V_4
C30129
1u/6.3V_4C30132
C30052
1u/6.3V_4
WHL=>RSVD WHL=>RSVD
C30036
*22u/6.3V_6
C30062
10u/6.3V_4
U30015O
K12
VCCOPC1
K14
VCCOPC2
K15
VCCOPC3
K17
VCCOPC4
K18
VCCOPC5
K20
VCCOPC6
L25
VCCOPC7
M24
VCCOPC8
M26
VCCOPC9
P24
VCCOPC10
P26
VCCOPC11
R24
VCCOPC12
R25
VCCOPC13
R26
VCCOPC14
W25
VCC_OPC_1P82
V24
VCC_OPC_1P81
Y25
VCC_OPC_1P84
Y24
VCC_OPC_1P83
*CFL_U_43E_IL_IP_DDR4
VCCEOPIO_SENSE
VSSEOPIO_SENSE
15 of 20
C30073
22u/6.3V_6
C30373
0.1U/16V_4
C99152
10u/6.3V_4
+VCCPLL
05
C99153
10u/6.3V_4
+VCC_CORE
B B
A A
5
C30385
10u/6.3V_4
C30374
10u/6.3V_4
C30370
*22U/6.3V_6
4
C30392
10u/6.3V_4
C30415
C30381
10u/6.3V_4
10u/6.3V_4
PLACE THE PU RESISTORS
CLOSE TO VR
PULL UP IS IN THE VR MODULE
CLOSE TO CPU
PLACE THE PU RESISTORS
C30380
10u/6.3V_4
C30387
*22U/6.3V_6
VR_SVID_CLK_R
H_CPU_SVIDDAT
3
R30254 *0_4/S
Layout note: need routing together and ALERT need between CLK and DATA.
+VCCSTPLL
CLOSE TO CPU
PLACE THE PU RESISTORS
+VCCSTPLL
R30230
*54.9/F_4
H_CPU_SVIDALRT#
R30276 220_1%_4
R30229
56.2_1%_4
C99154
*0.1U/16V_4
SVID CLK
VR_SVID_CLK <42>
+VCCSTPLL
R30236
100_1%_4
PROJECT : G7BD
PROJECT : G7BD
R30224 *0_4/S
SVID DATA
VR_SVID_DATA <42>
2
PROJECT : G7BD
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
SVID ALERT
VR_SVID_ALERT# <42>
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
KBL-U 4/15 (POWER-1)
KBL-U 4/15 (POWER-1)
KBL-U 4/15 (POWER-1)
1
5 49Wednesday, December 26, 2018
5 49Wednesday, December 26, 2018
5 49Wednesday, December 26, 2018
1A
1A
1A
5
+VCCSTPLL <2,4,5,41,42>
+VCCSA <42,44>
+1.2VSUS <3,17,18,39,41>
+1.05V_DEEP_SUS <9,15,33,40,41>
+1.05V <2,35,41>
+3VPCU <13,31,34,35,36,38,49>
Under CPU
D D
10u/6.3V_4
C30445
C30195
10u/6.3V_4
C30448
10u/6.3V_4
C30191
10u/6.3V_4
C30447
10u/6.3V_4
C30169
1u/6.3V_4
C30446
10u/6.3V_4
Close CPU
C30189
1u/6.3V_4
*10U/6.3V_4
+1.2VSUS
C30444
1u/6.3V_4
1u/6.3V_4
C30148
1u/6.3V_4
C30147
Close CPU Under CPU
+1.05V
R124550 0_5%_4
C C
R124551 0_6
Under CPU
+VCCSTG +VCCPLL_OC
C30382
1u/6.3V_4
C30128
1u/6.3V_4
+VCCSTG
+VCCPLL+VCCSTPLL
+1.2VSUS
+1.2V_VCCPLL_OC +VCCPLL_OC
Volume
R124548 0_5%_6
R124549 *0_5%_6
Premium
+VCCSTPLL
+VCCSTG
+VCCPLL_OC
+VCCPLL
+VCCPLL_OC
4
?
U30015N
AD36
VDDQ1
AH32
VDDQ2
AH36
VDDQ3
AM36
VDDQ4
AN32
VDDQ5
AW32
VDDQ6
AY36
VDDQ7
BE32
VDDQ8
BH36
VDDQ9
R32
VDDQ10
Y36
VDDQ11
BC28
RSVD1
BP11
VCCST1
BP2
VCCST2
BG1
VCCSTG1
BG2
VCCSTG2
BL27
VCCPLL_OC1
BM26
VCCPLL_OC2
BR11
VCCPLL1
BT11
VCCPLL2
*CFL_U_43E_IL_IP_DDR4
VCCIO_SENSE
VSSIO_SENSE
VSSSA_SENSE
VCCSA_SENSE
14 of 20
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCSA2
VCCSA1
VCCSA3
VCCSA5
VCCSA6
VCCSA4
VCCSA9
VCCSA7
VCCSA8
VCCSA13
VCCSA14
VCCSA10
VCCSA11
VCCSA12
VCCSA15
VCCSA16
AK24
AK26
AL24
AL25
AL26
AL27
AM25
AM27
BH24
BH25
BH26
BH27
BJ24
BJ26
BP16
BP18
BG8
BG10
BH9
BJ8
BJ9
BJ10
BK8
BK25
BK27
BL8
BL9
BL10
BL24
BL26
BM24
BN25
BP28
BP29
BE7
BG7
3
VCCIO_VCCSENSE
VCCIO_VSSSENSE
VCCIO_VCCSENSE
VCCIO_VSSSENSE
C30163
1u/6.3V_4
+VCCSA
C30155
1u/6.3V_4
R30082 100_1%_4
R30085 100_1%_4
2
Under CPU Close CPU
C30162
1u/6.3V_4C30175
C30177
1u/6.3V_4
10u/6.3V_4
C30161
10u/6.3V_4
C30126
10u/6.3V_4
C30181
1u/6.3V_4
C30124
Under CPU
C30094
C30140
1u/6.3V_4
1u/6.3V_4
C30154
C30139
10u/6.3V_4
10u/6.3V_4
VSSSA_SENSE <42>
VCCSA_SENSE <42>
+VCCIO
C30136
1u/6.3V_4
C30171
10u/6.3V_4
C30103
1u/6.3V_4
C30109
10u/6.3V_4
C30152
1u/6.3V_4
C30141
10u/6.3V_4
C30153
1u/6.3V_4
C30173
10u/6.3V_4
C30164
1u/6.3V_4
C30174
10u/6.3V_4
Close CPU
C30114
10u/6.3V_4
C30182
1u/6.3V_4
+VCCIO
C30142
10u/6.3V_4
C30123
1u/6.3V_4
C30172
10u/6.3V_4
C30137
10u/6.3V_4
1
C30170
10u/6.3V_4
06
C30156
10u/6.3V_4
IO Thrm Protect
Close A18 Ball
+VCCSTPLL
B B
C30376
*1U/6.3V_4
C30371
22U/6.3V_6
Close CPU
C30388
1u/6.3V_4
+VCCSTPLL
C30042
1u/6.3V_4
+VCCPLL
+3VPCU
R30002
20K_1%_4
For 75 degree, 1.2v limit, (HW)
THER_CPU
TM30001
100K_NTC_4_3%
1 2
C30005
0.1u/16V_4
THERMISTOR <35>
For CPU USEFor PIPE USE
+3VPCU
R30001
20K_1%_4
For 75 degree, 1.2v limit, (HW)
THER_PIPE
TM30000
100K_NTC_4_3%
1 2
C30004
0.1u/16V_4
THERMISTOR_SHDN <35>
A A
+1.2VSUS
C30193
10u/6.3V_4
C30194
10u/6.3V_4
Close to CPU
C30190
10u/6.3V_4
5
C30188
10u/6.3V_4
10u/6.3V_4
C30176
C30146
10u/6.3V_4
C30168
1u/6.3V_4
C30149
1u/6.3V_4
4
C30167
1u/6.3V_4
C30192
1u/6.3V_4
PROJECT : G7BD
PROJECT : G7BD
PROJECT : G7BD
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
KBL-U 5/15 (POWER-2)
KBL-U 5/15 (POWER-2)
KBL-U 5/15 (POWER-2)
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
1
6 49Wednesday, December 26, 2018
6 49Wednesday, December 26, 2018
6 49Wednesday, December 26, 2018
1A
1A
1A
5
+VCCGT <42,44>
+VCC_CORE <5,42,43>
+1.2VSUS <3,6,17,18,39,41>
Under CPU
D D
C C
B B
C30068
10u/6.3V_4
C30045
10u/6.3V_4
C30093
10u/6.3V_4
C30070
10u/6.3V_4
C30047
10u/6.3V_4
C30095
10u/6.3V_4
C30113
10u/6.3V_4
C30144
22U/6.3V_6
C30393
1u/6.3V_4
C30419
1u/6.3V_4
C30048
10u/6.3V_4
C30178
10u/6.3V_4
+VCCGT_+VCORE
C30110
22U/6.3V_6
C30426
1u/6.3V_4
C30412
1u/6.3V_4
C30067
10u/6.3V_4
C30104
10u/6.3V_4
C30127
22U/6.3V_6
C30425
1u/6.3V_4
C30405
1u/6.3V_4
4
C30044
10u/6.3V_4
+VCCGT_+VCORE
C30087
10u/6.3V_4
C30386
22U/6.3V_6
C30430
1u/6.3V_4
C30406
1u/6.3V_4
+VCCGT
C30092
10u/6.3V_4
C30125
10u/6.3V_4
C30184
22U/6.3V_6
C30071
10u/6.3V_4
C30065
10U/6.3V_4
C30135
22U/6.3V_6
C30396
1u/6.3V_4
C30431
1u/6.3V_4
3
?
U30015M
A5
VCCGT8
A6
VCCGT9
A8
VCCGT10
A11
VCCGT1
C30046
10u/6.3V_4
C30079
10u/6.3V_4
C30183
22u/6.3V_6
+VCCGT
C30411
1u/6.3V_4
C30418
1u/6.3V_4
+VCCGT_+VCORE +VCCGT_+VCORE
A12
VCCGT2
A14
VCCGT3
A15
VCCGT4
A17
VCCGT5
A18
VCCGT6
A20
VCCGT7
AA9
VCCGT11
AB2
VCCGT13
AB8
VCCGT14
AB9
VCCGT15
AB10
VCCGT12
AC8
VCCGT16
AD9
VCCGT17
AE8
VCCGT19
AE9
VCCGT20
AE10
VCCGT18
AF2
VCCGT22
AF8
VCCGT23
AF10
VCCGT21
AG8
VCCGT24
AG9
VCCGT25
AH9
VCCGT26
AJ8
VCCGT28
AJ10
VCCGT27
AK2
VCCGT29
AK9
VCCGT30
AL8
VCCGT32
AL9
VCCGT33
AL10
VCCGT31
AM8
VCCGT34
B3
VCCGT39
B4
VCCGT40
B6
VCCGT41
B8
VCCGT42
B11
VCCGT35
B14
VCCGT36
B17
VCCGT37
B20
VCCGT38
C2
VCCGT49
C3
VCCGT51
C6
VCCGT52
C7
VCCGT53
C8
VCCGT54
C11
VCCGT43
C12
VCCGT44
C14
VCCGT45
C15
VCCGT46
C17
VCCGT47
C18
VCCGT48
C20
VCCGT50
D4
VCCGT62
D7
VCCGT63
D11
VCCGT55
D12
VCCGT56
D14
VCCGT57
Y10
VCCGT119
*CFL_U_43E_IL_IP_DDR4
BOM
VCCGT_SENSE
VSSGT_SENSE
13 of 20
VCCGT58
VCCGT59
VCCGT60
VCCGT61
VCCGT64
VCCGT69
VCCGT70
VCCGT71
VCCGT72
VCCGT65
VCCGT66
VCCGT67
VCCGT68
VCCGT73
VCCGT74
VCCGT75
VCCGT76
VCCGT77
VCCGT78
VCCGT79
VCCGT87
VCCGT88
VCCGT89
VCCGT90
VCCGT80
VCCGT81
VCCGT82
VCCGT83
VCCGT84
VCCGT85
VCCGT86
VCCGT95
VCCGT96
VCCGT91
VCCGT92
VCCGT93
VCCGT94
VCCGT98
VCCGT97
VCCGT100
VCCGT101
VCCGT99
VCCGT102
VCCGT104
VCCGT105
VCCGT106
VCCGT103
VCCGT107
VCCGT108
VCCGT109
VCCGT111
VCCGT112
VCCGT110
VCCGT114
VCCGT113
VCCGT115
VCCGT116
VCCGT117
VCCGT118
VCCGT120
D15
D17
D18
D20
E4
F5
F6
F7
F8
F11
F14
F17
F20
G11
G12
G14
G15
G17
G18
G20
H5
H6
H7
H8
H11
H12
H14
H15
H17
H18
H20
J7
J8
J11
J14
J17
J20
K2
K11
L7
L8
L10
M9
N7
N8
N9
N10
P2
P8
R9
T8
T9
T10
U8
U10
V2
V9
W8
W9
Y8
E3
D2
+VCCGT
+VCCGT_+VCORE
+VCCGT
+VCCGT
+VCCGT
Close CPU
C30400
22u/6.3V_6
C30403
22u/6.3V_6
C99134
22u/6.3V_6
VCCGT_SENSE <42>
VSSGT_SENSE <42>
C30409
22u/6.3V_6
C30423
22u/6.3V_6
C99136
22u/6.3V_6
2
C30416
22u/6.3V_6
C30086
22u/6.3V_6
C99135
22u/6.3V_6
C30072
22u/6.3V_6
C30421
22u/6.3V_6
C99137
22u/6.3V_6
C30134
22u/6.3V_6
C30057
22u/6.3V_6
C30166
47U/6.3VS_6
C30157
22u/6.3V_6
C30143
22u/6.3V_6
1
07
+VCC_CORE
A A
5
4
R30097 *0805S
R30092 *0805S
R30069 *0805S
For WHL U42 ES2
3
+VCCGT
R30098 *0.0002_5%_0805
+VCCGT_+VCORE +VCCGT_+VCORE
/0122 For WHL U42 ES1
R30073 *0.0002_5%_0805
2
/0122
PROJECT : G7BD
PROJECT : G7BD
PROJECT : G7BD
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
KBL-U 6/15 (POWER-3)
KBL-U 6/15 (POWER-3)
KBL-U 6/15 (POWER-3)
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
1A
1A
7 49Wednesday, December 26, 2018
7 49Wednesday, December 26, 2018
7 49Wednesday, December 26, 2018
1A
5
4
3
2
1
08
?
D D
C C
B B
U30015T
N6
VSS_290
B37
VSS_291
CB3
VSS_292
P10
VSS_293
B5
VSS_294
CB33
VSS_295
P3
VSS_296
B7
VSS_297
CB4
VSS_298
P33
VSS_299
B9
VSS_300
CB7
VSS_301
P36
VSS_302
BA10
VSS_303
CC11
VSS_304
P4
VSS_305
BA28
VSS_306
P7
VSS_307
BA3
VSS_308
CC20
VSS_309
R27
VSS_310
BB3
VSS_311
CC25
VSS_312
R28
VSS_313
BB33
VSS_314
CC28
VSS_315
R29
VSS_316
BB36
VSS_317
CC31
VSS_318
R30
VSS_319
BB4
VSS_320
CC7
VSS_321
R31
VSS_322
BC25
VSS_323
CD11
VSS_324
T27
VSS_325
CD12
VSS_326
T30
VSS_327
BC29
VSS_328
CD14
VSS_329
T33
VSS_330
T35
VSS_331
BC32
VSS_332
CD24
VSS_333
T36
VSS_334
CD25
VSS_335
T7
VSS_336
BC8
VSS_337
CE33
VSS_338
U26
VSS_339
BD28
VSS_340
CE35
VSS_341
U7
VSS_342
BD33
VSS_343
CE36
VSS_344
V26
VSS_345
BD35
VSS_346
CE7
VSS_347
V27
VSS_348
BD36
VSS_349
CF11
VSS_350
V3
VSS_351
BE10
VSS_352
CF14
VSS_353
V30
VSS_354
BE28
VSS_355
CF19
VSS_356
V33
VSS_357
BE29
VSS_358
CF2
VSS_359
V36
VSS_360
BE3
VSS_361
19 of 20
*CFL_U_43E_IL_IP_DDR4
VSS_362
VSS_363
VSS_364
VSS_365
VSS_366
VSS_367
VSS_368
VSS_369
VSS_370
VSS_371
VSS_372
VSS_373
VSS_374
VSS_375
VSS_376
VSS_377
VSS_378
VSS_379
VSS_380
VSS_381
VSS_382
VSS_383
VSS_384
VSS_385
VSS_386
VSS_387
VSS_388
VSS_389
VSS_390
VSS_391
VSS_392
VSS_393
VSS_394
VSS_395
VSS_396
VSS_397
VSS_398
VSS_399
VSS_400
VSS_401
VSS_402
VSS_403
VSS_404
VSS_405
VSS_406
VSS_407
VSS_408
VSS_409
VSS_410
VSS_411
VSS_412
VSS_413
VSS_414
VSS_415
VSS_416
VSS_417
VSS_418
VSS_419
VSS_420
VSS_421
VSS_422
VSS_423
VSS_424
VSS_425
VSS_426
VSS_427
VSS_428
VSS_429
VSS_430
VSS_431
VSS_432
VSS_433
CF23
V4
BE30
CF28
W10
BE31
CF3
W27
CF4
W30
BF3
CG33
W7
BF33
CG7
BF36
Y26
BF4
CH31
Y27
BG25
Y30
BG28
CJ11
Y33
CJ14
Y35
BH28
CJ19
Y7
BH29
CJ23
BH32
CJ28
BH33
CJ33
BH35
CJ35
BP19
BR16
BY18
BY19
CC16
BU16
CC14
BR22
BU20
CD20
BT14
BP12
CB24
CC24
J5
U24
BD7
AR4
AU4
AW4
BA6
BC4
BE4
BE8
BA4
BD4
BG4
CJ2
CJ3
AM5
CM4
AC5
AG5
CR6
?
U30015R
CR34
VSS_1
BT5
VSS_2
BY5
VSS_3
CP35
VSS_4
CM37
VSS_5
CK37
VSS_6
AW1
VSS_7
CM1
VSS_8
BD6
VSS_9
AY4
VSS_10
B34
VSS_11
E35
VSS_12
A4
VSS_13
AE24
VSS_14
AE26
VSS_15
AF25
VSS_16
AG24
VSS_17
AG26
VSS_18
AH24
VSS_19
AH25
VSS_20
B2
VSS_21
B36
VSS_22
C36
VSS_23
C37
VSS_24
CN1
VSS_25
CN2
VSS_26
CN37
VSS_27
CP2
VSS_28
D1
VSS_29
A32
VSS_30
F33
VSS_31
A3
VSS_32
BJ7
VSS_33
CJ36
VSS_34
A36
VSS_35
BK10
VSS_36
CJ4
VSS_37
AB27
VSS_38
BK2
VSS_39
CK1
VSS_40
AB3
VSS_41
BK28
VSS_42
AB30
VSS_43
BK3
VSS_44
CK4
VSS_45
AB33
VSS_46
BK33
VSS_47
CK7
VSS_48
AB36
VSS_49
BK4
VSS_50
CL2
VSS_51
AB4
VSS_52
BK7
VSS_53
CM13
VSS_54
AB7
VSS_55
BL25
VSS_56
CM17
VSS_57
AC10
VSS_58
BL28
VSS_59
CM21
VSS_60
AC27
VSS_61
BL29
VSS_62
CM25
VSS_63
AC30
VSS_64
BL30
VSS_65
CM29
VSS_66
BL31
VSS_67
CM31
VSS_68
AD33
VSS_69
BL32
VSS_70
CM33
VSS_71
AD35
VSS_72
*CFL_U_43E_IL_IP_DDR4
17 of 20
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
BL7
AE25
BM33
CM5
AE27
BM35
CM9
AE30
BM36
CN13
AE7
BM9
CN17
AF27
BN30
CN21
AF3
BN7
CN25
AF30
CN29
AF33
BP15
AF36
AF4
CN5
AF7
BP25
CN9
AG10
BP3
CP1
BP32
CP11
AH27
BP33
CP13
AH28
BP4
CP15
AH29
BP7
CP19
AH30
CP21
AH31
BR19
CP27
AH33
BR25
AH35
CP37
AJ25
BT15
AJ28
BT16
CP9
AJ7
CR2
AK3
CR36
AK33
D21
AK36
BT25
D25
AK4
BT28
AL28
BT33
D5
AL29
?
U30015S
BT35
VSS_145
D6
VSS_146
AL32
VSS_147
BT36
VSS_148
D8
VSS_149
AL7
VSS_150
D9
VSS_151
AM10
VSS_152
BU11
VSS_153
E23
VSS_154
AM28
VSS_155
E27
VSS_156
AM33
VSS_157
BU23
VSS_158
E29
VSS_159
AM35
VSS_160
BU24
VSS_161
E31
VSS_162
BU25
VSS_163
E33
VSS_164
AN25
VSS_165
BU7
VSS_166
E9
VSS_167
AN28
VSS_168
BV11
VSS_169
F12
VSS_170
AN29
VSS_171
F15
VSS_172
AN30
VSS_173
F18
VSS_174
AN31
VSS_175
BV3
VSS_176
F2
VSS_177
AN7
VSS_178
BV31
VSS_179
F21
VSS_180
AN8
VSS_181
BV33
VSS_182
F24
VSS_183
BV4
VSS_184
F3
VSS_185
AP3
VSS_186
BW11
VSS_187
F4
VSS_188
AP33
VSS_189
BW15
VSS_190
G21
VSS_191
AP36
VSS_192
G27
VSS_193
AP4
VSS_194
G33
VSS_195
AR28
VSS_196
G35
VSS_197
G36
VSS_198
AT33
VSS_199
BW24
VSS_200
G9
VSS_201
AT35
VSS_202
H21
VSS_203
AT36
VSS_204
BW7
VSS_205
H27
VSS_206
AT4
VSS_207
BY11
VSS_208
AU10
VSS_209
BY15
VSS_210
H9
VSS_211
AU28
VSS_212
BY22
VSS_213
J12
VSS_214
AU29
VSS_215
J15
VSS_216
*CFL_U_43E_IL_IP_DDR4
18 of 20
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
BOM
BY25
J18
AU32
BY28
J21
AV25
BY33
J24
AV28
BY35
J33
AV3
BY36
J36
AV33
J6
AV36
C1
K21
AV4
C21
K22
AV6
C25
K24
AV8
C29
K25
AW28
C33
K27
AW29
C4
K28
AW3
C9
K29
AW30
CA11
K3
AW31
CA15
K30
AY33
CA22
K31
AY35
K32
B12
K4
B15
CA25
K9
B18
CB11
L27
B21
L33
B23
L35
B25
CB18
L36
B27
CB19
L6
B29
CB2
N25
B31
CB20
N27
CB25
A A
PROJECT : G7BD
PROJECT : G7BD
PROJECT : G7BD
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
KBL-U 7/15 (GND)
KBL-U 7/15 (GND)
KBL-U 7/15 (GND)
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
1
8 49Wednesday, December 26, 2018
8 49Wednesday, December 26, 2018
8 49Wednesday, December 26, 2018
1A
1A
1A
5
4
3
2
1
+1.05V_DEEP_SUS <15,33,40,41>
?
09
U30015Q
CFG0<16>
CFG1<16>
CFG2<16>
CFG3<16>
D D
+1.05V_DEEP_SUS
C C
B B
CFG4<16>
CFG5<16>
CFG6<16>
CFG7<16>
CFG8<16>
CFG9<16>
CFG10<16>
CFG11<16>
CFG12<16>
CFG13<16>
CFG14<16>
CFG15<16>
CFG16<16>
CFG18<16>
CFG17<16>
CFG19<16>
R30223 49.9_1%_4
R30270 *1K_4
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG18
CFG17
CFG19
CFG_RCOMP
T4
CFG_0
R4
CFG_1
T3
CFG_2
R3
CFG_3
J4
CFG_4
M4
CFG_5
J3
CFG_6
M3
CFG_7
R2
CFG_8
N2
CFG_9
R1
CFG_10
N1
CFG_11
J2
CFG_12
L2
CFG_13
J1
CFG_14
L1
CFG_15
L3
CFG_16
N3
CFG_18
L4
CFG_17
N4
CFG_19
AB5
CFG_RCOMP
W4
ITP_PMODE
CG2
RSVD25
CG1
RSVD24
H4
RSVD34
H3
RSVD33
BV24
RSVD22
BV25
RSVD23
G3
VSS_436
G4
VSS_437
BK36
RSVD17
BK35
RSVD16
W3
RSVD35
AM4
RSVD7
AM3
RSVD6
A35
RSVD1
D34
RSVD30
G2
RSVD32
G1
RSVD31
*CFL_U_43E_IL_IP_DDR4
BOM
20 of 20
RSVD_TP5
RSVD_TP4
IST_TRIG
RSVD_TP3
RSVD15
RSVD14
RSVD21
RSVD20
RSVD18
RSVD19
RSVD29
RSVD26
RSVD27
RSVD12
RSVD13
RSVD8
RSVD9
RSVD11
RSVD10
RSVD3
RSVD2
RSVD5
RSVD4
VSS
VSS_435
RSVD_TP1
RSVD_TP2
RSVD28
ZVM#
MSM#
SKTOCC#
TP4
TP3
TP1
TP2
F37
F34
CP36
CN36
BJ36
BJ34
BK34
BR18
BT9
BT8
BP8
BP9
CR4
CP3
CR3
AT3
AU3
AN1
AN2
AN4
AN3
AL2
AL1
AL4
AL3
BP34
BP36
BP35
C34
A34
B35
CR35
AH26
AJ27
E1
R30386 0_4
R30263 *0_4
Processor Strapping
CFG3
(Physcial Debug Enable)
DFX Privacy
CFG4
(DP Presence Strap)
A A
5
The CFG signals have a default value of '1' if not terminated on the board.
1 0
Disable: Enable: Set DFX Enable in DFX interface MSR
Disable; No physical DP attached to eDP
4
Enable; An ext DP device is connected to eDP
3
CFG3
CFG4
Circuit
R30246 *1K_4
R30264 1K_5%_4
PROJECT : G7BD
PROJECT : G7BD
PROJECT : G7BD
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
KBL-U 8/15 (RSV)
KBL-U 8/15 (RSV)
KBL-U 8/15 (RSV)
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
1
9 49Wednesday, December 26, 2018
9 49Wednesday, December 26, 2018
9 49Wednesday, December 26, 2018
1A
1A
1A
5
+3V_DEEP_SUS <4,11,13,14,15,16,32>
+3V <4,11,12,13,14,15,17,18,22,25,26,27,28,29,31,32,33,34,35,42,45,46,47>
+5V <25,26,27,31,32,33,45>
+1.05V <2,6,35,41>
+3VS5 <4,12,13,15,29,32,33,34,35,38,39,40,41,45,48>
D D
C C
PCH_SPI1_CLK<32>
PCH_SPI1_SO<32>
PCH_SPI1_SI<16,32>
PCH_SPI_IO2<16>
SPI_TPM_CS#<32>
SIO_EXT_SMI#<35>
TPM_PIRQ#<32>
EC_RCIN#<35>
4
R124572 100K_1%_4
PCH_SPI1_CLK
PCH_SPI1_SO
PCH_SPI1_SI
PCH_SPI_IO2
PCH_SPI_IO3
PCH_SPI_CS0#
SPI_TPM_CS#
SPI1_CLK
TP30013
SIO_EXT_SMI#
TPM_PIRQ#
SPI1_IO2
SPI1_IO3
TP30015
SPI1_CS#
TP30014
TP30012
SERIRQ<32,35>
U30015E
CH37
SPI0_CLK
CF37
SPI0_MISO
CF36
SPI0_MOSI
CF34
SPI0_IO2
CG34
SPI0_IO3
CG36
SPI0_CS0#
CG35
SPI0_CS1#
CH34
SPI0_CS2#
CF20
GPP_D1/SPI1_CLK/BK1/SBK1
CG22
GPP_D2/SPI1_MISO_IO1/BK2/SBK2
CF22
GPP_D3/SPI1_MOSI_IO0/BK3/SBK3
CG23
GPP_D21/SPI1_IO2
CH23
GPP_D22/SPI1_IO3
CG20
GPP_D0/SPI1_CS0#/BK0/SBK0
CH7
CL_CLK
CH8
CL_DATA
CH9
CL_RST#
BV29
GPP_A0/RCIN#/TIME_SYNC1
BV28
GPP_A6/SERIRQ
*CFL_U_43E_IL_IP_DDR4
3
GPP_C5/SML0ALERT#
GPP_B23/SML1ALERT#/PCHHOT#
5
GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3
GPP_A5/LFRAME#/ESPI_CS#
GPP_A14/SUS_STAT#/ESPI_RESET#
GPP_A9/CLKOUT_LPC0/ESPI_CLK
GPP_A10/CLKOUT_LPC1
5 of 20
PDC
GPP_C0/SMBCLK
GPP_C1/SMBDATA
GPP_C2/SMBALERT#
GPP_C3/SML0CLK
GPP_C4/SML0DATA
GPP_C6/SML1CLK
GPP_C7/SML1DATA
GPP_A8/CLKRUN#
CK14
CH15
CJ15
CH14
CF15
CG15
CN15
CM15
CC34
CA29
BY29
BY27
BV27
CA28
CA27
BV32
BV30
BY30
SMB_PCH_CLK
SMB_PCH_DAT
SML0ALERT#
SMB_ME0_CLK
SMB_ME0_DAT
SML1ALERT#
SMB_ME1_CLK
SMB_ME1_DAT
GPP_B23
SUS_STAT#
CLK_PCI_EC_R
CLK_PCI_LPC_R
CLKRUN#
SML0ALERT# <11>
SML1ALERT# <11>
LAD0 <32,34,35>
LAD1 <32,34,35>
LAD2 <32,34,35>
LAD3 <32,34,35>
LFRAME# <32,34,35>
TP30086
CLKRUN# <35>
R30123 22/F_4
2
R30121 22_1%_4
R30122 22_1%_4
EC30031 18p/50V_4
EC30030
EC30032
18P/50V_4
18p/50V_4
CLK_24M_KBC <35>
CLK_24M_DEBUG <34>
CLK_PCI_TPM <32>
EMI(near PCH)
+3V_DEEP_SUS
GPP_B23
2/3 add for HW STRAP
EMI(near PCH)
1
R124556
4.7K_5%_4
EXI BOOT STALL BYPASS
HIGH->ENABLE
LOW->DISABLE
WEAK INTERNAL PD
R124557
*20K_1%_4
10
GPIO Pull UP
+3V +3V_DEEP_SUS
SERIRQ
CLKRUN#
SIO_EXT_SMI#
EC_RCIN#
TPM_PIRQ#
B B
R30106 10K_5%_4
R30109 8.2K_5%_4
R30108 10K_5%_4
R30344 10K_5%_4
SMB_PCH_CLK
SMB_PCH_DAT
SMB_ME0_CLK
SMB_ME0_DAT
SMB_ME1_CLK
SMB_ME1_DAT
ACC_LED#<14,33>
R30308 2.2K_5%_4
R30313 2.2K_5%_4
R30316 1K_5%_4R30345 10K_5%_4
R30320 1K_5%_4
R30304 1K_5%_4
R30301 1K_5%_4
R30358 10K_5%_4
SMBus/Pull-up(CLG)
CPU heat pipe local thermal sensor
DDR thermal sensor
EC
+3V
R30306 4.7K_5%_4
A A
+3V
SMB_RUN_DAT<16,17,18,31>
R30307 4.7K_5%_4
+3V
SMB_RUN_CLK<16,17,18,31>
5
5
Q30017A 2N7002KDW
2
Q30017B 2N7002KDW
34
61
SMB_PCH_DAT
SMB_PCH_CLK
Touch Pad
XDP
DDR4
4
PCH SPI ROM(CLG)
Vender P/N
MXIC
Winbond
GigaDevice
Socket
3
Size
AKE3DZN0Z03 (MX25L12873FM2I-10G)16MB
16MB
AKE3DF-KN01 (W25Q128JVSIQ)
16MB
AKE3DZN0Q02 (GD25B127DSIGR)
DG008000011
PCH_SPI_CS0#_R<35>
PCH_SPI1_CLK_R<35>
PCH_SPI1_SI_R<35>
PCH_SPI1_SO_R<35>
PCH_SPI_CS0#
PCH_SPI1_SO
PCH_SPI_IO2
C30515 1u/6.3V_4
+3VSPI
P/N DG008000011 (Socket)
PCH_SPI_CS0#_R
PCH_SPI1_CLK_R
PCH_SPI1_SI_R
PCH_SPI1_SO_R
R30444 15_1%_4
R30443 33.2_1%_4
R30441 15_1%_4
R30442 100K_1%_4
PCH_SPI_CS0#_R
PCH_SPI1_SO_R
BIOS_WP#
PCH SPI ROM(CLG)
U30023
2
1
CS
2
IO1/DO
3
IO2/WP
4
GND
W25Q64FVSSIQ
VCC
IO3/HOLD
CLK
IO0/DI
8
7
HOLD#
PCH_SPI1_CLK_R
6
PCH_SPI1_SI_R
5
C30471
*22p/50V_4
need place to TOP
TP30037
TP30033
TP30032
TP30036
TP30035
TP30034
PCH_SPI_CS0#_R
PCH_SPI1_CLK_R
PCH_SPI1_SI_R
PCH_SPI1_SO_R
BIOS_WP#
HOLD#
TP size TP2675
+3V_DEEP_SUS
+3VSPI
R30429 100K_1%_4
R30428 15_1%_4
R30427 33.2_1%_4
R30431 33.2_1%_4
PROJECT : G7BD
PROJECT : G7BD
PROJECT : G7BD
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
PCH_SPI_IO3
PCH_SPI1_CLK
PCH_SPI1_SI
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
KBL-U 09/15(SPI/LPC/SM)
KBL-U 09/15(SPI/LPC/SM)
KBL-U 09/15(SPI/LPC/SM)
1
+3VSPI
C30475
0.1u/16V_4
1A
1A
10 49Wednesday, December 26, 2018
10 49Wednesday, December 26, 2018
10 49Wednesday, December 26, 2018
1A
5
4
3
2
1
11
D D
DESIGN NOTE:
WEAK PULL UP RESISTOR PRESENT ON THIS NET
ACZ_SPKR<14,26>
C C
B B
GSPI1_MOSI<14>
ACZ_SPKR
SML0ALERT#
GSPI1_MOSI
R30379
*20K/F_4
+3V_DEEP_SUS
R30319
1K_5%_4
R30318
*20K/F_4
R30124
*20K/F_4
Functional Strap Definitions
TOP SWAP OVERRIDE
HIGH - TOP SWAP ENABLE
LOW-DISABLED
HIGH: LPC SELECTED FOR SYSTEM FLASH
WEAK INTERNAL PD
No Boot:
The signal has a weak internal pull-down.
0 = Disable Intel ME Crypto Transport Layer Security
(TLS) cipher suite (no confidentiality).
1 = Enable Intel ME Crypto Transport Layer Security
(TLS) cipher suite (with confidentiality). Must be
pulled up to support Intel AMT with TLS and Intel
SBA (Small Business Advantage) with TLS.
No Boot:
The signal has a weak internal pull-down.
This field determines the destination of accesses to the
BIOS memory range. Also controllable using Boot BIOS
Destination bit (Chipset Configuration Registers: Offset
3410h:Bit 10). This strap is used in conjunction with Boot
BIOS Destination Selection 0 strap.
Bit 10 Boot BIOS Destination
0 SPI
1 LPC
ACZ_SDOUT<14>
GPIO33_EC<35>
GPP_B18<14>SML0ALERT#<10>
SML1ALERT#<10>
ACZ_SDOUT
R30397 1K_5%_4
GPP_B18
+3V_DEEP_SUS
SML1ALERT#
+3V_DEEP_SUS
R30384
*4.7K_4
ACZ_SDOUT
+3V
R30343
*4.7K_4
R30347
10K_5%_4
R30323
*10K_4
R30322
20K_1%_4
No Boot:
The signal has a weak internal pull-down.
0 = Enable security measures defined in the Flash
Descriptor.
1 = Disable Flash Descriptor Security (override). This
strap should only be asserted high using external
pull-up in manufacturing/debug environments ONLY.
This function is useful when running ITP/XDP.
No Boot:
The signal has a weak internal pull-down.
0 = Disable No Reboot mode.
1 = Enable No Reboot mode
(PCH will disable the TCO
Timer system reboot feature).
This function is useful when running ITP/XDP.
No Boot:
The signal has a weak internal pull-down.
0 = LPC Is selected for EC.
1 = eSPI Is selected for EC.
A A
PROJECT : G7BD
PROJECT : G7BD
PROJECT : G7BD
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
KBL-U 10/15(HDA)
KBL-U 10/15(HDA)
KBL-U 10/15(HDA)
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
1
11 49Wednesday, December 26, 2018
11 49Wednesday, December 26, 2018
11 49Wednesday, December 26, 2018
1A
1A
1A
5
+3V <4,10,11,13,14,15,17,18,22,25,26,27,28,29,31,32,33,34,35,42,45,46,47>
+3VS5 <4,13,15,29,32,33,34,35,38,39,40,41,45,48>
+3V_DEEP_SUS <4,10,11,13,14,15,16,32>
dGPU
dGPU
D D
WLAN
LAN
HDD
SATA/PCIE
C C
SSD
B B
A A
PEG_RXN1<19>
PEG_RXP1<19>
PEG_TXN1<19>
PEG_TXP1<19>
PEG_RXN2<19>
PEG_RXP2<19>
PEG_TXN2<19>
PEG_TXP2<19>
PEG_RXN3<19>
PEG_RXP3<19>
PEG_TXN3<19>
PEG_TXP3<19>
PEG_RXN4<19>
PEG_RXP4<19>
PEG_TXN4<19>
PEG_TXP4<19>
PCIE_RXN5_WLAN<34>
PCIE_RXP5_WLAN<34>
PCIE_TXN5_WLAN<34>
PCIE_TXP5_WLAN<34>
PCIE_RXN6_LAN<28>
PCIE_RXP6_LAN<28>
PCIE_TXN6_LAN<28>
PCIE_TXP6_LAN<28>
SATA_RXN0<33>
SATA_RXP0<33>
SATA_TXN0<33>
SATA_TXP0<33>
SATA_RXN1A<34>
SATA_RXP1A<34>
SATA_TXN1A<34>
SATA_TXP1A<34>
PCIE_RXN9<34>
PCIE_RXP9<34>
PCIE_TXN9<34>
PCIE_TXP9<34>
PCIE_RXN10<34>
PCIE_RXP10<34>
PCIE_TXN10<34>
PCIE_TXP10<34>
PCIE_RXN11<34>
PCIE_RXP11<34>
PCIE_TXN11<34>
PCIE_TXP11<34>
SATA_RXN2<34>
SATA_RXP2<34>
SATA_TXN2<34>
SATA_TXP2<34>
5
C4178 0.22u/10V_4
C4179 0.22u/10V_4
C4180 0.22u/10V_4
C4181 0.22u/10V_4
C4182 0.22u/10V_4
C4183 0.22u/10V_4
C4184 0.22u/10V_4
C4185 0.22u/10V_4
C4186 0.1u/16V_4
C4187 0.1u/16V_4
C4188 0.1u/16V_4
C4189 0.1u/16V_4
PEG_TXN1_C
PEG_TXP1_C
PEG_TXN2_C
PEG_TXP2_C
PEG_TXN3_C
PEG_TXP3_C
PEG_TXN4_C
PEG_TXP4_C
PCIE_TXN5_WLAN_C
PCIE_TXP5_WLAN_C
PCIE_TXN6_LAN_C
PCIE_TXP6_LAN_C
R30277 100_1%_4
4
?
U30015H
BW9
PCIE5_RXN/USB31_5_RXN
BW8
PCIE5_RXP/USB31_5_RXP
BW4
PCIE5_TXN/USB31_5_TXN
BW3
PCIE5_TXP/USB31_5_TXP
BU6
PCIE6_RXN/USB31_6_RXN
BU5
PCIE6_RXP/USB31_6_RXP
BU4
PCIE6_TXN/USB31_6_TXN
BU3
PCIE6_TXP/USB31_6_TXP
BT7
PCIE7_RXN
BT6
PCIE7_RXP
BU2
PCIE7_TXN
BU1
PCIE7_TXP
BU9
PCIE8_RXN
BU8
PCIE8_RXP
BT4
PCIE8_TXN
BT3
PCIE8_TXP
BP5
PCIE9_RXN
BP6
PCIE9_RXP
BR2
PCIE9_TXN
BR1
PCIE9_TXP
BN6
PCIE10_RXN
BN5
PCIE10_RXP
BR4
PCIE10_TXN
BR3
PCIE10_TXP
BN10
PCIE11_RXN/SATA0_RXN
BN8
PCIE11_RXP/SATA0_RXP
BN4
PCIE11_TXN/SATA0_TXN
BN3
PCIE11_TXP/SATA0_TXP
BL6
PCIE12_RXN/SATA1A_RXN
BL5
PCIE12_RXP/SATA1A_RXP
BN2
PCIE12_TXN/SATA1A_TXN
BN1
PCIE12_TXP/SATA1A_TXP
BK6
PCIE13_RXN
BK5
PCIE13_RXP
BM4
PCIE13_TXN
BM3
PCIE13_TXP
BJ6
PCIE14_RXN
BJ5
PCIE14_RXP
BL2
PCIE14_TXN
BL1
PCIE14_TXP
BG5
PCIE15_RXN/SATA1B_RXN
BG6
PCIE15_RXP/SATA1B_RXP
BL4
PCIE15_TXN/SATA1B_TXN
BL3
PCIE15_TXP/SATA1B_TXP
BE5
PCIE16_RXN/SATA2_RXN
BE6
PCIE16_RXP/SATA2_RXP
BJ4
PCIE16_TXN/SATA2_TXN
BJ3
PCIE16_TXP/SATA2_TXP
CE6
PCIE_RCOMP
CE5
PCIE_RCOMP_P
CR28
GPP_H12/M2_SKT2/CFG_0
CP28
GPP_H13/M2_SKT2/CFG_1
CN28
GPP_H14/M2_SKT2/CFG_2
CM28
GPP_H15/M2_SKT2/CFG_3
*CFL_U_43E_IL_IP_DDR4
PCI-E Port Mapping Table
PCI-E Port
Port5
Port6
Port7
Port8
Port9
Port10
Port11
Port12
Port13
Port14
Port15
Port16
Function
dGPU
dGPU
dGPU
dGPU
WLAN
LAN
HDD
ODD
PCIE SSDx4
PCIE SSDx4
PCIE SSDx4
PCIE SSDx4
/SATA SSD
4
PCIE2_RXN/USB31_2_RXN/SSIC_1_RXN
PCIE2_RXP/USB31_2_RXP/SSIC_1_RXP
PCIE2_TXN/USB31_2_TXN/SSIC_1_TXN
PCIE2_TXP/USB31_2_TXP/SSIC_1_TXP
GPP_E9/USB2_OC0#/GP_BSSB_CLK
GPP_E10/USB2_OC1#/GP_BSSB_DI
PDC
8 of 20
CLK RQ Port
Port0
Port1
Port2
Port3
Port4
Port5
PCIE1_RXN/USB31_1_RXN
PCIE1_RXP/USB31_1_RXP
PCIE1_TXN/USB31_1_TXN
PCIE1_TXP/USB31_1_TXP
PCIE3_RXN/USB31_3_RXN
PCIE3_RXP/USB31_3_RXP
PCIE3_TXN/USB31_3_TXN
PCIE3_TXP/USB31_3_TXP
PCIE4_RXN/USB31_4_RXN
PCIE4_RXP/USB31_4_RXP
PCIE4_TXN/USB31_4_TXN
PCIE4_TXP/USB31_4_TXP
GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2
GPP_E8/SATALED#/SPI1_CS1#
USB2_1N
USB2_1P
USB2_2N
USB2_2P
USB2_3N
USB2_3P
USB2_4N
USB2_4P
USB2_5N
USB2_5P
USB2_6N
USB2_6P
USB2_7N
USB2_7P
USB2_8N
USB2_8P
USB2_9N
USB2_9P
USB2_10N
USB2_10P
USB2_COMP
USB2_ID
USB2_VBUSSENSE
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#
GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2
UFS_RESET#
Function
VGA
CR
SSD
WLAN
LAN
Un-used
3
CB5
CB6
CA4
CA3
BY8
BY9
CA2
CA1
BY7
BY6
BY4
BY3
BW6
BW5
BW2
BW1
CE3
CE4
CE1
CE2
CG3
CG4
CD3
CD4
CG5
CG6
CC1
CC2
CG8
CG9
CB8
CB9
CH5
CH6
CC3
CC4
CC5
CE8
CC6
CK6
CK5
CK8
CK9
CP8
CR8
CM8
CN8
CM10
CP10
CN7
AR3
USB30_RX1USB30_RX1+
USB30_TX1USB30_TX1+
USB30_RX2USB30_RX2+
USB30_TX2USB30_TX2+
USB30_RX3USB30_RX3+
USB30_TX3USB30_TX3+
USBP1USBP1+
USBP2USBP2+
USBP3_CAMUSBP3_CAM+
USBP4USBP4+
USBP5_IRUSBP5_IR+
USBP6USBP6+
USBP7_FPUSBP7_FP+
USBP8_TSUSBP8_TS+
USBP10USBP10+
USB2_COMP
USB2_ID
USB2_VBUSSENSE
GPPC_E9
DGPU_HOLD_RST#
DGPU_PWR_EN
DGPU_PWROK
GC6_FB_EN_Q
DEVSLP0
GPU_EVENT#
ODD_PRSNT#_R
SATAGP1
GPIO35_R
SATA_LED#_R
USB30_RX1- <29>
USB30_RX1+ <29>
USB30_TX1- <29>
USB30_TX1+ <29>
USB30_RX2- <29>
USB30_RX2+ <29>
USB30_TX2- <29>
USB30_TX2+ <29>
USB30_RX3- <30>
USB30_RX3+ <30>
USB30_TX3- <30>
USB30_TX3+ <30>
USBP1- <29>
USBP1+ <29>
USBP2- <29>
USBP2+ <29>
USBP3_CAM- <25>
USBP3_CAM+ <25>
USBP4- <30>
USBP4+ <30>
USBP5_IR- <25>
USBP5_IR+ <25>
USBP6- <29>
USBP6+ <29>
USBP7_FP- <33>
USBP7_FP+ <33>
USBP8_TS- <25>
USBP8_TS+ <25>
USBP10- <34>
R30261 113_1%_4
R30255 1K_5%_4
R30262 1K_5%_4
R30291 *0_4/S
R30283 *0_4/S
USBP10+ <34>
DGPU_HOLD_RST# <19>
DGPU_PWR_EN <20,22>
DGPU_PWROK <35>
GC6_FB_EN_Q <22>
DEVSLP0 <34>
GPU_EVENT# <22>
SATA_LED#
GPIO35 <34>
USB3.0 Port Mapping Table
USB3.0 Function
PORT-1
PORT-2
PORT-3
PORT-4
SATAGP1:GPP_E1 - SATA#1/PCIE#8
SATA => High < Base U>
PCIE => Low
3
USB3.0 Small Board Cobime USB3.0 Small Board
USB3.0 Small Board
Type C
NC
SATAGP1
2
USB3.0 Small Board
DB 1SPD TypeA UP
USB3.0 Small Board
DB 1SPD TypeA DN
GPPC_E9
MB Type C#1a
2/3 add for HW STRAP
Combo USB3.0 Small Board UP
Combo USB3.0 Small Board DN
Camera
Type C
IR CAM
CR
Finger print
Touch Screen
BT
PLACE 'Ra' WITHIN 500 MILS
FROM USB2_COMP PIN WITH
TRACE IMPEDANCE LESS THAN 0.5 OHMS
If OTG is not implemented on the platform,
then USB2_ID and USB2_VBUSSENSE should both
be connected to ground.
SATA_LED# <33,34>
GPIO35:
SSD SATA IF => High
SSD PCIE IF => Low
USB2.0 Port Mapping Table
USB2.0 Function
PORT-1
Cobime USB3.0 Small Board
Camera
Type C
IR CAM
Card reader
NC
NC
NC
+3V
R30282
10K_5%_4
R30284
*10K_5%_4
2
PORT-2
PORT-3
PORT-4
PORT-5
PORT-6
PORT-7
PORT-8
PORT-9
PORT-10 BT
1
+3VS5
R124559
10K_5%_4
RING OSCILLATOR BYPASS
HIGH :BYPASS MODE ENABLED
LOW: RING OSCILLATOR
(QUALIFIED BY DFXTESTMODE)
NO INTERNAL PU/PD
R124558
*20K_1%_4
+3V
DGPU_PWR_EN
DGPU_PWROK
GC6_FB_EN_Q
GPU_EVENT#
SATA_LED#
ODD_PRSNT#_R
GPIO35
DGPU_HOLD_RST#
R4113 10K_5%_4
R4114 10K_5%_4
R127 10K_5%_4
R122 *10K_5%_4
R4115 10K_5%_4
R124591 10K_5%_4
R4117 10K_5%_4
R4118 100K_5%_4
PROJECT : G7BD
PROJECT : G7BD
PROJECT : G7BD
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
KBL-U 11/15 (PCIE/USB)
KBL-U 11/15 (PCIE/USB)
KBL-U 11/15 (PCIE/USB)
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
12
DIS ONLY
DIS ONLY
12 49Wednesday, December 26, 2018
12 49Wednesday, December 26, 2018
12 49Wednesday, December 26, 2018
1A
1A
1A
5
4
3
2
1
TP9080
TP9084
13
HW STRAP
HIGH-> 24MHz
+3VS5
+BAT_RTC <4,15,31,36,49>
+1.8V_DEEP_SUS <15,29,34,40,45,48>
+3V <4,10,11,12,14,15,17,18,22,25,26,27,28,29,31,32,33,34,35,42,45,46,47>
+3V_DEEP_SUS <4,10,11,14,15,16,32>
CNV_WR_LANE0_DN<34>
D D
VGA
WLAN
C C
CLK_VGA_N<19>
CLK_VGA_P<19>
PCIE_CLKREQ_VGA#<19>
CLK_PCIE_SSDN<34>
CLK_PCIE_SSDP<34>
PCIE_CLKREQ_SSD#<34>
CLK_PCIE_WLANN<34>
CLK_PCIE_WLANP<34>
PCIE_CLKREQ_WLAN#<34>
CLK_PCIE_LANN<28>
CLK_PCIE_LANP<28>
PCIE_CLKREQ_LAN#<28>
For C10
2/5 add for C10
CPU_C10_GATE# PWR_GATE#
R124567 *2.2K_5%_4
CLK_VGA_N
CLK_VGA_P
PCIE_CLKREQ_VGA#
PCIE_CLKREQ_CR#
CLK_PCIE_SSDN
CLK_PCIE_SSDP
PCIE_CLKREQ_SSD#
CLK_PCIE_WLANN
CLK_PCIE_WLANP
PCIE_CLKREQ_WLAN#
CLK_PCIE_LANN
CLK_PCIE_LANP
PCIE_CLKREQ_LAN#
PCIE_CLKREQ5#
+1.8V_DEEP_SUS +3V_DEEP_SUS
R124565
*100K_5%_4
?
U30015J
AW2
CLKOUT_PCIE_N_0
AY3
CLKOUT_PCIE_P_0
CF32
GPP_B5/SRCCLKREQ0#
BC1
CLKOUT_PCIE_N_1
BC2
CLKOUT_PCIE_P_1
CE32
GPP_B6/SRCCLKREQ1#
BD3
CLKOUT_PCIE_N_2
BC3
CLKOUT_PCIE_P_2
CF30
GPP_B7/SRCCLKREQ2#
BH3
CLKOUT_PCIE_N_3
BH4
CLKOUT_PCIE_P_3
CE31
GPP_B8/SRCCLKREQ3#
BA1
CLKOUT_PCIE_N_4
BA2
CLKOUT_PCIE_P_4
CE30
GPP_B9/SRCCLKREQ4#
BE1
CLKOUT_PCIE_N_5
BE2
CLKOUT_PCIE_P_5
CF31
GPP_B10/SRCCLKREQ5#
*CFL_U_43E_IL_IP_DDR4
+1.8V_DEEP_SUS
3
Q9078 *DMG1012T-7
2
1
R124597
0_4
10 of 20
R124566
100K_5%_4
CLKOUT_ITPXDP
CLKOUT_ITPXDP_P
GPD8/SUSCLK
XTAL_IN
XTAL_OUT
CLK_BIASREF
CLKIN_XTAL
RTCX1
RTCX2
SRTCRST#
RTCRST#
PWR_GATE# <41>
AU1
AU2
BT32
SUSCLK_32K <34>
XTAL24_IN
CK3
XTAL24_OUT
CK2
XCLK_BIASREF
CJ1
PULSAR_38P4M_REFCLK_R
CM3
RTC_X1
BN31
RTC_X2
BN32
SRTC_RST#
BR37
RTC_RST#
BR34
R30256 60.4/F_4
PULSAR_38P4M_REFCLK_R
R30273
10K_5%_4
GPD7
CK_XDP_N <16>
CK_XDP_P <16>
12
L30017
0_4
L < 5" 4.7pF
5" < L < 9" 2.2pF to 3.3pF
C30375
*2.2p/50V_4
9" < L < 10" 1pF to 2.2pF
Close to CPU
+3VS5
R124560
100K_5%_4
R124561
*20K_1%_4
XTAL INPUT MODE (HVM Only)
LOW: XTAL INPUT IS SINGLE ENDED
HIGH: XTAL IS ATTACHED
CNV_WR_LANE0_DP<34>
CNV_WR_LANE1_DN<34>
CNV_WR_LANE1_DP<34>
CNV_WT_LANE0_DN<34>
CNV_WT_LANE0_DP<34>
CNV_WT_LANE1_DN<34>
CNV_WT_LANE1_DP<34>
CNV_WR_CLK_DN<34>
CNV_WR_CLK_DP<34>
CNV_WT_CLK_DN<34>
CNV_WT_CLK_DP<34>
PULSAR_38P4M_REFCLK <34>
CNV_WT_RCOMP
CNV_WT_RCOMP
R124568
150_1%_4
GPP_F23
GPP_F23
?
U30015I
CR30
CNV_WR_D0N
CP30
CNV_WR_D0P
CM30
CNV_WR_D1N
CN30
CNV_WR_D1P
CN32
CNV_WT_D0N
CM32
CNV_WT_D0P
CP33
CNV_WT_D1N
CN33
CNV_WT_D1P
CN31
CNV_WR_CLKN
CP31
CNV_WR_CLKP
CP34
CNV_WT_CLKN
CN34
CNV_WT_CLKP
CP32
CNV_WT_RCOMP_0
CR32
CNV_WT_RCOMP_1
CP20
GPP_F0/CNV_PA_BLANKING
CK19
GPP_F1
CG17
GPP_F2
CR14
GPP_C8/UART0_RXD
CP14
GPP_C9/UART0_TXD
CN14
GPP_C10/UART0_RTS#
CM14
GPP_C11/UART0_CTS#
CJ17
GPP_F8/CNV_MFUART2_RXD
CH17
GPP_F9/CNV_MFUART2_TXD
CF17
GPP_F23/A4WP_PRESENT
*CFL_U_43E_IL_IP_DDR4
+1.8V_DEEP_SUS
R124562
*100K_5%_4
R124563
100K_5%_4
GPP_H18/CPU_C10_GATE#
GPP_H19/TIMESYNC_0
GPP_H21
GPP_H22
GPP_H23
GPP_F10
GPD7
GPP_D4/IMGCLKOUT0/BK4/SBK4
GPP_H20/IMGCLKOUT_1
GPP_F12/EMMC_DATA0
GPP_F13/EMMC_DATA1
GPP_F14/EMMC_DATA2
GPP_F15/EMMC_DATA3
GPP_F16/EMMC_DATA4
GPP_F17/EMMC_DATA5
GPP_F18/EMMC_DATA6
GPP_F19/EMMC_DATA7
GPP_F22/EMMC_RESET#
PDC
9 of 20
GPP_F3
GPP_F20/EMMC_RCLK
GPP_F21/EMMC_CLK
GPP_F11/EMMC_CMD
EMMC_RCOMP
CLK_REQ/Strap Pin(CLG)
PCIE_CLKREQ_VGA#
PCIE_CLKREQ_WLAN#
PCIE_CLKREQ_LAN#
PCIE_CLKREQ_CR#
PCIE_CLKREQ_SSD#
PCIE_CLKREQ5#
R30354 10K_5%_4
R30349 10K_5%_4
R30346 10K_5%_4
R30353 10K_5%_4
R30100 10K_5%_4
R30352 10K_5%_4
CN27
CM27
CF25
CN26
CM26
CK17
BV35
CN20
CG25
CH25
CR20
CM20
CN19
CM19
CN18
CR18
CP18
CM18
CM16
CP16
CR16
CN16
CK15
CPU_C10_GATE#
GPP_H21
GPP_H23
GPP_F10
GPD7
EMMC_RCOMP
+3V
R124552 4.7K_5%_4
R30317 200_1%_4
2/3 add for HW STRAP
B B
RTC Clock 32.768KHz
C30455 15p/50V_4
32.768KHZ/20ppm
C30454 15p/50V_4
A A
12
Y30001
5
RTC_X1
R30392
10M_5%_4
RTC_X2
RTC Circuitry(RTC)
RTC Power trace width 20mils.
+3VPCU
D30004 SDM20U30-7
1u/6.3V_4
+3VPCU
C30278
0.1u/16V_4
30mils
C30266
4
+BAT_RTC
R30145
20K_1%_4
R30142
20K_1%_4 Q30006A 2N7002KDW
RTC_RST#
R30125 *0_6
C30242
1u/6.3V_4
C30257
1u/6.3V_4
R30130 *0_6
RTC_RST#
SRTC_RST#
SRTC_RST#
Q30006B
5
2
2N7002KDW
3
34
61
R30163
10K_5%_4
RTC_RST#
R30172 *0_4
SRTC_RST#
R30173
10K_5%_4
2/3 add follow CRB
EC_RTC_RST <35>
EC_SRTC_RST <35>
External Crystal
The 24 MHz (50 Ohm ESR) XTAL used for Skylake-U
needs to be replaced by 38.4 MHz (30 Ohm ESR) XTAL
for Cannonlake-U.
C30367
27p/50V_4
1
XTAL24_IN
XTAL24_OUT
2
R30258 33.2_4
R30257 33.2_4
2
R30237
200K_1%_4
PROJECT : G7BD
PROJECT : G7BD
PROJECT : G7BD
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Y30000
24MHZ/20ppm
4
3
27p/50V_4
C30366
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
KBL-U 12/15 (CLK/EMMC)
KBL-U 12/15 (CLK/EMMC)
KBL-U 12/15 (CLK/EMMC)
1A
1A
13 49Wednesday, December 26, 2018
13 49Wednesday, December 26, 2018
1
13 49Wednesday, December 26, 2018
1A
5
+3V <4,10,11,12,13,15,17,18,22,25,26,27,28,29,31,32,33,34,35,42,45,46,47>
+3V_DEEP_SUS <4,10,11,13,15,16,32>
D D
CNVi_EN#
PCH_TEMPALERT#
SIO_EXT_SCI#
SPK_ID
PIRQA#
C C
ACCEL_INTA#
PCI_SERR#
R30401 *10K_4
R30327 10K_5%_4
R30295 10K_5%_4
R30321 10K_5%_4
R1601 10K_4
R30292 10K_5%_4
R30102 10K_5%_4
+3V_DEEP_SUS
+3V
CNV_RGI_DT
4
GPP_B18<11>
TP_INTH#_BIOS<31>
PCI_SERR#<35>
ACC_LED#<10,33>
GSPI1_MOSI<11>
CNV_BRI_RSP<34>
CNV_RGI_DT<34>
CNV_BRI_DT<34>
CNV_RGI_RSP<34>
ACCEL_INTA#<32>
SIO_EXT_SCI#<35>
TP_I2C_DATA<31>
TP_I2C_CLK<31>
M.2 CNVI MODES
LOW-> INTEGRATED CNVI ENABLE
HIGH-> INTEGRATED CNVI DISABLE
PIRQA#
GPP_B18
TP_INTH#_BIOS
PCI_SERR#
ACC_LED#
GSPI1_MOSI
UART2_RXD
UART2_TXD
ACCEL_INTA#
SIO_EXT_SCI#
TP_I2C_DATA
TP_I2C_CLK
3
?
U30015F
CC27
GPP_B15/GSPI0_CS0#
CC32
GPP_A7/PIRQA#/GSPI0_CS1#
CE28
GPP_B16/GSPI0_CLK
CE27
GPP_B17/GSPI0_MISO
CE29
GPP_B18/GSPI0_MOSI
CA31
GPP_B19/GSPI1_CS0#
CA32
GPP_A11/PME#/GSPI1_CS1#/SD_VDD2_PW R_EN#
CC29
GPP_B20/GSPI1_CLK
CC30
GPP_B21/GSPI1_MISO
CA30
GPP_B22/GSPI1_MOSI
CK20
GPP_F5/CNV_BRI_RSP
CG19
GPP_F6/CNV_RGI_DT
CJ20
GPP_F4/CNV_BRI_DT
CH19
GPP_F7/CNV_RGI_RSP
CR12
GPP_C20/UART2_RXD
CP12
GPP_C21/UART2_TXD
CN12
GPP_C22/UART2_RTS#
CM12
GPP_C23/UART2_CTS#
CM11
GPP_C16/I2C0_SDA
CN11
GPP_C17/I2C0_SCL
CK12
GPP_C18/I2C1_SDA
CJ12
GPP_C19/I2C1_SCL
CF27
GPP_H4/I2C2_SDA
CF29
GPP_H5/I2C2_SCL
CH27
GPP_H6/I2C3_SDA
CH28
GPP_H7/I2C3_SCL
CJ30
GPP_H8/I2C4_SDA
CJ31
GPP_H9/I2C4_SCL
*CFL_U_43E_IL_IP_DDR4
WHLake (GPIO)
GPP_D9/ISH_SPI_CS#/GSPI2_CS0#
GPP_D10/ISH_SPI_CLK/GSPI2_CLK
GPP_D11/ISH_SPI_MISO/GSPI2_MISO
GPP_D12/ISH_SPI_MOSI/GSPI2_MOSI
GPP_D5/ISH_I2C0_SDA
GPP_D6/ISH_I2C0_SCL
GPP_D7/ISH_I2C1_SDA
GPP_D8/ISH_I2C1_SCL
GPP_H10/I2C5_SDA/ISH_I2C2_SDA
GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA
GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL
GPP_A12/ISH_GP6/BM_BUSY#/SX_EXIT_HOLDOFF#
6 of 20
GPP_H11/I2C5_SCL/ISH_I2C2_SCL
GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#
GPP_D16/ISH_UART0_CTS#/SML0BALERT#
GPP_C12/UART1_RXD/ISH_UART1_RXD
GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
GPP_C15/UART1_CTS#/ISH_UART1_CTS#
GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5
2
1
14
CN22
CR22
CM22
CP22
CK22
CH20
CH22
CJ22
CJ27
CJ29
CM24
CN23
CM23
CR24
CG12
CH12
CF12
CG14
BW35
BW34
CA37
CA36
CA35
CA34
BW37
SPK_ID
GPP_D12
PCH_TEMPALERT#
R124599
*0_4/S
FP_LOCK_CN <33>
SPK_ID <26>
FP_SLEEP_CN <33>
Board ID 4
R124576
*4.7K_5%_4
Add cap for RF issue
ACZ_SDOUT_AUDIO
+3V_DEEP_SUS
Board ID6 default High,when device insert will become low
SI
BOARD_ID[3:1] BOARD_ID0
ID3
10014" (WHL)
10115" 1SPD (WHL)
1102SPD (WHL)
11113" (WHL)
000 : 14"
001 : 15 1SPD
010 : MAX-Q
011 : 2SPD
4
ACZ_RST#_AUDIO
ID0ID2 ID1ID4ID8 ID7
0UMA
1DIS
C30467
15p/50V_4
HDA Bus(CLG)
+3V_DEEP_SUS
ACZ_SYNC_AUDIO<26>
ACZ_RST#_AUDIO<26>
ACZ_SDOUT_AUDIO<26>
ACZ_SPKR
BIT_CLK_AUDIO<26>
15p/50V_4
?
U30015G
BN34
HDA_SYNC/I2S0_SFRM
BN37
HDA_BCLK/I2S0_SCLK
BN36
HDA_SDO/I2S0_TXD
BN35
HDA_SDI0/I2S0_RXD
BL36
HDA_SDI1/I2S1_RXD/SNDW1_DATA
BL35
HDA_RST#/I2S1_SCLK/SNDW1_CLK
CK23
GPP_D23/I2S_MCLK
BL37
I2S1_SFRM/SNDW 2_CLK
BL34
I2S1_TXD/SNDW2_DATA
CJ32
GPP_H1/I2S2_SFRM/CNV_BT_I2S_BCLK/CNV_RF_RESET#
CH32
GPP_H0/I2S2_SCLK/CNV_BT_I2S_SCLK
CH29
GPP_H2/I2S2_TXD/CNV_BT_I2S_SDI/MODEM_CLKREQ
CH30
GPP_H3/I2S2_RXD/CNV_BT_I2S_SDO
CP24
GPP_D19/DMIC_CLK0/SNDW4_CLK
CN24
GPP_D20/DMIC_DATA0/SNDW4_DATA
CK25
GPP_D17/DMIC_CLK1/SNDW3_CLK
CJ25
GPP_D18/DMIC_DATA1/SNDW3_DATA
CF35
GPP_B14/SPKR
*CFL_U_43E_IL_IP_DDR4
C30465
15p/50V_4
ACZ_SYNC
ACZ_BCLK
3
ACZ_SDOUT
ACZ_SDIN0
ACZ_RST#
CNV_RF_RESET#
MODEM_CLKREQ
ACZ_SDOUT<11>
ACZ_SDIN0<26>
CNV_RF_RESET#<34>
MODEM_CLKREQ<34>
ACZ_SPKR<11,26>
R30383 *1K_4
R30396 33_5%_4
R30420 33_5%_4
R30417 33_5%_4
R30385 33_5%_4R30364 *10K_4
C30451
ACZ_SYNC
ACZ_SYNC
ACZ_RST#
ACZ_SDOUT
ACZ_BCLK
GPP_A17/SD_VDD1_PW R_EN#/ISH_GP7
7 of 20
C30464
GPP_G0/SD_CMD
GPP_G1/SD3_DATA0
GPP_G2/SD3_DATA1
GPP_G3/SD3_DATA2
GPP_G4/SD_DATA3
GPP_G5/SD_CD#
GPP_G6/SD_CLK
GPP_A16/SD_1P8_SEL
2
GPP_G7/SD_W P
SD_1P8_RCOMP
SD_3P3_RCOMP
C30466
3p/50V_4
3p/50V_4
close to CPU/1004
ACZ_SDOUT
ACZ_RST#
ACZ_SDIN0
C30443
3p/50V_4
BOARD_ID0
CH36
BOARD_ID1
CL35
BOARD_ID2
CL36
BOARD_ID3
CM35
BOARD_ID4
CN35
BOARD_ID5
CH35
BOARD_ID6
CK36
BOARD_ID7
CK34
BOARD_ID8
BW36
BY31
CK33
CM34
2/23 add for CNVI_EN# need check with BIOS
CNVi_EN# <34>
R30099 200_1%_4
PROJECT : G7BD
PROJECT : G7BD
PROJECT : G7BD
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
KBL-U 13/15 (GPIO)
KBL-U 13/15 (GPIO)
KBL-U 13/15 (GPIO)
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
14 49Wednesday, December 26, 2018
14 49Wednesday, December 26, 2018
14 49Wednesday, December 26, 2018
1A
1A
1A
UART2_RXD
UART2_TXD
R30297 49.9K_1%_4
R30296 49.9K_1%_4
2/7 add for HW STRAP
R30393 *10K_4
R30368 10K_4 R30369 *10K_5%_4
R30362 *10K_5%_4
B B
WHL
R30360 10K_4
R30389 *10K_4
R30380 *10K_5%_4
R30376 10K_5%_4
R30415 10K_5%_4
BOARD_ID[8:7]
Model
Definition
A A
Reserve
(Default = 00)
0:Finger Print
1:Non-Finger Print
5
BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID3
BOARD_ID4
BOARD_ID5
BOARD_ID6
BOARD_ID7
BOARD_ID8
R30394 10K_5%_4
R30365 10K_5%_4
R30363 10K_4
R30361 *10K_5%_4
R30390 10K_5%_4
R30381 10K_4
R30377 *10K_4
R30416 *10K_4
Board ID 5Board ID 6
ID5ID6
0AMD
1Nvidia
GPU setting
02G VRAM
14G VRAM
5
+3V_DEEP_SUS<4,10,11,13,14,16,32>
+1.05V_DEEP_SUS<9,33,40,41>
+1.8V_DEEP_SUS<13,29,34,40,45,48>
+BAT_RTC<4,13,31,36,49>
+3VS5
+1.05V_DEEP_SUS
C30179 1u/6.3V_4
close BP20
+1.8V_DEEP_SUS
D D
+3V_DEEP_SUS
C30083 1u/6.3V_4
close CP17
C30099 1u/6.3V_4
C30097 0.1u/16V_4
close CP29
+1.05V_DEEP_SUS
C30180 1u/6.3V_4
close BV18
+1.05V_DEEP_SUS
C C
Need check WHL EMI need or not
because PDG not recommend
B B
close to CPU/1004
+V3.3DX_1.5DX_ADO
C30096
A A
C30054
*3p/50V_4
3p/50V_4
1 2
0_4
L30005 BLM15AG121SN1D
PCH Internal VRM
L30004
C30059
0.1u/16V_4
+1.05V_DEEP_SUS
+3VS5
+V3.3DX_1.5DX_ADO
+3V_DEEP_SUS
+1.05V_DEEP_SUS
+1.05V_DEEP_SUS
12
+VCCDSW_1.05V
+1.05V_DEEP_SUS
+1.05V_DEEP_SUS
C30066
3p/50V_4
+3V
close BT24
C30116 1u/6.3V_4
C99151 10u/6.3V_4
C30063 10u/6.3V_4
close BV12
C30055 1u/6.3V_4
close BV2
C30119 1u/6.3V_4
close BR24
C30082 1u/6.3V_4
C30080 1u/6.3V_4
+3V_DEEP_SUS
R124611
*0_4
R124612
0_4
*1U/6.3V_4
+1.05V_DEEP_SUS
C30056
C30185
*22U/6.3V_6
4
VCCPRIM_1P05
VCCPRIM_1P8
VCCPRIM_3P3
VCCPRIM_CORE
VCCAPLL_1.05V
VCCMPHYGTAON_1P05
VCCAMPHYPLL_1P05
VCCAPLL_1.05V
VCCDUSB_1P05
VCCDSW_GPIO
VCCHDA
VCCSPI
VCCPRIM_1P05
VCCMPHYGTAON_1P05
SLP_SUS_ON<35,40>
?
U30015P
BP20
VCCPRIM_1P051
BW16
VCCPRIM_1P059
BW18
VCCPRIM_1P0510
BW19
VCCPRIM_1P0511
BY16
VCCPRIM_1P0512
CA14
VCCPRIM_1P0514
CC15
VCCPRIM_1P81
CD15
VCCPRIM_1P84
CD16
VCCPRIM_1P85
CP17
VCCPRIM_1P88
CB22
VCCPRIM_3P34
CB23
VCCPRIM_3P35
CC22
VCCPRIM_3P36
CC23
VCCPRIM_3P37
CD22
VCCPRIM_3P38
CD23
VCCPRIM_3P39
CP29
VCCPRIM_3P310
BU15
VCCPRIM_CORE1
BU22
VCCPRIM_CORE2
BV15
VCCPRIM_CORE3
BV16
VCCPRIM_CORE4
BV18
VCCPRIM_CORE5
BV19
VCCPRIM_CORE6
BV20
VCCPRIM_CORE7
BV22
VCCPRIM_CORE8
BW20
VCCPRIM_CORE9
BW22
VCCPRIM_CORE10
CA12
VCCPRIM_CORE11
CA16
VCCPRIM_CORE12
CA18
VCCPRIM_CORE13
CA19
VCCPRIM_CORE14
CA20
VCCPRIM_CORE15
CB12
VCCPRIM_CORE16
CB14
VCCPRIM_CORE17
CB15
VCCPRIM_CORE18
BT24
VCCDSW_1P05
BU14
VCCAPLL_1P054
BV12
VCCPRIM_MPHY_1P051
BW12
VCCPRIM_MPHY_1P053
BW14
VCCPRIM_MPHY_1P054
BY12
VCCPRIM_MPHY_1P055
BY14
VCCPRIM_MPHY_1P056
BV2
VCCAMPHYPLL_1P05
BR15
VCCAPLL_1P052
CC12
VCCDUSB_1P05
BR24
VCCDSW_3P31
BT20
VCCHDA
BV23
VCCSPI
BT18
VCCPRIM_1P054
BT19
VCCPRIM_1P055
BU18
VCCPRIM_1P057
BU19
VCCPRIM_1P058
BT22
VCCPRIM_1P056
BP22
VCCPRIM_1P052
BV14
VCCPRIM_MPHY_1P052
R30435
*100K_5%_4
C30514
*1u/6.3V_4
C30479
*10P/50V_4
4.26A
16 of 20
3
VCCPRIM_3P33
VCCRTC
VCCPRIM_1P0513
DCPRTC
VCCPRIM_1P053
VCCAPLL_1P053
VCCA_BCLK_1P05
VCCAPLL_1P051
VCCA_SRC_1P05
VCCA_XTAL_1P05
VCCDPHY_1P242
VCCDPHY_1P244
VCCDPHY_1P241
VCCDPHY_1P243
VCCDPHY_EC_1P24
VCCDSW_3P32
VCCA_19P2_1P05
VCCPRIM_1P82
VCCPRIM_1P83
VCCPRIM_1P86
VCCPRIM_1P87
VCCPRIM_1P89
VCCPRIM_3P32
VCCPRIM_3P31
GPP_B0/CORE_VID0
GPP_B1/CORE_VID1
*CFL_U_43E_IL_IP_DDR4
for DS3
R30070 0_5%_6
SI
U30022
*APL3512ABI-TRG
4
VIN#1
5
VIN#2
3
EN
VOUT
GND
CB16
BR23
BY20
BP24
BR20
BT12
BP14
BR14
BU12
CP5
BY24
CA24
BY23
CA23
CP25
BT23
BR12
CC18
CC19
CD18
CD19
CP23
BW23
BP23
CB36
CB35
C99150 0.1U/16V_4
C30098 1u/6.3V_4
+VCCRTC
C30115 1u/6.3V_4
1
2
R30074 *0_4/S
VCCPRIM_1P05
VCCPRIM_1P05
VCCAPLL_1.05V
VCCA_OC_1P05
VCCAPLL_1.05V
VCCA_SRC_1P05
VCCA_XTAL_1P05
C30081 1u/6.3V_4
+VCCLDOSRAM_1P24
R1704 0_4
VCCDPHY_1P24
C1709 4.7u/6.3V_4
VCCA_19P2_1P05
VCCPRIM_1P8
VCCPRIM_3P3
VCCPRIM_3P3
+3V_DEEP_SUS+3VS5
C30478
0.1u/16V_4
+3V_DEEP_SUS
+BAT_RTC
+1.05V_DEEP_SUS
DCPRTC
+1.05V_DEEP_SUS
+1.05V_DEEP_SUS
+1.05V_DEEP_SUS
+1.05V_DEEP_SUS
+VCCLDOSRAM_1P24
VCCDPHY_1P24
+3VS5
+1.05V_DEEP_SUS
C30075 10u/6.3V_4
close CP23
+3V_DEEP_SUS
+3V_DEEP_SUS
2
20mils
PCH Internal VRM
PCH Internal VRM
PCH Internal VRM
+1.8V_DEEP_SUS
C30112
0.1u/16V_4
+VCCRTC
C30105
1u/6.3V_4
1
15
PROJECT : G7BD
PROJECT : G7BD
PROJECT : G7BD
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
KBL-U 14/15(PCH POWER)
KBL-U 14/15(PCH POWER)
KBL-U 14/15(PCH POWER)
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
1
15 49Wednesday, December 26, 2018
15 49Wednesday, December 26, 2018
15 49Wednesday, December 26, 2018
1A
1A
1A
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