Hotenda MPC8349EA Technical Data Manual

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© 2006–2011 Freescale Semiconductor, Inc. All rights reserved.

Freescale Semiconductor

Technical Data

The MPC8349EA PowerQUICC II Pro is a next generation
PowerQUICC II integrated host processor. The
MPC8349EA contains a processor core built on Power
Architecture® technology with system logic for networking,
storage, and general-purpose embedded applications. For
functional characteristics of the processor, refer to the

MPC8349EA PowerQUICC II Pro Integrated Host
Processor Family Reference Manual.

T o locate published errata or updates for this document, refer
to the MPC8349EA product summary page on our website,
as listed on the back cover of this document, or contact your
local Freescale sales office.

Document Number: MPC8349EAEC

Rev. 13, 09/2011

Contents

1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 6

3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 10

4. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 13

6. DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 15

7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

8. Ethernet: Three-Speed Ethernet, MII Management . 22

9. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

10. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

11. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

12. I

2

C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

13. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

14. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

15. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

16. IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

17. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

18. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 53

19. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

20. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

21. System Design Information . . . . . . . . . . . . . . . . . . . 79

22. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 82

23. Document Revision History . . . . . . . . . . . . . . . . . . . 84

MPC8349EA PowerQUICC II Pro
Integrated Host Processor Hardware
Specifications

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MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13

2 Freescale Semiconductor

Overview

NOTE

The information in this document is accurate for revision 3.x silicon and
later (in other words, for orderable part numbers ending in A or B). For
information on revision 1.1 silicon and earlier versions, see the MPC8349E

PowerQUICC II Pro Integrated Host Processor Hardware Specifications.

See Section 22.1, “Part Numbers Fully Addressed by This Document,” for
silicon revision level determination.

1 Overview

This section provides a high-level overview of the device features. Figure 1 shows the major functional
units within the MPC8349EA.

Figure 1. MPC8349EA Block Diagram

Major features of the device are as follows:

• Embedded PowerPC e300 processor core; operates at up to 667 MHz
— High-performance, superscalar processor core
— Floating-point, integer, load/store, system register, and branch processing units
— 32-Kbyte instruction cache, 32-Kbyte data cache
— Lockable portion of L1 cache
— Dynamic power management
— Software-compatible with the other Freescale processor families that implement Power

Architecture technology

TSEC

Coherent System Bus

PCI1

10/100/1Gb

MII, GMII, TBI,
RTBI, RGMII

SPI

Serial

IRQs

ROM

I2C

I

2

C Interfaces

TSEC

DDR/DDR2

Memory Controller

Local Bus Controller

Programmable Interrupt

Controller

DUART

e300 Core

DMA Controller

Serial Peripheral

Interface

32-Kbyte L1

Instruction

Cache

32-Kbyte

L1 Data

Cache

Sequencer

SEQ

64/32b PCI Controller

PCI2

0/32b PCI Controller

Security Engine

Arbiter Bus
Monitor

USB Hi-Speed

Host Device

General Purpose I/O

USB0

USB1

GPIO

SDRAM

DDR/DD

R2

DMA

MII, GMII, TBI,
RTBI, RGMII

10/100/1Gb

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MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13

Freescale Semiconductor 3

Overview

• Double data rate, DDR1/DDR2 SDRAM memory controller
— Programmable timing supporting DDR1 and DDR2 SDRAM
— 32- or 64-bit data interface, up to 400 MHz data rate
— Up to four physical banks (chip selects), each bank up to 1 Gbyte independently addressable
— DRAM chip configurations from 64 Mbits to 1 Gbit with ×8/×16 data ports
— Full error checking and correction (ECC) support
— Support for up to 16 simultaneous open pages (up to 32 pages for DDR2)
— Contiguous or discontiguous memory mapping
— Read-modify-write support
— Sleep-mode support for SDRAM self refresh
— Auto refresh
— On-the-fly power management using CKE
— Registered DIMM support
— 2.5-V SSTL2 compatible I/O for DDR1, 1.8-V SSTL2 compatible I/O for DDR2

• Dual three-speed (10/100/1000) Ethernet controllers (TSECs)
— Dual controllers designed to comply with IEEE 802.3™, 802.3u™, 820.3x™, 802.3z™,

802.3ac™ standards

— Ethernet physical interfaces:

– 1000 Mbps IEEE Std. 802.3 GMII/RGMII, IEEE Std. 802.3z TBI/RTBI, full-duplex
– 10/100 Mbps IEEE Std. 802.3 MII full- and half-duplex

— Buffer descriptors are backward-compatible with MPC8260 and MPC860T 10/100

programming models
— 9.6-Kbyte jumbo frame support
— RMON statistics support
— Internal 2-Kbyte transmit and 2-Kbyte receive FIFOs per TSEC module
— MII management interface for control and status
— Programmable CRC generation and checking

• Dual PCI interfaces
— Designed to comply with PCI Specification Revision 2.3
— Data bus width options:

– Dual 32-bit data PCI interfaces operating at up to 66 MHz

– Single 64-bit data PCI interface operating at up to 66 MHz
— PCI 3.3-V compatible
— PCI host bridge capabilities on both interfaces
— PCI agent mode on PCI1 interface
— PCI-to-memory and memory-to-PCI streaming
— Memory prefetching of PCI read accesses and support for delayed read transactions
— Posting of processor-to-PCI and PCI-to-memory writes

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4 Freescale Semiconductor

Overview

— On-chip arbitration supporting five masters on PCI1, three masters on PCI2
— Accesses to all PCI address spaces
— Parity supported
— Selectable hardware-enforced coherency
— Address translation units for address mapping between host and peripheral
— Dual address cycle for target
— Internal configuration registers accessible from PCI

• Security engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP,
IEEE Std. 802.11i®, iSCSI, and IKE processing. The security engine contains four
crypto-channels, a controller, and a set of crypto execution units (EUs):

— Public key execution unit (PKEU) :

– RSA and Diffie-Hellman algorithms
– Programmable field size up to 2048 bits
– Elliptic curve cryptography
– F2m and F(p) modes
– Programmable field size up to 511 bits

— Data encryption standard (DES) execution unit (DEU)

– DES and 3DES algorithms
– Two key (K1, K2) or three key (K1, K2, K3) for 3DES
– ECB and CBC modes for both DES and 3DES

— Advanced encryption standard unit (AESU)

– Implements the Rijndael symmetric-key cipher
– Key lengths of 128, 192, and 256 bits

– ECB, CBC, CCM, and counter (CTR) modes
— XOR parity generation accelerator for RAID applications
— ARC four execution unit (AFEU)

– Stream cipher compatible with the RC4 algorithm

– 40- to 128-bit programmable key
— Message digest execution unit (MDEU)

– SHA with 160-, 224-, or 256-bit message digest

– MD5 with 128-bit message digest

– HMAC with either algorithm
— Random number generator (RNG)
— Four crypto-channels, each supporting multi-command descriptor chains

– Static and/or dynamic assignment of crypto-execution units through an integrated controller

– Buffer size of 256 bytes for each execution unit, with flow control for large data sizes

• Universal serial bus (USB) dual role controller
— USB on-the-go mode with both device and host functionality

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MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13

Freescale Semiconductor 5

Overview

— Complies with USB specification Rev. 2.0
— Can operate as a stand-alone USB device

– One upstream facing port
– Six programmable USB endpoints

— Can operate as a stand-alone USB host controller

– USB root hub with one downstream-facing port
– Enhanced host controller interface (EHCI) compatible
– High-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operations

— External PHY with UTMI, serial and UTMI+ low-pin interface (ULPI)

• Universal serial bus (USB) multi-port host controller
— Can operate as a stand-alone USB host controller

– USB root hub with one or two downstream-facing ports
– Enhanced host controller interface (EHCI) compatible

– Complies with USB Specification Rev. 2.0
— High-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operations
— Direct connection to a high-speed device without an external hub
— External PHY with serial and low-pin count (ULPI) interfaces

• Local bus controller (LBC)
— Multiplexed 32-bit address and data operating at up to 133 MHz
— Eight chip selects for eight external slaves
— Up to eight-beat burst transfers
— 32-, 16-, and 8-bit port sizes controlled by an on-chip memory controller
— Three protocol engines on a per chip select basis:

– General-purpose chip select machine (GPCM)
– Three user-programmable machines (UPMs)

– Dedicated single data rate SDRAM controller
— Parity support
— Default boot ROM chip select with configurable bus width (8-, 16-, or 32-bit)

• Programmable interrupt controller (PIC)
— Functional and programming compatibility with the MPC8260 interrupt controller
— Support for 8 external and 35 internal discrete interrupt sources
— Support for 1 external (optional) and 7 internal machine checkstop interrupt sources
— Programmable highest priority request
— Four groups of interrupts with programmable priority
— External and internal interrupts directed to host processor
— Redirects interrupts to external INTA

pin in core disable mode.

— Unique vector number for each interrupt source

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MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13

6 Freescale Semiconductor

Electrical Characteristics

• Dual industry-standard I2C interfaces
— Two-wire interface
— Multiple master support
— Master or slave I2C mode support
— On-chip digital filtering rejects spikes on the bus
— System initialization data optionally loaded from I2C-1 EPROM by boot sequencer embedded

hardware

• DMA controller
— Four independent virtual channels
— Concurrent execution across multiple channels with programmable bandwidth control
— Handshaking (external control) signals for all channels: DMA_DREQ[0:3],

DMA_DACK[0:3], DMA_DDONE[0:3]
— All channels accessible to local core and remote PCI masters
— Misaligned transfer capability
— Data chaining and direct mode
— Interrupt on completed segment and chain

• DUAR T
— Two 4-wire interfaces (RxD, TxD, RTS, CTS)
— Programming model compatible with the original 16450 UART and the PC16550D

• Serial peripheral interface (SPI) for master or slave

• General-purpose parallel I/O (GPIO)
— 64 parallel I/O pins multiplexed on various chip interfaces

• System timers
— Periodic interrupt timer
— Real-time clock
— Software watchdog timer
— Eight general-purpose timers

• Designed to comply with IEEE Std. 1149.1™, JTAG boundary scan

• Integrated PCI bus and SDRAM clock generation

2 Electrical Characteristics

This section provides the AC and DC electrical specifications and thermal characteristics for the
MPC8349EA. The device is currently targeted to these specifications. Some of these specifications are
independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer
design specifications.

2.1 Overall DC Electrical Characteristics

This section covers the ratings, conditions, and other characteristics.

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MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13

Freescale Semiconductor 7

Electrical Characteristics

2.1.1 Absolute Maximum Ratings

Table 1 provides the absolute maximum ratings.

Table 1. Absolute Maximum Ratings

1

Parameter Symbol Max Value Unit Notes

Core supply voltage V

DD

–0.3 to 1.32 (1.36 max

for 667-MHz core

frequency)

V—

PLL supply voltage AV

DD

–0.3 to 1.32 (1.36 max

for 667-MHz core

frequency)

V—

DDR and DDR2 DRAM I/O voltage GV

DD

–0.3 to 2.75
–0.3 to 1.98

V—

Three-speed Ethernet I/O, MII management voltage LV

DD

–0.3 to 3.63 V —

PCI, local bus, DUART, system control and power management, I2C,
and JTAG I/O voltage

OV

DD

–0.3 to 3.63 V —

Input voltage DDR DRAM signals MV

IN

–0.3 to (GVDD + 0.3) V 2, 5

DDR DRAM reference MV

REF

–0.3 to (GVDD + 0.3) V 2, 5

Three-speed Ethernet signals LV

IN

–0.3 to (LVDD + 0.3) V 4, 5

Local bus, DUART, CLKIN, system control and
power management, I

2

C, and JTAG signals

OV

IN

–0.3 to (OVDD + 0.3) V 3, 5

PCI OV

IN

–0.3 to (OVDD + 0.3) V 6

Storage temperature range T

STG

–55 to 150 °C—

Notes:

1

Functional and tested operating conditions are given in Ta bl e 2 . Absolute maximum ratings are stress ratings only, and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause
permanent damage to the device.

2

Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit can be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.

3

Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit can be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.

4

Caution: LVIN must not exceed LVDD by more than 0.3 V. This limit can be exceeded for a maximum of 20 ms during power-on
reset and power-down sequences.

5

(M,L,O)VIN and MV

REF

may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.

6 OVIN on the PCI interface can overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation, as

shown in Figure 3.

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MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13

8 Freescale Semiconductor

Electrical Characteristics

2.1.2 Power Supply Voltage Specification

Table 2 provides the recommended operating conditions for the MPC8349EA. Note that the values in
Table 2 are the recommended and tested operating conditions. Proper device operation outside these

conditions is not guaranteed.

Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8349EA.

Figure 2. Overshoot/Undershoot Voltage for GVDD/OVDD/LV

DD

Table 2. Recommended Operating Conditions

Parameter Symbol

Recommended

Val ue

Unit Notes

Core supply voltage for 667-MHz core frequency V

DD

1.3 V ± 60 mV V 1

Core supply voltage V

DD

1.2 V ± 60 mV V 1

PLL supply voltage for 667-MHz core frequency AV

DD

1.3 V ± 60 mV V 1

PLL supply voltage AV

DD

1.2 V ± 60 mV V 1

DDR and DDR2 DRAM I/O voltage GV

DD

2.5 V ± 125 mV

1.8 V ± 90 mV

V—

Three-speed Ethernet I/O supply voltage LV

DD1

3.3 V ± 330 mV

2.5 V ± 125 mV

V—

Three-speed Ethernet I/O supply voltage LV

DD2

3.3 V ± 330 mV

2.5 V ± 125 mV

V—

PCI, local bus, DUART, system control and power
management, I

2

C, and JTAG I/O voltage

OV

DD

3.3 V ± 330 mV V —

Note:

1

GVDD, LVDD, OVDD, AVDD, and VDD must track each other and must vary in the same direction—either in the positive or
negative direction.

GND

GND – 0.3 V

GND – 0.7 V

Not to Exceed 10%

G/L/OVDD + 20%

G/L/OV

DD

G/L/OVDD + 5%

of t

interface

1

1. t

interface

refers to the clock period associated with the bus clock interface.

V

IH

V

IL

Note:

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MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13

Freescale Semiconductor 9

Electrical Characteristics

Figure 3 shows the undershoot and overshoot voltage of the PCI interface of the MPC8349EA for the

3.3-V signals, respectively.

Figure 3. Maximum AC Waveforms on PCI Interface for 3.3-V Signaling

2.1.3 Output Driver Characteristics

Table 3 provides information on the characteristics of the output driver strengths. The values are

preliminary estimates.

2.2 Power Sequencing

This section details the power sequencing considerations for the MPC8349EA.

2.2.1 Power-Up Sequencing

MPC8349EA does not require the core supply voltage (VDD and AVDD) and I/O supply voltages (GVDD,
LVDD, and OVDD) to be applied in any particular order. During the power ramp up, before the power

Table 3. Output Drive Capability

Driver Type

Output Impedance

(Ω)

Supply

Volt ag e

Local bus interface utilities signals 40 OV

DD

= 3.3 V

PCI signals (not including PCI output clocks) 25

PCI output clocks (including PCI_SYNC_OUT) 40

DDR signal 18 GV

DD

= 2.5 V

DDR2 signal 18

36 (half-strength mode)

GV

DD

= 1.8 V

TSEC/10/100 signals 40 LVDD = 2.5/3.3 V

DUART, system control, I

2

C, JTAG, USB 40 OVDD = 3.3 V

GPIO signals 40 OV

DD

= 3.3 V,

LV

DD

= 2.5/3.3 V

Undervoltage

Wavefor m

Overvoltage

Wavefor m

11 ns
(Min)

+7.1 V

7.1 V p-to-p
(Min)

4 ns
(Max)

–3.5 V

7.1 V p-to-p
(Min)

62.5 ns
+3.6 V

0 V

4 ns
(Max)

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MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13

10 Freescale Semiconductor

Power Characteristics

supplies are stable and if the I/O voltages are supplied before the core voltage, there may be a period of
time that all input and output pins will actively be driven and cause contention and excessive current from
3A to 5A. In order to avoid actively driving the I/O pins and to eliminate excessive current draw , apply the
core voltage (VDD) before the I/O voltage (GVDD, LVDD, and OVDD) and assert PORESET before the
power supplies fully ramp up. In the case where the core voltage is applied first, the core voltage supply
must rise to 90% of its nominal value before the I/O supplies reach 0.7 V, see Figure 4.

Figure 4. Power Sequencing Example

I/O voltage supplies (GVDD, L VDD, and OVDD) do not have any ordering requirements with respect to one
another.

3 Power Characteristics

The estimated typical power dissipation for the MPC8349EA device is shown in Table 4.

Table 4. MPC8349EA Power Dissipation

1

1

The values do not include I/O supply power (OVDD, LVDD, GVDD) or AVDD. For I/O power values, see Tab l e 5 .

Core Frequency (MHz) CSB Frequency (MHz) Typical at T

J

= 65 Typical

2, 3

Maximum

4

Unit

TBGA 333 333 2.0 3.0 3.2 W

166 1.8 2.8 2.9 W

400 266 2.1 3.0 3.3 W

133 1.9 2.9 3.1 W

450 300 2.3 3.2 3.5 W

150 2.1 3.0 3.2 W

500 333 2.4 3.3 3.6 W

166 2.2 3.1 3.4 W

533 266 2.4 3.3 3.6 W

133 2.2 3.1 3.4 W

667

5, 6

333 3.5 4.6 5 W

I/O Voltage (GVDD, LVDD, OVDD)

Core Voltage (V

DD

, AVDD)

90%

0.7 V

Time

Voltage

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MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13

Freescale Semiconductor 11

Power Characteristics

Table 5 shows the estimated typical I/O power dissipation for MPC8349EA.

2

Typical power is based on a voltage of VDD = 1.2 V, a junction temperature of TJ= 105°C, and a Dhrystone benchmark
application.

3

Thermal solutions may need to design to a value higher than typical power based on the end application, TA target, and I/O
power.

4

Maximum power is based on a voltage of VDD = 1.2 V, worst case process, a junction temperature of TJ=105°C, and an
artificial smoke test.

5

Typical power is based on a voltage of VDD = 1.3 V, a junction temperature of TJ = 105°C, and a Dhrystone benchmark
application.

6

Maximum power is based on a voltage of VDD = 1.3 V, worst case process, a junction temperature of TJ=105°C, and an
artificial smoke test.

Table 5. MPC8349EA Typical I/O Power Dissipation

Interface Parameter

GV

DD

(1.8 V)

GVDD

(2.5 V)

OVDD

(3.3 V)

LVDD

(3.3 V)

LVDD

(2.5 V)

Unit Comments

DDR I/O
65% utilization

2.5 V
Rs = 20 Ω
Rt = 50 Ω
2 pair of clocks

200 MHz, 32 bits 0.31 0.42 — — — W —

200 MHz, 64 bits 0.42 0.55 — — — W —

266 MHz, 32 bits 0.35 0.5 — — — W —

266 MHz, 64 bits 0.47 0.66 — — — W —

300 MHz, 32 bits 0.37 0.54 — — — W —

300 MHz, 64 bits 0.50 0.7 — — — W —

333 MHz, 32 bits 0.39 0.58 — — — W —

333 MHz, 64 bits 0.53 0.76 — — — W —

400 MHz, 32 bits0.44————— —

400 MHz, 64 bits0.59————— —

PCI I/O
load = 30 pF

33 MHz, 64 bits — — 0.08 — — W —

66 MHz, 64 bits — — 0.14 — — W —

33 MHz, 32 bits — — 0.04 — — W Multiply by 2 if using

2ports.

66 MHz, 32 bits — — 0.07 — — W

Local bus I/O
load = 25 pF

133 MHz, 32 bits — — 0.27 — — W —

83 MHz, 32 bits — — 0.17 — — W —

66 MHz, 32 bits — — 0.14 — — W —

50 MHz, 32 bits — — 0.11 — — W —

TSEC I/O
load = 25 pF

MII — — — 0.01 — W Multiply by number of

interfaces used.

GMII or TBI — — — 0.06 — W

RGMII or RTBI————0.04W

USB 12 MHz — — 0.01 — — W Multiply by 2 if using

2ports.

480 MHz — — 0.2 — — W

Other I/O — — — 0.01 — — W —

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MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13

12 Freescale Semiconductor

Clock Input Timing

4 Clock Input Timing

This section provides the clock input DC and AC electrical characteristics for the device.

4.1 DC Electrical Characteristics

Table 6 provides the clock input (CLKIN/PCI_SYNC_IN) DC timing specifications for the MPC8349EA.

4.2 AC Electrical Characteristics

The primary clock source for the MPC8349EA can be one of two inputs, CLKIN or PCI_CLK, depending
on whether the device is configured in PCI host or PCI agent mode. Table 7 provides the clock input
(CLKIN/PCI_CLK) AC timing specifications for the device.

Table 6. CLKIN DC Timing Specifications

Parameter Condition Symbol Min Max Unit

Input high voltage — V

IH

2.7 OVDD+0.3 V

Input low voltage — V

IL

–0.3 0.4 V

CLKIN input current 0 V ≤ VIN≤ OV

DD

I

IN

— ±10 μA

PCI_SYNC_IN input current 0 V ≤ VIN≤ 0.5 V or

OVDD–0.5V≤ VIN≤ OV

DD

I

IN

— ±10 μA

PCI_SYNC_IN input current 0.5 V ≤VIN ≤ OVDD – 0.5 V I

IN

— ±50 μA

Table 7. CLKIN AC Timing Specifications

Parameter/Condition Symbol Min Typical Max Unit Notes

CLKIN/PCI_CLK frequency f

CLKIN

——66MHz1, 6

CLKIN/PCI_CLK cycle time t

CLKIN

15 — — ns —

CLKIN/PCI_CLK rise and fall time t

KH

, t

KL

0.6 1.0 2.3 ns 2

CLKIN/PCI_CLK duty cycle t

KHK/tCLKIN

40 — 60 % 3

CLKIN/PCI_CLK jitter — — — ±150 ps 4, 5

Notes:

1. Caution: The system, core, USB, security, and TSEC must not exceed their respective maximum or minimum operating
frequencies.

2. Rise and fall times for CLKIN/PCI_CLK are measured at 0.4 and 2.7 V.

3. Timing is guaranteed by design and characterization.

4. This represents the total input jitter—short term and long term—and is guaranteed by design.

5. The CLKIN/PCI_CLK driver’s closed loop jitter bandwidth should be < 500 kHz at –20 dB. The bandwidth must be set low to
allow cascade-connected PLL-based devices to track CLKIN drivers with the specified jitter.

6. Spread spectrum clocking is allowed with 1% input frequency down-spread at maximum 50 KHz modulation rate regardless
of input frequency.

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Freescale Semiconductor 13

RESET Initialization

4.3 TSEC Gigabit Reference Clock Timing

Table 8 provides the TSEC gigabit reference clocks (EC_GTX_CLK125) AC timing specifications.

5 RESET Initialization

This section describes the DC and AC electrical specifications for the reset initialization timing and
electrical requirements of the MPC8349EA.

5.1 RESET DC Electrical Characteristics

Table 9 provides the DC electrical characteristics for the RESET pins of the MPC8349EA.

Table 8. EC_GTX_CLK125 AC Timing Specifications

At recommended operating conditions with LVDD = 2.5 ± 0.125 mV/ 3.3 V ± 165 mV

Parameter Symbol Min Typical Max Unit Notes

EC_GTX_CLK125 frequency t

G125

—125—MHz—

EC_GTX_CLK125 cycle time t

G125

—8—ns—

EC_GTX_CLK125 rise and fall time

LV

DD

= 2.5 V

LVDD = 3.3 V

t

G125R/tG125F

——

0.75

1.0

ns 1

EC_GTX_CLK125 duty cycle

GMII, TBI

1000Base-T for RGMII, RTBI

t

G125H/tG125

45
47

—

55
53

%2

EC_GTX_CLK125 jitter — — — ±150 ps 2

Notes:

1. Rise and fall times for EC_GTX_CLK125 are measured from 0.5 and 2.0 V for LV

DD

= 2.5 V and from 0.6 and 2.7 V for

LV

DD

=3.3V.

2. EC_GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2% degradation. The EC_GTX_CLK125

duty cycle can be loosened from 47%/53% as long as the PHY device can tolerate the duty cycle generated by the eTSEC
GTX_CLK. See Section 8.2.4, “RGMII and RTBI AC Timing Specifications for the duty cycle for 10Base-T and 100Base-T
reference clock.

Table 9. RESET Pins DC Electrical Characteristics

1

Parameter Symbol Condition Min Max Unit

Input high voltage V

IH

—2.0OV

DD

+0.3 V

Input low voltage V

IL

—–0.30.8V

Input current I

IN

——±5μA

Output high voltage

2

V

OH

I

OH

= –8.0 mA 2.4 — V

Output low voltage V

OL

IOL = 8.0 mA — 0.5 V

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14 Freescale Semiconductor

RESET Initialization

5.2 RESET AC Electrical Characteristics

Table 10 provides the reset initialization AC timing specifications of the MPC8349EA.

Output low voltage V

OL

IOL = 3.2 mA — 0.4 V

Notes:

1. This table applies for pins PORESET

, HRESET, SRESET, and QUIESCE.

2. HRESET

and SRESET are open drain pins, thus VOH is not relevant for those pins.

Table 10. RESET Initialization Timing Specifications

Parameter Min Max Unit Notes

Required assertion time of HRESET or SRESET (input) to activate reset flow 32 — t

PCI_SYNC_IN

1

Required assertion time of PORESET with stable clock applied to CLKIN when the
MPC8349EA is in PCI host mode

32 — t

CLKIN

2

Required assertion time of PORESET with stable clock applied to PCI_SYNC_IN
when the MPC8349EA is in PCI agent mode

32 — t

PCI_SYNC_IN

1

HRESET

/SRESET assertion (output) 512 — t

PCI_SYNC_IN

1

HRESET negation to SRESET negation (output) 16 — t

PCI_SYNC_IN

1

Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:2] and
CFG_CLKIN_DIV) with respect to negation of PORESET when the MPC8349EA is
in PCI host mode

4—t

CLKIN

2

Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:2] and
CFG_CLKIN_DIV) with respect to negation of PORESET

when the MPC8349EA is

in PCI agent mode

4—t

PCI_SYNC_IN

1

Input hold time for POR configuration signals with respect to negation of HRESET

0— ns—

Time for the MPC8349EA to turn off POR configuration signals with respect to the
assertion of HRESET

—4 ns 3

Time for the MPC8349EA to turn on POR configuration signals with respect to the
negation of HRESET

1—t

PCI_SYNC_IN

1, 3

Notes:

1. t

PCI_SYNC_IN

is the clock period of the input clock applied to PCI_SYNC_IN. In PCI host mode, the primary clock is applied
to the CLKIN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV. See the MPC8349EA
PowerQUICC II Pro Integrated Host Processor Family Reference Manual.

2. t

CLKIN

is the clock period of the input clock applied to CLKIN. It is valid only in PCI host mode. See the MPC8349EA

PowerQUICC II Pro Integrated Host Processor Family Reference Manual.

3. POR configuration signals consist of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV.

Table 9. RESET Pins DC Electrical Characteristics1 (continued)

Parameter Symbol Condition Min Max Unit

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Freescale Semiconductor 15

DDR and DDR2 SDRAM

Table 11 lists the PLL and DLL lock times.

6 DDR and DDR2 SDRAM

This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the
MPC8349EA. Note that DDR SDRAM is GVDD(typ) = 2.5 V and DDR2 SDRAM is GVDD(typ) = 1.8 V.
The AC electrical specifications are the same for DDR and DRR2 SDRAM.

NOTE

The information in this document is accurate for revision 3.0 silicon and
later. For information on revision 1.1 silicon and earlier versions see the

MPC8349E PowerQUICC II Pro Integrated Host Processor Hardware
Specifications. See Section 22.1, “Part Numbers Fully Addressed by This

Document,” for silicon revision level determination.

6.1 DDR and DDR2 SDRAM DC Electrical Characteristics

Table 12 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the

MPC8349EA when GVDD(typ) = 1.8 V.

Table 11. PLL and DLL Lock Times

Parameter/Condition Min Max Unit Notes

PLL lock times — 100 μs—

DLL lock times 7680 122,880 csb_clk cycles 1, 2

Notes:

1. DLL lock times are a function of the ratio between the output clock and the coherency system bus clock (csb_clk). A 2:1 ratio
results in the minimum and an 8:1 ratio results in the maximum.

2. The csb_clk is determined by the CLKIN and system PLL ratio. See Section 19, “Clocking.”

Table 12. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V

Parameter/Condition Symbol Min Max Unit Notes

I/O supply voltage GV

DD

1.71 1.89 V 1

I/O reference voltage MV

REF

0.49 × GV

DD

0.51 × GV

DD

V2

I/O termination voltage V

TT

MV

REF

–0.04 MV

REF

+0.04 V 3

Input high voltage V

IH

MV

REF

+ 0.125 GVDD+0.3 V —

Input low voltage V

IL

–0.3 MV

REF

–0.125 V —

Output leakage current I

OZ

–9.9 9.9 μA4

Output high current (V

OUT

= 1.420 V) I

OH

–13.4 — mA —

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16 Freescale Semiconductor

DDR and DDR2 SDRAM

Table 13 provides the DDR2 capacitance when GV

DD

(typ) = 1.8 V.

Table 14 provides the recommended operating conditions for the DDR SDRAM component(s) when

GVDD(typ) = 2.5 V.

Output low current (V

OUT

= 0.280 V) I

OL

13.4 — mA —

Notes:

1. GV

DD

is expected to be within 50 mV of the DRAM GV

DD

at all times.

2. MV

REF

is expected to equal 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak noise

on MV

REF

cannot exceed ±2% of the DC value.

3. V

TT

is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to equal

MV

REF

. This rail should track variations in the DC level of MV

REF

.

4. Output leakage is measured with all outputs disabled, 0 V

≤ V

OUT

≤ GVDD.

Table 13. DDR2 SDRAM Capacitance for GVDD(typ) = 1.8 V

Parameter/Condition Symbol Min Max Unit Notes

Input/output capacitance: DQ, DQS, DQS C

IO

68pF1

Delta input/output capacitance: DQ, DQS, DQS C

DIO

—0.5pF1

Note:

1. This parameter is sampled. GV

DD

= 1.8 V ± 0.090 V, f = 1 MHz, TA = 25°C, V

OUT

= GVDD/2, V

OUT

(peak-to-peak) = 0.2 V.

Table 14. DDR SDRAM DC Electrical Characteristics for GVDD(typ) = 2.5 V

Parameter/Condition Symbol Min Max Unit Notes

I/O supply voltage GV

DD

2.375 2.625 V 1

I/O reference voltage MV

REF

0.49 × GV

DD

0.51 × GV

DD

V2

I/O termination voltage V

TT

MV

REF

–0.04 MV

REF

+0.04 V 3

Input high voltage V

IH

MV

REF

+0.18 GVDD+0.3 V —

Input low voltage V

IL

–0.3 MV

REF

–0.18 V —

Output leakage current I

OZ

–9.9 –9.9 μA4

Output high current (V

OUT

= 1.95 V) I

OH

–15.2 — mA —

Output low current (V

OUT

= 0.35 V) I

OL

15.2 — mA —

Notes:

1. GV

DD

is expected to be within 50 mV of the DRAM GV

DD

at all times.

2. MV

REF

is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak

noise on MV

REF

may not exceed ±2% of the DC value.

3. V

TT

is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

equal to MV

REF

. This rail should track variations in the DC level of MV

REF

.

4. Output leakage is measured with all outputs disabled, 0 V

≤ V

OUT

≤ GVDD.

Table 12. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V (continued)

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Freescale Semiconductor 17

DDR and DDR2 SDRAM

Table 15 provides the DDR capacitance when GVDD(typ) = 2.5 V.

Table 16 provides the current draw characteristics for MV

REF

.

6.2 DDR and DDR2 SDRAM AC Electrical Characteristics

This section provides the AC electrical characteristics for the DDR and DDR2 SDRAM interface.

6.2.1 DDR and DDR2 SDRAM Input AC Timing Specifications

Table 17 provides the input AC timing specifications for the DDR2 SDRAM when GVDD(typ) = 1.8 V.

Table 18 provides the input AC timing specifications for the DDR SDRAM when GV

DD

(typ) = 2.5 V.

Table 15. DDR SDRAM Capacitance for GVDD(typ) = 2.5 V

Parameter/Condition Symbol Min Max Unit Notes

Input/output capacitance: DQ, DQS C

IO

68pF1

Delta input/output capacitance: DQ, DQS C

DIO

—0.5pF1

Note:

1. This parameter is sampled. GV

DD

= 2.5 V ± 0.125 V, f = 1 MHz, TA = 25°C, V

OUT

= GVDD/2, V

OUT

(peak-to-peak) = 0.2 V.

Table 16. Current Draw Characteristics for MV

REF

Parameter/Condition Symbol Min Max Unit Note

Current draw for MV

REF

I

MVREF

—500 μA1

Note:

1. The voltage regulator for MV

REF

must supply up to 500 μA current.

Table 17. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface

At recommended operating conditions with GVDD of 1.8 ± 5%.

Parameter Symbol Min Max Unit Notes

AC input low voltage V

IL

—MV

REF

– 0.25 V —

AC input high voltage V

IH

MV

REF

+ 0.25 — V —

Table 18. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface

At recommended operating conditions with GVDD of 2.5 ± 5%.

Parameter Symbol Min Max Unit Notes

AC input low voltage V

IL

—MV

REF

– 0.31 V —

AC input high voltage V

IH

MV

REF

+ 0.31 — V —

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18 Freescale Semiconductor

DDR and DDR2 SDRAM

Table 19 provides the input AC timing specifications for the DDR SDRAM interface.

Figure 5 illustrates the DDR input timing diagram showing the t

DISKEW

timing parameter.

Figure 5. DDR Input Timing Diagram

Table 19. DDR and DDR2 SDRAM Input AC Timing Specifications

At recommended operating conditions with GVDD of (1.8 or 2.5 V) ± 5%.

Parameter Symbol Min Max Unit Notes

Controller Skew for MDQS—MDQ/MECC/MDM t

CISKEW

ps 1, 2

400 MHz –600 600 3

333 MHz –750 750 —

266 MHz –750 750 —

200 MHz –750 750 —

Notes:

1. t

CISKEW

represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that

will be captured with MDQS[n]. This should be subtracted from the total timing budget.

2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called t

DISKEW

. This can be

determined by the equation: t

DISKEW

= ± (T/4 – abs (t

CISKEW

)); where T is the clock period and abs (t

CISKEW

) is the absolute

value of t

CISKEW

.

3. This specification applies only to the DDR interface.

MCK[n]

MCK[n]

t

MCK

MDQ[x]

MDQS[n]

t

DISKEW

D1D0

t

DISKEW

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Freescale Semiconductor 19

DDR and DDR2 SDRAM

6.2.2 DDR and DDR2 SDRAM Output AC Timing Specifications

Table 20 shows the DDR and DDR2 output AC timing specifications.

Table 20. DDR and DDR2 SDRAM Output AC Timing Specifications

At recommended operating conditions with GVDD of (1.8 or 2.5 V) ± 5%.

Parameter Symbol

1

Min Max Unit Notes

ADDR/CMD/MODT output setup with respect to MCK t

DDKHAS

ns 3

400 MHz 1.95 —

333 MHz 2.40 —

266 MHz 3.15 —

200 MHz 4.20 —

ADDR/CMD/MODT output hold with respect to MCK t

DDKHAX

ns 3

400 MHz 1.95 —

333 MHz 2.40 —

266 MHz 3.15 —

200 MHz 4.20 —

MCS

(n) output setup with respect to MCK t

DDKHCS

ns 3

400 MHz 1.95 —

333 MHz 2.40 —

266 MHz 3.15 —

200 MHz 4.20 —

MCS

(n) output hold with respect to MCK t

DDKHCX

ns 3

400 MHz 1.95 —

333 MHz 2.40 —

266 MHz 3.15 —

200 MHz 4.20 —

MCK to MDQS Skew t

DDKHMH

–0.6 0.6 ns 4

MDQ/MECC/MDM output setup with respect to
MDQS

t

DDKHDS,

t

DDKLDS

ps 5

400 MHz 700 —

333 MHz 775 —

266 MHz 1100 —

200 MHz 1200 —

MDQ/MECC/MDM output hold with respect to MDQS t

DDKHDX,

t

DDKLDX

ps 5

400 MHz 700 —

333 MHz 900 —

266 MHz 1100 —

200 MHz 1200 —

MDQS preamble start t

DDKHMP

–0.5 × t

MCK

– 0.6 –0.5 × t

MCK

+ 0.6 ns 6

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20 Freescale Semiconductor

DDR and DDR2 SDRAM

Figure 6 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (t

DDKHMH

).

Figure 6. Timing Diagram for t

DDKHMH

MDQS epilogue end t

DDKHME

–0.6 0.6 ns 6

Notes:

1. The symbols for timing specifications follow the pattern of t

(first two letters of functional block)(signal)(state)(reference)(state)

for inputs

and t

(first two letters of functional block)(reference)(state)(signal)(state)

for outputs. Output hold time can be read as DDR timing (DD) from

the rising or falling edge of the reference clock (KH or KL) until the output goes invalid (AX or DX). For example, t

DDKHAS

symbolizes DDR timing (DD) for the time t

MCK

memory clock reference (K) goes from the high (H) state until outputs (A) are

set up (S) or output valid time. Also, t

DDKLDX

symbolizes DDR timing (DD) for the time t

MCK

memory clock reference (K) goes

low (L) until data outputs (D) are invalid (X) or data output hold time.

2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.

3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK

, MCS, and MDQ/MECC/MDM/MDQS. For the
ADDR/CMD setup and hold specifications, it is assumed that the clock control register is set to adjust the memory clocks by
1/2 applied cycle.

4. t

DDKHMH

follows the symbol conventions described in note 1. For example, t

DDKHMH

describes the DDR timing (DD) from the

rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). t

DDKHMH

can be modified through control of the
DQSS override bits in the TIMING_CFG_2 register and is typically set to the same delay as the clock adjust in the CLK_CNTL
register. The timing parameters listed in the table assume that these two parameters are set to the same adjustment value.
See the MPC8349EA PowerQUICC II Pro Integrated Host Processor Family Reference Manual for the timing modifications
enabled by use of these bits.

5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
(MECC), or data mask (MDM). The data strobe should be centered inside the data eye at the pins of the microprocessor.

6. All outputs are referenced to the rising edge of MCK(n) at the pins of the microprocessor. Note that t

DDKHMP

follows the

symbol conventions described in note 1.

Table 20. DDR and DDR2 SDRAM Output AC Timing Specifications (continued)

At recommended operating conditions with GVDD of (1.8 or 2.5 V) ± 5%.

Parameter Symbol

1

Min Max Unit Notes

MDQS

MCK[n]

MCK[n]

t

MCK

MDQS

t

DDKHMH(min) = –0.6 ns

t

DDKHMHmax) = 0.6 ns

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Freescale Semiconductor 21

DUART

Figure 7 shows the DDR SDRAM output timing diagram.

Figure 7. DDR SDRAM Output Timing Diagram

Figure 8 provides the AC test load for the DDR bus.

Figure 8. DDR AC Test Load

7DUART

This section describes the DC and AC electrical specifications for the DUART interface of the
MPC8349EA.

7.1 DUART DC Electrical Characteristics

Table 21 provides the DC electrical characteristics for the DUART interface of the MPC8349EA.

Table 21. DUART DC Electrical Characteristics

Parameter Symbol Min Max Unit

High-level input voltage V

IH

2OV

DD

+ 0.3 V

Low-level input voltage V

IL

–0.3 0.8 V

Input current (0.8 V ≤ VIN ≤ 2 V) I

IN

—±5 μA

ADDR/CMD/MODT

t

DDKHMH

t

DDKLDS

t

DDKHDS

MDQ[x]

MDQS[n]

MCK[n]

MCK[n]

t

MCK

t

DDKLDX

t

DDKHDX

D1D0

t

DDKHAX,tDDKHCX

Write A0 NOOP

t

DDKHMP

t

DDKHAS,tDDKHCS

t

DDKHME

Output

Z0 = 50 Ω

RL = 50 Ω

GVDD/2

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22 Freescale Semiconductor

Ethernet: Three-Speed Ethernet, MII Management

7.2 DUART AC Electrical Specifications

Table 22 provides the AC timing parameters for the DUART interface of the MPC8349EA.

8 Ethernet: Three-Speed Ethernet, MII Management

This section provides the AC and DC electrical characteristics for three-speeds (10/100/1000 Mbps) and
MII management.

8.1 Three-Speed Ethernet Controller
(TSEC)—GMII/MII/TBI/RGMII/RTBI Electrical Characteristics

The electrical characteristics specified here apply to gigabit media independent interface (GMII), the
media independent interface (MII), ten-bit interface (TBI), reduced gigabit media independent
interface (RGMII), and reduced ten-bit interface (RTBI) signals except management data input/output
(MDIO) and management data clock (MDC). The MII, GMII, and TBI interfaces are defined for 3.3 V,
and the RGMII and RTBI interfaces are defined for 2.5 V. The RGMII and RTBI interfaces follow the
Hewlett-Packard Reduced Pin-Count Interface for Gigabit Ethernet Physical Layer Device Specification,
Version 1.2a (9/22/2000). The electrical characteristics for MDIO and MDC are specified in Section 8.3,

“Ethernet Management Interface Electrical Characteristics.”

High-level output voltage, IOH = –100 μAV

OH

OVDD – 0.2 — V

Low-level output voltage, I

OL

= 100 μAV

OL

—0.2V

Table 22. DUART AC Timing Specifications

Parameter Value Unit Notes

Minimum baud rate 256 baud —

Maximum baud rate > 1,000,000 baud 1

Oversample rate 16 — 2

Notes:

1. Actual attainable baud rate will be limited by the latency of interrupt processing.

2. The middle of a start bit is detected as the 8

th

sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are

sampled each 16th sample.

Table 21. DUART DC Electrical Characteristics (continued)

Parameter Symbol Min Max Unit

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Freescale Semiconductor 23

Ethernet: Three-Speed Ethernet, MII Management

8.1.1 TSEC DC Electrical Characteristics

GMII, MII, TBI, RGMII, and RTBI drivers and receivers comply with the DC parametric attributes
specified in Table 23 and Table 24. The RGMII and R TBI signals in Table 24 are based on a 2.5-V CMOS
interface voltage as defined by JEDEC EIA/JESD8-5.

8.2 GMII, MII, TBI, RGMII, and RTBI AC Timing Specifications

The AC timing specifications for GMII, MII, TBI, RGMII, and RTBI are presented in this section.

8.2.1 GMII Timing Specifications

This section describes the GMII transmit and receive AC timing specifications.

Table 23. GMII/TBI and MII DC Electrical Characteristics

Parameter Symbol Conditions Min Max Unit

Supply voltage 3.3 V LV

DD

2

— 2.97 3.63 V

Output high voltage V

OH

I

OH

= –4.0 mA LVDD = Min 2.40 LVDD+0.3 V

Output low voltage V

OL

IOL = 4.0 mA LVDD = Min GND 0.50 V

Input high voltage V

IH

——2.0LV

DD

+0.3 V

Input low voltage V

IL

— — –0.3 0.90 V

Input high current I

IH

V

IN

1

= LV

DD

—40μA

Input low current I

IL

V

IN

1

= GND –600 — μA

Notes:

1. The symbol V

IN

, in this case, represents the LVIN symbol referenced in Ta b le 1 and Tab l e 2 .

2. GMII/MII pins not needed for RGMII or RTBI operation are powered by the OV

DD

supply.

Table 24. RGMII/RTBI (When Operating at 2.5 V) DC Electrical Characteristics

Parameters Symbol Conditions Min Max Unit

Supply voltage 2.5 V LV

DD

— 2.37 2.63 V

Output high voltage V

OH

IOH = –1.0 mA LVDD = Min 2.00 LVDD+0.3 V

Output low voltage V

OL

I

OL

= 1.0 mA LV

DD

= Min GND – 0.3 0.40 V

Input high voltage V

IH

—LV

DD

= Min 1.7 LVDD+0.3 V

Input low voltage V

IL

—LV

DD

= Min –0.3 0.70 V

Input high current I

IH

V

IN

1

= LV

DD

—10μA

Input low current I

IL

V

IN

1

= GND –15 — μA

Note:

1. The symbol V

IN

, in this case, represents the LVIN symbol referenced in Ta b le 1 and Tab l e 2 .

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8.2.1.1 GMII Transmit AC Timing Specifications

Table 25 provides the GMII transmit AC timing specifications.

Figure 9 shows the GMII transmit AC timing diagram.

Figure 9. GMII Transmit AC Timing Diagram

8.2.1.2 GMII Receive AC Timing Specifications

Table 26 provides the GMII receive AC timing specifications.

Table 25. GMII Transmit AC Timing Specifications

At recommended operating conditions with LVDD/OV

DD

of 3.3 V ± 10%.

Parameter/Condition Symbol

1

Min Typ Max Unit

GTX_CLK clock period t

GTX

—8.0 — ns

GTX_CLK duty cycle t

GTXH/tGTX

43.75 — 56.25 %

GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay t

GTKHDX

0.5 — 5.0 ns

GTX_CLK clock rise time (20%–80%) t

GTXR

——1.0ns

GTX_CLK clock fall time (80%–20%) t

GTXF

——1.0ns

Notes:

1. The symbols for timing specifications follow the pattern t

(first two letters of functional block)(signal)(state)(reference)(state)

for inputs and

t

(first two letters of functional block)(reference)(state)(signal)(state)

for outputs. For example, t

GTKHDV

symbolizes GMII transmit timing (GT)

with respect to the t

GTX

clock reference (K) going to the high state (H) relative to the time date input signals (D) reaching the

valid state (V) to state or setup time. Also, t

GTKHDX

symbolizes GMII transmit timing (GT) with respect to the t

GTX

clock
reference (K) going to the high state (H) relative to the time date input signals (D) going invalid (X) or hold time. In general,
the clock reference symbol is based on three letters representing the clock of a particular function. For example, the subscript
of t

GTX

represents the GMII(G) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate

letter: R (rise) or F (fall).

Table 26. GMII Receive AC Timing Specifications

At recommended operating conditions with LVDD/OV

DD

of 3.3 V ± 10%.

Parameter/Condition Symbol

1

Min Typ Max Unit

RX_CLK clock period t

GRX

—8.0—ns

RX_CLK duty cycle t

GRXH/tGRX

40 — 60 %

RXD[7:0], RX_DV, RX_ER setup time to RX_CLK t

GRDVKH

2.0 — — ns

RXD[7:0], RX_DV, RX_ER hold time to RX_CLK t

GRDXKH

0.5 — — ns

GTX_CLK

TXD[7:0]

t

GTKHDX

t

GTX

t

GTXH

t

GTXR

t

GTXF

TX_EN
TX_ER

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Figure 10 shows the GMII receive AC timing diagram.

G

Figure 10. GMII Receive AC Timing Diagram

8.2.2 MII AC Timing Specifications

This section describes the MII transmit and receive AC timing specifications.

8.2.2.1 MII Transmit AC Timing Specifications

Table 27 provides the MII transmit AC timing specifications.

RX_CLK clock rise (20%–80%) t

GRXR

——1.0ns

RX_CLK clock fall time (80%–20%) t

GRXF

——1.0ns

Note:

1. The symbols for timing specifications follow the pattern of t

(first two letters of functional block)(signal)(state)(reference)(state)

for inputs

and t

(first two letters of functional block)(reference)(state)(signal)(state)

for outputs. For example, t

GRDVKH

symbolizes GMII receive timing
(GR) with respect to the time data input signals (D) reaching the valid state (V) relative to the tRX clock reference (K) going
to the high state (H) or setup time. Also, t

GRDXKL

symbolizes GMII receive timing (GR) with respect to the time data input

signals (D) went invalid (X) relative to the t

GRX

clock reference (K) going to the low (L) state or hold time. In general, the clock

reference symbol is based on three letters representing the clock of a particular function. For example, the subscript of t

GRX

represents the GMII (G) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter:
R (rise) or F (fall).

Table 27. MII Transmit AC Timing Specifications

At recommended operating conditions with LVDD/OV

DD

of 3.3 V ± 10%.

Parameter/Condition Symbol

1

Min Typ Max Unit

TX_CLK clock period 10 Mbps t

MTX

—400—ns

TX_CLK clock period 100 Mbps t

MTX

—40—ns

TX_CLK duty cycle t

MTXH/tMTX

35 — 65 %

TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay t

MTKHDX

1 5 15 ns

Table 26. GMII Receive AC Timing Specifications (continued)

At recommended operating conditions with LVDD/OV

DD

of 3.3 V ± 10%.

Parameter/Condition Symbol

1

Min Typ Max Unit

RX_CLK

RXD[7:0]

t

GRDXKH

t

GRX

t

GRXH

t

GRXR

t

GRXF

t

GRDVKH

RX_DV
RX_ER

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Figure 11 shows the MII transmit AC timing diagram.

Figure 11. MII Transmit AC Timing Diagram

8.2.2.2 MII Receive AC Timing Specifications

Table 28 provides the MII receive AC timing specifications.

TX_CLK data clock rise (20%–80%) t

MTXR

1.0 — 4.0 ns

TX_CLK data clock fall (80%–20%) t

MTXF

1.0 — 4.0 ns

Note:

1. The symbols for timing specifications follow the pattern of t

(first two letters of functional block)(signal)(state)(reference)(state)

for inputs

and t

(first two letters of functional block)(reference)(state)(signal)(state)

for outputs. For example, t

MTKHDX

symbolizes MII transmit timing

(MT) for the time t

MTX

clock reference (K) going high (H) until data outputs (D) are invalid (X). In general, the clock reference

symbol is based on two to three letters representing the clock of a particular function. For example, the subscript of t

MTX

represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter:
R (rise) or F (fall).

Table 28. MII Receive AC Timing Specifications

At recommended operating conditions with LVDD/OV

DD

of 3.3 V ± 10%.

Parameter/Condition Symbol

1

Min Typ Max Unit

RX_CLK clock period 10 Mbps t

MRX

— 400 — ns

RX_CLK clock period 100 Mbps t

MRX

—40—ns

RX_CLK duty cycle t

MRXH/tMRX

35 — 65 %

RXD[3:0], RX_DV, RX_ER setup time to RX_CLK t

MRDVKH

10.0 — — ns

RXD[3:0], RX_DV, RX_ER hold time to RX_CLK t

MRDXKH

10.0 — — ns

Table 27. MII Transmit AC Timing Specifications (continued)

At recommended operating conditions with LVDD/OV

DD

of 3.3 V ± 10%.

Parameter/Condition Symbol

1

Min Typ Max Unit

TX_CLK

TXD[3:0]

t

MTKHDX

t

MTX

t

MTXH

t

MTXR

t

MTXF

TX_EN
TX_ER

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Figure 12 provides the AC test load for TSEC.

Figure 12. TSEC AC Test Load

Figure 13 shows the MII receive AC timing diagram.

Figure 13. MII Receive AC Timing Diagram

8.2.3 TBI AC Timing Specifications

This section describes the TBI transmit and receive AC timing specifications.

RX_CLK clock rise (20%–80%) t

MRXR

1.0 — 4.0 ns

RX_CLK clock fall time (80%–20%) t

MRXF

1.0 — 4.0 ns

Note:

1. The symbols for timing specifications follow the pattern of t

(first two letters of functional block)(signal)(state)(reference)(state)

for inputs

and t

(first two letters of functional block)(reference)(state)(signal)(state)

for outputs. For example, t

MRDVKH

symbolizes MII receive timing

(MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t

MRX

clock reference (K) going to

the high (H) state or setup time. Also, t

MRDXKL

symbolizes MII receive timing (GR) with respect to the time data input signals

(D) went invalid (X) relative to the t

MRX

clock reference (K) going to the low (L) state or hold time. In general, the clock

reference symbol is based on three letters representing the clock of a particular function. For example, the subscript of t

MRX

represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter:
R (rise) or F (fall).

Table 28. MII Receive AC Timing Specifications (continued)

At recommended operating conditions with LVDD/OV

DD

of 3.3 V ± 10%.

Parameter/Condition Symbol

1

Min Typ Max Unit

Output

Z0 = 50 Ω

OVDD/2

R

L

= 50 Ω

RX_CLK

RXD[3:0]

t

MRDXKH

t

MRX

t

MRXH

t

MRXR

t

MRXF

RX_DV
RX_ER

t

MRDVKH

Val i d Data

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8.2.3.1 TBI Transmit AC Timing Specifications

Table 29 provides the TBI transmit AC timing specifications.

Figure 14 shows the TBI transmit AC timing diagram.

Figure 14. TBI Transmit AC Timing Diagram

8.2.3.2 TBI Receive AC Timing Specifications

Table 30 provides the TBI receive AC timing specifications.

Table 29. TBI Transmit AC Timing Specifications

At recommended operating conditions with LVDD/OV

DD

of 3.3 V ± 10%.

Parameter/Condition Symbol

1

Min Typ Max Unit

GTX_CLK clock period t

TTX

—8.0—ns

GTX_CLK duty cycle t

TTXH/tTTX

40 — 60 %

GTX_CLK to TBI data TXD[7:0], TX_ER, TX_EN delay t

TTKHDX

1.0 — 5.0 ns

GTX_CLK clock rise (20%–80%) t

TTXR

——1.0ns

GTX_CLK clock fall time (80%–20%) t

TTXF

——1.0ns

Notes:

1. The symbols for timing specifications follow the pattern of t

(first two letters of functional block)(signal)(state)(reference)(state)

for inputs

and t

(first two letters of functional block)(reference)(state)(signal)(state)

for outputs. For example, t

TTKHDV

symbolizes the TBI transmit

timing (TT) with respect to the time from t

TTX

(K) going high (H) until the referenced data signals (D) reach the valid state (V)

or setup time. Also, t

TTKHDX

symbolizes the TBI transmit timing (TT) with respect to the time from t

TTX

(K) going high (H) until
the referenced data signals (D) reach the invalid state (X) or hold time. In general, the clock reference symbol is based on
three letters representing the clock of a particular function. For example, the subscript of t

TTX

represents the TBI (T) transmit

(TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

Table 30. TBI Receive AC Timing Specifications

At recommended operating conditions with LVDD/OV

DD

of 3.3 V ± 10%.

Parameter/Condition Symbol

1

Min Typ Max Unit

PMA_RX_CLK clock period t

TRX

16.0 ns

PMA_RX_CLK skew t

SKTRX

7.5 — 8.5 ns

RX_CLK duty cycle t

TRXH/tTRX

40 — 60 %

GTX_CLK

TXD[7:0]

t

TTX

t

TTXH

t

TTXR

t

TTXF

t

TTKHDX

TX_EN
TX_ER

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Figure 15 shows the TBI receive AC timing diagram.

Figure 15. TBI Receive AC Timing Diagram

RXD[7:0], RX_DV, RX_ER (RCG[9:0]) setup time to rising
PMA_RX_CLK

t

TRDVKH

2

2.5 — — ns

RXD[7:0], RX_DV, RX_ER (RCG[9:0]) hold time to rising
PMA_RX_CLK

t

TRDXKH

2

1.5 — — ns

RX_CLK clock rise time (20%–80%) t

TRXR

0.7 — 2.4 ns

RX_CLK clock fall time (80%–20%) t

TRXF

0.7 — 2.4 ns

Notes:

1. The symbols for timing specifications follow the pattern of t

(first two letters of functional block)(signal)(state)(reference)(state)

for inputs

and t

(first two letters of functional block)(reference)(state)(signal)(state)

for outputs. For example, t

TRDVKH

symbolizes TBI receive timing

(TR) with respect to the time data input signals (D) reach the valid state (V) relative to the t

TRX

clock reference (K) going to

the high (H) state or setup time. Also, t

TRDXKH

symbolizes TBI receive timing (TR) with respect to the time data input signals

(D) went invalid (X) relative to the t

TRX

clock reference (K) going to the high (H) state. In general, the clock reference symbol

is based on three letters representing the clock of a particular function. For example, the subscript of t

TRX

represents the TBI
(T) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). For
symbols representing skews, the subscript SK followed by the clock that is being skewed (TRX).

2. Setup and hold time of even numbered RCG are measured from the riding edge of PMA_RX_CLK1. Setup and hold times
of odd-numbered RCG are measured from the riding edge of PMA_RX_CLK0.

Table 30. TBI Receive AC Timing Specifications (continued)

At recommended operating conditions with LVDD/OV

DD

of 3.3 V ± 10%.

Parameter/Condition Symbol

1

Min Typ Max Unit

PMA_RX_CLK1

RCG[9:0]

t

TRX

t

TRXH

t

TRXR

t

TRXF

t

TRDVKH

PMA_RX_CLK0

t

TRDXKH

t

TRDVKH

t

TRDXKH

t

TRXH

Even RCG Odd RCG

t

SKTRX

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8.2.4 RGMII and RTBI AC Timing Specifications

Table 31 presents the RGMII and RTBI AC timing specifications.

Table 31. RGMII and RTBI AC Timing Specifications

At recommended operating conditions with LVDD of 2.5 V ± 5%.

Parameter/Condition Symbol

1

Min Typ Max Unit

Data to clock output skew (at transmitter) t

SKRGT

–0.5 — 0.5 ns

Data to clock input skew (at receiver)

2

t

SKRGT

1.0 — 2.8 ns

Clock cycle duration

3

t

RGT

7.2 8.0 8.8 ns

Duty cycle for 1000Base-T

4, 5

t

RGTH/tRGT

45 50 55 %

Duty cycle for 10BASE-T and 100BASE-TX

3, 5

t

RGTH/tRGT

40 50 60 %

Rise time (20%–80%) t

RGTR

— — 0.75 ns

Fall time (80%–20%) t

RGTF

— — 0.75 ns

Notes:

1. In general, the clock reference symbol for this section is based on the symbols RGT to represent RGMII and RTBI timing. For
example, the subscript of t

RGT

represents the TBI (T) receive (RX) clock. Also, the notation for rise (R) and fall (F) times

follows the clock symbol. For symbols representing skews, the subscript is SK followed by the clock being skewed (RGT).

2. This implies that PC board design requires clocks to be routed so that an additional trace delay of greater than 1.5 ns is added
to the associated clock signal.

3. For 10 and 100 Mbps, t

RGT

scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.

4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet clock domains as long
as the minimum duty cycle is not violated and stretching occurs for no more than three t

RGT

of the lowest speed transitioned.

5. Duty cycle reference is LV

DD

/2.

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Figure 16 shows the RBMII and RTBI AC timing and multiplexing diagrams.

Figure 16. RGMII and RTBI AC Timing and Multiplexing Diagrams

8.3 Ethernet Management Interface Electrical Characteristics

The electrical characteristics specified here apply to the MII management interface signals management
data input/output (MDIO) and management data clock (MDC). The electrical characteristics for GMII,
RGMII, TBI and RTBI are specified in Section 8.1, “Three-Speed Ethernet Controller

(TSEC)—GMII/MII/TBI/RGMII/RTBI Electrical Characteristics.”

8.3.1 MII Management DC Electrical Characteristics

The MDC and MDIO are defined to operate at a supply voltage of 2.5 or 3.3 V. The DC electrical
characteristics for MDIO and MDC are provided in Table 32 and Table 33.

Table 32. MII Management DC Electrical Characteristics Powered at 2.5 V

Parameter Symbol Conditions Min Max Unit

Supply voltage (2.5 V) LV

DD

— 2.37 2.63 V

Output high voltage V

OH

I

OH

= –1.0 mA LV

DD

= Min 2.00 LVDD+0.3 V

Output low voltage V

OL

I

OL

= 1.0 mA LV

DD

= Min GND – 0.3 0.40 V

Input high voltage V

IH

—LV

DD

= Min 1.7 — V

Input low voltage V

IL

—LV

DD

= Min –0.3 0.70 V

GTX_CLK

t

RGT

t

RGTH

t

SKRGT

TX_CTL

TXD[8:5]
TXD[7:4]

TXD[9]

TXERR

TXD[4]

TXEN

TXD[3:0]

(At Transmitter)

TXD[8:5][3:0]

TXD[7:4][3:0]

TX_CLK

(At PHY)

RX_CTL

RXD[8:5]
RXD[7:4]

RXD[9]

RXERR

RXD[4]

RXDV

RXD[3:0]

RXD[8:5][3:0]

RXD[7:4][3:0]

RX_CLK
(At PHY)

t

SKRGT

t

SKRGT

t

SKRGT

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8.3.2 MII Management AC Electrical Specifications

Table 34 provides the MII management AC timing specifications.

Input high current I

IH

V

IN

1

= LV

DD

—10μA

Input low current I

IL

V

IN

= LV

DD

–15 — μA

Note:

1. The symbol V

IN

, in this case, represents the LVIN symbol referenced in Ta b le 1 and Tab l e 2 .

Table 33. MII Management DC Electrical Characteristics Powered at 3.3 V

Parameter Symbol Conditions Min Max Unit

Supply voltage (3.3 V) LV

DD

— 2.97 3.63 V

Output high voltage V

OH

I

OH

= –1.0 mA LV

DD

= Min 2.10 LVDD+0.3 V

Output low voltage V

OL

I

OL

= 1.0 mA LV

DD

= Min GND 0.50 V

Input high voltage V

IH

—2.00—V

Input low voltage V

IL

— — 0.80 V

Input high current I

IH

LVDD = Max V

IN

1

= 2.1 V — 40 μA

Input low current I

IL

LVDD = Max V

IN

= 0.5 V –600 — μA

Note:

1. The symbol V

IN

, in this case, represents the LVIN symbol referenced in Ta b le 1 and Tab l e 2 .

Table 34. MII Management AC Timing Specifications

At recommended operating conditions with LVDD is 3.3 V ± 10% or 2.5 V ± 5%.

Parameter/Condition Symbol

1

Min Typ Max Unit Notes

MDC frequency f

MDC

—2.5—MHz2

MDC period t

MDC

—400—ns—

MDC clock pulse width high t

MDCH

32 — — ns —

MDC to MDIO delay t

MDKHDX

10 — 70 ns 3

MDIO to MDC setup time t

MDDVKH

5——ns—

MDIO to MDC hold time t

MDDXKH

0——ns—

MDC rise time t

MDCR

— — 10 ns —

Table 32. MII Management DC Electrical Characteristics Powered at 2.5 V (continued)

Parameter Symbol Conditions Min Max Unit

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Figure 17 shows the MII management AC timing diagram.

Figure 17. MII Management Interface Timing Diagram

MDC fall time t

MDHF

— — 10 ns —

Notes:

1. The symbols for timing specifications follow the pattern of t

(first two letters of functional block)(signal)(state)(reference)(state)

for inputs

and t

(first two letters of functional block)(reference)(state)(signal)(state)

for outputs. For example, t

MDKHDX

symbolizes management data

timing (MD) for the time t

MDC

from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time. Also,

t

MDDVKH

symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state (V)

relative to the t

MDC

clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention

is used with the appropriate letter: R (rise) or F (fall).

2. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 267 MHz, the maximum frequency is 8.3 MHz
and the minimum frequency is 1.2 MHz; for a csb_clk of 375 MHz, the maximum frequency is 11.7 MHz and the minimum
frequency is 1.7 MHz).

3. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 267 MHz, the delay is 70 ns and for a csb_clk of
333 MHz, the delay is 58 ns).

Table 34. MII Management AC Timing Specifications (continued)

At recommended operating conditions with LVDD is 3.3 V ± 10% or 2.5 V ± 5%.

Parameter/Condition Symbol

1

Min Typ Max Unit Notes

MDC

t

MDDXKH

t

MDC

t

MDCH

t

MDCR

t

MDCF

t

MDDVKH

t

MDKHDX

MDIO

MDIO

(Input)

(Output)

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USB

9USB

This section provides the AC and DC electrical specifications for the USB interface of the MPC8349EA.

9.1 USB DC Electrical Characteristics

Table 35 provides the DC electrical characteristics for the USB interface.

9.2 USB AC Electrical Specifications

Table 36 describes the general timing parameters of the USB interface of the MPC8349EA.

Table 35. USB DC Electrical Characteristics

Parameter Symbol Min Max Unit

High-level input voltage V

IH

2OV

DD

+0.3 V

Low-level input voltage V

IL

–0.3 0.8 V

Input current I

IN

—±5 μA

High-level output voltage, IOH = –100 μAV

OH

OVDD–0.2 — V

Low-level output voltage, IOL = 100 μAV

OL

—0.2V

Table 36. USB General Timing Parameters (ULPI Mode Only)

Parameter Symbol

1

Min Max Unit Notes

USB clock cycle time t

USCK

15 — ns 2–5

Input setup to USB clock—all inputs t

USIVKH

4 — ns 2–5

Input hold to USB clock—all inputs t

USIXKH

1 — ns 2–5

USB clock to output valid—all outputs t

USKHOV

— 7 ns 2–5

Output hold from USB clock—all outputs t

USKHOX

2 — ns 2–5

Notes:

1. The symbols for timing specifications follow the pattern of t

(first two letters of functional block)(signal)(state)(reference)(state)

for inputs

and t

(first two letters of functional block)(reference)(state)(signal)(state)

for outputs. For example, t

USIXKH

symbolizes USB timing (US) for

the input (I) to go invalid (X) with respect to the time the USB clock reference (K) goes high (H). Also, t

USKHOX

symbolizes
USB timing (US) for the USB clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold
time.

2. All timings are in reference to USB clock.

3. All signals are measured from OV

DD

/2 of the rising edge of the USB clock to 0.4 × OVDD of the signal in question for 3.3 V

signaling levels.

4. Input timings are measured at the pin.

5. For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the
component pin is less than or equal to that of the leakage current specification.

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Freescale Semiconductor 35

Local Bus

Figure 18 and Figure 19 provide the AC test load and signals for the USB, respectively.

Figure 18. USB AC Test Load

Figure 19. USB Signals

10 Local Bus

This section describes the DC and AC electrical specifications for the local bus interface of the
MPC8349EA.

10.1 Local Bus DC Electrical Characteristics

Table 37 provides the DC electrical characteristics for the local bus interface.

Table 37. Local Bus DC Electrical Characteristics

Parameter Symbol Min Max Unit

High-level input voltage V

IH

2OV

DD

+0.3 V

Low-level input voltage V

IL

–0.3 0.8 V

Input current I

IN

—±5μA

High-level output voltage, IOH = –100 μAV

OH

OVDD–0.2 — V

Low-level output voltage, IOL = 100 μAV

OL

—0.2V

Output

Z0 = 50 Ω

OVDD/2

R

L

= 50 Ω

Output Signals:

t

USKHOV

USB0_CLK/USB1_CLK/DR_CLK

Input Signals

t

USIXKH

t

USIVKH

t

USKHOX

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Local Bus

10.2 Local Bus AC Electrical Specification

Table 38 and Table 39 describe the general timing parameters of the local bus interface of the

MPC8349EA.

Table 38. Local Bus General Timing Parameters—DLL On

Parameter Symbol

1

Min Max Unit Notes

Local bus cycle time t

LBK

7.5 — ns 2

Input setup to local bus clock (except LUPWAIT) t

LBIVKH1

1.5 — ns 3, 4

LUPWAIT input setup to local bus clock t

LBIVKH2

2.2 — ns 3, 4

Input hold from local bus clock (except LUPWAIT) t

LBIXKH1

1.0 — ns 3, 4

LUPWAIT Input hold from local bus clock t

LBIXKH2

1.0 — ns 3, 4

LALE output fall to LAD output transition (LATCH hold time) t

LBOTOT1

1.5 — ns 5

LALE output fall to LAD output transition (LATCH hold time) t

LBOTOT2

3—ns6

LALE output fall to LAD output transition (LATCH hold time) t

LBOTOT3

2.5 — ns 7

Local bus clock to LALE rise t

LBKHLR

—4.5ns—

Local bus clock to output valid (except LAD/LDP and LALE) t

LBKHOV1

—4.5ns—

Local bus clock to data valid for LAD/LDP t

LBKHOV2

—4.5ns3

Local bus clock to address valid for LAD t

LBKHOV3

—4.5ns3

Output hold from local bus clock (except LAD/LDP and LALE) t

LBKHOX1

1—ns3

Output hold from local bus clock for LAD/LDP t

LBKHOX2

1—ns3

Local bus clock to output high impedance for LAD/LDP t

LBKHOZ

—3.8ns8

Notes:

1. The symbols for timing specifications follow the pattern of t

(first two letters of functional block)(signal)(state)(reference)(state)

for inputs

and t

(first two letters of functional block)(reference)(state)(signal)(state)

for outputs. For example, t

LBIXKH1

symbolizes local bus timing (LB)

for the input (I) to go invalid (X) with respect to the time the t

LBK

clock reference (K) goes high (H), in this case for clock one

(1). Also, t

LBKHOX

symbolizes local bus timing (LB) for the t

LBK

clock reference (K) to go high (H), with respect to the output

(O) going invalid (X) or output hold time.

2. All timings are in reference to the rising edge of LSYNC_IN.

3. All signals are measured from OV

DD

/2 of the rising edge of LSYNC_IN to 0.4 × OVDD of the signal in question for 3.3 V

signaling levels.

4. Input timings are measured at the pin.

5. t

LBOTOT 1

should be used when RCWH[LALE] is not set and when the load on the LALE output pin is at least 10 pF less than

the load on the LAD output pins.

6. t

LBOTOT 2

should be used when RCWH[LALE] is set and when the load on the LALE output pin is at least 10 pF less than the

load on the LAD output pins.

7. t

LBOTOT 3

should be used when RCWH[LALE] is set and when the load on the LALE output pin equals the load on the LAD

output pins.

8. For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the
component pin is less than or equal to that of the leakage current specification.

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Freescale Semiconductor 37

Local Bus

Figure 20 provides the AC test load for the local bus.

Figure 20. Local Bus C Test Load

Table 39. Local Bus General Timing Parameters—DLL Bypass

9

Parameter Symbol

1

Min Max Unit Notes

Local bus cycle time t

LBK

15 — ns 2

Input setup to local bus clock t

LBIVKH

7 — ns 3, 4

Input hold from local bus clock t

LBIXKH

1.0 — ns 3, 4

LALE output fall to LAD output transition (LATCH hold time) t

LBOTOT1

1.5 — ns 5

LALE output fall to LAD output transition (LATCH hold time) t

LBOTOT2

3—ns6

LALE output fall to LAD output transition (LATCH hold time) t

LBOTOT3

2.5 — ns 7

Local bus clock to output valid t

LBKLOV

—3ns3

Local bus clock to output high impedance for LAD/LDP t

LBKHOZ

—4ns8

Notes:

1. The symbols for timing specifications follow the pattern of t

(first two letters of functional block)(signal)(state)(reference)(state)

for inputs

and t

(first two letters of functional block)(reference)(state)(signal)(state)

for outputs. For example, t

LBIXKH1

symbolizes local bus timing (LB)

for the input (I) to go invalid (X) with respect to the time the t

LBK

clock reference (K) goes high (H), in this case for clock one

(1). Also, t

LBKHOX

symbolizes local bus timing (LB) for the t

LBK

clock reference (K) to go high (H), with respect to the output

(O) going invalid (X) or output hold time.

2. All timings are in reference to the falling edge of LCLK0 (for all outputs and for LGTA

and LUPWAIT inputs) or the rising edge

of LCLK0 (for all other inputs).

3. All signals are measured from OVDD/2 of the rising/falling edge of LCLK0 to 0.4 × OVDD of the signal in question for 3.3 V
signaling levels.

4. Input timings are measured at the pin.

5. t

LBOTOT 1

should be used when RCWH[LALE] is set and when the load on the LALE output pin is at least 10 pF less than the

load on the LAD output pins.

6. t

LBOTOT 2

should be used when RCWH[LALE] is not set and when the load on the LALE output pin is at least 10 pF less than

the load on the LAD output pins.the

7. t

LBOTOT 3

should be used when RCWH[LALE] is not set and when the load on the LALE output pin equals to the load on the

LAD output pins.

8. For purposes of active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.

9. DLL bypass mode is not recommended for use at frequencies above 66 MHz.

Output

Z0 = 50 Ω

OVDD/2

R

L

= 50 Ω

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Local Bus

Figure 21 through Figure 26 show the local bus signals.

Figure 21. Local Bus Signals, Nonspecial Signals Only (DLL Enabled)

Figure 22. Local Bus Signals, Nonspecial Signals Only (DLL Bypass Mode)

Output Signals:

LA[27:31]/LBCTL/LBCKE/LOE

LSDA10/LSDWE/LSDRAS/

LSDCAS

/LSDDQM[0:3]

t

LBKHOV

t

LBKHOV

t

LBKHOV

LSYNC_IN

Input Signals:

LAD[0:31]/LDP[0:3]

Output (Data) Signals:

LAD[0:31]/LDP[0:3]

Output (Address) Signal:

LAD[0:31]

LALE

t

LBIXKH

t

LBIVKH

t

LBIXKH

t

LBKHOX

t

LBKHOZ

t

LBKHLR

t

LBOTOT

t

LBKHOZ

t

LBKHOX

Output Signals:

LSDA10/LSDWE/LSDRAS

/

LSDCAS

/LSDDQM[0:3]

LCLK[n]

Input Signals:

LAD[0:31]/LDP[0:3]

Output Signals:

LAD[0:31]/LDP[0:3]

LALE

Input Signal:

LGTA

t

LBIXKH

t

LBKLOV

t

LBKHOZ

t

LBOTOT

t

LBIVKH

t

LBIXKH

t

LBKLOV

t

LBKLOV

t

LBIVKH

LA[27:31]/LBCTL/LBCKE/LOE

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Freescale Semiconductor 39

Local Bus

Figure 23. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2 (DLL Enabled)

Figure 24. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2 (DLL Bypass Mode)

LSYNC_IN

UPM Mode Input Signal:

LUPWAIT

t

LBIXKH2

t

LBIVKH2

t

LBIVKH1

t

LBIXKH1

t

LBKHOZ1

T1

T3

Input Signals:

LAD[0:31]/LDP[0:3]

UPM Mode Output Signals:

LCS

[0:7]/LBS[0:3]/LGPL[0:5]

GPCM Mode Output Signals:

LCS[0:7]/LWE

t

LBKHOV1

t

LBKHOV1

t

LBKHOZ1

LCLK

UPM Mode Input Signal:

LUPWAIT

t

LBIXKH

t

LBIVKH

t

LBIVKH

t

LBIXKH

t

LBKHOZ

T1

T3

Input Signals:

LAD[0:31]/LDP[0:3]

UPM Mode Output Signals:

LCS

[0:7]/LBS[0:3]/LGPL[0:5]

GPCM Mode Output Signals:

LCS

[0:7]/LWE

t

LBKLOV

t

LBKLOV

t

LBKHOZ

(DLL Bypass Mode)

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40 Freescale Semiconductor

Local Bus

Figure 25. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (DLL Bypass Mode)

LCLK

UPM Mode Input Signal:

LUPWAIT

t

LBIXKH

t

LBIVKH

t

LBIVKH

t

LBIXKH

t

LBKHOZ

T1

T3

UPM Mode Output Signals:

LCS

[0:7]/LBS[0:3]/LGPL[0:5]

GPCM Mode Output Signals:

LCS

[0:7]/LWE

t

LBKLOV

t

LBKLOV

t

LBKHOZ

T2

T4

Input Signals:

LAD[0:31]/LDP[0:3]

(DLL Bypass Mode)

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MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13

Freescale Semiconductor 41

JTAG

Figure 26. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (DLL Enabled)

11 JTAG

This section describes the DC and AC electrical specifications for the IEEE Std. 1 149.1 (JTAG) interface
of the MPC8349EA.

11.1 JTAG DC Electrical Characteristics

Table 40 provides the DC electrical characteristics for the IEEE Std. 1149.1 (JTAG) interface of the

MPC8349EA.

Table 40. JTAG Interface DC Electrical Characteristics

Parameter Symbol Condition Min Max Unit

Input high voltage V

IH

—OV

DD

–0.3 OVDD+0.3 V

Input low voltage V

IL

—–0.30.8V

Input current I

IN

——±5μA

Output high voltage V

OH

I

OH

= –8.0 mA 2.4 — V

LSYNC_IN

UPM Mode Input Signal:

LUPWAIT

t

LBIXKH2

t

LBIVKH2

t

LBIVKH1

t

LBIXKH1

t

LBKHOZ1

T1

T3

Input Signals:

LAD[0:31]/LDP[0:3]

UPM Mode Output Signals:

LCS

[0:3]/LBS[0:3]/LGPL[0:5]

GPCM Mode Output Signals:

LCS[0:3]/LWE

t

LBKHOV1

t

LBKHOV1

t

LBKHOZ1

T2

T4

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JTAG

11.2 JTAG AC Timing Specifications

This section describes the AC electrical specifications for the IEEE Std. 1149.1 (JTAG) interface of the
MPC8349EA. Table 41 provides the JTAG AC timing specifications as defined in Figure 28 through

Figure 31.

Output low voltage V

OL

IOL = 8.0 mA — 0.5 V

Output low voltage V

OL

IOL = 3.2 mA — 0.4 V

Table 41. JTAG AC Timing Specifications (Independent of CLKIN)

1

At recommended operating conditions (see Ta bl e 2 ).

Parameter Symbol

2

Min Max Unit Notes

JTAG external clock frequency of operation f

JTG

033.3MHz—

JTAG external clock cycle time t

JTG

30 — ns —

JTAG external clock pulse width measured at 1.4 V t

JTKHKL

15 — ns —

JTAG external clock rise and fall times t

JTGR

, t

JTGF

02ns—

TRST assert time t

TRST

25 — ns 3

Input setup times:

Boundary-scan data

TMS, TDI

t

JTDVKH

t

JTIVKH

4
4

—
—

ns

4

Input hold times:

Boundary-scan data

TMS, TDI

t

JTDXKH

t

JTIXKH

10
10

—
—

ns

4

Val id ti m es:

Boundary-scan data

TDO

t

JTKLDV

t

JTKLOV

2
2

11
11

ns

5

Output hold times:

Boundary-scan data

TDO

t

JTKLDX

t

JTKLOX

2
2

—
—

ns

5

Table 40. JTAG Interface DC Electrical Characteristics (continued)

Parameter Symbol Condition Min Max Unit

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MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13

Freescale Semiconductor 43

JTAG

Figure 27 provides the AC test load for TDO and the boundary-scan outputs of the MPC8349EA.

Figure 27. AC Test Load for the JTAG Interface

Figure 28 provides the JTAG clock input timing diagram.

Figure 28. JTAG Clock Input Timing Diagram

Figure 29 provides the TRST timing diagram.

Figure 29. TRST Timing Diagram

JTAG external clock to output high impedance:

Boundary-scan data

TDO

t

JTKLDZ

t

JTKLOZ

2
2

19

9

ns

5, 6

Notes:

1. All outputs are measured from the midpoint voltage of the falling/rising edge of t

TCLK

to the midpoint of the signal in question.
The output timings are measured at the pins. All output timings assume a purely resistive 50 Ω load (see Figure 18).
Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.

2. The symbols for timing specifications follow the pattern of t

(first two letters of functional block)(signal)(state)(reference)(state)

for inputs

and t

(first two letters of functional block)(reference)(state)(signal)(state)

for outputs. For example, t

JTDVKH

symbolizes JTAG device timing

(JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the t

JTG

clock reference (K) going

to the high (H) state or setup time. Also, t

JTDXKH

symbolizes JTAG timing (JT) with respect to the time data input signals (D)

went invalid (X) relative to the t

JTG

clock reference (K) going to the high (H) state. In general, the clock reference symbol is
based on three letters representing the clock of a particular function. For rise and fall times, the latter convention is used with
the appropriate letter: R (rise) or F (fall).

3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.

4. Non-JTAG signal input timing with respect to t

TCLK

.

5. Non-JTAG signal output timing with respect to t

TCLK

.

6. Guaranteed by design and characterization.

Table 41. JTAG AC Timing Specifications (Independent of CLKIN)1 (continued)

At recommended operating conditions (see Ta bl e 2 ).

Parameter Symbol

2

Min Max Unit Notes

Output

Z0 = 50 Ω

OVDD/2

R

L

= 50 Ω

JTAG

t

JTKHKL

t

JTGR

External Clock

VMVMVM

t

JTG

t

JTGF

VM = Midpoint Voltage (OVDD/2)

TRST

VM = Midpoint Voltage (OVDD/2)

VM VM

t

TRST

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44 Freescale Semiconductor

JTAG

Figure 30 provides the boundary-scan timing diagram.

Figure 30. Boundary-Scan Timing Diagram

Figure 31 provides the test access port timing diagram.

Figure 31. Test Access Port Timing Diagram

VM = Midpoint Voltage (OVDD/2)

VM VM

t

JTDVKH

t

JTDXKH

Boundary

Data Outputs

Boundary

Data Outputs

JTAG

External Clock

Boundary

Data Inputs

Output Data Valid

t

JTKLDX

t

JTKLDZ

t

JTKLDV

Input

Data Valid

Output Data Valid

VM = Midpoint Voltage (OVDD/2)

VM VM

t

JTIVKH

t

JTIXKH

JTAG

External Clock

Output Data Valid

t

JTKLOX

t

JTKLOZ

t

JTKLOV

Input

Data Valid

Output Data Valid

TDI, TMS

TDO

TDO

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MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13

Freescale Semiconductor 45

I2C

12 I2C

This section describes the DC and AC electrical characteristics for the I2C interface of the MPC8349EA.

12.1 I2C DC Electrical Characteristics

Table 42 provides the DC electrical characteristics for the I2C interface of the MPC8349EA.

12.2 I2C AC Electrical Specifications

Table 43 provides the AC timing parameters for the I2C interface of the MPC8349EA. Note that all values

refer to V

IH

(min) and VIL(max) levels (see Table 42).

Table 4 2 . I2C DC Electrical Characteristics

At recommended operating conditions with OVDD of 3.3 V ± 10%.

Parameter Symbol Min Max Unit Notes

Input high voltage level V

IH

0.7 × OV

DD

OVDD+0.3 V —

Input low voltage level V

IL

–0.3 0.3 × OV

DD

V—

Low level output voltage V

OL

00.2× OV

DD

V1

Output fall time from VIH(min) to VIL(max) with a bus
capacitance from 10 to 400 pF

t

I2KLKV

20 + 0.1 × C

B

250 ns 2

Pulse width of spikes which must be suppressed by the
input filter

t

I2KHKL

050ns3

Input current each I/O pin (input voltage is between

0.1 × OV

DD

and 0.9 × OVDD(max)

I

I

–10 10 μA4

Capacitance for each I/O pin C

I

—10pF—

Notes:

1. Output voltage (open drain or open collector) condition = 3 mA sink current.

2. C

B

= capacitance of one bus line in pF.

3. Refer to the MPC8349EA Integrated Host Processor Family Reference Manual, for information on the digital filter used.

4. I/O pins obstruct the SDA and SCL lines if OV

DD

is switched off.

Table 43. I2C AC Electrical Specifications

Parameter Symbol

1

Min Max Unit

SCL clock frequency f

I2C

0 400 kHz

Low period of the SCL clock t

I2CL

1.3 — μs

High period of the SCL clock t

I2CH

0.6 — μs

Setup time for a repeated START condition t

I2SVKH

0.6 — μs

Hold time (repeated) START condition (after this period, the first clock
pulse is generated)

t

I2SXKL

0.6 — μs

Data setup time t

I2DVKH

100 — ns

Data hold time:CBUS compatible masters
I

2

C bus devices

t

I2DXKL

—
0

2

—

0.9

3

μs

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I2C

Figure 32 provides the AC test load for the I2C.

Figure 32. I2C AC Test Load

Figure 33 shows the AC timing diagram for the I2C bus.

Figure 33. I2C Bus AC Timing Diagram

Fall time of both SDA and SCL signals

5

t

I2CF

__

300 ns

Setup time for STOP condition t

I2PVKH

0.6 — μs

Bus free time between a STOP and START condition t

I2KHDX

1.3 — μs

Noise margin at the LOW level for each connected device (including
hysteresis)

V

NL

0.1 × OV

DD

—V

Noise margin at the HIGH level for each connected device (including
hysteresis)

V

NH

0.2 × OV

DD

—V

Notes:

1. The symbols for timing specifications follow the pattern of t

(first two letters of functional block)(signal)(state)(reference)(state)

for inputs

and t

(first two letters of functional block)(reference)(state)(signal)(state)

for outputs. For example, t

I2DVKH

symbolizes I2C timing (I2) with

respect to the time data input signals (D) reach the valid state (V) relative to the t

I2C

clock reference (K) going to the high (H)

state or setup time. Also, t

I2SXKL

symbolizes I2C timing (I2) for the time that the data with respect to the start condition (S)

goes invalid (X) relative to the t

I2C

clock reference (K) going to the low (L) state or hold time. Also, t

I2PVKH

symbolizes I2C

timing (I2) for the time that the data with respect to the stop condition (P) reaches the valid state (V) relative to the t

I2C

clock
reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate
letter: R (rise) or F (fall).

2. The device provides a hold time of at least 300 ns for the SDA signal (referred to the V

IH

(min) of the SCL signal) to bridge

the undefined region of the falling edge of SCL.

3. The maximum t

I2DVKH

must be met only if the device does not stretch the LOW period (t

I2CL

) of the SCL signal.

4. C

B

= capacitance of one bus line in pF.

5.)The device does not follow the “I

2C-BUS Specifications” version 2.1 regarding the tI2CF AC parameter.

Tab l e 43 . I2C AC Electrical Specifications (continued)

Parameter Symbol

1

Min Max Unit

Output

Z0 = 50 Ω

OVDD/2

R

L

= 50 Ω

SrS

SDA

SCL

t

I2CF

t

I2SXKL

t

I2CL

t

I2CH

t

I2DXKL

t

I2DVKH

t

I2SXKL

t

I2SVKH

t

I2KHKL

t

I2PVKH

t

I2CR

t

I2CF

PS

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Freescale Semiconductor 47

PCI

13 PCI

This section describes the DC and AC electrical specifications for the PCI bus of the MPC8349EA.

13.1 PCI DC Electrical Characteristics

Table 44 provides the DC electrical characteristics for the PCI interface of the MPC8349EA.

13.2 PCI AC Electrical Specifications

This section describes the general AC timing parameters of the PCI bus of the MPC8349EA. Note that the
PCI_CLK or PCI_SYNC_IN signal is used as the PCI input clock depending on whether the device is
configured as a host or agent device. Table 45 provides the PCI AC timing specifications at 66 MHz.

Table 44. PCI DC Electrical Characteristics

Parameter Symbol Test Condition Min Max Unit

High-level input voltage V

IH

V

OUT

≥ VOH (min) or 2 OVDD+0.3 V

Low-level input voltage V

IL

V

OUT

≤ VOL (max) –0.3 0.8 V

Input current I

IN

V

IN

1

= 0 V or VIN = OV

DD

—±5 μA

High-level output voltage V

OH

OVDD = min,

IOH = –100 μA

OVDD–0.2 — V

Low-level output voltage V

OL

OVDD = min,
I

OL

= 100 μA

—0.2V

Note:

1. The symbol V

IN

, in this case, represents the OVIN symbol referenced in Ta bl e 1.

Table 45. PCI AC Timing Specifications at 66 MHz

1

Parameter Symbol

2

Min Max Unit Notes

Clock to output valid t

PCKHOV

—6.0ns3

Output hold from clock t

PCKHOX

1—ns3

Clock to output high impedance t

PCKHOZ

—14ns3, 4

Input setup to clock t

PCIVKH

3.0 — ns 3, 5

Input hold from clock t

PCIXKH

0 — ns 3, 5

REQ64 to PORESET setup time t

PCRVRH

5 — clocks 6

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PCI

Table 46 provides the PCI AC timing specifications at 33 MHz.

PORESET to REQ64 hold time t

PCRHRX

050ns6

Notes:

1. PCI timing depends on M66EN and the ratio between PCI1/PCI2. Refer to the PCI chapter of the reference manual for a
description of M66EN.

2. The symbols for timing specifications follow the pattern of t

(first two letters of functional block)(signal)(state)(reference)(state)

for inputs

and t

(first two letters of functional block)(reference)(state)(signal)(state)

for outputs. For example, t

PCIVKH

symbolizes PCI timing (PC) with

respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, t

SYS

, reference (K) going

to the high (H) state or setup time. Also, t

PCRHFV

symbolizes PCI timing (PC) with respect to the time hard reset (R) went

high (H) relative to the frame signal (F) going to the valid (V) state.

3. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications.

4. For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the
component pin is less than or equal to the leakage current specification.

5. Input timings are measured at the pin.

6. The setup and hold time is with respect to the rising edge of PO

RESET.

Table 46. PCI AC Timing Specifications at 33 MHz

Parameter Symbol

1

Min Max Unit Notes

Clock to output valid t

PCKHOV

—11ns2

Output hold from clock t

PCKHOX

2—ns2

Clock to output high impedance t

PCKHOZ

—14ns2, 3

Input setup to clock t

PCIVKH

3.0 — ns 2, 4

Input hold from clock t

PCIXKH

0 — ns 2, 4

REQ64 to PORESET setup time t

PCRVRH

5 — clocks 5

PORESET to REQ64 hold time t

PCRHRX

050ns5

Notes:

1. The symbols for timing specifications follow the pattern of t

(first two letters of functional block)(signal)(state)(reference)(state)

for inputs

and t

(first two letters of functional block)(reference)(state)(signal)(state)

for outputs. For example, t

PCIVKH

symbolizes PCI timing (PC) with

respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, t

SYS

, reference (K) going

to the high (H) state or setup time. Also, t

PCRHFV

symbolizes PCI timing (PC) with respect to the time hard reset (R) went

high (H) relative to the frame signal (F) going to the valid (V) state.

2. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications.

3. For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the
component pin is less than or equal to the leakage current specification.

4. Input timings are measured at the pin.

5. The setup and hold time is with respect to the rising edge of PO

RESET.

Table 45. PCI AC Timing Specifications at 66 MHz1 (continued)

Parameter Symbol

2

Min Max Unit Notes

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Freescale Semiconductor 49

Timers

Figure 34 provides the AC test load for PCI.

Figure 34. PCI AC Test Load

Figure 35 shows the PCI input AC timing diagram.

Figure 35. PCI Input AC Timing Diagram

Figure 36 shows the PCI output AC timing diagram.

Figure 36. PCI Output AC Timing Diagram

14 Timers

This section describes the DC and AC electrical specifications for the timers.

14.1 Timer DC Electrical Characteristics

Table 47 provides the DC electrical characteristics for the MPC8349EA timer pins, including TIN, TOUT ,

TGATE

, and RTC_CLK.

Table 47. Timer DC Electrical Characteristics

Parameter Symbol Condition Min Max Unit

Input high voltage V

IH

—2.0OV

DD

+0.3 V

Input low voltage V

IL

—–0.30.8V

Input current I

IN

——±5μA

Output high voltage V

OH

I

OH

= –8.0 mA 2.4 — V

Output

Z0 = 50 Ω

OVDD/2

R

L

= 50 Ω

t

PCIVKH

CLK

Input

t

PCIXKH

CLK

Output Delay

t

PCKHOV

High-Impedance

t

PCKHOZ

Output

t

PCKHOX

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50 Freescale Semiconductor

GPIO

14.2 Timer AC Timing Specifications

Table 48 provides the timer input and output AC timing specifications.

15 GPIO

This section describes the DC and AC electrical specifications for the GPIO.

15.1 GPIO DC Electrical Characteristics

Table 49 provides the DC electrical characteristics for the MPC8349EA GPIO.

Output low voltage V

OL

IOL = 8.0 mA — 0.5 V

Output low voltage V

OL

IOL = 3.2 mA — 0.4 V

Table 48. Timers Input AC Timing Specifications

1

Parameter Symbol

2

Min Unit

Timers inputs—minimum pulse width t

TIWID

20 ns

Notes:

1. Input specifications are measured from the 50 percent level of the signal to the 50 percent level of the rising edge of CLKIN.
Timings are measured at the pin.

2. Timer inputs and outputs are asynchronous to any visible clock. Timer outputs should be synchronized before use by external
synchronous logic. Timer inputs are required to be valid for at least t

TIWID

ns to ensure proper operation.

Table 49. GPIO DC Electrical Characteristics

PArameter Symbol Condition Min Max Unit

Input high voltage V

IH

—2.0OV

DD

+0.3 V

Input low voltage V

IL

—–0.30.8V

Input current I

IN

——±5μA

Output high voltage V

OH

I

OH

= –8.0 mA 2.4 — V

Output low voltage V

OL

IOL = 8.0 mA — 0.5 V

Output low voltage V

OL

IOL = 3.2 mA — 0.4 V

Table 47. Timer DC Electrical Characteristics (continued)

Parameter Symbol Condition Min Max Unit

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Freescale Semiconductor 51

IPIC

15.2 GPIO AC Timing Specifications

Table 50 provides the GPIO input and output AC timing specifications.

16 IPIC

This section describes the DC and AC electrical specifications for the external interrupt pins.

16.1 IPIC DC Electrical Characteristics

Table 51 provides the DC electrical characteristics for the external interrupt pins.

16.2 IPIC AC Timing Specifications

Table 52 provides the IPIC input and output AC timing specifications.

Table 50. GPIO Input AC Timing Specifications

1

Parameter Symbol

2

Min Unit

GPIO inputs—minimum pulse width t

PIWID

20 ns

Notes:

1. Input specifications are measured from the 50 percent level of the signal to the 50 percent level of the rising edge of CLKIN.
Timings are measured at the pin.

2. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by external
synchronous logic. GPIO inputs must be valid for at least t

PIWID

ns to ensure proper operation.

Table 51. IPIC DC Electrical Characteristics

1

Parameter Symbol Condition Min Max Unit Notes

Input high voltage V

IH

—2.0OV

DD

+0.3 V —

Input low voltage V

IL

—–0.30.8V—

Input current I

IN

——±5μA—

Output low voltage V

OL

IOL = 8.0 mA — 0.5 V 2

Output low voltage V

OL

IOL = 3.2 mA — 0.4 V 2

Notes:

1. This table applies for pins IRQ

[0:7], IRQ_OUT, and MCP_OUT.

2. IRQ_OUT

and MCP_OUT are open-drain pins; thus VOH is not relevant for those pins.

Table 52. IPIC Input AC Timing Specifications

1

Parameter Symbol

2

Min Unit

IPIC inputs—minimum pulse width t

PICWID

20 ns

Notes:

1. Input specifications are measured at the 50 percent level of the IPIC input signals. Timings are measured at the pin.

2. IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by external
synchronous logic. IPIC inputs must be valid for at least t

PICWID

ns to ensure proper operation in edge triggered mode.

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52 Freescale Semiconductor

SPI

17 SPI

This section describes the SPI DC and AC electrical specifications.

17.1 SPI DC Electrical Characteristics

Table 53 provides the SPI DC electrical characteristics.

17.2 SPI AC Timing Specifications

Table 54 provides the SPI input and output AC timing specifications.

Table 53. SPI DC Electrical Characteristics

Parameter Symbol Condition Min Max Unit

Input high voltage V

IH

—2.0OV

DD

+0.3 V

Input low voltage V

IL

—–0.30.8V

Input current I

IN

——±5μA

Output high voltage V

OH

I

OH

= –8.0 mA 2.4 — V

Output low voltage V

OL

IOL = 8.0 mA — 0.5 V

Output low voltage V

OL

IOL = 3.2 mA — 0.4 V

Table 54. SPI AC Timing Specifications

1

Parameter Symbol

2

Min Max Unit

SPI outputs valid—Master mode (internal clock) delay t

NIKHOV

—6ns

SPI outputs hold—Master mode (internal clock) delay t

NIKHOX

0.5 — ns

SPI outputs valid—Slave mode (external clock) delay t

NEKHOV

—8ns

SPI outputs hold—Slave mode (external clock) delay t

NEKHOX

2—ns

SPI inputs—Master mode (internal clock input setup time t

NIIVKH

4—ns

SPI inputs—Master mode (internal clock input hold time t

NIIXKH

0—ns

SPI inputs—Slave mode (external clock) input setup time t

NEIVKH

4—ns

SPI inputs—Slave mode (external clock) input hold time t

NEIXKH

2—ns

Notes:

1. Output specifications are measured from the 50 percent level of the rising edge of CLKIN to the 50 percent level of the signal.
Timings are measured at the pin.

2. The symbols for timing specifications follow the pattern of t

(first two letters of functional block)(signal)(state)(reference)(state)

for inputs

and t

(first two letters of functional block)(reference)(state)(signal)(state)

for outputs. For example, t

NIKHOX

symbolizes the internal timing

(NI) for the time SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X).

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Freescale Semiconductor 53

Package and Pin Listings

Figure 37 provides the AC test load for the SPI.

Figure 37. SPI AC Test Load

Figure 38 and Figure 39 represent the AC timings from Table 54. Note that although the specifications

generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge
is the active edge.

Figure 38 shows the SPI timings in slave mode (external clock).

Figure 38. SPI AC Timing in Slave Mode (External Clock) Diagram

Figure 39 shows the SPI timings in master mode (internal clock).

Figure 39. SPI AC Timing in Master Mode (Internal Clock) Diagram

18 Package and Pin Listings

This section details package parameters, pin assignments, and dimensions. The MPC8349EA is available
in a tape ball grid array (TBGA). See Section 18.1, “Package Parameters for the MPC8349EA TBGA” and

Section 18.2, “Mechanical Dimensions for the MPC8349EA TBGA.

Output

Z0 = 50 Ω

OVDD/2

R

L

= 50 Ω

SPICLK (Input)

t

NEIXKH

t

NEIVKH

t

NEKHOX

Input Signals:

SPIMOSI

(See Note)

Output Signals:

SPIMISO

(See Note)

Note: The clock edge is selectable on SPI.

SPICLK (Output)

t

NIIXKH

t

NIKHOX

Input Signals:

SPIMISO

(See Note)

Output Signals:

SPIMOSI

(See Note)

Note: The clock edge is selectable on SPI.

t

NIIVKH

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Package and Pin Listings

18.1 Package Parameters for the MPC8349EA TBGA

The package parameters are provided in the following list. The package type is 35 mm × 35 mm, 672 tape
ball grid array (TBGA).

Package outline 35 mm × 35 mm
Interconnects 672
Pitch 1.00 mm
Module height (typical) 1.46 mm
Solder balls 62 Sn/36 Pb/2 Ag (ZU package)

96.5 Sn/3.5Ag (VV package)

Ball diameter (typical) 0.64 mm

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Package and Pin Listings

18.2 Mechanical Dimensions for the MPC8349EA TBGA

Figure 40 shows the mechanical dimensions and bottom surface nomenclature for the MPC8349EA,

672-TBGA package.

Figure 40. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC8349EA TBGA

Notes:

1. All dimensions are in millimeters.

2. Dimensions and tolerances per ASME Y14.5M-1994.

3. Maximum solder ball diameter measured parallel to datum A.

4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls.

5. Parallelism measurement must exclude any effect of mark on top surface of package.

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Package and Pin Listings

18.3 Pinout Listings

Table 55 provides the pin-out listing for the MPC8349EA, 672 TBGA package.

Table 55. MPC8349EA (TBGA) Pinout Listing

Signal Package Pin Number Pin Type

Power

Supply

Notes

PCI1 and PCI2 (One 64-Bit or Two 32-Bit)

PCI1_INTA

/IRQ_OUT B34 O OV

DD

2

PCI1_RESET_OUT C33 O OV

DD

—

PCI1_AD[31:0] G30, G32, G34, H31, H32, H33, H34, J29,

J32, J33, L30, K31, K33, K34, L33, L34,

P34, R29, R30, R33, R34, T31, T32, T33,

U31, U34, V31, V32, V33, V34, W33, W34

I/O OV

DD

—

PCI1_C/BE

[3:0] J30, M31, P33, T34 I/O OV

DD

—

PCI1_PAR P32 I/O OV

DD

—

PCI1_FRAME M32 I/O OV

DD

5

PCI1_TRDY N29 I/O OV

DD

5

PCI1_IRDY M34 I/O OV

DD

5

PCI1_STOP N31 I/O OV

DD

5

PCI1_DEVSEL N30 I/O OV

DD

5

PCI1_IDSEL J31 I OV

DD

—

PCI1_SERR N34 I/O OV

DD

5

PCI1_PERR N33 I/O OV

DD

5

PCI1_REQ[0] D32 I/O OV

DD

—

PCI1_REQ[1]/CPCI1_HS_ES D34 I OV

DD

—

PCI1_REQ[2:4] E34, F32, G29 I OV

DD

—

PCI1_GNT0

C34 I/O OV

DD

—

PCI1_GNT1/CPCI1_HS_LED D33 O OV

DD

—

PCI1_GNT2/CPCI1_HS_ENUM E33 O OV

DD

—

PCI1_GNT[3:4] F31, F33 O OV

DD

—

PCI2_RESET_OUT/GPIO2[0] W32 I/O OV

DD

—

PCI2_AD[31:0]/PCI1[63:32] AA33, AA34, AB31, AB32, AB33, AB34,

AC29, AC31, AC33, AC34, AD30, AD32,

AD33, AD34, AE29, AE30, AH32, AH33,

AH34, AM33, AJ31, AJ32, AJ33, AJ34,

AK32, AK33, AK34, AM34, AL33, AL34,

AK31, AH30

I/O OV

DD

—

PCI2_C/BE

[3:0]/PCI1_C/BE[7:4] AC32, AE32, AH31, AL32 I/O OV

DD

—

PCI2_PAR/PCI1_PAR64 AG34 I/O OV

DD

—

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Package and Pin Listings

PCI2_FRAME/GPIO2[1] AE33 I/O OV

DD

5

PCI2_TRDY/GPIO2[2] AF32 I/O OV

DD

5

PCI2_IRDY/GPIO2[3] AE34 I/O OV

DD

5

PCI2_STOP/GPIO2[4] AF34 I/O OV

DD

5

PCI2_DEVSEL/GPIO2[5] AF33 I/O OV

DD

5

PCI2_SERR/PCI1_ACK64 AG33 I/O OV

DD

5

PCI2_PERR/PCI1_REQ64 AG32 I/O OV

DD

5

PCI2_REQ[0:2]/GPIO2[6:8] Y32, Y34, AA32 I/O OV

DD

—

PCI2_GNT[0:2]/GPIO2[9:11] Y31, Y33, AA31 I/O OV

DD

—

M66EN A19 I OV

DD

—

DDR SDRAM Memory Interface

MDQ[0:63] D5, A3, C3, D3, C4, B3, C2, D4, D2, E5,

G2, H6, E4, F3, G4, G3, H1, J2, L6, M6,
H2, K6, L2, M4, N2, P4, R2, T4, P6, P3,

R1, T2, AB5, AA3, AD6, AE4, AB4, AC2,

AD3, AE6, AE3, AG4, AK5, AK4, AE2,

AG6, AK3, AK2, AL2, AL1, AM5, AP5,

AM2, AN1, AP4, AN5, AJ7, AN7, AM8,

AJ9, AP6, AL7, AL9, AN8

I/O GV

DD

—

MECC[0:4]/MSRCID[0:4] W4, W3, Y3, AA6, T1 I/O GV

DD

—

MECC[5]/MDVAL U1 I/O GV

DD

—

MECC[6:7] Y1, Y6 I/O GV

DD

—

MDM[0:8] B1, F1, K1, R4, AD4, AJ1, AP3, AP7, Y4 O GV

DD

—

MDQS[0:8] B2, F5, J1, P2, AC1, AJ2, AN4, AL8, W2 I/O GV

DD

—

MBA[0:1] AD1, AA5 O GV

DD

—

MA[0:14] W1, U4, T3, R3, P1, M1, N1, L3, L1, K2,

Y2, K3, J3, AP2, AN6

OGVDD—

MWE

AF1 O GV

DD

—

MRAS AF4 O GV

DD

—

MCAS AG3 O GV

DD

—

MCS[0:3] AG2, AG1, AK1, AL4 O GV

DD

—

MCKE[0:1] H3, G1 O GV

DD

3

MCK[0:5] U2, F4, AM3, V3, F2, AN3 O GV

DD

—

MCK

[0:5] U3, E3, AN2, V4, E1, AM4 O GV

DD

—

MODT[0:3] AH3, AJ5, AH1, AJ4 O GV

DD

—

Table 55. MPC8349EA (TBGA) Pinout Listing (continued)

Signal Package Pin Number Pin Type

Power

Supply

Notes

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Package and Pin Listings

MBA[2] H4 O GV

DD

—

MDIC0 AB1 I/O — 9

MDIC1 AA1 I/O — 9

Local Bus Controller Interface

LAD[0:31] AM13, AP13, AL14, AM14, AN14, AP14,

AK15, AJ15, AM15, AN15, AP15, AM16,

AL16, AN16, AP16, AL17, AM17, AP17,
AK17, AP18, AL18, AM18, AN18, AP19,
AN19, AM19, AP20, AK19, AN20, AL20,

AP21, AN21

I/O OV

DD

—

LDP[0]/CKSTOP_OUT

AM21 I/O OV

DD

—

LDP[1]/CKSTOP_IN AP22 I/O OV

DD

—

LDP[2]/LCS[4] AN22 I/O OV

DD

—

LDP[3]/LCS[5] AM22 I/O OV

DD

—

LA[27:31] AK21, AP23, AN23, AP24, AK22 O OV

DD

—

LCS[0:3] AN24, AL23, AP25, AN25 O OV

DD

—

LWE [0:3]/LSDDQM[0:3]/LBS[0:3] AK23, AP26, AL24, AM25 O OV

DD

—

LBCTL AN26 O OV

DD

—

LALE AK24 O OV

DD

—

LGPL0/LSDA10/cfg_reset_source0 AP27 I/O OV

DD

—

LGPL1/LSDWE/cfg_reset_source1 AL25 I/O OV

DD

—

LGPL2/LSDRAS/LOE AJ24 O OV

DD

—

LGPL3/LSDCAS/cfg_reset_source2 AN27 I/O OV

DD

—

LGPL4/LGTA

/LUPWAIT/LPBSE AP28 I/O OV

DD

12

LGPL5/cfg_clkin_div AL26 I/O OV

DD

—

LCKE AM27 O OV

DD

—

LCLK[0:2] AN28, AK26, AP29 O OV

DD

—

LSYNC_OUT AM12 O OV

DD

—

LSYNC_IN AJ10 I OV

DD

—

General Purpose I/O Timers

GPIO1[0]/DMA_DREQ0/GTM1_TIN1/
GTM2_TIN2

F24 I/O OV

DD

—

GPIO1[1]/DMA_DACK0/
GTM1_TGATE1

/GTM2_TGATE2

E24 I/O OV

DD

—

Table 55. MPC8349EA (TBGA) Pinout Listing (continued)

Signal Package Pin Number Pin Type

Power

Supply

Notes

Electronic Component Distributor. Source::Freescale Semiconductor

P.N:MPC8349CZUAGDB Desc:IC MPU POWERQUICC II PRO 672TBGA
Web:http://www.hotenda.cn E-mail:[email protected] Phone:[phone]

MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13

Freescale Semiconductor 59

Package and Pin Listings

GPIO1[2]/DMA_DDONE0/
GTM1_TOUT1

B25 I/O OV

DD

—

GPIO1[3]/DMA_DREQ1/GTM1_TIN2/
GTM2_TIN1

D24

I/O

OV

DD

—

GPIO1[4]/DMA_DACK1

/

GTM1_TGATE2/GTM2_TGATE1

A25

I/O

OV

DD

—

GPIO1[5]/DMA_DDONE1/
GTM1_TOUT2/GTM2_TOUT1

B24

I/O

OV

DD

—

GPIO1[6]/DMA_DREQ2/GTM1_TIN3/
GTM2_TIN4

A24

I/O

OV

DD

—

GPIO1[7]/DMA_DACK2

/

GTM1_TGATE3/GTM2_TGATE4

D23

I/O

OV

DD

—

GPIO1[8]/DMA_DDONE2/
GTM1_TOUT3

B23

I/O

OV

DD

—

GPIO1[9]/DMA_DREQ3/GTM1_TIN4/
GTM2_TIN3

A23

I/O

OV

DD

—

GPIO1[10]/DMA_DACK3

/

GTM1_TGATE4/GTM2_TGATE3

F22

I/O

OV

DD

—

GPIO1[11]/DMA_DDONE3/
GTM1_TOUT4/GTM2_TOUT3

E22

I/O

OV

DD

—

USB Port 1

MPH1_D0_ENABLEN/
DR_D0_ENABLEN

A26 I/O OV

DD

—

MPH1_D1_SER_TXD/
DR_D1_SER_TXD

B26 I/O OV

DD

—

MPH1_D2_VMO_SE0/
DR_D2_VMO_SE0

D25 I/O OV

DD

—

MPH1_D3_SPEED/DR_D3_SPEED A27 I/O OV

DD

—

MPH1_D4_DP/DR_D4_DP B27 I/O OV

DD

—

MPH1_D5_DM/DR_D5_DM C27 I/O OV

DD

—

MPH1_D6_SER_RCV/
DR_D6_SER_RCV

D26 I/O OV

DD

—

MPH1_D7_DRVVBUS/
DR_D7_DRVVBUS

E26 I/O OV

DD

—

MPH1_NXT/DR_SESS_VLD_NXT D27 I OV

DD

—

MPH1_DIR_DPPULLUP/
DR_XCVR_SEL_DPPULLUP

A28 I/O OV

DD

—

MPH1_STP_SUSPEND/
DR_STP_SUSPEND

F26 O OV

DD

—

Table 55. MPC8349EA (TBGA) Pinout Listing (continued)

Signal Package Pin Number Pin Type

Power

Supply

Notes

Electronic Component Distributor. Source::Freescale Semiconductor

P.N:MPC8349CZUAGDB Desc:IC MPU POWERQUICC II PRO 672TBGA
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MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13

60 Freescale Semiconductor

Package and Pin Listings

MPH1_PWRFAULT/
DR_RX_ERROR_PWRFAULT

E27 I OV

DD

—

MPH1_PCTL0/DR_TX_VALID_PCTL0 A29 O OV

DD

—

MPH1_PCTL1/DR_TX_VALIDH_PCTL1 D28 O OV

DD

—

MPH1_CLK/DR_CLK B29 I OV

DD

—

USB Port 0

MPH0_D0_ENABLEN/

DR_D8_CHGVBUS

C29 I/O OV

DD

—

MPH0_D1_SER_TXD/
DR_D9_DCHGVBUS

A30 I/O OV

DD

—

MPH0_D2_VMO_SE0/DR_D10_DPPD E28 I/O OV

DD

—

MPH0_D3_SPEED/DR_D11_DMMD B30 I/O OV

DD

—

MPH0_D4_DP/DR_D12_VBUS_VLD C30 I/O OV

DD

—

MPH0_D5_DM/DR_D13_SESS_END A31 I/O OV

DD

—

MPH0_D6_SER_RCV/DR_D14 B31 I/O OV

DD

—

MPH0_D7_DRVVBUS/
DR_D15_IDPULLUP

C31 I/O OV

DD

—

MPH0_NXT/DR_RX_ACTIVE_ID B32 I OV

DD

—

MPH0_DIR_DPPULLUP/DR_RESET A32 I/O OV

DD

—

MPH0_STP_SUSPEND/
DR_TX_READY

A33 I/O OV

DD

—

MPH0_PWRFAULT/DR_RX_VALIDH C32 I OV

DD

—

MPH0_PCTL0/DR_LINE_STATE0 D31 I/O OV

DD

—

MPH0_PCTL1/DR_LINE_STATE1 E30 I/O OV

DD

—

MPH0_CLK/DR_RX_VALID B33 I OV

DD

—

Programmable Interrupt Controller

MCP_OUT AN33 O OV

DD

2

IRQ0/MCP_IN/GPIO2[12] C19 I/O OV

DD

—

IRQ[1:5]/GPIO2[13:17] C22, A22, D21, C21, B21 I/O OV

DD

—

IRQ[6]/GPIO2[18]/CKSTOP_OUT A21 I/O OV

DD

—

IRQ[7]/GPIO2[19]/CKSTOP_IN C20 I/O OV

DD

—

Ethernet Management Interface

EC_MDC A7 O LV

DD1

—

EC_MDIO E9 I/O LV

DD1

11

Table 55. MPC8349EA (TBGA) Pinout Listing (continued)

Signal Package Pin Number Pin Type

Power

Supply

Notes

Electronic Component Distributor. Source::Freescale Semiconductor

P.N:MPC8349CZUAGDB Desc:IC MPU POWERQUICC II PRO 672TBGA
Web:http://www.hotenda.cn E-mail:[email protected] Phone:[phone]

MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13

Freescale Semiconductor 61

Package and Pin Listings

Gigabit Reference Clock

EC_GTX_CLK125 C8 I LV

DD1

—

Three-Speed Ethernet Controller (Gigabit Ethernet 1)

TSEC1_COL/GPIO2[20] A17 I/O OV

DD

—

TSEC1_CRS/GPIO2[21] F12 I/O LV

DD1

—

TSEC1_GTX_CLK D10 O LV

DD1

3

TSEC1_RX_CLK A11 I LV

DD1

—

TSEC1_RX_DV B11 I LV

DD1

—

TSEC1_RX_ER/GPIO2[26] B17 I/O OV

DD

—

TSEC1_RXD[7:4]/GPIO2[22:25] B16, D16, E16, F16 I/O OV

DD

—

TSEC1_RXD[3:0] E10, A8, F10, B8 I LV

DD1

—

TSEC1_TX_CLK D17 I OV

DD

—

TSEC1_TXD[7:4]/GPIO2[27:30] A15, B15, A14, B14 I/O OV

DD

—

TSEC1_TXD[3:0] A10, E11, B10, A9 O LV

DD1

10

TSEC1_TX_EN B9 O LV

DD1

—

TSEC1_TX_ER/GPIO2[31] A16 I/O OV

DD

—

Three-Speed Ethernet Controller (Gigabit Ethernet 2)

TSEC2_COL/GPIO1[21] C14 I/O OV

DD

—

TSEC2_CRS/GPIO1[22] D6 I/O LV

DD2

—

TSEC2_GTX_CLK A4 O LV

DD2

—

TSEC2_RX_CLK B4 I LV

DD2

—

TSEC2_RX_DV/GPIO1[23] E6 I/O LV

DD2

—

TSEC2_RXD[7:4]/GPIO1[26:29] A13, B13, C13, A12 I/O OV

DD

—

TSEC2_RXD[3:0]/GPIO1[13:16] D7, A6, E8, B7 I/O LV

DD2

—

TSEC2_RX_ER/GPIO1[25] D14 I/O OV

DD

—

TSEC2_TXD[7]/GPIO1[31] B12 I/O OV

DD

—

TSEC2_TXD[6]/
DR_XCVR_TERM_SEL

C12 O OV

DD

—

TSEC2_TXD[5]/
DR_UTMI_OPMODE1

D12 O OV

DD

—

TSEC2_TXD[4]/
DR_UTMI_OPMODE0

E12 O OV

DD

—

TSEC2_TXD[3:0]/GPIO1[17:20] B5, A5, F8, B6 I/O LV

DD2

—

Table 55. MPC8349EA (TBGA) Pinout Listing (continued)

Signal Package Pin Number Pin Type

Power

Supply

Notes

Electronic Component Distributor. Source::Freescale Semiconductor

P.N:MPC8349CZUAGDB Desc:IC MPU POWERQUICC II PRO 672TBGA
Web:http://www.hotenda.cn E-mail:[email protected] Phone:[phone]

MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13

62 Freescale Semiconductor

Package and Pin Listings

TSEC2_TX_ER/GPIO1[24] F14 I/O OV

DD

—

TSEC2_TX_EN/GPIO1[12] C5 I/O LV

DD2

—

TSEC2_TX_CLK/GPIO1[30] E14 I/O OV

DD

—

DUART

UART_SOUT[1:2]/MSRCID[0:1]/
LSRCID[0:1]

AK27, AN29 O OV

DD

—

UART_SIN[1:2]/MSRCID[2:3]/

LSRCID[2:3]

AL28, AM29 I/O OV

DD

—

UART_CTS

[1]/MSRCID4/LSRCID4 AP30 I/O OV

DD

—

UART_CTS[2]/MDVAL/ LDVAL AN30 I/O OV

DD

—

UART_RTS[1:2] AP31, AM30 O OV

DD

—

I2C interface

IIC1_SDA AK29 I/O OV

DD

2

IIC1_SCL AP32 I/O OV

DD

2

IIC2_SDA AN31 I/O OV

DD

2

IIC2_SCL AM31 I/O OV

DD

2

SPI

SPIMOSI/LCS[6] AN32 I/O OV

DD

—

SPIMISO/LCS[7] AP33 I/O OV

DD

—

SPICLK AK30 I/O OV

DD

—

SPISEL AL31 I OV

DD

—

Clocks

PCI_CLK_OUT[0:2] AN9, AP9, AM10, O OV

DD

—

PCI_CLK_OUT[3]/LCS[6] AN10 O OV

DD

—

PCI_CLK_OUT[4]/LCS[7] AJ11 O OV

DD

—

PCI_CLK_OUT[5:7] AP10, AL11, AM11 O OV

DD

—

PCI_SYNC_IN/PCI_CLOCK AK12 I OV

DD

—

PCI_SYNC_OUT AP11 O OV

DD

3

RTC/PIT_CLOCK AM32 I OV

DD

—

CLKIN AM9 I OV

DD

—

JTAG

TCK E20 I OV

DD

—

TDI F20 I OV

DD

4

Table 55. MPC8349EA (TBGA) Pinout Listing (continued)

Signal Package Pin Number Pin Type

Power

Supply

Notes

Electronic Component Distributor. Source::Freescale Semiconductor

P.N:MPC8349CZUAGDB Desc:IC MPU POWERQUICC II PRO 672TBGA
Web:http://www.hotenda.cn E-mail:[email protected] Phone:[phone]

MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13

Freescale Semiconductor 63

Package and Pin Listings

TDO B20 O OV

DD

3

TMS A20 I OV

DD

4

TRST B19 I OV

DD

4

Test

TEST D22 I OV

DD

6

TEST_SEL AL13 I OV

DD

6

PMC

QUIESCE A18 O OV

DD

—

System Control

PORESET C18 I OV

DD

—

HRESET B18 I/O OV

DD

1

SRESET D18 I/O OV

DD

2

Thermal Management

THERM0 K32 I — 8

Power and Ground Signals

AVDD1 L31 Power for e300

PLL (1.2 V

nominal, 1.3 V

for 667 MHz)

AVDD1—

AV

DD

2 AP12 Power for

system PLL (1.2

V nominal, 1.3 V

for 667 MHz)

AVDD2—

AV

DD

3 AE1 Power for DDR

DLL (1.2 V

nominal, 1.3 V

for 667 MHz)

——

AV

DD

4 AJ13 Power for LBIU

DLL (1.2 V

nominal, 1.3 V

for 667 MHz)

AVDD4—

Table 55. MPC8349EA (TBGA) Pinout Listing (continued)

Signal Package Pin Number Pin Type

Power

Supply

Notes

Electronic Component Distributor. Source::Freescale Semiconductor

P.N:MPC8349CZUAGDB Desc:IC MPU POWERQUICC II PRO 672TBGA
Web:http://www.hotenda.cn E-mail:[email protected] Phone:[phone]

MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13

64 Freescale Semiconductor

Package and Pin Listings

GND A1, A34, C1, C7, C10, C11, C15, C23,

C25, C28, D1, D8, D20, D30, E7, E13,

E15, E17, E18, E21, E23, E25, E32, F6,

F19, F27, F30, F34, G31, H5, J4, J34, K30,

L5, M2, M5, M30, M33, N3, N5, P30, R5,

R32, T5, T30, U6, U29, U33, V2, V5, V30,

W6, W30, Y30, AA2, AA30, AB2, AB6,

AB30, AC3, AC6, AD31, AE5, AF2, AF5,

AF31, AG30, AG31, AH4, AJ3, AJ19,

AJ22, AK7, AK13, AK14, AK16, AK18,

AK20, AK25, AK28, AL3, AL5, AL10,

AL12, AL22, AL27, AM1, AM6, AM7,

AN12, AN17, AN34, AP1, AP8, AP34

———

GV

DD

A2, E2, G5, G6, J5, K4, K5, L4, N4, P5, R6,
T6, U5, V1, W5, Y5, AA4, AB3, AC4, AD5,

AF3, AG5, AH2, AH5, AH6, AJ6, AK6,

AK8, AK9, AL6

Power for DDR

DRAM I/O

voltage

(2.5 V)

GV

DD

—

LV

DD1

C9, D11 Power for three

speed Ethernet

#1 and for

Ethernet

management

interface I/O

(2.5 V, 3.3 V)

LV

DD1

—

LV

DD2

C6, D9 Power for three

speed Ethernet

#2 I/O (2.5 V,

3.3 V)

LV

DD2

—

V

DD

E19, E29, F7, F9, F11,F13, F15, F17, F18,

F21, F23, F25, F29, H29, J6, K29, M29,

N6, P29, T29, U30, V6, V29, W29, AB29,

AC5, AD29, AF6, AF29, AH29, AJ8, AJ12,

AJ14, AJ16, AJ18, AJ20, AJ21, AJ23,
AJ25, AJ26, AJ27, AJ28, AJ29, AK10

Power for core

(1.2 V nominal,

1.3 V for

667 MHz)

V

DD

—

OV

DD

B22, B28, C16, C17, C24, C26, D13, D15,

D19, D29, E31, F28, G33, H30, L29, L32,

N32, P31, R31, U32, W31, Y29, AA29,

AC30, AE31, AF30, AG29, AJ17, AJ30,

AK11, AL15, AL19, AL21, AL29, AL30,

AM20, AM23, AM24, AM26, AM28, AN11,

AN13

PCI, 10/100

Ethernet, and

other standard

(3.3 V)

OV

DD

—

MVREF1 M3 I DDR

reference

voltage

—

Table 55. MPC8349EA (TBGA) Pinout Listing (continued)

Signal Package Pin Number Pin Type

Power

Supply

Notes

Electronic Component Distributor. Source::Freescale Semiconductor

P.N:MPC8349CZUAGDB Desc:IC MPU POWERQUICC II PRO 672TBGA
Web:http://www.hotenda.cn E-mail:[email protected] Phone:[phone]

MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13

Freescale Semiconductor 65

Package and Pin Listings

MVREF2 AD2 I DDR

reference

voltage

—

Notes:

1. This pin is an open-drain signal. A weak pull-up resistor (1 kΩ) should be placed on this pin to OVDD.

2. This pin is an open-drain signal. A weak pull-up resistor (2–10 kΩ) should be placed on this pin to OV

DD

.

3. During reset, this output is actively driven rather than three-stated.

4. These JTAG pins have weak internal pull-up P-FETs that are always enabled.

5. This pin should have a weak pull-up if the chip is in PCI host mode. Follow the PCI specifications.

6. This pin must always be tied to GND.

7. This pin must always be left not connected.

8. Thermal sensitive resistor.

9. It is recommended that MDIC0 be tied to GND using an 18.2 Ω resistor and MDIC1 be tied to DDR power using an 18.2 Ω
resistor.

10.TSEC1_TXD[3] is required an external pull-up resistor. For proper functionality of the device, this pin must be pulled up or
actively driven high during a hard reset. No external pull-down resistors are allowed to be attached to this net.

11. A weak pull-up resistor (2–10 kΩ) should be placed on this pin to LV

DD1

.

12. For systems that boot from local bus (GPCM)-controlled NOR flash, a pullup on LGPL4 is required.

Table 55. MPC8349EA (TBGA) Pinout Listing (continued)

Signal Package Pin Number Pin Type

Power

Supply

Notes

Electronic Component Distributor. Source::Freescale Semiconductor

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Web:http://www.hotenda.cn E-mail:[email protected] Phone:[phone]

MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13

66 Freescale Semiconductor

Clocking

19 Clocking

Figure 41 shows the internal distribution of the clocks.

Figure 41. MPC8349EA Clock Subsystem

The primary clock source can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device
is configured in PCI host or PCI agent mode. When the MPC8349EA is configured as a PCI host device,
CLKIN is its primary input clock. CLKIN feeds the PCI clock divider (÷2) and the multiplexors for
PCI_SYNC_OUT and PCI_CLK_OUT. The CFG_CLKIN_DIV configuration input selects whether
CLKIN or CLKIN/2 is driven out on the PCI_SYNC_OUT signal. The OCCR[PCICDn] parameters select
whether CLKIN or CLKIN/2 is driven out on the PCI_CLK_OUTn signals.

PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subsystem to
synchronize to the system PCI clocks. PCI_SYNC_OUT must be connected properly to PCI_SYNC_IN,
with equal delay to all PCI agent devices in the system, to allow the MPC8349EA to function. When the
device is configured as a PCI agent device, PCI_CLK is the primary input clock and the CLKIN signal
should be tied to GND.

Core PLL

System PLL

DDR

LBIU

LSYNC_IN

LSYNC_OUT

LCLK[0:2]

MCK[0:5]

MCK

[0:5]

core_clk

e300 Core

csb_clk to Rest

CLKIN

csb_clk

6

6

DDR
Memory

Local Bus

PCI_CLK_OUT[0:7]

PCI_SYNC_OUT

PCI_CLK/

Clock

Unit

of the Device

ddr_clk

lbiu_clk

CFG_CLKIN_DIV

PCI Clock

PCI_SYNC_IN

Device

Memory
Device

/n

To Local Bus

Memory

Controller

To DDR
Memory

Controller

DLL

Clock

Div

/2

Divider

8

Electronic Component Distributor. Source::Freescale Semiconductor

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MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13

Freescale Semiconductor 67

Clocking

As shown in Figure 41, the primary clock input (frequency) is multiplied up by the system phase-locked
loop (PLL) and the clock unit to create the coherent system bus clock (csb_clk), the internal clock for the
DDR controller (ddr_clk), and the internal clock for the local bus interface unit (lbiu_clk).

The csb_clk frequency is derived from a complex set of factors that can be simplified into the following
equation:

csb_clk = {PCI_SYNC_IN × (1 + CFG_CLKIN_DIV)} × SPMF
In PCI host mode, PCI_SYNC_IN × (1 + CFG_CLKIN_DIV) is the CLKIN frequency.
The csb_clk serves as the clock input to the e300 core. A second PLL inside the e300 core multiplies the

csb_clk frequency to create the internal clock for the e300 core (core_clk). The system and core PLL
multipliers are selected by the SPMF and COREPLL fields in the reset configuration word low (RCWL),
which is loaded at power-on reset or by one of the hard-coded reset options. See the chapter on reset,
clocking, and initialization in the MPC8349EA Reference Manual for more information on the clock
subsystem.

The internal ddr_clk frequency is determined by the following equation:

ddr_clk = csb_clk × (1 + RCWL[DDRCM])
ddr_clk is not the external memory bus frequency; ddr_clk passes through the DDR clock divider (÷2) to

create the differential DDR memory bus clock outputs (MCK and MCK). However, the data rate is the
same frequency as ddr_clk.

The internal lbiu_clk frequency is determined by the following equation:

lbiu_clk = csb_clk × (1 + RCWL[LBIUCM])
lbiu_clk is not the external local bus frequency; lbiu_clk passes through the LBIU clock divider to create

the external local bus clock outputs (LSYNC_OUT and LCLK[0:2]). The LBIU clock divider ratio is
controlled by LCCR[CLKDIV].

In addition, some of the internal units may have to be shut off or operate at lower frequency than the
csb_clk frequency. Those units have a default clock ratio that can be configured by a memory-mapped
register after the device exits reset. Table 56 specifies which units have a configurable clock frequency.

Table 56. Configurable Clock Units

Unit Default Frequency Options

TSEC1 csb_clk/3 Off, csb_clk, csb_clk/2, csb_clk/3

TSEC2, I2C1 csb_clk/3 Off, csb_clk, csb_clk/2, csb_clk/3

Security core csb_clk/3 Off, csb_clk, csb_clk/2, csb_clk/3

USB DR, USB MPH csb_clk/3 Off, csb_clk, csb_clk/2, csb_clk/3

PCI1, PCI2 and DMA complex csb_clk Off, csb_clk

Electronic Component Distributor. Source::Freescale Semiconductor

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MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13

68 Freescale Semiconductor

Clocking

Table 57 provides the operating frequencies for the MPC8349EA TBGA under recommended operating

conditions (see Table 2).

All frequency combinations shown in the table below may not be available. Maximum operating
frequencies depend on the part ordered, see Section 22.1, “Part Numbers Fully Addressed by This

Document,” for part ordering details and contact your Freescale Sales Representative or authorized

distributor for more information.

19.1 System PLL Configuration

The system PLL is controlled by the RCWL[SPMF] parameter. Table 58 shows the multiplication factor
encodings for the system PLL.

Table 57. Operating Frequencies for TBGA

Characteristic

1

1

The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen so that the resulting csb_clk, MCK,
LCLK[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. The value of
SCCR[ENCCM], SCCR[USBDRCM] and SCCR[USBMPHCM] must be programmed so that the maximum internal operating
frequency of the security core and USB modules does not exceed the respective values listed in this table.

400 MHz 533 MHz 667 MHz Unit

e300 core frequency (core_clk) 266–400 266–533 266–667 MHz

Coherent system bus frequency (csb_clk) 100–266 100–333 100–333 MHz

DDR1 memory bus frequency (MCK)

2

2

The DDR data rate is 2x the DDR memory bus frequency.

100–133 100–133 100–166.67 MHz

DDR2 memory bus frequency (MCK)

3

3

The DDR data rate is 2x the DDR memory bus frequency.

100–133 100–133 100–200 MHz

Local bus frequency (LCLKn)

4

4

The local bus frequency is 1/2, 1/4, or 1/8 of the lbiu_clk frequency (depending on LCCR[CLKDIV]) which is in turn 1x or 2x the
csb_clk frequency (depending on RCWL[LBIUCM]).

16.67–133 16.67–133 16.67–133 MHz

PCI input frequency (CLKIN or PCI_CLK) 25–66 25–66 25–66 MHz

Security core maximum internal operating frequency 133 133 166 MHz

USB_DR, USB_MPH maximum internal operating frequency 133 133 166 MHz

Table 58. System PLL Multiplication Factors

RCWL[SPMF] System PLL Multiplication Factor

0000 × 16

0001 Reserved

0010 × 2

0011 × 3

0100 × 4

0101 × 5

0110 × 6

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Clocking

As described in Section 19, “Clocking,” the LBIUCM, DDRCM, and SPMF parameters in the reset
configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the
primary clock input (CLKIN or PCI_CLK) and the internal coherent system bus clock (csb_clk). Table 59
and Table 60 show the expected frequency values for the CSB frequency for select csb_clk to
CLKIN/PCI_SYNC_IN ratios.

0111 × 7

1000 × 8

1001 × 9

1010 × 10

1011 × 11

1100 × 12

1101 × 13

1110 × 14

1111 × 15

Table 59. CSB Frequency Options for Host Mode

CFG_CLKIN_DIV

at Reset

1

SPMF

csb_clk :

Input Clock Ratio

2

Input Clock Frequency (MHz)

2

16.67 25 33.33 66.67

csb_clk Frequency (MHz)

Low 0010 2 : 1

133

Low 0011 3 : 1 100 200

Low 0100 4 : 1 100 133 266

Low 0101 5 : 1 125 166 333

Table 58. System PLL Multiplication Factors (continued)

RCWL[SPMF] System PLL Multiplication Factor

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Clocking

Low 0110 6 : 1 100 150 200

Low 0111 7 : 1 116 175 233

Low 1000 8 : 1 133 200 266

Low 1001 9 : 1 150 225 300

Low 1010 10 : 1 166 250 333

Low 1011 11 : 1 183 275

Low 1100 12 : 1 200 300

Low 1101 13 : 1 216 325

Low 1110 14 : 1 233

Low 1111 15 : 1 250

Low 0000 16 : 1 266

High 0010 2 : 1 133

High 0011 3 : 1 100 200

High 0100 4 : 1 133 266

High 0101 5 : 1 166 333

High 0110 6 : 1 200

High 0111 7 : 1 233

High 1000 8 : 1

1

CFG_CLKIN_DIV selects the ratio between CLKIN and PCI_SYNC_OUT.

2

CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.

Table 60. CSB Frequency Options for Agent Mode

CFG_CLKIN_DIV

at Reset

1

SPMF

csb_clk :

Input Clock Ratio

2

Input Clock Frequency (MHz)

2

16.67 25 33.33 66.67

csb_clk Frequency (MHz)

Low 0010 2 : 1

133

Low 0011 3 : 1 100 200

Low 0100 4 : 1 100 133 266

Low 0101 5 : 1 125 166 333

Table 59. CSB Frequency Options for Host Mode (continued)

CFG_CLKIN_DIV

at Reset

1

SPMF

csb_clk :

Input Clock Ratio

2

Input Clock Frequency (MHz)

2

16.67 25 33.33 66.67

csb_clk Frequency (MHz)

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Clocking

19.2 Core PLL Configuration

RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300
core clock (core_clk). Table 61 shows the encodings for RCWL[COREPLL]. COREPLL values that are
not listed in Table 61 should be considered as reserved.

NOTE

Core VCO frequency = core frequency × VCO divider
VCO divider must be set properly so that the core VCO frequency is in the

range of 800–1800 MHz.

Low 0110 6 : 1 100 150 200

Low 0111 7 : 1 116 175 233

Low 1000 8 : 1 133 200 266

Low 1001 9 : 1 150 225 300

Low 1010 10 : 1 166 250 333

Low 1011 11 : 1 183 275

Low 1100 12 : 1 200 300

Low 1101 13 : 1 216 325

Low 1110 14 : 1 233

Low 1111 15 : 1 250

Low 0000 16 : 1 266

High 0010 4 : 1 100 133 266

High 0011 6 : 1 100 150 200

High 0100 8 : 1 133 200 266

High 0101 10 : 1 166 250 333

High 0110 12 : 1 200 300

High 0111 14 : 1 233

High 1000 16 : 1 266

1

CFG_CLKIN_DIV doubles csb_clk if set high.

2

CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.

Table 60. CSB Frequency Options for Agent Mode (continued)

CFG_CLKIN_DIV

at Reset

1

SPMF

csb_clk :

Input Clock Ratio

2

Input Clock Frequency (MHz)

2

16.67 25 33.33 66.67

csb_clk Frequency (MHz)

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Clocking

Table 61. e300 Core PLL Configuration

RCWL[COREPLL]

core_clk : csb_clk Ratio VCO Divider

1

1

Core VCO frequency = core frequency × VCO divider. The VCO divider must be set properly so that the core VCO frequency
is in the range of 800–1800 MHz.

0–1 2–5 6

nn 0000 n PLL bypassed

(PLL off, csb_clk clocks core directly)

PLL bypassed

(PLL off, csb_clk clocks core directly)

00 0001 01:1 2

01 0001 01:1 4

10 0001 01:1 8

11 0001 01:1 8

00 0001 1 1.5:1 2

01 0001 1 1.5:1 4

10 0001 1 1.5:1 8

11 0001 1 1.5:1 8

00 0010 02:1 2

01 0010 02:1 4

10 0010 02:1 8

11 0010 02:1 8

00 0010 1 2.5:1 2

01 0010 1 2.5:1 4

10 0010 1 2.5:1 8

11 0010 1 2.5:1 8

00 0011 03:1 2

01 0011 03:1 4

10 0011 03:1 8

11 0011 03:1 8

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Clocking

19.3 Suggested PLL Configurations

Table 62 shows suggested PLL configurations for 33 and 66 MHz input clocks.

Table 62. Suggested PLL Configurations

Ref

No.

1

RCWL 400 MHz Device 533 MHz Device 667 MHz Device

SPMF

CORE

PLL

Input

Clock

Freq

(MHz)

2

CSB
Freq

(MHz)

Core
Freq

(MHz)

Input

Clock

Freq

(MHz)

2

CSB
Freq

(MHz)

Core

Freq

(MHz)

Input

Clock

Freq

(MHz)

2

CSB

Freq

(MHz)

Core

Freq

(MHz)

33 MHz CLKIN/PCI_CLK Options

922 1001 0100010 —————f30033300300

723 0111 0100011 33 233 350 33 233 350 33 233 350

604 0110 0000100 33 200 400 33 200 400 33 200 400

624 0110 0100100 33 200 400 33 200 400 33 200 400

803 1000 0000011 33 266 400 33 266 400 33 266 400

823 1000 0100011 33 266 400 33 266 400 33 266 400

903 1001 0000011 — 3330045033300450

923 1001 0100011 — 3330045033300450

704 0111 0000011 — 3323346633233466

724 0111 0100011 — 3323346633233466

A03 1010 0000011 — 33 333 500 33 333 500

804 1000 0000100 — 3326653333266533

705 0111 0000101 — — 33 233 583

606 0110 0000110 — — 33 200 600

904 1001 0000100 — — 33 300 600

805 1000 0000101 — — 33 266 667

A04 1010 0000100 — — 33 333 667

66 MHz CLKIN/PCI_CLK Options

304 0011 0000100 66 200 400 66 200 400 66 200 400

324 0011 0100100 66 200 400 66 200 400 66 200 400

403 0100 0000011 66 266 400 66 266 400 66 266 400

423 0100 0100011 66 266 400 66 266 400 66 266 400

305 0011 0000101 — 6620050066200500

503 0101 0000011 — 66 333 500 66 333 500

404 0100 0000100 — 6626653366266533

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Thermal

20 Thermal

This section describes the thermal specifications of the MPC8349EA.

20.1 Thermal Characteristics

Table 63 provides the package thermal characteristics for the 672 35 × 35 mm TBGA of the MPC8349EA.

306 0011 0000110 — — 66 200 600

405 0100 0000101 — — 66 266 667

504 0101 0000100 — — 66 333 667

1

The PLL configuration reference number is the hexadecimal representation of RCWL, bits 4–15 associated with the SPMF and
COREPLL settings given in the table.

2

The input clock is CLKIN for PCI host mode or PCI_CLK for PCI agent mode.

Table 63. Package Thermal Characteristics for TBGA

Characteristic Symbol Value Unit Notes

Junction-to-ambient natural convection on single-layer board (1s) R

θJA

14 °C/W 1, 2

Junction-to-ambient natural convection on four-layer board (2s2p) R

θJMA

11 °C/W 1, 3

Junction-to-ambient (at 200 ft/min) on single-layer board (1s) R

θJMA

11 °C/W 1, 3

Junction-to-ambient (at 200 ft/min) on four-layer board (2s2p) R

θJMA

8 °C/W 1, 3

Junction-to-ambient (at 2 m/s) on single-layer board (1s) R

θJMA

9 °C/W 1, 3

Junction-to-ambient (at 2 m/s) on four-layer board (2s2p) R

θJMA

7 °C/W 1, 3

Junction-to-board thermal R

θJB

3.8 °C/W 4

Junction-to-case thermal R

θJC

1.7 °C/W 5

Table 62. Suggested PLL Configurations (continued)

Ref

No.

1

RCWL 400 MHz Device 533 MHz Device 667 MHz Device

SPMF

CORE

PLL

Input

Clock

Freq

(MHz)

2

CSB
Freq

(MHz)

Core
Freq

(MHz)

Input

Clock

Freq

(MHz)

2

CSB
Freq

(MHz)

Core

Freq

(MHz)

Input

Clock

Freq

(MHz)

2

CSB

Freq

(MHz)

Core

Freq

(MHz)

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Thermal

20.2 Thermal Management Information

For the following sections, PD = (VDD× IDD) + P

I/O

where P

I/O

is the power dissipation of the I/O drivers.

See Table 5 for I/O power dissipation values.

20.2.1 Estimation of Junction Temperature with Junction-to-Ambient

Thermal Resistance

An estimation of the chip junction temperature, TJ, can be obtained from the equation:

TJ = TA + (R

θ

JA

× PD)

where:

TJ = junction temperature (°C)

TA = ambient temperature for the package (°C)

R

θ

JA

= junction-to-ambient thermal resistance (°C/W)

P

D

= power dissipation in the package (W)

The junction-to-ambient thermal resistance is an industry-standard value that provides a quick and easy
estimation of thermal performance. Generally , the value obtained on a single-layer board is appropriate for
a tightly packed printed-circuit board. The value obtained on the board with the internal planes is usually
appropriate if the board has low power dissipation and the components are well separated. T est cases have
demonstrated that errors of a factor of two (in the quantity TJ–TA) are possible.

20.2.2 Estimation of Junction Temperature with Junction-to-Board

Thermal Resistance

The thermal performance of a device cannot be adequately predicted from the junction-to-ambient thermal
resistance. The thermal performance of any component is strongly dependent on the power dissipation of
surrounding components. In addition, the ambient temperature varies widely within the application. For
many natural convection and especially closed box applications, the board temperature at the perimeter

Junction-to-package natural convection on top ψ

JT

1 °C/W 6

Notes:

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.

2. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.

3. Per JEDEC JESD51-6 with the board horizontal, 1 m/s is approximately equal to 200 linear feet per minute (LFM).

4. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.

5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method

1012.1).

6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature
per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.

Table 63. Package Thermal Characteristics for TBGA (continued)

Characteristic Symbol Value Unit Notes

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Thermal

(edge) of the package is approximately the same as the local air temperature near the device. Specifying
the local ambient conditions explicitly as the board temperature provides a more precise description of the
local ambient conditions that determine the temperature of the device.

At a known board temperature, the junction temperature is estimated using the following equation:

TJ = TA + (R

θ

JA

× PD)

where:

TJ = junction temperature (°C)
TA = ambient temperature for the package (°C)
R

θ

JA

= junction-to-ambient thermal resistance (°C/W)

PD = power dissipation in the package (W)

When the heat loss from the package case to the air can be ignored, acceptable predictions of junction
temperature can be made. The application board should be similar to the thermal test condition: the
component is soldered to a board with internal planes.

20.2.3 Experimental Determination of Junction Temperature

To determine the junction temperature of the device in the application after prototypes are available, use
the thermal characterization parameter (

Ψ

JT

) to determine the junction temperature and a measure of the

temperature at the top center of the package case using the following equation:

TJ = TT + (

Ψ

JT

× PD)

where:

TJ = junction temperature (°C)
TT = thermocouple temperature on top of package (°C)

Ψ

JT

= junction-to-ambient thermal resistance (°C/W)

PD = power dissipation in the package (W)

The thermal characterization parameter is measured per the JESD51-2 specification using a 40 gauge type
T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so
that the thermocouple junction rests on the package. A small amount of epoxy is placed over the
thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire
is placed flat against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.

20.2.4 Heat Sinks and Junction-to-Case Thermal Resistance

Some application environments require a heat sink to provide the necessary thermal management of the
device. When a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case
thermal resistance and a case-to-ambient thermal resistance:

R

θ

JA

= R

θ

JC

+ R

θ

CA

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Thermal

where:

R

θ

JA

= junction-to-ambient thermal resistance (°C/W)

R

θ

JC

= junction-to-case thermal resistance (°C/W)

R

θ

CA

= case-to-ambient thermal resistance (°C/W)

R

θ

JC

is device-related and cannot be influenced by the user . The user controls the thermal environment to

change the case-to-ambient thermal resistance, R

θ

CA

. For instance, the user can change the size of the heat
sink, the air flow around the device, the interface material, the mounting arrangement on printed-circuit
board, or change the thermal dissipation on the printed-circuit board surrounding the device.

The thermal performance of devices with heat sinks has been simulated with a few commercially available
heat sinks. The heat sink choice is determined by the application environment (temperature, air flow,
adjacent component power dissipation) and the physical space available. Because there is not a standard
application environment, a standard heat sink is not required.

Table 64 shows heat sink thermal resistance for TBGA of the MPC8349EA.

Accurate thermal design requires thermal modeling of the application environment using computational
fluid dynamics software which can model both the conduction cooling and the convection cooling of the
air moving through the application. Simplified thermal models of the packages can be assembled using the
junction-to-case and junction-to-board thermal resistances listed in the thermal resistance table. More
detailed thermal models can be made available on request.

Table 64. Heat Sink and Thermal Resistance of MPC8349EA (TBGA)

Heat Sink Assuming Thermal Grease Air Flow

35 × 35 mm TBGA

Thermal Resistance

AAVID 30 × 30 × 9.4 mm pin fin Natural convection 10

AAVID 30 × 30 × 9.4 mm pin fin 1 m/s 6.5

AAVID 30 × 30 × 9.4 mm pin fin 2 m/s 5.6

AAVID 31 × 35 × 23 mm pin fin Natural convection 8.4

AAVID 31 × 35 × 23 mm pin fin 1 m/s 4.7

AAVID 31 × 35 × 23 mm pin fin 2 m/s 4

Wakefield, 53 × 53 × 25 mm pin fin Natural convection 5.7

Wakefield, 53 × 53 × 25 mm pin fin 1 m/s 3.5

Wakefield, 53 × 53 × 25 mm pin fin 2 m/s 2.7

MEI, 75 × 85 × 12 no adjacent board, extrusion Natural convection 6.7

MEI, 75 × 85 × 12 no adjacent board, extrusion 1 m/s 4.1

MEI, 75 × 85 × 12 no adjacent board, extrusion 2 m/s 2.8

MEI, 75 × 85 × 12 mm, adjacent board, 40 mm side bypass 1 m/s 3.1

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Thermal

Heat sink vendors include the following list:

Aavid Thermalloy 603-224-9988
80 Commercial St.
Concord, NH 03301
Internet: www.aavidthermalloy.com

Alpha Novatech 408-567-8082
473 Sapena Ct. #12
Santa Clara, CA 95054
Internet: www.alphanovatech.com

International Electronic Research Corporation (IERC) 818-842-7277
413 North Moss St.
Burbank, CA 91502
Internet: www.ctscorp.com

Millennium Electronics (MEI) 408-436-8770
Loroco Sites
671 East Brokaw Road
San Jose, CA 95112
Internet: www.mei-thermal.com

Tyco Electronics 800-522-2800
Chip Coolers™
P.O. Box 3668
Harrisburg, PA 17105-3668
Internet: www.chipcoolers.com

Wakefield Engineering 603-635-5102
33 Bridge St.
Pelham, NH 03076
Internet: www.wakefield.com

Interface material vendors include the following:

Chomerics, Inc. 781-935-4850
77 Dragon Ct.
Woburn, MA 01801
Internet: www.chomerics.com

Dow-Corning Corporation 800-248-2481
Dow-Corning Electronic Materials
P.O. Box 994
Midland, MI 48686-0997
Internet: www.dowcorning.com

Shin-Etsu MicroSi, Inc. 888-642-7674
10028 S. 51st St.
Phoenix, AZ 85044
Internet: www.microsi.com

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System Design Information

The Bergquist Company 800-347-4572
18930 West 78th St.
Chanhassen, MN 55317
Internet: www.bergquistcompany.com

20.3 Heat Sink Attachment

When heat sinks are attached, an interface material is required, preferably thermal grease and a spring clip.
The spring clip should connect to the printed-circuit board, either to the board itself, to hooks soldered to
the board, or to a plastic stiffener . Avoid attachment forces that can lift the edge of the package or peel the
package from the board. Such peeling forces reduce the solder joint lifetime of the package. The
recommended maximum force on the top of the package is 10 lb force (4.5 kg force). Any adhesive
attachment should attach to painted or plastic surfaces, and its performance should be verified under the
application requirements.

20.3.1 Experimental Determination of the Junction Temperature with a

Heat Sink

When a heat sink is used, the junction temperature is determined from a thermocouple inserted at the
interface between the case of the package and the interface material. A clearance slot or hole is normally
required in the heat sink. Minimize the size of the clearance to minimize the change in thermal
performance caused by removing part of the thermal interface to the heat sink. Because of the experimental
difficulties with this technique, many engineers measure the heat sink temperature and then back calculate
the case temperature using a separate measurement of the thermal resistance of the interface. From this
case temperature, the junction temperature is determined from the junction-to-case thermal resistance.

TJ = TC + (R

θ

JC

× PD)

where:

TJ = junction temperature (°C)
TC = case temperature of the package (°C)
R

θ

JC

= junction-to-case thermal resistance (°C/W)

PD = power dissipation (W)

21 System Design Information

This section provides electrical and thermal design recommendations for successful application of the
MPC8349EA.

21.1 System Clocking

The MPC8349EA includes two PLLs:

1. The platform PLL generates the platform clock from the externally supplied CLKIN input. The
frequency ratio between the platform and CLKIN is selected using the platform PLL ratio
configuration bits as described in Section 19.1, “System PLL Configuration.”

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System Design Information

2. The e300 core PLL generates the core clock as a slave to the platform clock. The frequency ratio
between the e300 core clock and the platform clock is selected using the e300 PLL ratio
configuration bits as described in Section 19.2, “Core PLL Configuration.”

21.2 PLL Power Supply Filtering

Each PLL gets power through independent power supply pins (AVDD1, AVDD2, respectively). The AVDD
level should always equal to VDD, and preferably these voltages are derived directly from VDD through a
low frequency filter scheme.

There are a number of ways to provide power reliably to the PLLs, but the recommended solution is to
provide four independent filter circuits as illustrated in Figure 42, one to each of the four AVDD pins.
Independent filters to each PLL reduce the opportunity to cause noise injection from one PLL to the other.

The circuit filters noise in the PLL resonant frequency range from 500 kHz to 10 MHz. It should be built
with surface mount capacitors with minimum effective series inductance (ESL). Consistent with the
recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic
(Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a single large value
capacitor.

T o minimize noise coupled from nearby circuits, each circuit should be placed as closely as possible to the
specific AVDD pin being supplied. It should be possible to route directly from the capacitors to the AV

DD

pin, which is on the periphery of package, without the inductance of vias.

Figure 42 shows the PLL power supply filter circuit.

Figure 42. PLL Power Supply Filter Circuit

21.3 Decoupling Recommendations

Due to large address and data buses and high operating frequencies, the MPC8349EA can generate
transient power surges and high frequency noise in its power supply, especially while driving large
capacitive loads. This noise must be prevented from reaching other components in the MPC8349EA
system, and the device itself requires a clean, tightly regulated source of power. Therefore, the system
designer should place at least one decoupling capacitor at each VDD, OVDD, GVDD, and LVDD pin of the
device. These capacitors should receive their power from separate V

DD

, OVDD, GVDD, LVDD, and GND
power planes in the PCB, with short traces to minimize inductance. Capacitors can be placed directly under
the device using a standard escape pattern. Others can surround the part.

These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.

In addition, distribute several bulk storage capacitors around the PCB, feeding the V

DD

, OVDD, GVDD,

and LV

DD

planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should

V

DD

AVDD (or L2AVDD)

2.2 µF 2.2 µF

GND

Low ESL Surface Mount Capacitors

10 Ω

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Freescale Semiconductor 81

System Design Information

have a low ESR (equivalent series resistance) rating to ensure the quick response time. They should also
be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk
capacitors are 100–330 µF (AVX TPS tantalum or Sanyo OSCON).

21.4 Connection Recommendations

To ensure reliable operation, connect unused inputs to an appropriate signal level. Unused active low
inputs should be tied to OVDD, GVDD, or LVDD as required. Unused active high inputs should be
connected to GND. All NC (no-connect) signals must remain unconnected.

Power and ground connections must be made to all external VDD, GVDD, L VDD, OVDD, and GND pins of
the MPC8349EA.

21.5 Output Buffer DC Impedance

The MPC8349EA drivers are characterized over process, voltage, and temperature. For all buses, the
driver is a push-pull single-ended driver type (open drain for I2C).

To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to OVDD
or GND. Then the value of each resistor is varied until the pad voltage is OVDD/2 (see Figure 43). The
output impedance is the average of two components, the resistances of the pull-up and pull-down devices.
When data is held high, SW1 is closed (SW2 is open) and RP is trimmed until the voltage at the pad equals
OVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN are designed to be close to each
other in value. Then, Z0 = (RP + RN) ÷ 2.

Figure 43. Driver Impedance Measurement

T wo measurements give the value of this resistance and the strength of the driver current source. First, the
output voltage is measured while driving logic 1 without an external differential termination resistor. The
measured voltage is V

1

= R

source

× I

source

. Second, the output voltage is measured while driving logic 1

with an external precision differential termination resistor of value R

term

. The measured voltage is

OV

DD

OGND

R

P

R

N

Pad

Data

SW1

SW2

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82 Freescale Semiconductor

Ordering Information

V2=(1÷ (1/R1+1/R2)) × I

source

. Solving for the output impedance gives R

source

= R

term

× (V1÷ V2–1).

The drive current is then I

source=V1

÷ R

source

.

Table 65 summarizes the signal impedance targets. The driver impedance are targeted at minimum VDD,

nominal OVDD, 105°C.

21.6 Configuration Pin Multiplexing

The MPC8349EA power-on configuration options can be set through external pull-up or pull-down
resistors of 4.7 kΩ on certain output pins (see the customer-visible configuration pins). These pins are used
as output only pins in normal operation.

However, while HRESET is asserted, these pins are treated as inputs, and the value on these pins is latched
when PORESET deasserts. Then the input receiver is disabled and the I/O circuit takes on its normal
function. Careful board layout with stubless connections to these pull-up/pull-down resistors coupled with
the large value of the pull-up/pull-down resistor should minimize the disruption of signal quality or speed
for the output pins.

21.7 Pull-Up Resistor Requirements

The MPC8349EA requires high resistance pull-up resistors (10 kΩ is recommended) on open-drain pins,
including I

2

C pins, and IPIC interrupt pins.

For more information on required pull-up resistors and the connections required for the JTAG interface,
refer to application note AN2931, “PowerQUICC Design Checklist.”

22 Ordering Information

This section presents ordering information for the device discussed in this document, and it shows an
example of how the parts are marked.

NOTE

The information in this document is accurate for revision 3.x silicon and
later (in other words, for orderable part numbers ending in A or B). For
information on revision 1.1 silicon and earlier versions, see the MPC8349E

PowerQUICC II Pro Integrated Host Processor Hardware Specifications

(Document Order No. MPC8349EEC).

Table 65. Impedance Characteristics

Impedance

Local Bus, Ethernet,

DUART, Control,

Configuration, Power

Management

PCI Signals

(Not Including PCI

Output Clocks)

PCI Output Clocks

(Including

PCI_SYNC_OUT)

DDR DRAM Symbol Unit

R

N

42 Target 25 Target 42 Target 20 Target Z

0

W

R

P

42 Target 25 Target 42 Target 20 Target Z

0

W

Differential NA NA NA NA Z

DIFF

W

Note: Nominal supply voltages. See Ta bl e 1 , Tj = 105°C.

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Freescale Semiconductor 83

Ordering Information

22.1 Part Numbers Fully Addressed by This Document

Table 66 shows an analysis of the Freescale part numbering nomenclature for the MPC8349EA. The

individual part numbers correspond to a maximum processor core frequency. Each part number also
contains a revision code that refers to the die mask revision number. For available freq uency configuration
parts including extended temperatures, refer to the device product summary page on our website listed on
the back cover of this document or, contact your local Freescale sales office.

Table 67 shows the SVR settings by device and package type.

Table 66. Part Numbering Nomenclature

MPC nnnn e t pp aa a r

Product

Code

Part

Identifier

Encryption

Acceleration

Tem pera ture

1

Range

Package

2

Processor

Frequency

3

Platform

Frequency

Revision

Level

MPC 8349 Blank = Not

included

E = included

Blank = 0 to 105°C
C = –40 to 105°C

ZU =TBGA
VV = PB free TBGA

e300 core

speed

AG = 400

AJ = 533

AL = 667

D = 266

F = 333

4

B = 3.1

Notes:

1. For temperature range = C, processor frequency is limited to with a platform frequency of 266 and up to 533 with a platform
frequency of 333

2. See Section 18, “Package and Pin Listings,” for more information on available package types.

3. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this
specification support all core frequencies. Additionally, parts addressed by Part Number Specifications may support other
maximum core frequencies.

4. ALF marked parts support DDR1 data rate up to 333 MHz (at 333 MHz CSB as the 'F' marking implies) and DDR2 data rate
up to 400 MHz (at 200 MHz CSB). AJF marked parts support DDR1 and DDR2 data rate up to 333 MHz (at a CSB of 333
MHz).

Table 67. SVR Settings

Device Package SVR (Rev. 3.0)

MPC8349EA TBGA 8050_0030

MPC8349A TBGA 8051_0030

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84 Freescale Semiconductor

Document Revision History

22.2 Part Marking

Parts are marked as in the example shown in Figure 44.

Figure 44. Freescale Part Marking for TBGA Devices

23 Document Revision History

This table provides a revision history of this document.

Table 68. Document Revision History

Rev.

Number

Date Substantive Change(s)

13 09/2011 • In Section 2.2, “Power Sequencing,” added Section 2.2.1, “Power-Up Sequencing” and Figure 4.

•In Tab l e 2 5, Ta b l e 2 9 and Ta bl e 3 1, removed the GTX_CLK125.

•In Tab l e 3 4, updated t

MDKHDX

Max value from 170ns to 70ns.

12 11/2010 • In Ta bl e 5 5 added note for pin LGPL4.

•In Section 21.7, “Pull-Up Resistor Requirements, updated the list of open drain type pins.

11 05/2010 • In Ta bl e 2 5 through Ta bl e 3 0 , changed V

IL

(min) to VIH(max) to (20%–80%).

• Added Ta b le 8 , “EC_GTX_CLK125 AC Timing Specifications.”

10 5/2009 • In Ta bl e 5 7 , updated frequency for max csb_clk to 333 MHz and DDR2, from 100-200 to 100-133

at core frequency = 533MHz.

•In Section 18.1, “Package Parameters for the MPC8349EA TBGA, changed solder ball for TBGA
and PBGA from 95.5 Sn/0.5 Cu/4 Ag to 96.5 Sn/3.5 Ag.

•In Tab l e 6 6 , footnote 1, changed 667(TBGA) to 533(TBGA). footnote 4, added data rate for DDR1
and DDR2.

MPCnnnnetppaaar

core/platform MHZ

AT W LY YW W

CCCCC

TBGA

*MMMMM YWWLAZ

Notes

:

ATWLYYWW is the traceability code.
CCCCC is the country code.
MMMMM is the mask number.
YWWLAZ is the assembly traceability code.

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Freescale Semiconductor 85

Document Revision History

9 2/2009 • Added footnote 6 to Ta b le 7 .

•In Section 9.2, “USB AC Electrical Specifications,” clarified that AC table is for ULPI only.

•In Tab l e 3 9 , corrected t

LBKHOV

parameter to t

LBKLOV

(output data is driven on falling edge of clock
in DLL bypass mode). Similarly, made the same correction to Figure 22, Figure 24, and Figure 25
for output signals.

• Added footnote 11 to Ta bl e 5 5.

• Added footnote 4 to Ta bl e 6 6.

•In Section 21.1, “System Clocking,” removed “(AVDD1)” and “(AVDD2”) from bulleted list.

•In Section 21.2, “PLL Power Supply Filtering,” in the second paragraph, changed “provide five
independent filter circuits,” and “the five AVDD pins” to provide four independent filter circuits,” and
“the four AVDD pins.”

•In Tab l e 5 7, corrected the max csb_clk to 266 MHz.

•In Tab l e 6 2, added PLL configurations 903, 923, A03, A23, and 503 for 533 MHz

•In Tab l e 6 6 , updated note 1 to say the following: “For temperature range = C, processor frequency
is limited to 533 with a platform frequency of 266.”

8 4/2007 • In Ta bl e 3, “Output Drive Capability,” changed the values in the Output Impedance column and

added USB to the seventh row.

•In Section 21.7, “Pull-Up Resistor Requirements,“deleted last two paragraphs and after first
paragraph, added a new paragraph.

• Deleted Section 21.8, “JTAG Configuration Signals,” and Figure 43, “JTAG Interface Connection.”

7 3/2007 • In Table 57, “Operating Frequencies for TBGA,” in the ‘Coherent system bus frequency (csb_clk)’

row, changed the value in the 533 MHz column to 100-333.

• In Table 63, “Suggested PLL Configurations,” under the subhead, ‘33 MHz CLKIN/PCI_CLK
Options,’ added row A03 between Ref. No. 724 and 804. Under the subhead ‘66 MHz
CLKIN/PCI_CLK Options,’ added row 503 between Ref. No. 305 and 404. For Ref. No. 306,
changed the CORE PLL value to 0000110.

• In Section 23, “Ordering Information,” replaced first paragraph and added a note.

• In Section 23.1, “Part Numbers Fully Addressed by this Document,” replaced first paragraph.

6 2/2007 • Page 1, updated first paragraph to reflect PowerQUICC II Pro information.

• In Table 18, “DDR and DDR2 SDRAM Input AC Timing Specifications,” added note 2 to t

CISKEW

and deleted original note 3; renumbered the remaining notes.

• In Figure 41, “JTAG Interface Connection,” updated with new figure.

• In Section 23.1, “Part Numbers Fully Addressed by This Document,” replaced third sentence of
first paragraph directing customer to product summary page for available frequency configuration
parts.

5 1/2007 • In Table 1, “Absolute Maximum Ratings,” added (1.36 max for 667-MHz core frequency) to max

V

DD

and AvDD values.

• In Table 2, “Recommended Operating Conditions,” added a row showing nominal core supply
voltage and PLL supply voltage of 1.3 V for 667-MHz parts.

• In Table 4, “MPC8349EA Power Dissipation,” added two footnotes to 667-MHz row showing
nominal core supply voltage and PLL supply voltage of 1.3 V for 667-MHz parts.

• In Table 54, “MPC83479EA (TBGA) Pinout Listing,” updated V

DD

nd AV

DD

rows to show nominal

core supply voltage and PLL supply voltage of 1.3 V for 667-MHz parts.

4 12/2006 Table 19, “DDR and DDR2 SDRAM Output AC Timing Specifications,” modified T

ddkhds

for 333 MHz

from 900 ps to 775 ps.

Table 68. Document Revision History (continued)

Rev.

Number

Date Substantive Change(s)

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Document Revision History

3 11/2006 • Updated note in introduction.

• In the features list in Section 1, “Overview,” updated DDR data rate to show 400 MHz for DDR2
for TBGA parts for silicon 3.x and 400 MHz for DDR2 for TBGA parts for silicon 3.x.

• In Section 23, “Ordering Information,” replicated note from document introduction.

2 8/2006 • Changed all references to revision 2.0 silicon to revision 3.0 silicon.

• Changed VIH minimum value in Table 40, “JTAG Interface DC Electrical Characteristics,” to
OV

DD

–0.3.

• In Table 44, “PCI DC Electrical Characteristics,” changed high-level input voltage values to min
= 2 and max = OVDD + 0.3; changed low-level input voltage values to min = (–0.3) and max = 0.8.

• Updated DDR2 I/O power values in Table 5, “MPC8347EA Typical I/O Power Dissipation.”

• In Table 66, “Suggested PLL Configurations,” deleted reference-number rows 902 and 703.

1 4/2006 • Removed Table 20, “Timing Parameters for DDR2-400.”

• Changed ADDR/CMD to ADDR/CMD/MODT in Table 9, “DDR and DDR2 SDRAM Output AC
Timing Specifications,” rows 2 and 3, and in Figure 2, “DDR SDRAM Output Timing Diagram.

• Changed Min and Max values for V

IH

and VIL in Table 40Table 44,“PCI DC Electrical

Characteristics.”

• In Table 55, “MPC8349EA (TBGA) Pinout Listing,” and Table 52, “MPC8347EA (PBGA) Pinout
Listing,” modified rows for MDICO and MDIC1 signals and added note ‘It is recommended that
MDICO be tied to GRD using an 18 Ω resistor and MCIC1 be tied to DDR power using an 18 Ω
resistor.’

• Table 55, “MPC8349EA (TBGA) Pinout Listing,” in row AVDD3 changed power supply from
“AVDD3” to ‘—.’

0 3/2006 Initial public release

Table 68. Document Revision History (continued)

Rev.

Number

Date Substantive Change(s)

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Document Number: MPC8349EAEC
Rev. 13
09/2011

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