HON HAI PRECISION IND 951993A Users Manual
COMPANY CONFIDENTIAL REV 0.7
LTE PCI Express M.2 Module
95.1993T01
User Manual
version 0.7
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COMPANY CONFIDENTIAL REV 0.7
Table of Contents
1. INTRODUCTION ................................................................................................................................................... - 3 -
1.1 S
COPE
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1.2 F
UNCTION
2. SPECIFICATION ................................................................................................................................................... - 4 -
2.1 P
HYSICAL INTERFACE
2.2 P
IN ARRANGEMENT
3. PRODUCT REQUIREMENTS ............................................................................................................................ - 6 -
3.1 H
ARDWARE FEATURE
3.2 M
ECHANICAL SPECIFICATIONS
3.3 E
LECTRICAL SPECIFICATIONS
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COMPANY CONFIDENTIAL REV 0.7
B41 (20+20) contiguous
B41 (20+20+20) contiguous
B
25 (5+5) non
-
contiguous
B25 (5+10) non
-
contiguous
1. Introduction
Project Name: LTE PCI Express M.2 Module
Foxconn Project Code: 95.1993T01
This documentation describes the hardware, and mechanical requirements specification of
LTE PCI Express M.2 Module. It is a confidential document of Foxconn.
1.1 Scope
The function of this module provides a LTE wireless WAN interface to access the internet,
and it is fully compliant with LTE specification (3GPP Release 12).
1.2 Function
LTE Standards 3GPP standard
Operating Frequency Band 25: 1930 to 1995 MHz (DL),
1850 to 1915 MHz (UL)
Band 41: (L) 2500 to 2570 MHz (DL/UL)
(H) 2620 to 2690MHz (DL/UL)
Number of T/Rx interface: Band 25: 2Tx /8Rx
Band 41L/H: 4Tx /8Rx
Channel Bandwidth: 5, 10, 15, 20 MHz for Band 41
5, 10, 15, 20 MHz for Band 25
Carrier Aggregation
DL carrier aggregation UL carrier aggregation
B41 (20+20) contiguous and non-contiguous
B41 (20+15) contiguous and non-contiguous
B41 (15+20) contiguous and non-contiguous
B41 (20+10) contiguous and non-contiguous
B41 (10+20) contiguous and non-contiguous
B41 (20+5) contiguous and non-contiguous
B41 (5+20) contiguous and non-contiguous
B41 (15+15) contiguous and non-contiguous
(hardware design can support above CA combination, but the final CA combinations plan
depends on carrier engagement and software design.)
B41 (10+15) contiguous and non-contiguous
B41 (15+10) contiguous and non-contiguous
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COMPANY CONFIDENTIAL REV 0.7
2. Specification
2.1 Physical Interface
RGMII, PCI express M.2 module,
PCB size: 64.4 mm x 65 mm
Antenna connector: UFL connector *8
Dual SIM interface (one for testing)
2.2 Pin Arrangement
Figure 2.1 the sequence of pins on the 75-pin signal interface of M.2 Key.B.
(Input: Carrier board to Module)
(Output: Module to Carrier board)
(Bi-direction: both direction among module and carrier board)
Pin number pin name description direction Voltage Domain
Select SIM0 or SIM1
1 SIM_SEL
2 3.6V_AUX power input VCC = 3.6V
3 GND ground NA NA
4 3.6V_AUX power input VCC = 3.6V
5 GND ground NA NA
6 PWR_EN enable/disable PMIC Input PU(VCC=3.6V)
7 USB2.0_DP USB2.0 D+ signal Bi-Direction
8 DCDC_1.8V power Output 1.8V
9 USB2.0_DM USB2.0 D- signal Bi-Direction
10 VBUS USB VBUS NA floating
· SIM_SEL Open or HIGH = SIM0 is active
· SIM_SEL LOW = SIM1 is active
Input OD, PU(1.8V)
11 GND ground NA NA
12 NA NA NA NA
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13 NA NA NA NA
14 NA NA NA NA
15 NA NA NA NA
16 NA NA NA NA
17 NA NA NA NA
18 NA NA NA NA
19 NA NA NA NA
20 SIM1_RST_O Test SIM reset Output SIM1 VCC
21 GND ground NA NA
22 SIM1_CLK_O Test SIM clock Output SIM1 VCC
23 UART0_RXD UART0 serial receive data Input 1.8V
24 SIM1_DAT_O Test SIM data Bi-Direction SIM1 VCC
25 UART0_TXD UART0 serial transmit data Output 1.8V
26 SIM_VCC1 Test SIM power output SIM1 VCC
27 GND ground NA
28 GPD2_21 GPIO for future use NA 1.8V
29 3.6V_AUX power input VCC = 3.6V
30 SIM0_RST LTE SIM reset Output SIM0 VCC
31 3.6V_AUX power input VCC = 3.6V
32 SIM0_CLK LTE SIM clock Output SIM0 VCC
33 GND ground NA NA
34 SIM0_DAT LTE SIM data Bi-Direction SIM0 VCC
35 3.6V_AUX power input VCC = 3.6V
36 SIM_VCC0 SIM power output SIM0 VCC
37 3.6V_AUX power input VCC = 3.6V
38 10MS_PULSE GPIO(1PPS PULSE) Output 1.8V
39 GND ground NA NA
40 RGMII_RCTL RGMII Interface Input 1.8V
41 3.6V_AUX power input VCC = 3.6V
42 RGMII_RCLK RGMII Interface Input 1.8V
43 3.6V_AUX power input VCC = 3.6V
NA
44 RGMII_MDIO RGMII Interface Input 1.8V
45 GND ground NA
46 RGMII_MDC RGMII Interface Output 1.8V
47 Default_Fact factory default Input 1.8V
48 RGMII_TCLK RGMII Interface Output 1.8V
49 GPD2_0 GPIO for future use NA 1.8V
50 RGMII_TCTL RGMII Interface Output 1.8V
NA
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