Holtek Semiconductor Inc HTG2150 Datasheet

HTG2150

Preliminary

8-Bit 320 Pixel LCD Microcontroller

Features

Operating voltage: 2.2V~3.6V

16K ´ 16 bits program ROM

192 ´ 8 bits data RAM

8~12 bidirectional I/O lines

8 common ´ 33~40 segment LCD driver

One 16-bit programmable timer

with overflow interrupts One 8-bit programmable timer with 8 stage

prescaler for PFD One 8-bit programmable timer with 8 stage

prescaler for Time base One 8-bit PWM audio output to directly

drive speaker and buzzer

General Description

The HTG2150 is an 8-bit high performance RISC-like microcontroller. The single cycle in struction and two-stage pipeline architecture make it suitable for high speed application. The device is ideally suited for multiple LCD low

Watchdog Timer

On-chip RC oscillator for system clock and

32768Hz crystal oscillator for timebase and LCD driver HALT function and wake-up feature reduce

power consumption 8-level subroutine nesting

Bit manipulation instructions

63 powerful instructions

One interrupt input

power application among which are calcula tors, clock timer, game, scales, toys and hand

held LCD products, as well as for battery sys tems.

1 July 24, 2000

Block Diagram

Preliminary

SYS CLK/4

HTG2150

Program

ROM

Instruction

R egister

Instruction

D ecoder

Tim ing

G enerator

OSCI RES

VDD VSS

Program

C ounter

Memory

MP0 MP1

Shifter

ACC

LC D

ALU

STACK0

STACK1

STACK2

STACK3

STACK4

STACK5

STACK6

STACK7

MUX

M U X

IN T /S E G 3 7

In te rru p t

DATA

Memory

STATUS

Circuit

IN T C

TM R0

TM R0C

16 bit

TM R2

TM R2C

WDTS

W D T P rescaler

PAC

PORT A

PBC

PORT B

SYS C LK

32768H z Crystal

8-stage

P resca ler

PW M D AC1

PFD

PW M D AC2

256

PA0~PA7

PB4~PB7/SEG 33~SEG36

8-stage

P resca ler

M U X

WDT RC

OSC

SYS C LK

PW M 1

PW M 2

LCD Driver

COM 0~CO M 7

SEG0~SEG 32 PB4~PB7/SEG 33~SEG36 IN T /S E G 3 7 XOUT/SEG 38 XIN/SEG 39

TM R3

TM R3C

PW M

D/A

8-stage

P resca ler

SYS CLK

PW M D AC1

PW M D AC2

M U X

2 July 24, 2000

Pad Assignment

Preliminary

SEG 10

SEG 11

SEG 12

SEG 13

SEG 14

SEG 15

SEG 16

SEG 17

SEG 18

SEG 19

SEG 20

SEG 21

SEG 22

SEG 23

SEG 24

HTG2150

SEG 9

SEG 25

SEG 26

SEG 27

SEG 28

SEG 29

SEG 30

SEG 31

SEG 32

PB4/SEG 33

PB5/SEG 34

PB6/SEG 35

PB7/SEG 36

IN T /S E G 3 7

XOUT/SEG 38

XIN/SEG 39

(0 ,0 )

SEG 8

SEG 7

SEG 6

SEG 5

SEG 4

SEG 3

SEG 2

SEG 1

SEG 0

COM 7

COM 6

COM 5

COM 4

COM 3

COM 2

COM 1

COM 0

RES

PW M 1

PW M 2

OSCI

VDD

22532354245525562657275828

PA0

PA1

PA2

VSS

PA3

PA4

PA5

PA6

PA7

* The IC substrate should be connected to VSS in the PCB layout artwork.

3 July 24, 2000

Preliminary

HTG2150

Pad Coordinates

Pad No. X Y Pad No. X Y

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 58.61 23 175.41 24 289.41 25 406.21 26 520.21 27 637.01 28 751.01 29 867.81 30 882.36 31 882.36

-880.45

-887.11

-822.70

-822.70 -13.52

-822.70 -127.52

-822.70 -244.52

-824.04 -354.49

-824.04 -462.62

-823.97 -580.52

-871.13 -1052.80

-720.90 -1052.80

-539.25 -1052.80

-404.50 -1051.65

-273.79 -1032.67

-99.06 -1097.34

1114.46 32 882.36

872.13 33 882.36

765.63 34 882.36

659.03 35 882.36

552.53 36 882.36

445.93 37 882.36

339.43 38 882.36

232.83 39 882.36 106.43

103.48 40 882.36 212.93

-1057.70

-852.57

-745.97

41 882.36 319.53 42 882.36 426.03 43 882.36 532.63 44 882.36 639.13 45 882.36 745.73 46 882.36 852.23 47 824.35 1114.46 48 717.85 1114.46 49 611.25 1114.46 50 504.75 1114.46 51 398.15 1114.46 52 291.65 1114.46 53 185.05 1114.46 54 78.55 1114.46 55 56 57 58 59 60 61 62

-28.05

-134.55

-241.15

-347.65

-454.25

-560.75

-667.35

-773.85

Unit: mm

-639.47

-532.87

-426.37

-319.77

-213.27

-106.67

-0.17

1114.46

Pad Description

Pad No. Pad Name I/O

38~62 1~8

9~12

SEG0~SEG24 SEG25~SEG32

PB4~PB7/ SEG33~SEG36

I/O

or O

Mask

Option

Input/Output

or Segment

Output

Description

LCD segment signal output.

Selectable as bidirectional input/output or LCD segment signal output by mask option. On bidirectional input/output port. Software instruc tions determine the CMOS output or schmitt trig ger input with pull-high resistor. PB4~PB7 share pad with SEG33~SEG36.

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Preliminary

HTG2150

Pad No. Pad Name I/O

13 INT

15 14

16 RES

17 PWM1 O CMOS Positive PWM CMOS output

18 PWM2 O CMOS Negative PWM CMOS output

19 VDD

20 OSCI I

21 VSS

22~29 PA0~PA7 I/O

37~31 COM7~COM0 O

/SEG37

XIN/SEG39 XOUT/SEG38

or O

IorO

¾¾

Mask

Option

Interrupt

input or

Segment 37

output

Crystal or

Segment

Output

Wake-up

or None

Wake-up

Description

Selectable as external interrupt schmitt trigger input or LCD segment 37 signal output by mask option. External interrupt schmitt trigger input with pull-high resistor. Edge triggered activated on a high to low transition. INT SEG37.

Selectable as 32768Hz crystal oscillator or LCD segment signal output by mask option. Crystal oscillator (32.768kHz) for Timer 3 and LCD clock. XIN shares pad with SEG39; XOUT shares pad with SEG38.

Schmitt trigger reset input. Active low without pull-high resistor.

Positive power supply

OSCI is connected to the RC network of the in ternal system clock.

Negative power supply, ground

Bidirectional 8-bit input/output port. Each bit can be configured as a wake-up input by mask option. Software instructions determine the CMOS output or schmitt trigger input with pull-high resistor.

LCD common signal output

shares pad with

Absolute Maximum Ratings

Supply Voltage ..............................-0.3V to 3.6V

Input Voltage .................V

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maxi

mum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged expo sure to extreme conditions may affect device reliability.

-0.3V to VDD+0.3V

Storage Temperature.................-50°Cto125°C

Operating Temperature ..................0°Cto70°C

5 July 24, 2000

Preliminary

HTG2150

D.C. Characteristics

Symbol Parameter

STB1

STB2

OH1

OH2

OH3

OL1

OL2

OL3

IL1

IH1

IL2

IH2

IL3

IH3

Operating Voltage

Operating Current (RC OSC) 3V

Standby Current With 7mA LCD Bias Option (RTC ON, LCD ON)

Standby Current LCD Bias Off Option (RTC ON, LCD OFF)

Input Low Voltage for PA/PB 3V

Input High Voltage for PA/PB 3V

Input Low Voltage (INT)3V¾0

Input High Voltage (INT)3V¾2.3

Input Low Voltage (RES)3V

Input High Voltage (RES)3V

Port A, Port B Source Current 3V

Segment, Common Output Source Current

PWM1/PWM2 Source Current 3V

Port A, Port B Sink Current 3V

Segment, Common Output Sink Current

PWM1/PWM2 Sink Current 3V

Pull-high Resistance of PA/PB and INT 3V

Test Conditions

Conditions

¾¾

No load,

=4MHz

SYS

No load,

HALT mode

No load,

HALT mode

¾ ¾

¾¾ ¾¾

=2.7V

=0.3V

Ta=25°C

Min. Typ. Max. Unit

2.2

¾¾

2.1

-1 -2 ¾

3.6 V

12mA

0.9 V

0.7 V

1.5

2.4

¾ ¾

-50 -90 ¾mA

-8 -10 ¾

1.5 4

80 130

12 16

40 60 80

¾mA

A.C. Characteristics

Symbol Parameter

SYS

RES

SST

INT

Note: t

System Clock (RC OSC)

External Reset Low Pulse Width

System Start-up Timer Period

Interrupt Pulse Width

=1/f

SYS

Test Conditions

Conditions

¾ ¾

2.2V

¾¾

Power-up or

Wake-up from HALT

¾¾

6 July 24, 2000

Min. Typ. Max. Unit

400

4000

2000

1000

¾ ¾¾ms

1024

¾¾ms

Ta=25°C

kHz2.4V

SYS

Preliminary

Functional Description

Execution flow

The system clock for the HTG2150 is derived from an RC oscillator. The system clock is inter nally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles.

Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while decoding and execution takes the next in struction cycle. However, the pipelining scheme causes each instruction to effectively execute in one cycle. If an instruction changes the program coun ter, two cycles are required to complete the instruc tion.

Program counter - PC

The 13-bit program counter (PC) controls the sequence in which the instructions stored in the program ROM are executed and its contents specify a maximum of 8192 addresses.

After accessing a program memory word to fetch an instruction code, the contents of the program counter are incremented by one. The program counter then points to the memory word containing the next instruction code.

When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction.

T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4

System

Clock

PC PC+1 PC+2

F e tc h IN S T (P C )

Execute IN S T (PC -1)

F e tc h IN S T ( P C + 1 )

Execute IN S T (PC )

Execution flow

The conditional skip is activated by instruction. Once the condition is met, the next instruction, fetched during the current instruction execu

tion, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise pro ceed with the next instruction. The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination will be within 256 loca

tions.

When a control transfer takes place, an addi tional dummy cycle is required.

Program memory - ROM

The program memory, which contains execut able program instructions, data and table infor mation, is composed of a 16384 x 16 bit format. However as the PC (program counter) is com prised of only 13 bits, the remaining 1 ROM ad dress bit is managed by dividing the program memory into 2 banks, each bank having a range between 0000H and 1FFFH. To move from the present ROM bank to a different ROM bank, the higher 1 bit of the ROM address are set by the BP (Bank Pointer), while the remaining 13 bits of the PC are set in the usual way by executing the appropriate jump or call instruction. As the full 14 address bits are latched during the execution of a call or jump instruction, the correct value of the BP must first be setup before a jump or call is executed. When either a software or hardware interrupt is received, note that no matter which ROM bank the pro-

Bank0

0000H

1FFFH

R O M Address

A13 bit Latch

F e tc h IN S T (P C + 2 )

Execute INST (PC +1)

13 bits

Program

C ounter

Stack

Bank Pointer

R egister Bit5

Latch data on E xecution of Jum p or C all Instruction 16K Program R O M Addressing Architecture

HTG2150

Bank1

8192

Bits

2000H

3FFFH

7 July 24, 2000

Preliminary

HTG2150

gram is in the program will always jump to the appropriate interrupt service address in Bank

0. The original full 14 bit address will be stored on the stack and restored when the relevant RET/RETI instruction is executed, automati cally returning the program to the original ROM bank. This eliminates the need for pro grammers to manage the BP when interrupts occur. Certain locations in Bank 0 of program memory are reserved for special usage:

ROM Bank 0 (BP5~BP7=000B) The ROM bank 0 ranges from 0000H to 1FFFH.

Location 000H This area is reserved for the initialization program. After chip reset, the program al

Location 008H This area is reserved for the timer counter 0 in terrupt service program. If a timer interrupt re sults from a timer counter 0 overflow, and if the

interrupt is enabled and the stack is not full, the program begins execution at location 008H.

0000H

0004H

0008H

000C H

010H

014H

018H

D evice initialization program

External interrupt subroutine

Tim er counter 0 interrupt subroutine

U nused

Tim er 2 interrupt subroutine

Tim er 3 interrupt subroutine

D /A buffer em pty interrupt

Program ROM

ways begins execution at location 000H.

Location 004H This area is reserved for the external inter rupt service program. If the INT

input pin is activated, and the interrupt is enabled and the stack is not full, the program begins exe cution at location 004H.

Mode

*13 *12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0

3FFFH

Program Rom Address

16 bits

Program memory

Initial reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0

External interrupt 0 0 0 0 0 0 0 0 0 0 0 1 0 0

Timer counter 0 overflow 0 0 0 0 0 0 0 0 0 0 1 0 0 0

Timer 2 overflow 0 0 0 0 0 0 0 0 0 1 0 0 0 0

Timer 3 overflow 0 0 0 0 0 0 0 0 0 1 0 1 0 0

D/A buffer empty interrupt 0 0 0 0 0 0 0 0 0 1 1 0 0 0

Skip PC+2

Loading PCL *13 *12 *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0

Jump, call branch BP.5 #12 #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0

Return from subroutine S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

Note: *13~*0: Program ROM address

@7~@0: PCL bits #12~#0: Instruction code bits

Program rom address

S13~S0: Stack register bits BP.5: Bit 5 of bank pointer (04H)

8 July 24, 2000

Preliminary

HTG2150

Location 010H/014H This area is reserved for the timer 2/3 interrupt service program. If a timer interrupt results from a timer 2/3 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 010H/014H.

Location 018H This area is reserved for the D/A buffer empty interrupt service program. After the system latch a D/A code at RAM address 28H, the in terrupt is enable, and the stack is not full, the program begins execution at location 020H.

Location 020H For best condition, this is the starting loca tion for writing the program..

ROM Bank 1 (BP5~BP7=001B) The range of the ROM starts from 2000H to 3FFFH.

Table location Any location in the ROM space can be used as look up tables. The instructions TABRDC [m] (use for any bank) and TABRDL [m] (only used for last page of program ROM) transfers the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the table is well-defined. The higher-order byte of the table word are transferred to the TBLH. The table higher-order byte register (TBLH) is read only. The table pointer (TBHP, TBLP) is a read/write register (1FH, 07H), which indicates the table location. Before accessing the table, the location must be placed in TBLP. The TBLH is read only and cannot be restored. If the main routine and the ISR (Inter rupt Service Routine) both employ the table read instruction, the contents of the TBLH in

the main routine are likely to be changed by the table read instruction used in the ISR. Er rors can occur. In other words, using the table read instruction in the main routine and the ISR simultaneously should be avoided. How ever, if the table read instruction has to be ap plied in both the main routine and the ISR, the interrupt is supposed to be disabled prior to the table read instruction. It will not be en

abled until the TBLH has been backed up. All table related instructions need two cycles to complete the operation. These areas may function as normal program memory depend ing upon the requirements.

Stack register - STACK

This is a special part of the memory which is used to save the contents of the program coun ter (PC) only. The stack is organized into eight levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the stack pointer (SP) and is neither readable nor writeable. At a subroutine call or interrupt ac knowledgment, the contents of the program counter and ROM address A13 bit latch Data are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the program counter and ROM address A13 bit latch Data are restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack.

If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledgment will be inhibited. When the stack pointer is decremented (by RET or RETI), the interrupt will be serviced. This fea ture prevents stack overflow allowing the pro

Instruction(s)

TABRDC [m] #5 #4 #3 #2 #1 #0 @7 @6 @5 @4 @3 @2 @1 @0

TABRDL [m] 1 1 1 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0

Note: @7~@0: TBLP register bit 7~bit 0

#5~#0: TBHP register bit 13~bit 8

*13 *12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0

Table Location

Table location

*13~*0: Current Program ROM table

address bit 13~bit 0

9 July 24, 2000

Preliminary

HTG2150

grammer to use the structure more easily. In a similar case, if the stack is full and a CALL is subsequently executed, stack overflow occurs and the first entry will be lost (only the most recent eight return address are stored).

00H

IA R 0

01H

MP0

02H

IA R 1

03H

MP1

04H

05H

ACC

06H

PCL

07H

TBLP

08H

TBLH

09H

WDTS

STATUS

0AH

IN T C

0BH

TM R 0H

0C H

TM R 0L

0D H

TM R 0C

0EH

0FH

10H

11H

12H

PAC

13H

14H

PBC

15H

16H

17H

18H

19H

1AH

1BH

1C H

1D H

IN T C H

1EH

TBH P

1FH

20H

TM R 2

21H

TM R 2C

22H

23H

TM R 3

24H

TM R 3C

25H

X'TALC

26H

PW M C

27H

28H

PW M

29H

2AH

2BH

2C H

2D H

LC D C LC D C ontrol R egister

2EH

COM R

2FH

30H

3FH 40H

FFH

80H

A7H

Indirect Addressing R egister 0

M em ory P ointer 0

Indirect Addressing R egister 1

M em ory P ointer 1

Bank P ointer

A ccum ulato r

Program C ounter Lower-byte R egister

Table Pointer Low er-order Byte R egister

Table H igher-order Byte R egister

W atchdog Tim er O ption Setting R egister

Status R egister

Interrupt C ontrol R egister

Tim er C ounter 0 H igher-order B yte R egister

Tim er C ounter 0 Low er-order B yte R egister

Tim er C ounter 0 C ontrol R egister

PA I/O D ata R egister

PA I/O C ontrol R egister

PB I/O D ata R egister

PB I/O C ontrol R egister

Interrupt C ontrol H igher-order Byte R egister

Table Pointer H igher-order B yte R egister

Tim er 2 R egister

Tim er 2 C ontrol R egister

Tim er 3 R egister

Tim er 3 C ontrol R egister

X 'tal Fa st O scilla tor up C ontrol

PW M C ontrol

PW M Data

C om m on P ad A ddress R otator

G eneral Purpose

Bank 0 D ata M em ory

(192 B yte)

Bank 15 D ata M em ory

(40 B yte)

S p e c ia l P u rp o s e D ata M em ory

: U n u s e d

R ead as "00" PB bit 3/2/1/0 R ead=0

RAM mapping

Data memory - RAM

Bank 0 (BP4~BP0=00000) The Bank 0 data memory includes special purpose and general purpose memory. The special purpose memory is addressed from 00H to 2FH, while general purpose memory is addressed from 40H to FFH. All data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Ex cept for some dedicated bits, each bit in the data memory can be set and reset by the SET [m].i and CLR [m].i instructions, respectively. They are also indirectly accessible through the memory pointer registers (MP0;01H, MP1;03H).

Bank 15 (BP4~BP0=01111B) The range of RAM starts from 80H to A7H. On the LCD, every bit stands for one dot. If the bit is ²1², the light of the dot on the LCD will be turned on. If the bit is ²0², then it will be turned off. Only MP1 can deal with the memory of this range. The contrast form of RAM location, COM MON, and SEGMENT is as follows.

Indirect addressingregister

Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation of [00H] and [02H] access data memory are pointed to by MP0 (01H) and MP1 (03H) respectively. Reading location 00H or 02H indirectly will return the result 00H. Writing indirectly results in no operation. The function of data movement between two indirect addressing registers, is not supported. The memory pointer registers, MP0 and MP1, are 8-bit registers which can be used to access the data memory by combining corresponding indi rect addressing registers but Bank 15 can use MP1 only.

Accumulator

The accumulator is closely related to ALU oper ations. It is also mapped to location 05H of the data memory and it can carry out immediate data operations. The data movement between two data memories has to pass through the ac cumulator.

10 July 24, 2000

Preliminary

HTG2150

LCD driver output

The maximum output number of the HTG2150 LCD driver is 8´40. The LCD driver bias type is ²R²type, no external capacitor is required and the bias voltage is 1/4 bias. Some of the Segment out puts share pins with another pins, PB4~PB7 (SEG33~SEG36), INT

(SEG37), XOUT (SEG38), XIN (SEG39). Whether segment output or I/O pin can individually bedecided bymask option.

32H z

COM 0

COM 1

SEG 0

512H z

3/4 V 2/4 V 1/4 V

GND

3/4 V 2/4 V 1/4 V

GND

3/4 V 2/4 V 1/4 V

GND

LCD driver output can be enabled or disabled by setting the LCD (bit 6 of LCDC; 2EH) without the influence of the related memory condition. There is a special function for LCD display, which is Ro tate function. There are 8 kinds of Rotate func

tion, (user can changethe dataof theSS0 toSS3.)

An example of an lcd driving waveform (1/8 duty, 1/4 bias) is shown below.

LC D d isplay m em ory: (B ank 15)

Address

COM 0

COM 1

COM 2

COM 3

COM 4

COM 5

COM 6

COM 7

80H

Bit0

Bit1

Bit2

Bit3

Bit4

Bit5

Bit6

Bit7

SEG 0

81H

SEG 1

82H

SEG 2

83H

SEG 3

84H

SEG 4

85H

SEG 5

SEG 17

91H

92H

SEG 18

11 July 24, 2000

A7H

SEG 39

Preliminary

0~5

6 LCD Control the LCD output (0=disable; 1=enabled) (Default=1)

LCDC

7RC

Can R/W (Default 000000B)

LCD clock source select (Default=0) 1= 32768Hz crystal 0= system clock

LCDC register

HTG2150

Rotate

SSL3 SSL2 SSL1 SSL0

x000

x001

x010

x011

x100

x101

x110

x111

Description

The Pad of common 0 is connected to common 0 and the Pad of common 1 is connected to common 1 and so on.

The Pad of common 0 is connected to common 1 and the Pad of common 1 is connected to common 2 and so on.

The Pad of common 0 is connected to common 2 and the Pad of common 1 is connected to common 3 and so on.

The Pad of common 0 is connected to common 3 and the Pad of common 1 is connected to common 4 and so on.

The Pad of common 0 is connected to common 4 and the Pad of common 1 is connected to common 5 and so on.

The Pad of common 0 is connected to common 5 and the Pad of common 1 is connected to common 6 and so on.

The Pad of common 0 is connected to common 6 and the Pad of common 1 is connected to common 7 and so on.

The Pad of common 0 is connected to common 7 and the Pad of common 1 is connected to common 0 and so on.

2FH register

12 July 24, 2000

Preliminary

HTG2150

Arithmetic and logic unit - ALU

This circuit performs 8-bit arithmetic and logic operation. The ALU provides the following functions:

Arithmetic operations (ADD, ADC, SUB, SBC, DAA)

Logic operations (AND, OR, XOR, CPL)

Rotation (RL, RR, RLC, RRC)

Increment and Decrement (INC, DEC)

Branch decision (SZ, SNZ, SIZ, SDZ ....)

The ALU not only saves the results of a data op eration but also changes the status register.

Status register - STATUS

This 8-bit register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PD) and watchdog time-out flag (TO). It also records the status information and controls the operation se quence.

With the exception of the TO and PD flags, bits in the status register can be altered by instruc tions like any other register. Any data written into the status register will not change the TO or PD flags. In addition it should be noted that operations related to the status register may

give different results from those intended. The TO and PD flags can only be changed by system power up, Watchdog Timer overflow, executing the HALT instruction and clearing the Watch dog Timer.

The Z, OV, AC and C flags generally reflect the status of the latest operations.

In addition, on entering the interrupt sequence or executing the subroutine call, the status reg ister will not be automatically pushed onto the stack. If the contents of status are important and if the subroutine can corrupt the status

Interrupt

The HTG2150 provides an external interrupt and a PWM D/A interrupt and internal timer inter rupts. The Interrupt Control register (INTC;0BH, INTCH;1EH) contains the interrupt control bits to

set the enable/disable and the interrupt request

flags.

Once an interrupt subroutine is serviced, all

other interrupts will be blocked (by clearing the

EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may happen during this interval but only the inter-

Labels Bits Function

C is set if the operation results in a carry during an addition operation or if a bor-

AC 1

OV 3

PD 4

TO 5

row does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction.

AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared.

Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.

OV is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared.

PD is cleared when either a system powers up or a CLR WDT instruction is exe cuted. PD is set by executing the HALT instruction.

TO is cleared by a system power-up or executing the CLR WDT or HALT in struction. TO is set by a WDT time-out.

6, 7

Undefined bits, read as ²0².

Status register

13 July 24, 2000

Preliminary

HTG2150

rupt request flag is recorded. If a certain inter rupt needs servicing within the service routine, the programmer may set the EMI bit and the corresponding bit of the INTC to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related in terrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must be prevented from becoming full.

All these kinds of interrupt have a wake-up ca pability. As an interrupt is serviced, a control transfer occurs by pushing the program counter and A13 bit onto the stack followed by a branch to subroutines at specified locations in the pro gram memory. Only the program counter and A13 bit are pushed onto the stack. If the con tents of the register and Status register (STATUS) are altered by the interrupt service program which corrupt the desired control se quence, the contents should be saved first.

External interrupt is triggered by a high to low transition of INT quest flag (EIF; bit 4 of INTC) will be set. When the interrupt is enabled, and the stack is not full and the external interrupt is active, a sub routine call to location 04H will occur. The interrupt request flag (EIF) and EMI bits will be cleared to disable other interrupts.

The internal timer counter 0 interrupt is initialized by setting the timer counter 0 interrupt

and the related interrupt re

request flag (T0F; bit 5 of INTC), resulting from

a timer 0 overflow. When the interrupt is en abled, and the stack is not full and the T0F bit is set, a subroutine call to location 08H will oc cur. The related interrupt request flag (T0F) will be reset and the EMI bit cleared to disable

further interrupts.

The Timer 2/3 interrupts are operated in the same manner as timer 0. While ET2I/ET3I and T2F/T3F are the related control bits and the re

lated request flags of TMR2/TMR3, which lo cate at bit0/bit1 and bit4/bi5 of the INTCH respectively.

During the execution of an interrupt subroutine,

other interrupt acknowledgments are held until

the RETI instruction is executed or the EMI bit

and the related interrupt control bit are set to1(if the stack is not full). To return from the interrupt

subroutine, the RET or RETI instruction may be

invoked. RETI will set the EMI bit to enable an in terrupt service, but RET will not.

Interrupts occurring in the interval between

the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2

pulses, if the corresponding interrupts are en

abled. In the case of simultaneous requests the priorities applied are shown in the following table. These can be masked by resetting the EMI bit.

Controls the (global) interrupt (1=enable; 0=disable)

Controls the external interrupt

(1=enable; 0=disable)

Controls the timer counter 0 interrupt (1=enable; 0=disable)

Unused bit

External interrupt request flag (1=active; 0=inactive)

Internal timer counter 0 request flag (1=active; 0=inactive)

Unused bit

INTC register

14 July 24, 2000

INTC

0 EMI

1 EEI

2 ET0I

4 EIF

5 T0F

6, 7

Preliminary

Controls the Timer 2 interrupt (1=enable; 0=disable)

Controls the Timer 3 interrupt (1=enable; 0=disable)

Internal Timer 2 request flag (1=active; 0=inactive)

Internal Timer 3 request flag (1=active; 0=inactive)

INTCH register

INTCH

0 ET2I

1 ET3I

2 PWMI PWM D/A interrupt (1=enable; 0=disable)

¾ Should be set as ²0² always

4 T2F

5 T3F

6 PWMF PWM D/A flag (1=active; 0=inactive)

¾ Should be set as ²0² always

HTG2150

No. Interrupt Source Priority Vector

a External interrupt 1 04H

Timer counter 0

overflow

2 08H

d Timer 2 overflow 4 10H

e Timer 3 overflow 5 14H

f PWM D/A interrupt 6 18H

The timer counter 0 and Timer 2/3 interrupt request flag (T0F/T2F/T3F), External interrupt request flag (EIF), PWM D/A interrupt request flag (PWMF),Enable Timer 0/2/3 bit (ET0I/ET2I/ET3I) , Enable PWM D/A interrupt (PWMI), Enable external interrupt bit (EEI) and Enable master interrupt bit (EMI) constitute an interrupt control register (INTC/INTCH) which is located at 0BH/1EH in the data memory. EMI, EEI, ET0I, ET2I, ET3I, PWMI are used to control the en abling/disabling of interrupts. These bits prevent the requested interrupt from being serviced. Once the interrupt request flags (T0F, T2F, T3F, EIF, PWMF) are set, they will remain in the INTC/INTCH register until the interrupts are ser viced or cleared by a software instruction.

It is recommended that a program does not use the ²CALL subroutine² within the interrupt subroutine. Interrupts often occur in an unpre dictable manner or need to be serviced immedi ately in some applications. If only one stack is left

and enabling the interrupt is not well controlled, the ²CALL subroutine² should not operate in the in terrupt subroutine as it will damage the original control sequence.

Oscillator configuration

There are two oscillator circuits in the HTG2150.

OSCI

32768H z

R C O scillator

XIN

XOUT

R T C O s c illa to r

System and RTC oscillator

The RC oscillator signal provides the internal system clock. The HALT mode stops the system oscillator and ignores any external signal to

conserve power. Only the RC oscillator is de

signed to drive the internal system clock. The RTC oscillator provides the Timer 3 and LCD driver clock source. The RC oscillator needs an external resistor

connected between OSCI and VSS. The resis

tance value must range from 50kW to 400kW. However, the frequency of the oscillation may vary with V

due to process variations. It is, therefore, not suit

able for timing sensitive operations where accu

, temperature and the chip itself

rate oscillator frequency is desired.

15 July 24, 2000

+ 34 hidden pages

Holtek Semiconductor Inc HTG2150 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

General Description

Block Diagram

Pad Assignment

Pad Coordinates

Pad Description

Absolute Maximum Ratings

D.C. Characteristics

A.C. Characteristics

Functional Description