Holtek Semiconductor Inc HTG12B0 Datasheet
Features
Operating voltage: 2.4V~3.6V
·
Eight input lines
·
Eight input/output lines
·
Five working registers
·
4K ´ 8 ´ 4 program ROM
·
128 ´ 4 ´ 8 (4096) bits data memory RAM
·
Sound effect circuit
·
40 segment ´ 16 common, 1/4 bias LCD driver
·
LCD output is fixed at 4.4V
·
General Description
The HTG12B0 is a processor from HOLTEK¢s
4-bit stand-alone single chip microcontroller
specially designed for LCD display and time
piece product applications.
HTG12B0
4-Bit Microcontroller
RC oscillator & 32768Hz crystal oscillator
·
8-bit timer with internal or external clock
·
source
Internal timer overflow
·
Up to 4ms instruction cycle with 1MHz
·
system clock
One level subroutine nesting
·
Halt feature reduces power consumption
·
8-bit table read instruction
·
It is ideally suited for multiple LCD for time
piece low power applications among which are
calculators, scales, calendar and hand held
LCD products.
1 September 8, 1999
Block Diagram
HTG12B0
XIN
XOUT
OSCI
OSCO
RES
TEST1
TEST2
T1D
T512
VDD
VSS
C ontrol
&
Tim ing
Circuit
Stack
Program
C ounter
ROM
In stru ction
D ecoder
ROM B
RAMB
LC D C
Tem porary
D ata R AM
D isplay D ata R AM
R0
R1
R2
R3
R4
ALU
ACC
Tim er
PA
PB
PS
PM
Sound
Effect
TM C LK
PA0
PA1
PA2
PA3
PB0
PB1
PB2
PB3
PS0
PS1
PS2
PS3
PM 0
PM 1
PM 2
PM 3
BZ
BZ
VOUT1
VOUT2
VOUT3
VOUT4
SEG 0
Note: ACC: Accumulator
R0~R4: Working registers
ROMB: ROM bank switch
RAMB: RAM bank switch
LCDC: LCD control register
PA, PB: I/O ports
PS, PM: Input ports
VLC 1
LC D Driver
SEG 1
SEG 38
SEG 39
COM 1
COM 0
COM 3
COM 2
COM 15
VLC 2
VLC 3
VLC 4
2 September 8, 1999
Pad Assignment
HTG12B0
SEG 18
SEG 17
SEG 16
SEG 15
SEG 14
SEG 13
SEG 12
SEG 11
TEST2
TEST1
T512
PM 3
SEG 1
SEG 0
SEG 4
SEG 3
SEG 2
SEG 7
SEG 6
SEG 5
SEG 10
SEG 9
SEG 8
PM 2
PM 1
PM 0
PS3
PS2
PS1
PS0
TM CLK
RES
PB3
PB2
PB1
PB0
PA0
PA1
PA2
PA3
T1D
VDD
OSCO
OSCI
XOUT
XIN
VSS
BZ
BZ
94
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
(0 , 0 )
722673277428752976307731783279808182833784388539864087418842894390449145924693
71
SEG 19
70
SEG 20
69
SEG 21
68
SEG 22
67
SEG 23
66
SEG 24
65
SEG 25
64
SEG 26
63
SEG 27
62
SEG 28
61
SEG 29
60
SEG 30
59
SEG 31
58
SEG 32
57
SEG 33
56
SEG 34
55
SEG 35
54
SEG 36
53
SEG 37
52
SEG 38
51
SEG 39
50
COM 0
33
35
36
VLC1
VLC2
VLC3
VLC4
VOUT1
34
VOUT2
VOUT3
VOUT4
COM 15
COM 14
COM 13
COM 12
COM 11
COM 10
COM 9
COM 8
Chip size: 3060 ´ 5140 (mm)
COM 7
COM 6
COM 5
COM 4
2
49
47
48
COM 3
COM 2
COM 1
* The IC substrate should be connected to VSS in the PCB layout artwork.
3 September 8, 1999
HTG12B0
Pad Coordinates
Pad No. X Y Pad No. X Y Pad No. X Y
65 1398.48 972.60
66 1398.48 1092.60
67 1398.48 1381.40
68 1398.48 1501.40
69 1398.48 1790.20
70 1398.48 1910.20
71 1398.48 2199.00
72 1327.44 2436.28
73 1207.44 2436.28
74 1087.44 2436.28
75 967.44 2436.28
76 847.44 2436.28
77 727.44 2436.28
78 607.44 2436.28
79 487.44 2436.28
80 367.44 2436.28
81 247.44 2436.28
82 127.44 2436.28
83 7.44 2436.28
84
85
86
87
88
89
90
91
92
93
94
-112.56
-232.56
-352.56
-472.56
-592.56
-712.56
-832.56
-952.56
-1072.56
-1192.56
-1312.56
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
-1394.56
2
-1394.56
3
-1394.56
4
-1394.56
5
-1394.56
6
-1394.56
7
-1394.56
8
-1394.56
9
-1394.56
-1368.40
-1368.40
-1368.40
-1368.40
-1368.40
-1368.40 -217.16
-1368.40 -451.88
-1368.40 -700.68
-1368.40 -935.40
-1304.07 -1189.85
-1304.07 -1344.25
-1318.48 -1483.72
-1355.04 -1630.76
-1355.04 -1750.76
-1355.04 -1885.00
-1355.04 -2005.00
-1343.84 -2164.44
-1315.52 -2436.28
-1195.52 -2436.28
-1075.52 -2436.28
-955.52 -2436.28
-835.52 -2436.28
-715.52 -2436.28
2163.72 33 1204.48
2043.72 34 1324.48
1923.72 35 1398.48
1803.72 36 1398.48
1683.72 37 1398.48
1563.72 38 1398.48
1443.72 39 1398.48
1323.72 40 1398.48
1203.72 41 1398.48
998.68 42 1398.48
749.88 43 1398.48
515.16 44 1398.48
266.36 45 1398.48
31.64 46 1398.48
47 1398.48
48 1398.48
49 1398.48
50 1398.48
51 1398.48
52 1398.48
53 1398.48
54 1398.48
55 1398.48
56 1398.48
57 1398.48
58 1398.48
59 1398.48
60 1398.48
61 1398.48 155.00
62 1398.48 275.00
63 1398.48 563.80
64 1398.48 683.80
-2436.28
-2436.28
-2436.28
-2436.28
-2436.28
-2436.28
-2436.28
-2436.28
-2436.28
-2436.28
-2436.28
-2436.28
-2436.28
-2436.28
-2436.28
-2436.28
-2436.28
-2177.80
-1889.00
-1769.00
-1480.20
-1360.20
-1071.40
-951.40
-662.60
-542.60
-253.80
-133.80
Unit: mm
2436.28
2436.28
2436.28
2436.28
2436.28
2436.28
2436.28
2436.28
2436.28
2436.28
2436.28
4 September 8, 1999
Pad Description
HTG12B0
Pad No. Pad Name I/O
4~7
94, 1~3
8 TMCLK I
9 RES
17~14
10~13
19, 20 BZ, BZ
21 VDD I
23
22
25
24
26 VSS I
27~30 VLC1~VLC4 I
31~34 VOUT1~VOUT4 I
35~50 COM15~COM0 O
51~90 SEG39~SEG0 O
93
18
92
91
PS3~PS0
PM3~PM0
PA3~PA0
PB3~PB0
OSCI
OSCO
XIN
XOUT
T512
T1D
TEST1
TEST2
I
I
I/O
O Note 1 Sound effect outputs
I
O
I
O
O
O
I
I
Mask
Option
Pull-high or
None.
Note 2
Pull-high
or None.
Note 4
¾
CMOS or
NMOS with
Pull-high or
None.
Note 3
¾
¾
¾
¾
¾
¾
¾
¾
Description
Input pins for input only
Input for TIMER clock
TIMER can be clocked by an external clock or an
internal frequency source.
Input to reset an internal LSI
Reset is active on logical low level.
Input/output pins
Positive power supply
An external resistor between OSCI and OSCO is
needed for internal system clock.
32768Hz crystal oscillator for time base, LCD
clock
Negative power supply, GND
LCD system power 1/4 bias generated
LCDsystemvoltage booster condenserconnecting
terminal
Output for LCD panel common plate
LCD driver outputs for LCD panel segment
For test mode only
TEST1 and TEST2 are left open when the chip is
in normal operation (with an internal pull-high
resistor).
Note: 1. The system clock provides six different sources selectable by mask option to drive the
sound effect clock. If the Holtek sound library is used, only 128K and 64K are acceptable.
2. Each bit of ports PM, PS can be a trigger source of the HALT interrupt, selectable by
mask option.
3. Each bit of ports PA, PB can be selected as CMOS for output pin only, or as NMOS for
I/O pin with pull-high resistor or none by mask option.
4. 14 internal clock sources can be selected by mask option to drive TMCLK. Note that
TMCLK should not be connected to a pull high resistor if an internal source is used.
5 September 8, 1999
Absolute Maximum Ratings
HTG12B0
Supply Voltage ..............................-0.3V to 5.5V
Storage Temperature.................-50°Cto125°C
Input Voltage ......................V
-0.3 to VDD+0.3
SS
Operating Temperature ..................0°Cto70°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maxi
mum Ratings² may cause substantial damage to the device. Functional operation of this device
at other conditions beyond those listed in the specification is not implied and prolonged expo
sure to extreme conditions may affect device reliability.
D.C. Characteristics
Ta=25°C
Test Conditions
Symbol Parameter
V
DD
I
DD
Operating Voltage
Operating Current 3V
V
DD
Conditions
¾¾
No load,
=512kHz
f
SYS
Min. Typ. Max. Unit
2.4 3 3.6 V
¾
200 300
mA
Standby Current,
I
STB
(f
OFF and RTC ON,
SYS
3V Halt mode
¾
10 15
mA
LCD ON)
V
V
I
I
I
I
R
V
IL
IH
OL1
OH1
OL2
OH2
PH
LCD
Input Low Voltage 3V
Input High Voltage 3V
PA, PB, BZ and BZ
Output Sink Current
PA, PB, BZ and BZ
Output Source Current
Segment Output Sink
Current
Segment Output Source
Current
3V
3V
3V
3V
Pull-high Resistor 3V
V
Output Voltage
LCD
3V
¾
¾
=0.3V
V
OL
=2.7V
V
OH
VOL=0.44V
V
=4.4V
LCD
VOH=4.0V
V
=4.4V
LCD
PS, PM, RES
TMCLK
¾
0.8V
0
DD
¾
¾
1.5 3
-0.5 -1 ¾
100 200
30 60
,
50 100 150
3.96 4.4 4.84 V
0.2V
DD
V
DD
¾
¾mA
¾mA
V
V
mA
mA
kW
-
-
6 September 8, 1999
HTG12B0
A.C. Characteristics
Symbol Parameter
f
SYS
t
CY
f
TIMER
t
RES
f
SOUND
System Clock 3V
Cycle Time 3V
Timer I/P Frequency
(TMCLK)
Reset Pulse Width
Sound Effect Clock
*: Only these two clocking signal frequencies are supported by the Holtek sound library.
Test Conditions
V
DD
Conditions
R=620kW~51kW
f
=1MHz
SYS
3V
¾
¾¾
¾¾ ¾
Min. Typ. Max. Unit
128
¾
0
5
*64 or 128
¾
4
¾
1000 kHz
¾ms
1000 kHz
¾¾
¾
Functional Description
·
Program counter - PC
This counter addresses the program ROM and
is arranged as a 12-bit binary counter from PC0
to PC11 whose contents specify a maximum of 4096
addresses. The program counter counts with an
increment of 1 or 2 with each execution of an instruc
tion.
When executing the jump instruction (JMP,
JNZ, JC, JTMR,...), a subroutine call, initial reset, internal interrupt, RTC interrupt or returning from a subroutine, the program
counter is loaded with the corresponding instruction data as shown in the table.
Note: P0~P11: Instruction code
@: PC11 keeps current value
S0~S11: Stack register bits
ROMB0 and ROMB1 are set to 0 at
power on reset.
Program memory - ROM
The program memory is the executable memory
and is arranged in a 4096´8-bit format. There
are four banks for program memory in
HTG12B0, each bank shown in the figure can be
switched by assigning ROMB0 and ROMB1 (bit0
and bit1 of ROMB). ROMB is the ROM bank
pointer and can be written only by executing
²MOV ROMB, A² instruction. Bit 2 and bit 3 of
ROMB are unused bits. The address is specified
by the program counter (PC). Four special loca
tions are reserved as described next.
-
-
Location 000H: (Bank 0)
Activating the processor RES
pin causes the
first instruction to be fetched from location 0.
000H
004H
008H
00BH
F00H
FFFH
R e s e t in itia l p r o g r a m
Tim er interrupt subroutine
R T C interrupt subroutine
Page N look-up table
Page F look-up table (256 bytes)
8 bits
Program memory ROMB=XX00B
000H
004H
008H
00BH
F00H
FFFH
Tim er interrupt subroutine
R T C interrupt subroutine
Page N look-up table
Page F look-up table (256 bytes)
8 bits
Program memory ROMB=XX01B
Ta=25°C
ms
kHz
Program
ROM
Bank 0
Program
ROM
Bank 1
7 September 8, 1999
HTG12B0
·
Location 004H: (Bank 0~3)
Contains the timer interrupt resulting from a
TIMER overflow. If the interrupt is enabled, the
CPU begins execution at location 004H.
·
Location 008H: (Bank 0~3)
Activating the RTC of the processor with the
interrupts enabled causes the program to
jump to this location.
·
Locations n00H to nFFH: (Bank 0~3)
Each page in the program memory consists of
256 bytes. This area from n00H to nFFH and
F00H to FFFH can be used as a look-up table.
Instructions such as READ R4A, READ
MR0A, READF R4A, READF MR0A can read
the table and transfer the contents of the ta
ble to ACC and R4 or to ACC and a data mem
ory address specified by the register pair
R1,R0. However as R1,R0 can only store 8
bits, these instructions cannot fully specify
the full 12 bit program memory address. For
this reason a jump instruction should first be
used to place the program counter in the right
page. The above instructions can then be used
to read the look up table data.
Note that the page number n must be greater
than zero since some locations in page 0 are reserved for specific usage. This area may function as normal program memory.
The program memory mapping is shown in the
diagram.
Mode
Initial
reset
Internal
interrupt
RTC
interrupt
Jump, call
instruction
Conditional
branch
Return from
subroutine
PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
ROMB1 ROMB0 000000000000
ROMB1 ROMB0 000000000100
ROMB1 ROMB0 000000001000
ROMB1 ROMB0 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0
ROMB1 ROMB0 @ P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0
ROMB1 ROMB0 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
In the execution of an instruction, the program
counter is added before the execution phase, so
careful manipulation of READ MR0A and
READ R4A is required in the page margin.
000H
004H
008H
00BH
F00H
FFFH
-
Tim er interrupt subroutine
R T C interrupt subroutine
Page N look-up table
Page F look-up table (256 bytes)
8 bits
Program memory ROMB=XX10B
-
000H
004H
008H
00BH
F00H
FFFH
Tim er interrupt subroutine
R T C interrupt subroutine
Page N look-up table
Page F look-up table (256 bytes)
8 bits
Program memory ROMB=XX11B
Program Counter
Program
ROM
Bank 2
Program
ROM
Bank 3
Program memory
8 September 8, 1999
HTG12B0
R A M B ank 1
(RAM B=X001B)
Tem porary D ata A rea
00H
Tem porary D ata A rea
7FH
R A M B ank 0
(RAM B=X000B)
(128 x 4)
4 bits
00H
7FH
Temporary data memory
Stack register
The stack register is a group of registers used to
save the contents of the program counter (PC)
and is arranged into 13 bits ´ 1 level. One bit is
used to store the carry flag. An interrupt will
force the contents of the PC and the carry flag
onto the stack register. A subroutine call will
also cause the PC contents to be pushed onto
the stack; however the carry flag will not be
stored. At the end of a subroutine or an inter
rupt routine which is signaled by a return in
struction, RET or RETI restore the program
counter to its previous value from stack regis
ter. Executing ²RETI² instruction will restore
the carry flag from the stack register, but
²RET² does not.
Working registers - R0, R1, R2, R3, R4
There are five working registers (R0, R1, R2, R3,
R4) usually used to store the frequently accessed
intermediate results. Using the instructions INC
Rn and DEC Rn the working registers can increment (+1) or decrement (-1). The JNZ Rn (n=0, 1,
4) instruction makes efficient use of the working
registers as a program loop counter. Also the register pairs R0,R1 and R2,R3 are used as a data
memory pointer when the memory transfer instruction is executed.
Data memory - RAM
The static data memory (RAM) is arranged in
128´4-bit format and is used to store data. All
of the data memory locations are indirectly
addressable through the register pair R1,R0 or
R3,R2; for example MOV A,[R3R2] or MOV
[R3R2],A.
There are two areas in the data memory, the
temporary data area and display data area. Ac
cess to the temporary data area is from 00H to
R A M B ank 7
(RAM B=X111B)
00H
(128 x 4)
4 bits
Tem porary D ata A rea
7FH
(128 x 4)
4 bits
7FH of RAM bank 0~RAM bank 7. Access to the
display data area is from B0H to FFH of LCD
bank 0 and bank 1.
There are eight banks for the temporary data
memory in HTG12B0, each bank shown in the
figure can be switched by assigning
RAMB0~RAMB2 (bit 0~bit 2 of RAMB). RAMB
is the RAM bank pointer and can be written
only by executing ²MOV RAMB, A² instruction.
Bit 3 of RAMB is unused bit. Each bank maps to
different area of the data memory.
-
There are two banks for displaying the data
memory, each bank can be switched by the as
signment of LCDC0 (bit 0 of LCDC). LCDC is a
control register for LCD application and can be
written only by executing ²MOV LCDC, A² in
struction.
When data is written into the display data area,
it is automatically read by the LCD driver
which then generates the corresponding LCD
driving signals.
LC D B ank 0
(LCDC =XXX0B)
B0H
FFH
B0H
FFH
D isplay D ata Area
(80 x 4)
4 bits
LC D B ank 1
(LC DC =XXX1B)
D isplay D ata Area
(80 x 4)
4 bits
Display data memory
-
-
-
9 September 8, 1999
HTG12B0
The locations between the temporary and
display data areas are undefined and cannot be
used.
Accumulator - ACC
The accumulator is the most important data
register in the processor. It is one of the sources
of input to the ALU and the destination of the
results of the operations performed in the ALU.
Data to and from the I/O ports and memory also
passes through the accumulator.
Arithmetic and logic unit - ALU
This circuit performs the following arithmetic
and logic operations ...
·
Add with or without carry
·
Subtract with or without carry
·
AND, OR, Exclusive-OR
·
Rotate right, left through carry
·
BCD decimal adjust for addition
·
Increment, decrement
·
Data transfers
·
Branch decisions
The ALU not only outputs the results of data
operations, but also sets the status of the carry
flag (CF) in some instructions.
Timer/counter
The HTG12B0 contains a programmable 8-bit
count-upcounter which can be used to count external
events or used as a clock to generate an accurate
time base.
If the 8-bit timer clock is supplied by an exter
nal source from pin TMCLK, synchronization
problems may occur when reading the data
from the timer. It is therefore recommended
that the timer is stopped before retrieving the
data. The 8-bit counter will increment on the
rising edge of the clock whether it is internally
or externally generated.
The Timer/Counter may be set and read with
software instructions and stopped by a hard
ware reset or a TIMER OFF instruction. To re
start the timer, load the counter with the value
XXH and then issue a TIMER ON instruction.
Note that XX is the desired start count immedi
ate value of the 8 bits. Once the Timer/Counter
is started it increments to a maximum count of
FFH and then overflows to zero (00H). It then
continues to count until stopped by a TIMER
OFF instruction or a reset.
The increment from the maximum count of
FFH to a zero (00H) triggers a timer flag TF
and an internal interrupt request. The inter
rupt may be enabled or disabled by executing
the EI and DI instructions. If the interrupt is
enabled, the timer overflow will cause a subrou
tine call to location 4. The state of the timer flag
can also be tested with the conditional jump in
struction JTMR. The timer flag is cleared after
the interrupt or the JTMR instruction is exe
cuted.
If an internal source is used, the frequency is
determined by the system clock and the param
eter n as defined in the equation. The frequency
of the internal frequency source can be selected
by mask option.
Frequency of TIMER clock =
system clock
where n=0, 1, 2... 3 selectable by mask option.
RTC
There is a real time clock (RTC) function implemented on the HTG12B0. The RTC function is
used to generate an accurate time period. The
RTC circuit clock source comes from the 32768Hz
crystal oscillator. The block diagram is shown as
follows.
-
X'tal 32768H z
1
128
1
, n=0~7
n
2
M ask O ptio n
The output of RTC can be selected by mask op
tion.
256
Frequency of RTC output =
-
The RTC output is used to generate an inter
-
rupt signal.
n
2
, n=0~7
n
2
In te rru p t
-
-
-
-
-
-
-
-
10 September 8, 1999
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