Holtek Semiconductor Inc HT82V14 Datasheet
14-Bit CCD/CIS Analog Signal Processor
Features
Low power CMOS : 350 mW
·
9 ADC clock latency for digital data output
·
14-bit 6 MSPS A/D converter
·
3-channel correlated double sampler
·
1~6 programmable gain
·
Input clamp circuitry for CDS-mode
·
Internal/external circuitfor CIS
·
General Description
The HT82V14 is a complete analog signal pro
cessor for CCD imaging applications. It fea
tures a 3-channel architecture designed to
sample and condition the outputs of the
trilinear color CCD arrays. Each channel con
sists of an input clamp, Correlated Double
Sampler (CDS), offset DAC and Programmable
Gain Amplifier (PGA), multiplexed to a high
performance 14-bit A/D converter.
HT82V14
Internal/external voltage reference
·
Internal MUX for channel operation
·
1 or 3-channel operation
·
Pixel-rate or line-rate switch operation
·
Programmable 3-wire serial interface
·
+5V digital I/O compatibility
·
28-pin SOP/SOJ package
·
The CDS amplifiers may be disabled for use
with sensors such as Contact Image Sensors
(CIS) and CMOS active pixel sensors, which do
not require CDS.
The 14-bit digital output is multiplexed into an
8-bit output word that is accessed using two
read cycles. The internal registers are pro
grammed through a 3-wire serial interface,
which provides gain, offset, and operating mode
adjustments.
-
Block Diagram
RIN
GIN
BIN
CLP
CLP
CLP
CDSCLK1 CDSCLK2
O F F S E T R E F T C M L R E F
Voltage R eference
CDS
CDS
CDS
+
+
3´8 bits
DAC
Offset
+
VGA
VGA
VGA
3´2 bits
C oarse
Gain
OE
Pixel Rate
G uarantee
MUX
C onfig
R egister
1 July 12, 2000
PGA
3´5 bits
F in e
Gain
14-bit
ADC
ADC CLK
C ontrol
Port
D 13~D 0
SCLK
CS
SDATA
Pin Assignment
HT82V14
CDSCLK1
CDSCLK2
ADC CLK
OE
DRVDD
DRVSS
D 13/D 5
D 12/D 4
D 11/D 3
D 10/D 2
D9/D1
D8/D0
D7
D6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AVDD
AVSS
RIN
OFFSET
GIN
CML
BIN
REFT
REF
AVSS
AVDD
SLO AD
SCLK
SDATA
HT82V14
2 8 S O P /S O J
Pin Description
Pin No. Pin Name I/O Description
1 CDSCLK1 DI CDS reset clock pulse input
2 CDSCLK2 DI CDS data clock pulse input
3 ADCCLK DI A/D sample clock input for 3-channels mode
4OE
5 DRVDD
6 DRVSS
14~7 D0~D13 DO Digital data output
15 SDATA DIO Serial data input/output
16 SCLK DI Clock input for serial interface
17 CS
18, 27 AVSS
19, 28 AVDD
20 REF
21 REFT AO Reference decoupling
22 BIN AI Analog Input, blue
23 CML AO Internal reference output
24 GIN AI Analog Input, green
25 OFFSET AO CIS reference decoupling
26 RIN AI Analog input, red
DI Output enable
¾
¾
Digital driver power
Digital driver ground
DI Chip select
¾
¾
Analog ground
+5V analog supply
AO Reference decoupling
2 July 12, 2000
Absolute Maximum Ratings
HT82V14
Supply Voltage .............................-0.3V to 5.5V
Input Voltage ................V
-0.3V to VDD+0.3V
SS
Storage Temperature ......................0°Cto70°C
Operating Temperature ...............25°Cto50°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maxi
mum Ratings² may cause substantial damage to the device. Functional operation of this device
at other conditions beyond those listed in the specification is not implied and prolonged expo
sure to extreme conditions may affect device reliability.
Electrical Characteristics
Symbol Parameter
Conversion Rate
3-channel Mode with CDS
1-channel Mode with CDS
A/D Converter
Resolution
Integral Nonlinearity
(INL)
Differential Nonlinearity
(DNL)
Analog Inputs
Full-scale Input Range
Input Limits
Input Capacitance
Input Current
Amplifiers
Coarse Gain Range
Coarse Gain Resolution
PGA Gain Range
PGA Gain Resolution
Offset Range
Offset Resolution
Test Conditions
Min. Typ. Max. Unit
V
5V±10% ¾¾¾
5V±10% ¾¾¾
DD
Conditions
6 MSPS
5 MSPS
5V±10% ¾¾14¾
5V±10% ¾¾±4.5 ¾
5V±10% ¾-0.5 ¾
1.2 LSB
5V±10% ¾¾4¾
TBD
TBD
¾
AV
DD
¾
¾mA
3 V/V
5V±10% ¾ AV
-0.3 ¾
DD
5V±10% ¾¾
5V±10% ¾¾
5V±10% ¾
1
5V±10% ¾¾2¾
5V±10% ¾
1
¾
2 V/V
5V±10% ¾¾5¾
5V±10% ¾-200 ¾
200 mV
5V±10% ¾¾8¾
+0.3
BIT
LSB
Vp-p
V
pF
Bits
Bits
Bits
-
-
3 July 12, 2000
HT82V14
Symbol Parameter
Power Supplies
AVDD
DRVDD
Power Consumption
Power Consumption
Digital Specifications
Symbol Parameter
Logic Inputs
V
IH
V
IL
I
IH
I
IL
C
IN
High Level Input Voltage 3.3V~5V
Low Level Input Voltage 3.3V~5V
High Level Input Current 3.3V~5V
Low Level Input Current 3.3V~5V
Input Capacitance 3.3V~5V
Logic Outputs
V
V
V
V
C
OH
OH
OL
OL
OUT
High Level Output Voltage 3.3V~5V
High Level Output Voltage 3.3V~5V
Low Level Output Voltage 3.3V~5V
Low Level Output Voltage 3.3V~5V
Output Capacitance 3.3V~5V
Test Conditions
Min. Typ. Max. Unit
V
5V±10% ¾
5V±10% ¾
5V±10% ¾¾
DD
Conditions
4.75
4.75
¾
¾
350
Test Conditions
Min. Typ. Max. Unit
V
DD
Conditions
¾
2.0
¾¾¾
¾¾10¾mA
¾¾10¾mA
¾¾10¾
I
=50mA
OH
I
=0.5mA
OH
=-50mA ¾¾
I
OL
=-0.6mA ¾¾
I
OL
4.5 4.9
2.4
¾¾5¾
5.25 V
5.25 V
¾
¾¾
0.8 V
¾
¾¾
0.1 V
0.4 V
mW
V
pF
V
V
pF
4 July 12, 2000
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