Holtek Semiconductor Inc HT827A0 Datasheet

8-Bit Microcontroller with Voice ROM

Features

8-bit microcontroller

Operating voltage: 2.4V~5.2V

8K´16 program ROM

208´8 data RAM

36 bidirectional I/O lines

Interrupt input

16-bit programmable timer/event

counter with overflow interrupts Watchdog timer

On-chip crystal or RC types of oscillator

Voice and melody synthesizer

128K´8 voice ROM

3/4 bit ADPCM coding algorithm

26 kinds of voice sampling rates

Tone level of 4 octaves

14 kinds of melody beats

Applications

Intelligent educational toys

High end toy controllers

Talking alarm clocks

HT827A0

Halt function and wake-up feature reduces

power consumption 63 powerful instructions

Up to a 1ms instruction cycle with a 4MHz

system clock at V All instructions in 1 or 2 machine cycles

16-bit table read instruction

8-level subroutine nesting

Bit manipulation instruction

Current type of D/A switch output

Tone generator counter

Controllable volume

48-pin DIP package

Alert and warning systems

Public address systems

Sound effect generators

=5V

General Description

The HT827A0 is 8-bit high performance microcontroller with a voice synthesizer and tone generator. They are designed for applications on multiple I/Os with sound effects. The LSIs provide 26 kinds of voice sampling rates, 4 octaves of tone level as well as a high quality of

current type D/A output. With such a flexible structure, the HT827A0 is excellent for versatile voice and sound effect product applications. It also includes a halt function to reduce power consumption.

1 March 15, 2000

Block Diagram

IN T

HT827A0

TM R

OSC1

OSC2

8-bit H igh P erform ance

RES

VDD

VSS

PA0

PA7

PB0 PB7 PC0 PC7

Pin Assignment

PA3

PA2

PA1

PA0

PB3

PB2

PB1

PB0

VSS

PE0

PE1

PE2

PE3

IN T

TM R

PD0

PD1

PD2

PD3

PD4

PD5

PD6

PD7

0 6& %) 

"&, 12

M icrocontroller

PB4

PB5

PB6

PB7

PA4

PA5

PA6

PA7

OSC2

OSC1

VDD

RES

AUD

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

36-bit Bidirectional

I/O P o r ts

PD0 PD7 PE0 PE3

Voice RO M & C ontroller

Voice

Synthesizer &

Tone generator

C urrent T ype

D/A Output

AUD

2 March 15, 2000

Pad Assignment

HT827A0

PA7

PB4

PA3

PA2

PA1

PA0

PB6

PB5

PA4

PB7

PA6

PA5

PB3

PB2

PB1

PB0

VSS

PE0

PE1

PE2

PE3

IN T

TM R

13 14 15 16 17

PD0

PD2

PD1

42 43

20 21 22

PD7

PD6

PD5

PD4

PD3

39 40

(0 ,0 )

23 24

PC3

PC2

PC1

PC0

25 26

PC5

PC4

36 37 38

OSC2

OSC1

VDD

RES

AUD

PC7

PC6

Chip size: 3555 ´ 5015 (mm)

* The IC substrate should be connected to VSS in the PCB layout artwork.

* The TMR pad must be bound to VDD or VSS if it is not used.

3 March 15, 2000

HT827A0

Pad Coordinates

Pad No. X Y Pad No. X Y

10 11 12 13 14 15 16 17 18 19 20 21 22

1 2 3 4 5 6 7 8 9

-1543.05

-1486.75

-1486.75 -28.35

-1486.75 -219.25

-1547.75 -2211.75

-1389.55 -2211.75

-1239.35 -2211.75

-1072.15 -2211.75

-913.45 -2211.75

-744.65 -2211.75

-585.95 -2211.75

-417.15 -2211.75

-258.45 -2211.75

-89.65 -2211.75

2242.95 23 69.05

1675.25 24 237.85

1491.25 25 598.35

1308.95 26 890.95

1126.15 27 1184.35

925.35 28 1476.95

727.25 29 1507.85

538.35 30 1499.05

347.85 31 1539.95

157.35 32 1585.75 33 1574.15 34 1502.55 2242.95 35 1227.35 2242.95 36 951.35 2242.95 37 676.15 2242.95 38 396.95 2242.95 39 119.35 2242.95 40 41 42 43 44

-159.85

-437.45

-716.65

-991.85

-1267.85

Unit: mm

-2211.75

-2291.45

-2091.35

-1925.15

-1757.35

-1465.55

-667.75

2242.95

Pad Description

Pad No. Pad Name I/O

1, 44~42, 37~34

5~2, 41~38

21~28 PC0~PC7 I/O

PA0~PA7 I/O

PB0~PB7 I/O

Mask

Option

Wake-up Pull-high

or None

Pull-high

or None

Pull-high

or None

Description

Bidirectional 8-bit input/output ports Each bit can be configured as a wake-up input by mask option. Software instructions determine the CMOS output or schmitt trigger input with or without a pull-high resistor (mask option).

Bidirectional 8-bit input/output ports Software instructions determine the CMOS output or schmitt trigger input with or without a pull-high resistor (mask option).

4 March 15, 2000

HT827A0

Pad No. Pad Name I/O

13~20 PD0~PD7 I/O

6 VSS

7~10 PE0~PE3 I/O

11 INT

12 TMR I

29 AUD O

30 RES

31 VDD

32 33

OSC1 OSC2

¾¾

IOCrystal or

Mask

Option

Pull-high

or None

Pull-high

or None

Description

Bidirectional 8-bit input/output ports Software instructions determine the CMOS output or schmitt trigger input with or without a pull-high resistor (mask option).

Negative power supply, ground

Bidirectional 8-bit input/output ports Software instructions determine the CMOS output or schmitt trigger input with or without a pull-high resistor (mask option).

External interrupt schmitt trigger input with a pull-high resistor Edge triggered is activated on a high to low transition.

Schmitt trigger input for a timer/event counter

Audio output for driving an external transistor PMOS open drain output

Schmitt trigger reset input, active low

Positive power supply

OSC1 and OSC2 connect to an RC network or crystal os cillator (determined by mask option) for an internal sys tem clock. In the case of RC operation, an oscillation resistor connects to OSC1. OSC2 is the output terminal of a 1/4 system clock.

Absolute Maximum Ratings

Supply Voltage..............................-0.3V to 5.5V

Input Voltage.................V

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maxi

mum Ratings² may cause substantial damage to the device. Functional operation of this de vice at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.

-0.3V to VDD+0.3V

Storage Temperature.................-50°Cto125°C

Operating Temperature ..............-25°Cto70°C

5 March 15, 2000

HT827A0

D.C. Characteristics

Symbol Parameter

DD1

DD2

STB1

STB2

IL1

IH1

OL1

OH1

OL2

OH2

Operating Voltage

Operating Current (Crystal OSC)

Operating Current (RC OSC)

Standby Current (WDT Enabled)

Standby Current (WDT Disabled)

Input Low Voltage for I/O Ports

Input High Voltage for I/O Ports

Input Low Voltage (RES

, TMR, INT)

Input High Voltage (RES

, TMR, INT)

I/O Port Sink Current (PA, PC, PD, PE)

I/O Port Source Current (PA, PC, PD, PE)

PB Sink Current

PB Source Current

Pull-high Resistance of I/O Ports & INT

Max. AUD Output Current

Test Conditions

Conditions

¾¾

No load,

=4MHz

SYS

No load,

=4MHz

SYS

No load, system Halt

¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾

=0.3V

=0.5V

=2.7V

=4.5V

=0.3V

=0.5V

=2.7V

=4.5V

¾ ¾

=0.6V

Ta=25°C

Min. Typ. Max. Unit

2.4

1.5 3 mA

¾ ¾

1.5 3 mA

2.5 5 mA

¾ ¾¾ ¾¾ ¾¾ ¾¾

2.4

4.0

2.4

4.0

610

-1 -1.5 ¾

-2 -4 ¾

610

20 25

-0.5 -1 ¾

-1 -2 ¾

25 50 100

10 30 60

-1.5 -2 ¾

-3.5 -4 ¾

5.2 V

35mA

0.6 V

1.0 V

¾ ¾ ¾ ¾ ¾ ¾ ¾

0.6 V

1.0 V

kW kW

6 March 15, 2000

HT827A0

A.C. Characteristics

Symbol Parameter

SYS1

SYS2

TIMER

WDTOSC

WDT1

WDT2

RES

INT

Note: t

System Clock (Crystal OSC)

System Clock (RC OSC)

Timer I/P Frequency (TMR)

Watchdog Oscillator 5V

Watchdog Timeout Period (RC) 5V

Watchdog Timeout Period (System Clock)

External Reset Low Pulse Width 5V

Interrupt Pulse Width 5V

SYS

=1/(f

SYS

)

Test Conditions

Conditions

Without WDT prescaler

Without WDT

prescaler

Ta=25°C

Min. Typ. Max. Unit

400

31 78 140

4000 kHz

82036ms

1024

¾¾ms

SYS

7 March 15, 2000

Functional Description

Executive flow

The HT827A0 provides a system clock which is derived from a crystal or an RC type of oscillator. The clock is internally divided into four non-overlapping clocks denoted by P1, P2, P3 and P4. An instruction cycle consists of T1~T4.

Instruction fetching and execution are pipelined in such a way that a fetch takes an in struction cycle while decoding and execution take the next instruction cycle. The pipelining scheme causes each instruction to execute ef fectively in a cycle. If an instruction changes the program counter, two cycles are required to complete that instruction.

Program counter - PC

The program counter (PC) controls the se quence in which the instructions stored in the program ROM are executed.

The contents of the program counter are incre mented by one after a program memory word is accessed to fetch an instruction code. The pro

gram counter then points to a memory word containing the next instruction code.

The PC manipulates a program transfer by loading the address corresponding to each in struction when executing a jump instruction, conditional skip execution, loading PCL regis ter, subroutine call, initial reset, internal inter rupt, external interrupt or return from

subroutine.

The conditional skip is activated by instructions. Once the condition is satisfied, the next instruc

tion, fetched during the current instruction exe

cution, is discarded and a dummy cycle replaces it to get a proper instruction. Otherwise, the sys tem will proceed with the next instructions.

The lower byte of the program counter (PCL) is a readable and writable register (06H). Moving

data into PCL performs a short jump. The desti

nation is within 256 locations.

Once a control transfer takes place, the execu

tion suffers from an additional dummy cycle.

HT827A0

S yste m C lock

OSC2 (RC only)

T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4

PC PC+1 PC+2

F e tc h IN S T (P C )

Execute IN S T (P C -1)

F e tc h IN S T (P C + 1 )

Execute IN S T (P C )

F e tc h IN S T (P C + 2 )

Execute IN S T (P C +1)

Execution flow

8 March 15, 2000

Internal Phase C lo cks

HT827A0

Program memory - ROM

The program memory stores the to-be-executed program instructions. It also includes data, ta ble and interrupt entries, addressed by the pro gram counter along with the table pointer.

The program memory size for HT827A0 is 8K´16.

Certain locations in the program memory are reserved for special usage:

Location 000H This area is reserved for program initializa

tion. The program always begins execution at location 000H each time the system is reset.

Location 004H This area is reserved for an external interrupt

service program. The program begins execu tion at location 004H if the INT

input pin is activated, the interrupt is enabled and the stack is not full.

Location 008H This area is reserved for a voice sampling rate

counter interrupt service program. The pro gram begins execution at location 008H if a timer interrupt results from a sampling rate

000H

004H

008H

00C H

1FFFH

D evice initialization program

External interrupt subroutine

Sam pling rate counter interrupt subroutine

Tim er/event counter interrupt subroutine

Look-up table (256 w ords)

Program ROM

Program memory

counter overflow, the interrupt is enabled and the stack is not full.

Location 00CH This area is reserved for a timer/event coun

ter interrupt service program. The program begins execution at location 00CH if an inter rupt results from a timer/event counter over

flow, the interrupt is enabled and the stack is

not full.

Mode

*12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0

Program Counter

Initial reset 00000000000 0 0

External interrupt 00000000001 0 0

Sampling rate counter overflow

Timer/event counter overflow

00000000010 0 0

00000000011 0 0

Skip PC+2

Loading PCL *12 *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0

Jump, call branch #12 #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0

Return from subroutine S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

Program counter

Note: *12~*0: Bits of program counter S12~S0: Bits of stack register

#12~#0: Bits of instruction code @7~@0: Bits of PCL

9 March 15, 2000

HT827A0

Table location Any location in the program ROM can be used

as a look-up table. The instructions ²TABRDC [m]² (the current page, 1 page=256 words) and ²TABRDL [m]² (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the ta ble is well-defined. The other bits of the table word are transferred to the lower portion of TBLH. The higher-order byte register (TBLH) of the table is read only. The table pointer (TBLP), on the other hand, is a read/write register (07H) indicating the table location. This location must be placed in TBLP before accessing the table. All the table related instructions require 2 cycles to com plete an operation. These areas may function as a normal program memory depending upon the user¢s requirements.

Stack register - Stack

The stack register is a special part of the mem ory used to save the contents of the program counter (PC). This stack is organized into 8 levels. It is neither part of the data nor program space, and cannot be read or written to. Its activated level is indexed by a stack pointer (SP) and cannot be read or written to. At a subroutine call or interrupt acknowledgment, the contents of the program counter are pushed onto the stack. The program counter is restored to its previous value from the stack at the end of a subroutine or interrupt routine, which is signaled by a return instruction (RET or RETI). After a chip resets, SP will point to the top of the stack.

The interrupt request flag will be recorded but the acknowledgment will be inhibited when the stack is full and a non-masked interrupt takes place. After the stack pointer is decremented (by RET or RETI), the interrupt will be ser viced. This feature prevents stack overflow and allows programmers to use the structure more easily. In a similar case, if the stack is full and a ²CALL² is subsequently executed, stack over

flow occurs and the first entry is lost.

Data memory - RAM

The data memory is further divided into two functional groups, namely, special function reg isters and general purpose data memories. Al though most of them can be read or be written to, some are read only.

The data memory size for HT827A0 is shown as

follows.

Pard No.

HT827A0 00H~2FH 30H~FFH

The special function registers include an indi

rect addressing register (00H), timer/event counter high byte register (TMRH; 0FH), timer/event counter low byte register (TMRL; 10H); timer/event counter control register (TMRC; 11H), program counter lower-order byte register (PCL; 06H), memory pointer register (MP; 01H), accumulator (ACC; 05H), table pointer (TBLP; 07H), table higher-order byte register (TBLH; 08H), status register (STATUS; 0AH), interrupt control register (INTC; 0BH), watchdog timer option setting register (WDTS; 09H), I/O registers (PA; 12H, PB; 14H, PC; 16H, PD; 18H, PE; 1AH) and I/O

Special

RAM

RAM Address

General

Instruction(s)

TABRDC [m] P12 P11 P10 P9 P8 @7 @6 @5 @4 @3 @2 @1 @0

TABRDL [m] 1 1 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0

Note: *12~*0: Bits of table location P12~P8: Bits of current program counter

@7~@0: Bits of table pointer

*12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0

Table Location

Table location

10 March 15, 2000

HT827A0

Ind irect A dd ressing R e giste r

00H

01H

02H

03H

04H 05H

06H

07H

08H

09H

0AH

0BH

0C H

0D H

0EH

0FH

10H

11H

12H

13H

14H

15H

16H

17H

18H

19H

1AH

1BH

1C H

1D H

1EH

1FH

20H

21H

22H 23H

24H

25H

26H

27H 28H

29H

2AH

2BH

2C H

2D H

2EH

2FH 30H

G eneral P urpose DATA M EM ORY

FFH

ACC

PCL

TBLP

TBLH

WDTS

STATUS

IN T C

TM R H

TM R L

TM RC

PAC

PBC

PCC

PDC

PEC

DAL

DAH

VCR

SRC

BEAT

TEM PO

TO N E

ROM C

RAM mapping

Special P urpose

DATA M EM ORY

: U n u s e d

R ead as "00"

control registers (PAC; 13H, PBC; 15H, PCC; 17H, PDC; 19H, PEC; 1BH). The 20H to 2FH are used for sound and tone (melody) synthesis. The function registers include a lower-order byte register (DAL; 20H) of D/A data, higher-order byte register (DAH;21H) of D/A data , volume control register (VCR; 22H), sam pling rate control register (SRC; 23H), beat con trol register (BEAT; 28H), tempo control register (TEMPO; 29H), tone control register (TONE; 2AH) and voice ROM control register (ROMC; 2CH). The remaining space before 30H is reserved for future expansion. Reading these remaining locations will get ²00H². The general purpose data memory is used for data and con trol information under instruction commands.

All of the areas of data memory can handle arithmetic, logic, increment, decrement and ro tate operations directly. Except for some dedi cated bits, each bit in the data memory can be set and reset by ²SET [m].i² and ²CLR [m].i², and can also be indirectly accessed through a memory pointer register (MP; 01H).

Indirect addressing register

Location 00H is an indirect addressing register that is not physically implemented. Any read/write operation of [00H] accesses the data memory pointed to by MP (01H). Indirectly reading location 00H will return the result to 00H whereas, indirectly writing it will have no effect.

Arithmetic and logic unit - ALU

This circuit performs 8-bit arithmetic and logic operations. ALU provides the following functions:

Arithmetic operations (ADD, ADC, SUB, SBC, DAA)

Logic operations (AND, OR, XOR, CPL)

Rotation (RL, RR, RLC, RRC)

Increment & decrement (INC, DEC)

Branch decision (SZ, SNZ, SIZ, SDZ ....)

ALU not only saves the results of a data opera tion but also change the status register.

11 March 15, 2000

HT827A0

Status register - STATUS

This 8-bit register (0AH) consists of a zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PD) and watchdog time-out flag (TO). It also records the status information and controls the operation sequence. Except the TO and PD flags, bits in the status register can be altered by instructions similar to other registers. Any data written into the status register will not change the TO or PD flag. Opera tions related to the status register may yield dif ferent results from those intended. The TO and PD flags can be altered only by a watchdog timer overflow, chip power-up, clearing the watchdog time or executing the ²HALT² instruction. The Z, OV, AC and C flags generally reflect the statuses of the latest operations. The status register will not be pushed onto the stack automatically on entering the interrupt sequence or executing the subroutine call. If the status contents are important and the subrou tine may corrupt the status register, the pro grammer must take precautions and save it properly.

Labels Bits Function

C is set if an operation results in a carry during an addition operation or if a bor-

AC 1

OV 3

PD 4

TO 5

row does not take place during a subtraction operation; otherwise C is cleared. It is also affected by a rotate through carry instruction.

AC is set if the operation results in a carry out of the low nibbles in addition or if no borrow from the high nibble into the low nibble in subtraction takes place; otherwise AC is cleared.

Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.

OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa, otherwise OV is cleared.

PD is cleared by a system power-up or executing the ²CLR WDT² instruction. PD is set by executing the ²HALT² instruction.

TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² in structions. TO is set by a WDT time-out.

Undefined, read as ²0²

Interrupt

The HT827A0 provides an external interrupt in addition to two internal timer/event counter in terrupts. The interrupt control register (INTC; 0BH) includes interrupt control bits to set the enable/disable and the interrupt request flags.

Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clear ing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt re

quests may happen during this interval but

only the interrupt request flag is recorded. If

an interrupt needs servicing within the ser vice routine, the programmer may set the EMI bit and the corresponding bit of INTC, allow ing interrupt nesting. If the stack is full, the interrupt request will not be acknowledged till the SP is decremented, whether or not the re lated interrupt is enabled. If immediate ser vice is desired, the stack has to be prevented from becoming full.

All these interrupts have a wakeup capability.

As an interrupt is serviced, a control transfer

occurs by pushing the program counter onto the

STATUS register

12 March 15, 2000

HT827A0

stack and then branching to subroutines at the specified location(s) in the program memory. Only the program counter is pushed onto the stack. The programmer must save the contents of the register or status register (STATUS) in advance if they are altered by an interrupt ser vice program which corrupts the desired con trol sequence.

External interrupts are triggered by a high to low transition of INT quest flag (EIF; bit 4 of INTC) are also set. When an interrupt is enabled, the stack is not full and the external interrupt is active, a sub routine call to location 04H will occur. The in terrupt request flag (EIF) and EMI bits will be cleared to disable other interrupts.

The sampling rate counter interrupt is initial ized by setting a sampling rate counter inter rupt request flag (SRF; bit 5 of INTC), which is caused by a timer overflow. When an interrupt is enabled, the stack is not full and the SRF bit is set, a subroutine call to location 08H will oc cur. The related interrupt request flag (SRF) will be reset and the EMI bit be cleared to dis able further interrupts.

. The related interrupt re

The internal timer/event counter interrupt is initialized by setting a timer/event counter in terrupt request flag (TF; bit 6 of INTC), which is caused by a timer overflow. When an inter rupt is enabled, the stack is not full and the TF bit is set, a subroutine call to location 0CH will

occur. The related interrupt request flag (TF)

will be reset and the EMI bit will be cleared to disable further interrupts.

During the execution of an interrupt subrou

tine, other interrupt acknowledgments are all held until the ²RETI² instruction is executed or

the EMI bit and the related interrupt control

bit are set to 1 (if the stack is not full). To return from an interrupt subroutine, ²RET² or ²RETI² may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not.

Interrupts occurring in an interval between the rising edges of two consecutive T2 pulses will be serviced at the latter of the two T2 pulses if the corresponding interrupts are enabled. In the

case of simultaneous requests, they can be masked by resetting the EMI bit. The following

table illustrates the priority of applying the si multaneous requests:

Controls a master (global) interrupt (1=enabled; 0=disabled)

Controls an external interrupt (1=enabled; 0=disabled)

Controls a sampling rate counter interrupt (1=enabled; 0=disabled)

Controls a timer/event counter interrupt (1=enabled; 0=disabled)

External interrupt request flag (1=active; 0=inactive)

Sampling rate counter request flag (1=active; 0=inactive)

Internal timer/event counter request flag (1=active; 0=inactive)

INTC register

13 March 15, 2000

INTC

(0BH)

0 EMI

1 EEI

2 ESI

3 ETI

4 EIF

5 SRF

6TF

¾ Unused bit, read as ²0²

HT827A0

No.

Interrupt

Source

Priority Vector

a External Interrupt 1 04H

Sampling Rate

Counter Overflow

Timer/Event

Counter Overflow

2 08H

3 0CH

The timer/event counter interrupt request flag (TF), external interrupt request flag (EIF), sam pling rate counter interrupt request flag (SRF), enable timer/event counter bit (ETI), enable ex ternal interrupt bit (EEI), enable sampling rate counter bit (ESI) and enable master interrupt bit (EMI) make up an interrupt control register (INTC) which is located at 0BH in the data mem ory. EMI, EEI, ESI and ETI are used to control the enable/disable status of interrupts. These bits prevent the requested interrupt from being ser viced. Once the interrupt request flags (TF, SRF, EIF) are all set, they will remain in the INTC reg ister till the interrupts are serviced or cleared by a software instruction.

The ²CALL subroutine² is preferably not used within the interrupt subroutine. This is because interrupts often occur in an unpredictable manner or required to be serviced immediately in certain applications. If only one stack is left and enabling the interrupt is not well controlled, operation of the ²call² in the interrupt subroutine will damage the original control sequence.

Oscillator configuration

The HT827A0 provides two kinds of oscillator circuits, namely, RC and crystal oscillators, for system clocks. Selection of the oscillator circuit type is determined by mask option. When the device enters the HALT mode, the system oscil lator stops to conserve power. The system clock is later reset with an external signal.

If an RC type of oscillator is used, an external resistor between OSC1 and GND is required and the range of the resistance has to be from 51kW to 1MW. The system, divided by 4, is available on OSC2, which synchronizes exter nal logic. The RC type of oscillator provides the most cost-effective solution. Nonetheless, the

OSC1

OSC2

C rystal O scilla to r

SYS

System oscillator

frequency of the oscillation may vary with

VDD, temperature and the chip itself due to

process variations. It is, therefore, not suitable

for timing sensitive operations where an accu

rate oscillator frequency is demanded.

On the other hand, if a crystal type of oscillator is used instead, a crystal across OSC1 and OSC2

is required, providing feedback and phase shift

for the oscillator. No other external components are needed. The resonator can replace the crys

tal and connects between OSC1 and OSC2 so

that a frequency reference can be derived. But

two external capacitors in OSC1 and OSC2 are

required.

The WDT oscillator is a free running on-chip RC oscillator, requiring no external components. The WDT oscillator still works a period of approximately 78ms even when the system enters the power down mode and the system clock is terminated. It nonetheless can be disabled by mask option for conserving power.

Watchdog timer - WDT

The clock source of WDT is implemented by a dedicated RC oscillator (WDT oscillator) or instruction clock (system clock divided by 4), de cided by mask option. The watchdog timer is designed to prevent a software malfunction or sequence jumping to an unknown location with

unpredictable results. It can be disabled by mask option. After it is disabled, all executions related to WDT are ignored.

WDT is first divided by 256 (8 stages) to get a nominal time-out period of 20 ms once an inter nal WDT oscillator (RC type of oscillator nor mally with a period of 78ms) is selected. This

time-out period may vary with temperature, VDD and process variations. By invoking the

OSC1

OSC2

R C O scillator

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HT827A0

WDT prescaler, a longer time-out period can be attained. Writing data to WS2, WS1 and WS0 (bits 2, 1 and 0 of WDTS) can derive different time-out periods. If WS2, WS1 and WS0 are all equal to 1, the division ratio is up to 1:128, and the maximum time-out period is 2.6 seconds.

WS2 WS1 WS0 Division Ratio

000 1:1

001 1:2

010 1:4

011 1:8

1 0 0 1:16

1 0 1 1:32

1 1 0 1:64

1 1 1 1:128

WDTS register

If the WDT oscillator is disabled, the WDT clock may still come from an instruction clock. It oper ates in the same manner except that WDT may stop counting and loses its protecting purpose in the HALT state. In this situation the logic can only be re-initialized by external logic. The high nibble and bit 3 of WDTS are reserved for user¢s defined flags. The programmer may use these flags to indicate some specified statuses.

The on-chip RC oscillator (WDT OSC) is strongly recommended if the device operates in a noisy environment, since the HALT function will stop the system clock.

Overflow of the WDT under a normal operation initializes a ²chip reset² and sets the status bit ²TO². It will initialize a ²warm reset², and only PC and SP are reset to zero in the HALT mode.

To clear the contents of WDT (including the WDT prescaler), three methods are adopted, namely, external reset (a low level to RES software instructions, and ²HALT² instruction. The software instructions include ²CLR WDT² and the other sets -²CLR WDT1² and ²CLR WDT2². Of these two types of instructions, by mask option only one can be active at a time ²CLR WDT times selection option².If²CLR WDT² is chosen (i.e., CLRWDT times equal one), any execution of the ²CLR WDT² instruc tion will clear WDT. In the case that ²CLR WDT1² and ²CLR WDT2² are selected (i.e., CLRWDT times equal two), these two instruc tions must be executed to clear WDT; otherwise WDT may reset the chip as a result of time-out.

Power down operation - HALT

The HALT mode is initialized by the ²HALT² instruction and results in the following:

The system oscillator is turned off but the WDT oscillator still keeps running (if the WDT oscillator is selected).

The contents of the on-chip RAM and regis ters remain unchanged.

The WDT and WDT prescaler are cleared and re-counted (if the clock of WDT is from the WDT oscillator).

All the I/O ports maintain their original statuses.

The PD flag is set and the TO flag cleared.

The system can quit the HALT mode by an external reset, interrupt, external falling edge signal on port A or WDT overflow. An external reset leads to device initialization and a WDT overflow performs a ²warm reset². The reason for chip re

S yste m C lock/4

WDT OSC

Mask

Option

S e le c tio n

W D T P rescale r

8-bit C ounter

7-bit C ounter

8 -to -1 M U X

W D T Tim e-out

WS0~WS2

Watchdog timer

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+ 34 hidden pages

Holtek Semiconductor Inc HT827A0 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

Applications

General Description

Block Diagram

Pin Assignment

Pad Assignment

Pad Coordinates

Pad Description

Absolute Maximum Ratings

D.C. Characteristics

A.C. Characteristics

Functional Description