Holtek Semiconductor Inc HT62l256 Datasheet
HT62L256
Preliminary
Features
·
Operation voltage: 2.7V~3.3V
·
Low power consumption:
-
Operating current: 20mA max.
-
Standby current: 2mA
·
High speed access time: 70ns
·
Input levels are LVTTL-compatible
General Description
The HT62L256 is a 262,144-bit static random access
memory organized into 32,768 words by 8 bits and oper
ating from a low power range of 2.7V to 3.3V supply volt
age. It is fabricated with high performance CMOS
process that provides both high speed and low power
feature with typical standby current of 2mA and maxi
mum access time of 70ns.
Block Diagram
A 1 4
A 0
A d d r e s s
B u f f e r s
X - D e c
Y - D e c
CMOS 32K´8 Low Power SRAM
·
Automatic power down when chip is deselected
·
Three state outputs
·
Fully static operation
·
Data retention supply voltage as low as 2.0V
·
Easy expansion with CS and OE options
·
28-pin SOP/TSOP package
The HT62L256 has an automatic power down feature,
reducing the power consumption significantly when chip
is deselected. The HT62L256 supports the JEDEC
standard 28-pin SOP and TSOP package.
-
M e m o r y C e l l A r r a y
( 3 2 K
8 B i t s
´
Pin Assignment
A 1 4
A 1 2
A 7
A 6
A 5
A 4
A 3
A 2
A 1
A 0
D 0
D 1
D 2
V S S
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
H T 6 2 L 2 5 6
2 8 S O P - A
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
V D D
W E
A 1 3
A 8
A 9
A 1 1
O E
A 1 0
C S
D 7
D 6
D 5
D 4
D 3
V D D
V S S
C S
W E
O E
A 1 1
A 1 3
W E
V D D
A 1 4
A 1 2
O E
A 9
A 8
A 7
A 6
A 5
A 4
A 3
R e a d / W r i t e
C o n t r o l L o g i c
1
1 4
S e n s e A m p l i f i e r
O u t p u t B u f f e r s
D 0 D 7
H T 6 2 L 2 5 6
2 8 T S O P - A
2 8
1 5
A 1 0
C S
D 7
D 6
D 5
D 4
D 3
V S S
D 2
D 1
D 0
A 0
A 1
A 2
Rev. 0.00 1 August 15, 2002
Preliminary
HT62L256
Pin Description
Pin Name I/O Description
A0~A14 I Address input pins
WE
OE
CS
I Write enable signal pin, active LOW
I Output enable signal pin, active LOW
I Chip select signal pin, active LOW
D0~D7 I/O Data input and output signal pins
VDD
VSS
Positive power supply
¾
Negative power supply, ground
¾
Absolute Maximum Rating
VDDto VSS ........................................... -0.5V to +3.6V
IN, IN/OUT Voltage to V
............. -0.5V to VDD+0.5V
SS
Operating Temperature, T
Storage Temperature (Plastic), Tstg ... -55°Cto125°C
Power Consumption, PT .......................................0.7W
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil
ity.
......................0°Cto70°C
OP
-
D.C. Characteristics
Ta=25°C, VDD=3.0V±10%, TOP=0°Cto70°C
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
I
I
V
V
V
I
LI
I
LO
V
V
DD
SB1
SB2
DD
IL
IH
OL
OH
Operating Voltage
Input Low Voltage
Input High Voltage
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
Operating Current
Standby Current
Power Down Supply Current
¾
¾¾
¾ 0.7´V
=0 to V
V
CS
V
V
V
CS
CS
CS
IN
OUT
DD
DD
DD
=VIHor OE=VIH,
=0 to V
DD
=Max, IOL=2mA
=Min, IOH=-1mA VDD-0.3 ¾¾
=VIH,I
=VIH,I
OUT
OUT
=0mA
=0mA
³ VDD- 0.2V, VIN³0V ¾
2.7 3.0 3.3 V
0 0.4 V
DD
¾¾
¾¾
¾¾
0.3 V
¾¾
¾¾
210
¾
1
1
20 mA
50
V
mA
mA
V
mA
mA
Rev. 0.00 2 August 15, 2002
Preliminary
HT62L256
A.C. Characteristics
Ta=25°C, VDD=3.0V±10%
Symbol Parameter Min. Typ. Max. Unit
Read cycle
t
RC
t
AA
t
ACS
t
AOE
t
CLZ*
t
OLZ
t
CHZ
t
OHZ
t
OH
Read Cycle Time 70
Address Access Time
Chip Selection Access Time
Output Enable to Valid Outputs
Chip Selection to Output in Low-Z 10
*
Output Enabled to Output in Low-Z 5
*
Chip Deselected to Output in High-Z
*
Output Disable to Output in High-Z
Output Hold from Address Change 10
¾¾
¾¾
¾¾
¾¾
¾¾
¾¾
¾¾
¾¾
¾¾
70 ns
70 ns
35 ns
25 ns
25 ns
Write cycle
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
Write Cycle Time 70
Chip Selection to End of Write 60
Address Setup Time 0
Address Valid to End of Write 60
Write Pulse Width 50
Write Recovery Time 0
¾¾
¾¾
¾¾
¾¾
¾¾
¾¾
Write to Output in High-Z ¾¾
Data Valid to End of Write 30
Data Hold from End of Write 0
Output Active from End of Write 5
¾¾
¾¾
¾¾
20 ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note: 1. A write cycle occurs during the overlap of a low CS and a low WE
2. OE may be both high and low in a write cycle
is specified from CS or WE, whichever occurs last
3. t
AS
is an overlap time of a low CS and a low WE
4. t
WP
5. tWR,tDWand tDHare specified from CS or WE, whichever occurs first
is specified by the time when DATA OUT is floating and not defined by the output level
6. t
WHZ
7. When the I/O pins are in data output mode, they should not be forced with inverse signals
Rev. 0.00 3 August 15, 2002
Preliminary
A.C. Test Conditions
Item Conditions
Input Pulse Level 0V to 3V
Input Rise and Fall Time 5ns
Input and Output Timing Reference Level 1.5V
Output Load See figures below
HT62L256
+ 1 . 5 V
1 . 8 k
W
I / O
9 9 0
W
* I n c l u d i n g s c o p e a n d j i g
1 0 0 p F
+ 1 . 5 V
1 . 8 k
W
I / O
9 9 0
W
* I n c l u d i n g s c o p e a n d j i g
5 p F
O u t p u t l o a d O u t p u t l o a d f o r
t C L Z , t O L Z , t C H Z , t W H Z a n d t O W
Functional Description
Operation truth table
CS
H X X Standby High-Z
L H H Output Disable High-Z
L L H Read Dout
L X L Write Din
Data retention characteristics
Symbol Parameter Conditions Min. Max. Unit
V
DR
I
CCDR
t
CDR
t
R
VDDfor Data Retention
Data Retention Current
Chip Disable Data Retention Time See retention timing 0
Operation Recovery Time See retention timing
OE WE Mode D0~D7
Ta =-40°Cto85°C
CS
³ VDD-0.2V
V
³ VDD-0.2V or VIN£0.2V
IN
³ VDD-0.2V
CS
V
³ VDD-0.2V or VIN£0.2V
IN
2.0 3.3 V
¾
2
¾
*
t
RC
¾
mA
ns
ns
Low VDDdata retention timing
V
D D
C S
3 . 0 V
3 . 0 V
V
2 . 0 V
D D
³
t
C D R
V
I H
C S
V
- 0 . 2 V
³
D D
t
R
V
I H
Rev. 0.00 4 August 15, 2002
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