Holtek Semiconductor Inc HT48RA0A Datasheet

HT48RA0A

Preliminary

8-Bit OTP IR Remote Controller

Features

Operating voltage: 2.2V~3.6V

·

Ten bidirectional I/O lines

·

Six schmitt trigger input lines

·

One carrier output (1/2 or 1/3 duty)

·

On-chip crystal and RC oscillator

·

Watchdog timer

·

1K´14 program EPROM

·

32´8 data RAM

·

Low voltage reset function

·

Halt function and wake-up feature reduce

·

power consumption

General Description

The HT48RA0A is an 8-bit high performance
RISC-like microcontroller specifically designed
for multiple I/O product applications. The de
vice is particularly suitable for use in products

62 powerful instructions

·

Up to 1ms instruction cycle with 4MHz

·

system clock
All instructions in 1 or 2 machine cycles

·

14-bit table read instructions

·

One-level subroutine nesting

·

Bit manipulation instructions

·

20-pin SOP package

·

24-pin SOP package

such as infrared remote controllers and various
subsystem controllers. A halt feature is in
cluded to reduce power consumption.

-

-

1 May 17, 2000

Block Diagram

Preliminary

HT48RA0A

Program
EPRO M

Instruction

R egister

Instruction

D ecoder

G enerator

OSC2

Tim ing

OSC1

RES

VDD
VSS

Program

C ounter

Pin Assignment

MP

ALU

S h ifte r

ACC

STACK

MUX

M
U
X

DATA

Memory

STATUS

SYS CLK/4

Frequency D ivider

WDT

PORT B

PB

PORT A

PA

Level or C arrier

C a r rie r C o n tro l

P C 0 C o n tro l

PB0~PB1

PB2~PB7

PA0~PA7

PC0/REM

PA1

PA0

PB1

PB0

PC0/REM

VDD

OSC2

OSC1

VSS

RES

20

1

19

2

18

3

17

4

16

5

15

6

14

7

13

8

12

9

11

10

H T 4 8 R A 0 A

20 S O P

PA2

PA3

PA4

PA5

PA6

PA7

PB2

PB3

PB4

PB5

PA1

PA0

PB1

PB0

PC0/REM

VDD

OSC2

OSC1

VSS

RES

NC

NC

1

2

3

4

5

6

7

8

9

10

11

12

PA2

24

PA3

23

PA4

22

PA5

21

PA6

20

PA7

19

PB2

18

PB3

17

PB4

16

PB5

15

PB6

14

PB7

13

H T 4 8 R A 0 A

24 S O P

2 May 17, 2000

Pin Description

Preliminary

HT48RA0A

Pin Name I/O

PB0, PB1 I/O

PC0/REM O

VDD

OSC2
OSC1

VSS

RES

PB2~PB7 I

PA0~PA7 I/O

¾¾

I

O

¾¾

I

Code

Option

Wake-up

or none

Level or

carrier

Crystal

or RC

¾

Wake-up

or none

¾

Description

2-bit bidirectional input/output lines with pull-high resistors.
Each bit can be determined as NMOS output or schmitt trigger in
put by software instructions. Each bit can also be configured as
wake-up input by code option.

Level or carrier output pin
PC0 can be set as CMOS output pin or carrier output pin by code
option.

Positive power supply

OSC1, OSC2 are connected to an RC network or a crystal (deter
mined by code option) for the internal system clock. In the case of
RC operation, OSC2 is the output terminal for 1/4 system clock
(NMOS open drain output).

Negative power supply, ground

Schmitt trigger reset input. Active low.

6-bit schmitt trigger input lines with pull-high resistors. Each bit
can be configured as a wake-up input by code option.

Bidirectional 8-bit input/output port with pull-high resistors.
Each bit can be determined as NMOS output or schmitt trigger in
put by software instructions.

-

-

-

Absolute Maximum Ratings

Supply Voltage..............................-0.3V to 5.5V

Input Voltage.................V

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maxi-

mum Ratings² may cause substantial damage to the device. Functional operation of this device
at other conditions beyond those listed in the specification is not implied and prolonged expo
sure to extreme conditions may affect device reliability.

-0.3V to VDD+0.3V

SS

Storage Temperature.................-50°Cto125°C

Operating Temperature ..............-40°Cto85°C

3 May 17, 2000

-

Preliminary

HT48RA0A

D.C. Characteristics

Symbol Parameter

V

I

I

V

V

V

V

I

I

R

R

V

DD

DD

STB

IL1

IH1

IL2

IH2

OL

OH

PH1

PH2

LVR

Operating Voltage

Operating Current 3V

Standby Current 3V

Input Low Voltage for I/O Ports 3V

Input High Voltage for I/O Ports 3V

Input Low Voltage (RES)3V

Input High Voltage (RES)3V

I/O Ports Sink Current 3V

PC0/REM Output Source Current 3V

Pull-high Resistance of PA
Port, PB0~PB1 and RES

Pull-high Resistance of PB2~PB7 3V

Low Voltage Reset 3V

Test Conditions

Conditions

V

DD

LVR disabled 2.2

¾

No load
f

=4MHz

SYS

No load
system HALT

¾

¾

¾

¾

V

=0.1V

OL

V

=0.9V

OH

3V

¾¾60¾ kW

¾¾60¾ kW

¾

Min. Typ. Max. Unit

¾

¾

0.7 1.5 mA

¾¾

DD

DD

0

0.8V

0

0.9V

1.5 2.5

-1 -1.5 ¾

DD

DD

¾

¾

¾

¾

2.1 2.3 2.5 V

3.6 V

1

0.2V

DD

V

DD

0.4V

DD

V

DD

¾

Ta=25°C

mA

V

V

V

V

mA

mA

A.C. Characteristics

Symbol Parameter

f

SYS

t

RES

t

SST

Note: t

System Clock 3V

External Reset Low
Pulse Width

System Start-up timer
Period

=1/f

SYS

SYS

Test Conditions

Min. Typ. Max. Unit

V

DD

¾¾

¾

Conditions

¾

Power-up or
wake-up from HALT

4 May 17, 2000

400

1

¾

¾

¾¾ms

1024

Ta=25°C

4000 kHz

t

¾

SYS

Preliminary

Functional Description

Execution flow

The HT48RA0A system clock can be derived
from a crystal/ceramic resonator oscillator. It is
internally divided into four non-overlapping
clocks. One instruction cycle consists of four
system clock cycles.

Instruction fetching and execution are
pipelined in such a way that a fetch takes one
instruction cycle while decoding and execution
takes the next instruction cycle. However, the
pipelining scheme causes each instruction to ef
fectively execute within one cycle. If an instruc
tion changes the program counter, two cycles
are required to complete the instruction.

Program counter - PC

The 10-bit program counter (PC) controls the
sequence in which the instructions stored in
program EPROM are executed and its contents
specify a maximum of 1024 addresses.

After accessing a program memory word to
fetch an instruction code, the contents of the
program counter are incremented by one. The
program counter then points to the memory
word containing the next instruction code.

When executing a jump instruction, conditional
skip execution, loading PCL register, subrou­tine call, initial reset or return from subroutine,
the PC manipulates the program transfer by

HT48RA0A

loading the address corresponding to each in
struction.

The conditional skip is activated by instruction.
Once the condition is met, the next instruction,
fetched during the current instruction execu
tion, is discarded and a dummy cycle replaces it
to get the proper instruction. Otherwise pro
ceed with the next instruction.

The lower byte of the program counter (PCL) is
a readable and writeable register (06H).
Moving data into the PCL performs a short

­jump. The destination will be within 256 loca

­tions.

When a control transfer takes place, an addi
tional dummy cycle is required.

Program memory - EPROM

The program memory is used to store the pro
gram instructions which are to be executed. It
also contains data and table and is organized
into 1024´14 bits, addressed by the program
counter and table pointer.

Certain locations in the program memory are
reserved for special usage:

·

Location 000H
This area is reserved for the initialization

program. After chip reset, the program al­ways begins execution at location 000H.

-

-

-

-

-

-

S ystem C lock

Instruction C ycle

PC

T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4

PC PC+1 PC+2

F e tc h IN S T (P C )

Execute IN S T (PC -1)

F e tc h IN S T (P C + 1 )

Execute IN S T (PC )

F e tc h IN S T (P C + 2 )

Execute IN S T (PC +1)

Execution flow

5 May 17, 2000

Preliminary

HT48RA0A

·

Table location

Any location in the EPROM space can be used
as look-up tables. The instructions TABRDC
[m] (the current page, 1 page=256 words) and
TABRDL [m] (the last page) transfer the con
tents of the lower-order byte to the specified
data memory, and the higher-order byte to
TBLH (08H). Only the destination of the
lower-order byte in the table is well-defined,
the other bits of the table word are trans
ferred to the lower portion of TBLH, the re
maining 2 bits are read as ²0². The Table
Higher-order byte register (TBLH) is read
only. The table pointer (TBLP) is a read/write
register (07H), where P indicates the table lo
cation. Before accessing the table, the loca
tion must be placed in TBLP. The TBLH is
read only and cannot be restored. All table re
lated instructions need 2 cycles to complete
the operation. These areas may function as
normal program memory depending upon the
requirements.

Stack register - STACK

This is a special part of the memory used to
save the contents of the program counter (PC)
only. The stack is organized into one level and is
neither part of the data nor part of the program
space, and is neither readable nor writeable.
The activated level is indexed by the stack

000H

D evice initialization program

-

n00H

nFFH

Look-up table (256 w ords)

-

-

3FFH

-

-

­pointer (SP) and is neither readable nor

Look-up table (256 w ords)

14 bits

N ote: n ranges from 0 to 3

Program memory

writeable. At a subroutine call the contents of
the program counter are pushed onto the stack.
At the end of a subroutine signaled by a return
instruction (RET), the program counter is re
stored to its previous value from the stack. Af
ter a chip reset, the SP will point to the top of the
stack.

If the stack is full and a ²CALL² is subsequently
executed, stack overflow occurs and the first en­try will be lost (only the most recent return ad­dress is stored).

Program
ERO M

-

-

Mode

Program Counter

*9 *8 *7 *6 *5 *4 *3 *2 *1 *0

Initial reset 0000000000

Skip PC+2

Loading PCL *9 *8 @7 @6 @5 @4 @3 @2 @1 @0

Jump, call branch #9 #8 #7 #6 #5 #4 #3 #2 #1 #0

Return from subroutine S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

Program counter

Note: *9~*0: Program counter bits S9~S0: Stack register bits

#9~#0: Instruction code bits @7~@0: PCL bits

6 May 17, 2000

Preliminary

HT48RA0A

Data memory - RAM

The data memory is designed with 42´8 bits.
The data memory is divided into two functional
groups: special function registers and general
purpose data memory (32´8). Most of them are
read/write, but some are read only.

The special function registers include the indirect
addressing register (00H), the memory pointer
register (MP;01H), the accumulator (ACC;05H)
the program counter lower-order byte register
(PCL;06H), the table pointer (TBLP;07H), the ta
ble higher-order byte register (TBLH;08H), the
status register (STATUS;0AH) and the I/O regis
ters (PA;12H, PB;14H, PC;16H). The remaining
space before the 20H is reserved for future ex
panded usage and reading these locations will re
turn the result 00H. The general purpose data
memory, addressed from 20H to 3FH, is used for
data and control information under instruction
command.

All data memory areas can handle arithmetic,
logic, increment, decrement and rotate opera
tions directly. Except for some dedicated bits,
each bit in the data memory can be set and re
set by the SET [m].i and CLR [m].i instructions,
respectively. They are also indirectly accessible
through memory pointer register (MP;01H).

Indirect addressing register

Location 00H is an indirect addressing register
that is not physically implemented. Any
read/write operation of [00H] accesses data
memory pointed to by MP (01H). Reading loca­tion 00H itself indirectly will return the result

-

-

-

-

-

-

Indirect Addressing R egister

00H

01H

02H

03H

04H

05H

06H

07H
08H

09H

0AH

0BH

0C H

0D H

0EH

0FH

10H

11H

12H

13H

14H

15H

16H

17H

18H

19H

1AH

1BH

1C H

1D H
1EH
1FH

20H

G eneral P urpose

DATA M EMO RY

3FH

MP

ACC

PCL

TBLP

TBLH

STATUS

Special P urpose

DATA M EMO RY

PA

PB

PC

: U n u s e d

R ead as "00"

(32 Bytes)

RAM mapping

00H. Writing indirectly results in no operation.

Table Location

Instruction(s)

*9 *8 *7 *6 *5 *4 *3 *2 *1 *0

TABRDC [m] P9 P8 @7 @6 @5 @4 @3 @2 @1 @0

TABRDL [m] 1 1 @7 @6 @5 @4 @3 @2 @1 @0

Table location

Note: *9~*0: Table location bits @7~@0: Table pointer bits

P9~P8: Current program counter bits

7 May 17, 2000

Preliminary

HT48RA0A

The memory pointer register MP (01H) is a
6-bit register. The bit 7~6 of MP is undefined
and reading will return the result ²1². Any writ
ing operation to MP will only transfer the lower
6-bit data to MP.

Accumulator

The accumulator closely relates to ALU opera
tions. It is also mapped to location 05H of the
data memory and is capable of carrying out im
mediate data operations. Data movement be
tween two data memory locations has to pass
through the accumulator.

Arithmetic and logic unit - ALU

This circuit performs 8-bit arithmetic and logic
operation. The ALU provides the following
functions.

·

Arithmetic operations (ADD, ADC, SUB,
SBC, DAA)

·

Logic operations (AND, OR, XOR, CPL)

·

Rotation (RL, RR, RLC, RRC)

·

Increment and Decrement (INC, DEC)

Labels Bits Function

C is set if the operation results in a carry during an addition operation or if a bor-

C0

AC 1

Z2

OV 3

PD 4

TO 5

¾

¾

row does not take place during a subtraction operation; otherwise C is cleared. C
is also affected by a rotate through carry instruction.

AC is set if the operation results in a carry out of the low nibbles in addition or no
borrow from the high nibble into the low nibble in subtraction; otherwise AC is
cleared.

Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is
cleared.

OV is set if the operation results in a carry into the highest-order bit but not a
carry out of the highest-order bit, or vice versa; otherwise OV is cleared.

PD is cleared when either a system power-up or executing the CLR WDT in
struction. PD is set by executing the HALT instruction.

TO is cleared by a system power-up or executing the CLR WDT or HALT instruc
tion. TO is set by a WDT time-out.

6

Undefined, read as ²0²

7

Undefined, read as ²0²

·

Branch decision (SZ, SNZ, SIZ, SDZ ....)

The ALU not only saves the results of a data op

­eration but also changes the contents of the sta

tus register.

Status register - STATUS

This 8-bit status register (0AH) contains the zero

­flag (Z), carry flag (C), auxiliary carry flag (AC),

overflow flag (OV), power down flag (PD) and

­watchdog time-out flag (TO). It also records the

­status information and controls the operation se

quence.

With the exception of the TO and PD flags, bits
in the status register can be altered by instruc
tions like most other register. Any data written
into the status register will not change the TO
or PD flags. In addition it should be noted that
operations related to the status register may
give different results from those intended. The
TO and PD flags can only be changed by the
Watchdog Timer overflow, chip power-up, clear
ing the Watchdog Timer and executing the
HALT instruction.

-

-

-

-

-

-

-

Status register

8 May 17, 2000

Preliminary

HT48RA0A

The Z, OV, AC and C flags generally reflect the
status of the latest operations.

In addition, on executing the subroutine call,
the status register will not be automatically
pushed onto the stack. If the contents of the sta
tus are important and if the subroutine can cor
rupt the status register, precautions must be
taken to save it properly.

Oscillator configuration

There are two oscillator circuits in the
HT48RA0A.

/4

OSC1

OSC2

R C O scillator

OSC1

OSC2

C rystal O scilla tor

f

SYS

(N M O S open
drain output)

System oscillator

Both are designed for system clocks; the RC os
cillator and the Crystal oscillator, which are de
termined by code options. No matter what
oscillator type is selected, the signal provides
the system clock. The HALT mode stops the
system oscillator and ignores the external sig­nal to conserve power.

If an RC oscillator is used, an external resistor
between OSC1 and VSS in needed and the re­sistance must range from 51kW to 1MW. The

system clock, divided by 4, is available on
OSC2, which can be used to synchronize exter
nal logic. The RC oscillator provides the most
cost effective solution. However, the frequency
of the oscillation may vary with V

­ture and the chip itself due to process varia

­tions. It is, therefore, not suitable for timing

sensitive operations where accurate oscillator
frequency is desired.

If the Crystal oscillator is used, a crystal across
OSC1 and OSC2 is needed to provide the feed
back and phase shift for the oscillator. No other
external components are needed. Instead of a
crystal, the resonator can also be connected be
tween OSC1 and OSC2 to get a frequency refer
ence, but two external capacitors in OSC1 and
OSC2 are required.

Watchdog timer - WDT

The clock source of the WDT is implemented by
instruction clock (system clock divided by 4).
The clock source is processed by a frequency di
vider and a prescaller to yield various time out
periods.

-

­WDT time out period =

Clock Source

n

2

Where n= 8~11 selected by code option.

This timer is designed to prevent a software
malfunction or sequence jumping to an un­known location with unpredictable results. The
Watchdog Timer can be disabled by code option.
If the Watchdog Timer is disabled, all the exe-

, tempera

DD

-

-

-

-

-

-

-

C lo ck S o urce

(S ystem C lock/4 )

Frequency D ivider

3-bit Counter

Clear W DT

P resca lle r

(8 -b it)

Code Option

Select

C ode

Option

Watchdog timer

9 May 17, 2000

WDT
Tim e-out

C lo ck S o urce

n

2

(n=8~11)

Preliminary

HT48RA0A

cutions related to the WDT result in no opera
tion and the WDT will lose its protection
purpose. In this situation the logic can only be
restarted by an external logic.

A WDT overflow under normal operation will ini
tialize ²chip reset² and set the status bit ²TO².To
clear the contents of the WDT prescaler, three
methods are adopted; external reset (a low level
to RES

), software instructions, or a HALT in
struction. There are two types of software in
structions. One type is the single instruction
²CLR WDT², the other type comprises two in
structions, ²CLR WDT1² and ²CLR WDT2².Of
these two types of instructions, only one can be
active depending on the code option -²CLR WDT
times selection option².Ifthe²CLR WDT² is se
lected (i.e.. CLRWDT times equal one), any execu
tion of the CLR WDT instruction will clear the
WDT. In case ²CLR WDT1² and ²CLR WDT2² are
chosen (i.e.. CLRWDT times equal two), these two
instructions must be executed to clear the WDT;
otherwise, the WDT may reset the chip due to a
time-out.

Power down operation - HALT

The HALT mode is initialized by the HALT in­struction and results in the following...

·

The system oscillator turns off and the WDT
stops.

·

The contents of the on-chip RAM and regis­ters remain unchanged.

·

WDT prescaler are cleared.

·

All I/O ports maintain their original status.

·

The PD flag is set and the TO flag is cleared.

The system can quit the HALT mode by means
of an external reset or an external falling edge
signal on port B. An external reset causes a de
vice initialization. Examining the TO and PD
flags, the reason for chip reset can be deter
mined. The PD flag is cleared when the system
powers up or execute the CLR WDT instruction
and is set when the HALT instruction is exe

cuted. The TO flag is set if the WDT time-out oc

­curs, and causes a wake-up that only resets the
PC (Program Counter) and SP, the others keep
their original status.

The port B wake-up can be considered as a con

­tinuation of normal execution. Each bit in port
B can be independently selected to wake up the
device by the code option. Awakening from an
I/O port stimulus, the program will resume exe

­cution of the next instruction.

-

Once a wake-up event(s) occurs, it takes 1024

­t

(system clock period) to resume normal op

SYS

eration. In other words, a dummy cycle period
will be inserted after the wake-up.

To minimize power consumption, all I/O pins

­should be carefully managed before entering

­the HALT status.

Reset

There are three waysin which a reset canoccur:

·

RES reset during normal operation

·

RES reset during HALT

·

WDT time-out reset during normal
operation

Some registers remain unchanged during reset
conditions. Most registers are reset to the ²ini­tial condition² when the reset conditions are
met. By examining the PD and TO flags, the
program can distinguish between different
²chip resets².

TO PD RESET Conditions

0 0 RES

uu

-

-

-

0 1 RES

1u

Note: ²u² means ²unchanged².

reset during power-up

reset during normal

RES
operation

wake-up HALT

WDT time-out during normal
operation

-

-

-

-

10 May 17, 2000

Preliminary

t

HT48RA0A

When a system power up occurs, an SST delay

RES

is added during the reset period. But when the
reset comes from the RES

pin, the SST delay is
disabled. Any wake-up from HALT will enable
the SST delay.

VDD

HALT

RES

OSC1

LVR R eset

Reset circuit

WDT

WDT

Tim e-out

Reset

SST

10-stage

R ipple C ounter

Rese

RES

SST Tim e-out

C hip R eset

t

SST

Reset timing chart

The functional unit chip reset status is shown be
low.

PC 000H

Power-on Detection

Reset configuration

To guarantee that the system oscillator has
started and stabilized, the SST (System
Start-up Timer) provides an extra-delay of 1024

WDT Prescaler Clear

Input/output ports Input mode

SP

Points to the top of the
stack

Carrier Output Low level

system clock pulses when the system powers up
or when the system awakes from a HALT state.

The chip reset status of the registers is summarized in the following table:

Reset

RES

(Normal

Operation)

RES

(HALT)

Register

PC
(Program Counter)

Reset

(Power On)

WDT Time-out

(Normal

Operation)

000H 000H 000H 000H

MP -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu

ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu

TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu

TBLH --xx xxxx --uu uuuu --uu uuuu --uu uuuu

STATUS --00 xxxx --1u uuuu --uu uuuu --01 uuuu

PA 1111 1111 1111 1111 1111 1111 1111 1111

PB 1111 1111 1111 1111 1111 1111 1111 1111

PC ---- ---1 ---- ---1 ---- ---1 ---- ---1

-

Reset

Note:

²u² means ²unchanged²
²x² means ²unknown²

11 May 17, 2000

Preliminary

HT48RA0A

Low voltage reset - LVR

The HT48RA0A provides low voltage reset cir
cuit in order to monitor the supply voltage of
the device. If the supply voltage of the device is
within the range 0.9V~2.3V, such as changing a
battery, the LVR will automatically reset the
device internally.

The LVR includes the following specifications:

·

The low voltage (0.9V~2.3V) has to remain in
their original state to exceed 1 ms. If the low
voltage state does not exceed 1 ms, the LVR
will ignore it and do not perform a reset func
tion.

·

The LVR uses the ²OR² function with the exter
nal RES

·

During HALT mode, if the LVR occurs, the

signal to perform chip reset.

device will wake-up and the PD flag will be

DD

.

)is

set as ²1², the same as the external RES

Because the operating voltage (V

2.3V~3.6V and the LVR operating voltage
(V

) is 0.9V~2.3V, therefore one margin volt

LVR

age about 0.1V is needed for proper chip opera
tion. The relationship between V

DD

and V

LVR

shown below.

V

DD

3.6V

V

DDVOPR

3.6V

2.3V

3.6V

2.2V

V

LVR

0.9V

-

-

Note: V

-

is the voltage range for proper chip

OPR

operation at 4MHz system clock.

Carrier

The HT48RA0A provides a carrier output
which shares the pin with PC0. It can be se
lected to be a carrier output (REM) or level out
put pin (PC0) by code option. If the carrier
output option is selected, setting PC0=²0² to en

-

able carrier output and setting PC0=²1² to dis

­able it at low level output.

is

-

-

-

-

V

LVR

0.9V

0V

R eset S ignal

Reset

N orm al O peration R eset

*1 *2

LVR D etect Voltage

V

= 0.9~2.3V

LVR

Low voltage reset

Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of

1024 system clock pulses before entering the normal operation.

*2: Since the low voltage has to maintain in its original state and exceed 1ms, therefore 1ms

delay enter the reset mode.

12 May 17, 2000