Holtek Semiconductor Inc HT48CA3 Datasheet

Features

Operating voltage: 2.2V~3.6V

23 bidirectional I/O lines (max.)

1 interrupt input shared with an I/O line

8-bit programmable timer/event counter with overflow interrupt and 8-stage prescaler (TMR0)

16-bit programmable timer/event counter and overflow interrupts (TMR1)

On-chip crystal and RC oscillator

Watchdog Timer

24K´16 program memory ROM (8K´16 bits´3 banks)

224´8 data memory RAM

General Description

The HT48CA3 is an 8-bit high performance, RISC archi tecture microcontroller device specifically designed for multiple I/O control product applications. The data ROM can be used to store remote control codes. This device is the mask version which is fully pin and functionally compatible with the OTP version HT48RA3 device.

HT48CA3

8-Bit Remote Type MCU

PFD supported

HALT function and wake-up feature reduce power consumption

8-level subroutine nesting

Up to 1ms instruction cycle with 4MHz system clock at V

=3V

Bit manipulation instruction

16-bit table read instruction

63 powerful instructions

All instructions in one or two machine cycles

28-pin SKDIP/SOP package

The advantages of low power consumption, I/O flexibil

ity, timer functions, oscillator options, watchdog timer, programmable frequency divider, HALT and wake-up functions, as well as low cost, enhance the versatility of this device to suit a wide range of application possibili ties such as industrial control, consumer products, subsystem controllers, and particularly suitable for use in products such as universal remote controller (URC).

Block Diagram

P r o g r a m

I n s t r u c t i o n

R e g i s t e r

I n s t r u c t i o n

D e c o d e r

T i m i n g

G e n e r a t o r

O S C 2

R O M

O S C 1

R E S V D D V S S

P r o g r a m

C o u n t e r

B P

M P

A L U

S h i f t e r

A C C

M U X

S T A C K

M U X

D A T A

M e m o r y

S T A T U S

I N T / P F 0

I n t e r r u p t

C i r c u i t

I N T C

T M R 1 C

T M R 1

T M R 0

T M R 0 C

W D T S

W D T P r e s c a l e r

P A C

P O R T A

P A

P F D

P B C

P O R T B

P B

P C C

P O R T C

P C

P F C

P O R T F

P F

/ 4

M U X

E N / D I S

W D T

S Y S

T M R 1

P r e s c a l e r

T M R 0

P A 0 ~ P A 7

P B 0 ~ P B 7

P C 0 ~ P C 5

P F 0

M U X

S Y S

W D T O S C

S Y S

/ 4

M U X

Rev. 1.40 1 July 16, 2003

Pin Assignment

HT48CA3

Pin Description

Pin Name I/O

RES

PA0~PA7 I/O

PB0/PFD PB1~PB7

VSS

PC0/TMR0 PC1~PC4 PC5/TMR1

PF0/INT

VDD

OSC1 OSC2

P B 0 / P F D

P F 0 / I N T

P C 0 / T M R 0

ROM Code

Option

Wake-up*

Pull-high***

I/O

Pull-high**

PB0 or PFD

¾¾

I/O Pull-high*

¾¾

Crystal

or RC

P B 5

P B 4

P A 3

P A 2

P A 1

P A 0

P B 3

P B 2

P B 1

V S S

P C 1

1 0

1 1

1 2

1 3

1 4

2 8

2 7

2 6

2 5

2 4

2 3

2 2

2 1

2 0

1 9

1 8

1 7

1 6

1 5

P B 6

P B 7

P A 4

P A 5

P A 6

P A 7

O S C 2

O S C 1

V D D

R E S

P C 5 / T M R 1

P C 4

P C 3

P C 2

H T 4 8 C A 3

2 8 S K D I P - A / S O P - A

Description

Schmitt trigger reset input, active low.

Bidirectional 8-bit input/output port. Each bit can be configured as a wake-up input by a mask option. Software instructions determine the CMOS output or Schmitt trigger input with/without pull-high resistor. The pull-high resistor of each input/output line is also optional.

Bidirectional 8-bit input/output port. Software instructions determine the CMOS output or Schmitt trigger input with/without pull-high resistor. The pull-high resistor of each input/output line is also optional. The output mode of PB0 can be used as an internal PFD signal output and it can be used as a various frequency carrier signal.

Negative power supply, ground

Bidirectional 6-bit input/output port. Software instructions determine the CMOS output or Schmitt trigger input with/without pull-high resis tor. Thepull-high resistor of each input/output line is also optional. PC0 and PC5 are pin shared with TMR0 and TMR1 function pins.

Bidirectional 1-bit input/output port. Software instructions determine the CMOS output or Schmitt trigger input with/without pull-high resis tor. The pull-high resistor of this input/output line is also optional. PF0 is pin shared with the INT

Positive power supply

OSC1, OSC2 are connected to an RC network or Crystal (determined by hardwareoption) for the internal system clock. In the case of RC op eration, OSC2 is the output terminal for 1/4 system clock.

function pin.

Note: * Bit option

** Nibble option *** Byte option

Rev. 1.40 2 July 16, 2003

HT48CA3

Absolute Maximum Ratings

Supply Voltage...........................VSS-0.3V to VSS+4.0V

Input Voltage..............................V

-0.3V to VDD+0.3V

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may

cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil ity.

Storage Temperature ............................-50°Cto125°C

Operating Temperature...........................-40°Cto85°C

D.C. Characteristics

Symbol Parameter

STB1

STB2

OH1

OH2

Operating Voltage

Operating Current 3V

Standby Current (WDT Enabled) 3V No load, system HALT

Standby Current (WDT Disabled) 3V No load, system HALT

Input Low Voltage for I/O Ports

IL1

Input High Voltage for I/O Ports

IH1

Input Low Voltage (RES Ports)

IL2

Input High Voltage (RES Ports)

IH2

I/O Port Sink Current 3V

I/O Port Source Current 3V

Pull-high Resistance 3V

A.C. Characteristics

Symbol Parameter

SYS

TIMER

WDTOSC

WDT1

WDT2

RES

SST

INT

ACC

System Clock 3V

Timer I/P Frequency (TMR0/TMR1) 3V 50% duty 0

Watchdog Oscillator 3V

Watchdog Time-out Period (WDT OSC)

Watchdog Time-out Period (f

External Reset Low Pulse Width

System Start-up Timer Period

Interrupt Pulse Width

Data ROM Access Time

SYS

Test Conditions

Conditions

¾¾

No load, f

SYS

=4MHz

¾¾

=0.1V

=0.9V

=0.8V

Test Conditions

Conditions

Min. Typ. Max. Unit

2.2

0.8V

0.9V

35mA

510

0.1 1

510

-2 -5 ¾

-4 -8 ¾

40 60 80

Min. Typ. Max. Unit

400

45 90 180

3V Without WDT prescaler 11.5 23 46 ms

/4)

3V Without WDT prescaler

¾¾

Power-up, reset or

wake-up from HALT

¾¾

1024

¾¾ms

1024

¾¾ms

Ta=25°C

3.6 V

0.2V

0.4V

Ta=25°C

4000 kHz

SYS

Note: t

SYS

=1/(f

SYS

)

Rev. 1.40 3 July 16, 2003

Functional Description

Execution Flow

The system clock for the MCU is derived from either a crystal or an RC oscillator. The system clock is internally divided into four non-overlapping clocks. One instruc tion cycle consists of four system clock cycles.

Instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while de coding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruc tion to effectively execute in a cycle. If an instruction changes theprogram counter, two cycles are required to complete the instruction.

Program Counter - PC

The program counter (PC) controls the sequence in which the instructions stored in the program ROM are executed and its contents specify a full range of pro gram memory.

After accessing a program memory word to fetch an in struction code, the contents of the program counter are

S y s t e m C l o c k

T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4

incremented byone. The program counter then points to the memory word containing the next instruction code.

When executing a jump instruction, conditional skip ex ecution, loading register, subroutine call or return from

subroutine, initial reset, internal interrupt, external inter rupt or return from interrupts, the PC manipulates the program transfer by loading the address corresponding

to each instruction.

The conditional skip is activated by instructions. Once

the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise proceed to the next instruction.

The lower byte of the program counter (PCL) is a read able and writeable register (06H). Moving data into the PCL performs a short jump. The destination will be

within the current program ROM page.

When a control transfer takes place, an additional

dummy cycle is required.

HT48CA3

O S C 2 ( R C o n l y )

P C

P C P C + 1 P C + 2

F e t c h I N S T ( P C )

E x e c u t e I N S T ( P C - 1 )

F e t c h I N S T ( P C + 1 )

E x e c u t e I N S T ( P C )

F e t c h I N S T ( P C + 2 )

E x e c u t e I N S T ( P C + 1 )

Execution flow

Mode

*14~*8 *7 *6 *5 *4 *3 *2 *1 *0

Program Counter

Initial Reset 0000000 00000000

External Interrupt 0000000 00000100

Timer/Event Counter 0 Overflow 0000000 00001000

Timer/Event Counter 1 Overflow 0000000 00001100

Skip *14~*13, (*12~*0+2): (within current bank)

Loading PCL *14~*8 @7 @6 @5 @4 @3 @2 @1 @0

Jump, Call Branch BP(1~0), #12~#8 #7 #6 #5 #4 #3 #2 #1 #0

Return (RET, RETI) S14~S8 S7 S6 S5 S4 S3 S2 S1 S0

Program Counter

Note: *14~*0: Program counter bits S14~S0: Stack register bits

#14~#0: Instruction code bits @7~@0: PCL bits 1 bank: 8K words

Rev. 1.40 4 July 16, 2003

HT48CA3

Program Memory - ROM

The program memory is used to store the program in structions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 8192´16 bits´3 banks, addressed by the program coun ter and table pointer.

Certain locations in the program memory are reserved for special usage:

Location 000H This area is reserved for program initialization. After chip reset, the program always begins execution at lo cation 000H.

Location 004H This area is reserved for the external interrupt service program. If the INT

input pin is activated, the interrupt is enabled and the stack is not full, the program begins execution at location 004H.

Location 008H This areais reserved for the Timer/Event Counter 0 in terrupt service program. If a timer interrupt results from a Timer/Event Counter 0 overflow, and if the in terrupt is enabled and the stack is not full, the program begins execution at location 008H.

Location 00CH This location is reserved for the Timer/Event Counter 1 interrupt service program. If a timer interrupt results from a Timer/Event Counter 1 overflow, and the interrupt is enabled and the stack is not full, the program begins execution at location 00CH.

Table location Any location in the program memory can be used as look-up tables. The instructions ²TABRDC [m]² (page specified by TBHP) and ²TABRDL [m]² (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH(08H). The higher-order byte table pointer TBHP(1FH) and lower-order byte table pointer TBLP (07H) are read/write registers, which indicate the table locations. Before accessing the table, the location has to be placed in TBHP and TBLP. The TBLH is read only and cannot be restored. If the main routine and the ISR (interrupt service routine) both employ the ta ble read instruction, the contents of TBLH in the main routine are likely to be changed by the table read in struction used in the ISR. Errors are thus brought about. Given this, using the table read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read instruction has to be applied in both main routine and the ISR, the in

0 0 0 H

0 0 4 H

0 0 8 H

0 0 C H

n 0 0 H

n F F H

D e v i c e I n i t i a l i z a t i o n P r o g r a m

E x t e r n a l I n t e r r u p t S u b r o u t i n e

T i m e r / E v e n t C o u n t e r 0

I n t e r r u p t S u b r o u t i n e

T i m e r / E v e n t C o u n t e r 1

I n t e r r u p t S u b r o u t i n e

L o o k - u p T a b l e ( 2 5 6 w o r d s )

5 F F F H

terrupt(s) is supposed to be disabled prior to the table read instruction. It (They) will not be enabled until the

L o o k - u p T a b l e ( 2 5 6 w o r d s )

1 6 b i t s

N o t e : n r a n g e s f r o m 0 t o 5 F

Program memory

TBLH in the main routine has been backup. All table related instructions require 2 cycles to complete the operation.

Stack Register - STACK

This is a special part of the memory which is used to save the contents of the program counter (PC) only. The stack is organized into 8 levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the stack pointer (SP) and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the pro gram counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack.

If the stack is full and a non-masked interrupt takes

place, the interrupt request flag will be recorded but the

acknowledge signal will be inhibited. When the stack pointer is decremented (by RET or RETI), the interrupt will be serviced. This feature prevents stack overflow al lowing the programmer to use the structure more easily. In a similar case, if the stack is full and a ²CALL² is sub

P r o g r a m M e m o r y

Instruction

*14~*8 *7 *6 *5 *4 *3 *2 *1 *0

Table Location

TABRDC [m] TBHP @7 @6 @5 @4 @3 @2 @1 @0

TABRDL [m] 1011111 @7 @6 @5 @4 @3 @2 @1 @0

Table location

Note: *14~*0: Table location bits @7~@0: Table pointer bits

Rev. 1.40 5 July 16, 2003

sequently executed, stack overflow occurs and the first entry will be lost (only the most recent 8 return ad dresses are stored).

Data Memory - RAM

The data memory is designed with 250´8 bits. The data memory is divided into two functional groups: spe cial function registers and general purpose data mem ory (224´8). Most are read/write, but some are read only.

The special function registers include the indirect ad dressing registers (R0;00H, R1;02H) bank pointer (BP;04H), Timer/Event Counter 0 (TMR0;0DH), Timer/Event Counter 0 control register (TMR0C;0EH), Timer/Event Counter 1 higher order byte register (TMR1H;0FH), Timer/Event Counter 1 lower order byte register (TMR1L;10H), Timer/Event Counter 1 control register (TMR1C;11H), program counter lower-order byte register ( (MP0;01H, MP1;03H), accumulator (

;06H), memory pointer registers

PCL

;05H), table

ACC pointer (TBLP;07H, TBHP;1FH), table higher-order byte register (TBLH;08H), status register (STATUS;0AH), interrupt control register (INTC;0BH), Watchdog Timer option setting register (WDTS;09H), I/O registers (PA;12H, PB;14H, PC;16H, PF;1CH, and I/O control registers (PAC;13H, PBC;15H, PCC;17H, PFC;1DH). The remaining space before the 20H is reserved for future expanded usage and reading these locations will get ²00H². The general purpose data memory, addressed from 20H to FFH, is used for data and control information under instruction commands.

All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by ²SET [m].i² and ²CLR [m].i². They are also indirectly accessible through memory pointer registers (MP0 or MP1).

HT48CA3

I n d i r e c t A d d r e s s i n g R e g i s t e r 0

0 0 H

0 1 H

I n d i r e c t A d d r e s s i n g R e g i s t e r 1

0 2 H

0 3 H

0 4 H

0 5 H

0 6 H

0 7 H

0 8 H

0 9 H

0 A H

0 B H

0 C H

0 D H

0 E H

0 F H

1 0 H

1 1 H

1 2 H

1 3 H

1 4 H

1 5 H

1 6 H

1 7 H

1 8 H

1 9 H

1 A H

1 B H

1 C H

1 D H

1 E H

1 F H

2 0 H

F F H

M P 0

M P 1

B P

A C C

P C L

T B L P

T B L H

W D T S

S T A T U S

I N T C

T M R 0

T M R 0 C

T M R 1 H

T M R 1 L

T M R 1 C

P A

P A C

P B

P B C

P C

P C C

P F

P F C

T B H P

G e n e r a l P u r p o s e D A T A M E M O R Y

( 2 2 4 B y t e s )

S p e c i a l P u r p o s e D A T A M E M O R Y

: U n u s e d

R e a d a s " 0 0 "

Indirect Addressing Register

RAM mapping

Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write op eration of [00H] ([02H]) will access data memory pointed to by MP0 (MP1). Reading location 00H (02H) itself indi rectly will return the result 00H. Writing indirectly results in no operation.

The memory pointer registers (MP0 and MP1) are 8-bit registers.

Accumulator

The accumulator is closely related to ALU operations. It is also mapped to location of the data memory and can carry out immediate data operations. The data move ment between two data memory locations must pass

Arithmetic and Logic Unit - ALU

This circuit performs 8-bit arithmetic and logic opera

tions. The ALU provides the following functions:

Arithmetic operations (ADD, ADC, SUB, SBC, DAA)

Logic operations (AND, OR, XOR, CPL)

Increment and decrement (INC, DEC)

Rotation (RL, RR, RLC, RRC)

Increment and Decrement (INC, DEC)

Branch decision (SZ, SNZ, SIZ, SDZ ....)

The ALU not only saves the results of a data operation

but also changes the status register.

through the accumulator.

Rev. 1.40 6 July 16, 2003

HT48CA3

Status Register - STATUS

This 8-bit register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PD), and watchdog time-out flag (TO). It also records the status information and controls the operation sequence.

With the exception of the TO and PD flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PD flag. In addition operations related to the status register may give dif ferent results from those intended. The TO flag can be affected only by system power-up, a WDT time-out or executing the ²CLR WDT² or ²HALT² in struction. The PD flag can be affected only by execut ing the ²HALT² or ²CLR WDT² instruction or during a system power-up.

The Z, OV, AC and C flags generally reflect the status of the latest operations.

In addition, on entering the interrupt sequence or exe cuting the subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status are important and if the subroutine can cor rupt the status register, precautions must be taken to save it properly.

Interrupt

The device provides an external interrupt and internal timer/event counter interrupts. The Interrupt Control Register (INTC;0BH) contains the interrupt control bits to setthe enable/disable and the interrupt request flags.

Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may occur during this interval but only the interrupt request flag is recorded. If a certain inter rupt requires servicing within the service routine, the

EMI bit and the corresponding bit of the INTC may be set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related in terrupt is enabled, until the SP is decremented. If immedi ate service is desired, the stack must be prevented from becoming full.

All these kinds of interrupts have a wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at specified location in the pro gram memory. Only the program counter is pushed onto

the stack. If the contents of the register or status register

(STATUS) are altered by the interrupt service program which corrupts the desired control sequence, the con

tents should be saved in advance.

External interrupts are triggered by a high to low transi tion ofthe INT bit 4 of INTC) will be set. When the interrupt is enabled, the stack is not full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt

request flag (EIF) and EMI bits will be cleared to disable

other interrupts.

The internal Timer/Event Counter 0 interrupt is initial

ized by setting the Timer/Event Counter 0 interrupt re

quest flag (T0F;bit 5 of INTC), caused by a timer 0 overflow. When the interrupt is enabled, the stack is not full and the T0F bit is set, a subroutine call to location 08H will occur. The related interrupt request flag (T0F) will be reset and the EMI bit cleared to disable further interrupts.

The internal Timer/Event Counter 1 interrupt is initialized by setting the Timer/Event Counter 1 interrupt request flag (T1F;bit 6 of INTC), caused by a timer 1 overflow. When the interrupt is enabled, the stack is not full and the T1F is set, a subroutine call to location 0CH will occur. The related interrupt request flag (T1F) will be

reset and the EMI bit cleared to disable further inter

rupts.

and therelated interrupt request flag (EIF;

Labels Bits Function

AC 1

Z 2 Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.

OV 3

PD 4

TO 5

Rev. 1.40 7 July 16, 2003

C is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction.

AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared.

OV is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared.

PD is cleared by system power-up or executing the ²CLR WDT² instruction. PD is set by exe cuting the ²HALT² instruction.

TO is cleared by system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is set by a WDT time-out.

6~7

Undefined, read as ²0²

Status register

HT48CA3

During the execution of an interrupt subroutine, other in terrupt acknowledge signals are held until the ²RETI² in struction is executed or the EMI bit and the related interrupt control bit are set to 1 (if the stack is not full). To return from the interrupt subroutine, ²RET² or ²RETI² may be invoked. RETI will set the EMI bit to enable an in terrupt service, but RET will not.

Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding inter rupts are enabled. In the case of simultaneous requests the following table shows the priority that is applied. These can be masked by resetting the EMI bit.

Interrupt Source Priority Vector

External Interrupt 1 04H

Timer/Event Counter 0 Overflow 2 08H

Timer/Event Counter 1 Overflow 3 0CH

The Timer/Event Counter 0/1 interrupt request flag (T0F/T1F), external interrupt request flag (EIF), enable Timer/Event Counter 0/1 interrupt bit (ET0I/ET1I), en able external interrupt bit (EEI) and enable master inter rupt bit (EMI) constitute an interrupt control register (INTC) which is located at 0BH in the data memory. EMI, EEI, ET0I and ET1I are used to control the enabling/dis abling of interrupts. These bits prevent the requested interrupt from being serviced. Once the interrupt request flags (T0F, T1F, EIF) are set, they will remain in the INTC register until the interrupts are serviced or cleared by a software instruction.

It is recommended that a program does not use the ²CALL subroutine² within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and enabling the interrupt is not well controlled, the original control sequence will be dam aged once the ²CALL² operates in the interrupt subrou tine.

Oscillator Configuration

There are 2 oscillator circuits in the MCU.

O S C 1

/ 4

O S C 2

C r y s t a l O s c i l l a t o r R C O s c i l l a t o r

S Y S

N M O S O p e n D r a i n

System oscillator

There are 2 oscillator circuits implemented in the mi cro-controller.

Both of them are designed for system clocks, namely the RC oscillator and the crystal oscillator, which are de termined by options. No matter what oscillator type is selected, the signal provides the system clock. The HALT mode stops the system oscillator and resists the external signal to conserve power.

If an RC oscillator is used, an external resistor between

OSC1 and VSS is required and the resistance should

range from 100kW to 820kW. The system clock, divided

by 4, is available on OSC2, which can be used to syn chronize external logic. The internal RC oscillator pro

vides the most cost effective solution. However, the

frequency of oscillation may vary with VDD, temperatures and the chip itself due to process variations. It is, therefore, not suitable for timing sensitive operations where an accurate oscillator frequency is desired.

If the crystal oscillator is used, a crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator, and no other external components are demanded. Instead of a crystal, the resonator can also be connected between OSC1 and OSC2 to get a frequency reference, but two external ca

pacitors in OSC1 and OSC2 are required.

The WDT oscillator is a free running on-chip RC oscilla

tor, and no external components are required. Even if the system enters the power down mode, the system clock is stopped, but the WDT oscillator still works with a

O S C 1

O S C 2

0 EMI Controls the master (global) interrupt (1=enabled; 0=disabled)

1 EEI Controls the external interrupt (1=enabled; 0=disabled)

2 ET0I Controls the Timer/Event Counter 0 interrupt (1=enabled; 0=disabled)

INTC

(0BH)

3 ET1I Controls the Timer/Event Counter 1 interrupt (1=enabled; 0=disabled)

4 EIF External interrupt request flag (1= active; 0= inactive)

5 T0F Internal Timer/Event Counter 0 request flag (1=active; 0=inactive)

6 T1F Internal Timer/Event Counter 1 request flag (1=active; 0=inactive)

¾ Unused bit, read as ²0²

INTC register

Rev. 1.40 8 July 16, 2003

HT48CA3

period of approximately 90ms. The WDT oscillator can be disabled by ROM code option to conserve power.

Watchdog Timer - WDT

The WDT clock source is implemented by a dedicated RC oscillator (WDT oscillator), instruction clock (system clock divided by 4), determines the ROM code option. This timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. The Watchdog Timer can be dis abled by ROM code option. If the Watchdog Timer is dis abled, all the executions related to the WDT result in no operation.

Once the internal WDT oscillator (RC oscillator with a period of 90ms@3V normally) is selected, it is first di vided by 256 (8-stage) to get the nominal time-out pe riod of 23ms@3V. This time-out period may vary with temperatures, VDD and process variations. By invoking the WDT prescaler, longer time-out periods can be real ized. Writing data to WS2, WS1, WS0 (bit 2,1,0 of the WDTS) can give different time-out periods. If WS2, WS1, and WS0 are all equal to 1, the division ratio is up to 1:128, and the maximum time-out period is 2.9s/3V seconds. If the WDT oscillator is disabled, the WDT clock may still come from the instruction clock and oper ates in the same manner except that in the HALT state the WDT may stop counting and lose its protecting purpose. In this situation the logic can only be restarted by external logic. The high nibble and bit 3 of the WDTS are reserved for user¢s defined flags, which can be used to indicate some specified status.

If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock.

WS2 WS1 WS0 Division Ratio

000 1:1

001 1:2

010 1:4

011 1:8

1 0 0 1:16

1 0 1 1:32

1 1 0 1:64

1 1 1 1:128

WDTS register

The WDT overflow under normal operation will initialize ²chip reset² and set the status bit ²TO². But in the HALT mode, the overflow will initialize a ²warm reset² and only the PC and SP are reset to zero. To clear the contents of WDT (including the WDT prescaler), three methods are adopted; external reset (a low level to RES struction anda ²HALT² instruction. The software instruc tion include ²CLR WDT² and the other set -²CLR WDT1² and ²CLR WDT2². Of these two types of instruc

tion, only one can be active depending on the ROM

code option -²CLR WDT times selection option².Ifthe ²CLR WDT² is selected (i.e. CLR WDT times equal one), any execution of the ²CLR WDT² instruction will clear the WDT. In the case that ²CLR WDT1² and ²CLR WDT2² are chosen (i.e. CLR WDT times equal two),

these two instructions must be executed to clear the

WDT; otherwise, the WDT may reset the chip as a result of time-out.

Power Down Operation - HALT

The HALT mode is initialized by the ²HALT² instruction and results in the following...

The system oscillator will be turned off but the WDT

oscillator remains running (if the WDT oscillator is se lected).

The contents of the on chip RAM and registers remain unchanged.

WDT and WDT prescaler will be cleared and recounted again (if the WDT clock is from the WDT oscillator).

All of the I/O ports maintain their original status.

The PD flag is set and the TO flag is cleared.

The system can leave the HALT mode by means of an external reset, an interrupt, an external falling edge sig nal on port A or a WDT overflow. An external reset causes a device initialization and the WDT overflow per forms a ²warm reset². After the TO and PD flags are ex amined, the reason for chip reset can be determined. The PD flag is cleared by system power-up or executing the ²CLR WDT² instruction and is set when executing the ²HALT² instruction. The TO flag is set if the WDT time-out occurs, and causes a wake-up that only resets the PCand SP; the others remain in their original status.

The port A wake-up and interrupt methods can be con sidered as a continuation of normal execution. Each bit

), software in

S y s t e m C l o c k / 4

W D T P r e s c a l e r

7 - b i t C o u n t e r

8 - t o - 1 M U X

W D T T i m e - o u t

W S 0 ~ W S 2

W D T O S C

R O M C o d e

O p t i o n

S e l e c t

8 - b i t C o u n t e r

Watchdog Timer

Rev. 1.40 9 July 16, 2003

HT48CA3

in port A can be independently selected to wake up the device by mask option. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If it awakens from an interrupt, two se quence may occur. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. If the inter rupt is enabled and the stack is not full, the regular inter rupt response takes place. If an interrupt request flag is set to ²1² before entering the HALT mode, the wake-up function of the related interrupt will be disabled. Once a wake-up event occurs, it takes 1024 t

(system clock

SYS

period) to resume normal operation. In other words, a dummy period will be inserted after a wake-up. If the wake-up results from an interrupt acknowledge signal, the actual interrupt subroutine execution will be delayed by one or more cycles. If the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished.

To minimize power consumption, all the I/O pins should be carefully managed before entering the HALT status.

Reset

There are threewaysinwhicharesetcanoccur:

RES reset during normal operation

RES reset during HALT

WDT time-out reset during normal operation

The WDT time-out during HALT is different from other chip reset conditions, since it can perform a ²warm re set² that resets only the PC and SP, leaving the other circuits in their original state. Some registers remain unchanged during other reset conditions. Most registers are reset to the ²initial condition² when the reset conditions are met. By examining the PD and TO flags, the program can distinguish between different ²chip resets².

TO PD RESET Conditions

0 0 RES

u u RES

0 1 RES

reset during power-up

reset during normal operation

wake-up HALT

1 u WDT time-out during normal operation

1 1 WDT wake-up HALT

The functional unit chip reset status are shown below.

PC 000H

Interrupt Disable

Prescaler Clear

WDT

Clear. After master reset, WDT begins counting

Timer/Event Counter Off

Input/output Ports Input mode

SP Points to the top of the stack

V D D

R E S

S S T T i m e - o u t

C h i p R e s e t

Reset timing chart

D D

R E S

Reset circuit

H A L T

W D T

R E S

S S T

O S C 1

1 0 - b i t R i p p l e

C o u n t e r

S y s t e m R e s e t

S S T

W a r m R e s e t

C o l d R e s e t

Note: ²u² stands for unchanged

To guarantee that the system oscillator is started and

Reset configuration

stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses when the sys

tem reset (power-up, WDT time-out or RES reset) or the system awakes from the HALT state.

When a system reset occurs, the SST delay is added during the reset period. Any wake-up from HALT will en

able the SST delay.

Rev. 1.40 10 July 16, 2003

HT48CA3

The states of the registers is summarized in the table.

MP0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

MP1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

BP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

Program Counter

TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

TBLH --xx xxxx --uu uuuu --uu uuuu --uu uuuu --uu uuuu

WDTS 0000 0111 0000 0111 0000 0111 0000 0111 uuuu uuuu

STATUS --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu

INTC --00 -000 --00 -000 --00 -000 --00 -000 --uu -uuu

TMR0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

TMR0C 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu

TMR1H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

TMR1L xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

TMR1C 00-0 1--- 00-0 1--- 00-0 1--- 00-0 1--- uu-u u---

PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu

PAC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu

PB 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu

PBC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu

PC --11 1111 --11 1111 --11 1111 --11 1111 --uu uuuu

PCC --11 1111 --11 1111 --11 1111 --11 1111 --uu uuuu

PF ---- ---1 ---- ---1 ---- ---1 ---- ---1 ---- ---u

PFC ---- ---1 ---- ---1 ---- ---1 ---- ---1 ---- ---u

TBHP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

Reset

(Power On)

0000H 0000H 0000H 0000H 0000H

WDT Time-out

(Normal Operation)

RES

Reset

RES Reset

(HALT)

WDT Time-out

(HALT)*

Note:

²*² stands for warm reset ²u² stands for unchanged ²x² stands for unknown

Rev. 1.40 11 July 16, 2003

+ 25 hidden pages

Holtek Semiconductor Inc HT48CA3 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

General Description

Block Diagram

Pin Assignment

Pin Description

Absolute Maximum Ratings

D.C. Characteristics

A.C. Characteristics

Functional Description