Holtek Semiconductor Inc HT48C50-1, HT48C50-1-A Datasheet

HT48C50-1

8-Bit Microcontroller

1 June 14, 2000

General Description

The device is an 8-bit high performance RISC-like microcontroller designed for multi

ple I/O product applications. The device is particularly suitable for use in products such as

remote controllers, fan/light controllers, wash

ing machine controllers, scales, toys and vari

ous subsystem controllers. A HALT feature is included to reduce power consumption.

Features

Operating voltage: f

SYS

=4MHz: 2.4V~5.5V

SYS

=8MHz: 4.5V~5.5V

Low voltage reset function

35 bidirectional I/O lines (max.)

1 interrupt input shared with an I/O line

8-bit programmable timer/event counter with overflow interrupt and 8-stage prescaler

16-bit programmable timer/event counter and overflow interrupts

On-chip RC oscillator, external crystal and RC oscillator

32768Hz crystal oscillator for timing purposes only

Watchdog Timer

4096´15 program memory ROM

160´8 data memory RAM

Buzzer driving pair and PFD supported

Halt function and wake-up feature reduce power consumption

6-level subroutine nesting

Up to 0.5ms instruction cycle with 8MHz system clock at V

=5V

Bit manipulation instruction

15-bit table read instruction

63 powerful instructions

All instructions in one or two machine cycles

28-pin SKDIP and 40-pin DIP package

Preliminary

Block Diagram

HT48C50-1

2 June 14, 2000

Preliminary

IN T /P G 0

OSC2/

PG2

OSC1/

PG1 RES

VDD

MUX

TM R 0

TM R 0C

TM R 0

VSS

P re scaler

SYS

PG0

Program

ROM

Program

C ounter

Interrupt

Circuit

STACK

IN T C

DATA

Memory

In struction

R egister

M U X

In struction

D ecoder

STATUS

ALU

Shifter

Tim ing

G enerator

ACC

M U X

S Y S C L K /4

WDTS

WDT

WDT OSC

W D T P rescale r

M U X

RTC OSC

E N /D IS

PG1 PG2

In te rn a l

RC OSC

PDC

PORT D

PD0~PD7

PGC

PORT G

PG0~PG2

PBC

PORT B

PB0~PB7

BZ/BZ

PAC

PORT A

PA0~PA7

PORT C

PC0~PC7

PCC

TM R 1C

TM R 1

M U X

TM R 1

SYS

M U X

Pin Assignment

Pad Assignment

* The IC substrate should be connected to VSS in the PCB layout artwork.

HT48C50-1

3 June 14, 2000

Preliminary

301131

1232133314341535163617371838193920

(0 , 0 )

PA0

PB3

PB2

PB0/BZ

PD7

PD6

PD5

PD4

VSS

TM R 0

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

PD0

P G 0 /IN T

VDD

TM R 1

PD3

PD2

PD1

RES

OSC1/PG1

OSC2/PG2

PA7

PA6

PA5

PA4

PB7

PB6

PB5

PB4

PA3

PA2

PA1

PB1/BZ

PB6

PB7

PA4

PA5

PA6

PA7

OSC2/PG2

OSC1/PG1

VDD

RES

PC5/TM R 1

PC4

PC3

PC2

PB5

PB4

PA3

PA2

PA1

PA0

PB3

PB2

PB1/BZ

PB0/BZ

VSS

P G 0 /IN T

PC0/TM R 0

PC1

H T48C 50-1-A

2 8 S K D IP

H T48C 50-1

4 0 D IP

PB6

PB7

PA4

PA5

PA6

PA7

OSC2/PG2

OSC1/PG1

VDD

RES

TM R1

PD3

PD2

PD1

PD0

PC7

PC6

PC5

PC4

PC3

PB5

PB4

PA3

PA2

PA1

PA0

PB3

PB2

PB1/BZ

PB0/BZ

PD7

PD6

PD5

PD4

VSS

PG0/INT

TM R0

PC0

PC1

PC2

Pad Description

Pad

No.

Pad Name I/O Mask Option Description

1, 40~38, 33~30

PA0~PA7 I/O

Pull-high*

Wake-up

CMOS/schmitt

trigger input

Bidirectional 8-bit input/output port. Each bit can be configured as a wake-up input by mask option. Soft

ware instructions determine the CMOS output or schmitt trigger or CMOS input with pull-high resistor (determined by pull-high options).

5 4 3, 2, 37~34

PB0/BZ PB1/BZ PB2~PB7

I/O

Pull-high*

I/O or BZ/BZ

CMOS/schmitt

trigger input

Bidirectional 8-bit input/output port. Software in

structions determine the CMOS output or schmitt trigger input with pull-high resistor (determined by pull-high options). The PB0 and PB1 are pin-shared with the BZ and BZ

, respectively. Once the PB0 and PB1 are selected as buzzer driving outputs, the output signals come from an internal PFD generator (shared with timer/event counter 0).

21~24, 9~6

PD0~PD7 I/O

Pull-high*

CMOS/schmitt

trigger input

Bidirectional I/O lines. Software instructions deter

mine the CMOS output or schmitt trigger input with pull-high resistor (determined by pull-high options).

10 VSS

¾¾

Negative power supply, ground

11 PG0/INT

I/O Pull-high*

Bidirectional I/O lines. Software instructions deter

mine the CMOS output or schmitt trigger input with pull-high resistor (determined by pull-high options). This external interrupt input is pin-shared with PG0. The external interrupt input is activated on a high to low transition.

12 TMR0 I

Timer/event counter 0 schmitt trigger input (without pull-high resistor)

13~20 PC0~PC7 I/O

Pull-high*

CMOS/schmitt

trigger input

Bidirectional I/O lines. Software instructions determine the CMOS output or schmitt trigger input with pull-high resistor (determined by pull-high options).

25 TMR1 I

Timer/event counter 1 schmitt trigger input (without pull-high resistor)

26 RES

Schmitt trigger reset input. Active low

27 VDD

¾¾

Positive power supply

HT48C50-1

4 June 14, 2000

Preliminary

Pad

No.

Pad Name I/O Mask Option Description

28 29

OSC1/PG1 OSC2/PG2IO

Pull-high*

Crystal

or RC

or Int. RC+I/O

or Int.

RC+RTC

OSC1, OSC2 are connected to an RC network or Crys

tal (determined by mask option) for the internal sys

tem clock. In the case of RC operation, OSC2 is the output terminal for 1/4 system clock. These two pins can also be optioned as an RTC oscillator (32768Hz) or I/O lines. In these two cases, the system clock comes from an internal RC oscillator whose frequency has 4 options (3.2MHz, 1.6MHz, 800kHz, 400kHz). If the I/O option is selected, the pull-high options can also be en

abled or disabled. Otherwise the PG1 and PG2 are used as internal registers (pull-high resistors are al

ways disabled).

Note: * The pull-high resistors of each I/O port (PA, PB, PC, PD, PG) are controlled by options.

Absolute Maximum Ratings

Supply Voltage ...............VSS-0.3V to VSS+5.5V

Storage Temperature.................-50°Cto125°C

Input Voltage.................V

-0.3V to VDD+0.3V

Operating Temperature ..............-40°Cto85°C

Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maxi

mum Ratings" may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged expo

sure to extreme conditions may affect device reliability.

D.C. Characteristics

Ta=25°C

Symbol Parameter

Test Conditions

Min. Typ. Max. Unit

Conditions

DD1

Operating Voltage

SYS

=4MHz

2.4

5.5 V

DD2

Operating Voltage

SYS

=8MHz

4.5

5.5 V

DD1

Operating Current (Crystal OSC)

No load, f

SYS

=4MHz

12mA

35mA

DD2

Operating Current (RC OSC)

No load, f

SYS

=4MHz

12mA

35mA

DD3

Operating Current (Crystal OSC)

No load, f

SYS

=8MHz

48mA

STB1

Standby Current (WDT Enabled RTC Off)

No load, system HALT

¾¾

STB2

Standby Current (WDT Disabled RTC Off)

No load, system HALT

¾¾

HT48C50-1

5 June 14, 2000

Preliminary

Symbol Parameter

Test Conditions

Min. Typ. Max. Unit

Conditions

STB3

Standby Current (WDT Disabled, RTC On)

No load, system HALT

¾¾

IL1

Input Low Voltage for I/O Ports

¾¾

0.2V

IH1

Input High Voltage for I/O Ports

¾¾

0.8V

IL2

Input Low Voltage (RES

)

¾¾

0.4V

IH2

Input High Voltage (RES

)

¾¾

0.9V

I/O Port Sink Current

=0.1V

612

=0.1V

10 25

I/O Port Source Current

=0.9V

-3 -6 ¾

=0.9V

-5 -10 ¾

Pull-high Resistance

40 60 80

10 30 50

LVR1

Low Voltage Reset

2.2V option 2.0 2.2 2.4 V

LVR2

Low Voltage Reset

3.3V option 3.0 3.3 3.6 V

A.C. Characteristics

Ta=25°C

Symbol Parameter

Test Conditions

Min. Typ. Max. Unit

Conditions

SYS1

System Clock (Crystal OSC)

400

4000 kHz

400

8000 kHz

SYS2

System Clock (RC OSC)

400

4000 kHz

400

8000 kHz

SYS3

System Clock (Internal RC)

3.2MHz option

1600 2500 3500 kHz

5V 2000 3200 4500 kHz

TIMER

Timer I/P Frequency (TMR0/TMR1)

4000 kHz

8000 kHz

WDTOSC

Watchdog Oscillator

43 86 168

35 65 130

WDT1

Watchdog Time-out Period (WDT OSC)

Without WDT prescaler

11 22 43 ms

5V 9 17 35 ms

HT48C50-1

6 June 14, 2000

Preliminary

Symbol Parameter

Test Conditions

Min. Typ. Max. Unit

Conditions

WDT2

Watchdog Time-out Period (System Clock)

Without WDT prescaler

1024

SYS

WDT3

Watchdog Time-out Period (RTC OSC)

Without WDT prescaler

7.812

RES

External Reset Low Pulse Width

¾¾

¾¾ms

SST

System Start-up Timer Period

Power-up, reset or wake-up from HALT

1024

SYS

INT

Interrupt Pulse Width

¾¾

¾¾ms

Functional Description

HT48C50-1

7 June 14, 2000

Preliminary

Execution flow

The system clock for the microcontroller is de

rived from either a crystal or an RC oscillator. The system clock is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles.

Instruction fetching and execution are pipelined in such a way that a fetch takes an in

struction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruction to effectively execute in a cycle. If an instruction changes the program counter, two cycles are required to complete the instruction.

Program counter - PC

The program counter (PC) controls the sequence in which the instructions stored in the program ROM are executed and its contents

specify a full range of program memory.

After accessing a program memory word to fetch an instruction code, the contents of the program counter are incremented by one. The program counter then points to the memory word contain

ing the next instruction code.

When executing a jump instruction, conditional skip execution, loading PCL register, subrou

tine call, initial reset, internal interrupt, exter

nal interrupt or return from subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction.

The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise proceed with the next instruction.

T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4

F e tc h IN S T (P C )

Execute IN S T (P C -1)

F e tc h IN S T (P C + 1 )

Execute IN S T (P C )

F e tc h IN S T (P C + 2 )

Execute IN S T (P C + 1)

PC PC+1 PC+2

S ystem C lock

OSC2 (RC only)

Execution flow

HT48C50-1

8 June 14, 2000

Preliminary

The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination will be within 256 loca

tions.

When a control transfer takes place, an addi

tional dummy cycle is required.

Program memory - ROM

The program memory is used to store the pro

gram instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 4096´15 bits, addressed by the program counter and table pointer.

Certain locations in the program memory are reserved for special usage:

Location 000H This area is reserved for program initializa

tion. After chip reset, the program always be

gins execution at location 000H.

Location 004H This area is reserved for the external inter

rupt service program. If the INT

input pin is activated, the interrupt is enabled and the stack is not full, the program begins execution at location 004H.

Location 008H This area is reserved for the timer/event coun

ter 0 interrupt service program. If a timer inter

rupt results from a timer/event counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 008H .

Mode

Program Counter

*11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0

Initial Reset 000000000000

External Interrupt 000000000100

Timer/Event Counter 0 Overflow

000000001000

Timer/Event Counter 1 Overflow

000000001100

Skip PC+2

Loading PCL *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0

Jump, Call Branch #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0

Return from Subroutine S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

Program counter

Note: *11~*0: Program counter bits S11~S0: Stack register bits

#11~#0: Instruction code bits @7~@0: PCL bits

15 bits

FFFH

nFFH

Program Memory

D evice Initia liza tion P rogram

E x te rn a l In te rr u p t S u b ro u tin e

Tim er/E vent C ounter 0

Interrupt Subroutine

Look-up Table (256 words)

N ote: n ranges from 0 to F

00C H

n00H

008H

004H

000H

Tim er/E vent C ounter 1

Interrupt Subroutine

Program memory

HT48C50-1

9 June 14, 2000

Preliminary

Instruction

Table Location

*11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0

TABRDC [m] P11 P10 P9 P8 @7 @6 @5 @4 @3 @2 @1 @0

TABRDL [m] 1 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0

Table location

Note: *11~*0: Table location bits P11~P8: Current program counter bits

@7~@0: Table pointer bits

Location 00CH This location is reserved for the timer/event

counter 1 interrupt service program. If a timer interrupt results from a timer/event counter 1 overflow, and the interrupt is en

abled and the stack is not full, the program begins execution at location 00CH.

Table location Any location in the ROM space can be used as

look-up tables. The instructions "TABRDC [m]" (the current page, 1 page=256 words) and "TABRDL [m]" (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are transferred to the lower portion of TBLH, and the remaining 1-bit words are read as "0". The Table Higher-order byte register (TBLH) is read only. The table pointer (TBLP) is a read/write register (07H), which indicates the table location. Before accessing the table, the location must be placed in the TBLP. The TBLH is read only and cannot be restored. If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR. Errors can occur. In other words, using the table read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read instruction has to be applied in both the main routine and the ISR, the interrupt is supposed to be disabled prior to the table read instruction. It will not be enabled

until the TBLH has been backed up. All table related instructions require two cycles to com

plete the operation. These areas may function as normal program memory depending upon the requirements.

Stack register - STACK

This is a special part of the memory which is used to save the contents of the program coun

ter (PC) only. The stack is organized into 6 lev

els and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the stack pointer (SP) and is neither readable nor writeable. At a subroutine call or interrupt ac

knowledge signal, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the pro

gram counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack.

If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be in

hibited. When the stack pointer is decremented (by RET or RETI), the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. In a similar case, if the stack is full and a "CALL" is subsequently executed, stack overflow occurs and the first entry will be lost (only the most recent 6 return addresses are stored).

HT48C50-1

10 June 14, 2000

Preliminary

Data memory - RAM

The data memory is designed with 184´8 bits. The data memory is divided into two func

tional groups: special function registers and general purpose data memory (160´8). Most are read/write, but some are read only.

The special function registers include the indi

rect addressing registers (00H, 02H), timer/event counter 0 (TMR0;0DH), timer/event counter 0 control register (TMR0C;0EH), timer/event counter 1 higher order byte register (TMR1H;0FH), timer/event counter 1 lower order byte register (TMR1L;10H), timer/event counter 1 control register (TMR1C;11H), program counter lower-order byte register (PCL;06H), memory pointer registers (MP0;01H, MP1;03H), accu

mulator (ACC;05H), table pointer (TBLP;07H), table higher-order byte register (TBLH;08H), status register (STATUS;0AH), interrupt control register (INTC;0BH), Watch

dog Timer option setting register (WDTS;09H), I/O registers (PA;12H, PB;14H, PC;16H, PD;18H, PG;1EH) and I/O control registers (PAC;13H, PBC;15H, PCC;17H, PDC;19H, PGC;1FH). The remaining space be

fore the 60H is reserved for future expanded usage and reading these locations will get "00H". The general purpose data memory, ad

dressed from 60H to FFH, is used for data and control information under instruction com

mands.

All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by "SET [m].i" and "CLR [m].i". They are also indirectly accessible through memory pointer registers (MP0 or MP1).

Indirect addressing register

Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation of [00H] ([02H]) will access data memory pointed to by MP0 (MP1). Reading location 00H (02H) itself indirectly will return the result 00H. Writing indirectly results in no operation.

The memory pointer registers (MP0 and MP1) are 8-bit registers.

G eneral P urpose DATA M EM ORY

(160 B ytes)

Special P urpose DATA M EM ORY

00H

01H

02H

03H

04H

05H

06H

07H

08H

09H

0AH

0BH

0C H

0D H

0EH

0FH

10H

11H

12H

13H

14H

15H

16H

17H

18H

19H

1AH

1BH

1C H

1D H

1EH

1FH

FFH

: U n u s e d

R ead as "00"

5FH 60H

20H

Indirect Addressing R egister 0

MP0

Indirect Addressing R egister 1

MP1

ACC

PCL

TBLP

TBLH

WDTS

STATUS

IN T C

TM R 0

TM R 0C

TM R 1H

TM R 1L

TM R 1C

PAC

PBC

PCC

PDC

PGC

RAM mapping

HT48C50-1

11 June 14, 2000

Preliminary

Accumulator

The accumulator is closely related to ALU oper

ations. It is also mapped to location 05H of the data memory and can carry out immediate data operations. The data movement between two data memory locations must pass through the accumulator.

Arithmetic and logic unit - ALU

This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following func

tions:

Arithmetic operations (ADD, ADC, SUB, SBC, DAA)

Logic operations (AND, OR, XOR, CPL) Rota

tion (RL, RR, RLC, RRC)

Increment and Decrement (INC, DEC)

Branch decision (SZ, SNZ, SIZ, SDZ ....)

The ALU not only saves the results of a data op

eration but also changes the status register.

Status register - STATUS

This 8-bit register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PD), and

watchdog time-out flag (TO). It also records the status information and controls the operation sequence.

With the exception of the TO and PD flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PD flag. In addition opera

tions related to the status register may give different results from those intended. The TO flag can be affected only by system power-up, a WDT time-out or executing the "CLR WDT" or "HALT" instruction. The PD flag can be affected only by executing the "HALT" or "CLR WDT" instruction or during a system power-up.

The Z, OV, AC and C flags generally reflect the status of the latest operations.

In addition, on entering the interrupt sequence or executing the subroutine call, the status reg

ister will not be pushed onto the stack automat

ically. If the contents of the status are important and if the subroutine can corrupt the status register, precautions must be taken to save it properly.

Labels Bits Function

C is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction.

AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared.

Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.

OV is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared.

PD is cleared by system power-up or executing the "CLR WDT" instruction. PD is set by executing the "HALT" instruction.

TO is cleared by system power-up or executing the "CLR WDT" or "HALT" in

struction. TO is set by a WDT time-out.

6 Undefined, read as "0"

7 Undefined, read as "0"

Status register

HT48C50-1

12 June 14, 2000

Preliminary

Interrupt

The device provides an external interrupt and internal timer/event counter interrupts. The Interrupt Control Register (INTC;0BH) con

tains the interrupt control bits to set the en

able/disable and the interrupt request flags.

Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing the EMI bit). This scheme may prevent any fur

ther interrupt nesting. Other interrupt re

quests may occur during this interval but only the interrupt request flag is recorded. If a cer

tain interrupt requires servicing within the ser

vice routine, the EMI bit and the corresponding bit of the INTC may be set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related in

terrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must be prevented from becoming full.

All these kinds of interrupts have a wake-up ca

pability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a sub

routine at specified location in the program memory. Only the program counter is pushed

onto the stack. If the contents of the register or status register (STATUS) are altered by the in

terrupt service program which corrupts the de

sired control sequence, the contents should be saved in advance.

External interrupts are triggered by a high to low transition of the INT

and the related inter

rupt request flag (EIF; bit 4 of INTC) will be set. When the interrupt is enabled, the stack is not full and the external interrupt is active, a sub

routine call to location 04H will occur. The in

terrupt request flag (EIF) and EMI bits will be cleared to disable other interrupts.

The internal timer/event counter 0 interrupt is initialized by setting the timer/event counter 0 interrupt request flag (T0F; bit 5 of INTC), caused by a timer 0 overflow. When the inter

rupt is enabled, the stack is not full and the T0F bit is set, a subroutine call to location 08H will occur. The related interrupt request flag (T0F) will be reset and the EMI bit cleared to disable further interrupts.

The internal timer/even counter 1 interrupt is initialized by setting the timer/event counter 1 interrupt request flag (T1F;bit 6 of INTC), caused by a timer 1 overflow. When the inter-

INTC

(0BH)

0 EMI

Controls the master (global) interrupt (1= enabled; 0= disabled)

1 EEI

Controls the external interrupt (1= enabled; 0= disabled)

2 ET0I

Controls the timer/event counter 0 interrupt (1= enabled; 0= disabled)

3 ET1I

Controls the timer/event counter 1 interrupt (1= enabled; 0= disabled)

4 EIF

External interrupt request flag (1= active; 0= inactive)

5 T0F

Internal timer/event counter 0 request flag (1= active; 0= inactive)

6 T1F

Internal timer/event counter 1 request flag (1= active; 0= inactive)

Unused bit, read as "0"

INTC register

HT48C50-1

13 June 14, 2000

Preliminary

rupt is enabled, the stack is not full and the T1F is set, a subroutine call to location 0CH will oc

cur. The related interrupt request flag (T1F) will be reset and the EMI bit cleared to disable further interrupts.

During the execution of an interrupt subroutine, other interrupt acknowledge signals are held until the "RETI" instruction is executed or the EMI bit and the related interrupt control bit are set to 1 (if the stack is not full). To return from the interrupt subroutine, "RET" or "RETI" may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not.

Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are en

abled. In the case of simultaneous requests the following table shows the priority that is ap

plied. These can be masked by resetting the EMI bit.

No. Interrupt Source Priority Vector

a External Interrupt 1 04H

Timer/event Counter 0 Overflow

2 08H

Timer/event Counter 1 Overflow

3 0CH

The timer/event counter 0/1 interrupt request flag (T0F/T1F), external interrupt request flag (EIF), enable timer/event counter 0/1 interrupt bit (ET0I/ET1I), enable external interrupt bit (EEI) and enable master interrupt bit (EMI) constitute an interrupt control register (INTC) which is located at 0BH in the data memory. EMI, EEI, ET0I and ET1I are used to control the enabling/disabling of interrupts. These bits

prevent the requested interrupt from being ser

viced. Once the interrupt request flags (T0F, T1F, EIF) are set, they will remain in the INTC register until the interrupts are serviced or cleared by a software instruction.

It is recommended that a program does not use the "CALL subroutine" within the inter

rupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and enabling the interrupt is not well controlled, the original control sequence will be damaged once the "CALL" operates in the in

terrupt subroutine.

Oscillator configuration

There are 3 oscillator circuits in the microcontroller.

All of them are designed for system clocks, namely the external RC oscillator, the external Crystal oscillator and the internal RC oscillator, which are determined by mask option. No matter what oscillator type is selected, the signal provides the system clock. The HALT mode stops the system oscillator and ignores an external signal to conserve power.

S ystem C lo ck/4

8-bit C ounter

W D T P rescaler

7-bit C ounter

8-to-1 M U X

W D T T im e-out

WS0~WS2

ROM

C ode Option Select

WDT OSC

RTC O SC

Watchdog Timer

C rystal O scilla to r

(Include 32768H z)

R C O s c illa to r

OSC1

OSC2

N M O S O p e n D r a in

OSC2

SYS

470pF

OSC1

System oscillator

HT48C50-1

14 June 14, 2000

Preliminary

If an RC oscillator is used, an external resistor between OSC1 and VDD is required and the resistance must range from 51kW to 1MW. The system clock, divided by 4, is available on OSC2, which can be used to synchronize exter

nal logic. The RC oscillator provides the most cost effective solution. However, the frequency of oscillation may vary with VDD, tempera

tures and the chip itself due to process varia

tions. It is, therefore, not suitable for timing sensitive operations where an accurate oscilla

tor frequency is desired.

If the Crystal oscillator is used, a crystal across OSC1 and OSC2 is needed to provide the feed

back and phase shift required for the oscillator. No other external components are required. In stead of a crystal, a resonator can also be con

nected between OSC1 and OSC2 to get a fre

quency reference, but two external capacitors in OSC1 and OSC2 are required. If the internal RC oscillator is used, the OSC1 and OSC2 can be selected as general I/O lines or an 32768Hz crystal oscillator (RTC OSC). Also, the frequen

cies of the internal RC oscillator can be

3.2MHz, 1.6MHz, 800kHz and 400kHz (de

pends on the options).

The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if the system enters the power down mode, the system clock is stopped, but the WDT oscillator still works within a period of 78ms. The WDT oscillator can be disabled by mask option to conserve power.

Watchdog Timer - WDT

The WDT clock source is implemented by a ded

icated RC oscillator (WDT oscillator), RTC clock or instruction clock (system clock divided by 4), determines the mask option. This timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. The Watchdog Timer can be disabled by mask option. If the Watchdog Timer is disabled, all the executions related to the WDT result in no operation. The RTC clock is enabled only in the internal RC+RTC mode.

Once the internal WDT oscillator (RC oscillator with a period of 65ms/5V normally) is selected, it

is first divided by 256 (8-stage) to get the nomi

nal time-out period of 16.6ms/5V. This time-out period may vary with temperatures, VDD and process variations. By invoking the WDT prescaler, longer time-out periods can be real

ized. Writing data to WS2, WS1, WS0 (bit 2,1,0 of the WDTS) can give different time-out periods. If WS2, WS1, and WS0 are all equal to 1, the divi

sion ratio is up to 1:128, and the maximum time-out period is 2.2s/5V seconds. If the WDT os

cillator is disabled, the WDT clock may still come from the instruction clock and operates in the same manner except that in the HALT state the WDT may stop counting and lose its protecting purpose. In this situation the logic can only be re

started by external logic. The high nibble and bit 3 of the WDTS are reserved for user's defined flags, which can be used to indicate some speci

fied status.

If the device operates in a noisy environment, us

ing the on-chip RC oscillator (WDT OSC) or 32kHz crystal oscillator (RTC OSC) is strongly recommended, since the HALT will stop the sys

tem clock.

WS2 WS1 WS0 Division Ratio

000 1:1

001 1:2

010 1:4

011 1:8

1 0 0 1:16

1 0 1 1:32

1 1 0 1:64

1 1 1 1:128

WDTS register

The WDT overflow under normal operation will initialize "chip reset" and set the status bit "TO". But in the HALT mode, the overflow will initialize a ²warm reset² and only the PC and SP are reset to zero. To clear the contents of WDT (including the WDT prescaler), three methods are adopted; external reset (a low level to RES

), software instruction and a "HALT" in

struction. The software instruction include "CLR WDT" and the other set - "CLR WDT1" and "CLR WDT2". Of these two types of instruc

+ 31 hidden pages

Holtek Semiconductor Inc HT48C50-1, HT48C50-1-A Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual