Holtek Semiconductor Inc HT47C20L Datasheet

Features

Operating voltage: 1.2V~2.2V

Eight bidirectional I/O lines

Four input lines

One interrupt input

One 16-bit programmable timer/event

counter with PFD (programmable frequency divider) function On-chip 32768Hz crystal oscillator

Watchdog timer

2K ´ 16 program memory ROM

64 ´ 8 data memory RAM

One real time clock (RTC)

One 8-bit prescaler for real time clock

One buzzer output

One low voltage detector

General Description

The HT47C20L is an 8-bit high performance RISC-like microcontroller. Its single cycle in struction and two-stage pipeline architecture make high speed applications. The device is suited for use in multiple LCD low power appli-

HT47C20L

8-Bit Microcontroller

One low voltage reset circuit

Halt function and wake-up feature reduce

power consumption LCD bias C type

One LCD driver with 20 ´ 2or20´ 3or19´ 4

segments Two channels RC type A/D converter

Four-level subroutine nesting

Bit manipulation instruction

16-bit table read instruction

Up to 122ms instruction cycle with 32768Hz

system clock All instructionsin one or two machine cycles

63 powerful instructions

cations among which are calculators, clock tim ers, games, scales, toys, thermometers,

hygrometers, body thermometers, capacitor scaler, other hand held LCD products, and battery system in particular.

1 January 18, 2000

Block Diagram

HT47C20L

PB0/INT

Program

ROM

Instruction

R egister

Instruction

D ecoder

Tim ing

G enerator

OSC2

OSC1 RES

VDD VSS

D ouble

Voltage

V1 V2 V3

Program

C ounter

ALU

S h ifte r

ACC

COM 0~ COM 2

STACK0 STACK1 STACK2 STACK3

M U X

MUX

LCD Driver

COM 3/ SEG19

In te r ru p t

Circuit

DATA

Memory

STATUS

LC D

Memory

SEG0~ SEG18

IN T C

Tim er A

Tim er B

R eal Tim e C lock

WDT

Tim e B ase

Port B

Port A

M U X

PFD

C onverter

A/D Clock

Type

A/D

32768H z (alw ays on)

PB0/IN T

PB1

PB2/TM R PB3

PA0/BZ PA1/BZ PA2 PA3/PFD PA4~PA7

S ystem C lock T1 RTC Output PB2/TM R

PB3/PFD

IN 0 CS0 RS0 CRT0 RT0 IN 1 CS1 RS1 RT1

2 January 18, 2000

Pin Assignment

HT47C20L

OSC2

OSC1

RES

VDD

PA0/BZ

PA1/BZ

PA2

PA3/PFD

PA4

PA5

PA6

PA7

PB0/INT

PB1

PB2/TM R

PB3

TEST

VSS

20 21 22 23 24 25 26 27 28 29 30 31 32

RT1

61 60 59 58 57 56 55 54 53 5264 63 62

HT47C20L

64 Q FP

RS1

CS1

IN 1

CRT0

RT0

RS0

CS0

IN 0

COM 0

COM 1

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

COM 2

COM 3/SEG19

3 January 18, 2000

Pad Assignment

HT47C20L

RES

PA0/BZ

PA1/BZ

PA2

PA3/PFD

PA4

PA5

PA6

PA7

PB0/IN T

PB1

PB2/TM R

PB3

TEST

VSS

OSC1

RT1

OSC2

VDD

(0 , 0 )

RS1

CS1

IN 1

RT0

CRT0

225023

RS0

CS0

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

COM 3/SEG19

IN 0

COM 0

COM 1

COM 2

* The IC substrate should be connected to VSS in the PCB layout artwork.

4 January 18, 2000

Pin Description

HT47C20L

Pin Name I/O

RES

PA0/BZ PA1/BZ PA2 PA3/PFD PA4~PA7

PB0/INT PB1 PB2/TMR PB3

VSS

V1~V3, C1~C2

SEG19/COM3 COM2~COM0

SEG18~SEG0 O

VDD

OSC2 OSC1

IN0 CS0 RS0 CRT0

RT0

IN1 CS1 RS1 RT1

TEST

I/O

¾¾

I O O O

Mask

Option

Wake-up Pull-high

or None

CMOS or

NMOS

1/2 or 1/3

or 1/4

Duty

Function

Schmitt trigger reset input. Active low.

Bidirectional 8-bit input/output port. The low nibble of the PA can be configured as CMOS output or NMOS output with or without pull-high resistors (mask option). NMOS output can be configured as schmitt trigger input with or without pull-high resistors. Each bit of NMOS output can be configured as wake up input by mask option. Of the eight bits, PA0~PA1 can be set as I/O pins or buzzer outputs by mask option. PA3 can be set as an I/O pin or a PFD output by mask option.

Four-bit schmitt trigger input port. The PB is configured as with pull-high resistors. Of the four bits, PB0 can be set as an input pin or an external interrupt input pin (INT application. While PB2 can be set as an input pin or a timer/event counter input pin by software application.

Negative power supply, GND

Voltage pump

SEG19/COM3 can be set as a segment or a common output driver for LCD panel by mask option. COM2~COM0 are out puts for LCD panel plate.

LCD driver outputs for LCD panel segments

Positive power supply

OSC1 and OSC2 are connected to a 32768Hz crystal for the internal system clock and WDT source.

Oscillation input pin of channel 0 Reference capacitor connection pin of channel 0 Reference resistor connection pin of channel 0 Resistor/capacitor sensor connection pin for measurement of channel 0 Resistor sensor connection pin for measurement of channel 0

Oscillation input pin of channel 1 Reference capacitor connection pin of channel 1 Reference resistor connection pin of channel 1 Resistor sensor connection pin for measurement of channel 1

TEST mode input pin with pull-high resistor. It disconnects in normal operation.

) by software

5 January 18, 2000

Absolute Maximum Ratings

HT47C20L

Supply Voltage..............................-0.3V to 2.5V

Input Voltage.................V

-0.3V to VDD+0.3V

Storage Temperature.................-50°Cto125°C

Operating Temperature ..............-40°Cto85°C

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maxi

mum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged expo sure to extreme conditions may affect device reliability.

D.C. Characteristics

Ta=25°C

Test Conditions

Symbol Parameter

LVD

LVR

DD1

DD2

DD3

Operating Voltage

Low Voltage Detector Voltage

Low Voltage Reset Voltage

Operating Current (LVR Disable, LVD Disable)

Operating Current (LVR Disable, LVD Enable)

Operating Current (LVR Enable, LVD Enable)

Standby Current

STB1

(LVR Disable, LVD Disable, LCD Off)

Standby Current

STB2

(LVR Disable, LVD Enable, LCD On)

Standby Current

STB3

(LVR Enable, LVD Enable, LCD On)

Standby Current

STB4

(LVR Disable, LVD Enable, LCD On)

Standby Current

STB5

(LVR Off, LVD Disable, LCD Off)

Input Low Voltage for I/O Ports 1.5V

Input High Voltage for I/O Ports

Conditions

¾¾

No load, f

1.5V A/D Off, LVD Off

No load, f

1.5V A/D Off, LVD Off

No load, f

1.5V A/D Off, LVD Off

No load, system Halt

1.5V A/D Off, LVD Off

No load, system Halt

1.5V A/D Off, LVD Off

No load, system Halt

1.5V A/D Off, LVD Off

No load, system Halt

1.5V A/D Off, LVD On

=32768Hz

SYS

=32768Hz

SYS

=32768Hz

SYS

No load, system Halt A/D On

1.5

*R=5.1kW, *C=500P

1.5V

Min. Typ. Max. Unit

1.2 1.5 2.2 V

1.1 1.2 1.3 V

1.0 1.1 1.2 V

1.05

915

12 20

610

915

815

270 500

0.45 V

1.5 V

6 January 18, 2000

HT47C20L

Symbol Parameter

IL1

IL2

IH1

OL1

OH1

OL2

OH2

OL3

OH3

OL4

OH4

OL5

OH5

PH1

PH2

Input Low Voltage (RES) 1.5V

Input Low Voltage (INT

, TMR)

Input High Voltage (RES

, INT, TMR)

I/O Port Sink Current 1.5V

I/O Port Source Current 1.5V

Common 0~3 Output Sink Current

Common 0~3 Output Source Current

Segment 0~19 Output Sink Current

Segment 0~19 Output Source Current

Common 0~3 Output Sink Current

Common 0~3 Output Source Current

Segment 0~19 Output Sink Current

Segment 0~19 Output Source Current

RC oscillation Output Sink Current

RC oscillation Output Source Current

Pull-high Resistance of I/O Ports and INT

Pull-high Resistance of TEST 1.5V

Test Conditions

0.5V

0.3V

1.5V

0.8V

1.5V

Conditions

=0.15V

=1.35V

=0.3V (1/2 bias)

=2.7V (1/2 bias)

=0.3V (1/2 bias)

=2.7V (1/2 bias)

=0.45V (1/3 bias)

=4.05V (1/3 bias)

=0.45V (1/3 bias)

=4.05V (1/3 bias)

=0.15V

=1.35V

Min. Typ. Max. Unit

1.2

0.3 0.6

-0.2 -0.4 ¾

120 230

0.75 V

0.45 V

1.5 V

¾mA

-50 -100 ¾mA

30 60

¾mA

-20 -30 ¾mA

120 220

¾mA

-50 -100 ¾mA

30 60

¾mA

-20 -30 ¾mA

2 2.7

-2 -3.1 ¾

100 150 200

10 30 60

Note: *R means the resistance of RC type A/D converter

*C means the capacitance of RC type A/D converter

7 January 18, 2000

HT47C20L

A.C. Characteristics

Symbol Parameter

SYS1

TIMER

RES

SST

INT

RIS

LVD

Note: t

System Clock 1.5V

Timer I/P Frequency (TMR) 1.5V

External Reset Low Pulse Width

System Start-up Timer Period

Interrupt Pulse Width 1.5V

Power Supply Rise Time

Low Voltage Detector Response Time 1.5V

A/D Converter Frequency 1.5V

=1/f

SYS

Test Conditions

Min. Typ. Max. Unit

Conditions

¾¾

¾¾ ¾

Power-up

32768

100

8192

100

¾¾

200

¾¾¾

Ta=25°C

32768 Hz

¾¾ms

SYS

¾¾ms

500 kHz

8 January 18, 2000

Functional Description

HT47C20L

Execution flow

The HT47C20L system clock is derived from a 32768Hz crystal oscillator. The system clock is internally divided into four non-overlapping clocks (T1, T2, T3 and T4). One instruction cycle consists of four system clock cycles.

Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruction to ef fectively execute in one cycle. If an instruction changes the program counter, two cycles are re quired to complete the instruction.

Program counter - PC

The 11-bit program counter (PC) controls the sequence in which the instructions stored in the program ROM are executed and its contents specify a maximum of 2048 addresses.

After accessing a program memory word to fetch an instruction code, the contents of the program counter are incremented by one. The program counter then points to the memory word containing the next instruction code.

When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction.

The conditional skip is activated by instruction. Once the condition is met, the next instruction, fetched during the current instruction execu tion, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise pro ceed with the next instruction.

The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination will be within 256 loca

tions.

When a control transfer takes place, an addi

tional dummy cycle is required.

Program memory - ROM

The program memory is used to store the pro gram instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 2048´16 bits, addressed by the program counter and table pointer.

Certain locations in the program memory are reserved for special usage:

Location 000H This area is reserved for the initialization pro-

gram. After chip reset, the program always begins execution at location 000H.

Location 004H This area is reserved for the external inter-

rupt service program. If the INT activated, and the interrupt is enabled and

input pin is

S yste m C lock

Instruction C lo ck

T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4

PC PC+1 PC+2

F e tc h IN S T (P C )

Execute IN S T (P C -1)

F e tc h IN S T (P C + 1 )

Execute IN S T (P C )

F e tc h IN S T (P C + 2 )

Execute IN S T (P C +1)

Execution flow

9 January 18, 2000

HT47C20L

the stack is not full, the program begins exe cution at location 004H.

Location 008H This area is reserved for the time base inter

rupt service program. If time base interrupt resulting from a time base overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 008H.

Location 00CH This area is reserved for the real time clock

interrupt service program. If a real time clock interrupt occurs, and if the interrupt is en abled and the stack is not full, the program begins execution at location 00CH.

Location 010H This area is reserved for the timer/event coun

ter interrupt service program. If timer inter rupt results from a timer/event counter Aor B overflow, and if the interrupt is enabled and the stack is not full, the program begins exe cution at location 010H.

Table location Any location in the ROM space can be used as

look-up tables. The instructions TABRDC [m] (the current page, 1 page=256 words) and TABRDL [m] (the last page) transfer the contents of the lower-order byte to the specified

000H

004H

008H

00C H

010H

n00H

nFFH

7FFH

D evice initialization program

External interrupt subroutine

Tim e B ase Interrupt subroutine

R eal Tim e C lock Interrupt subroutine

Tim er/event C ounter interrupt subroutine

Look-up table (256 w ords)

16 bits

N ote: n ranges from 0 to 7

Progra ROM

Program memory

data memory, and the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the table is well-defined, the higher-order byte of the table word are transferred to the TBLH. The table higher-order byte register (TBLH) is read only. The table pointer (TBLP) is a read/write register (07H), which indicates the table loca-

Mode

*10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0

Program Counter

Initial reset 00000000000

External interrupt 00000000100

Time base interrupt 00000001000

Real time clock interrupt 00000001100

Timer/event counter interrupt 00000010000

Skip PC+2

Loading PCL *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0

Jump, call branch #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0

Return from subroutine S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

Program counter

Note: *10~*0: Program counter bits #10~#0: Instruction code bits

S10~S0: Stack register bits @7~@0: PCL bits

10 January 18, 2000

HT47C20L

tion. Before accessing the table, the location must be placed in TBLP. The TBLH is read only and cannot be restored. If the main rou tine and the ISR (interrupt service routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruc tion used in the ISR. Errors can occur. In other words using the table read instruction in the main routine and the ISR simulta neously should be avoided. However, if the ta ble read instruction has to be applied in both the main routine and the ISR, the interrupt is supposed to be disabled prior to the table read instruction. It will not be enabled until the TBLH has been backed up. All table related instructions need two cycles to complete the operation. These areas may function as nor mal program memory depending upon the re quirements.

Stack register - STACK

This is a special part of the memory which is used to save the contents of the program counter (PC) only. The stack is organized into four levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the stack pointer (SP) and is neither readable nor writeable. At a subroutine call or interrupt acknowledgment, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the program counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack.

If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be

Instruction(s)

TABRDC [m] P10 P9 P8 @7 @6 @5 @4 @3 @2 @1 @0

TABRDL [m] 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0

*10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0

Table location

recorded but the acknowledgment will be inhib ited. When the stack pointer is decremented (by RET or RETI), the interrupt will be serviced.

This feature prevents stack overflow allowing the programmer to use the structure more eas ily. In a similar case, if the stack is full and a

²CALL² is subsequently executed, stack over flow occurs and the first entry will be lost (only the most recent four return addresses are

stored).

Data memory - RAM

The data memory is designed with 83´8 bits. The data memory is divided into two functional groups: special function registers and general purpose data memory (64´8). Most are read/write, but some are read only.

The special function registers include the indirect

addressing register 0 (00H), the memory pointer

register 0 (MP0; 01H), the indirect addressing register 1 (02H), the memory pointer register 1 (MP1;03H), the bank pointer (BP;04H), the accu mulator (ACC;05H), the program counter lower-order byte register (PCL;06H), the table pointer (TBLP;07H), the table higher-order byte register (TBLH;08H), the real time clock control register (RTCC;09H), the status register (STATUS;0AH), the interrupt control register 0 (INTC0;0BH), the I/O registers (PA;12H, PB;14H), the interrupt control register 1 (INTC1;1EH), the timer/event counter A higher order byte register (TMRAH; 20H), the timer/event counter A lower order byte register (TMRAL; 21H), the timer/event counter control register (TMRC; 22H), the timer/event counter B higher order byte register (TMRBH; 23H), the timer/event counter B lower-order byte register (TMRBL; 24H), and the RC oscillator type A/D converter control register (ADCR; 25H). The re

Table Location

Note: *10~*0: Bits of table location @7~@0: Bits of table pointer

P10~P8: Bits of current program counter

11 January 18, 2000

HT47C20L

Indirect A ddressing R egister 0

00H

01H

Indirect A ddressing R egister 1

02H

03H

04H

05H

06H

07H

08H

09H

0AH

0BH

0C H

0D H

0EH

0FH

10H

11H

12H

13H

14H

15H

16H

17H

18H

19H

1AH

1BH

1C H

1D H

1EH

1FH

20H

21H

22H

23H

24H

25H

26H

40H

7FH

RTCC

STATUS

IN T C 0

IN T C 1

TM RA H

TM RA L

TM RC

TM RB H

TM RB L

ADCR

G eneral P urpose

D ata M em ory

(64 B ytes)

MP 0

MP1

ACC

PCL

TBLP

TBLH

Special P urpose D ata M em ory

: U n u s e d

R ead as "00"

maining space before the 40H are reserved for future expanded usage and reading these loca tion will return the result 00H. The general pur pose data memory, addressed from 40H to 7FH, is used for data and control information under in struction command.

All data memory areas can handle arithmetic, logic, increment, decrement and rotate operations. Except for some dedicated bits, each bit in the data memory can be set and reset by the SET [m].i and CLR [m].i instruction, respectively. They are also indirectly accessible through mem ory pointer registers (MP0;01H, MP1;03H).

Indirect addressing register

Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation of [00H] and [02H] ac cess data memory pointed to by MP0 (01H) and MP1 (03H) respectively. Reading location 00H or 02H indirectly will return the result 00H. Writing indirectly results in no operation.

The function of data movement between two in direct addressing registers are not supported. The memory pointer registers, MP0 and MP1, are both 8-bit registers which can be used to access the data memory by combining corresponding indirect addressing registers.

MP0 only can be applied to data memory, while MP1 can be applied to data memory and LCD display memory.

Accumulator

The accumulator is closely related to ALU operations. It is also mapped to location 05H of the data memory and is capable of carrying out im mediate data operations. The data movement be tween two data memory locations must pass through the accumulator.

RAM mapping (bank 0)

12 January 18, 2000

HT47C20L

Arithmetic and logic unit - ALU

This circuit performs 8-bit arithmetic and logic operation. The ALU provides the following functions:

Arithmetic operations (ADD, ADC, SUB, SBC, DAA)

Logic operations (AND, OR, XOR, CPL)

Rotation (RL, RR, RLC, RRC)

Increment and Decrement (INC, DEC)

Branch decision (SZ, SNZ, SIZ, SDZ ....)

The ALU not only saves the results of a data op eration but can change the status register.

should be noted that operations related to the status register may give different results from those intended. The TO and PD flags can only be changed by the watchdog timer overflow, system power-up, clearing the watchdog timer and executing the HALT in struction.

The Z, OV, AC and C flags generally reflect the status of the latest operations.

In addition, on entering the interrupt sequence or executing the subroutine call, the status reg ister will not be automatically pushed onto the

stack. If the contents of status are important and if the subroutine can corrupt the status

Status register - STATUS

This 8-bit register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), over flow flag (OV), power down flag (PD) and watch dog time-out flag (TO). It also records the status information and controls the operation sequence.

With the exception of the TO and PD flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PD flags. In addition it

Interrupts

The HT47C20L provides an external interrupt,

an internal timer/event counter interrupt, an internal time base interrupt, and an internal real time clock interrupt. The interrupt control register 0 (INTC0;0BH) and interrupt control register 1 (INTC1;1EH) both contain the inter rupt control bits to set the enable/disable and interrupt request flags.

Labels Bits Function

C is set if the operation results in a carry during an addition operation or if a bor-

row does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction.

AC is set if the operation results in a carry out of the low nibbles in addition or no

AC 1

borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared.

OV 3

PD 4

TO 5

¾ ¾

Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.

OV is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared.

PD is cleared when either a system power-up or executing the CLR WDT in struction. PD is set by executing the HALT instruction.

TO is cleared by a system power-up or executing the CLR WDT or HALT in struction. TO is set by a WDT time-out.

Undefined, read as ²0²

STATUS register

13 January 18, 2000

HT47C20L

Once an interrupt subroutine is serviced, all other interrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may happen during this interval, but only the interrupt request flag is recorded. If a certain interrupt needs servicing within the service routine, the programmer may set the EMI bit and the corresponding bit of INTC0 or INTC1 al low interrupt nesting. If the stack is full, the in terrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must be prevented from becoming full.

Control the master (global) interrupt (1=enabled; 0=disabled)

Control the external interrupt (1=enabled; 0=disabled)

Control the time base interrupt (1=enabled; 0=disabled)

Control the real time clock interrupt (1=enabled; 0=disabled)

External interrupt request flag (1=active; 0=inactive)

Time base interrupt request flag (1=active; 0=inactive)

Real time clock interrupt request flag (1=active; 0=inactive)

Control the timer/event counter interrupt (1=enabled; 0=disabled)

Internal timer/event counter interrupt request flag (1=active; 0=inactive)

INTC Register

INTC0 (0BH)

INTC1 (1EH)

0 EMI

1 EEI

2 ETBI

3 ERTI

4 EIF

5 TBF

6 RTF

0 ETI

4TF

¾ Unused bit, read as ²0²

¾ Unused bit, read as ²0² ¾ Unused bit, read as ²0² ¾ Unused bit, read as ²0²

All these kinds of interrupt have a wake-up ca pability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a sub routine at specified locations in the program memory. Only the program counter is pushed onto the stack. If the contents of the register and status register (STATUS) is altered by the interrupt service program which corrupts the

desired control sequence, the contents must be

saved first.

14 January 18, 2000

HT47C20L

External interrupt is triggered by a high to low transition of INT request flag (EIF; bit 4 of INTC0) will be set. When the interrupt is enabled, and the stack is not full and the external interrupt is active, a sub routine call to location 04H will occur. The inter rupt request flag (EIF) and EMI bits will be cleared to disable other interrupts.

The internal timer/event counter interrupt is initialized by setting the timer/event counter interrupt request flag (TF; bit 4 of INTC1), caused by a timer A or timer B overflow. When the interrupt is enabled, and the stack is not full and the TF bit is set, a subroutine call to lo cation 10H will occur. The related interrupt re quest flag (TF) will be reset and the EMI bit cleared to disable further interrupts.

The time base interrupt is initialized by setting the time base interrupt request flag (TBF; bit 5 of INTC0), caused by a regular time base sig nal. When the interrupt is enabled, and the stack is not full and the TBF bit is set, a subrou tine call to location 08H will occur. The related interrupt request flag (TBF) will be reset and the EMI bit cleared to disable further inter rupts.

The real time clock interrupt is initialized by setting the real time clock interrupt request flag (RTF; bit 6 of INTC0), caused by a regular real time clock signal. When the interrupt is enabled, and the stack is not full and the RTF bit is set, a subroutine call to location 0CH will occur. The related interrupt request flag (RTF) will be reset and the EMI bit cleared to disable further interrupts.

During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set to 1 (if the stack is not full). To return from the inter rupt subroutine, RET or RETI instruction may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET does not.

and the related interrupt

Interrupts occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are en abled. In the case of simultaneous requests the

following table shows the priority that is ap

plied. These can be masked by resetting the EMI bit.

No. Interrupt Source Priority Vector

a External interrupt 1 04H

b Time base interrupt 2 08H

Real time clock

interrupt

Timer/event counter

interrupt

The external interrupt request flag (EIF), real time clock interrupt request flag (RTF), time base interrupt request flag (TBF), enable exter nal interrupt bit (EEI), enable real time clock in terrupt bit (ERTI), enable time base interrupt bit (ETBI), and enable master interrupt bit (EMI) constitute an interrupt control register 0 (INTC0) which is located at 0BH in the data memory. The timer/event counter interrupt request flag (TF), enable timer/event counter interrupt bit (ETI) on the other hand, constitute an interrupt control register 1 (INTC1) which is located at 1EH in the data memory. EMI, EEI, ETI, ETBI, and ERTI are used to control the enabling/disabling of interrupts. These bits prevent the requested interrupt being serviced. Once the interrupt request flags (RTF, TBF, TF, EIF) are set, they remain in the INTC1 or INTC0 respectively until the interrupts are ser viced or cleared by a software instruction.

It is recommended that a program does not use the ²CALL subroutine² within the interrupt subroutine. Interrupts often occur in an unpre dictable manner or need to be serviced immedi ately in some applications. If only one stack is left, and enabling the interrupt is not well con trolled, the original control sequence will be damaged once the ²CALL subroutine² operates in the interrupt subroutine.

3 0CH

4 10H

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HT47C20L

Oscillator configuration

The HT47C20L provides one 32768Hz crystal oscillator for real time clock and system clock. The 32768Hz crystal oscillator still work at halt mode. The halt mode stop the system clock and T1 and ignores an external signal to conserve power. The real time clock comes from 32768Hz crystal and still works at halt mode.

OSC1

32768H z

OSC2

C rysta l O scillator

fs (still w orks at halt m ode)

S ystem clock (S tops at halt m ode)

T1 (stops at halt m ode)

32768Hz crystal

A 32768Hz crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift needed for the oscillator, no other external components are needed.

Watchdog timer - WDT

The clock source of the WDT (f

) is implemented

by a 32768Hz crystal oscillator. The timer is designed to prevent a software malfunction or sequence jumping to an unknown location with unpredictable results. The watchdog timer can be disabled by mask option. If the watchdog timer is disabled, all the executions related to the WDT result in no operation.

The ²HALT² instruction is executed, WDT still counts and can wake-up from halt mode due to the WDT time-out.

The WDT overflow under normal operation will initialize ²chip reset² and set the status bit TO. Whereas in the halt mode, the overflow will ini tialize a ²warm reset² only the PC and SP are re set to zero. To clear the contents of WDT, three methods are adopted, external reset (a low level to RES

), software instruction, or a HALT instruc

tion. The software instructions are of two sets which include CLR WDT and the other set - CLR WDT1 and CLR WDT2. Of these two types of in struction, only one can be active depending on the mask option -²CLR WDT times selection op tion².Ifthe²CLR WDT² is selected (i.e., CLR WDT times equal one), any execution of the CLR WDT instruction will clear the WDT. In case ²CLR WDT1² and ²CLR WDT2² are chosen (i.e. CLR WDT times equal two), these two instruc tions must be executed to clear the WDT; other wise, the WDT may reset the chip because of the time-out.

The WDT time-out period ranges from

s/2

. The ²CLR WDT² or ²CLR WDT1²

s/2

and ²CLRWDT2² instruction only clear the last two-stage of the WDT.

Multi-function timer

The HT47C20L provides a multi-function timer for the WDT, time base and real time clock but with different time-out periods. The multi-function timer consists of a 7-stage divider and an 8-bit prescaler, with the clock source coming from the 32768Hz. The multi-function timer also provides a fixed frequency signal (f

/8) for the LCD driver circuits,

and a selectable frequency signal (ranges from f

/22to fs/29) for buzzer output by mask option.

32768H z C rystal O SC

D ivider

fs/2f

P rescaler

W D T C lear

CK TRCK T

Tim e-out R eset

15 16

/2 ~ fs/2

Watchdog timer

16 January 18, 2000

HT47C20L

Time base

The time base offers a periodic time-out period to generate a regular internal interrupt. Its time-out period ranges from f

/212to fs/215selected by mask

option. If time base time-out occurs, the related interrupt request flag (TBF; bit 5 of INTC0) is set. But if the interrupt is enabled, and the stack is not full, a subroutine call to location 08H occurs.

When the HALT instruction is executed, the time base still works and can wake up from halt mode. If the TBF is set ²1² before entering the halt mode, the wake up function will be disabled.

Real time clock - RTC

The real time clock is operated in the same manner as the time base that is used to supply a regular internal interrupt. Its time-out period ranges from f

/28to fs/215by software program

ming. Writing data to RT2, RT1 and RT0 (bits 2, 1, 0 of RTCC;09H) yields various time-out periods. If a real time clock time-out occurs, the related interrupt request flag (RTF; bit 6 of INTC0) is set. But if the interrupt is enabled, and the stack is not full, a subroutine call to lo cation 0CH occurs. The real time clock time-out signal can also be applied as a clock source of timer/event counter A, so as to get a longer time-out period.

RT2 RT1 RT0

RTC Clock Divided

Factor

000 2

001 2

010 2

011 2

100 2

101 2

110 2

111 2

Power down operation - HALT

The halt mode is initialized by the HALT in struction and results in the following.

The 32768Hz crystal oscillator will still work but the system clock and T1 will turn off.

The contents of the on-chip RAM and regis ters remain unchanged.

The WDT will be cleared and recount again.

All I/O ports maintain their original status.

The PD flag is set and the TO flag is cleared.

LCD driver is still running (by mask option).

The time base and real time clock will still work.

D ivider

fs/2

Mask Option

Tim e B ase Interrupt

12 15

/2 ~ fs/2

Prescaler

LC D D river

Buzzer

/2 ~ fs/2

fs/8

Time base

RT2 RT1 RT0

fs/2

P rescaler

8 to 1

Mux.

fs/2 ~ fs/2 R eal Tim e C lock Interrupt

D ivider

Real time clock

17 January 18, 2000

+ 38 hidden pages

Holtek Semiconductor Inc HT47C20L Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

General Description

Block Diagram

Pin Assignment

Pad Assignment

Pin Description

Absolute Maximum Ratings

D.C. Characteristics

A.C. Characteristics

Functional Description