Holtek Semiconductor Inc HT47C20L Datasheet

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Features

Operating voltage: 1.2V~2.2V

Eight bidirectional I/O lines

Four input lines

One interrupt input

One 16-bit programmable timer/event

counter with PFD (programmable frequency divider) function On-chip 32768Hz crystal oscillator

Watchdog timer

2K ´ 16 program memory ROM

64 ´ 8 data memory RAM

One real time clock (RTC)

One 8-bit prescaler for real time clock

One buzzer output

One low voltage detector

General Description

The HT47C20L is an 8-bit high performance RISC-like microcontroller. Its single cycle in struction and two-stage pipeline architecture make high speed applications. The device is suited for use in multiple LCD low power appli-

HT47C20L

8-Bit Microcontroller

One low voltage reset circuit

Halt function and wake-up feature reduce

power consumption LCD bias C type

One LCD driver with 20 ´ 2or20´ 3or19´ 4

segments Two channels RC type A/D converter

Four-level subroutine nesting

Bit manipulation instruction

16-bit table read instruction

Up to 122ms instruction cycle with 32768Hz

system clock All instructionsin one or two machine cycles

63 powerful instructions

cations among which are calculators, clock tim ers, games, scales, toys, thermometers,

hygrometers, body thermometers, capacitor scaler, other hand held LCD products, and battery system in particular.

1 January 18, 2000

Block Diagram

HT47C20L

PB0/INT

Program

ROM

Instruction

R egister

Instruction

D ecoder

Tim ing

G enerator

OSC2

OSC1 RES

VDD VSS

D ouble

Voltage

V1 V2 V3

Program

C ounter

ALU

S h ifte r

ACC

COM 0~ COM 2

STACK0 STACK1 STACK2 STACK3

M U X

MUX

LCD Driver

COM 3/ SEG19

In te r ru p t

Circuit

DATA

Memory

STATUS

LC D

Memory

SEG0~ SEG18

IN T C

Tim er A

Tim er B

R eal Tim e C lock

WDT

Tim e B ase

Port B

Port A

M U X

PFD

C onverter

A/D Clock

Type

A/D

32768H z (alw ays on)

PB0/IN T

PB1

PB2/TM R PB3

PA0/BZ PA1/BZ PA2 PA3/PFD PA4~PA7

S ystem C lock T1 RTC Output PB2/TM R

PB3/PFD

IN 0 CS0 RS0 CRT0 RT0 IN 1 CS1 RS1 RT1

2 January 18, 2000

Pin Assignment

HT47C20L

OSC2

OSC1

RES

VDD

PA0/BZ

PA1/BZ

PA2

PA3/PFD

PA4

PA5

PA6

PA7

PB0/INT

PB1

PB2/TM R

PB3

TEST

VSS

20 21 22 23 24 25 26 27 28 29 30 31 32

RT1

61 60 59 58 57 56 55 54 53 5264 63 62

HT47C20L

64 Q FP

RS1

CS1

IN 1

CRT0

RT0

RS0

CS0

IN 0

COM 0

COM 1

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

COM 2

COM 3/SEG19

3 January 18, 2000

Pad Assignment

HT47C20L

RES

PA0/BZ

PA1/BZ

PA2

PA3/PFD

PA4

PA5

PA6

PA7

PB0/IN T

PB1

PB2/TM R

PB3

TEST

VSS

OSC1

RT1

OSC2

VDD

(0 , 0 )

RS1

CS1

IN 1

RT0

CRT0

225023

RS0

CS0

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

COM 3/SEG19

IN 0

COM 0

COM 1

COM 2

* The IC substrate should be connected to VSS in the PCB layout artwork.

4 January 18, 2000

Pin Description

HT47C20L

Pin Name I/O

RES

PA0/BZ PA1/BZ PA2 PA3/PFD PA4~PA7

PB0/INT PB1 PB2/TMR PB3

VSS

V1~V3, C1~C2

SEG19/COM3 COM2~COM0

SEG18~SEG0 O

VDD

OSC2 OSC1

IN0 CS0 RS0 CRT0

RT0

IN1 CS1 RS1 RT1

TEST

I/O

¾¾

I O O O

Mask

Option

Wake-up Pull-high

or None

CMOS or

NMOS

1/2 or 1/3

or 1/4

Duty

Function

Schmitt trigger reset input. Active low.

Bidirectional 8-bit input/output port. The low nibble of the PA can be configured as CMOS output or NMOS output with or without pull-high resistors (mask option). NMOS output can be configured as schmitt trigger input with or without pull-high resistors. Each bit of NMOS output can be configured as wake up input by mask option. Of the eight bits, PA0~PA1 can be set as I/O pins or buzzer outputs by mask option. PA3 can be set as an I/O pin or a PFD output by mask option.

Four-bit schmitt trigger input port. The PB is configured as with pull-high resistors. Of the four bits, PB0 can be set as an input pin or an external interrupt input pin (INT application. While PB2 can be set as an input pin or a timer/event counter input pin by software application.

Negative power supply, GND

Voltage pump

SEG19/COM3 can be set as a segment or a common output driver for LCD panel by mask option. COM2~COM0 are out puts for LCD panel plate.

LCD driver outputs for LCD panel segments

Positive power supply

OSC1 and OSC2 are connected to a 32768Hz crystal for the internal system clock and WDT source.

Oscillation input pin of channel 0 Reference capacitor connection pin of channel 0 Reference resistor connection pin of channel 0 Resistor/capacitor sensor connection pin for measurement of channel 0 Resistor sensor connection pin for measurement of channel 0

Oscillation input pin of channel 1 Reference capacitor connection pin of channel 1 Reference resistor connection pin of channel 1 Resistor sensor connection pin for measurement of channel 1

TEST mode input pin with pull-high resistor. It disconnects in normal operation.

) by software

5 January 18, 2000

Absolute Maximum Ratings

HT47C20L

Supply Voltage..............................-0.3V to 2.5V

Input Voltage.................V

-0.3V to VDD+0.3V

Storage Temperature.................-50°Cto125°C

Operating Temperature ..............-40°Cto85°C

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maxi

mum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged expo sure to extreme conditions may affect device reliability.

D.C. Characteristics

Ta=25°C

Test Conditions

Symbol Parameter

LVD

LVR

DD1

DD2

DD3

Operating Voltage

Low Voltage Detector Voltage

Low Voltage Reset Voltage

Operating Current (LVR Disable, LVD Disable)

Operating Current (LVR Disable, LVD Enable)

Operating Current (LVR Enable, LVD Enable)

Standby Current

STB1

(LVR Disable, LVD Disable, LCD Off)

Standby Current

STB2

(LVR Disable, LVD Enable, LCD On)

Standby Current

STB3

(LVR Enable, LVD Enable, LCD On)

Standby Current

STB4

(LVR Disable, LVD Enable, LCD On)

Standby Current

STB5

(LVR Off, LVD Disable, LCD Off)

Input Low Voltage for I/O Ports 1.5V

Input High Voltage for I/O Ports

Conditions

¾¾

No load, f

1.5V A/D Off, LVD Off

No load, f

1.5V A/D Off, LVD Off

No load, f

1.5V A/D Off, LVD Off

No load, system Halt

1.5V A/D Off, LVD Off

No load, system Halt

1.5V A/D Off, LVD Off

No load, system Halt

1.5V A/D Off, LVD Off

No load, system Halt

1.5V A/D Off, LVD On

=32768Hz

SYS

=32768Hz

SYS

=32768Hz

SYS

No load, system Halt A/D On

1.5

*R=5.1kW, *C=500P

1.5V

Min. Typ. Max. Unit

1.2 1.5 2.2 V

1.1 1.2 1.3 V

1.0 1.1 1.2 V

1.05

915

12 20

610

915

815

270 500

0.45 V

1.5 V

6 January 18, 2000

HT47C20L

Symbol Parameter

IL1

IL2

IH1

OL1

OH1

OL2

OH2

OL3

OH3

OL4

OH4

OL5

OH5

PH1

PH2

Input Low Voltage (RES) 1.5V

Input Low Voltage (INT

, TMR)

Input High Voltage (RES

, INT, TMR)

I/O Port Sink Current 1.5V

I/O Port Source Current 1.5V

Common 0~3 Output Sink Current

Common 0~3 Output Source Current

Segment 0~19 Output Sink Current

Segment 0~19 Output Source Current

Common 0~3 Output Sink Current

Common 0~3 Output Source Current

Segment 0~19 Output Sink Current

Segment 0~19 Output Source Current

RC oscillation Output Sink Current

RC oscillation Output Source Current

Pull-high Resistance of I/O Ports and INT

Pull-high Resistance of TEST 1.5V

Test Conditions

0.5V

0.3V

1.5V

0.8V

1.5V

Conditions

=0.15V

=1.35V

=0.3V (1/2 bias)

=2.7V (1/2 bias)

=0.3V (1/2 bias)

=2.7V (1/2 bias)

=0.45V (1/3 bias)

=4.05V (1/3 bias)

=0.45V (1/3 bias)

=4.05V (1/3 bias)

=0.15V

=1.35V

Min. Typ. Max. Unit

1.2

0.3 0.6

-0.2 -0.4 ¾

120 230

0.75 V

0.45 V

1.5 V

¾mA

-50 -100 ¾mA

30 60

¾mA

-20 -30 ¾mA

120 220

¾mA

-50 -100 ¾mA

30 60

¾mA

-20 -30 ¾mA

2 2.7

-2 -3.1 ¾

100 150 200

10 30 60

Note: *R means the resistance of RC type A/D converter

*C means the capacitance of RC type A/D converter

7 January 18, 2000

HT47C20L

A.C. Characteristics

Symbol Parameter

SYS1

TIMER

RES

SST

INT

RIS

LVD

Note: t

System Clock 1.5V

Timer I/P Frequency (TMR) 1.5V

External Reset Low Pulse Width

System Start-up Timer Period

Interrupt Pulse Width 1.5V

Power Supply Rise Time

Low Voltage Detector Response Time 1.5V

A/D Converter Frequency 1.5V

=1/f

SYS

Test Conditions

Min. Typ. Max. Unit

Conditions

¾¾

¾¾ ¾

Power-up

32768

100

8192

100

¾¾

200

¾¾¾

Ta=25°C

32768 Hz

¾¾ms

SYS

¾¾ms

500 kHz

8 January 18, 2000

Functional Description

HT47C20L

Execution flow

The HT47C20L system clock is derived from a 32768Hz crystal oscillator. The system clock is internally divided into four non-overlapping clocks (T1, T2, T3 and T4). One instruction cycle consists of four system clock cycles.

Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruction to ef fectively execute in one cycle. If an instruction changes the program counter, two cycles are re quired to complete the instruction.

Program counter - PC

The 11-bit program counter (PC) controls the sequence in which the instructions stored in the program ROM are executed and its contents specify a maximum of 2048 addresses.

After accessing a program memory word to fetch an instruction code, the contents of the program counter are incremented by one. The program counter then points to the memory word containing the next instruction code.

When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction.

The conditional skip is activated by instruction. Once the condition is met, the next instruction, fetched during the current instruction execu tion, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise pro ceed with the next instruction.

The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination will be within 256 loca

tions.

When a control transfer takes place, an addi

tional dummy cycle is required.

Program memory - ROM

The program memory is used to store the pro gram instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 2048´16 bits, addressed by the program counter and table pointer.

Certain locations in the program memory are reserved for special usage:

Location 000H This area is reserved for the initialization pro-

gram. After chip reset, the program always begins execution at location 000H.

Location 004H This area is reserved for the external inter-

rupt service program. If the INT activated, and the interrupt is enabled and

input pin is

S yste m C lock

Instruction C lo ck

T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4

PC PC+1 PC+2

F e tc h IN S T (P C )

Execute IN S T (P C -1)

F e tc h IN S T (P C + 1 )

Execute IN S T (P C )

F e tc h IN S T (P C + 2 )

Execute IN S T (P C +1)

Execution flow

9 January 18, 2000

HT47C20L

the stack is not full, the program begins exe cution at location 004H.

Location 008H This area is reserved for the time base inter

rupt service program. If time base interrupt resulting from a time base overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 008H.

Location 00CH This area is reserved for the real time clock

interrupt service program. If a real time clock interrupt occurs, and if the interrupt is en abled and the stack is not full, the program begins execution at location 00CH.

Location 010H This area is reserved for the timer/event coun

ter interrupt service program. If timer inter rupt results from a timer/event counter Aor B overflow, and if the interrupt is enabled and the stack is not full, the program begins exe cution at location 010H.

Table location Any location in the ROM space can be used as

look-up tables. The instructions TABRDC [m] (the current page, 1 page=256 words) and TABRDL [m] (the last page) transfer the contents of the lower-order byte to the specified

000H

004H

008H

00C H

010H

n00H

nFFH

7FFH

D evice initialization program

External interrupt subroutine

Tim e B ase Interrupt subroutine

R eal Tim e C lock Interrupt subroutine

Tim er/event C ounter interrupt subroutine

Look-up table (256 w ords)

16 bits

N ote: n ranges from 0 to 7

Progra ROM

Program memory

data memory, and the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the table is well-defined, the higher-order byte of the table word are transferred to the TBLH. The table higher-order byte register (TBLH) is read only. The table pointer (TBLP) is a read/write register (07H), which indicates the table loca-

Mode

*10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0

Program Counter

Initial reset 00000000000

External interrupt 00000000100

Time base interrupt 00000001000

Real time clock interrupt 00000001100

Timer/event counter interrupt 00000010000

Skip PC+2

Loading PCL *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0

Jump, call branch #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0

Return from subroutine S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

Program counter

Note: *10~*0: Program counter bits #10~#0: Instruction code bits

S10~S0: Stack register bits @7~@0: PCL bits

10 January 18, 2000

HT47C20L

tion. Before accessing the table, the location must be placed in TBLP. The TBLH is read only and cannot be restored. If the main rou tine and the ISR (interrupt service routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruc tion used in the ISR. Errors can occur. In other words using the table read instruction in the main routine and the ISR simulta neously should be avoided. However, if the ta ble read instruction has to be applied in both the main routine and the ISR, the interrupt is supposed to be disabled prior to the table read instruction. It will not be enabled until the TBLH has been backed up. All table related instructions need two cycles to complete the operation. These areas may function as nor mal program memory depending upon the re quirements.

Stack register - STACK

This is a special part of the memory which is used to save the contents of the program counter (PC) only. The stack is organized into four levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the stack pointer (SP) and is neither readable nor writeable. At a subroutine call or interrupt acknowledgment, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the program counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack.

If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be

Instruction(s)

TABRDC [m] P10 P9 P8 @7 @6 @5 @4 @3 @2 @1 @0

TABRDL [m] 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0

*10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0

Table location

recorded but the acknowledgment will be inhib ited. When the stack pointer is decremented (by RET or RETI), the interrupt will be serviced.

This feature prevents stack overflow allowing the programmer to use the structure more eas ily. In a similar case, if the stack is full and a

²CALL² is subsequently executed, stack over flow occurs and the first entry will be lost (only the most recent four return addresses are

stored).

Data memory - RAM

The data memory is designed with 83´8 bits. The data memory is divided into two functional groups: special function registers and general purpose data memory (64´8). Most are read/write, but some are read only.

The special function registers include the indirect

addressing register 0 (00H), the memory pointer

register 0 (MP0; 01H), the indirect addressing register 1 (02H), the memory pointer register 1 (MP1;03H), the bank pointer (BP;04H), the accu mulator (ACC;05H), the program counter lower-order byte register (PCL;06H), the table pointer (TBLP;07H), the table higher-order byte register (TBLH;08H), the real time clock control register (RTCC;09H), the status register (STATUS;0AH), the interrupt control register 0 (INTC0;0BH), the I/O registers (PA;12H, PB;14H), the interrupt control register 1 (INTC1;1EH), the timer/event counter A higher order byte register (TMRAH; 20H), the timer/event counter A lower order byte register (TMRAL; 21H), the timer/event counter control register (TMRC; 22H), the timer/event counter B higher order byte register (TMRBH; 23H), the timer/event counter B lower-order byte register (TMRBL; 24H), and the RC oscillator type A/D converter control register (ADCR; 25H). The re

Table Location

Note: *10~*0: Bits of table location @7~@0: Bits of table pointer

P10~P8: Bits of current program counter

11 January 18, 2000

HT47C20L

Indirect A ddressing R egister 0

00H

01H

Indirect A ddressing R egister 1

02H

03H

04H

05H

06H

07H

08H

09H

0AH

0BH

0C H

0D H

0EH

0FH

10H

11H

12H

13H

14H

15H

16H

17H

18H

19H

1AH

1BH

1C H

1D H

1EH

1FH

20H

21H

22H

23H

24H

25H

26H

40H

7FH

RTCC

STATUS

IN T C 0

IN T C 1

TM RA H

TM RA L

TM RC

TM RB H

TM RB L

ADCR

G eneral P urpose

D ata M em ory

(64 B ytes)

MP 0

MP1

ACC

PCL

TBLP

TBLH

Special P urpose D ata M em ory

: U n u s e d

R ead as "00"

maining space before the 40H are reserved for future expanded usage and reading these loca tion will return the result 00H. The general pur pose data memory, addressed from 40H to 7FH, is used for data and control information under in struction command.

All data memory areas can handle arithmetic, logic, increment, decrement and rotate operations. Except for some dedicated bits, each bit in the data memory can be set and reset by the SET [m].i and CLR [m].i instruction, respectively. They are also indirectly accessible through mem ory pointer registers (MP0;01H, MP1;03H).

Indirect addressing register

Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation of [00H] and [02H] ac cess data memory pointed to by MP0 (01H) and MP1 (03H) respectively. Reading location 00H or 02H indirectly will return the result 00H. Writing indirectly results in no operation.

The function of data movement between two in direct addressing registers are not supported. The memory pointer registers, MP0 and MP1, are both 8-bit registers which can be used to access the data memory by combining corresponding indirect addressing registers.

MP0 only can be applied to data memory, while MP1 can be applied to data memory and LCD display memory.

Accumulator

The accumulator is closely related to ALU operations. It is also mapped to location 05H of the data memory and is capable of carrying out im mediate data operations. The data movement be tween two data memory locations must pass through the accumulator.

RAM mapping (bank 0)

12 January 18, 2000

HT47C20L

Arithmetic and logic unit - ALU

This circuit performs 8-bit arithmetic and logic operation. The ALU provides the following functions:

Arithmetic operations (ADD, ADC, SUB, SBC, DAA)

Logic operations (AND, OR, XOR, CPL)

Rotation (RL, RR, RLC, RRC)

Increment and Decrement (INC, DEC)

Branch decision (SZ, SNZ, SIZ, SDZ ....)

The ALU not only saves the results of a data op eration but can change the status register.

should be noted that operations related to the status register may give different results from those intended. The TO and PD flags can only be changed by the watchdog timer overflow, system power-up, clearing the watchdog timer and executing the HALT in struction.

The Z, OV, AC and C flags generally reflect the status of the latest operations.

In addition, on entering the interrupt sequence or executing the subroutine call, the status reg ister will not be automatically pushed onto the

stack. If the contents of status are important and if the subroutine can corrupt the status

Status register - STATUS

This 8-bit register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), over flow flag (OV), power down flag (PD) and watch dog time-out flag (TO). It also records the status information and controls the operation sequence.

With the exception of the TO and PD flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PD flags. In addition it

Interrupts

The HT47C20L provides an external interrupt,

an internal timer/event counter interrupt, an internal time base interrupt, and an internal real time clock interrupt. The interrupt control register 0 (INTC0;0BH) and interrupt control register 1 (INTC1;1EH) both contain the inter rupt control bits to set the enable/disable and interrupt request flags.

Labels Bits Function

C is set if the operation results in a carry during an addition operation or if a bor-

row does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction.

AC is set if the operation results in a carry out of the low nibbles in addition or no

AC 1

borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared.

OV 3

PD 4

TO 5

¾ ¾

Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.

OV is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared.

PD is cleared when either a system power-up or executing the CLR WDT in struction. PD is set by executing the HALT instruction.

TO is cleared by a system power-up or executing the CLR WDT or HALT in struction. TO is set by a WDT time-out.

Undefined, read as ²0²

STATUS register

13 January 18, 2000

HT47C20L

Once an interrupt subroutine is serviced, all other interrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may happen during this interval, but only the interrupt request flag is recorded. If a certain interrupt needs servicing within the service routine, the programmer may set the EMI bit and the corresponding bit of INTC0 or INTC1 al low interrupt nesting. If the stack is full, the in terrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must be prevented from becoming full.

Control the master (global) interrupt (1=enabled; 0=disabled)

Control the external interrupt (1=enabled; 0=disabled)

Control the time base interrupt (1=enabled; 0=disabled)

Control the real time clock interrupt (1=enabled; 0=disabled)

External interrupt request flag (1=active; 0=inactive)

Time base interrupt request flag (1=active; 0=inactive)

Real time clock interrupt request flag (1=active; 0=inactive)

Control the timer/event counter interrupt (1=enabled; 0=disabled)

Internal timer/event counter interrupt request flag (1=active; 0=inactive)

INTC Register

INTC0 (0BH)

INTC1 (1EH)

0 EMI

1 EEI

2 ETBI

3 ERTI

4 EIF

5 TBF

6 RTF

0 ETI

4TF

¾ Unused bit, read as ²0²

¾ Unused bit, read as ²0² ¾ Unused bit, read as ²0² ¾ Unused bit, read as ²0²

All these kinds of interrupt have a wake-up ca pability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a sub routine at specified locations in the program memory. Only the program counter is pushed onto the stack. If the contents of the register and status register (STATUS) is altered by the interrupt service program which corrupts the

desired control sequence, the contents must be

saved first.

14 January 18, 2000

HT47C20L

External interrupt is triggered by a high to low transition of INT request flag (EIF; bit 4 of INTC0) will be set. When the interrupt is enabled, and the stack is not full and the external interrupt is active, a sub routine call to location 04H will occur. The inter rupt request flag (EIF) and EMI bits will be cleared to disable other interrupts.

The internal timer/event counter interrupt is initialized by setting the timer/event counter interrupt request flag (TF; bit 4 of INTC1), caused by a timer A or timer B overflow. When the interrupt is enabled, and the stack is not full and the TF bit is set, a subroutine call to lo cation 10H will occur. The related interrupt re quest flag (TF) will be reset and the EMI bit cleared to disable further interrupts.

The time base interrupt is initialized by setting the time base interrupt request flag (TBF; bit 5 of INTC0), caused by a regular time base sig nal. When the interrupt is enabled, and the stack is not full and the TBF bit is set, a subrou tine call to location 08H will occur. The related interrupt request flag (TBF) will be reset and the EMI bit cleared to disable further inter rupts.

The real time clock interrupt is initialized by setting the real time clock interrupt request flag (RTF; bit 6 of INTC0), caused by a regular real time clock signal. When the interrupt is enabled, and the stack is not full and the RTF bit is set, a subroutine call to location 0CH will occur. The related interrupt request flag (RTF) will be reset and the EMI bit cleared to disable further interrupts.

During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set to 1 (if the stack is not full). To return from the inter rupt subroutine, RET or RETI instruction may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET does not.

and the related interrupt

Interrupts occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are en abled. In the case of simultaneous requests the

following table shows the priority that is ap

plied. These can be masked by resetting the EMI bit.

No. Interrupt Source Priority Vector

a External interrupt 1 04H

b Time base interrupt 2 08H

Real time clock

interrupt

Timer/event counter

interrupt

The external interrupt request flag (EIF), real time clock interrupt request flag (RTF), time base interrupt request flag (TBF), enable exter nal interrupt bit (EEI), enable real time clock in terrupt bit (ERTI), enable time base interrupt bit (ETBI), and enable master interrupt bit (EMI) constitute an interrupt control register 0 (INTC0) which is located at 0BH in the data memory. The timer/event counter interrupt request flag (TF), enable timer/event counter interrupt bit (ETI) on the other hand, constitute an interrupt control register 1 (INTC1) which is located at 1EH in the data memory. EMI, EEI, ETI, ETBI, and ERTI are used to control the enabling/disabling of interrupts. These bits prevent the requested interrupt being serviced. Once the interrupt request flags (RTF, TBF, TF, EIF) are set, they remain in the INTC1 or INTC0 respectively until the interrupts are ser viced or cleared by a software instruction.

It is recommended that a program does not use the ²CALL subroutine² within the interrupt subroutine. Interrupts often occur in an unpre dictable manner or need to be serviced immedi ately in some applications. If only one stack is left, and enabling the interrupt is not well con trolled, the original control sequence will be damaged once the ²CALL subroutine² operates in the interrupt subroutine.

3 0CH

4 10H

15 January 18, 2000

HT47C20L

Oscillator configuration

The HT47C20L provides one 32768Hz crystal oscillator for real time clock and system clock. The 32768Hz crystal oscillator still work at halt mode. The halt mode stop the system clock and T1 and ignores an external signal to conserve power. The real time clock comes from 32768Hz crystal and still works at halt mode.

OSC1

32768H z

OSC2

C rysta l O scillator

fs (still w orks at halt m ode)

S ystem clock (S tops at halt m ode)

T1 (stops at halt m ode)

32768Hz crystal

A 32768Hz crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift needed for the oscillator, no other external components are needed.

Watchdog timer - WDT

The clock source of the WDT (f

) is implemented

by a 32768Hz crystal oscillator. The timer is designed to prevent a software malfunction or sequence jumping to an unknown location with unpredictable results. The watchdog timer can be disabled by mask option. If the watchdog timer is disabled, all the executions related to the WDT result in no operation.

The ²HALT² instruction is executed, WDT still counts and can wake-up from halt mode due to the WDT time-out.

The WDT overflow under normal operation will initialize ²chip reset² and set the status bit TO. Whereas in the halt mode, the overflow will ini tialize a ²warm reset² only the PC and SP are re set to zero. To clear the contents of WDT, three methods are adopted, external reset (a low level to RES

), software instruction, or a HALT instruc

tion. The software instructions are of two sets which include CLR WDT and the other set - CLR WDT1 and CLR WDT2. Of these two types of in struction, only one can be active depending on the mask option -²CLR WDT times selection op tion².Ifthe²CLR WDT² is selected (i.e., CLR WDT times equal one), any execution of the CLR WDT instruction will clear the WDT. In case ²CLR WDT1² and ²CLR WDT2² are chosen (i.e. CLR WDT times equal two), these two instruc tions must be executed to clear the WDT; other wise, the WDT may reset the chip because of the time-out.

The WDT time-out period ranges from

s/2

. The ²CLR WDT² or ²CLR WDT1²

s/2

and ²CLRWDT2² instruction only clear the last two-stage of the WDT.

Multi-function timer

The HT47C20L provides a multi-function timer for the WDT, time base and real time clock but with different time-out periods. The multi-function timer consists of a 7-stage divider and an 8-bit prescaler, with the clock source coming from the 32768Hz. The multi-function timer also provides a fixed frequency signal (f

/8) for the LCD driver circuits,

and a selectable frequency signal (ranges from f

/22to fs/29) for buzzer output by mask option.

32768H z C rystal O SC

D ivider

fs/2f

P rescaler

W D T C lear

CK TRCK T

Tim e-out R eset

15 16

/2 ~ fs/2

Watchdog timer

16 January 18, 2000

HT47C20L

Time base

The time base offers a periodic time-out period to generate a regular internal interrupt. Its time-out period ranges from f

/212to fs/215selected by mask

option. If time base time-out occurs, the related interrupt request flag (TBF; bit 5 of INTC0) is set. But if the interrupt is enabled, and the stack is not full, a subroutine call to location 08H occurs.

When the HALT instruction is executed, the time base still works and can wake up from halt mode. If the TBF is set ²1² before entering the halt mode, the wake up function will be disabled.

Real time clock - RTC

The real time clock is operated in the same manner as the time base that is used to supply a regular internal interrupt. Its time-out period ranges from f

/28to fs/215by software program

ming. Writing data to RT2, RT1 and RT0 (bits 2, 1, 0 of RTCC;09H) yields various time-out periods. If a real time clock time-out occurs, the related interrupt request flag (RTF; bit 6 of INTC0) is set. But if the interrupt is enabled, and the stack is not full, a subroutine call to lo cation 0CH occurs. The real time clock time-out signal can also be applied as a clock source of timer/event counter A, so as to get a longer time-out period.

RT2 RT1 RT0

RTC Clock Divided

Factor

000 2

001 2

010 2

011 2

100 2

101 2

110 2

111 2

Power down operation - HALT

The halt mode is initialized by the HALT in struction and results in the following.

The 32768Hz crystal oscillator will still work but the system clock and T1 will turn off.

The contents of the on-chip RAM and regis ters remain unchanged.

The WDT will be cleared and recount again.

All I/O ports maintain their original status.

The PD flag is set and the TO flag is cleared.

LCD driver is still running (by mask option).

The time base and real time clock will still work.

D ivider

fs/2

Mask Option

Tim e B ase Interrupt

12 15

/2 ~ fs/2

Prescaler

LC D D river

Buzzer

/2 ~ fs/2

fs/8

Time base

RT2 RT1 RT0

fs/2

P rescaler

8 to 1

Mux.

fs/2 ~ fs/2 R eal Tim e C lock Interrupt

D ivider

Real time clock

17 January 18, 2000

HT47C20L

The system can leave the halt mode by means of an external reset, an interrupt, an external fall ing edge signal on port A or a WDT overflow. An external reset causes a device initialization and the WDT overflow performs a ²warm reset².Ex amining the TO and PD flags, the reason for chip reset can be determined. The PD flag is cleared when system power-up or executing the CLR WDT instruction and is set when the HALT instruction is executed. The TO flag is set if the WDT time-out occurs, and causes a wake-up that only resets the PC and SP, the others main tain their original status.

The port A wake-up and interrupt methods can be considered as a continuation of normal execu tion. Each bit in port A can be independently se lected to wake up the device by mask option. Awakening from an I/O port stimulus, the pro gram will resume execution of the next instruc tion. If awakening from an interrupt, two sequences may happen. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. If the interrupt is enabled and the stack is not full, a regular interrupt response takes place.

If an interrupt request flag is set to ²1² before entering the halt mode the wake-up function of the related interrupt will be disabled.

If the wake-up results from an interrupt acknowledgment, the actual interrupt subroutine execution will be delayed by more than one cycle. However, if the wake-up results in the next instruction execution, the execution will be performed immediately.

To minimize power consumption, all the I/O pins should be carefully managed before entering the halt mode.

Reset

There are three ways in which a reset may occur.

RES reset during normal operation

RES reset during halt mode

WDT time-out reset during normal operation

The LVR is enable and the VDD is lower then V

LVR

The WDT time-out during halt mode is differ ent from other chip reset conditions, since it can perform a warm reset that just resets the PC

and SP leaving the other circuits in their origi

nal state. Some registers remain unchanged during other reset conditions. Most registers

are reset to the ²initial condition² when the re

set conditions are met. By examining the PD and TO flags, the program can distinguish be

tween different ²chip resets².

TO PD RESET Conditions

0 0 System power-up

reset or LVR reset during

RES normal operation

reset or LVR reset

RES wake-up from halt mode

WDT time-out during normal operation

1 1 WDT wake-up from halt mode

Note: ²u² means ²unchanged²

To guarantee that the crystal oscillator has started and stabilized, the SST (system start-up timer) provides an extra delay of 8192 system clock pulses when the system powers up.

18 January 18, 2000

HT47C20L

The functional unit chip reset status are shown below.

PC 000H

Interrupt Disabled

Prescaler, divider Cleared

WDT, real time clock, time base

Clear. After master reset, begin counting

Timer/event counter Off

Input/output ports Input mode

VDD

RES

SST T im e-out

Chip Reset

Points to the top of the stack

SST

Reset circuit

HALT

WDT

RES

OSC1

Pow er-on D etection

RES

Reset timing chart

WDT Tim e-out

Reset

SST

10-bit R ipple

C ounter

External

Reset configuration

W arm R eset

Cold Reset

19 January 18, 2000

HT47C20L

The states of the registers are summarized in the following table:

TMRAH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

TMRAL xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

TMRC 0000 1--- 0000 1--- 0000 1--- 0000 1--- uuuu u---

TMRBH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

TMRBL xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

ADCR 1xxx --00 1xxx --00 1xxx --00 1xxx --00 uuuu --uu

Program

Counter

MP0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

MP1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

TBLP xxxx xxxx uuuu uuuu uuu uuuu uuuu uuuu uuuu uuuu

TBLH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

STATUS 00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu

INTC0 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu

INTC1 ---0 ---0 ---0 ---0 ---0 ---0 ---0 ---0 ---u ---u

RTCC --xx 0111 --xx 0111 --xx 0111 --xx 0111 --uu uuuu

PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu

Reset

(power on)

000H 000H 000H 000H

WDT time-out

(normal

operation)

reset

RES

(normal

operation)

RES

(HALT)

reset

WDT

time-out

(HALT)

000H*

Note:

²*² refers to ²warm reset² ²u² means ²unchanged² ²x² means ²unknown²

20 January 18, 2000

HT47C20L

Timer/event counter

One 16-bit timer/event counter with PFD out put or two channels of RC type A/D converter is implemented in the HT47C20L. The ADC/TM bit (bit 1 of ADCR register) decides whether timer A and timer B are composed of one 16-bit timer/event counter or timer A and timer B are composed of two channels RC type A/D con verter.

The TMRAL, TMRAH, TMRBL, TMRBH com posed of one 16-bit timer/event counter, when ADC/TM

bit is ²0². The TMRBL and TMRBH

are timer/event counter preload registers for lower-order byte and higher-order byte respec tively.

The timer/event counter clock source may come from system clock or T1 (system clock/4) or real time clock time-out signal or external source.

The external clock input allows the user to count external events, count external RC type A/D clock, measure time intervals or pulse widths, or gener ate an accurate time base.

There are six registers related to the timer/event counter operatingmode. TMRAH ([20H]), TMRAL ([21H]), TMRC ([22H]), TMRBH ([23H]), TMRBL ([24H]) and ADCR ([25H]). Writing to TMRBL only writes the data into a low byte buffer, and writing to TMRBH will write the data and the contents of the low byte buffer into the time/event counter preload register (16-bit) simultaneously. The timer/event counter preload register is changed by writing to TMRBH operations and writing to TMRBL will keep the timer/event counter preload register unchanged.

System Clock

R e a l tim e c lo c k o u tp u t

TM R0

A/D Clock

M U X

Reading TMRAH will also latch the TMRAL into the low byte buffer to avoid the false timing

problem. Reading TMRAL returns the contents

of the low byte buffer. In other words, the low byte of the timer/event counter can not be read directly. It must read the TMRAH first to make the low byte contents of timer/event counter be latched into the buffer.

The TMRC is the timer/event counter control register, which defines the timer/event counter

options.

The timer/event counter control register define the operating mode, counting enable or disable and active edge.

Writing to timer B location puts the starting value in the timer/event counter preload regis ter, while reading timer Ayields the contents of the timer/event counter. Timer B is timer/event counter preload register.

The TN0, TN1 and TN2 bits define the opera tion mode. The event count mode is used to

count external events, which means that the clock source comes from an external (TMR) pin. The A/D clock mode is used to count external A/D clock, the RC oscillation mode is decided by ADCR register. The timer mode functions as a normal timer with the clock source coming from the internal selected clock source. Finally, the pulse width measurement mode can be used to count the high or low level duration of the external signal (TMR). The counting is based on the T1 (system clock/4).

In the event count, A/D clock or internal timer mode, once the timer/event counter starts counting, it will count from the current con-

Data Bus

16 bit T im er A

over flow

PFD

TN2 TN1 TN0

TO N

Pulse W idth M easurem ent M ode C ontrol

TN2 TN1 TN0

Timer/event counter

21 January 18, 2000

16 bit T im er B

RELOAD

PA3 Data CTRL

HT47C20L

Label

(TMRC)

TE 3

TON 4

TN0 TN1 TN2

tents in the timer/event counter (TMRAH and TMRAL) to FFFFH. Once overflow occurs, the counter is reloaded from the timer/event coun ter preload register (TMRBH and TMRBL) and generates the corresponding interrupt request flag (TF; bit 4 of INTC1) at the same time.

In the pulse width measurement mode with the TON and TE bits equal to one, once the TMR has received a transient from low to high (or high to low if the TE bit is 0) it will start counting until the TMR returns to the original level and resets the TON. The measured result will remain in the timer/event counter even if the activated transient occurs again. In other words, only one cycle measurement can be done. Until setting the TON, the cycle measurement will function again as long as it receives fur ther transient pulse. Note that in this operation mode, the timer/event counter starts counting not according to the logic level but according to the transient edges. In the case of counter over flow, the counter is reloaded from the timer/event counter preload register and is sues interrupt request just like the other three modes.

To enable the counting operation, the timer On bit (TON; bit 4 of TMRC) should be set to 1. In the pulse width measurement mode, the TON

Bits Function

0~2

Unused bits, read as ²0²

To define the TMR active edge of timer/event counter (0= active on low to high; 1= active on high to low)

To enable/disable timer counting (0= disabled; 1= enabled)

To define the operating mode (TN2, TN1, TN0) 000= Timer mode (system clock) 001= Timer mode (system clock/4) 010= Timer mode (real time clock output)

011= A/D clock mode (RC oscillation decided by ADCR register)

100= Event counter mode (external clock)

101= Pulse width measurement mode (system clock/4) 110= Unused 111= Unused

TMRC register

will automatically be cleared after the mea surement cycle is completed. But in the other three modes, the TON can only be reset by in

structions. The overflow of the timer/event counter is one of the wake-up sources and can also be applied as a PFD (programmable frequency divider) output at PA3 by mask option. No matter what the operation mode is, writing a 0 to ETI can disable the corresponding interrupt service. When the PFD function is selected, executing ²CLR PA.3² instruction to enable the PFD output and executing ²SET PA.3² instruction to disable the PFD output and PA.3 output low level.

In the case of timer/event counter Off condition, writing data to the timer/event counter preload

register also reloads that data to the timer/ event counter. But if the timer/event counter turns On, data written to the timer/event counter preload register is kept only in the timer/event

counter preload register. The timer/event coun ter will still operate until overflow occurs.

When the timer/event counter (reading

TMRAH) is read, the clock will be blocked to avoid errors. As this may results in a counting error, this must be taken into consideration by the programmer.

22 January 18, 2000

HT47C20L

It is strongly recommended to load first the de sired value into TMRBL, TMRBH, TMRAL, and TMRAH registers then turn on the related timer/event counter for proper operation. Because the initial value of TMRBL, TMRBH, TMRAL and TMRAH are unknown.

Example for Timer/event counter mode (disable interrupt):

clr tmrc

clr adcr.1 ; set timer mode

clr intc1.4 ; clear timer/event counter interrupt request flag

mov a, low (65536-1000) ; give timer initial value

mov tmrbl, a ; count 1000 time and then overflow

mov a, high (65536-1000)

mov tmrbh, a

mov a, 00110000b ; timer clock source=T1 and timer on

mov tmrc, a

p10:

clr wdt

snz intcl.4 ; polling timer/event counter interrupt request flag

jmp p10

If the timer/event counter is on, the TMRAH,

TMRAL, TMRBH and TMRBL cannot be read or written to. Only when the timer/event coun ter is off and when the instruction ²MOV² is used could those four registers be read or writ ten to.

clr intcl.4 ; clear timer/event counter interrupt request flag

; program contimue

23 January 18, 2000

HT47C20L

A/D converter

Two channels of RC type A/D converter are im plemented in the HT47C20L. The A/D con verter contains two 16-bit programmable count-up counter and the timer A clock source may come from the system clock, T1 (system clock/4) or real time clock output. The timer B clock source may come from the external RC os cillator. The TMRAL, TMRAH, TMRBL, TMRBH are composed of the A/D converter when ADC/TM

The A/D converter timer B clock source may come from channel 0 (IN0 external clock input mode, RS0~CS0 oscillation, RT0~CS0 oscilla tion, CRT0~CS0 oscillation (CRT0 is a resis tor), or RS0~CRT0 oscillation (CRT0 is a capacitor) or channel 1 (RS1~CS1 oscillation, RT1~CS1 oscillation or IN1 external clock in put). The timer A clock source is from the sys tem clock, T1 or real time clock prescaler clock output decided by TMRC register.

There are six registers related to A/D converter, i.e., TMRAH, TMRAL, TMRC, TMRBH, TMRBL and ADCR. The internal timer clock is input to TMRAH and TMRAL, the A/D clock is input to

bit (bit 1 of ADCR register) is ²1².

Label

(ADCR)

OVB/OVA

ADC/TM

M0 M1 M2 M3

Bits Function

In the RC type A/D converter mode, this bit is used to define the timer/event counter interrupt which comes from timer A overflow or timer B overflow.

(0= timer A overflow; 1= timer B overflow) In the timer/event counter mode, this bit is void.

To define 16-bit timer/event counter or RC type A/D converter is enable.

(0= timer/event counter enable; 1= A/D converter is enable)

2~3

Unused bits, read as ²0²

To define the A/D converter operating mode (M3, M2, M1, M0) 0000= IN0 external clock input mode 0001= RS0~CS0 oscillation (reference resistor and reference capacitor) 0010= RT0~CS0 oscillation (resistor sensor and reference capacitor)

0011= CRT0~CS0 oscillation (resistor sensor and reference capacitor)

0100= RS0~CRT0 oscillation (reference resistor and sensor capacitor)

0101= RS1~CS1 oscillation (reference resistor and reference capacitor)

0110= RT1~CS1 oscillation (resistor sensor and reference capacitor) 0111= IN1 external clock input mode 1XXX= Undefined mode

ADCR register

TMRBH and TMRBL. The OVB/OVA of the ADCR register) decides whether timer A

overflows or timer B overflows, then the TF bit

is set and timer interrupt occurs. When the A/D

converter mode timer A or timer B overflows, the TON bit is reset and stop counting. Writing TMRAH/TMRBH puts the starting value in the timer A/timer B and reading TMRAH/TMRBH

gets the contents of the timer A/timer B. Writ

ing TMRAL/TMRBL only writes the data into a low byte buffer, and writing TMRAH/TMRBH will write the data and the contents of the low byte buffer into the timer A/timer B (16-bit) si multaneously. The timer A/timer B is change by

writing TMRAH/TMRBH operations and writing

TMRAL/TMRBL will keep the timer A/timer B

unchanged.

Reading TMRAH/TMRBH will also latch the

TMRAL/TMRBL into the low byte buffer to

avoid the false timing problem. Reading

TMRAL/TMRBL returns the contents of the low byte buffer. In other word, the low byte of timer A/timer B can not be read directly. It must read the TMRAH/TMRBH first to make the low byte contents of timer A/timer B be latched into the buffer.

bit (bit 0

24 January 18, 2000

S ystem C lock

S ystem C lock/4

RTC Output

Tim er A

TO N

Tim er B

HT47C20L

OVB/OVA=0

In te r ru p t

OVB/OVA=1

Reset TON

S12

S13

TN0

TN1

TN2

Other

N o te : 0 = o ff, 1 = o n

CS0IN 0

S6 S7

CRT0

RS0S8RT0

M3 M20M10M00S4 S5 S60S7 S8 S90S10 S11 S12

000

N ote: 0=off, 1=on

000

111

S10

CS1IN 1

1 000

1 00

00000

S11

RS1

RT1

00000000

S13

000000000

0000000000

RC type A/D converter

25 January 18, 2000

HT47C20L

The bit4~bit7 of ADCR decides which resistor and capacitor compose an oscillation circuit and input to TMRBH and TMRBL.

The TN0, TN1 and TN2 bits of TMRC define the clock source of timer A. It is suggested that the clock source of timer Ause the system clock, instruction clock or real time clock prescaler clock.

The TON bit (bit 4 of TMRC) is set ²1², the timer A and timer B will start counting until

Example for RC type AD converter mode (Timer A overflow):

clr tmrc

clr adcr.1 ; set timer mode

clr intc1.4 ; clear timer/event counter interrupt request flag

mov a, low (65536-1000) ; give timer A initial value

mov tmrbl, a ; count 1000 time and then overflow

mov a, high (65536-1000)

mov tmrbh, a

mov a, 00010010b ; RS0~CS0; set RC type ADC mode; set Timer A overflow

mov adcr,a

mov a, 00h ; give timer B initial value

mov tmrbl, a

mov a, 00h

mov tmrbh, a

timer A or timer B overflows, the timer/event counter generates the interrupt request flag (TF ; bit 4 of INTC1) and the timer A and timer B stop counting and reset the TON bit to ²0² at the same time.

If the TON bit is ²1², the TMRAH, TMRAL, TMRBH and TMRBL cannot be read or written to. Only when the timer/event counter is off and when the instruction ²MOV² is used could those four registers be read or written to.

mov a, 00110000b ; timer A clock source=T1 and timer on

mov tmrc, a

p10:

clr wdt

snz intcl.4 ; polling timer/event counter interrupt request flag

jmp p10

clr intcl.4 ; clear timer/event counter interrupt request flag

; program continue

26 January 18, 2000

HT47C20L

Example for RC type AD converter mode (Timer B overflow):

clr tmrc

clr adcr.1 ; set timer mode

clr intc1.4 ; clear timer/event counter interrupt request flag

mov a, 00h ; give timer A initial value

mov tmrbl, a

mov a, 00h

mov tmrbh, a

mov a, 00010011b ; RS0~CS0; set RC type ADC mode; set Timer B overflow

mov adcr,a

mov a, low (65536-1000) ; give timer B initial value

mov tmrbl, a ; count 1000 time and then overflow

mov a, high (65536-1000)

mov tmrbh, a

mov a, 00110000b ; timer A clock source=T1 and timer on

mov tmrc, a

p10:

clr wdt

snz intcl.4 ; polling timer/event counter interrupt request flag

jmp p10

clr intcl.4 ; clear timer/event counter interrupt request flag

; program continue

27 January 18, 2000

HT47C20L

Input/output ports

There are 8-bit bidirectional input/output port and 4-bit input port in the HT47C20L, labeled PA and PB which are mapped to the data mem ory of [12H] and [14H] respectively. The high nibble of the PAis NMOS output and input with pull-high resistors. The low nibble of the PA can be used for input/output or output operation by selecting NMOS or CMOS output by mask op tion. Each bit on the PA can be configured as a wake-up input and the low nibble of the PAwith or without pull-high resistors by mask option. PB can only be used for input operation, and each bit on the port can be configured with pull high resistor. Both are for the input operation, these ports are non-latched, that is, the inputs should be ready at the T2 rising edge of the in struction ²MOV A, [m]² (m=12H or 14H). For PA output operation, all data are latched and remain unchanged until the output latch is re written.

WEAK Pull-up

Data Bus

C hip R eset

DCKQ

B Z O p tio n

M U X

Mask

Option

When the structures of PA are open drain NMOS type, it should be noted that, before reading data from the pads a ²1² should be written to the re lated bits to disable the NMOS device. That is

done first before executing the instruction ²MOV A, 0FFH² and ²MOV [12H], A² to disable the re lated NMOS device, and then ²MOV A, [12H]² to get a stable data.

After chip reset, these input lines remain at a high level or are left floating (by mask option).

Some instructions first input data and then fol low the output operations. For example, ²SET [m].i², ²CLR [m].i², ²CPL [m]², ²CPLA [m]² read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or to the accumula

tor. Each bit of the PA output latches can not use

these instruction, which may change the input lines to output lines (when the input lines are at

low level).

PA0/BZ

C hip R eset

Data Bus

DCKQ

B Z O p tio n

M U X

Mask

Option

WEAK Pull-up

PA1/B

BZ S ignal

R ead P ath

System W ake-up

M U X

M ask O p tion

R ead P ath

System W ake-up

PA0/BZ, PA1/BZ input/output lines

28 January 18, 2000

M U X

M ask O p tion

HT47C20L

Data Bus

C hip R eset

BZ S ignal

R ead P ath

System W ake-up

DCKQ

B Z O p tio n

M U X

M ask O p tion

Mask

Option

WEAK Pull-up

PA0/BZ

C hip R eset

Data Bus

R ead P ath

System W ake-up

DCKQ

BZ O ption

M U X

M ask O p tion

Mask

Option

WEAK Pull-up

PA1/B

PA3/PFD input/output line

WEAK Pull-up

Data Bus

Write

C hip R eset

PA4~PA7

R ead D ata

Data Bus

System W ake-up

PB input lines

WEAK Pull-up

PB0~PB3

R e a d I/O

M a sk O ption

PA2 input/output line

Data Bus

Write

C hip R eset

R e a d I/O

System W ake-up

PA4~PA7 input/output lines

29 January 18, 2000

M a sk O ption

Mask

Option

WEAK Pull-up

M a sk O ptio

PA2

COM

41H 42H 43H 51H 52H 53H

40H

HT47C20L

Bit

SEGM ENT

0 1 2 3 17 18 19

Display memory (bank 1)

LCD display memory

The HT47C20L provides an area of embedded data memory for LCD display. The LCD display memory is designed into 20´4 bits. If the LCD selected 19´4 segments output, the 53H of the LCD display memory can not be accessed. This area is located from 40H to 53H of the RAM at Bank 1. Bank pointer (BP; located at 04H of the data memory) is the switch between the gen eral data memory and the LCD display memory. When the BP is set ²1² any data written into 40H~53H will effect the LCD display (indirect addressing mode using MP1). When the BP is cleared ²0², any data written into 40H~53H has to access the general purpose data memory. The LCD display memory can be read and written only by indirect addressing mode using MP1. When data is written into the display data area, it is automatically read by the LCD driver which then generates the corresponding LCD driving signals. To turn the display On or Off, a ²1²or a ²0² is written to the corresponding bit of the display memory, respectively.

The figure illustrates the mapping between the display memory and LCD pattern for the HT47C20L.

LCD driver output

The output number of the HT47C20L LCD driver can be 20´2or20´3or19´4 by mask option (i.e.1/ 2duty, 1/3 duty or 1/4 duty).

The bias type LCD driver is ²C² type. If the 1/2 duty or 1/3 duty type is selected, the 1/2 bias type is selected. If the 1/4 duty type is selected, the 1/3 bias type is selected. A capacitor has to

be connected between C1 and C2. The two kinds

of the configurations of V1, V2 and V3 pins are as follows:

C1 C2

V3 V

V1, V2, V3 application diagram

30 January 18, 2000

HT47C20L

D urin g a R eset P ulse:

COM 0,CO M 1,COM2

All LC D driver outputs

Norm al O peration M ode :

COM 0

COM 1

COM 2

LC D segm ents on C O M 0,1,2 sides being unlit

O nly LC D segm ents on C O M 0 side being lit

O nly LC D segm ents on C O M 1 side being lit

O nly LC D segm ents on C O M 2 side being lit

LC D segm ents on C O M 0,1 sides being lit

LC D segm ents on C O M 0,2 sides being lit

LC D segm ents on C O M 1,2 sides being lit

LC D segm ents on C O M 0,1,2 sides being lit

H a lt M o d e :

COM 0,CO M 1,COM2

All LC D driver outputs

2 V D D VDD VSS

2 V D D VDD VSS 2 V D D VDD VSS 2 V D D VDD VSS 2 V D D VDD VSS 2 V D D VDD VSS 2 V D D VDD VSS 2 V D D VDD VSS

2 V D D VDD VSS 2 V D D VDD VSS 2 V D D VDD VSS 2 V D D VDD VSS

2 V D D VDD VSS 2 V D D VDD

VSS

LCD driver output (1/3 duty, 1/2 bias)

31 January 18, 2000

3 V D D

2 V D D

HT47C20L

COM 0

COM 1

COM 2

COM 3

LC D segm ents O N C O M 2 side lighted

VDD

VSS

3 V D D

2 V D D

VDD

VSS

3 V D D

2 V D D

VDD

VSS

3 V D D

2 V D D

VDD

VSS

3 V D D

2 V D D

VDD

VSS

LCD driver output (1/4 duty, 1/3 bias)

32 January 18, 2000

HT47C20L

Voltage low detector

The HT47C20L provides a voltage low detector for battery system application. If the battery voltage is lower than the specified value, the battery low flag (BLF; bit 5 of RTCC) is set. The specified value is 1.2V±0.1V. The voltage low detector circuit can be turn On or Off by writing a ²1² or a ²0² to BON (bit 3 of RTCC register). A delay time of 1ms is required to monitor the BLF after setting the BON bit. The BLF is in valid when the BON is cleared as ²0². The volt age low detector can be disabled by mask option.

Buzzer

HT47C20L provides a pair of buzzer output BZ and BZ

, which share pins with PA0 and PA1 re spectively, determined by mask option. Its out put frequency can also be selected by mask option.

When the buzzer function is selected, setting PA.0 and PA.1 ²0² simultaneously will enable the buzzer output and setting PA.0 ²1² will dis able the buzzer output and setting PA.0 ²0² and PA.1 ²1² will only enable the BZ output and disable the BZ

output.

PA1 PA0 Function

(CLR PA.1)0(CLR PA.0)

(SET PA.1)0(CLR PA.0)

Programmable frequency divider - PFD

The PFD output shares pin with PA3 as deter mined by mask option.

When the PFD option is selected, setting PA3 ²0² will enable the PFD output and setting PA3

²1² will disable the PFD output and PA3 output

at low level.

PA3 Function

0 (CLR PA.3) PA3= PFD Output

1 (SET PA.3) PA3= 0

PFD output frequency= 1

21timer overflow period

(SET PA.0)

Buzzer enable

PA0= BZ PA1= BZ

PA0= BZ PA1= 0

PA0= 0 PA1= 0

0 1 2

3 BON R/W 0

RTCC

(09H)

Note: ²X² means ²invalid²

5 BLF R X

6, 7

RT0 RT1 RT2

¾¾¾Undefined bit, read as ²unknown²

¾¾¾Unused bits, read as ²0²

R/W

8 to 1 multiplexer control inputs to select the

real time clock prescaler output

Voltage low detector enable/disable control bit

²0² indicates voltage detector is disabled ²1² indicates voltage detector is enabled

Battery low flag

²0² indicates that the voltage is not low ²1² indicates that the voltage is low

RTCC Register

33 January 18, 2000

HT47C20L

Low voltage reset - LVR

The low voltage reset circuit is used to monitor the power supply of the device. If the power sup ply voltage of the device is lower than 1.1V±0.1V, the device will automatically reset internally. It is enabled or disabled by mask option.

The LVR includes the following specification:

The low voltage (lower than 1.1V±0.1V) must

be maintained for over 1ms. If the low voltage state does not exceed 1ms, the LVR will ignore it and does not perform the reset function.

The LVR uses the ²OR² function with the ex ternal RES

During HALT mode, if the LVR occurs, the

signal to perform chip reset.

device will wake-up and the PD flag will be set as ²1², the same as the RES

reset.

Mask option

The following shows many kinds of mask options in the HT47C20L. All these options should be defined in order to ensure proper system functioning.

No. Mask Option

1 WDT enable/disable selection. WDT can be enabled or disabled by mask option.

CLR WDT times selection. This option defines how to clear the WDT by instruction. One

time means that the ²CLR WDT² can clear the WDT. ²Two times² means that only if both of the ²CLR WDT1² and ²CLR WDT2² have been executed, then WDT can be cleared.

Time base time-out period selection. The time base time-out period ranges from f

/215. ²fs² stands for the 32768Hz frequency.

Buzzer output frequency selection. There are eight types of frequency signals for the buzzer

output: f

/22~fs/29. ²fs² stands for the 32768Hz.

/212to

Wake-up selection. This option defines the wake-up function activity. External I/O pins (PA

NMOS output only) all have the capability to wake-up the chip from a halt mode by a following edge.

Pull high selection. This option is to decide whether the pull high resistance is viable or not

on the low nibble of the PA.

PA CMOS or NMOS selection. The structure of the low nibble of the PA can be selected as CMOS or NMOS. When CMOS is

selected, the related pins can only be used for output operations. When NMOS is selected, the related pins can be used for input or output operations.

I/O pins share with other function selection.

PA0/BZ, PA1/BZ

: PA0 and PA1 can be set as I/O pins or buzzer outputs.

PA3/PFD: PA3 can be set as I/O pins or PFD output.

LCD common selection. There are three types of selection: 2 common (1/2 duty, 1/2 bias) 3 common (1/3 duty, 1/2 bias) or 4 common (1/4 duty, 1/3 bias). If the 4 common is selected, the

segment output pin ²SEG19/COM3² will be set as a common output ²COM3².

The low voltage reset and the low voltage detector enable or disable selection. There are three types of selection. The low voltage reset and the voltage detector are both

enabled or both disabled or the low voltage reset is disabled but the voltage low detector is enabled.

LCD on or LCD off at the halt mode selection.

The LCD can be enable or disable at the halt mode by mask option.

34 January 18, 2000

Application Circuits

HT47C20L

32768H z

OSC1

OSC2

RES

IN T

TM R

SEG0~18

COM 0~3

IN 0

CS0

CRT0

RT0

RS0

IN 1

CS1

RS1

RT1

PA0~PA7

PB0~PB3

LC D

Panel

R or C

HT47C20L

35 January 18, 2000

HT47C20L

Instruction Set Summary

Mnemonic Description Flag Affected

Arithmetic

ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m]

DAA [m]

Logic Operation

AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m]

Increment & Decrement

INCA [m] INC [m] DECA [m] DEC [m]

Rotate

RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m]

Add data memory to ACC Add ACC to data memory Add immediate data to ACC Add data memory to ACC with carry Add ACC to register with carry Subtract immediate data from ACC Subtract data memory from ACC Subtract data memory from ACC with result in data memory Subtract data memory from ACC with carry Subtract data memory from ACC with carry and result in data memory Decimal adjust ACC for addition with result in data memory

AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC Complement data memory Complement data memory with result in ACC

Increment data memory with result in ACC Increment data memory Decrement data memory with result in ACC Decrement data memory

Rotate data memory right with result in ACC Rotate data memory right Rotate data memory right through carry with result in ACC Rotate data memory right through carry Rotate data memory left with result in ACC Rotate data memory left Rotate data memory left through carry with result in ACC Rotate data memory left through carry

Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV

None None

Z Z Z Z Z Z Z Z Z Z Z

Z Z Z Z

C C

36 January 18, 2000

HT47C20L

Mnemonic Description Flag Affected

Data Move

MOV A,[m] MOV [m],A MOV A,x

Bit Operation

CLR [m].i SET [m].i

Branch

JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI

Table Read

TABRDC [m] TABRDL [m]

Miscellaneous

NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT

Move data memory to ACC Move ACC to data memory Move immediate data to ACC

Clear bit of data memory Set bit of data memory

Jump unconditional Skip if data memory is zero Skip if data memory is zero with data movement to ACC Skip if bit i of data memory is zero Skip if bit i of data memory is not zero Skip if increment data memory is zero Skip if decrement data memory is zero Skip if increment data memory is zero with result in ACC Skip if decrement data memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt

Read ROM code (current page) to data memory and TBLH Read ROM code (last page) to data memory and TBLH

No operation Clear data memory Set data memory Clear Watchdog timer Pre-clear Watchdog timer Pre-clear Watchdog timer Swap nibbles of data memory Swap nibbles of data memory with result in ACC Enter power down mode

None None None

None None

None None None None None None None None None None None None None

None None

None None None

TO, PD TO*, PD* TO*, PD*

None None

TO, PD

Note: x: 8 bits immediate data

m: 7 bits data memory address A: accumulator i= 0~7 number of bits addr: 11 bits program memory address

Ö: Flag is affected

-: Flag is not affected

*: Flag may be affected by the execution status

37 January 18, 2000

HT47C20L

Instruction Definition

ADC A,[m] Add data memory and carry to accumulator

Description The contents of the specified data memory, accumulator and the carry

flag are added simultaneously, leaving the result in the accumulator.

Operation

Affected flag(s)

ADCM A,[m] Add accumulator and carry to data memory

Description The contents of the specified data memory, accumulator and the carry

Operation

Affected flag(s)

ACC ¬ ACC+[m]+C

TC2 TC1 TO PD OV Z AC C

¾¾¾¾ÖÖÖÖ

flag are added simultaneously, leaving the result in the specified data memory.

[m] ¬ ACC+[m]+C

TC2 TC1 TO PD OV Z AC C

¾¾¾¾ÖÖÖÖ

ADD A,[m] Add data memory to accumulator

Description The contents of the specified data memory and the accumulator are

added. The result is stored in the accumulator.

Operation

Affected flag(s)

ADD A,x Add immediate data to accumulator

Description The contents of the accumulator and the specified data are added, leav

Operation

Affected flag(s)

ACC ¬ ACC+[m]

TC2 TC1 TO PD OV Z AC C

¾¾¾¾ÖÖÖÖ

ing the result in the accumulator. ACC ¬ ACC+x

TC2 TC1 TO PD OV Z AC C

¾¾¾¾ÖÖÖÖ

38 January 18, 2000

HT47C20L

ADDM A,[m] Add accumulator to data memory

Description The contents of the specified data memory and the accumulator are

added. The result is stored in the data memory.

Operation

Affected flag(s)

AND A,[m] Logical AND accumulator with data memory

Description Data in the accumulator and the specified data memory performs a

Operation

Affected flag(s)

AND A,x Logical AND immediate data to accumulator

Description Data in the accumulator and the specified data performs a bitwise logi

Operation

Affected flag(s)

[m] ¬ ACC+[m]

TC2 TC1 TO PD OV Z AC C

¾¾¾¾ÖÖÖÖ

bitwise logical_AND operation. The result is stored in the accumulator. ACC ¬ ACC ²AND² [m]

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾Ö¾¾

cal_AND operation. The result is stored in the accumulator. ACC ¬ ACC ²AND² x

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾Ö¾¾

ANDM A,[m] Logical AND data memory with accumulator

Description Data in the specified data memory and the accumulator performs a

bitwise logical_AND operation. The result is stored in the data memory.

Operation

Affected flag(s)

[m] ¬ ACC ²AND² [m]

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾Ö¾¾

39 January 18, 2000

HT47C20L

CALL addr Subroutine call

Description The instruction unconditionally calls a subroutine located at the indi

cated address. The program counter increments once to obtain the ad dress of the next instruction, and pushes this onto the stack. The indicated address is then loaded. Program execution continues with the instruction at this address.

Operation

Affected flag(s)

CLR [m] Clear data memory

Description The contents of the specified data memory are cleared to zero.

Operation

Affected flag(s)

CLR [m].i Clear bit of data memory

Description The bit i of the specified data memory is cleared to zero.

Operation

Affected flag(s)

Stack ¬ PC+1 PC ¬ addr

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

[m] ¬ 00H

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

[m].i ¬ 0

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

CLR WDT Clear watchdog timer

Description The WDT is cleared. The power down bit (PD) and time-out bit (TO) are

cleared.

Operation

Affected flag(s)

WDT last two bits ¬ 00H PD and TO ¬ 0

TC2 TC1 TO PD OV Z AC C

¾¾

¾¾¾¾

40 January 18, 2000

HT47C20L

CLR WDT1 Preclear watchdog timer

Description The PD, TO flags and WDT are cleared, if the other preclear WDT in

struction had been executed. Only execution of this instruction without the other preclear instruction sets the indicating flag which implies that this instruction was executed and the PD and TO flags remain un changed.

Operation

Affected flag(s)

CLR WDT2 Preclear watchdog timer

Description The PD, TO flags and WDT are cleared, if the other preclear WDT in

Operation

Affected flag(s)

WDT last two bits ¬ 00H* PD&TO¬ 0*

TC2 TC1 TO PD OV Z AC C

¾¾

WDT last two bits ¬ 00H* PD&TO¬ 0*

TC2 TC1 TO PD OV Z AC C

¾¾

0* 0*

¾¾¾¾

CPL [m] Complement data memory

Description Each bit of the specified data memory is logically complemented (1 s

complement). Bits which previously contain a one are changed to zero and vice-versa.

Operation

Affected flag(s)

[m]¬ [m

TC2 TC1 TO PD OV Z AC C

]

¾¾¾¾¾Ö¾¾

41 January 18, 2000

HT47C20L

CPLA [m] Complement data memory-place result in accumulator

Description Each bit of the specified data memory is logically complemented (1 s

complement). Bits which previously contained a one are changed to zero and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remains unchanged.

Operation

Affected flag(s)

DAA [m] Decimal-Adjust accumulator for addition

Description The accumulator value is adjusted to the BCD (Binary Code Decimal)

Operation If (ACC.3~ACC.0) >9 or AC=1

Affected flag(s)

ACC ¬ [m

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾Ö¾¾

code. The accumulator is divided into two nibbles. Each nibble is ad justed to the BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored in the data memory and only the carry flag (C) may be affected.

then ([m].3~[m].0) ¬ (ACC.3~ACC.0)+6, AC1=AC else ([m].3~[m].0) ¬ (ACC.3~ACC.0), AC1=0 If (ACC.7~ACC.4)+AC1 >9 or C=1 then ([m].7~[m].4) ¬ (ACC.7~ACC.4)+6+AC1, C=1 else ([m].7~[m].4) ¬ (ACC.7~ACC.4)+AC1, C=C

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾ Ö

]

DEC [m] Decrement data memory

Description Data in the specified data memory is decremented by one.

Operation

Affected flag(s)

[m] ¬ [m]-1

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾Ö¾¾

42 January 18, 2000

HT47C20L

DECA [m] Decrement data memory and place result in accumulator

Description Data in the specified data memory is decremented by one, leaving the re

sult in the accumulator. The contents of the data memory remain un changed.

Operation

Affected flag(s)

HALT Enter power down mode

Description This instruction stops program execution and turn off the system clock.

Operation

Affected flag(s)

ACC ¬ [m]-1

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾Ö¾¾

The contents of the RAM and registers are retained. The WDT is cleared. The power down bit (PD) is set and the WDT time-out bit (TO) is cleared.

PC ¬ PC+1 PD ¬ 1 TO ¬ 0

TC2 TC1 TO PD OV Z AC C

¾¾

¾¾¾¾

INC [m] Increment data memory

Description Data in the specified data memory is incremented by one.

Operation

Affected flag(s)

INCA [m] Increment data memory and place result in accumulator

Description Data in the specified data memory is incremented by one, leaving the re-

Operation

Affected flag(s)

[m] ¬ [m]+1

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾Ö¾¾

sult in the accumulator. The contents of the data memory remain un changed.

ACC ¬ [m]+1

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾Ö¾¾

43 January 18, 2000

HT47C20L

JMP addr Direct Jump

Description Bits 0~10 of the program counter are unconditionally replaced with the

directly-specified address, and control is passed to this destination.

Operation

Affected flag(s)

MOV A,[m] Move data memory to accumulator

Description The contents of the specified data memory is copied to the accumulator.

Operation

Affected flag(s)

MOV A,x Move immediate data to accumulator

Description The 8-bit data specified by the code is loaded into the accumulator.

Operation

Affected flag(s)

PC ¬ addr

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

ACC ¬ [m]

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

ACC ¬ x

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

MOV [m],A Move accumulator to data memory

Description The contents of the accumulator is copied to the specified data memory

(one of the data memories).

Operation

Affected flag(s)

NOP No operation

Description No operation is performed. Execution continues with the next instruc

Operation

Affected flag(s)

[m] ¬ ACC

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

tion. PC ¬ PC+1

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

44 January 18, 2000

HT47C20L

OR A,[m] Logical OR accumulator with data memory

Description Data in the accumulator and the specified data memory (one of the data

memories) performs a bitwise logical_OR operation. The result is stored in the accumulator.

Operation

Affected flag(s)

OR A,x Logical OR immediate data to accumulator

Description Data in the accumulator and the specified data performs a bitwise logi

Operation

Affected flag(s)

ORM A,[m] Logical OR data memory with accumulator

Description Data in the data memory (one of the data memories) and the accumula

Operation

Affected flag(s)

ACC ¬ ACC ²OR² [m]

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾Ö¾¾

cal_OR operation. The result is stored in the accumulator. ACC ¬ ACC ²OR² x

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾Ö¾¾

tor performs a bitwise logical_OR operation. The result is stored in the data memory.

[m] ¬ ACC ²OR² [m]

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾Ö¾¾

RET Return from subroutine

Description The program counter is restored from the stack. This is a two-cycle in-

struction.

Operation

Affected flag(s)

PC ¬ Stack

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

45 January 18, 2000

HT47C20L

RET A,x Return and place immediate data in accumulator

Description The program counter is restored from the stack and the accumulator

loaded with the specified 8-bit immediate data.

Operation

Affected flag(s)

RETI Return from interrupt

Description The program counter is restored from the stack, and interrupts enabled

Operation

Affected flag(s)

RL [m] Rotate data memory left

Description The contents of the specified data memory is rotated left one bit with bit

Operation

Affected flag(s)

PC ¬ Stack ACC ¬ x

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

by setting the EMI bit. EMI is the enable master (global) interrupt bit (bit 0; register INTC).

PC ¬ Stack EMI ¬ 1

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

7 rotated into bit 0. [m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)

[m].0 ¬ [m].7

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

RLA [m] Rotate data memory left and place result in accumulator

Description Data in the specified data memory is rotated left one bit with bit 7 ro

tated into bit 0, leaving the rotated result in the accumulator. The con tents of the data memory remain unchanged.

Operation

Affected flag(s)

ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 ¬ [m].7

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

46 January 18, 2000

HT47C20L

RLC [m] Rotate data memory left through carry

Description The contents of the specified data memory and the carry flag are together

rotated left one bit. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position.

Operation

Affected flag(s)

RLCA [m] Rotate left through carry and place result in accumulator

Description Data in the specified data memory and the carry flag are together ro

Operation

Affected flag(s)

[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 ¬ C C ¬ [m].7

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾ Ö

tated left one bit. Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the data memory remain unchanged.

ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 ¬ C C ¬ [m].7

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾ Ö

RR [m] Rotate data memory right

Description The contents of the specified data memory are rotated right one bit with

bit 0 rotated to bit 7.

Operation

Affected flag(s)

[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 ¬ [m].0

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

47 January 18, 2000

HT47C20L

RRA [m] Rotate right and place result in accumulator

Description Data in the specified data memory is rotated right one bit with bit 0 ro

tated into bit 7, leaving the rotated result in the accumulator. The con tents of the data memory remain unchanged.

Operation

Affected flag(s)

RRC [m] Rotate data memory right through carry

Description The contents of the specified data memory and the carry flag are together

Operation

Affected flag(s)

ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 ¬ [m].0

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

rotated right one bit. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.

[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 ¬ C C ¬ [m].0

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾ Ö

RRCA [m] Rotate right through carry and place result in accumulator

Description Data of the specified data memory and the carry flag are together rotated

right one bit. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged.

Operation

Affected flag(s)

ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 ¬ C C ¬ [m].0

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾ Ö

48 January 18, 2000

HT47C20L

SBC A,[m] Subtract data memory and carry from accumulator

Description The contents of the specified data memory and the complement of the

carry flag are together subtracted from the accumulator, leaving the re sult in the accumulator.

Operation

Affected flag(s)

SBCM A,[m] Subtract data memory and carry from accumulator

Description The contents of the specified data memory and the complement of the

Operation

Affected flag(s)

SDZ [m] Skip if decrement data memory is zero

Description The contents of the specified data memory are decremented by one. If the

Operation

Affected flag(s)

ACC ¬ ACC+[m

TC2 TC1 TO PD OV Z AC C

¾¾¾¾ÖÖÖÖ

carry flag are together subtracted from the accumulator, leaving the re sult in the data memory.

[m] ¬ ACC+[m

TC2 TC1 TO PD OV Z AC C

¾¾¾

result is zero, the next instruction is skipped. If the result is zero, the fol lowing instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaced to get the proper instruction. This makes a 2-cycle instruction. Otherwise proceed with the next instruction.

Skip if ([m]-1)=0, [m] ¬ ([m]-1)

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

]+C

ÖÖÖÖ

49 January 18, 2000

HT47C20L

SDZA [m] Decrement data memory and place result in ACC, skip if zero

Description The contents of the specified data memory are decremented by one. If the

result is zero, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is zero ,the following instruction, fetched during the current instruction ex ecution, is discarded and a dummy cycle is replaced to get the proper in struction, that makes a 2-cycle instruction. Otherwise proceed with the next instruction.

Operation

Affected flag(s)

SET [m] Set data memory

Description Each bit of the specified data memory is set to one.

Operation

Affected flag(s)

Skip if ([m]-1)=0, ACC ¬ ([m]-1)

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

[m] ¬ FFH

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

SET [m].i Set bit of data memory

Description Bit i of the specified data memory is set to one.

Operation

Affected flag(s)

SIZ [m] Skip if increment data memory is zero

Description The contents of the specified data memory is incremented by one. If the

Operation

Affected flag(s)

[m].i ¬ 1

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

result is zero, the following instruction, fetched during the current in struction execution, is discarded and a dummy cycle is replaced to get the proper instruction. This is a 2-cycle instruction. Otherwise proceed with the next instruction.

Skip if ([m]+1)=0, [m] ¬ ([m]+1)

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

50 January 18, 2000

HT47C20L

SIZA [m] Increment data memory and place result in ACC, skip if zero

Description The contents of the specified data memory is incremented by one. If the

result is zero, the next instruction is skipped and the result stored in the accumulator. The data memory remains unchanged. If the result is zero, the following instruction, fetched during the current instruction execu tion, is discarded and a dummy cycle replaced to get the proper instruc tion. This is a 2-cycle instruction. Otherwise proceed with the next instruction.

Operation

Affected flag(s)

SNZ [m].i Skip if bit i of the data memory is not zero

Description If bit i of the specified data memory is not zero, the next instruction is

Operation

Affected flag(s)

Skip if ([m]+1)=0, ACC ¬ ([m]+1)

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

skipped. If bit i of the data memory is not zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction. This is a 2-cycle in struction. Otherwise proceed with the next instruction.

Skip if [m].i¹0

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

SUB A,[m] Subtract data memory from accumulator

Description The specified data memory is subtracted from the contents of the accu-

mulator, leaving the result in the accumulator.

Operation

Affected flag(s)

SUBM A,[m] Subtract data memory from accumulator

Description The specified data memory is subtracted from the contents of the accu

Operation

Affected flag(s)

ACC ¬ ACC+[m

TC2 TC1 TO PD OV Z AC C

¾¾¾¾ÖÖÖÖ

mulator, leaving the result in the data memory. [m] ¬ ACC [m

TC2 TC1 TO PD OV Z AC C

¾¾¾¾ÖÖÖÖ

]+1

51 January 18, 2000

HT47C20L

SUB A,x Subtract immediate data from accumulator

Description The immediate data specified by the code is subtracted from the contents

of the accumulator, leaving the result in the accumulator.

Operation

Affected flag(s)

SWAP [m] Swap nibbles within the data memory

Description The low-order and high-order nibbles of the specified data memory (one

Operation

Affected flag(s)

SWAPA [m] Swap data memory and place result in accumulator

Description The low-order and high-order nibbles of the specified data memory are

Operation

Affected flag(s)

ACC ¬ ACC+x

TC2 TC1 TO PD OV Z AC C

¾¾¾¾ÖÖÖÖ

of the data memories) are interchanged. [m].3~[m].0 « [m].7~[m].4

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged.

ACC.3~ACC.0 ¬ [m].7~[m].4 ACC.7~ACC.4 ¬ [m].3~[m].0

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

SZ [m] Skip if data memory is zero

Description If the contents of the specified data memory is zero, the following instruc-

tion, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction. This is a 2-cycle in struction. Otherwise proceed with the next instruction.

Operation Skip if [m]=0

Affected flag(s)

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

52 January 18, 2000

HT47C20L

SZA [m] Move data memory to ACC, skip if zero

Description The contents of the specified data memory is copied to accumulator. If the

contents is zero, the following instruction, fetched during the current in struction execution, is discarded and a dummy cycle is replaced to get the proper instruction. This is a 2-cycle instruction. Otherwise proceed with the next instruction.

Operation

Affected flag(s)

SZ [m].i Skip if bit i of the data memory is zero

Description If bit i of the specified data memory is zero, the following instruction,

Operation Skip if [m].i=0

Affected flag(s)

Skip if [m]=0, ACC¬ [m]

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction. This is a 2-cycle in struction. Otherwise proceed with the next instruction.

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

TABRDC [m] Move the ROM code (current page) to TBLH and data memory

Description The low byte of ROM code (current page) addressed by the table pointer

(TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly.

Operation

Affected flag(s)

[m] ¬ ROM code (low byte) TBLH ¬ ROM code (high byte)

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

53 January 18, 2000

HT47C20L

TABRDL [m] Move the ROM code (last page) to TBLH and data memory

Description The low byte of ROM code (last page) addressed by the table pointer

(TBLP) is moved to the data memory and the high byte transferred to TBLH directly.

Operation

Affected flag(s)

XOR A,[m] Logical XOR accumulator with data memory

Description Data in the accumulator and the indicated data memory performs a

Operation

Affected flag(s)

XORM A,[m] Logical XOR data memory with accumulator

Description Data in the indicated data memory and the accumulator perform a

Operation

Affected flag(s)

[m] ¬ ROM code (low byte) TBLH ¬ ROM code (high byte)

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾¾¾¾

bitwise logical Exclusive_OR operation and the result is stored in the ac cumulator.

ACC ¬ ACC ²XOR² [m]

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾Ö¾¾

bitwise logical Exclusive_OR operation. The result is stored in the data memory. The zero flag is affected.

[m] ¬ ACC ²XOR² [m]

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾Ö¾¾

XOR A,x Logical XOR immediate data to accumulator

Description Data in the accumulator and the specified data perform a bitwise logical

Exclusive_OR operation. The result is stored in the accumulator. The zero flag is affected.

Operation

Affected flag(s)

ACC ¬ ACC ²XOR² x

TC2 TC1 TO PD OV Z AC C

¾¾¾¾¾Ö¾¾

54 January 18, 2000

HT47C20L

Holtek Semiconductor Inc. (Headquarters)

No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C. Tel: 886-3-563-1999 Fax: 886-3-563-1189

Holtek Semiconductor Inc. (Taipei Office)

5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C. Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International sales hotline)

Holtek Semiconductor (Hong Kong) Ltd.

RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657

The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may pres ent a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.

55 January 18, 2000

Holtek Semiconductor Inc HT47C20L Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

General Description

Block Diagram

Pin Assignment

Pad Assignment

Pin Description

Absolute Maximum Ratings

D.C. Characteristics

A.C. Characteristics

Functional Description

Application Circuits

Instruction Set Summary

Instruction Definition