Holtek Semiconductor Inc HT47C20 Datasheet

Features

Operating voltage: 2.4V~3.6V

Eight bidirectional I/O lines

Four input lines

One interrupt input

One 16-bit programmable timer/event

counter with PFD (programmable frequency divider) function On-chip crystal and RC oscillator for system

clock One 32.768kHz crystal oscillator for real

time clock Watchdog timer

2K ´ 16 program memory ROM

64 ´ 8 data memory RAM

One Real Time Clock (RTC)

One 8-bit prescaler for RTC

General Description

The HT47C20 is an 8-bit high performance RISC-like microcontroller. Its single cycle instruction and two-stage pipeline architecture make high speed applications. The device is suited for use in multiple LCD low power

HT47C20

8-Bit Microcontroller

One buzzer output

Halt function and wake-up feature reduce

power consumption LCD bias C type

One LCDdriver with 20´ 3or19´4 segments

One 38kHz or 40kHz IR carrier output

(455kHz or 480kHz system clock only) Two channels RC type A/D converter

Four-level subroutine nesting

Bit manipulation instruction

16-bit table read instruction

Up to 8.3ms instruction cycle with 480kHz

system clock All instructions in one or two machine cycles

63 powerful instructions

applications among which are calculators, clock timers, games, scales, toys, thermometers, hygrometers, body thermometers, capacitor scaler, other hand held LCD products, and battery systems in particular.

1 January 18, 2000

Block Diagram

HT47C20

Program

ROM

Instructio n

R egister

Instructio n

D ecoder

Tim ing

G enerator

OSC2

C1 C2

OSC1 RES

VDD VSS

Voltage

V1 V2 V3

Halve

Program

C ounter

ALU

S h ifte r

ACC

COM 0~ COM 2

STACK

M U X

MUX

LCD Driver

COM 3/ SEG19

PB0/INT

Interrupt

Circuit

DATA

Memory

STATUS

LC D

Memory

SEG0~ SEG18

IN T C

Tim er A

Tim er B

RTC

WDT

Tim e Base

M U X

O verflow

RC Type

A/D C onverter

Port B

Port A

System C lock

T1 RTC Output

PFD

A/D Clock

SYS CLK/4

M U X

WDT OSC

PB0/IN T

PB1

PB2/TM R PB3

PA0/BZ PA1/BZ PA2/IR PA3/PFD PA4~PA7

PB2/TMR

IN 0 CS0 RS0 CRT0 RT0 IN 1 CS1 RS1 RT1

RTC OSC

PA3/PFD

OSC3

OSC4

2 January 18, 2000

Pin Assignment

RES

HT47C20

OSC4

OSC3

OSC2

OSC1

VDD

PA0/BZ

PA1/BZ

PA2/IR

PA3/PFD

PA4

PA5

PA6

PA7

PB0/IN T

PB1

PB2/TM R

PB3

VSS

20 21 22 23 24 25 26 27 28 29 30 31 32

RT1

61 60 59 58 57 56 55 54 53 5264 63 62

HT47C20

64 Q FP

RS1

CS1

IN 1

CRT0

RT0

RS0

CS0

IN 0

COM 0

COM 1

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

COM 2

COM 3/SEG19

3 January 18, 2000

Pad Assignment

MCLR

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

PB0

PB1

PB2

PB3

VSS

HT47C20

OSC3

OSC1

15431644174518

RT1

OSC2

VDD

RS1

CS1

IN 1

OSC4

(0 , 0 )

RT0

CRT0

RS0

CS0

502351

IN 0

2452255326

COM 0

COM 1

SEG 0

SEG 1

SEG 2

SEG 3

SEG 4

SEG 5

SEG 6

SEG 7

SEG 8

SEG 9

SEG 10

SEG 11

SEG 12

SEG 13

SEG 14

SEG 15

SEG 16

SEG 17

SEG 18

COM 3

COM 2

* The IC substrate should be connected to VSS in the PCB layout artwork.

4 January 18, 2000

Pad Description

HT47C20

Pad No. Pad Name I/O

1 RES

2 3 4 5 6~9

10 11 12 13

14 VSS

18 17 16 15

23 22 21 20

27 26~24

28~46 SEG18~SEG0 O

49, 48, 47 51, 50

52 53

PA0/BZ PA1/BZ PA2/IR PA3/PFD PA4~PA7

PB0/INT PB1 PB2/TMR PB3

IN1 CS1 RS1 RT1

IN0 CS0 RS0 CRT0

RT0

SEG19/COM3 COM2~COM0

V1, V2, V3 C1, C2

OSC4 OSC3

I/O

¾¾

I O O O

Mask

Option

Wake-up

Pull-high

or None

CMOS or

NMOS

1/3 or 1/4

Duty

Function

Schmitt trigger reset input. Active low.

Bidirectional 8-bit input/output port. The low nibble of the PA can be configured as CMOS output or NMOS output with or without pull-high resistors (mask option). NMOS output can be configured as schmitt trigger input with or without pull-high resis tors. Each bit of NMOS output can be configured as wake up input by mask option. Of the eight bits, PA0~PA1 can be set as I/O pins or buzzer outputs by mask option. PA2 can be set as an I/O pin or an IR carrier output also by mask option. PA3 can be set as an I/O pin or a PFD output also by mask option.

Four-bit Schmitt trigger input port. The PB is config ured as with pull-high resistors. Of the four bits, PB0 can be set as an input pin or an external interrupt in put pin (INT be set as an input pin or a timer/event counter input pin also by software application.

Negative power supply, GND

Oscillation input pin of channel 1 Reference capacitor connection pin of channel 1 Reference resistor connection pin of channel 1 Resistor sensor connection pin for measurement of channel 1

Oscillation input pin of channel 0 Reference capacitor connection pin of channel 0 Reference resistor connection pin of channel 0 Resistor/capacitor sensor connection pin for measurement of channel 0 Resistor sensor connection pin for measurement of channel 0

SEG19/COM3 can be set as a segment or a common output driver for LCD panel by mask option. COM2~COM0 are outputs for LCD panel plate.

LCD driver outputs for LCD panel segments

Voltage pump

Real time clock oscillators

) by software application. While PB2 can

5 January 18, 2000

HT47C20

Pad No. Pad Name I/O

54 VDD

55 56

OSC2 OSC1

Mask

Option

¾¾

Positive power supply

Function

OICrystal orRCOSC1 and OSC2 are connected to an RC network or a

crystal (by mask option) for the internal system clock.

Absolute Maximum Ratings

Supply Voltage ..............................-0.3V to 5.5V

Storage Temperature.................-50°Cto125°C

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maxi

mum Ratings² may cause substantial damage to the device. Functional operation of this de vice at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.

D.C. Characteristics

Symbol Parameter

DD1

DD2

Operating Voltage

Operating Current (Crystal OSC)

Operating Current (RC OSC) 3V

Standby Current

STB1

(32.768kHz Crystal Oscillator Enable, LCD Off)

Standby Current

STB2

(32.768kHz Crystal Oscillator Enable, LCD On)

Standby Current

STB3

(Watchdog RC Oscillator Enable, LCD Off)

Standby Current

STB4

(Watchdog RC Oscillator Enable, LCD On)

Standby Current

STB5

(32.768kHz Crystal and Watchdog RC Oscillator Both Disabled, LCD Off)

¾¾

3V No load, system Halt

Input Voltage .................V

-0.3V to VDD+0.3V

Operating Temperature ..............-40°Cto85°C

Test Conditions

Conditions

Min. Typ. Max. Unit

2.4 3 3.6 V

No load, f

A/D Off

No load, f A/D Off

SYS

=455kHz

SYS

=455kHz

0.2 0.4 mA

¾¾

Ta=25°C

6 January 18, 2000

HT47C20

Symbol Parameter

STB6

OL1

OH1

OL2

OH2

OL3

OH3

OL4

OH4

OL5

OH5

Standby Current (A/D On, *R=5kW, *f=500kHz)

Input Low Voltage for I/O

IL1

Ports

Input High Voltage for I/O

IH1

Ports

Input Low Voltage (RES)3V

IL2

Input Low Voltage (INT, TMR) 3V

IL3

Input High Voltage

IH2

(RES

, INT, TMR)

I/O Port Sink Current 3V

I/O Port Source Current 3V

Common 0~3 Output Sink Current

Common 0~3 Output Source Current

Segment 0~19 Output Sink Current

Segment 0~19 Output Source Current

Common 0~3 Output Sink Current

Common 0~3 Output Source Current

Segment 0~19 Output Sink Current

Segment 0~19 Output Source Current

RC Oscillation Output Sink Current

RC Oscillation Output Source Current

Pull-high Resistance of I/O

Ports and INT

Test Conditions

Conditions

3V No load, system Halt

0.5V

0.3V

0.8V

=0.3V

=0.3V (1/2 bias)

=0.45V (1/3 bias)

=0.3V

=2.7V

=2.7V (1/2 bias)

=4.05V (1/3 bias)

=2.7V

Min. Typ. Max. Unit

600 1200

2.1

2.4

2 3.5

-1 -1.5 ¾

50 100

0.9 V

1.5 V

0.9 V

¾mA

-50 -100 ¾mA

15 30

¾mA

-15 -30 ¾mA

100 180

¾mA

-100 -180 ¾mA

20 40

¾mA

-20 -40 ¾mA

510

-5 -10 ¾

40 60 80

Note: *R means the resistance of RC type A/D converter

*f means the frequency of RC type A/D converter

7 January 18, 2000

HT47C20

A.C. Characteristics

Symbol Parameter

SYS1

SYS2

TIMER

WDTOSC

RES

SST

INT

Note: t

System Clock (Crystal OSC) 3V

System Clock (RC OSC) 3V

Timer I/P Frequency (TMR) 3V

Watchdog Oscillator 3V

External Reset Low Pulse Width

System Start-up Timer Period

Interrupt Pulse Width

A/D Converter Frequency 3V

=1/f

SYS

Test Conditions

Conditions

¾¾

Power-up or

wake-up from halt

¾¾

¾¾¾

Ta=25°C

Min. Typ. Max. Unit

455

45 90 180

1024

480 kHz

500 kHz

¾¾ms

SYS

¾¾ms

500 kHz

8 January 18, 2000

Functional Description

HT47C20

Execution flow

The system clock for the HT47C20 is derived from either a crystal or an RC oscillator. The system clock is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles.

Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruction to ef fectively execute in one cycle. If an instruction changes the program counter, two cycles are re quired to complete the instruction.

Program counter - PC

The 11-bit program counter (PC) controls the sequence in which the instructions stored in the program ROM are executed and its contents specify a maximum of 2048 addresses.

After accessing a program memory word to fetch an instruction code, the contents of the program counter are incremented by one. The program counter then points to the memory word containing the next instruction code.

When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction.

The conditional skip is activated by instruction. Once the condition is met, the next instruction, fetched during the current instruction execu tion, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise pro ceed with the next instruction.

The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination will be within 256 loca

tions.

When a control transfer takes place, an addi

tional dummy cycle is required.

Program memory - ROM

The program memory is used to store the pro gram instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 2048´16 bits, addressed by the program counter and table pointer.

Certain locations in the program memory are reserved for special usage

Location 000H This area is reserved for the initialization

program. After chip reset, the program always begins execution at location 000H.

Location 004H This area is reserved for the external inter-

rupt service program. If the INT activated, and the interrupt is enabled and

input pin is

S ystem C lock

Instructio n C lock

T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4

PC PC+1 PC+2

F e tc h IN S T (P C )

E xecute IN S T (P C -1 )

F e tc h IN S T (P C + 1 )

E xecute IN S T (P C )

F e tc h IN S T (P C + 2 )

E xecute IN S T (P C + 1)

Execution flow

9 January 18, 2000

HT47C20

the stack is not full, the program begins exe cution at location 004H.

Location 008H This area is reserved for the time base interrupt

service program. If time base interrupt results from a time base overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 008H.

Location 00CH This area is reserved for the real time clock in

terrupt service program. If a real time clock interrupt results from a real time clock over

000H

004H

008H

00C H

010H

n00H

nFF H

D evice initialization program

External interrupt subroutine

T im e b a s e in te rru p t s u b ro u tin e

R T C interrupt subroutine

Tim er/event counter interrupt subroutine

Look-up table (256 w ords)

Progra ROM

flow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 00CH.

Location 010H This area is reserved for the timer/event coun

ter interrupt service program. If a timer inter rupt results from a timer/event counter A or B overflow, and if the interrupt is enabled and the stack is not full, the program begins exe cution at location 010H.

Table location Any location in the ROM space can be used as

look up tables. The instructions TABRDC [m] (the current page, 1 page=256 words) and TABRDL [m] (the last page) transfer the contents of the lower-order byte to the specified

Mode

*10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0

7FFH

data memory, and the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the table is well-defined, the higher-order byte of the table word are transferred to the TBLH. The table higher-order byte register (TBLH) is read only. The table pointer (TBLP) is a read/write register (07H), which indicates the table location. Before accessing the table, the location

Look-up table (256 w ords)

16 bits

N ote: n ranges from 0 to 7

Program memory

Program Counter

Initial reset 00000000000

External interrupt 00000000100

Time base interrupt 00000001000

RTC interrupt 00000001100

Timer/event counter interrupt 00000010000

Skip PC+2

Loading PCL *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0

Jump, call branch #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0

Return from subroutine S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

Program counter

Note: *10~*0: Program counter bits #10~#0: Instruction code bits

S10~S0: Stack register bits @7~@0: PCL bits

10 January 18, 2000

HT47C20

must be placed in TBLP. The TBLH is read only and cannot be restored. If the main rou tine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruc tion used in the ISR. Errors can occur. In other words, using the table read instruction in the main routine and the ISR simulta neously should be avoided. However, if the ta ble read instruction has to be applied in both the main routine and the ISR, the interrupt is supposed to be disabled prior to the table read instruction. It will not be enabled until the TBLH has been backed up. All table related instructions need two cycles to complete the operation. These areas may function as nor mal program memory depending upon the re quirements.

Stack register - STACK

This is a special part of the memory which is used to save the contents of the program coun ter (PC) only. The stack is organized into four levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the stack pointer (SP) and is neither readable nor writeable. At a subroutine call or interrupt acknowledgment, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the program counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack.

If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be

Instruction(s)

TABRDC [m] P10 P9 P8 @7 @6 @5 @4 @3 @2 @1 @0

TABRDL [m] 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0

*10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0

recorded but the acknowledgment will be inhib ited. When the stack pointer is decremented (by

RET or RETI), the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more eas ily. In a similar case, if the stack is full and a

²CALL² is subsequently executed, stack over flow occurs and the first entry will be lost (only

the most recent four return addresses are

stored).

Data memory - RAM

The data memory is designed with 83 ´ 8 bits. The data memory and is divided into two func tional groups: special function registers and general purpose data memory (64´ 8). Most are

read/write, but some are read only.

The special function registers include the indi

rect addressing register 0 (00H), the memory pointer register 0 (mp0; 01H), the indirect ad dressing register 1 (02H), the memory pointer register 1 (MP1;03H), the bank pointer

(BP;04H), the accumulator (ACC;05H), the pro

gram counter lower-order byte register (PCL;06H), the table pointer (TBLP;07H), the table higher-order byte register (TBLH;08H), the real time clock control register (RTCC;09H), the status register (STATUS;0AH), the interrupt control register 0(INTC0;0BH), the I/O registers (PA;12H, PB;14H), the interrupt control register 1 (INTC1;1EH), the timer/event counter A higher order byte register (TMRAH; 20H), the timer/event counter A lower order byte register (TMRAL; 21H), the timer/event counter control register (TMRC; 22H), the timer/event counter B higher order byte register (TMRBH; 23H), the timer/event counter B lower order byte register (TMRBL; 24H), and the RC oscillator type A/D

Table Location

Table location

Note: *10~*0: Table location bits @7~@0: Table pointer bits

P10~P8: Current program counter bits

11 January 18, 2000

HT47C20

Indirect A ddressing R egister 0

00H

01H

Indirect A ddressing R egister 1

02H

03H

04H

05H

06H

07H

08H

09H

0AH

0BH

0C H

0D H

0EH

0FH

10H

11H

12H

13H

14H

15H

16H

17H

18H

19H

1AH

1BH

1C H

1D H

1EH

1FH

20H

21H

22H

23H

24H

25H

26H

40H

7FH

RTCC

STATUS

IN T C 0

IN T C 1

TM RA H

TM RA L

TM RC

TM RB H

TM RB L

ADCR

G eneral Purpose

D ata M em ory

(64 B ytes)

MP 0

MP1

ACC

PCL

TBLP

TBLH

Special Purpose D ata M em ory

: U n u s e d

R ead as "00"

converter control register (ADCR; 25H). The re maining space before the 40H are reserved for fu ture expanded usage and reading these location will return the result 00H. The general purpose data memory, addressed from 40H to 7FH, is used for data and control information under in struction command.

All data memory areas can handle arithme tic, logic, increment, decrement and rotate operations. Except for some dedicated bits, each bit in the data memory can be set and re set by the SET [m].i and CLR [m].i instruc tion, respectively. They are also indirectly accessible through memory pointer registers (MP0;01H, MP1;03H).

Indirect addressing register

Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation of [00H] and [02H] ac cess data memory pointed to by MP0 (01H) and MP1 (03H) respectively. Reading location 00H or 02H indirectly will return the result 00H. Writing indirectly results in no operation.

The function of data movement between two in direct addressing registers are not supported. The memory pointer registers, MP0 and MP1, are both 8-bit registers which can be used to access the data memory by combining corresponding indirect addressing registers.

Only MP0 can be applied to data memory, while MP1 can be applied to data memory and LCD display memory.

Accumulator

The accumulator is closely related to ALU op erations. It is also mapped to location 05H of the data memory and is capable of carrying out immediate data operations. The data move ment between two data memory locations must pass through the accumulator.

RAM mapping (bank 0)

12 January 18, 2000

HT47C20

Arithmetic and logic unit - ALU

This circuit performs 8-bit arithmetic and logic operation. The ALU provides the following functions:

Arithmetic operations (ADD, ADC, SUB, SBC, DAA)

Logic operations (AND, OR, XOR, CPL)

Rotation (RL, RR, RLC, RRC)

Increment and Decrement (INC, DEC)

Branch decision (SZ, SNZ, SIZ, SDZ ....)

The ALU not only saves the results of a data op eration but can change the status register.

TO or PD flags. In addition it should be noted that operations related to the status register may give different results from those intended. The TO and PD flags can only be changed by the watchdog timer overflow, system power-up, clearing the watchdog timer and executing the HALT instruction.

The Z, OV, AC and C flags generally reflect the status of the latest operations.

In addition, on entering the interrupt sequence or executing the subroutine call, the status reg ister will not be pushed onto the stack automat

ically. If the contents of the status are important and if the subroutine can corrupt the

Status register - STATUS

This 8-bit register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PD) and watchdog time-out flag (TO). It also records the status information and controls the operation se quence.

With the exception of the TO and PD flags, bits in the status register can be altered by instruc tions like most other registers. Any data writ ten into the status register will not change the

status register, precautions must be taken to save it properly.

Interrupts

The HT47C20 provides an external interrupt, an internal timer/event counter interrupt, an

internal time base interrupt, and an internal

real time clock interrupt. The interrupt control register 0 (INTC0;0BH) and interrupt control

rupt control bits to set the enable/disable and

interrupt request flags.

Labels Bits Function

C is set if the operation results in a carry during an addition operation or if a bor-

row does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction.

AC is set if the operation results in a carry out of the low nibbles in addition or no

AC 1

borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared.

OV 3

PD 4

TO 5

¾ ¾

Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.

OV is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared.

PD is cleared when either a system power-up or executing the CLR WDT in struction. PD is set by executing the HALT instruction.

TO is cleared by a system power-up or executing the CLR WDT or HALT in struction. TO is set by a WDT time-out.

Undefined, read as ²0²

STATUS register

13 January 18, 2000

HT47C20

Once an interrupt subroutine is serviced, all other interrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may happen during this interval, but only the interrupt request flag is recorded. If a certain interrupt needs servicing within the service routine, the EMI bit and the corresponding bit of INTC0 or INTC1 may be set allow interrupt nesting. If the stackis full, the interrupt request will not be acknowledged, even if the related in terrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must

Control the master (global) interrupt (1= enabled; 0= disabled)

Control the external interrupt (1= enabled; 0= disabled)

Control the time base interrupt (1= enabled; 0= disabled)

Control the real time clock interrupt (1= enabled; 0= disabled)

External interrupt request flag (1= active; 0= inactive)

Time base request flag (1= active; 0= inactive)

Real time clock request flag (1= active; 0= inactive)

Control the timer/event counter interrupt (1= enabled; 0=disabled)

Internal timer/event counter request flag (1= active; 0= inactive)

INTC0

(0BH)

INTC1

(1EH)

0 EMI

1 EEI

2 ETBI

3 ERTI

4 EIF

5 TBF

6 RTF

0 ETI

4TF

¾ Unused bit, read as ²0²

¾ Unused bit, read as ²0² ¾ Unused bit, read as ²0² ¾ Unused bit, read as ²0²

be prevented from becoming full.

All these kinds of interrupt have a wake-up ca pability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack and then by branching to subrou tines at specified location(s) in the program memory. Only the program counter is pushed onto the stack. If the contents of the register and status register (STATUS) is altered by the interrupt service program which corrupts the

desired control sequence, the contents must be

saved first.

INTC register

14 January 18, 2000

HT47C20

External interrupt is triggered by a high to low transition of INT quest flag (EIF; bit 4 of INTC0) will be set. When the interrupt is enabled, and the stack is not full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag (EIF) and EMI bits will be cleared to disable other interrupts.

The internal timer/event counter interrupt is initialized by setting the timer/event counter interrupt request flag (TF; bit 4 of INTC1), caused by a timer A or timer B overflow. When the interrupt is enabled, and the stack is not full and the TF bit is set, a subroutine call to lo cation 10H will occur. The related interrupt re quest flag (TF) will be reset and the EMI bit cleared to disable further interrupts.

The time base interrupt is initialized by setting the time base interrupt request flag (TBF; bit 5 of INTC0), caused by a regular time base sig nal. When the interrupt is enabled, and the stack is not full and the TBF bit is set, a subrou tine call to location 08H will occur. The related interrupt request flag (TBF) will be reset and the EMI bit cleared to disable further inter rupts.

The real time clock interrupt is initialized by setting the real time clock interrupt request flag (RTF; bit 6 of INTC0), caused by a regular real time clock signal. When the interrupt is enabled, and the stack is not full and the RTF bit is set, a subroutine call to location 0CH will occur. The related interrupt request flag (RTF) will be reset and the EMI bit cleared to disable further interrupts.

During the execution of an interrupt subrou tine, other interrupt acknowledgments are held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set to 1 (if the stack is not full). To return from the interrupt subroutine, RET or RETI in struction may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET does not.

and the related interrupt re

Interrupts occurring in the interval between the rising edges of two consecutive T2 pulses,

will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are en abled. In the case of simultaneous requests the following table shows the priority that is ap plied. These can be masked by resetting the EMI bit.

No. Interrupt Source Priority Vector

a External interrupt 1 04H

b Time base interrupt 2 08H

Real time clock

interrupt

Timer/event counter

interrupt

The external interrupt request flag (EIF), real time clock interrupt request flag (RTF), time base interrupt request flag (TBF), enable external in terrupt bit (EEI), enable real time clock interrupt bit (ERTI), enable time base interrupt bit (ETBI), and enable master interrupt bit (EMI) constitute an interrupt control register 0 (INTC0) which is located at 0BH in the data memory. The timer/event counter interrupt request flag (TF), enable timer/event counter interrupt bit (ETI) on the other hand, constitute an interrupt control register 1 (INTC1) which is located at 1EH in the data memory. EMI, EEI, ETI, ETBI, and ERTI are used to control the enabling/disabling of interrupts. These bits prevent the requested interrupt being serviced. Once the interrupt request flags (RTF, TBF, TF, EIF) are set, they remain in the INTC1 or INTC0 respectively until the interrupts are serviced or cleared by a software in struction.

It is recommended that a program does not use the ²CALL subroutine² within the interrupt subroutine. Because interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications, if only one stack is left, and enabling the interrupt is not well controlled, once the ²CALL subroutine² op erates in the interrupt subroutine will damage the original control sequence.

3 0CH

4 10H

15 January 18, 2000

HT47C20

Oscillator configuration

There are two oscillator circuits in the HT47C20.

OSC1

OSC2

C ry s t a l O s c illa t o r R C O s c illa to r

OSC1

OSC2

System oscillator

Both are designed for system clocks; the RC oscil lator and the crystal oscillator, which are deter mined by mask option. No matter what oscillator type is selected, the signal provides the system clock. The halt mode stops the system oscillator and ignores an external signal to conserve power. The OSC1 and OSC2 are at the same level when the system enters the power down mode.

If an RC oscillator is used, an external resistor between OSC1 and OSC2 is need and the resis tance must range from 51kW to 1MW. The RC oscillator provides the most cost effective solu tion. However, the frequency of the oscillation may vary with VDD, temperature and the chip itself due to process variations. It is, therefore, not suitable for timing sensitive operations where accurate oscillator frequency is desired.

If a crystal oscillator is used, a crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift needed for oscillator, no other external components are needed. Instead of a crystal, a resonator can also be connected between OSC1 and OSC2 to get a frequency reference, but two external capacitors in OSC1 and OSC2 are required.

There is another oscillator circuit designed for the real time clock. In this case, only the 32768kHz crystal oscillator can be applied. The crystal should be connected between OSC3 and OSC4, and two external capacitors along with one external resistor are required for the oscil lator circuit in order to get a stable frequency.

The RTC oscillator circuit can be controlled to oscillate quickly by setting ²SAVE² bit (bit 4 of RTCC) to ²0². After power on reset, the ²SAVE² bit initial value is ²0 ² that is on the

quick-oscillate mode. It¢s recommended to turn it off by setting the ²SAVE² bit ²1² after a period ofabout2secondstoavoiddrainingextrapower.

OSC3

32768H z

OSC4

RTC oscillator

The WDT oscillator is a free running on-chip

RC oscillator, and no external components are

required. Even if the system enters the power down mode, the system clock is stopped, but the WDT oscillator still works with a period of ap proximately 90ms. The WDT oscillator can be disabled by mask option to conserve power.

Watchdog timer - WDT

The clock source of the WDT(f

by a dedicated RC oscillator (WDT oscillator) or

a instruction clock (system clock divided by 4)

or a real time clock oscillator (RTC oscillator),

) is implemented

decided by mask options. The timer is designed to prevent a software malfunction or sequence jumping to an unknown location with unpredictable results. The watchdog timer can be disabled by a mask option. If the watchdog timer is disabled, all the executions related to the WDT result in no operation.

If the clock source of WDT chooses the internal WDT oscillator, the time-out period may vary with temperature, VDD, and process variations. On the other hand, if the clock source selects the instruction clock and the ²HALT² instruction is executed, WDT may stop count ing and lose its protecting purpose, and the logic can only be restarted by external logic.

When the device operates in a noisy environ ment, using the on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT

can cease the system clock.

The WDT overflow under normal operation will initialize ²chip reset² and set the status bit TO. Whereas in the halt mode, the overflow will ini tialize a ²warm reset² only the PC and SP are reset to zero. To clear the contents of WDT, three

16 January 18, 2000

HT47C20

methods are adopted, external reset (a low level to RES), software instruction, or a HALT instruc tion. The software instructions are of two types which include CLR WDT and the other set - CLR WDT1 and CLR WDT2. Of these two types of in struction, only one can be active depending on the mask option -²CLR WDT times selection op tion².Ifthe²CLR WDT² is selected (i.e., CLR WDT times equal one), any execution of the CLR WDT instruction will clear the WDT. In case ²CLR WDT1² and ²CLR WDT2² are chosen (i.e. CLR WDT times equal two), these two instructions must be executed to clear the WDT; otherwise, the WDT may reset the chip because of time-out.

The WDT time-out period ranges from

s/2

. Because the ²CLR WDT² or ²CLR

s/2

WDT1² and ²CLRWDT2² instruction only clear the last two-stage of the WDT.

Multi-function timer

The HT47C20 provides a multi-function timer for WDT, time base and real time clock but with different time-out periods. The multi-function timer consists of a 7-stage divider and an 8-bit prescaler, with the clock source coming from

WDT OSC or RTC OSC or the instruction clock (i.e., system clock divided by 4). The

multi-function timer also provides a selectable frequency signal (ranges from f LCD driver circuits, and a selectable frequency

signal (ranges from f put by mask option. It is recommended to select

/22to fs/29) for buzzer out

/22to fs/28) for

a near 4kHz signal for LCD driver circuits for proper display.

Time base

The time base offers a periodic time-out period to generate a regular internal interrupt. Its time-out period ranges from f

/212to fs/215se

lected by mask option. If time base time-out oc curs, the related interrupt request flag (TBF; bit 5 of INTC0) is set. But if the interrupt is en abled, and the stack is not full, a subroutine call to location 08H occurs.

When the HALT instruction is executed, the time base still works (if WDT clock source co mes from WDT RC OSC or RTC OSC) and can wake up from halt mode.

If the TBF is set ²1² before entering the halt mode, the wake up function will be disable.

S ystem C lock/4

RTC

32768H z

OSC

WDT

12kHz

OSC

Mask

Option

Selection

D ivider

Tim e Base Interrupt f

fs/2

Watchdog timer

fs/2

Mask Option

/2 ~ fs/2

12 15

Time base

Prescaler

W D T C lear

Prescaler

CK TRCK T

LC D D river

Buzzer

/2 ~ fs/2

fs/2 ~ fs/2

Tim e-out R eset f

/2 ~ fs/2

15 16

17 January 18, 2000

+ 39 hidden pages

Holtek Semiconductor Inc HT47C20 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

General Description

Block Diagram

Pin Assignment

Pad Assignment

Pad Description

Absolute Maximum Ratings

D.C. Characteristics

A.C. Characteristics

Functional Description