Holtek Semiconductor Inc HT16270 Datasheet

RAM Mapping 64 ´16 LCD Controller for I/O mC

Features

Operating voltage: 2.7V~5.2V

·

External Crystal 32.768kHz oscillator

·

1/5 bias, 1/16 duty, frame frequency is 64Hz

·

Max. 64´16 patterns, 16 commons,

·

64 segments
Built-in internal resistor type bias generator

·

3-wire serial interface

·

8 kinds of time base/WDT selection

·

Time base or WDT overflow output

·

Built-in LCD display RAM

·

General Description

HT16270 is a peripheral device specially de
signed for I/O type mC used to expand the dis
play capability. The max. display segment of
the device are 1024 patterns (64´16). It also
supports serial interface, buzzer sound, watch
dog timer or time base timer functions. The
HT16270 is a memory mapping and
multi-function LCD controller. The software

HT16270

R/W address auto increment

·

Two selectable buzzer frequencies

·

(2kHz/4kHz)
Power down command reduces power

·

consumption
Software configuration feature

·

Data mode and Command mode instructions

·

Three data accessing modes

·

VLCD pin to adjust LCD operating voltage

·

configuration feature of the HT16270 make it

­suitable for multiple LCD applications includ

­ing LCD modules and display subsystems. Only
three lines are required for the interface be
tween the host controller and the HT16270.

­The HT162X series have many kinds of prod
ucts that match various applications.

-

-

-

Selection Table

HT162X HT1620 HT1621 HT1622 HT16220 HT1623 HT1625 HT1626 HT1627 HT16270

COM

SEG

Built-in Osc.

Crystal Osc.

448888161616

32 32 32 32 48 64 48 64 64

ÖÖ ÖÖÖÖ

ÖÖ Ö ÖÖ Ö

1 April 21, 2000

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Block Diagram

HT16270

OSCO

OSCI

CS

RD

WR

DATA

VDD

VSS

BZ

Tone Frequency

BZ

Pin Assignment

WR

DATA

VSS

OSCI

OSCO

VDD

VLCD

IR Q

COM 0
COM 1
COM 2
COM 3
COM 4
COM 5
COM 6
COM 7
COM 8

COM 9
COM 10
COM 11
COM 12

SEG62

SEG63

CS

1

RD

2
3
4
5
6
7
8
9
10

BZ

11

BZ

12

T1

13

T2

14

T3

15

T4

16
17
18
19
20
21
22
23
24
25
26
27
28
29

NC

30

31

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

COM 14

COM 13

C ontrol

and
Tim ing
Circuit

G enerator

SEG59

SEG60

SEG61

SEG1

SEG0

COM 15

SEG58

SEG2

W atchdog Tim er

Tim e B ase G enerator

SEG53

SEG54

SEG55

SEG56

SEG57

H T 16270

100 Q F P

SEG7

SEG6

SEG5

SEG4

SEG3

D isplay R A M

LC D D river/
Bias Circuit

and

SEG49

SEG50

SEG51

SEG52

SEG11

SEG10

SEG9

SEG8

COM 0

COM 15

SEG 0

SEG 63

VLCD

IR Q

SEG44

SEG45

SEG46

SEG47

SEG48

81828384858687888990919293949596979899100

80

SEG43

79

SEG42
NC

78

SEG41

77

SEG40

76

SEG39

75

SEG38

74
73

SEG37
SEG36

72

SEG35

71

SEG34

70

SEG33

69

SEG32

68

SEG31

67

SEG30

66

SEG29

65

SEG28

64

SEG27

63

SEG26

62

SEG25

61

SEG24

60

SEG23

59

SEG22

58

SEG21

57

SEG20

56

SEG19

55

NC

54

NC

53

SEG18

52

SEG17

51

SEG16

SEG15

SEG14

SEG13

SEG12

2 April 21, 2000

Pad Assignment

WR

CS

RD

HT16270

SEG 59

SEG 60

SEG 62

SEG 63

SEG 61

SEG 58

SEG 56

SEG 57

SEG 53

SEG 54

SEG 55

SEG 50

SEG 52

SEG 49

SEG 51

SEG 46

SEG 47

SEG 48

SEG 43

SEG 44

SEG 45

SEG 42

DATA

VSS

OSCI

OSCO

VDD

VLCD

IR Q

COM 0

COM 1

COM 2

COM 3

COM 4

COM 5
COM 6

COM 7

COM 8

COM 9

BZ

BZ

T2
T3

T4

T1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

96

24

COM 10

95

25

94

93

92

91

90

89

88

87

86

85

84

83

82

(0 , 0 )

26

27

28

29

30

SEG 0

COM 15

COM 14

COM 13

COM 12

COM 11

31

SEG 1

32

33

35

34

SEG 3

SEG 2

SEG 4

37

38

36

SEG 7

SEG 6

SEG 5

79

80

81

39

SEG 8

78

40

41

42

SEG 10

SEG 9

SEG 11

75

76

77

43

44

45

SEG 12

SEG 13

SEG 14

72

73

74

71

SEG41

SEG40

70

SEG39

69

68

SEG38

67

SEG37

66

SEG36

65

SEG35

64

SEG34

63

SEG33

62

SEG32

61

SEG31

SEG30

60

SEG29

59

SEG28

58

SEG27

57

56

SEG26
SEG25

55

54

SEG24

53

SEG23

52

SEG22
SEG21

51

SEG20

50

SEG19

49

48

47

46

SEG 17

SEG 15

SEG 18

SEG 16

Chip size: 245 ´ 237 (mil)

2

* The IC substrate should be connected to VDD in the PCB layout artwork.

3 April 21, 2000

Pad Coordinates Unit: mil

Pad No. X Y Pad No. X Y

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36 3.67
37 15.63
38 22.27
39 34.28
40 40.88
41 52.88
42 59.47
43 71.47
44 78.13
45 90.07
46 96.72
47 108.72
48 116.19

-116.57

-116.68

-116.72

-116.72

-116.72

-115.93

-116.72

-116.72

-116.72

-115.94

-115.94 -0.60

-115.94 -7.18

-115.90 -19.21

-115.97 -25.85

-115.93 -37.85

-115.93 -44.45

-115.93 -56.45

-115.93 -63.05

-115.97

-115.93 -81.70

-115.93 -93.65

-115.94 -100.30

-115.94 -112.37

-108.08 -112.07

-96.03 -112.05

-89.43 -112.05

-77.43 -112.05

-70.82 -112.05

-58.83 -112.05

-52.17 -112.05

-40.22 -112.05

-33.58 -112.05

-21.58 -112.00

-14.98 -112.05

-2.97 -112.00

99.90 49

90.80 50

84.15 51

77.50 52 116.19

70.90 53 116.15

64.25 54 116.19

54.75 55 116.19

41.45 56 116.19

21.85 57 116.19

11.39 58 116.19
59 116.19
60 116.24
61 116.24 11.90
62 116.19 18.49
63 116.24 30.51
64 116.19 37.10
65 116.19 49.09
66 116.15 55.76

-75.05

-112.05

-112.05

-112.05

-112.05

-112.05

-112.05

-112.05

-112.00

-112.00

-112.05

-112.05

-112.00

-111.82

67 116.15 67.75
68 116.19 74.38
69 116.15 86.36
70 116.19 93.03
71 116.11 104.85
72 112.20 112.24
73 100.04 112.24
74 93.42 112.24
75 81.43 112.24
76 74.80 112.24
77 62.77 112.24
78 56.23 112.24
79 44.20 112.24
80 37.57 112.24
81 25.63 112.24
82 18.95 112.24
83 6.97 112.24
84 0.38 112.24
85
86
87
88
89
90
91
92
93
94
95
96

116.15 -99.79

116.15 -93.16

116.19 -81.18

-11.65

-18.23

-30.22

-36.89

-48.92

-55.51

-67.45

-74.12

-86.15

-92.72

-104.72

-114.22

-74.54

-62.58

-55.93

-43.94

-37.40

-25.37

-18.70

-6.72

-0.09

112.24

112.20

112.24

112.24

112.24

112.24

112.29

112.24

112.24

112.25

112.25

112.25

HT16270

4 April 21, 2000

Pad Description

Pad No. Pad Name I/O Description

1 DATA I/O Serial data input/output with pull-high resistor

2 VSS

3 OSCI I Crystal oscillator input pin

4 OSCO O Crystal oscillato output pin

5 VDD

6 VLCD I LCD operating voltage input pad.

7 IRQ

8, 9 BZ, BZ

10~13 T1~T4 I Not connected

14~29 COM0~COM15 O LCD common outputs

30~93 SEG0~SEG63 O LCD segment outputs

94 CS

95 RD

96 WR

Negative power supply, ground

¾

Positive power supply

¾

Time base or watchdog timer overflow flag, NMOS open drain

O

output

2kHz or 4kHz tone frequency output pair (Tristate output

O

buffer)

Chip selection input with pull-high resistor. When the CS
logic high, the data and command read from or write to the
HT16270 are disabled. The serial interface circuit is also reset.

I

But if the CS
data and command transmission between the host controller
and the HT16270 are all enabled.

READ clock input with pull-high resistor. Data in the RAM of
the HT16270 are clocked out on the rising edge of the RD
nal. The clocked out data will appear on the data line. The host

I

controller can use the next falling edge to latch the clocked out
data.

WRITE clock input with pull-high resistor. Data on the DATA

I

line are latched into the HT16270 on the rising edge of the WR
signal.

is at logic low level and is input to the CS pad, the

HT16270

is

sig-

Absolute Maximum Ratings

Supply Voltage .............................-0.3V to 5.5V

Input Voltage .................V

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maxi

mum Ratings² may cause substantial damage to the device. Functional operation of this device
at other conditions beyond those listed in the specification is not implied and prolonged expo
sure to extreme conditions may affect device reliability.

-0.3V to VDD+0.3V

SS

Storage Temperature.................-50°Cto125°C

Operating Temperature ..............-25°Cto75°C

5 April 21, 2000

-

-

HT16270

D.C. Characteristics

Symbol Parameter

V

I

I

I

V

V

I

I

I

I

I

I

I

I

R

DD

DD1

DD2

STB

IL

IH

OL1

OH1

OL2

OH2

OL3

OH3

OL4

OH4

PH

Operating Voltage

Operating Current

Operating Current

Standby Current

Input Low Voltage

Input High Voltage

BZ, BZ, IRQ

BZ, BZ

DATA

DATA

LCD Common Sink Current

LCD Common Source Current

LCD Segment Sink Current

LCD Segment Source Current

Pull-high Resistor

Test Conditions

V

DD

Conditions

¾¾

3V

No load/LCD ON
Crystal oscillator

5V

3V

No load/LCD OFF
Crystal oscillator

5V

3V

No load
Power down mode

5V

3V

DATA, WR,CS,RD

5V 0

3V

DATA, WR,CS,RD

5V 4.0

V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

=0.3V

OL

V

=0.5V

OL

V

=2.7V

OH

V

=4.5V

OH

V

=0.3V

OL

=0.5V

V

OL

V

=2.7V

OH

V

=4.5V

OH

V

=0.3V

OL

=0.5V

V

OL

V

=2.7V

OH

V

=4.5V

OH

V

=0.3V

OL

=0.5V

V

OL

V

=2.7V

OH

V

=4.5V

OH

3V

Min. Typ. Max. Unit

2.7

¾

30 75

¾

50 125

¾

0

525

10 45

214

428

¾

¾
¾
¾
¾

¾

2.4

¾
¾

0.9 1.8

1.7 3

-0.9 -1.8 ¾

-1.7 -3 ¾

0.9 1.8

1.7 3

-0.9 -1.8 ¾

-1.7 -3 ¾

80 160

180 360

-40 -80 ¾mA

-90 -180 ¾mA

50 100

120 240

-30 -60 ¾mA

-70 -140 ¾mA

100 200 300

DATA, WR,CS,RD

5V 50 100 150

Ta=25°C

5.2 V

mA
mA
mA
mA
mA
mA

0.6 V

1.0 V

3V

5V

mA

¾

mA

¾

mA

mA

mA

¾

mA

¾

mA

mA

¾mA
¾mA

¾mA
¾mA

kW
kW

6 April 21, 2000