RAM Mapping 48´8 LCD Controller for I/O mC
Features
Operating voltage: 2.7V~5.2V
·
Built-in RC oscillator
·
External 32.768kHz crystal or 32kHz
·
frequency source input
1/4 bias, 1/8 duty, frame frequency is 64Hz
·
Max. 48´8 patterns, 8 commons, 48 segments
·
Built-in internal resistor type bias generator
·
3-wire serial interface
·
8 kinds of time base/WDT selection
·
Time base or WDT overflow output
·
Built-in LCD display RAM
·
General Description
HT1623 is a peripheral device specially de
signed for I/O type mC used to expand the dis
play capability. The max. display segment of
the device are 384 patterns (48´8). It also sup
ports serial interface, buzzer sound, watchdog
timer or time base timer functions. The
HT1623 is a memory mapping and
multi-function LCD controller. The software
HT1623
R/W address auto increment
·
Two selection buzzer frequencies
·
(2kHz/4kHz)
Power down command reduces power
·
consumption
Software configuration feature
·
Data mode and Command mode instructions
·
Three data accessing modes
·
VLCD pin to adjust LCD operating voltage
·
Cascade application
·
configuration feature of the HT1623 make it
suitable for multiple LCD applications includ
ing LCD modules and display subsystems. Only
three lines are required for the interface be
tween the host controller and the HT1623. The
HT162X series have many kinds of products
that match various applications.
-
-
Selection Table
HT162X HT1620 HT1621 HT1622 HT16220 HT1623 HT1625 HT1626 HT1627 HT16270
COM
SEG
Built-in Osc.
Crystal Osc.
448 8
32 32 32 32
ÖÖ Ö ÖÖÖ
ÖÖ Ö ÖÖÖ Ö
8
48
1 April 21, 2000
8161616
64 48 64 64
Block Diagram
HT1623
OSCO
OSCI
CS
RD
WR
DATA
VDD
VSS
BZ
Tone Frequency
BZ
Pin Assignment
CS
RD
WR
DATA
VSS
OSCI
OSCO
VDD
VLCD
IR Q
BZ
BZ
T1
T2
T3
COM 0
COM 1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
COM 2
COM 3
COM 4
SEG46
SEG47
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32 33 34 35 3637 38 39 40 41 42 43 44 45 46 4748 49 50
COM 7
COM 6
COM 5
C ontrol
and
Tim ing
Circuit
G enerator
SEG43
SEG44
SEG45
SEG 2
SEG 1
SEG 0
Tim e Base G enerator
SEG38
SEG39
SEG40
SEG41
SEG42
H T1623
100 Q FP
SEG 7
SEG 6
SEG 5
SEG 4
SEG 3
D isplay R A M
LCD Driver/
Bias Circuit
W atchdog Tim er
and
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
NC
SEG 12
SEG 11
SEG 10
SEG 9
SEG 8
NC
NC
NC
NC
NC
81828384858687888990919293949596979899100
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
COM 0
COM 7
SEG 0
SEG 47
VLCD
IR Q
NC
NC
NC
NC
NC
NC
NC
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
NC
NC
NC
NC
2 April 21, 2000
Pad Assignment
HT1623
SEG 32
SEG 33
SEG 34
SEG 35
SEG 36
SEG 37
SEG 38
SEG 39
SEG 40
SEG 41
SEG 42
SEG 43
SEG 44
SEG 45
SEG 46
SEG 47
CS
RD
WR
DATA
VSS
OSCI
OSCO
VDD
VLCD
IR Q
BZ
BZ
COM 0
COM 1
COM 2
T1
T2
T3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
71
19
COM 3
20
COM 4
69 70
21
COM 5
68
22
COM 6
23
COM 7
66 67
63 64 65
24
25 26 27 28 29 30 31 32 33 34 35 36
SEG 1
SEG 2
SEG 0
59
57
(0 ,0 )
SEG 8
SEG 7
SEG 3
SEG 4
SEG 6
SEG 5
SEG 9
56
58
60 61 62
55
SEG 31
54
SEG 30
53
SEG 29
52
SEG 28
51
SEG 27
50
SEG 26
49
SEG 25
48
SEG 24
47
SEG 23
46
SEG 22
45
SEG 21
44
SEG 20
43
SEG 19
42
SEG 18
41
SEG 17
40
SEG 16
39
SEG 15
38
SEG 14
37
SEG 13
SEG 11
SEG 10
SEG 12
Chip size: 177 ´ 171 (mil)
2
* The IC substrate should be connected to VDD in the PCB layout artwork.
3 April 21, 2000
Pad Coordinates Unit: mil
Pad No. X Y Pad No. X Y
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28 4.76
29 11.39
30 23.80
31 30.43
32 42.84
33 49.47
34 61.88
35 68.51
36 80.92
-82.45
-82.45
-82.45
-83.21
-83.21
-83.21
-83.21
-83.21
-83.21
-83.21 -4.84
-83.21 -16.66
-83.21 -29.92
-83.21 -41.74
-83.21 -48.37
-83.21 -54.99
-83.21 -61.63
-83.21 -68.25
-82.88 -78.96
-72.50 -79.99
-65.88 -79.99
-59.24 -79.99
-52.62 -79.99
-45.73 -79.22
-33.32 -79.22
-26.69 -79.22
-14.28 -79.22
-7.65 -79.22
79.35 37 82.83
67.02 38 82.83
60.39 39 82.83
46.71 40 82.83
32.30 41 82.83
25.20 42 82.83
18.57 43 82.83
11.94 44 82.83 4.55
5.31 45 82.83 11.18
46 82.83 17.81
47 82.83 24.44
48 82.83 31.07
49 82.83 37.70
50 82.83 44.33
51 82.83 50.96
52 82.83 57.59
53 82.83 64.22
54 82.83 70.85
55 82.83 77.48
56 27.03 79.35
57 20.40 79.35
58 13.77 79.35
59 7.14 79.35
60 0.51 79.35
-79.22
-79.22
-79.22
-79.22
-79.22
-79.22
-79.22
-79.22
-79.22
61
62
63
64
65
66
67
68
69
70
71
-6.12
-12.75
-19.38
-26.01
-32.64
-39.27
-45.90
-52.53
-59.16
-65.79
-72.42
-52.44
-35.23
-28.60
-21.97
-15.34
-8.71
-2.08
79.35
79.35
79.35
79.35
79.35
79.35
79.35
79.35
79.35
79.35
79.35
HT1623
4 April 21, 2000
HT1623
Pad Description
Pad No. Pad Name I/O Description
Chip selection input with pull-high resistor. When the CS
high, the data and command read from or written to the HT1623
1CS
2RD
3WR
4 DATA I/O Serial data input/output with pull-high resistor
5 VSS
6 OSCI I The OSCI and OSCO pads are connected to a 32.768kHz crystal
7 OSCO O
8 VDD
9 VLCD I LCD operating voltage input pad.
10 IRQ
11, 12 BZ, BZ
13~15 T1~T3 I Not connected
16~23 COM0~COM7 O LCD common outputs
24~71 SEG0~SEG47 O LCD segment outputs
are disabled. The serial interface circuit is also reset But if the
I
CS
is at logic low level and is input to the CS pad, the data and
command transmission between the host controller and the
HT1623 are all enabled.
READ clock input with pull-high resistor. Data in the RAM of the
HT1623 are clocked out on the rising edge of the RD
I
clocked out data will appear on the data line. The host controller
can use the next falling edge to latch the clocked out data.
WRITE clock input with pull-high resistor. Data on the DATA
I
line are latched into the HT1623 on the rising edge of the WR sig
nal.
Negative power supply, ground
¾
in order to generate a system clock. If the system clock comes
from an external clock source, the external clock source should be
connected to the OSCI pad. But if an on-chip RC oscillator is se
lected instead, the OSCI and OSCO pads can be left open.
Positive power supply
¾
Time base or watchdog timer overflow flag, NMOS open drain
O
output
O 2kHz or 4kHz tone frequency output pair
is logic
signal. The
-
-
Absolute Maximum Ratings
Supply Voltage..............................-0.3V to 5.5V
Input Voltage................V
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maxi
mum Ratings² may cause substantial damage to the device. Functional operation of this device
at other conditions beyond those listed in the specification is not implied and prolonged expo
sure to extreme conditions may affect device reliability.
-0.3V to VDD+0.3V
SS
Storage Temperature.................-50°Cto125°C
Operating Temperature ..............-25°Cto75°C
5 April 21, 2000
-
-
HT1623
D.C. Characteristics
Symbol Parameter
V
DD
I
DD1
I
DD2
I
DD11
I
DD22
I
STB
V
IL
V
IH
I
OL1
I
OH1
I
OL1
I
OH1
I
OL2
I
OH2
Operating Voltage
Operating Current
Operating Current
Operating Current
Operating Current
Standby Current
Input Low Voltage
Input High Voltage
BZ, BZ, IRQ
BZ, BZ
DATA
DATA
LCD Common Sink Current
LCD Common Source Current
Test Conditions
Min. Typ. Max. Unit
V
DD
Conditions
¾¾
3V
No load/LCD ON
On-chip RC oscillator
5V
3V
No load/LCD ON
Crystal oscillator
5V
3V
No load/LCD OFF
On-chip RC oscillator
5V
3V
No load/LCD OFF
Crystal oscillator
5V
3V
No load
Power down mode
5V
3V
DATA, WR,CS,RD
5V 0
3V
DATA, WR,CS,RD
5V 4.0
V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
=0.3V
OL
=0.5V
V
OL
V
=2.7V
OH
V
=4.5V
OH
V
=0.3V
OL
V
=0.5V
OL
V
=2.7V
OH
=4.5V
V
OH
V
=0.3V
OL
=0.5V
V
OL
V
=2.7V
OH
V
=4.5V
OH
Ta=25°C
2.7
¾
¾
¾
¾
¾
¾
¾¾
¾¾
¾
¾
0
2.4
0.9 1.8
1.7 3
-0.9 -1.8 ¾
-1.7 -3 ¾
0.9 1.8
1.7 3
-0.9 -1.8 ¾
-1.7 -3 ¾
80 160
180 360
5.2 V
¾
155 310
260 420
150 310
250 420
830
20 60
20
35
110
220
0.6 V
¾
1.0 V
¾
3V
¾
5V
¾
¾
¾
¾
¾
¾mA
¾mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
-40 -80 ¾mA
-90 -180 ¾mA
6 April 21, 2000
HT1623
Symbol Parameter
I
OL3
I
OH3
R
PH
LCD Segment Sink Current
LCD Segment Source Current
Pull-high Resistor
A.C. Characteristics
Symbol Parameter
f
SYS1
f
SYS2
f
LCD1
f
LCD2
t
COM
f
CLK1
f
CLK2
t
CS
t
CLK
System Clock
System Clock
LCD Frame Frequency
LCD Frame Frequency
LCD Common Period
Serial Data Clock (WR Pin)
Serial Data Clock (RD Pin)
Serial Interface Reset Pulse
Width (Figure 3)
WR,RDInput Pulse Width
(Figure 1)
Test Conditions
Min. Typ. Max. Unit
V
DD
3V
5V
3V
5V
3V
Conditions
=0.3V
V
OL
V
=0.5V
OL
V
=2.7V
OH
V
=4.5V
OH
50 100
120 240
¾mA
¾mA
-30 -60 ¾mA
-70 -140 ¾mA
100 200 300
kW
DATA, WR,CS,RD
5V 50 100 150
kW
Ta=25°C
Test Conditions
Min. Typ. Max. Unit
V
DD
3V
Conditions
22 32 40 kHz
On-chip RC oscillator
5V 24 32 40 kHz
3V
¾
32
¾
kHz
External clock source
5V
3V
¾
44 64 80 Hz
32
¾
kHz
On-chip RC oscillator
5V 48 64 80 Hz
3V
¾
64
¾
Hz
External clock source
5V
n: Number of COM
¾
3V
¾
¾
¾¾
n/f
64
LCD
Hz
¾
sec
¾
150 kHz
Duty cycle 50%
5V
3V
¾¾
¾¾
300 kHz
75 kHz
Duty cycle 50%
5V
CS
¾
Write mode 3.34
¾¾
250
¾
150 kHz
¾
¾¾
3V
Read mode 6.67
Write mode 1.67
¾¾
¾¾
5V
Read mode 3.34
¾¾
ns
ms
ms
7 April 21, 2000
HT1623
Symbol Parameter
t
r,tf
t
su
t
h
t
su1
t
h1
WR, RD
Clock
Rise/Fall Time Serial Data
Clock Width (Figure 1)
Setup Time DATA to WR,RD
Clock Width (Figure 2)
Hold Time DATA to WR,RD
Clock Width (Figure 2)
Setup Time for CS to WR,RD
Clock Width (Figure 3)
Hold Time for CS to WR,RD
Clock Width (Figure 3)
90%
50%
10%
t
f
t
CLK
t
r
Figure 1
Test Conditions
Min. Typ. Max. Unit
V
DD
Conditions
3V
¾¾
120
¾
ns
5V
3V
¾¾
120
¾
ns
5V
3V
¾¾
120
¾
ns
5V
3V
¾¾
100
¾
ns
5V
3V
¾¾
100
¾
ns
5V
VALID DATA
V
DD
-
t
CLK
GND
DB
W R , R D
Clock
50%
50%
t
h
t
su
-
V
DD
GND
V
DD
GND
Figure 2
W R , R D
Clock
CS
50%
FIR ST
t
su1
50%
Clock
LAST
Clock
Figure 3
t
CS
t
h1
V
-
GND
V
-
GND
DD
DD
8 April 21, 2000
Functional Description
HT1623
Display memory - RAM structure
The static display RAM is organized into 96´4
bits and stores the display data. The contents of
the RAM are directly mapped to the contents of
the LCD driver. Data in the RAM can be
accessedbytheREAD,WRITEand
READ-MODIFY-WRITE commands. The fol
lowing is a mapping from the RAM to the LCD
patterns.
COM 4COM 5COM 6COM 7
SEG 0
SEG 1
SEG 2
SEG 3
SEG 47
D3 D2 D1 D0
1
3
5
7
95
Addr
Data
D a ta 4 B its
(D 3 , D 2 , D 1 , D 0 )
Time base and watchdog timer - WDT
The time base generator and WDT share the
same divided (/256) counter. TIMER DIS/EN/CLR,
WDT DIS/EN/CLR and IRQ
EN/DIS are inde
pendent from each other. Once the WDT
time-out occurs, the IRQ
logic low level until the CLR WDT or the IRQ
-
pin will remain at
DIS command is issued.
COM 0COM 1COM 2COM 3
0
2
4
Address 7 Bits
6
(A 6 , A 5 , ...., A 0 )
94
D3 D2 D1 D0
Addr
Data
-
C lock S ou rce
Tim e Base
/256
CLR Tim er
RAM mapping
T IM E R E N /D IS
WDT EN/DIS
V
DD
Q
/4
CLR W DT
D
CK
R
WDT
Timer and WDT configurations
9 April 21, 2000
IR Q
IR Q E N /D IS
HT1623
If an external clock is selected as the source of
system frequency, the SYS DIS command turns
out invalid and the power down mode fails to be
carried out until the external clock source is re
moved.
Buzzer tone output
A simple tone generator is implemented in the
HT1623. The tone generator can output a pair
of differential driving signals on the BZ and BZ
which are used to generate a single tone.
Command format
The HT1623 can be configured by the software
setting. There are two mode commands to con
figure the HT1623 resource and to transfer the
LCD display data.
Name Command Code Function
TONE OFF 0000-1000-X Turn-off tone output
TONE 4K 010X-XXXX-X Turn-on tone output, tone frequency is 4kHz
TONE 2K 0110-XXXX-X Turn-on tone output, tone frequency is 2kHz
The following are the data mode ID and the
command mode ID:
-
If successive commands have been issued, the
command mode ID can be omitted. While the
system is operating in the non-successive com
mand or the non-successive address data mode,
the CS
operation mode will be reset also. The CS
returns to ²0², a new operation mode ID should
be issued first.
Operation Mode ID
READ Data 1 1 0
WRITE Data 1 0 1
READ-MODIFY-WRITE Data 1 0 1
COMMAND Command 1 0 0
pin should be set to ²1² and the previous
-
pin
10 April 21, 2000
Timing Diagrams
READ mode (command code:110)
CS
WR
RD
HT1623
DATA
1
A6 A6
1
M em ory A ddress 1 (M A 1) Data (MA2)
A1 A0 D0 D1
D ata (M A 1) M em ory A ddress 2 (M A 2)
0A5A4A3 A2
READ mdoe (successive address reading)
CS
WR
RD
0A5A4A3 A2
DATA
1
A6
1
M em ory Address (M A ) D ata (M A )
A1 A0 D0 D1
D2 D3
0A5A4A3 A2
1
1
D2 D3
D2 D3
D0 D1
D ata (M A +1) D ata (M A +2) D ata (M A +3)
D0 D1
A1 A0 D0 D1
D2 D3
D0 D1
D2 D3
D2 D3
D0
11 April 21, 2000
WRITE mode (command code:101)
CS
WR
HT1623
DATA
1A5A4A3 A2
1
0
M em ory A ddress 1 (M A 1) D ata (M A 1)
A1 A0 D0 D1
WRITE mode (successive address writing)
CS
WR
1A5A4A3 A2
DATA
1
A6
0
M em ory A ddress (M A ) D ata (M A )
A1 A0 D0 D1
D2 D3
1A5A4A3 A2
A6A6
0
M em ory A ddress 2 (M A 2) Data (M A 2)
D2 D3
D0 D1
D ata (M A+1) D ata (M A +2) D ata (M A +3)
D2 D3
1
D0 D1
D2 D3
A1 A0 D0 D1
D2 D3
D0 D1
D2 D3
D0
12 April 21, 2000
READ-MODIFY-WRITE mode (command code:101)
CS
WR
RD
HT1623
DATA
1A5A4A3 A2
1
0
M em ory A ddress 1 (M A 1) D ata (M A 1)
A1 A0 D 0 D1
D2 D3
D0 D1
Data (M A1)
D2 D3
1
READ-MODIFY-WRITE mode (successive address accessing)
CS
WR
RD
DATA
1A5A4A3 A2
1
0
A6
M em ory A ddress (M A ) D ata (M A )
A1 A0 D0 D1
D2 D3
D2 D3
D0 D1
D ata (M A ) D ata (M A +1) D ata (M A +1)
A5A4A3 A2
A6A6
1
0
M em ory A ddress 2 (M A 2) D ata (M A 2)
D0 D1
D2 D3
D0 D1
D2 D3
A1 A0 D0 D1
D0
D1
Data (MA+2)
D2 D3
D2 D3
D0
13 April 21, 2000
Command mode (command code:100)
CS
WR
HT1623
DATA
1
0
0C8C7C6 C5
C4 C3 C2 C1
C om m and 1
Mode (data and command mode)
CS
WR
DATA
RD
C om m and
or
D ata M ode
Address and D ata
C0
C om m and
D ata M ode
C8C7C6 C5
or
C4 C3 C2 C1
C om m and iC om m and... C om m and
Address and D ata
C om m and
D ata M ode
C0
or
or
D ata M ode
Address and D ata
14 April 21, 2000
Application Circuits
HT1623
External C lock 1 (32kH z)
External C lock 2 (32kH z)
On-chip OSC
C rystal
32768H z
*Note:
The connection of IRQ
The voltage applied to V
Adjust VR to fit LCD display, at V
Adjust R (external pull-high resistance) to fit user¢s time base clock.
m
C
C lock O ut
CS
*
RD
WR
DATA
*
R
IR Q
OSCI
OSCO
C O M 0 ~ C O M 7 S E G 0 ~ S E G 4 7
H T 1623
1 /4 B ia s , 1 /8 D u ty
VDD
VLCD
BZ
BZ
*
VR
Piezo
LC D Panel
and RD pin can be selected depending on the requirement of the mC.
pin must be lower than VDD.
LCD
DD
=5V, V
=4V, VR=15kW±20%.
LCD
15 April 21, 2000
Command Summary
Name ID Command Code D/C Function Def.
READ
WRITE
READMODIFYWRITE
SYS DIS
SYS EN
LCD OFF
LCD ON
TIMER DIS
WDT DIS
TIMER EN
WDT EN
TONE OFF
CLR TIMER
CLR WDT
RC 32K
EXT (XTAL)
32K
TONE 4K
TONE 2K
DIS
IRQ
EN
IRQ
F1
F2
F4
A6A5A4A3A2A1A0D0D1D2D3 D Read data from the RAM
110
A6A5A4A3A2A1A0D0D1D2D3 D Write data to the RAM
101
A6A5A4A3A2A1A0D0D1D2D3 D Read and Write data to the RAM
101
0000-0000-X C
100
0000-0001-X C Turn on system oscillator
100
0000-0010-X C Turn off LCD display Yes
100
0000-0011-X C Turn on LCD display
100
0000-0100-X C Disable time base output Yes
100
0000-0101-X C Disable WDT time-out flag output Yes
100
0000-0110-X C Enable time base output
100
0000-0111-X C Enable WDT time-out flag output
100
0000-1000-X C Turn off tone outputs Yes
100
0000-1101-X C
100
0000-1111-X C
100
0001-10XX-X C
100
0001-11XX-X C
100
010X-XXXX-X C Tone frequency output: 4kHz
100
0110-XXXX-X C Tone frequency output: 2kHz
100
100X-0XXX-X C Disable IRQ output Yes
100
100X-1XXX-X C Enable IRQ output
100
101X-0000-X C
100
101X-0001-X C
100
101X-0010-X C
100
Turn off both system oscillator
and LCD bias generator
Clear the contents of the time
base generator
Clear the contents of the WDT
stage
System clock source, on-chip RC
oscillator
System clock source, external
32kHz clock source or crystal
oscillator 32.768kHz
Time base clock output: 1Hz
The WDT time-out flag after: 4s
Time base clock output: 2Hz
The WDT time-out flag after: 2s
Time base clock output: 4Hz
The WDT time-out flag after: 1s
HT1623
Yes
Yes
16 April 21, 2000
HT1623
Name ID Command Code D/C Function Def.
F8
F16
F32
F64
F128
TEST
NORMAL
Note:
X : Don¢t care
A6~A0 : RAM address
D3~D0 : RAM data
D/C : Data/Command mode
Def. : Power on reset default
All the bold forms, namely 110, 101, and 100, are mode commands. Of these, 100indicates the
command mode ID. If successive commands have been issued, the command mode ID except for the
first command will be omitted. The source of the tone frequency and of the time base/WDT clock frequency can be derived from an on-chip 32kHz RC oscillator, a 32.768kHz crystal oscillator, or an external 32kHz clock. Calculation of the frequency is based on the system frequency sources as stated
above. It is recommended that the host controller should initialize the HT1623 after power on reset,
for power on reset may fail, which in turn leads to the malfunctioning of the HT1623.
101X-0011-X C
100
101X-0100-X C
100
101X-0101-X C
100
101X-0110-X C
100
101X-0111-X C
100
1110-0000-X C
100
1110-0011-X C Normal mode Yes
100
Time base clock output: 8Hz
The WDT time-out flag after: 1/2 s
Time base clock output: 16Hz
The WDT time-out flag after: 1/4 s
Time base clock output: 32Hz
The WDT time-out flag after: 1/8 s
Time base clock output: 64Hz
The WDT time-out flag after: 1/16 s
Time base clock output: 128Hz
The WDT time-out flag after: 1/32 s
Test mode, user don¢t use.
Yes
17 April 21, 2000
HT1623
Holtek Semiconductor Inc. (Headquarters)
No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C.
Tel: 886-3-563-1999
Fax: 886-3-563-1189
Holtek Semiconductor Inc. (Taipei Office)
5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C.
Tel: 886-2-2782-9635
Fax: 886-2-2782-9636
Fax: 886-2-2782-7128 (International sales hotline)
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RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong
Tel: 852-2-745-8288
Fax: 852-2-742-8657
Copyright Ó 2000 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek
assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are
used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications
will be suitable without further modification, nor recommends the use of its products for application that may pres
ent a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior
notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
18 April 21, 2000
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