HOLTEK HT93LC56 User Manual
CMOS 2K 3-Wire Serial EEPROM
Features
·
Operating voltage: 2.2V~5.5V
·
Low power consumption
-
Operating: 5mA max.
-
Standby: 10mA max.
·
User selectable internal organization
-
2K(HT93LC56): 256´8or128´16
·
3-wire Serial Interface
·
Write cycle time: 5ms max.
General Description
The HT93LC56 is a 2K-bit low voltage nonvolatile, serial
electrically erasable programmable read only memory
device using the CMOS floating gate process. Its 2048
bits of memory are organized into 128 words of 16 bits
each when the ORG pin is connected to VCC or orga
nized into 256 words of 8 bits each when it is tied to
HT93LC56
·
Automatic erase-before-write operation
·
Word/chip erase and write operation
·
Write operation with built-in timer
·
Software controlled write protection
·
10-year data retention after 100K rewrite cycles
·
106rewrite cycles per word
·
Commercial temperature range (0°Cto+70°C)
·
8-pin DIP/SOP/TSSOP package
VSS. The device is optimized for use in many industrial
and commercial applications where low power and low
voltage operation are essential. By popular
microcontroller, the versatile serial interface including
chip select (CS), serial clock (SK), data input (DI) and
data output (DO) can be easily controlled.
Block Diagram
Pin Assignment
C S
S K
O R G
D I
C S
1
S K
2
3
D I
4
D O
H T 9 3 L C 5 6
8 D I P - A / S O P - A / T S S O P - A
C o n t r o l
L o g i c
a n d
C l o c k
G e n e r a t o r
D a t a
R e g i s t e r
A d d r e s s
R e g i s t e r
V C C
A d d r e s s
D e c o d e r
V S S
M e m o r y C e l l
A r r a y
2 K : ( 2 5 6
V C C
8
N C
7
6
O R G
5
V S S
8 o r 1 2 8 ´ 1 6 )
´
O u t p u t
B u f f e r
N C
1
V C C
2
3
C S
4
S K
H T 9 3 L C 5 6
8 S O P - B
D O
O R G
8
V S S
7
6
D O
5
D I
Rev. 1.30 1 March 15, 2006
HT93LC56
Pin Description
Pin Name I/O Description
CS I Chip select input
SK I Serial clock input
DI I Serial data input
DO O Serial data output
VSS
ORG I
NC
VCC
Absolute Maximum Ratings
Operation Temperature (Commercial)..........................................................................................................0°Cto70°C
Applied V
Applied Voltage onany Pin with Respect to VSS
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
Voltage with Respectto VSS ...................................................................................VSS-0.3V toVSS+6.0V
CC
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Negative power supply, ground
¾
Internal Organization
When ORG is connected to VDD or ORG is floated, the (´16) memory organization is se
lected. When ORG is tied to VSS, the (´8) memory organization is selected. There is an in
ternal pull-up resistor on the ORG pin. (HT93LC56-A)
No connection
¾
Positive power supply
¾
..................................................................................................VSS
-0.3V toVCC+0.3V
-
-
D.C. Characteristics
Symbol Parameter
V
I
I
I
I
I
V
V
V
V
C
C
CC1
CC2
STB
LI
LO
Operating Voltage
CC
Operating Current (TTL) 5V DO unload, SK=1MHz
Operating Current
(CMOS)
Standby Current (CMOS) 5V CS=SK=DI=0V
Input Leakage Current 5V
Output Leakage Current 5V
Input Low Voltage
IL
IH
OL
OH
IN
OUT
Input High Voltage
Output Low Voltage
Output High Voltage
Input Capacitance
Output Capacitance
Test Conditions
V
CC
Conditions
¾¾
5V DO unload, SK=1MHz
2.2V~5.5V DO unload, SK=250kHz
V
IN=VSS~VCC
, CS=0V
¾
¾
¾
¾
5V
2.2V~5.5V
5V
2.2V~5.5V
5V
2.2V~5.5V
5V
2.2V~5.5V
¾
¾
V
OUT=VSS~VCC
=2.1mA
I
OL
=10mA ¾¾
I
OL
=-400mA
I
OH
I
=-10mAV
OH
=0V, f=250kHz
V
IN
=0V, f=250kHz
V
OUT
Min. Typ. Max. Unit
2.2
¾
¾¾
¾¾
¾¾
¾¾
0
0
0
0
2
0.9V
CC
¾
¾
¾
¾
¾
¾
¾¾
5.5 V
5mA
5mA
5mA
10
1
1
0.8 V
0.1V
CC
V
CC
V
CC
0.4 V
0.2 V
2.4
CC
¾¾
¾¾
¾¾
-0.2 ¾¾
5pF
5pF
mA
mA
mA
V
V
V
V
V
Rev. 1.30 2 March 15, 2006
A.C. Characteristics
Symbol Parameter
f
t
t
t
t
t
t
t
t
t
t
t
t
SK
SKH
SKL
CSS
CSH
CDS
DIS
DIH
PD1
PD0
SV
HV
PR
Clock Frequency 0 2000 0 500 0 250 kHz
SK High Time 250
SK Low Time 250
CS Setup Time 50
CS Hold Time 0
CS Deselect Time 250
DI Setup Time 100
DI Hold Time 100
DO Delay to ²1²¾
DO Delay to ²0²¾
Status Valid Time
DO Disable Time 100
Write Cycle Time
VCC=5V±10% VCC=3V±10%
VCC=2.2V
Min. Max. Min. Max. Min. Max.
¾
¾
¾
¾
¾
¾
¾
250
250
¾
250
¾
¾
5
1000
1000
200
0
250
200
200
¾
¾
¾
400
¾
¾
¾
¾
¾
¾
¾
¾
1000
1000
250
¾
5
2000
2000
200
0
1000
400
400
¾
¾
¾
¾
¾
¾
¾
¾
¾
2000 ns
2000 ns
¾¾
400
¾
¾¾
HT93LC56
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
A.C. Test Conditions
Input rise and fall time: 5ns (1V to 2V)
Input and output timing reference levels: 1.5V
Output load circuit: See Figure below.
V C C = 1 . 9 5 2 V
8 0 0
W
D O
1 0 0 p F *
* Including Scope and Jig
t
C S
S K
D I
D O
C S S
t
D I S
H i - Z
t
t
D I H
V a l i d D a t a
S K H
t
P D 0
t
C D S
t
S K L
V a l i d D a t a
t
P D 1
t
C S H
Rev. 1.30 3 March 15, 2006
Functional Description
The HT93LC56 is accessed via a three-wire serial com
munication interface. The device is arranged into 128
words by 16 bits or 256 words by 8 bits depending whether
the ORG pin is connected to VCC or VSS. The HT93LC56
contains seven instructions: READ, ERASE, WRITE,
EWEN, EWDS, ERAL and WRAL. When the user
selectable internal organization is arranged into
128´16 (256´8), these instructions are all made up of
11(12) bits data: 1 start bit, 2 op code bits and 8(9) address
bits.
By using the control signal CS, SK and data input signal
DI, these instructions can be given to the HT93LC56.
These serial instruction data presented at the DI input
will be written into the device at the rising edge of SK.
During the READ cycle, DO pin acts as the data output
and during the WRITE or ERASE cycle, DO pin indi
cates the BUSY/READY status. When the DO pin is ac
tive for read data or as a BUSY/READY indicator the CS
pin must be high; otherwise DO pin will be in a
high-impedance state. For successful instructions, CS
must be low once after the instruction is sent. After
power on, the device is by default in the EWDS state.
And, an EWEN instruction must be performed before
any ERASE or WRITE instruction can be executed. The
following are the functional descriptions and timing diagrams of all seven instructions.
READ
The READ instruction will stream out data at a specified
address on the DO pin. The data on DO pin changes
during the low-to-high edge of SK signal. The 8 bits or
16 bits data stream is preceded by a logical ²0² dummy
bit. Irrespective of the condition of the EWEN or EWDS
instruction, the READ command is always valid and in
dependent of these two instructions. After the dataword
has been read the internal address will be automatically
incremented by 1 allowing the next consecutive data
word to be read out without entering further address
data. The address will wrap around with CS High until
CS returns to LOW.
HT93LC56
ERASE
-
The ERASE instruction erases data at the specified ad
dresses in the programming enable mode. After the
ERASE op-code and the specified address have been
issued, the data erase is activated by the falling edge of
CS. Since the internal auto-timing generator provides all
timing signals for the internal erase, so the SK clock is
not required. During the internal erase, we can verify the
busy/ready status if CS is high. The DO pin will remain
low butwhen the operation is over, the DO pin will return
to high and further instructions can be executed.
WRITE
The WRITE instruction writes data into the device at the
specified addresses in the programming enable mode.
After the WRITE op-code and the specified address and
data have been issued, the data writing is activated by
the falling edge of CS. Since the internal auto-timing
generator provides all timing signal for the internal writ
ing, so the SK clock is not required. The auto-timing
write cycle includes an automatic erase-before-write ca
pability. So, it is not necessary to erase data before the
WRITE instruction. During the internal writing, we can
verify the busy/ready status if CS is high. The DO pin will
remain low but when the operation is over, the DO pin
will return to high and further instructions can be executed.
ERAL
The ERALinstruction erases the entire 128´16 or 256´8
memory cellsto logical ²1² state in the programming enable mode. After the erase-all instruction set has been
issued, the data erase feature is activated by the falling
edge of CS. Since the internal auto-timing generator
provides all timing signal for the erase-all operation, so
the SK clock is not required. During the internal erase-all
operation, we can verify the busy/ready status if CS is
high. The DO pin will remain low but when the operation
is over, the DO pin will return to high and further instruc
tion can be executed.
-
-
-
-
EWEN/EWDS
The EWEN/EWDS instruction will enable or disable the
programming capabilities. At both the power on and
power off state the device automatically entered the dis
able mode. Before a WRITE, ERASE, WRAL or ERAL in
struction is given, the programming enable instruction
EWEN must be issued, otherwise the ERASE/WRITE in
struction is invalid. After the EWEN instruction is issued,
the programming enable condition remains until power is
turned off or an EWDS instruction is given. No data can be
written into the device in the programming disabled state.
By so doing, the internal memory data can be protected.
Rev. 1.30 4 March 15, 2006
WRAL
The WRAL instruction writes data into the entire 128´16
or 256´8 memory cells in the programming enable
-
mode. After the write-all instruction set has been issued,
-
the data writing is activated by the falling edge of CS.
Since the internal auto-timing generator provides all tim
-
ing signals for the write-all operation, so the SK clock is
not required. During the internal write-all operation, we
can verify the busy/ready status if CS is high. The DO
pin will remain low but when the operation is over the
DO pin will return to high and further instruction can be
executed.
-
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