Holtek HT48R10A-1, HT48R30A-1, HT48R50A-1, HT48R70A-1 Handbook

Page 1

HT48R10A-1, HT48R30A-1, HT48R50A-1, HT48R70A-1

I/O Type MCU

Handbook

September 2003

Copyright Ó 2003 by HOLTEK SEMICONDUCTOR INC. All rights reserved. Printed in Taiwan. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form by any means, electronic, mechanical photo copying, recording, or otherwise without the prior written permission of HOLTEK SEMICONDUCTOR INC.

Page 2

Page 3

Contents

Part I Microcontroller Profile ................................................................... 1

Contents

Chapter 1 Hardware Structure ........................................................................................ 3

Introduction ....................................................................................................................3

Features ......................................................................................................................... 4

Technology Features ............................................................................................... 4

Kernel Features ....................................................................................................... 4

Peripheral Features ................................................................................................. 4

Selection Table .............................................................................................................. 5

Block Diagram ............................................................................................................... 6

Pin Assignment .............................................................................................................. 7

Pin Description ............................................................................................................... 8

Absolute Maximum Ratings ......................................................................................... 13

D.C. Characteristics ..................................................................................................... 13

A.C. Characteristics ..................................................................................................... 14

System Architecture ..................................................................................................... 15

Clocking and Pipelining ......................................................................................... 15

Program Counter ................................................................................................... 16

Stack ..................................................................................................................... 17

Arithmetic and Logic Unit - ALU ............................................................................ 18

Program Memory ......................................................................................................... 18

Organization .......................................................................................................... 19

Special Vectors ..................................................................................................... 19

Look-up Table ........................................................................................................ 20

Table Program Example ........................................................................................ 20

Data Memory ............................................................................................................... 21

Organization .......................................................................................................... 22

General Purpose Data Memory ............................................................................ 22

Special Purpose Data Memory ............................................................................. 23

Page 4

I/O Type MCU

Special Function Registers .......................................................................................... 23

Indirect Addressing Registers - IAR, IAR0, IAR1 ................................................ 24

Memory Pointers - MP, MP0, MP1 ....................................................................... 24

Accumulator - ACC ............................................................................................... 25

Program Counter Low Register - PCL ......................................................................... 25

Look-up Table Registers - TBLP, TBLH ................................................................ 25

Watchdog Timer Register - WDTS ....................................................................... 25

Status Register - STATUS .................................................................................... 25

Interrupt Control Register - INTC ......................................................................... 26

Timer/Event Counter Registers ............................................................................ 27

Input/Output Ports and Control Registers ............................................................. 27

Input/Output Ports ........................................................................................................ 27

Pull-high Resistors ................................................................................................ 27

Port A Wake-up ..................................................................................................... 28

I/O Port Control Registers .................................................................................... 28

Pin-shared Functions ............................................................................................ 28

Programming Considerations ................................................................................ 30

Timer/Event Counters .................................................................................................. 31

Configuring the Timer/Event Counter Input Clock Source .................................... 31

Timer Registers - TMR, TMR0, TMR0L/TMR0H, TMR1L/TMR1H ....................... 32

Timer Control Registers - TMRC, TMR0C, TMR1C ............................................. 33

Configuring the Timer Mode .................................................................................. 34

Configuring the Event Counter Mode .................................................................... 35

Configuring the Pulse Width Measurement Mode ................................................. 35

Programmable Frequency Divider (PFD) and Buzzer Application ........................ 36

Prescaler ............................................................................................................... 37

I/O Interfacing ........................................................................................................ 37

Programming Considerations ................................................................................ 37

Interrupts ......................................................................................................................38

External Interrupt ................................................................................................... 39

Timer/Event Counter Interrupt ............................................................................... 39

Interrupt Priority ..................................................................................................... 40

Programming Considerations ................................................................................ 40

Reset and Initialization ................................................................................................. 41

Reset ..................................................................................................................... 41

Oscillator ......................................................................................................................48

System Clock Configurations ................................................................................ 48

System Crystal/Ceramic Oscillator ........................................................................ 48

System RC Oscillator ............................................................................................. 49

Internal System RC Oscillator ................................................................................ 49

RTC Oscillator........................................................................................................ 49

Watchdog Timer Oscillator .................................................................................... 50

HALT and Wake-up in Power Down Mode .................................................................. 50

Watchdog Timer ........................................................................................................... 51

Configuration Options .................................................................................................. 52

Application Circuits ...................................................................................................... 53

Page 5

Contents

Part II Programming Language ............................................................. 55

Chapter 2 Instruction Set Introduction ........................................................................ 57

Instruction Set .............................................................................................................. 57

Instruction Timing .................................................................................................. 57

Moving and Transferring Data ............................................................................... 58

Arithmetic Operations ............................................................................................ 58

Logical and Rotate Operations .............................................................................. 58

Branches and Control Transfer ............................................................................. 58

Bit Operations ....................................................................................................... 58

Table Read Operations ......................................................................................... 59

Other Operations ................................................................................................... 59

Instruction Set Summary ............................................................................................. 59

Convention ............................................................................................................ 59

Chapter 3 Instruction Definition ................................................................................... 63

Chapter 4 Assembly Language and Cross Assembler ............................................... 75

Notational Conventions ................................................................................................ 75

Statement Syntax ........................................................................................................ 76

Name ..................................................................................................................... 76

Operation .............................................................................................................. 76

Operand ................................................................................................................ 76

Comment ............................................................................................................... 77

Assembly Directives .................................................................................................... 77

Conditional Assembly Directives ........................................................................... 77

File Control Directives ........................................................................................... 78

Program Directives ................................................................................................ 79

Data Definition Directives ...................................................................................... 82

Macro Directives ................................................................................................... 84

Assembly Instructions .................................................................................................. 86

Name ..................................................................................................................... 86

Mnemonic .............................................................................................................. 86

Operand, Operator and Expression ...................................................................... 86

Miscellaneous ............................................................................................................. 88

Forward References .............................................................................................. 88

Local Labels .......................................................................................................... 88

Reserved Assembly Language Words .................................................................. 89

Cross Assembler Options ............................................................................................ 90

Assembly Listing File Format ....................................................................................... 90

Source Program Listing ......................................................................................... 90

Summary of Assembly .......................................................................................... 91

Miscellaneous ....................................................................................................... 91

iii

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I/O Type MCU

Part III Development Tools .................................................................... 93

Chapter 5 MCU Programming Tools ............................................................................. 95

HT-IDE3000 Development Environment ...................................................................... 95

Holtek In-Circuit Emulator - HT-ICE ............................................................................ 96

HT-ICE Interface Card ................................................................................................. 96

OTP Programmer ........................................................................................................ 97

OTP Adapter Card ....................................................................................................... 97

System Configuration .................................................................................................. 97

Installation ....................................................................................................................99

System Requirement ............................................................................................. 99

Hardware Installation ............................................................................................ 99

Software Installation .............................................................................................. 99

OTP HandyWriter ................................................................................................ 103

Chapter 6 Quick Start .................................................................................................. 105

Step 1 - Create a New Project ........................................................................... 105

Step 2 - Add Source Program Files to the Project ............................................ 105

Step 3 - Build the Project ................................................................................... 105

Step 4 - Transmit Code to Holtek ...................................................................... 105

Step 5 - Programming the OTP Device ............................................................. 106

Appendix ................................................................................................. 107

Appendix A Device Characteristic Graphics .............................................................. 109

Appendix B Package Information ................................................................................ 119

Page 7

Preface

Since the founding of the company, Holtek Semiconductor Inc. has concentrated much of its de sign efforts in the area of microcontroller development. Although supplying a wide range of semi conductor devices, the microcontroller category has always been a key product category within the Holtek range, and one which will continue to expand as their devices increase in functionality and maturity. By capitalizing on the substantial accumulated skills within its dedicated microcontroller development department, Holtek has been able to release a comprehensive range of high quality low-cost microcontroller devices for a wide range of application areas. Holtek¢s high quality embedded I/O microcontroller solutions provide a means for customers to greatly enhancethe functional contents of their products, which when combined with Holtek¢s com prehensive rangeof development tools provide designers with the means to reduce their designto market times and greatly increasing their added value.

This handbook is divided into three parts for user convenience. Most details regarding general datasheet information and device specification is located within Part I. Information related to microcontroller programming such as device instruction set, instruction definition, and assembly language directivesis found within Part II. Part III relates to the Holtek rangeof Development Tools where information can be found on their installation and use.

By compiling all relevant data together in one handbook we hope users of the Holtek range of I/O Type microcontroller devices will have at their fingertips a useful, complete and simple means to efficiently implementtheir microcontroller applications. Holtek¢s efforts to combine information on de vice specifications, programming and development tools into one publication have produced a handbook which with careful use by the user should result in trouble free designs and the maxi mum benefit being gained from the many features of Holtek microcontroller devices. We welcome feedback and comments from our customers regarding further improvements.

Page 8

I/O Type MCU

Page 9

Part I

Part I Microcontroller Profile

Microcontroller Profile

Page 10

I/O Type MCU

Page 11

Chapter 1

Hardware Structure

This section is the main datasheet section of the I/O Type microcontroller handbook and contains all theparameters and information related to the hardware. The information contained provides de signers with details on all the main hardware features of the I/O Type microcontroller range which together with the programming section contains the information to enable swift and successful im plementation of user microcontroller applications. By proper consultation of the relevant parts of this section, users can ensure that they make the most efficient use of the flexible and multi-function features within the I/O Type microcontroller series.

Introduction

The HT48R10A-1/HT48C10-1, HT48R30A-1/HT48C30-1, HT48R50A-1/HT48C50-1 and HT48R70A-1/HT48C70-1 are 8-bit high performance, RISC architecture microcontroller devices specifically designed for multiple I/O control product applications. Device flexibility is enhanced with their internal special features such as HALT and wake-up functions, oscillator options, buzzer driver, etc. These features combine to ensure applications require a minimum of external components and therefore reduce overall product costs. Having the advantages of low power consumption, high performance, I/O flexibility as well as low cost, these devices have the versatility to suit a wide range of application possibilities such as industrial control, consumer products, subsystem controllers, etc. Many features are common to all devices, however, they differ in areas such as I/O pin count, RAM and ROM capacity, timer number and size etc.

Chapter 1 Hardware Structure

The HT48R10A-1, HT48R30A-1, HT48R50A-1 and HT48R70A-1 are OTP devices offering the ad vantages of easy and effective program updates, using the Holtek range of development and pro gramming tools. These devices provide the designer with the means for fast and low cost product development cycles. However, for applications that are at a mature state in their design process, the HT48C10-1, HT48C30-1, HT48C50-1 and HT48C70-1 mask version devices offer a comple mentary device for products with high volume and low cost demands. Fully pin and functionally compatible with their OTP sister devices, such mask version devices provide the ideal substitute for productswhich havegone beyond their development cycle and are facing cost down demands.

Page 12

Features

Technology Features

High-performance RISC Architecture

Low-power Fully Static CMOS Design

Operating Voltage:

=4MHz: 2.2V~5.5V

SYS

=8MHz: 3.3V~5.5V

SYS

Power Consumption:

2mA Typical at 5V 4MHz Maximum of 1mA Standby Current at 3V with WDT and RTC Disabled Temperature Range:

Operating Temperature -40°Cto85°C (Industrial Grade) Storage Temperature -50°Cto125°C

Kernel Features

Program Memory:

1K´14 OTP/Mask ROM (HT48R10A-1/HT48C10-1) 2K´14 OTP/Mask ROM (HT48R30A-1/HT48C30-1) 4K´15 OTP/Mask ROM (HT48R50A-1/HT48C50-1) 8K´16 OTP/Mask ROM (HT48R70A-1/HT48C70-1) Data Memory:

64´8 SRAM (HT48R10A-1/HT48C10-1) 96´8 SRAM (HT48R30A-1/HT48C30-1) 160´8 SRAM (HT48R50A-1/HT48C50-1) 224´8 SRAM (HT48R70A-1/HT48C70-1)

· Table Read Function

· Multi-level Hardware Stack:

4-level (HT48R10A-1/HT48C10-1, HT48R30A-1/HT48C30-1) 6-level (HT48R50A-1/HT48C50-1) 16-level (HT48R70A-1/HT48C70-1)

· Direct and Indirect Data Addressing Mode

Bit Manipulation Instructions

63 Powerful Instructions

Most Instructions Implemented in 1 Machine Cycle

I/O Type MCU

Peripheral Features

From 21 to 56 Bidirectional I/O with Pull-high Options

Port A Wake-up Options

External Interrupt Input

Event Counter Input

Full Timer Functions with Prescaler and Interrupt

Watchdog Timer (WDT)

HALT and Wake-up Feature for Power Saving Operation

Page 13

PFD/Buzzer Driver Outputs

On-chip Crystal and RC Oscillator

32768Hz Real Time Clock (RTC) Function

Low Voltage Reset (LVR) Feature for Brown-out Protection

In-circuit Programming Interface with Code Protection

Mask Version Devices Available for High Volume Production

Full Suite of Supported Hardware and Software Tools Available

Selection Table

The series of I/O microcontrollers include a comprehensive range of features, some of which are standard and some of which are device dependent. Most features are common to all devices, the main feature distinguishing them are Program Memory, Data Memory capacity, I/O count and timer tion, the following table, which summarizes the main features of each device, is provided.

Chapter 1 Hardware Structure

functions. To assist users in their selection of the most appropriate device for their applica

Part No. VDD

HT48R10A-1 HT48C10-1

HT48R30A-1 HT48C30-1

HT48R50A-1 HT48C50-1

HT48R70A-1 HT48C70-1

Note

Part numbers including ²C² are mask version devices while ²R² are OTP devices.

2.2V~5.5V

Program

Memory

1K´14 64´8

2K´14 96´8

4K´15 160´8

8K´16 224´8

Data

Memory

I/O Timer Interrupt Stack

8-bit´1

16-bit´1

16-bit´2

Package

Types

2 4 24SKDIP/SOP

316

24SKDIP/SOP, 28SKDIP/SOP

28SKDIP/SOP,

48SSOP

48SSOP,

64QFP

Page 14

Block Diagram

The following block diagram illustrates the main functional blocks of the I/O Type microcontroller series of devices.

I/O Type MCU

P r o g r a m M e m o r y

L o o k - u p

T a b l e

R e g i s t e r

A d d r e s s D e c o d e r

I n t e r r u p t

C i r c u i t

L o o k - u p

T a b l e

P o i n t e r

C o n f i g .

R e g i s t e r

P r o g r a m

C o u n t e r

S t a c k

S t a c k P o i n t e r

I / O

P o r t s

S y s t e m R C /

X ' t a l O s c i l l a t o r

I n t e r n a l

R C O S C

W D T

O s c i l l a t o r

R e s e t &

L V R

This block diagram represents the OTP devices, for the mask device there is no Device Programming

Note

G e n e r a t o r

D a t a

M e m o r y

C o n f i g .

R e g i s t e r

T i m i n g

A d d r e s s D e c o d e r

W a t c h d o g

T i m e r

I n s t r u c t i o n

D e c o d e r

M U X

M e m o r y

P o i n t e r

C o n f i g .

R e g i s t e r

T i m e r ( s ) /

C o u n t e r

I n s t r u c t i o n

R e g i s t e r

M U X

S h i f t e r

A L U

A C C

B u z z e r

D r i v e r

C o n f i g .

R e g i s t e r

Circuitry.

T o P r o g r a m

M e m o r y

P r o g r a m m i n g

C o n f i g u r a t i o n

O p t i o n

D e v i c e

C i r c u i t r y

Page 15

Pin Assignment

Chapter 1 Hardware Structure

P B 5

P B 4

P A 3

P A 2

P A 1

P A 0

P B 3

P B 2

P B 1 / B Z

1 0

P B 0 / B Z

1 1

V S S

1 2

P C 0 / I N T

H T 4 8 R 1 0 A - 1 / H T 4 8 C 1 0 - 1

2 4 S K D I P - A / S O P - A

P B 5

P B 4

P A 3

P A 2

P A 1

P A 0

P B 3

P B 2

P B 1 / B Z

P B 0 / B Z

1 0

V S S

1 1

P G 0 / I N T

P C 0 / T M R 0

1 2

1 3

P C 1

1 4

H T 4 8 R 5 0 A - 1 / H T 4 8 C 5 0 - 1

2 8 S K D I P - A / S O P - A

2 4

2 3

2 2

2 1

2 0

1 9

1 8

1 7

1 6

1 5

1 4

1 3

2 8

2 7

2 6

2 5

2 4

2 3

2 2

2 1

2 0

1 9

1 8

1 7

1 6

1 5

P B 6

P B 7

P A 4

P A 5

P A 6

P A 7

O S C 2 / P C 4

O S C 1 / P C 3

V D D

R E S

P C 2

P C 1 / T M R

P B 6

P B 7

P A 4

P A 5

P A 6

P A 7

O S C 2 / P G 2

O S C 1 / P G 1

V D D

R E S

P C 5 / T M R 1

P C 4

P C 3

P C 2

P B 5

P B 4

P A 3

P A 2

P A 1

P A 0

P B 3

P B 2

P B 1 / B Z

P B 0 / B Z

V S S

P G 0 / I N T

2 4

2 3

2 2

2 1

2 0

1 9

1 8

1 7

1 6

1 5

1 0

1 4

1 1

1 3

1 2

H T 4 8 R 3 0 A - 1 / H T 4 8 C 3 0 - 1

2 4 S K D I P - A / S O P - A

P B 5

P B 4

P A 3

P A 2

P A 1

P A 0

P B 3

P B 2

P B 1 / B Z

P B 0 / B Z

N C

P D 7

P D 6

P D 5

P D 4

V S S

P G 0 / I N T

T M R 0

P C 0

P C 1

P C 2

4 7

4 6

4 5

4 4

4 3

4 2

4 1

4 0

3 9

1 0

3 8

1 1

3 7

1 2

3 6

1 3

3 5

1 4

3 4

1 5

3 3

1 6

3 2

1 7

3 1

1 8

3 0

1 9

2 9

2 0

2 8

2 1

2 7

2 2

2 6

2 3

2 5

2 4

4 8

H T 4 8 R 5 0 A - 1 / H T 4 8 C 5 0 - 1

4 8 S S O P - A

P B 6

P B 7

P A 4

P A 5

P A 6

P A 7

O S C 2 / P G 2

O S C 1 / P G 1

V D D

R E S

P C 2

P C 0 / T M R

P B 6

P B 7

P A 4

P A 5

P A 6

P A 7

N C

O S C 2 / P G 2

O S C 1 / P G 1

V D D

R E S

T M R 1

P D 3

P D 2

P D 1

P D 0

P C 7

P C 6

P C 5

P C 4

P C 3

P B 5

P B 4

P A 3

P A 2

P A 1

P A 0

P B 3

P B 2

P B 1 / B Z

P B 0 / B Z

V S S

P G 0 / I N T

P C 0 / T M R

P C 1

2 8

2 7

2 6

2 5

2 4

2 3

2 2

2 1

2 0

1 9

1 0

1 8

1 1

1 7

1 2

1 6

1 3

1 5

1 4

H T 4 8 R 3 0 A - 1 / H T 4 8 C 3 0 - 1

2 8 S K D I P - A / S O P - A

1 0

1 1

1 2

1 3

1 4

1 5

1 6

1 7

1 8

1 9

2 0

2 1

2 2

2 3

2 4

4 8 S S O P - A

4 8

4 7

4 6

4 5

4 4

4 3

4 2

4 1

4 0

3 9

3 8

3 7

3 6

3 5

3 4

3 3

3 2

3 1

3 0

2 9

2 8

2 7

2 6

2 5

P B 5

P B 4

P A 3

P A 2

P A 1

P A 0

P B 3

P B 2

P B 1 / B Z

P B 0 / B Z

P E 3

P E 2

P E 1

P E 0

P D 7

P D 6

P D 5

P D 4

V S S

I N T

T M R 0

P C 0

P C 1

P C 2

H T 4 8 R 7 0 A - 1 / H T 4 8 C 7 0 - 1

P B 6

P B 7

P A 4

P A 5

P A 6

P A 7

O S C 2 / P G 2

O S C 1 / P G 1

V D D

R E S

P C 5

P C 4

P C 3

P C 2

P B 6

P B 7

P A 4

P A 5

P A 6

P A 7

P F 0

P F 1

P F 2

P F 3

O S C 2

O S C 1

V D D

R E S

T M R 1

P D 3

P D 2

P D 1

P D 0

P C 7

P C 6

P C 5

P C 4

P C 3

Page 16

P B 1 / B Z

P B 0 / B Z

V S S

P A 1

P A 0

P E 7

P E 6

P E 5

P E 4

P B 3

P B 2

P E 3

P E 2

P E 1

P E 0

P D 7

P D 6

P D 5

P D 4

P G 5

P G 4

P A 2

P A 3

6 4 6 3 6 2 6 1 6 0 5 25 35 45 55 65 75 85 9

1 0

1 1

1 2

1 3

1 4

1 5

1 6

1 7

1 8

1 9

2 0 2 1 2 2 2 3 2 4 3 23 13 02 92 82 72 62 5

T M R 0

I N T

P G 0

P G 1

P G 7

P G 6

P B 4

P B 5

H T 4 8 R 7 0 A - 1

H T 4 8 C 7 0 - 1

6 4 Q F P - A

P G 2

P C 1

P C 0

P G 3

I/O Type MCU

P B 6

P B 7

P A 4

P A 5

P A 6

5 1

P A 7

5 0

P F 0

4 9

P F 1

4 8

P F 2

P F 3

4 7

O S C 2

4 6

O S C 1

4 5

P F 4

4 4

P F 5

4 3

P F 6

4 2

P F 7

4 1

V D D

4 0

R E S

3 9

T M R 1

3 8

P D 3

3 7

P D 2

3 6

P D 1

3 5

P D 0

3 4

P C 7

3 3

P C 6

P C 5

P C 4

P C 3

P C 2

Note The pin compatibility features of the microcontroller SKDIP/SOP packages allow for straightfor

ward upgrading to devices of higher functionality with minimal changes to application hardware.

Pin Description

HT48R10A-1/HT48C10-1

Pin Name I/O

PA0~PA7 I/O

PB0/BZ PB1/BZ PB2~PB7

Configuration

Schmitt Trigger

I/O

I/O or BZ/BZ

Option

Pull-high Wake-up

Pull-high

Description

Bidirectional 8-bit input/output port. Each bit can be configured as a wake-up input by configuration option. Software instructions determine if the pin is a CMOS output or input. Configuration options determine if all pins on this port have pull-high resistors and if the inputs are Schmitt Trigger or non Schmitt Trigger.

Bidirectional 8-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt Trigger in put. A configuration option determines if all pins on this port have pull-high resistors. Pins PB0 and PB1 are pin-shared with BZ and BZ

, respectively.

Page 17

Chapter 1 Hardware Structure

Pin Name I/O

PC0/INT PC1/TMR PC2

OSC1/PC3 OSC2/PC4IO

RES I

VDD

VSS

Note 1. Each pin on PA can be programmed through a configuration option to have a wake-up function.

2. Individual pins cannot be selected to have pull-high resistors. If the pull-high configuration is chosen for a particular port, then all input pins on this port will be connected to pull-high resistors.

Configuration

Option

I/O Pull-high

Pull-high

Crystal or RC or

Int. RC+I/O or

Int. RC+RTC

¾¾

Description

Bidirectional 3-bit input/output port. Software instructions de termine if the pin is a CMOS output or Schmitt Trigger input. A configuration option determines if all pins on this port have pull-high resistors. Pin PC0 is pin-shared with external inter rupt pin INT The externalinterrupt is activated on a high tolow transition.

OSC1, OSC2 are connected to an external RC network or external Crystal (determined by configuration option) for the internal system clock. For external RC system clock op eration, OSC2 is an output pin for 1/4 system clock. These two pins can also be optioned as an RTC oscillator (32768Hz) orI/O lines. In these two cases, the system clock comes from an internal RC oscillator whose nominal fre quency at 5V has 4 options, 3.2MHz, 1.6MHz, 800kHz, 400kHz. If the pins are used as normal I/O pins, then pull-high options are available. If used as oscillator pins, bits PC3 and PC4 will be free for use by the application pro gram. In this case the pull-high options are disabled.

Schmitt Trigger reset input. Active low.

Positive power supply

Negative power supply, ground

and PC1 shared with external timer pin TMR.

HT48R30A-1/HT48C30-1

Pin Name I/O

PA0~PA7 I/O

PB0/BZ PB1/BZ PB2~PB7

Configuration

Schmitt Trigger

I/O

I/O or BZ/BZ

Option

Pull-high Wake-up

Pull-high

Description

, respectively.

Page 18

I/O Type MCU

Pin Name I/O

PC0/TMR PC1~PC5

PG0/INT I/O Pull-high

OSC1/PG1 OSC2/PG2IO

RES I

VDD

VSS

Configuration

Option

I/O Pull-high

Pull-high

Crystal or RC or

Int. RC+I/O or

Int. RC+RTC

¾¾

Description

Bidirectional 6-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt Trigger in put. A configuration option determines if all pins on this port have pull-high resistors. PC0 is pin-shared with external timer pin TMR.

Bidirectional 1-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt Trigger in put. A configuration option determines if the pin has a pull-high resistor. PG0 is pin-shared with external interrupt

. Theexternal interrupt input is activated on a high to

pin INT low transition.

OSC1, OSC2 are connected to an external RC network or external Crystal (determined by configurations option) for the internal system clock. For external RC system clock op eration, OSC2 is an output pin for 1/4 system clock. These two pins can also be optioned as an RTC oscillator (32768Hz) or I/O lines. In these two cases, the system clock comes from an internal RC oscillator whose nominal frequency at 5V has 4 options, 3.2MHz, 1.6MHz, 800kHz, 400kHz. If the pins are used as normal I/O pins, then pull-high options are available. If used as oscillator pins, bits PG1and PG2 will be free for use by the application pro gram. In this case the pull-high options are disabled.

Schmitt Trigger reset input. Active low.

Positive power supply

Negative power supply, ground

Note 1. Eachpin on PA can be programmed through a configuration option to have a wake-up function.

3. PinsPC1 and PC3~PC5 only exist on the 28-pin package. On the 24-pin package, these pins are not available.

HT48R50A-1/HT48C50-1

Pin Name I/O

PA0~PA7 I/O

Configuration

Option

Pull-high Wake-up

Schmitt Trigger

Description

Bidirectional 8-bit input/output port. Each bit can be config ured as a wake-up input by configuration option. Software instructions determine if the pin is a CMOS output or input. Configuration optionsdetermine if all pins on this port have pull-high resistors and if the inputs are Schmitt Trigger or non Schmitt Trigger.

Page 19

Chapter 1 Hardware Structure

Pin Name I/O

PB0/BZ PB1/BZ PB2~PB7

PC0/TMR0 PC5/TMR1 PC1~PC4 PC6~PC7

PD0~PD7 I/O Pull-high

PG0/INT I/O Pull-high

OSC1/PG1 OSC2/PG2IO

RES I

VDD

VSS

Configuration

Option

I/O

I/O Pull-high

Pull-high

I/O or BZ/BZ

Pull-high

Crystal or RC or

Int. RC+I/O or

Int. RC+RTC

¾¾

Description

Bidirectional 8-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine if all pins on this port have pull-high resistors.

Bidirectional 1-bit input/output ports. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. A configuration option determines if the pin has a pull-high resistor. PG0 is pin-shared with external interrupt pin INT

OSC1, OSC2 are connected to an external RC network or external Crystal (determined by configurations option) for the internal system clock. For external RC system clock operation, OSC2 is an output pin for 1/4 system clock. These two pins can also be optioned as an RTC oscillator (32768Hz) or I/O lines. In these two cases, the system clock comes from an internal RC oscillator whose nominal frequency at 5V has 4 options, 3.2MHz, 1.6MHz, 800kHz, 400kHz. If the pins are used as normal I/O pins, then pull-high options are available. If used as oscillator pins, bits PG1 and PG2 will be free for use by the application program. In this case the pull-high options are disabled.

Schmitt Trigger reset input. Active low.

Positive power supply

Negative power supply, ground

, respectively.

Note 1. Eachpin on PA can be programmed through a configuration option to have a wake-up function.

2. Individual pins cannot be selected to have pull-high resistors. If the pull-high configuration is chosen fora particular port, then all input pinson this port will be connected to pull-high resistors.

3. Onthe 48-pin package Port C has no shared pins. All of Port C pins exist as I/Os as the TMR0 and TMR1 are independent pins.

4. Pins PC6 and PC7 only exist on the 48-pin package.

5. Port D is only present on the 48-pin package.

Page 20

HT48R70A-1/HT48C70-1

Pin Name I/O

PA0~PA7 I/O

PB0/BZ PB1/BZ PB2~PB7 PC0~PC7 PD0~PD7 PE0~PE7 PF0~PF7 PG0~PG7

INT I

TMR0 I

TMR1 I

OSC1 OSC2

RES I

VDD

VSS

Configuration

Option

Pull-high Wake-up

Schmitt Trigger

Pull-high

I/O

I/O or BZ/BZ

IOCrystal or RC or

Int. RC+RTC

¾¾

I/O Type MCU

Description

Bidirectional 8-bit input/output port. Each bit can be config ured as a wake-up input by configuration option. Software instructions determine if the pin is a CMOS output or input. Configuration options determine if all pins on this port have pull-high resistors and if the inputs are Schmitt Trigger or non Schmitt Trigger.

Bidirectional 8-bit input/output ports. Software instructions determine if the pin is a CMOS output or Schmitt Trigger in put. Aconfiguration option for each port determines if all pins on the relevant port have pull-high resistors. Pins PB0 and PB1 are pin-shared with BZ and BZ

External interrupt Schmitt Trigger input. Edge triggered on high to low transition.

Schmitt Trigger input for Timer/Event Counter 0

Schmitt Trigger input for Timer/Event Counter 1

Schmitt Trigger reset input. Active low.

Positive power supply

Negative power supply, ground

respectively.

Note 1. Eachpin on PA can be programmed through a configuration option to have a wake-up function.

2. Individual pins cannot be selected to have pull-high resistors. If the pull-high configuration is

chosen fora particular port, then all input pinson this port will be connected to pull-high resistors.

3. Pins PE4~PE7 and pins PF4~PF7 only exist on the 64-pin package.

4. Port PG only exists on the 64-pin package.

Page 21

Absolute Maximum Ratings

Supply Voltage ........................................................................................... VSS-0.3V to VSS+6.0V

Input Voltage ............................................................................................. V

Storage Temperature ........................................................................................... -50°Cto125°C

Operating Temperature .......................................................................................... -40°Cto85°C

These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to ex treme conditions may affect device reliability.

Chapter 1 Hardware Structure

-0.3V to VDD+0.3V

D.C. Characteristics

Symbol Parameter

DD1

DD2

DD3

STB1

STB2

STB3

IL1

IH1

IL2

IH2

LVR

Operating Voltage

Operating Current (Crystal OSC)

Operating Current (RC OSC)

Operating Current (Crystal OSC)

Standby Current (WDT Enabled, RTC Off)

Standby Current (WDT Disabled, RTC Off)

Standby Current (WDT Disabled, RTC On)

Input Low Voltage for I/O Ports

Input High Voltage for I/O Ports

Input Low Voltage (RES)

Input High Voltage (RES)

Low Voltage Reset

I/O Port Sink Current

I/O Port Source Current

Test Conditions

Conditions

=4MHz

SYS

=8MHz

SYS

No load, f

=4MHz

SYS

No load, f

=4MHz

SYS

No load, f

=8MHz

SYS

No load, system HALT

¾¾

LVR enabled 2.7 3 3.3 V

=0.1V

=0.9V

Min. Typ. Max. Unit

2.2

3.3

0.6 1.5 mA

0.8 1.5 mA

2.5 4 mA

¾¾

0.7V

0.9V

10 20

-2 -4 ¾

-5 -10 ¾

24mA

35mA

5.5 V

0.3V

0.4V

Ta=25°C

Page 22

I/O Type MCU

Symbol Parameter

A.C. Characteristics

Symbol Parameter

SYS1

SYS2

SYS3

TIMER

WDTOSC

WDT1

WDT2

WDT3

RES

SST

LVR

INT

= 1/f

SYS

SYS1

Pull-high Resistance

System Clock (Crystal OSC)

System Clock (RC OSC)

System Clock (Internal RC OSC)

Timer I/P Frequency (TMR)

Watchdog Oscillator Period

Watchdog Time-out Period (WDT OSC)

Watchdog Time-out Period (System Clock)

Watchdog Time-out Period (RTC OSC)

External Reset Low Pulse Width

System Start-up Timer Period

Low Voltage Width to Reset

Interrupt Pulse Width

, 1/f

or 1/f

SYS2

SYS3

Test Conditions

Conditions

Min. Typ. Max. Unit

40 60 80

10 30 50

Ta=25°C

Test Conditions

Conditions

2.2V~5.5V 400

3.3V~5.5V 400

2.2V~5.5V 400

3.3V~5.5V 400

3.2MHz 1800

1.6MHz 900

800kHz 450

400kHz 225

2.2V~5.5V 0

3.3V~5.5V 0

5V 8 17 33 ms

Without WDT prescaler

¾¾

Wake-up from

HALT

¾¾

Min. Typ. Max. Unit

4000 kHz

8000 kHz

4000 kHz

8000 kHz

5400 kHz

2700 kHz

1350 kHz

675 kHz

4000 kHz

8000 kHz

45 90 180

32 65 130

11 23 46 ms

1024

7.812

¾¾ms

1024

¾¾

¾¾ms

SYS

Note The internal RC system clock has a typical base frequency of 3.2MHz at 5V. The other internal RC

system typical clock frequencies of 1.6MHz, 800kHz and 400kHz at 5V are division ratios of this

3.2MHz base frequency.

Page 23

System Architecture

A key factor in the high performance features of the Holtek range of I/O Type microcontrollers is at tributed to the internal system architecture. The range of devices take advantage of the usual fea tures found within RISC microcontrollers providing increased speed of operation and enhanced performance. The pipelining scheme is implemented in such a way that instruction fetching and in struction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all operations of the instruction set. It carries out arithmetic operations, logic operations, rotation, increment, dec rement, branch decisions etc. The internal datapath is simplified by moving data through the Accu mulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with addi tional architectural features ensure that a minimum of external components is required to provide a functional I/O control system with maximum reliability and flexibility. This makes these devices suitable for low cost, high-volume production for controller applications requiring from 1K up to 8K words of program memory and from 64 to 224 bytes of data storage.

Clocking and Pipelining

The mainsystem clock, derived from either a Crystal/Resonator or RC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecu tive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the con tents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute.

Chapter 1 Hardware Structure

Note

When the RC oscillator is used, OSC2 is freed for use as a T1 phase clock synchronizing pin. This T1 phase clock has a frequency of f

O s c i l l a t o r C l o c k

( S y s t e m C l o c k )

P h a s e C l o c k T 1

P h a s e C l o c k T 2

P h a s e C l o c k T 3

P h a s e C l o c k T 4

P r o g r a m C o u n t e r

P i p e l i n i n g

F e t c h I n s t . ( P C )

E x e c u t e I n s t . ( P C - 1 )

/4 with a 1:3 high/low duty cycle.

SYS

P C P C + 1 P C + 2

F e t c h I n s t . ( P C + 1 )

E x e c u t e I n s t . ( P C )

F e t c h I n s t . ( P C + 2 )

E x e c u t e I n s t . ( P C + 1 )

System Clocking and Pipelining

Page 24

I/O Type MCU

For instructions involving branches, such as jump or call instructions, two machine cycles are re quired to complete instruction execution. An extra cycle is required as the program takes one cy cle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in tim ing sensitive applications

D E L A Y :

M O V A , [ 1 2 H ]

C A L L D E L A Y

C P L [ 1 2 H ]

N O P

F e t c h I n s t . 1 E x e c u t e I n s t . 1

F e t c h I n s t . 2

E x e c u t e I n s t . 2

F e t c h I n s t . 3

F l u s h P i p e l i n e

F e t c h I n s t . 6 E x e c u t e I n s t . 6

F e t c h I n s t . 7

Program Counter

During program execution, the Program Counter is used to keep track of the address of the next in struction to be executed. It is automatically incremented by one each time an instruction is exe cuted except for instructions such as JMP or CALL that demand a jump to a non-consecutive Program Memory address. For the I/O series of microcontrollers, note that the Program Counter width varies with the Program Memory capacity depending upon which device is selected. How ever, it must be noted that only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by user.

When executing instructions requiring jumps to non-consecutive addresses such as a jump in struction, a subroutine call, interrupt or reset etc., the microcontroller manages program control by loading the required address into the Program Counter. For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained.

The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and is a readable and writable register. By transferring data directly into this register a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted.

Note

The lower byte of the Program Counter is fully accessible under program control. The use of the PCL might cause program branching, so an extra cycle is needed to pre-fetch. Further information on the PCL register can be found in the Special Function Register section.

Page 25

Chapter 1 Hardware Structure

Mode

Initial Reset 0 0 0 0000000000

External Interrupt 0 0 0 0000000100

Timer/Event Counter 0 Overflow 0 0 0 0000001000

Timer/Event Counter 1 Overflow 0 0 0 0000001100

Skip Program Counter + 2

Loading PCL PC12 PC11 PC10 PC9 PC8 @7 @6 @5 @4 @3 @2 @1 @0

Jump, Call Branch #12 #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0

Return from Subroutine S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

Program Counter Bits

Note 1. PC12~PC8: Current Program Counter bits

2. @7~@0: PCL bits

3. #12~#0: Instruction code bits

4. S12~S0: Stack register bits

5. For the HT48R70A-1/HT48C70-1, the Program Counter is 13 bits wide, i.e. from b12~b0.

6. ForHT48R50A-1/HT48C50-1, since its Program Counter is 12 bits wide, the b12 column in the table is not applicable.

7. For the HT48R30A-1/HT48C30-1, since its Program Counter is 11 bits wide, the b11 and b12 columns in the table are not applicable.

8. Forthe HT48R10A-1/HT48C10-1, since its Program Counter is 10 bits wide, the b10, b11 and b12 columns in the table are not applicable.

9. The Timer/Event Counter 1 Overflow row is available only for HT48R50A-1/HT48C50-1 and HT48R70A-1/HT48C70-1.

10. For the HT48R10A-1/HT48C10-1 and HT48R30A-1/HT48C30-1 the Timer/Event Counter 0

represents the single timer, known as TMR.

Stack

This is a special part of the memory which is used to save the contents of the Program Counter only.The stack can have between 4, 6 or 16 levels depending upon which deviceis selected and is neither partof the data nor part of the program space, and is neither readable nor writable. The activated level is indexed by the stack pointer (SP) and is neither readable nor writable. At a subrou tine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the Program Counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack.

If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be re corded but the acknowledge signal will be inhibited. When the stack pointer is decremented (by RET or RETI), the interrupt will be serviced. This feature prevents stack overflow allowing the pro grammer to use the structure more easily. However, when the stack is full, a CALL subroutine in struction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching.

Page 26

P r o g r a m C o u n t e r

I/O Type MCU

T o p o f S T A C K

S t a c k

P o i n t e r

B o t t o m o f S T A C K

S t a c k L e v e l 1

S t a c k L e v e l 2

S t a c k L e v e l 3

S t a c k L e v e l N

P r o g r a m

M e m o r y

Note 1. For the HT48R10A-1/HT48C10-1 and HT48R30A-1/HT48C30-1, N=4, i.e. 4 levels ofstack available.

2. For the HT48R50A-1/HT48C50-1, N=6, i.e. 6 levels of stack available.

3. For the HT48R70A-1/HT48C70-1, N=16, i.e. 16 levels of stack available.

Arithmetic and Logic Unit - ALU

The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main microcontroller data bus the ALU receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or opera tions may result in carry, borrow or other status changes, the status register will be correspond ingly updated to reflect these changes. The ALU supports the following functions:

· Arithmetic operations ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA

· Logic operations AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA

· Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC

· Increment and Decrement INCA, INC, DECA, DEC

· Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI

Program Memory

The Program Memory is the location where the user code or program is stored. For microcontrollers, two types of Program Memory are usually supplied. The first type is the OneTime Programmable (OTP) Memory where users can program their application code into the de vice. Devices with OTP memory are denoted by having an ²R² within their device name. By using the appropriate programming tools, OTP devices offer users the flexibility to freely develop their applications which may be useful during debug or for products requiring frequent upgrades or pro gram changes. OTP devices are also applicable for use in applications that require low or medium volume production runs. The other type of memory is the mask ROM memory, denoted by having a ²C² within the device name. These devices offer the most cost effective solutions for high vol ume products.

Page 27

Chapter 1 Hardware Structure

Organization

The Program Memory has a capacity of 1K by 14 to 8K by 16 bits depending upon which device is selected. The Program Memory is addressed by the Program Counter and also contains data, ta ble information and interrupt entries. Table data, which can be setup in any location within the Pro gram Memory, is addressed by separate table pointer registers.

The following diagram shows the Program Memory for the I/O Type microcontroller series.

0 0 0 H

0 0 4 H

0 0 8 H

0 0 C H

3 F F H

4 0 0 H

7 F F H

8 0 0 H

F F F H

1 0 0 0 H

1 F F F H

H T 4 8 R 1 0 A - 1 H T 4 8 C 1 0 - 1

I n i t i a l i z a t i o n

V e c t o r

E x t e r n a l

I n t e r r u p t V e c t o r

T i m e r / C o u n t e r

I n t e r r u p t V e c t o r

H T 4 8 R 3 0 A - 1 H T 4 8 C 3 0 - 1

I n i t i a l i z a t i o n

V e c t o r

E x t e r n a l

I n t e r r u p t V e c t o r

T i m e r / C o u n t e r

I n t e r r u p t V e c t o r

1 4 b i t s1 4 b i t s

H T 4 8 R 5 0 A - 1 H T 4 8 C 5 0 - 1

I n i t i a l i z a t i o n

V e c t o r

E x t e r n a l

I n t e r r u p t V e c t o r

T i m e r / C o u n t e r 0

I n t e r r u p t V e c t o r

T i m e r / C o u n t e r 1

I n t e r r u p t V e c t o r

H T 4 8 R 7 0 A - 1 H T 4 8 C 7 0 - 1

I n i t i a l i z a t i o n

V e c t o r

E x t e r n a l

I n t e r r u p t V e c t o r

T i m e r / C o u n t e r 0

I n t e r r u p t V e c t o r

T i m e r / C o u n t e r 1

I n t e r r u p t V e c t o r

1 6 b i t s1 5 b i t s

N o t I m p l e m e n t e d

Special Vectors

Within the Program Memory, certain locations are reserved for special usage such as reset and interrupts.

· Location 000H

This vector is reserved for use by the chip reset for program initialization. After a chip reset is initiated, the program will jump to this location and begin execution.

· Location 004H

This vector is used by the external interrupt. If the external interrupt pin on the device goes low, the program will jump to this location and begin execution if the external interrupt is enabled and the stack is not full.

Location 008H This internal interrupt vector is used by the Timer/Event Counter. If a counter overflow occurs, the program will jump to this location and begin execution if the internal interrupt is enabled and the stack is not full. For the HT48R50A-1/HT48C50-1 and HT48R70A-1/HT48C70-1, the Timer/Event Counter is known as Timer/Event Counter 0.

Location 00CH This internal interrupt vector is used by the Timer/Event Counter. If a counter overflow occurs, the program will jump to this location and begin execution if the internal interrupt is enabled and the stack is not full. This vector is available for the HT48R50A-1/HT48C50-1 and HT48R70A-1/ HT48C70-1 only. The Timer/Event Counter is known as Timer/Event Counter 1.

Page 28

I/O Type MCU

Look-up Table

Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, the table pointer must first be setup by placing the lower-order address of the look-up data to be retrieved in the Table Pointer Register TBLP. This register defines the lower 8-bit address of the look-up table. After setting up the table pointer, the table data can be retrieved from the current Program Memory page or last Program Memory page using the ²TABRDC [m]² or ²TABRDL [m]² instructions respectively. When these instructions are executed, the lower order table byte from the Program Memory will be transferred to the user de fined Data Memory register [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will be read as ²0².

The following diagram illustrates the addressing/data flow of the look-up table:

P r o g r a m C o u n t e r h i g h b y t e

T B L P

T B L H S p e c i f i e d b y [ m ]

H i g h b y t e o f t a b l e c o n t e n t s

P r o g r a m

M e m o r y

L o w b y t e o f t a b l e c o n t e n t s

Table Program Example

The following example shows how the table pointer and table data is defined and retrieved from the HT48R10A-1 I/O microcontroller. This example uses raw table data located in the last page which is stored there using the ORG statement. The value at this ORG statement is ²300² hex which refers to the start address of the last page within the 1K Program Memory of the HT48R10A-1 microcontroller. The table pointer is setup here to have an initial value of 06 hex. This will ensure that the first data read from the data table will be at the Program Memory address 306 hex or 6 locations after the start of the last page. Note that the value for the table pointer is referenced to the first address of thepresent page if the ²TABRDC [m]² instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the ²TABRDL [m]² instruction is executed.

tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2

: :

mov a,06h ; initialize table pointer - note that this address is

mov tblp,a ; to the last page or present page

: :

tabrdl tempreg1 ; transfers value in table referenced by table pointer

; referenced

; to tempregl ; data at prog. memory address 306H transferred to ; tempreg1 and TBLH

Page 29

Chapter 1 Hardware Structure

dec tblp ; reduce value of table pointer by one

tabrdl tempreg2 ; transfers value in table referenced by table pointer

: :

org 300h ; sets initial address of last page (for HT48R10A-1)

dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh

: :

Because the TBLH register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use table read instruc tions. If using the table read instructions, the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is recom mended that simultaneous use of the table read instructions should be avoided. However, in situa tions where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions re quire two instruction cycles to complete their operation.

Instruction

TABRDC

TABRDL

[m] PC12 PC11 PC10 PC9 PC8 @7 @6 @5 @4 @3 @2 @1 @0

[m]11111@7@6@5@4@3@2@1@0

; to tempreg2 ; data at prog.memory address 305H transferred to ; tempreg2 and TBLH

; in this example the data ²1A² is transferred to tempreg1 ; and data ²0F² to register tempreg2 ; the value ²0² will be transferred to the high byte

; register TBLH

Table Location Bits

b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

Note 1. PC12~PC8: Current Program Counter bits

Data Memory

2. @7~@0: Table Pointer TBLP bits

3. For HT48R70A-1/HT48C70-1, the Table address location is 13 bits, i.e. from b12~b0.

4. For HT48R50A-1/HT48C50-1, the Table address location is 12 bits, i.e. from b11~b0.

5. For HT48R30A-1/HT48C30-1, the Table address location is 11 bits, i.e. from b10~b0.

6. For HT48R10A-1/HT48C10-1, the Table address location is 10 bits, i.e. from b9~b0.

The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. Divided into two sections, the first of these is an area of RAM where special function registers are located. These registers have fixed locations and are neces sary for correct operation of the device. Many of these registers can be read from and written to di rectly under program control, however, some remain protected from user manipulation. The second area of Data Memory is reserved for general purpose use. All locations within this area are read and write accessible under program control.

Page 30

I/O Type MCU

Organization

The two sections of Data Memory, the Special Purpose and General Purpose Data Memory are lo cated at consecutive locations. All are implemented in RAM and are 8 bits wide but the length of each memory section is dictated by the type of microcontroller chosen. The start address of the Data Memory for all devices is the address 00H. The last Data Memory address is 7FH for the HT48R10A-1/HT48C10-1 and HT48R30A-1/HT48C30-1 devices, and FFH for the HT48R50A-1/ HT48C50-1 and HT48R70A-1/HT48C70-1 devices. Registers which are common to all microcontrollers, such as ACC, PCL, etc., have the same Data Memory address.

0 0 H

S p e c i a l P u r p o s e D a t a M e m o r y

1 F H

2 0 H

G e n e r a l P u r p o s e D a t a M e m o r y C a p a c i t y i s d e v i c e d e p e n d e n t

7 F H / F F H

Note

Most of the Data Memory bits can be directly manipulated using the ²SET [m].i² and ²CLR [m].i² with the exception of a few dedicated bits. The Data Memory can also be accessed through the memory pointer register MP.

General Purpose Data Memory

All microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. It is this area of RAM memory that is known as General Purpose Data Memory. This area of Data Memory is fully accessible by the user program for both read and

write operations. By using the ²SET [m].i² and ²CLR [m].i² instructions individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the Data Memory.

The following diagram shows a General Purpose Data Memory Organization Map of the I/O Type microcontroller:

2 0 H

4 0 H

7 F H

H T 4 8 R 1 0 A - 1 H T 4 8 C 1 0 - 1

2 0 H

7 F H

H T 4 8 R 3 0 A - 1 H T 4 8 C 3 0 - 1

2 0 H

6 0 H

F F H

H T 4 8 R 5 0 A - 1 H T 4 8 C 5 0 - 1

2 0 H

F F H

H T 4 8 R 7 0 A - 1 H T 4 8 C 7 0 - 1

G e n e r a l P u r p o s e D a t a M e m o r y

: U n u s e d

R e a d a s " 0 0 "

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Chapter 1 Hardware Structure

Special Purpose Data Memory

This area of Data Memory is where registers, necessary for the correct operation of the microcontroller, are stored. Most of the registers are both readable and writable but some are pro tected and are read only, the details of which are located under the relevant Special Function Reg ister section. Note that for locations that are unused, any read instruction to these addresses will

return the value ²00H².

The following diagram shows a detailed Special Purpose Data Memory Organization Map of the I/O Type microcontroller:

0 0 H 0 1 H 0 2 H 0 3 H 0 4 H 0 5 H 0 6 H 0 7 H 0 8 H

0 9 H 0 A H 0 B H 0 C H 0 D H 0 E H 0 F H

1 0 H

1 1 H

1 2 H

1 3 H

1 4 H

1 5 H

1 6 H

1 7 H

1 8 H

1 9 H 1 A H 1 B H 1 C H 1 D H 1 E H 1 F H

H T 4 8 R 1 0 A - 1 H T 4 8 C 1 0 - 1

I A R

M P

A C C

P C L T B L P T B L H

W D T S

S T A T U S

I N T C

T M R

T M R C

P A

P A C

P B

P B C

P C

P C C

H T 4 8 R 3 0 A - 1 H T 4 8 C 3 0 - 1

I A R M P

A C C

P C L T B L P T B L H

W D T S

S T A T U S

I N T C

T M R

T M R C

P A

P A C

P B

P B C

P C

P C C

P G

P G C

H T 4 8 R 5 0 A - 1 H T 4 8 C 5 0 - 1

I A R 0 M P 0 I A R 1 M P 1

A C C

P C L T B L P T B L H

W D T S

S T A T U S

I N T C

T M R 0 T M R 0 C T M R 1 H

T M R 1 L

T M R 1 C

P A

P A C

P B

P B C

P C

P C C

P D

P D C

P G

P G C

H T 4 8 R 7 0 A - 1 H T 4 8 C 7 0 - 1

I A R 0 M P 0 I A R 1 M P 1

A C C

P C L T B L P T B L H

W D T S

S T A T U S

I N T C

T M R 0 H T M R 0 L T M R 0 C T M R 1 H T M R 1 L T M R 1 C

P A

P A C

P B

P B C

P C

P C C

P D

P D C

P E

P E C

P F

P F C

P G

P G C

S p e c i a l P u r p o s e D a t a M e m o r y

: U n u s e d

R e a d a s " 0 0 "

Special Function Registers

To ensure successful operation of the microcontroller, certain internal registers are implemented in the Data Memory area. These registers ensure correct operation of internal functions such as timers, interrupts, watchdog, etc. as well as external functions such as I/O data control. The loca tion of these registers within the Data Memory begins at the address 00H. Any unused Data Mem ory locations between these special function registers and the point where the General Purpose Memory beginsis reserved for future expansion purposes, attempting to read data from these loca tions will return a value of 00H.

Page 32

I/O Type MCU

Indirect Addressing Registers - IAR, IAR0, IAR1

The method of indirect addressing allows data manipulation using memory pointers instead of the usual direct memory addressing method where the actual memory address is defined. Any action on the Indirect Addressing Registers will result in corresponding read/write operations to the mem ory location specified by the corresponding memory pointer. For the HT48R10A-1/HT48C10-1 and HT48R30A-1/HT48C30-1 devices, one Indirect Addressing Register, IAR, and one Memory Pointer, MP, is provided. For the HT48R50A-1/HT48C50-1 and HT48R70A-1/HT48C70-1 devices, two Indirect Addressing Registers, IAR0 and IAR1, and two Memory Pointers, MP0 and MP1, are provided. Note that these Indirect Addressing Registers are not physically implemented and that reading the Indirect Addressing Registers directly will return a result of 00H and writing to the regis ters indirectly will result in no operation.

Memory Pointers - MP, MP0, MP1

For the HT48R10A-1/HT48C10-1 and HT48R30A-1/HT48C30-1 devices, one memory pointer known as MP is provided, whereas for the HT48R50A-1/HT48C50-1 and HT48R70A-1/ HT48C70-1 devices, two memory pointers known as MP0 and MP1 are provided. These memory pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller is directed to is the address specified by the related Memory Pointer.

Note

For the HT48R10A-1/HT48C10-1 and HT48R30A-1/HT48C30-1 devices, bit 7 of the memory pointers are not implemented. However, it must be noted that when the memory pointers in these

devices are read, a value of ²1² will be read.

The following example shows how to clear a section of four RAM locations already defined as locations adres1 to adres4.

data .section ¢data¢ adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ?

code .section at 0 ¢code¢ org 00h

start:

mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; Accumulator loaded with first RAM address mov mp,a ; setup memory pointer with first RAM address

loop:

clr [00h] ; clear the data at address defined by mp inc mp ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop

continue:

The important point to note here is that in the example shown above, no reference is made to spe cific RAM addresses.

Page 33

Chapter 1 Hardware Structure

Accumulator - ACC

The Accumulator is central to the operationof any microcontroller and is closely related with opera tions carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calcula tion or logical operation such as addition, subtraction, shift, etc. to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the tempo rary storage function of the Accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the Accumula tor as no direct transfer between two registers is permitted.

Program Counter Low Register - PCL

To provide additional program control functions, the low byte of the Program Counter is made ac cessible to programmers by locating it within the Special Purpose area of the Data Memory. By ma nipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted.

Look-up Table Registers - TBLP, TBLH

These two special function registers are used to control operation of the look-up table which is stored inthe Program Memory. TBLP is the table pointer and indicates the location where the table is located. Its value must be setup before any table read commands are executed. Its value can be changed, for example using the INC or DEC instructions, allowing for easy table data pointing and reading. TBLHis the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location.

Watchdog Timer Register - WDTS

The Watchdog feature of the microcontroller provides an automatic reset function giving the microcontroller a means of protection against spurious jumps to incorrect Program Memory addresses. To implement this, a timer is provided within the microcontroller which will issue a reset command when its value overflows. To provide variable Watchdog Timer reset times, the Watchdog Timer clock source can be divided by various division ratios, the value of which is set us ing the WDTS register. By writing directly to this register, the appropriate division ratio for the Watchdog Timer clock source can be setup. Note that only the lower 3 bits are used to set division ratios between 1 and 128, the remaining 5 bits of the 8-bit register can be used by programmers for other purposes.

Status Register - STATUS

This 8-bit register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). It also records the status infor mation and controls the operation sequence.

Page 34

I/O Type MCU

With the exception of the TO and PDF flags, bits in the status register can be altered by in structions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different re sults due to the different instruction operations.The TO flag can be affected only by a system power-up, a WDT time-out or by executing the ²CLR WDT² or ²HALT² instruction. The PDF flag is affected only by executing the ²HALT² or ²CLR WDT² instruction or during a system power-up.

The Z, OV, AC and C flags generally reflect the status of the latest operations.

C is set if an operation results in a carry during an addition operation or if a borrow does not take

place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the

high nibble into the low nibble in subtraction; otherwise AC is cleared. Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.

OV is set if an operation results in a carry into the highest-order bit but not a carry out of the

highest-order bit, or vice versa; otherwise OV is cleared.

PDF is cleared by a system power-up or executing the ²CLR WDT² instruction. PDF is set by

executing the ²HALT² instruction. TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is

set by a WDT time-out.

In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it.

b 7 b 0

T O P D F O V Z A C C

S T A T U S R e g i s t e r

A r i t h m e t i c / l o g i c o p e r a t i o n f l a g s

C a r r y F l a g A u x i l i a r y C a r r y F l a g Z e r o F l a g O v e r f l o w F l a g

S y s t e m m a n a g e m e n t f l a g s

P o w e r d o w n f l a g W a t c h d o g t i m e - o u t f l a g

N o t i m p l e m e n t e d , r e a d a s " 0 "

Interrupt Control Register - INTC

This 8-bit register, known as the INTC register, controls the operation of both external and internal interrupts. By setting various bits within this register using standard bit manipulation instructions, the enable/disable function of the external interrupt and each of the internal interrupts can be inde pendently controlled. A master interrupt bit within this register, the EMI bit, acts like a global en able/disable and is used to set all of the interrupt enable bits on or off. This bit is cleared when an interrupt routineis entered to disable further interrupt andis set by executing the ²RETI² instruction.

Note

In situations where other interrupts may require servicing within present interrupt service routines, the EMIbit can be manually set by the program after the present interrupt service routine has been entered.

Page 35

Chapter 1 Hardware Structure

Timer/Event Counter Registers

Depending upon which device is selected, all devices contain one or two integrated Timer/Event Counters of either 8-bit or 16-bit size. For devices with a single 8-bit timer counter, an associated register, known as TMR, is the location where the timer value is located. An associated control reg ister, known as TMRC, contains the setup information for the TMR register. For devices with two timers, the individual timers are known as TMR0 and TMR1 with their respective control registers known as TMR0C and TMR1C. In the case of 16-bit timers, the actual value stored in the timer re quires two bytes, a high byte and a low byte. These register pairs are known as TMR0L/TMR0H and TMR1L/TMR1H. Note that the timer registers can be directly written to in order to preload their contents with fixed data to allow different time intervals to be setup.

Input/Output Ports and Control Registers

Within the area of Special Function Registers, the I/O registers and their associated control regis ters play a prominent role. All I/O ports have a designated register correspondingly labeled as PA, PB, PC, etc. These labeled I/O registers are mapped to specific addresses within the Data Mem ory as shown in the Data Memory table which are used to transfer the appropriate output or input data on that port. With each I/O port there is an associated control register labeled PAC, PBC, PCC, etc. also mapped to specific addresses with the Data Memory. The control register specifies which pins of that port are set as inputs and which are set as outputs. To setup a pin as an input, the corresponding bit of the control register must be set high, for an output it must be set low. Dur ing program initialization, it is important to first setup the control registers to specify which pins are outputs and which are inputs before reading data from or writing data to the I/O ports. One flexible

feature of these registers is the ability to directly program single bits using the ²SET [m].i² and

²CLR [m].i² instructions. The ability to change I/O pins from output to input and vice-versa by ma nipulating specific bits of the I/O control registers during normal program operation is a useful feature of these devices.

Input/Output Ports

Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin fully under user program control, pull-high options for all pins and wake up options oncertain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities.

Depending upon which device or package is chosen, the microcontroller range provides from 21 to 56 bidirectional input/output lines labeled with port names PA, PB, PC, etc. These I/O ports are mapped to the Data Memory with specific addresses as shown in the Special Purpose Data Mem ory table. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of in

struction ²MOV A,[m]², where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten.

Pull-high Resistors

Many product applications require pull-high resistors for their switch inputs usually requiring the use ofan external resistor. To eliminate the need for theseexternal resistors, all I/O pins, when con figured as an input have the capability of being connected to an internal pull-high resistor. These

Page 36

I/O Type MCU

pull-high resistors are selectable via configuration option and are implemented using a weak PMOS transistor. Note that if the pull-high option is selected, then all I/O pins on that port will be connected to pull-high resistors, individual pins cannot be selected for pull-high resistor options.

Port A Wake-up

Each device has a HALT feature enabling the microcontroller to enter a power down mode and pre serve power, a feature that is important for battery and other low power applications. Various meth ods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port A pins from high to low. After a ²HALT² instruction forces the microcontroller into entering a HALT condition, the processor will remain idle or in a low-power state until the logic condition of the selected wake-up pin on Port A changes from high to low. This function is especially suitable for applications that can be woken up via external switches. Note that each pin on Port A can be se lected individually to have this wake-up feature.

I/O Port Control Registers

Each I/O line has its own control register (PAC, PBC, PCC, etc.) to control the input/output configu ration. With this control register, each CMOS output or Schmitt Trigger input with or without pull-high resistor structures can be reconfigured dynamically under software control. Each pin of the I/O ports is directly mapped to a bit in its associated port control register. For the I/O pin to func tion as an input, the corresponding bit of the control register must be written as a ²1². This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as a ²0², the I/O pin will be setup as a CMOS output. If the pin is cur rently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin.

Pin-shared Functions

The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be overcome. For some pins, the chosenfunction of the multi-function I/O pins is set by configuration options whilefor others the function is set by application program control.

Buzzer

The buzzer pins BZ and BZ pins, the correct hardware and software options must be selected.

External Interrupt Input

The externalinterrupt pin INT vice isused. However, forthe HT48R70A-1/HT48C70-1 devices, the external interrupt pin is an in dependent non shared pin. For this pin to operate as an external interrupt pin and not as a normal I/O pin, the corresponding external interrupt enable bits in the INTC interrupt control register must be correctly set. For applications not requiring an external interrupt input, with the exception of the HT48R70A-1/HT48C70-1 devices, the pin can be used as a normal I/O pin, however, to do this, the external interrupt enable bits in the INTC register must be disabled.

are pin-shared with I/O pins PB0 and PB1. If configured as buzzer

is pin-sharedwith the I/O pin PC0 or PG0depending upon which de

Page 37

Chapter 1 Hardware Structure

External Timer Clock Input

Each device contains either one or two timers depending upon which one is chosen. Each timer has an external input pin, which in the case of devices with a single timer, is known as TMR and in the case of devices with two timers are known as TMR0 and TMR1. For all devices with a single timer, the external input pin TMR is pin-shared with I/O pin PC0 or PC1. For devices with two tim ers, the external input pins TMR0 and TMR1 are pin-shared with pins PC0 and PC5 respectively or exist as independent non-shared pins depending upon which device and which package is se lected. If the timer input pins are shared pins and if they are to be configured as timer inputs, the corresponding control bits in the timer control register must be correctly set. These external timer pins, if they are shared pins, can be used as normal I/O pins for applications that donot require ex ternal timer inputs. For such applications the timer mode control bits in the timer control register must select the timer mode (internal clock source) to prevent the I/O from interfering with the timer counter operation.

D D

P A 0 ~ P A 7

* S c h m i t t T r i g g e r I n p u t O p t i o n

D a t a B u s

W r i t e C o n t r o l R e g i s t e r

C h i p R e s e t

R e a d C o n t r o l R e g i s t e r

W r i t e D a t a R e g i s t e r

R e a d D a t a R e g i s t e r

S y s t e m W a k e - u p

C o n t r o l B i t

C K

D a t a B i t

C K

P u l l - H i g h O p t i o n

M U X

W a k e - u p O p t i o n

D a t a B u s

W r i t e C o n t r o l R e g i s t e r

C h i p R e s e t

R e a d C o n t r o l R e g i s t e r

W r i t e D a t a R e g i s t e r

P B 0 D a t a B i t B Z ( P B 1 o n l y ) B Z ( P B 0 o n l y )

R e a d D a t a R e g i s t e r

PA Input/Output Ports

M U X

P u l l - H i g h O p t i o n

M U X

B Z O p t i o n

C o n t r o l B i t

C K

D a t a B i t

C K

PB0/PB1 Input/Output Ports

D D

P B 0 / B Z P B 1 / B Z

Page 38

I/O Type MCU

D D

P C 0 / I N T P G 0 / I N T

P C 0 / T M R P C 0 / T M R 0 P C 1 / T M R P C 5 / T M R 1 O S C 1 / P C 3 O S C 1 / P G 1

O S C 2 / P G 2

O S C 2 / P C 4

( H T 4 8 R 1 0 A - 1 / H T 4 8 C 1 0 - 1 ) ( H T 4 8 R 3 0 A - 1 / H T 4 8 C 3 0 - 1 , H T 4 8 R 5 0 A - 1 / H T 4 8 C 5 0 - 1 ) ( H T 4 8 R 3 0 A - 1 / H T 4 8 C 3 0 - 1 ) ( H T 4 8 R 5 0 A - 1 / H T 4 8 C 5 0 - 1 ) ( H T 4 8 R 1 0 A - 1 / H T 4 8 C 1 0 - 1 ) ( H T 4 8 R 5 0 A - 1 / H T 4 8 C 5 0 - 1 ) ( H T 4 8 R 1 0 A - 1 / H T 4 8 C 1 0 - 1 ) ( H T 4 8 R 3 0 A - 1 / H T 4 8 C 3 0 - 1 , H T 4 8 R 5 0 A - 1 / H T 4 8 C 5 0 - 1 ) ( H T 4 8 R 3 0 A - 1 / H T 4 8 C 3 0 - 1 , H T 4 8 R 5 0 A - 1 / H T 4 8 C 5 0 - 1 ) ( H T 4 8 R 1 0 A - 1 / H T 4 8 C 1 0 - 1 )

D a t a B u s

W r i t e C o n t r o l R e g i s t e r

C h i p R e s e t

R e a d C o n t r o l R e g i s t e r

W r i t e D a t a R e g i s t e r

R e a d D a t a R e g i s t e r

T M R / T M R 0 / T M R 1 ( P C 0 / P C 1 / P C 5 o n l y )

I N T ( P C 0 / P G 0 o n l y )

O S C 1 ( P C 3 / P G 1 o n l y ) O S C 2 ( P C 4 / P G 2 o n l y )

C o n t r o l B i t

C K

D a t a B i t

C K

M U X

P u l l - H i g h O p t i o n

PB2~PB7, PC, PD, PE, PF and PG Input/Output Ports

Oscillator

The system oscillator pins OSC1 and OSC2 are pin-shared with PC3 and PC4 on the HT48R10A-1/HT48C10-1 and pins PG1 and PG2 on the HT48R30A-1/HT48C30-1 and HT48R50A-1/HT48C50-1. On the HT48R70A-1/HT48C70-1 the oscillator pins are not pin-shared. The pin-shared functions are selected via configuration option. If chosen to function as I/O pins, then full pull-high options remain.

Programming Considerations

Within the user program, one of the first things to consider is port initialization. After a reset, all of the I/O data and port control registers will be set high. This means that all I/O pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high options have been selected. If the port control registers, PAC, PBC, PCC, etc., are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, PA, PB, PC, etc., are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using

the ²SET [m].i² and ²CLR [m].i² instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the en tire port,modify it to the required new bit values and then rewrite this data back to the output ports.

S y s t e m C l o c k

T 1 T 2

P o r t D a t a

T 3 T 4

W r i t e t o p o r t R e a d f r o m p o r t

Port A has the additional capability of providing wake-up functions. When the chip is in the HALT state, various methods are available to wake the device up. One of these is a high to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function.

T 1 T 2

T 3 T 4

Page 39

Timer/Event Counters

The provision of timers form an important part of any microcontroller giving the designer a means of carrying out time related functions. The devices in the I/O range contain either one or two count up timers of either 8 or 16-bit capacity depending upon which device is selected. As each timer has threedifferent operatingmodes, they can be configured to operate as a general timer, an exter nal event counter or as a pulse width measurement device. In the case of 8-bit timers, the provi sion of an internal 8-stage prescaler to the timer clock circuitry gives added range to the 8-bit timers.

There are two types of registers related to the Timer/Event Counters. The first is the register that contains the actual value of the timer and into which an initial value can be preloaded. Reading from this register retrieves the contents of the Timer/Event Counter. The second type of associ ated register is the timer control register which defines the timer options and determines how the timer is to be used. The timer clock source can be configured to come from the internal clock source or from the external timer pin. The accompanying table lists the associated timer register names.

No. of 8-bit Timers 1110

Timer Register Name

Timer Control Register

No. of 16-bit Timers 0012

Timer Register Name

Timer Control Register

Chapter 1 Hardware Structure

HT48R10A-1

HT48C10-1

TMR TMR

TMRC TMRC

¾¾

HT48R30A-1

HT48C30-1

HT48R50A-1

HT48C50-1

TMR0

TMR0C

TMR1L/TMR1H

TMR1C

HT48R70A-1

HT48C70-1

TMR0L/TMR0H TMR1L/TMR1H

TMR0C TMR1C

An external clock source is used when the timer is in the event counting mode, the clock source being provided on the external timer pin known as TMR, TMR0 or TMR1 depending on which device is selected. These external pins may be pin-shared with other I/O pins depending upon which device andpackage is chosen. Depending upon the condition of the TE bit in the corresponding timer control register, each high to low, or low to high transition on the external timer input pin will increment the counter by one.

Configuring the Timer/Event Counter Input Clock Source

The internal timer¢s clock source can originate from either the system clock or from an external clock source. The system clock input timer source is used when the timer is in the timer mode or in the pulse width measurement mode. For the 8-bit timers, the internal timer clock also passes through a prescaler, the value of which is conditioned by the bits PSC2, PSC1 and PSC0.

An external clock source is used when the timer is in the event counting mode, the clock source be ing provided on an external timer pin, TMR, TMR0 or TMR1 depending upon which device and which timer is used. Depending upon the condition of the TE bit, each high to low, or low to high transition on the external timer pin will increment the counter by one.

Page 40

O p t i o n

S Y S

R T C

T M R o r T M R 0 i n p u t

P S C 2 ~ P S C 0

8 - s t a g e p r e s c a l e r

( 1 / 2 ~ 1 / 2 5 6 )

T E

P r e l o a d R e g i s t e r

T M 1 T M 0

T i m e r / E v e n t C o u n t e r

M o d e C o n t r o l

T O N

T i m e r / E v e n t

8 - B i t T i m e r / E v e n t C o u n t e r

8-bit Timer/Event Counter Structure

C o u n t e r

L o w B y t e

I/O Type MCU

D a t a B u s

R e l o a d

D a t a B u s

B u f f e r

O v e r f l o w t o I n t e r r u p t

B Z

T M R 0 o r T M R 1 i n p u t

O p t i o n

S Y S / 4

M U

R T C

T E

T M 1 T M 0

T i m e r / E v e n t C o u n t e r

M o d e C o n t r o l

T O N

1 6 - B i t

P r e l o a d R e g i s t e r

H i g h B y t e

L o w B y t e

1 6 - B i t T i m e r / E v e n t C o u n t e r

R e l o a d

O v e r f l o w t o I n t e r r u p t

B Z

16-bit Timer/Event Counter Structure

Timer Registers - TMR, TMR0, TMR0L/TMR0H, TMR1L/TMR1H

The timer registers are special function registers located in the special purpose Data Memory and is the place where the actual timer value is stored. For the 8-bit timer, this register is known as TMR for the HT48R10A-1/HT48C10-1 and HT48R30A-1/HT48C30-1 devices and TMR0 for the HT48R50A-1/HT48C50-1 devices. In the case of the 16-bit timers, a pair of 8-bit registers is required to store the 16-bit timer value. These register pairs are known as TMR0L/TMR0H or TMR1L/TMR1H depending upon which device and timer is used. The value in the timer registers increases by one each time an internal clock pulse is received or an external transition occurs on the external timer pin. The timer will count from the initial value loaded by the preload register to the full count of FFH for the 8-bit timer or FFFFH for the 16-bit timers at which point the timer over flows and an internal interrupt signal generated. The timer value will then be reset with the initial preload register value and continue counting.

Note that to achieve a maximum full range count of FFH for the 8-bit timer or FFFFH for the 16-bit timers, the preload registers must first be cleared to all zeros. It should be noted that after power on, thepreload registers will be in an unknown condition. Note that if the Timer/Event Counters are in an OFF condition and data is written to their preload registers, this data will be immediately writ ten into the actual counter. However, if the counter is enabled and counting, any new data written into the preload data register during this period will remain in the preload register and will only be written intothe actual counter the next time an overflow occurs. Note also that when the timer regis ters are read, the timer clock will be blocked to avoid errors, however, as this may result in certain timing errors, programmers must take this into account.

Page 41

Chapter 1 Hardware Structure

For the devices with 16-bit timers, which have both low byte and high byte timer registers, access ing these registers is carried out in a specific way. It must be noted that when using instructions to preload data into the low byte register, namely, TMRL, TMR0L or TMR1L, the data will only be placed in a low byte buffer and not directly into the low byte register. The actual transfer of the data into the low byte register is only carried out when a write to its associated high byte register, namely, TMRH, TMR0H or TMR1H, is executed. On the other hand, using instructions to preload data into the high byte timer register will result in the data being directly written to the high byte reg ister. At the same time the data in the low byte buffer will be transferred into its associated low byte register. For this reason, when preloading data into the 16-bit timer registers, the low byte should be written first. It must also be noted that to read the contents of the low byte register, a read to the high byte register must first be executed to latch the contents of the low byte buffer into its associ ated low byte register. After this has been done the low byte register can be read in the normal way. Note that reading the low byte timer register will only result in reading the previously latched contents of the low byte buffer and not the actual contents of the low byte timer register.

Timer Control Registers - TMRC, TMR0C, TMR1C

The flexiblefeatures of the Holtek microcontroller Timer/Event Counters enable them to operate in three different modes, the options of which are determined by the contents of their respective con trol register. For devices with only one timer, the single timer control register is known as TMRC while for devices with two timers, there are two timer control registers known as TMR0C and TMR1C. It is the timer control register together with its corresponding timer registers that control the full operation of the Timer/Event Counters. Before the timers can be used, it is essential that the appropriate timer control register is fully programmed with the right data to ensure its correct operation, a process that is normally carried out during program initialization.

b 7

T ET O NT M 0T M 1

P S C 2

P S C 1 P S C 0

b 0

8 - b i t T i m e r / E v e n t C o u n t e r C o n t r o l R e g i s t e r

T i m e r p r e s c a l e r r a t e s e l e c t

P S C 1

P S C 2

0 0 0 0 1 1 1 1

E v e n t C o u n t e r a c t i v e e d g e s e l e c t 1 : c o u n t o n f a l l i n g e d g e 0 : c o u n t o n r i s i n g e d g e

P u l s e W i d t h M e a s u r e m e n t a c t i v e e d g e s e l e c t 1 : s t a r t c o u n t i n g o n r i s i n g e d g e , s t o p o n f a l l i n g e d g e 0 : s t a r t c o u n t i n g o n f a l l i n g e d g e , s t o p o n r i s i n g e d g e

T i m e r / E v e n t C o u n t e r c o u n t i n g e n a b l e 1 : e n a b l e 0 : d i s a b l e

N o t i m p l e m e n t e d , r e a d a s " 0 "

O p e r a t i n g m o d e s e l e c t T M 1

0 0 1 1

P S C 0

0 1 0 1 0 1 0 1

T i m e r R a t e 1 : 2 1 : 4 1 : 8 1 : 1 6 1 : 3 2 1 : 6 4 1 : 1 2 8 1 : 2 5 6

0 0 1 1 0 0 1 1

T M 0

n o m o d e a v a i l a b l e

e v e n t c o u n t e r m o d e

t i m e r m o d e

0 1

p u l s e w i d t h m e a s u r e m e n t m o d e

Page 42

I/O Type MCU

b 7

T ET O NT M 0T M 1

b 0

1 6 - b i t T i m e r / E v e n t C o u n t e r C o n t r o l R e g i s t e r

N o t i m p l e m e n t e d , r e a d a s " 0 "

E v e n t C o u n t e r a c t i v e e d g e s e l e c t 1 : c o u n t o n f a l l i n g e d g e 0 : c o u n t o n r i s i n g e d g e

T i m e r / E v e n t C o u n t e r c o u n t i n g e n a b l e 1 : e n a b l e 0 : d i s a b l e

N o t i m p l e m e n t e d , r e a d a s " 0 "

O p e r a t i n g m o d e s e l e c t T M 1

T M 0 0 0 1 1

n o m o d e a v a i l a b l e

e v e n t c o u n t e r m o d e

t i m e r m o d e

0 1

p u l s e w i d t h m e a s u r e m e n t m o d e

To choose which of the three modes the timer is to operate in, either in the timer mode, the event counting mode or the pulse width measurement mode, bits TM0 and TM1 must be set to the re quired logic levels. The timer-on bit TON or bit 4 of the Timer Control Register provides the basic on/off control of the timer, setting the bit high allows the counter to run, clearing the bit stops the counter. For the 8-bit Timer/Event Counter, bits 0~2 of the Timer Control Register determine the di vision ratio of the input clock prescaler. The prescaler bit settings have no effect if an external clock source is used. If the timer is in the event count or pulse width measurement mode, the ac tive transitionedge level type is selected by the logic level of the TE or bit 3 of the TMRC register.

Configuring the Timer Mode

In this mode, the timer can be utilized to measure fixed time intervals, providing an internal interrupt signaleach time the counter overflows. To operate in this mode, bits TM1 (bit7) andTM0 (bit6) of the TMRC register must be set to 1 and 0 respectively. In this mode, the internal clock is used as the timer clock. For the 8-bit Timer/Event Counter, the input clock frequency to the timer is f f

divided by the value programmed into the timer prescaler, the value of which is determined by

RTC

bits PSC2~PSC0 of the TMRC register. For the 16-bit Timer/Event Counter, the input clock frequency to the timer is f

/4 or the f

SYS

. There is no prescaler function for the 16-bit timer. The

RTC

timer-on bit, TON must be set high to enable the timer to run. Each time an internal clock high to low transition occurs, the timer increments by one; when the timer is full and overflows, an inter rupt signal is generated and the timer will preload the value already loaded into the preload regis ter and continue counting. It should be noted that a timer overflow is one of the interrupt and wake-up sources.

SYS

Page 43

P r e s c a l e r O u t p u t

Chapter 1 Hardware Structure

I n c r e m e n t

T i m e r C o n t r o l l e r

T i m e r + 1 T i m e r + 2

T i m e r + N T i m e r + N + 1

Timer Mode Timing Chart

Configuring the Event Counter Mode

In thismode, a number of externally changing logic events, occurring on the external timer pin, can be recorded by the internal timer. For the timer to operate in the event counting mode, bits TM1 and TM0 of the TMRC register must be set to 0 and 1 respectively. The timer-on bit, TON must be set highto enable the timer to count. With TE low, the counter will increment each time the external timer pin receives a low to high transition. If TE is high, the counter will increment each time the ex ternal timer pin receives a high to low transition. As in the case of the other two modes, when the counter is full, the timer will overflow and generate an internal interrupt signal; the counter will preload the value already loaded into the preload register. If the external timer pin is pin-shared with other I/O pins, to ensure that the pin is configured to operate as an event counter input pin, two things have to happen. The first is to ensure that the TM0 and TM1 bits place the timer/event counter in the event counting mode, the second is to ensure that the port control register configures the pin as an input. It should be noted that a timer overflow is one of the interrupt and wake-up sources.

E x t e r n a l E v e n t

I n c r e m e n t

T i m e r C o u n t e r

T i m e r + 1

Event Counter Mode Timing Chart

T i m e r + 2 T i m e r + 3

Configuring the Pulse Width Measurement Mode

In this mode, the width of external pulses applied to the external timer pin can be measured. In the Pulse Width Measurement Mode, the timer clock source is supplied by the internal clock. For the timer to operate in this mode, bits TM0 and TM1 must both be set high. If the TE bit is low, once a high to low transition has been received on the external timer pin, the timer will start counting until the external timer pin returns to its original high level. At this point the TON bit will be automatically

E x t e r n a l T i m e r

P i n I n p u t

T O N ( w i t h T E = 0 )

P r e s c a l e r O u t p u t

( w i t h c l o c k = f

T i m e r C o u n t e r

S Y S

I n c r e m e n t

)

T i m e r

P r e s c a l e r O u t p u t i s s a m p l e d a t e v e r y f a l l i n g e d g e o f T 1 .

+ 1 + 2 + 3 + 4

Pulse Width Measurement Mode Timing Chart

Page 44

I/O Type MCU

reset to zero and the timer will stop counting. If the TE bit is high, the timer will begin counting once a low to high transition has been received on the external timer pin and stop counting when the ex ternal timer pin returns to its original low level. As before, the TON bit will be automatically reset to zero and the timer will stop counting. It is important to note that in the Pulse Width Measurement Mode, the TON bit is automatically reset to zero when the external control signal on the external timer pin returns to its original level, whereas in the other two modes the TON bit can only be reset to zero under program control. The residual value in the timer, which can now be read by the pro gram, therefore represents the length of the pulse received on pin external timer pin. As the TON bit has now been reset any further transitions on the external timer pin will be ignored. Not until the TON bit is again set high by the program can the timer begin further pulse width measurements. In this way single shot pulse measurements can be easily made. It should be noted that in this mode the counter is controlled by logical transitions on the external timer pin and not by the logic level. As in the case of the other two modes, when the counter is full, the timer will overflow and generate an internal interrupt signal. The counter will also be reset to the value already loaded into the preload register. If the external timer pin is pin-shared with other I/O pins, to ensure that the pin is configured to operate as a pulse width measuring input pin, two things have to happen. The first is to ensure that the TM0 and TM1 bits place the timer/event counter in the pulse width measuring mode, thesecond is to ensure that the port control register configures the pin as an input. It should be noted that a timer overflow is one of the interrupt and wake-up sources.

Programmable Frequency Divider (PFD) and Buzzer Application

Operating similar to a programmable frequency divider, the buzzer function within the microcontroller provides a means of producing a variable frequency output suitable for applica tions such as piezo-buzzer driving or other interfaces requiring a precise frequency generator.

The BZ and BZ is selectedvia configuration option to have single BZ output or both BZ and BZ not selected, the pins can operate as normal I/O pins. Note that the BZ pin generating a kind of differential output and supplying more power to connected interfaces such as buzzers.

The timer overflow signal is the clock source for the buzzer circuit. The output frequency is controlled by loading the required values into the timer prescaler registers to give the required division ratio. The counter will begin to count-up from this preload register value until full, at which point an overflow signal is generated, causing both the BZ and BZ then be automatically reloaded with the preload register value and continue counting-up. Refer to the relevant Timer/Event Counters section for details of its settings and operations.

For the buzzer outputs to function, it is essential that the Port B control register PBC bit 0 and PBC bit 1 are setup as outputs. If they are setup as inputs the buzzer output will not function, and used

as normal input pins. The BZ and BZ put data bit is used as the on/off control bit for the BZ and BZ

puts will both be low if the PB0 output data bit is cleared to ²0². Note that the condition of bit PB1 has no effect on the overall control of the BZ and BZ

are a complimentary pair and pin-shared with I/O pins, PB0 and PB1. The function

outputs, however, if

pin is the inverse of the BZ

outputs to change state. The counter will

outputs will only be activated if bit PB0 is set to ²1². This out

outputs. Note that the BZ and BZ out

pins.

Page 45

Chapter 1 Hardware Structure

T i m e r O v e r f l o w

B u z z e r C l o c k

P B 0 D a t a

B Z O u t p u t a t P B 0

B Z O u t p u t a t P B 1

Using this method of frequency generation, and if a crystal oscillator is used for the system clock, very precise values of frequency can be generated.

Prescaler

For the 8-bit Timer/Event Counter, bit 0~2 of the timer control register can be used to define the pre-scaling stages of the internal clock sources of the Timer/Event Counter. The Timer/Event Counter overflow signal can be used to generate signals for buzzer driving and as a Timer Inter rupt.

I/O Interfacing

The Timer/Event Counter when configured to run in the event counter or pulse width measurement mode, require the use of the external timer pin for correct operation. This external timer pin may be pin-shared with other I/O pins, depending upon which device is selected. Pull-high resistors can be selected for connection to the timer input pins. The timers can also be setup to drive the pin-shared buzzer pins. When the buzzer pins are selected by selecting the correct configuration option, the output of the chosen timer can be made to drive this at a frequency determined by the contents of the timer register and where appropriate the timer.

Programming Considerations

When configured to run in the timer mode, the internal system clock or RTC is used as the timer clock source and is therefore synchronized with the overall operation of the microcontroller. In this mode, when the appropriate timer register is full, the microcontroller will generate an internal inter rupt signaldirecting the program flow to the respectiveinternal interrupt vector. For the pulse width measurement mode, the internal system clock or RTC is also used as the timer clock source but the timer will only run when the correct logic condition appears on the external timer input pin. As this is an external event and not synchronized with the internal timer clock, the microcontroller will only see this external event when thenext timer clock pulse arrives. As a result there may be small differences in measured values requiring programmers to take this into account during program ming. The same applies if the timer is configured to be in the event counting mode which again is an external event and not synchronized with the internal system or timer clock.

Page 46

Interrupts

I/O Type MCU

The I/O series microcontrollers provide both external interrupt and internal Timer/Event Counter in terrupt functions. The Interrupt Control Register (INTC;0BH) contains the interrupt control bits to set the enable/disable and the interrupt request flags.

Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may oc cur during this interval but only the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the EMI bit and the corresponding bit of the INTC may be set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must be prevented from becoming full.

b 7 b 0

T 1 F

E T 1 I

E T I E E I E M IE I F T F

E T 0 I E E I E M IE I F T 0 F

I N T C R e g i s t e r d e v i c e s w i t h s i n g l e t i m e r

M a s t e r I n t e r r u p t g l o b a l e n a b l e 1 : g l o b a l e n a b l e 0 : g l o b a l d i s a b l e

E x t e r n a l i n t e r r u p t e n a b l e

T i m e r / E v e n t C o u n t e r i n t e r r u p t e n a b l e 1 : e n a b l e 0 : d i s a b l e

N o t i m p l e m e n t e d , r e a d a s " 0 "

E x t e r n a l i n t e r r u p t r e q u e s t f l a g

T i m e r / E v e n t C o u n t e r i n t e r r u p t r e q u e s t f l a g 1 : r e q u e s t i s s u e d 0 : r e q u e s t n o t i s s u e d

N o t i m p l e m e n t e d , r e a d a s " 0 "

I N T C R e g i s t e r d e v i c e s w i t h t w o t i m e r s

M a s t e r I n t e r r u p t g l o b a l e n a b l e 1 : g l o b a l e n a b l e 0 : g l o b a l d i s a b l e

E x t e r n a l i n t e r r u p t s o u r c e e n a b l e

T i m e r / E v e n t C o u n t e r 0 i n t e r r u p t e n a b l e 1 : e n a b l e 0 : d i s a b l e

T i m e r / E v e n t C o u n t e r 1 i n t e r r u p t e n a b l e 1 : e n a b l e 0 : d i s a b l e

E x t e r n a l i n t e r r u p t r e q u e s t f l a g

T i m e r / E v e n t C o u n t e r 0 r e q u e s t f l a g 1 : r e q u e s t i s s u e d 0 : r e q u e s t n o t i s s u e d

T i m e r / E v e n t C o u n t e r 1 r e q u e s t f l a g 1 : r e q u e s t i s s u e d 0 : r e q u e s t n o t i s s u e d

N o t i m p l e m e n t e d , r e a d a s " 0 "

Page 47

Chapter 1 Hardware Structure

All of these interrupts have the capability of waking up the processor when in the HALT mode. As an interrupt is serviced, a control transfer occurs by pushing the Program Counter onto the stack, followed by a branch to a subroutine at a specified location in the Program Memory. Only the Pro gram Counter is pushed onto the stack. If the contents of the register or status register (STATUS) are altered by the interrupt service program which may corrupt the desired control sequence, then the contents should be saved in advance.

The various interrupt enable bits, together with their associated request flags, are shown in the fol lowing diagram with their order of priority.

A u t o m a t i c a l l y C l e a r e d b y I S R

M a n u a l l y S e t o r C l e a r e d b y S o f t w a r e

E x t e r n a l I n t e r r u p t R e q u e s t F l a g E I F

T i m e r / E v e n t C o u n t e r 0

I n t e r r u p t R e q u e s t F l a g T 0 F

T i m e r / E v e n t C o u n t e r 1

I n t e r r u p t R e q u e s t F l a g T 1 F

In the figure, the T0F and T1F interrupt request flags and the ET0I and ET1I interrupt enable bits

Note

A u t o m a t i c a l l y D i s a b l e d b y I S R

C a n b e E n a b l e d M a n u a l l y

E E I

E T 0 I

E T 1 I

E M I

P r i o r i t y

H i g h

L o w

refer tothe HT48R70A-1/ HT48C70-1 and HT48R50A-1/HT48C50-1 devices, which have two tim ers. For the HT48R10A-1/ HT48C10-1 and HT48R30A-1/HT48C30-1, which only have one timer, the Timer/Event Counter 0 represents the single timer, known as TMR and has an interrupt request flag known as TF and an interrupt enable bit known as ETI.

External Interrupt

For an external interrupt to occur, the corresponding external interrupt enable bit must be first set. This is bit 1 of the INTC register and shown as EEI. External interrupts are triggered by a high to low transition of the INT be set. When the interrupt is enabled, the stack is not full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag EIF will be reset and EMI bits will be cleared to disable other interrupts.

line, after which the related interrupt request flag (EIF; bit 4 of INTC) will

I n t e r r u p t

P o l l i n g

Timer/Event Counter Interrupt

For a timer generated internal interrupt to occur, the corresponding internal interrupt enable bit must be first properly set. In the case of devices with a single timer, this is bit 2 of the INTC register and is known as ETI. For devices with two timers, the Timer 0 interrupt enable is bit 2 and known as ET0I while the Timer 1 interrupt enable is bit 3 and known as ET1I. An actual Timer/Event Coun ter interruptwill be initialized when the Timer/Event Counter interrupt request flag is set, caused by a timer overflow. In the case of devices with a single timer, this is bit 5 of the INTC register and is known as TF. In the case of devices with two timers, the Timer 0 request flag is bit 5 and known as T0F, while the Timer 1 request flag is bit 6 and known as T1F. When the master interrupt global en able bit is set, the stack is not full and the corresponding internal interrupt enable bit is set, an inter

Page 48

I/O Type MCU

nal interrupt will be generated when the timer overflows. This will create a subroutine call to location 08H for devices with a single timer. For devices with two timers, a subroutine call to loca tion 08H will occur for Timer 0 and a subroutine call to location 0CH for Timer 1. When an internal interrupt occurs, the interrupt request flag, TF, T0F or T1F will be reset and the EMI bit will be cleared to disable other interrupts.

Interrupt Priority

Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In case of simultaneous requests,the following table shows the priority that is applied. These can be masked by resetting the EMI bit.

Interrupt Source Priority Vector

External Interrupt 1 04H

Timer/Event Counter 0 Overflow 2 08H

Timer/Event Counter 1 Overflow 3 0CH

Note The table is applicable for the HT48R70A-1/ HT48C70-1 and HT48R50A-1/HT48C50-1 devices

which have two timers, known as TMR0 and TMR1. For the HT48R30A-1/HT48C30-1 and HT48R10A-1/HT48C10-1, which only have one timer, the Timer/Event Counter 0 represents the single timer, known as TMR.

In cases where both external and internal interrupts are enabled and where an external and inter nal interrupt occurs simultaneously, the external interrupt will always have priority and will therefore be serviced first. Suitable masking of the individual interrupts using the INTC register can prevent simultaneous occurrences.

Programming Considerations

The Timer/Event Counter interrupt request flags, TF, T0F and T1F, external interrupt request flag EIF, enable Timer/Event Counter interrupt bits ETI, ET0I and ET1I, external interrupt enable bit EEI and master interrupt bit EMI form the interrupt control register INTC which is located at 0BH in the Data Memory. By disabling the interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the INTC register until the corresponding interrupt is serviced or until the request flag is cleared by a software instruction.

It is recommended that programs do not use the ²CALL subroutine² instruction within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stackis left and the interrupt is not well controlled, the original con trol sequencewill be damaged once a ²CALL subroutine² is executedin the interrupt subroutine.

Page 49

Reset and Initialization

A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condi tion is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the first program instruction. After this power-on reset, certain important internalregisters will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address.

Chapter 1 Hardware Structure

In addition to the power-on reset, situations may arise where it is necessary to forcefully apply a re set condition when the microcontroller is running. One example of this is where after power has been applied and the microcontroller is already running, the RES

line is forcefully pulled low. In such case, known as a normal operation reset, some of the microcontroller registers remain un changed allowing the microcontroller to proceed with normal operation after the reset line is al lowed to return high. Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup.

Another reset exists in the form of a Low Voltage or LVR, where a full reset, similar to the RES set is implemented in situations where the power supply voltage falls below a certain threshold.

Reset

There are five ways in which a microcontroller reset can occur, through events occurring both inter nally and externally:

® Power-on Reset

The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. As well as ensuring that the Program Memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs.

Although the microcontroller has an internal RC reset function, due to unstable power on conditions, an external RC network connected to the RES lay created by the RC network ensures that the RES the power supply stabilizes. During this time, normal operation of the microcontroller is inhibited. After the RES

line reaches a certain voltage value, the reset delay time t an extra delay time after which the microcontroller can begin normal operation. The abbreviation SST in the figures stands for System Start-up Timer.

pin is generally recommended. This time depin remains low for an extended period while

is invoked to provide

RSTD

V D D

R E S

S S T T i m e - o u t

I n t e r n a l R e s e t

0 . 9 V

R S T D

Power-On Reset Timing Chart

D D

Page 50

I/O Type MCU

RES

Pin Reset

This type of reset occurs when the microcontroller is already running and the RES pulled low by external hardware such as an external switch. In this case as in the case of other re set, the Program Counter will reset to zero and program execution initiated from this point.

0 . 9 V

R E S

S S T T i m e - o u t

I n t e r n a l R e s e t

0 . 4 V

D D

R S T D

RES Reset Timing Chart

Low Voltage Reset - LVR

The microcontrollercontains a low voltage reset circuit in order to monitor the supplyvoltage of the device. Ifthe supply voltage of the device drops to within a range of 0.9V~V

such asmight occur

LVR

when changing the battery, the LVR will automatically reset the device internally. For a valid LVR signal, a low voltage, i.e. a voltage in the range between 0.9V~V

must exist for greater than

LVR

1ms. If the low voltage state does not exceed 1ms, the LVR will ignore it and will not perform a re set function.

L V R

S S T T i m e - o u t

R S T D

pin is forcefully

I n t e r n a l R e s e t

Low Voltage Reset Timing Chart

® Watchdog Time-out Reset during Normal Operation

The Watchdog Time-out Reset during normal operation is the same as RES Watchdog Time-out flag TO will be set to 1.

W D T T i m e - o u t

S S T T i m e - o u t

I n t e r n a l R e s e t

R S T D

WDT Time-out Reset during Normal Operation Timing Chart

reset except that the

Page 51

Chapter 1 Hardware Structure

Watchdog Time-out Reset during HALT

The Watchdog Time-outReset during HALT is a little different from other kindsof reset. Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to 0 and the TO flag will be set to 1. Refer to A.C. Characteristics for t

W D T T i m e - o u t

S S T

S S T T i m e - o u t

WDT Time-out Reset during HALT Timing Chart

The different types of resets described affect the reset flags in different ways. These flags known as PDF and TO are located in the status register and are controlled by various microcontroller op erations such as the HALT function or Watchdog Timer. The reset flags are shown in the table:

0 0 RES

u u RES

1 u WDT time-out reset during normal operation

1 1 WDT time-out reset during HALT

²u² stands for unchanged

PDF

reset during power on

or LVR reset during normal operation

RESET Conditions

SST

details.

The followingtable indicates the way in which the various components of the microcontrollerare af fected after a reset occurs.

Item Condition After RESET

Program Counter Reset to zero

Interrupts All interrupts will be disabled

WDT Clear after reset, WDT begins counting

Timer/Event Counter All Timer Counters will be turned off

Prescaler

Input/Output Ports All I/O ports will be setup as inputs

Stack Pointer Stack pointer will point to the top of the stack

The Timer Counter Prescaler will be cleared

Page 52

I/O Type MCU

The different kinds of reset all affect the internal registers of the microcontroller in different ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table de scribes how each type of reset affects each of the microcontroller internal registers.

HT48R10A-1/HT48C10-1

ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu

PCL 0000 0000 0000 0000 0000 0000 0000 0000

TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu

TBLH

STATUS

INTC

WDTS 0000 0111 0000 0111 0000 0111 uuuu uuuu

TMR xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

TMRC

PA 1111 1111 1111 1111 1111 1111 uuuu uuuu

PAC 1111 1111 1111 1111 1111 1111 uuuu uuuu

PB 1111 1111 1111 1111 1111 1111 uuuu uuuu

PBC 1111 1111 1111 1111 1111 1111 uuuu uuuu

PCC

²u² stands for unchanged

²x² stands for unknown

²-² stands for unimplemented

Reset

(Power On)

- xxx xxxx - uuu uuuu - uuu uuuu - uuu uuuu

- - xx xxxx --uu uuuu --uu uuuu --uu uuuu

--00 xxxx --uu uuuu --1u uuuu - - 11 uuuu

--00 - 000 - - 00 - 000 --00 - 000 --uu - uuu

00- 0 1000 00- 0 1000 00- 0 1000 uu- u uuuu

- - - 1 1111 - - - 1 1111 - - - 1 1111 - - - u uuuu

RES

or LVR

Reset

Time-out

WDT

(Normal Operation)

WDT

Time-out

(HALT)

Page 53

Chapter 1 Hardware Structure

HT48R30A-1/HT48C30-1

ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu

PCL 0000 0000 0000 0000 0000 0000 0000 0000

TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu

TBLH

STATUS

INTC

WDTS 0000 0111 0000 0111 0000 0111 uuuu uuuu

TMR xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

TMRC

PA 1111 1111 1111 1111 1111 1111 uuuu uuuu

PAC 1111 1111 1111 1111 1111 1111 uuuu uuuu

PB 1111 1111 1111 1111 1111 1111 uuuu uuuu

PBC 1111 1111 1111 1111 1111 1111 uuuu uuuu

PCC

PGC

²u² stands for unchanged

²x² stands for unknown

²-² stands for unimplemented

Reset

(Power On)

- xxx xxxx - uuu uuuu - uuu uuuu - uuu uuuu

- - xx xxxx --uu uuuu --uu uuuu --uu uuuu

--00 xxxx - - uu uuuu - - 1u uuuu - - 11 uuuu

--00 - 000 --00 - 000 --00 - 000 --uu - uuu

00- 0 1000 00- 0 1000 00- 0 1000 uu- u uuuu

--11 1111 --11 1111 --11 1111 - - uu uuuu

- - - - - 111 - - - - - 111 - - - - - 111 - - - - - uuu

RES

or LVR

Reset

Time-out

WDT

(Normal Operation)

WDT

Time-out

(HALT)

Page 54

I/O Type MCU

HT48R50A-1/HT48C50-1

MP0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu

MP1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu

ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu

PCL 0000 0000 0000 0000 0000 0000 0000 0000

TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu

TBLH

STATUS

INTC

WDTS 0000 0111 0000 0111 0000 0111 uuuu uuuu

TMR0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

TMR0C

TMR1H xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

TMR1L xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

TMR1C

PA 1111 1111 1111 1111 1111 1111 uuuu uuuu

PAC 1111 1111 1111 1111 1111 1111 uuuu uuuu

PB 1111 1111 1111 1111 1111 1111 uuuu uuuu

PBC

PC 1111 1111 1111 1111 1111 1111 uuuu uuuu

PCC 1111 1111 1111 1111 1111 1111 uuuu uuuu

PD 1111 1111 1111 1111 1111 1111 uuuu uuuu

PDC 1111 1111 1111 1111 1111 1111 uuuu uuuu

PGC

²u² stands for unchanged

²x² stands for unknown

²-² stands for unimplemented

Reset

(Power On)

- xxx xxxx - uuu uuuu - uuu uuuu - uuu uuuu

--00 xxxx - - uu uuuu --1u uuuu - - 11 uuuu

- 000 0000 - 000 0000 - 000 0000 - uuu uuuu

00- 0 1000 00- 0 1000 00- 0 1000 uu- u uuuu

00- 01--- 00- 01- - - 00- 01- - - uu- uu---

1111 1111 1111 1111 1111 1111 uuuu uuuu

---- -111 ---- -111 ---- -111 - - - - - uuu

RES

or LVR

Reset

Time-out

WDT

(Normal Operation)

WDT

Time-out

(HALT)

Page 55

Chapter 1 Hardware Structure

HT48R70A-1/HT48C70-1

MP0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu

MP1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu

ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu

PCL 0000 0000 0000 0000 0000 0000 0000 0000

TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu

TBLH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu

STATUS

INTC

WDTS 0000 0111 0000 0111 0000 0111 uuuu uuuu

TMR0H xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

TMR0L xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

TMR0C

TMR1H xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

TMR1L xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

TMR1C

PA 1111 1111 1111 1111 1111 1111 uuuu uuuu

PAC 1111 1111 1111 1111 1111 1111 uuuu uuuu

PB 1111 1111 1111 1111 1111 1111 uuuu uuuu

PBC 1111 1111 1111 1111 1111 1111 uuuu uuuu

PC 1111 1111 1111 1111 1111 1111 uuuu uuuu

PCC 1111 1111 1111 1111 1111 1111 uuuu uuuu

PD 1111 1111 1111 1111 1111 1111 uuuu uuuu

PDC 1111 1111 1111 1111 1111 1111 uuuu uuuu

PE 1111 1111 1111 1111 1111 1111 uuuu uuuu

PEC 1111 1111 1111 1111 1111 1111 uuuu uuuu

PF 1111 1111 1111 1111 1111 1111 uuuu uuuu

PFC 1111 1111 1111 1111 1111 1111 uuuu uuuu

PG 1111 1111 1111 1111 1111 1111 uuuu uuuu

PGC 1111 1111 1111 1111 1111 1111 uuuu uuuu

²u² stands for unchanged

²x² stands for unknown

²-² stands for unimplemented

Reset

(Power On)

--00 xxxx - - uu uuuu - - 1u uuuu - - 11 uuuu

- 000 0000 - 000 0000 - 000 0000 - uuu uuuu

00- 01--- 00- 01--- 00- 01--- uu- uu---

00- 01--- 00- 01- - - 00- 01- - - uu- uu---

RES

or LVR

Reset

Time-out

WDT

(Normal Operation)

WDT

Time-out

(HALT)

Page 56

Oscillator

I/O Type MCU

Various oscillator options offer the user a wide range of functions according to their various applica tion requirements. Three types of system clocks can be selected while various clock source op tions for the Watchdog Timer as well as a real time clock function are provided for maximum flexibility. All oscillator options are selected through the configuration options.

System Clock Configurations

There are three methods of generating the system clock, using an external crystal/ceramic oscilla tor, an external RC network or using the internal RC clock source. The chosen method is selected through the configuration options.

System Crystal/Ceramic Oscillator

For the crystal oscillator configuration, the simple connection of a crystal across OSC1 and OSC2 will create the necessary phase shift and feedback for oscillation with no other external compo nents required. A ceramic resonator can be used instead of a crystal but two small value capaci tors should be connected between OSC1, OSC2 and ground.

C 1

R 1

C 2

O S C 1

O S C 2

Crystal/Ceramic Oscillator

The table below shows the C1, C2 and R1 values for various crystal/ceramic oscillating frequencies.

Crystal or Resonator C1, C2 R1

4MHz Crystal 0pF

4MHz Resonator (3 pin) 0pF

4MHz Resonator (2 pin) 10pF

3.58MHz Crystal 0pF

3.58MHz Resonator (2 pin) 25pF

2MHz Crystal & Resonator (2 pin) 25pF

1MHz Crystal 35pF

480kHz Resonator 300pF

455kHz Resonator 300pF

429kHz Resonator 300pF

10kW

12kW

10kW

27kW

9.1kW

10kW

Page 57

Chapter 1 Hardware Structure

System RC Oscillator

Using the external RC network as an oscillator requires that a resistor, with a value between 24kW and 1MW, is connected between OSC1 and VDD, and a 470pF capacitor is connected to ground. The generated system clock divided by 4 will be provided on OSC2 as an output which can be used for external synchronization purposes. Although this is a cost effective oscillator configura tion, the oscillation frequency can vary with VDD, temperature and process variations on the chip itself and is therefore not suitable for applications where timing is critical or where accurate oscilla tor frequencies are required. For the value of the external resistor R dix section for typical RC Oscillator vs. Temperature and V

D D

O S C

4 7 0 p F

characteristics graphics.

O S C 1

please refer to the Appen

OSC

/ 4 N M O S O p e n D r a i n

S Y S

O S C 2

RC Oscillator

Internal System RC Oscillator

In addition to the external crystal/resonator or external RC system clock configurations, the de vices also contain an internal RC system clock. This oscillator is integral to the microcontroller and requires no external components. The frequency of this internal RC oscillator can be selected by configuration option to have a typical value at 5V of either 3.2MHz, 1.6MHz, 800kHz or 400kHz. The 1.6MHz, 800kHz and 400kHz frequencies are internally generated by sequentially dividing the base 3.2MHz frequency by two. Note that if this internal system clock option is selected then with the exception of the HT48R70A-1/HT48C70-1 series, the OSC1 and OSC2 pins are free for use as normal I/O pins. The OSC1 and OSC2 pins can also be connected to a 32768Hz crystal for use as an RTC oscillator on all devices. If the RTC oscillator is to be used in user applications, the internal RC oscillator must be used as the system clock. Note that the oscillation frequency of this internal system RC oscillator can vary with VDD, temperature and process variations.

P C 3

( O S C 1 )

P C 4

( O S C 2 )

I n t e r n a l R C

O s c i l l a t o r

I n t e r n a l R C S y s t e m O s c i l l a t o r f o r H T 4 8 R 1 0 A - 1 / H T 4 8 C 1 0 - 1

O s c i l l a t o r P i n s U s e d a s I / O s

P G 1

( O S C 1 )

P G 2

( O S C 2 )

I n t e r n a l R C

O s c i l l a t o r

I n t e r n a l R C S y s t e m O s c i l l a t o r f o r H T 4 8 R 3 0 A - 1 / H T 4 8 C 3 0 - 1 a n d H T 4 8 R 5 0 A - 1 / H T 4 8 C 5 0 - 1

O s c i l l a t o r P i n s U s e d a s I / O s

R T C

3 2 7 6 8 H z

C r y s t a l

O S C 1

I n t e r n a l R C

O s c i l l a t o r

O S C 2

I n t e r n a l R C

S y s t e m O s c i l l a t o r

R T C 3 2 7 6 8 H z C r y s t a l

C o n n e c t e d t o O s c i l l a t o r P i n s

A p p l i c a b l e t o a l l D e v i c e s

RTC Oscillator

When microcontrollers enter a power down or HALT condition, the system clock is switched off to stop microcontroller activity and to conserve power. However, in many microcontroller applica

Page 58

I/O Type MCU

tions it may be necessary to keep the internal timers operational even when the microcontroller is in a HALT state. However, to do this, another clock, independent of the system clock, must be pro vided. To provide this feature, all of Holtek¢s I/O range of microcontrollers incorporate a Real Time Clock orRTC. This clock source has a fixed frequency of 32768Hz and requiresa 32768Hz crystal to be connected between pins OSC1 and OSC2. For applications using the RTC oscillator, the in ternal RC Oscillator must be used as the system clock. Oscillator configuration options determine if the RTC is to be used. If the RTC oscillator configuration option is selected, then the timer(s) have the configuration option of selecting either the internal RC system clock or RTC as their source clock.

The RTC, if selected as the clock source for the timers, allows the timer functions to remain active even if the microcontroller is in the power down or HALT mode and as such will issue the usual inter nal interrupt signal when the counter is full. This signal will causethe microcontroller to wake upfrom its HALT state and continue with normal operation until the next ²HALT² instruction is executed.

Watchdog Timer Oscillator

The WDT oscillator is a fully self-contained free running on-chip RC oscillator with a typical period of 65ms at 5V requiring no external components. When the device enters the power down mode, the system clock will stop running but the WDT oscillator continues to free-run and to keep the watchdog active. However, to preserve power in certain applications the WDT oscillator can be dis abled via a configuration option.

HALT and Wake-up in Power Down Mode

The HALT mode is initialized by the ²HALT² instruction and results in the following:

· The system oscillator will be turned off

· The contents of the on chip RAM and registers remain unchanged

· The WDT and WDT prescaler will be cleared and resume counting if the WDT clock source is

selected to come from the WDT oscillator

· All of the I/O ports remain unchanged

· The PDF flag is set and the TO flag is cleared

The system can leave the HALT mode by means of a reset, an interrupt, an external falling edge signal on Port A or a WDT overflow. A reset will initialize a chip reset and a WDT overflow will initial ize a WDT time-out Reset from HALT but by examining the TO and PDF flags the source of the re set can be determined. The PDF flag is cleared by a system power-up or executing the ²CLR WDT² instruction and is set when executing the ²HALT² instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the PC and SP; the other flags remain in their original status.

Port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in Port A can be independently selected to wake-up the device by configuration option. Awakening from an I/O port stimulus, the program will resume execution at the next instruction. If the system is woken up via an interrupt, two possibilities may occur. If the related interrupt is dis abled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. If the interrupt is enabled and the stack is not full, the regular interrupt response takes

Page 59

Chapter 1 Hardware Structure

place. If an interrupt request flag is set to ²1² before entering the HALT mode, the wake-up func tion of the related interrupt will be disabled. Once a wake-up event occurs, it takes 1024 system clock periods to resume normal operation. In other words, a dummy period will be inserted after a wake-up. If the wake-up results from an interrupt acknowledge signal, the actual interrupt subrou tine execution will be delayed by one or more cycles. If the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished.

Watchdog Timer

The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. It oper ates by providing a ²chip reset² when the WDT counter overflows. The WDT clock is supplied by one of three sources selected by configuration option: its own self contained dedicated internal WDT oscillator, the instruction clock (system clock divided by 4) or the 32kHz RTC oscillator. Note that if the WDT configuration option has been disabled, then any instruction relating to its opera tion will result in no operation.

The internal WDT oscillator has an approximate period of 65ms at a supply voltage of 5V. If se lected, it is first divided by 256 via an 8-stage counter to give a nominal period of 18ms. Note that this period can vary with VDD, temperature and process variations. For longer WDT time out peri ods the WDT prescaler can be utilized. By writing the required value to bits 0, 1 and 2 of the WDTS register, known as WS0, WS1 and WS2, longer time-out periods can be achieved. With WS0, WS1 and WS2 all equal to 1, the division ratio is 1:128 which gives a maximum time-out period of about 2.1s. The high nibble and bit 3 of the WDTS are reserved for user defined flags, which can be used to indicate some specified status.

b 7 b 0

W S 2 W S 1 W S 0

W D T S R e g i s t e r

W D T p r e s c a l e r r a t e s e l e c t

W S 2

W S 1

W S 0

N o t u s e d , u s e r a c c e s s i b l e

0 1 0 1 0 1 0 1

W D T R a t e

1 : 1 6 1 : 3 2 1 : 6 4

1 : 1 2 8

1 : 1 1 : 2 1 : 4 1 : 8

The WDT oscillator can be disabled and the WDT clock source can be supplied from the instruc tion clock (system clock divided by 4). If the instruction clock is used as the clock source it should be noted that when the system enters the power-down mode, then the instruction clock is stopped and the WDT will lose its protecting purposes. In such cases the system can only be restarted via external logic. For systems that operate in noisy environments, using the internal WDT oscillator or the 32kHz RTC oscillator is strongly recommended.

Under normal program operation, the WDT time-out will initialize a ²chip reset² and set the status bit ²TO². However, if the system is in the power-down mode, only a WDT time-out reset from ²HALT² will be initialized which willonly reset the Program Counter and SP. Three methods can be adopted toclear the contents of the WDT including the WDT prescaler. Thefirst is an external hard

Page 60

I/O Type MCU

1 o r 2 I n s t r u c t i o n s

W D T O S C O u t p u t

W D T S o u r c e S e l e c t

ware reset(a low level on the RES pin), the secondis via software instructions and the third is via a ²HALT² instruction. There are two methods of using software instructions to clear the Watchdog Timer, one of which must be chosen by configuration option. The first option is to use the single ²CLR WDT² instruction while the second is to use the two commands ²CLR WDT1² and ²CLR WDT2². For the first option, a simple execution of ²CLR WDT² will clear the WDT while for the sec ond option, both ²CLR WDT1² and ²CLR WDT2² must both be executed to successfully clear the WDT. Note that for this second option,if ²CLR WDT1² is used to clear the WDT, successive execu tions of this instruction will have no effect, only the execution of a ²CLR WDT2² instruction will clear the WDT. Similarly, after the ²CLR WDT2² instruction has been executed, only a successive ²CLR WDT1² instruction can clear the Watchdog Timer.

Configuration Options

The various microcontroller configuration options selected using the HT-IDE are stored in the option memory. All bits must be defined for proper system function, the details of which are shown in the table. After the configuration options have been programmed into the microcontroller by the user, it is important to note that they cannot be altered later by the application program. For the mask version devices, these configuration options, once defined, are implemented into the microcontroller duringthe manufacturing process and therefore cannot bereconfigured by the user.

No. Option

1 WDT clock source: WDT oscillator or f

2 CLRWDT instructions: 1 or 2 instructions

3 Timer/Event Counter TMR or TMR0 clock source: f

Timer/Event Counter TMR1 clock source: f

(HT48R50A-1/HT48C50-1 and HT48R70A-1/HT48C70-1 only)

5 PA0~PA7 wake-up: enable or disable

6 PA Schmitt Trigger or non Schmitt Trigger

PA, PB, PC, PD, PE, PF and PG pull-high enable or disable

(port numbers is device dependent)

Buzzer function: single BZ enable or both BZ and BZ

Buzzer clock source: timer 0 or timer 1 (for HT48R50A-1/HT48C50-1, HT48R70A-1/HT48C70-1)

9 LVR function: enable or disable

External RC system clock/External Crystal System Clock/Internal RC system clock plus RTC clock/Internal

RC system plus I/O (last option not applicable to HT48R70A-1/HT48C70-1)

11 Internal RC frequency selection 3.2MHz, 1.6MHz, 800kHz or 400kHz.

C L R W D T 1 F l a g

C L R W D T 2 F l a g

S Y S

3 2 k H z R T C

C o n t r o l

L o g i c

C L R

/ 4

C o n f i g .

O p t i o n

S e l e c t

8 - b i t C o u n t e r

2 5 6 )

(

C L R

7 - b i t P r e s c a l e r

8 - t o - 1 M U X

W D T T i m e - o u t

W S 0 ~ W S 2

Watchdog Timer

/4 or RTC oscillator or disable

SYS

or RTC oscillator

SYS

/4 or RTC oscillator

SYS

enable or both disable

Page 61

Application Circuits

The following application circuits although based around the HT48R50A-1 device equally apply to all devices in the I/O type range.

0 . 1mF

D D

0 . 0 1mF

1 0 0 k

1 0 k

0 . 1mF

O S C

C i r c u i t

S e e B e l o w

O S C

4 7 0 p F

N M O S o p e n d r a i n

C 1

C 2

R 1

Chapter 1 Hardware Structure

V D D

R E S

V S S

O S C 1

O S C 2

H T 4 8 R 5 0 A - 1 / H T 4 8 C 5 0 - 1

O S C 1

O S C 2

O S C 1

O S C 2

P A 0 ~ P A 7

P B 2 ~ P B 7

P C 0 ~ P C 7

P D 0 ~ P D 7

P B 0 / B Z

P B 1 / B Z

T M R 0

T M R 1

P G 0 / I N T

R C S y s t e m O s c i l l a t o r

2 4 k

< R

< 1 M

O S C

C r y s t a l S y s t e m O s c i l l a t o r

F o r c o m p o n e n t v a l u e s , c o n s u l t O s c i l l a t o r s e c t i o n

1 0 p F

O S C 1

O S C 2

O S C 1

3 2 7 6 8 H z

O S C 2

I n t e r n a l R C O s c i l l a t o r

O S C 1 a n d O S C 2 l e f t u n c o n n e c t e d

I n t e r n a l R C O s c i l l a t o r w i t h R T C

O S C C i r c u i t

Page 62

I/O Type MCU

Page 63

Part II

Part II Programming Language

Programming Language

Page 64

I/O Type MCU

Page 65

Chapter 2 Instruction Set Introduction

Chapter 2

Instruction Set Introduction

Instruction Set

Central to the successful operation of any microcontroller is its instruction set, which is a set of pro gram instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to en able programmers to implement their application with the minimum of programming overheads.

For easier understanding of the various instruction codes, they have been subdivided into several functional groupings.

Instruction Timing

Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be ²CLR PCL² or ²MOV PCL, A². For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required.

Page 66

I/O Type MCU

Moving and Transferring Data

The transfer of data within the microcontroller program is one of the most frequently used opera tions. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator andvice-versa as well as being able tomove specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports.

Arithmetic Operations

The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of Carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the val ues in the destination specified.

Logical and Rotate Operations

The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional pro gramming steps.In all logical data operations, the zeroflag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application where rotate data operations are used is to implement multiplication and division calculations.

Branches and Control Transfer

Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction RET in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruc tion, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condi tion of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instruc tions arethe key to decision making and branchingwithin the program, perhaps determined by the condition of certain input switches or by the condition of internal data bits.

Bit Operations

The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where in

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Chapter 2 Instruction Set Introduction

dividual bits or port pins can bedirectly set high or low using either the ²SET [m].i² or ²CLR [m].i² in structions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used.

Table Read Operations

Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in in dividual memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be setup as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory.

Other Operations

In addition to the above functional instructions, a range of other instructions also exist such as ²HALT² instruction for Power-down operation and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic envi ronment. For their relevant operations, refer to the functional related sections.

Instruction Set Summary

Convention

x : bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address

Mnemonic Description Cycles Flag Affected

Arithmetic

ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m]

Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract DataMemory fromACC withCarry, resultin DataMemory Decimal adjust ACC for Addition with result in Data Memory

Note

1 1

Note

Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV

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Mnemonic Description Cycles Flag Affected

Logic Operation

AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m]

Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC

Increment & Decrement

INCA [m] INC [m] DECA [m] DEC [m]

Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory

Rotate

RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m]

Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry

Data Move

MOV A,[m] MOV [m],A MOV A,x

Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC

Bit Operation

CLR [m].i SET [m].i

Clear bit of Data Memory Set bit of Data Memory

1 1 1

note

Note

1 1 1

Note

Z Z Z Z Z Z Z Z Z Z Z

Z Z Z Z

None None

C None None

None None None

None None

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Chapter 2 Instruction Set Introduction

Mnemonic Description Cycles Flag Affected

Branch

JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI

Table Read

TABRDC [m] TABRDL [m]

Miscellaneous

NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT

Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt

Read table (current page) to TBLH and Data Memory Read table (last page) to TBLH and Data Memory

No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode

Note

note

Note

2 2 2 2

Note

1 1 1

Note

1 1

None None None None None None None None None None None None None

None None

None None None

TO, PDF TO, PDF TO, PDF

None None

TO, PDF

Note 1. Forskip instructions, if the result of the comparison involves a skip then two cycles are required,

if no skip takes place only one cycle is required.

2. Anyinstruction which changes the contents of the PCL will also require 2 cycles for execution.

3. Forthe ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² or ²CLR WDT2² instructions are executed. Otherwise the TO and PDF flags remain unchanged.

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Chapter 3 Instruction Definition

Chapter 3

Instruction Definition

ADC A,[m] Add Data Memory to ACC with Carry

Description The contentsof the specified Data Memory, Accumulator and the carry flag are added. The

result is stored in the Accumulator.

Operation

Affected flag(s) OV, Z, AC, C

ADCM A,[m] Add ACC to Data Memory with Carry

Description The contentsof the specified Data Memory, Accumulator and the carry flag are added. The

Operation

Affected flag(s) OV, Z, AC, C

ACC ¬ ACC+[m]+C

result is stored in the specified Data Memory.

[m] ¬ ACC+[m]+C

ADD A,[m] Add Data Memory to ACC

Description The contents of the specified Data Memory and the Accumulator are added. The result is

stored in the Accumulator.

Operation

Affected flag(s) OV, Z, AC, C

ADD A,x Add immediate data to ACC

Description The contentsof the Accumulator and the specified immediate data are added. The result is

Operation

Affected flag(s) OV, Z, AC, C

ADDM A,[m] Add ACC to Data Memory

Description The contents of the specified Data Memory and the Accumulator are added. The result is

Operation

Affected flag(s) OV, Z, AC, C

ACC ¬ ACC + [m]

stored in the Accumulator.

ACC ¬ ACC+x

stored in the specified Data Memory.

[m] ¬ ACC + [m]

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I/O Type MCU

AND A,[m] Logical AND Data Memory to ACC

Description Data in the Accumulator and the specified Data Memory perform a bitwise logical AND op

eration. The result is stored in the Accumulator.

Operation

Affected flag(s) Z

AND A,x Logical AND immediate data to ACC

Description Data in the Accumulator and the specified immediate data perform a bitwise logical AND

Operation

Affected flag(s) Z

ANDM A,[m] Logical AND ACC to Data Memory

Description Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op

Operation

Affected flag(s) Z

CALL addr Subroutine call

Description Unconditionally calls a subroutine at the specified address. The Program Counter then in

Operation

Affected flag(s) None

ACC ¬ ACC ²AND² [m]

operation. The result is stored in the Accumulator.

ACC ¬ ACC ²AND² x

eration. The result is stored in the Data Memory.

[m] ¬ ACC ²AND² [m]

crements by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruc tion.

Stack ¬ Program Counter + 1 Program Counter ¬ addr

CLR [m] Clear Data Memory

Description Each bit of the specified Data Memory is cleared to 0.

Operation

Affected flag(s) None

CLR [m].i Clear bit of Data Memory

Description Bit i of the specified Data Memory is cleared to 0.

Operation

Affected flag(s) None

[m] ¬ 00H

[m].i ¬ 0

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Chapter 3 Instruction Definition

CLR WDT Clear Watchdog Timer

Description The TO, PDF flags and the WDT are all cleared.

Operation WDT cleared

TO ¬ 0 PDF ¬ 0

Affected flag(s) TO, PDF

CLR WDT1 Pre-clear Watchdog Timer

Description The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc

tion with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Re petitively executing this instruction without alternately executing CLR WDT2 will have no effect.

Operation WDT cleared

TO ¬ 0 PDF ¬ 0

Affected flag(s) TO, PDF

CLR WDT2 Pre-clear Watchdog Timer

Description The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc

tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re petitively executing this instruction without alternately executing CLR WDT1 will have no effect.

Operation WDT cleared

TO ¬ 0 PDF ¬ 0

Affected flag(s) TO, PDF

CPL [m] Complement Data Memory

Description

Operation

Affected flag(s) Z

CPLA [m] Complement Data Memory with result in ACC

Description

Operation

Affected flag(s) Z

Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits which previously contained a 1 are changed to 0 and vice versa.

[m] ¬ [m]

Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged.

ACC ¬ [m]

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I/O Type MCU

DAA [m] Decimal-Adjust ACC for addition with result in Data Memory

Description Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value re

sulting fromthe previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by add ing 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition.

Operation

Affected flag(s) C

DEC [m] Decrement Data Memory

Description Data in the specified Data Memory is decremented by 1.

Operation

Affected flag(s) Z

DECA [m] Decrement Data Memory with result in ACC

Description Data in the specified Data Memory is decremented by 1. The result is stored in the Accu

Operation

Affected flag(s) Z

[m] ¬ ACC + 00H or [m] ¬ ACC + 06H or [m] ¬ ACC + 60H or [m] ¬ ACC + 66H

[m] ¬ [m] - 1

mulator. The contents of the Data Memory remain unchanged.

ACC ¬ [m] - 1

HALT Enter power down mode

Description This instruction stops the program execution and turns off the system clock. The contents

of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared.

Operation

Affected flag(s) TO, PDF

INC [m] Increment Data Memory

Description Data in the specified Data Memory is incremented by 1.

Operation

Affected flag(s) Z

TO ¬ 0 PDF ¬ 1

[m] ¬ [m]+1

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Chapter 3 Instruction Definition

INCA [m] Increment Data Memory with result in ACC

Description Data inthe specified Data Memory is incremented by 1. The result is stored in the Accumu

lator. The contents of the Data Memory remain unchanged.

Operation

Affected flag(s) Z

JMP addr Jump unconditionally

Description The contents of the Program Counter are replaced with the specified address. Program

Operation

Affected flag(s) None

MOV A,[m] Move Data Memory to ACC

Description The contents of the specified Data Memory are copied to the Accumulator.

Operation

Affected flag(s) None

MOV A,x Move immediate data to ACC

Description The immediate data specified is loaded into the Accumulator.

Operation

Affected flag(s) None

ACC ¬ [m]+1

execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction.

Program Counter ¬ addr

ACC ¬ [m]

ACC ¬ x

MOV [m],A Move ACC to Data Memory

Description The contents of the Accumulator are copied to the specified Data Memory.

Operation

Affected flag(s) None

NOP No operation

Description No operation is performed. Execution continues with the next instruction.

Operation No operation

Affected flag(s) None

OR A,[m] Logical OR Data Memory to ACC

Description Data inthe Accumulator and the specified Data Memory perform abitwise logical OR oper

Operation

Affected flag(s) Z

[m] ¬ ACC

ation. The result is stored in the Accumulator.

ACC ¬ ACC ²OR² [m]

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I/O Type MCU

OR A,x Logical OR immediate data to ACC

Description Data inthe Accumulator and the specified immediate data perform a bitwise logical OR op

eration. The result is stored in the Accumulator.

Operation

Affected flag(s) Z

ORM A,[m] Logical OR ACC to Data Memory

Description Data inthe specified Data Memory and the Accumulator perform abitwise logical OR oper

Operation

Affected flag(s) Z

RET Return from subroutine

Description The Program Counter is restored from the stack. Program execution continues at the

Operation

Affected flag(s) None

RET A,x Return from subroutine and load immediate data to ACC

Description The Program Counter is restored from the stack and the Accumulator loaded with the

Operation

Affected flag(s) None

ACC ¬ ACC ²OR² x

ation. The result is stored in the Data Memory.

[m] ¬ ACC ²OR² [m]

restored address.

Program Counter ¬ Stack

specified immediate data. Program execution continues at the restored address.

Program Counter ¬ Stack ACC ¬ x

RETI Return from interrupt

Description The Program Counter is restored from the stack and the interrupts are re-enabled by set-

ting the EMI bit. EMI is the enable master (global) interrupt bit (bit 0; register INTC). If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program.

Operation

Affected flag(s) None

RL [m] Rotate Data Memory left

Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit

Operation

Affected flag(s) None

Program Counter ¬ Stack EMI ¬ 1

[m].(i+1) ¬ [m].i; (i = 0~6) [m].0 ¬ [m].7

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Chapter 3 Instruction Definition

RLA [m] Rotate Data Memory left with result in ACC

Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit

0. The rotated result is stored in the Accumulator and the contents of the Data Memory re main unchanged.

Operation

Affected flag(s) None

RLC [m] Rotate Data Memory left through Carry

Description The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7

Operation

Affected flag(s) C

RLCA [m] Rotate Data Memory left through Carry with result in ACC

Description Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces

Operation

Affected flag(s) C

ACC.(i+1) ¬ [m].i; (i = 0~6) ACC.0 ¬ [m].7

replaces the Carry bit and the original carry flag is rotated into bit 0.

[m].(i+1) ¬ [m].i; (i = 0~6) [m].0 ¬ C C ¬ [m].7

the Carrybit and the original carry flag is rotated into the bit 0.The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.

ACC.(i+1) ¬ [m].i; (i = 0~6) ACC.0 ¬ C C ¬ [m].7

RR [m] Rotate Data Memory right

Description The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into

bit 7.

Operation

Affected flag(s) None

RRA [m] Rotate Data Memory right with result in ACC

Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 ro

Operation

Affected flag(s) None

[m].i ¬ [m].(i+1); (i = 0~6) [m].7 ¬ [m].0

tated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.

ACC.i ¬ [m].(i+1); (i = 0~6) ACC.7 ¬ [m].0

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I/O Type MCU

RRC [m] Rotate Data Memory right through Carry

Description The contentsof the specified Data Memory and thecarry flag are rotated right by 1 bit. Bit 0

replaces the Carry bit and the original carry flag is rotated into bit 7.

Operation

Affected flag(s) C

RRCA [m] Rotate Data Memory right through Carry with result in ACC

Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re

Operation

Affected flag(s) C

SBC A,[m] Subtract Data Memory from ACC with Carry

Description The contents of the specified Data Memory and the complement of the carry flag are

Operation

Affected flag(s) OV, Z, AC, C

[m].i ¬ [m].(i+1); (i = 0~6) [m].7 ¬ C C ¬ [m].0

places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.

ACC.i ¬ [m].(i+1); (i = 0~6) ACC.7 ¬ C C ¬ [m].0

subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is pos itive or zero, the C flag will be set to 1.

ACC ¬ ACC - [m] - C

SBCM A,[m] Subtract Data Memory from ACC with Carry and result in Data Memory

Description The contents of the specified Data Memory and the complement of the carry flag are sub-

tracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.

Operation

Affected flag(s) OV, Z, AC, C

SDZ [m] Skip if decrement Data Memory is 0

Description The contents of the specified Data Memory are first decremented by 1. If the result is 0 the

Operation

Affected flag(s) None

[m] ¬ ACC - [m] - C

following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.

[m] ¬ [m] - 1 Skip if [m] = 0

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Chapter 3 Instruction Definition

SDZA [m] Skip if decrement Data Memory is zero with result in ACC

Description The contents of the specified Data Memory are first decremented by 1. If the result is 0, the

following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy in struction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction.

Operation

Affected flag(s) None

SET [m] Set Data Memory

Description Each bit of the specified Data Memory is set to 1.

Operation

Affected flag(s) None

SET [m].i Set bit of Data Memory

Description Bit i of the specified Data Memory is set to 1.

Operation

Affected flag(s) None

SIZ [m] Skip if increment Data Memory is 0

Description The contents of the specified Data Memory are first incremented by 1. If the result is 0, the

Operation

Affected flag(s) None

ACC ¬ [m] - 1 Skip if ACC = 0

[m] ¬ FFH

[m].i ¬ 1

[m] ¬ [m]+1 Skip if [m] = 0

SIZA [m] Skip if increment Data Memory is zero with result in ACC

Description The contents of the specified Data Memory are first incremented by 1. If the result is 0, the

following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy in struction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.

Operation

Affected flag(s) None

ACC ¬ [m]+1 Skip if ACC = 0

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SNZ [m].i Skip if bit i of Data Memory is not 0

Description If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this re

quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction.

Operation

Affected flag(s) None

SUB A,[m] Subtract Data Memory from ACC

Description The specified Data Memory is subtracted from the contents of the Accumulator. The result

Operation

Affected flag(s) OV, Z, AC, C

SUBM A,[m] Subtract Data Memory from ACC with result in Data Memory

Description The specified Data Memory is subtracted from the contents of the Accumulator. The result

Operation

Affected flag(s) OV, Z, AC, C

Skip if [m].i ¹ 0

is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.

ACC ¬ ACC - [m]

is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.

[m] ¬ ACC - [m]

SUB A,x Subtract immediate data from ACC

Description The immediate data specified by the code is subtracted from the contents of the Accumu

lator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.

Operation

Affected flag(s) OV, Z, AC, C

SWAP [m] Swap nibbles of Data Memory

Description The low-order and high-order nibbles of the specified Data Memory are interchanged.

Operation

Affected flag(s) None

SWAPA [m] Swap nibbles of Data Memory with result in ACC

Description The low-order and high-order nibbles of the specified Data Memory are interchanged. The

Operation

Affected flag(s) None

ACC ¬ ACC - x

[m].3~[m].0 « [m].7 ~ [m].4

result isstored in the Accumulator. Thecontents of the Data Memory remain unchanged.

ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4 ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0

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Chapter 3 Instruction Definition

SZ [m] Skip if Data Memory is 0

Description If the contents of the specified Data Memory is 0, the following instruction is skipped. As

this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruc tion.

Operation Skip if [m] = 0

Affected flag(s) None

SZA [m] Skip if Data Memory is 0 with data movement to ACC

Description The contents of the specified Data Memory are copied to the Accumulator. If the value is

zero, the following instruction is skipped. As this requires the insertion of a dummy instruc tion while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction.

Operation

Affected flag(s) None

SZ [m].i Skip if bit i of Data Memory is 0

Description If bit i of the specified Data Memory is 0, the following instruction is skipped. As this re

Operation Skip if [m].i = 0

Affected flag(s) None

ACC ¬ [m] Skip if [m] = 0

quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction.If the result is not 0, the program proceeds with the following instruction.

TABRDC [m] Read table (current page) to TBLH and Data Memory

Description The low byte of the program code (current page) addressed by the table pointer (TBLP) is

moved to the specified Data Memory and the high byte moved to TBLH.

Operation

Affected flag(s) None

TABRDL [m] Read table (last page) to TBLH and Data Memory

Description The low byte of the program code (last page) addressed by the table pointer (TBLP) is

Operation

Affected flag(s) None

[m] ¬ program code (low byte) TBLH ¬ program code (high byte)

moved to the specified Data Memory and the high byte moved to TBLH.

[m] ¬ program code (low byte) TBLH ¬ program code (high byte)

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XOR A,[m] Logical XOR Data Memory to ACC

Description Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR op

eration. The result is stored in the Accumulator.

Operation

Affected flag(s) Z

XORM A,[m] Logical XOR ACC to Data Memory

Description Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR op

Operation

Affected flag(s) Z

XOR A,x Logical XOR immediate data to ACC

Description Data in the Accumulator and the specified immediate data perform a bitwise logical XOR

Operation

Affected flag(s) Z

ACC ¬ ACC ²XOR² [m]

eration. The result is stored in the Data Memory.

[m] ¬ ACC ²XOR² [m]

operation. The result is stored in the Accumulator.

ACC ¬ ACC ²XOR² x

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Chapter 4 Assembly Language and Cross Assembler

Chapter 4

Assembly Language and Cross Assembler

Assembly-Language programs are written as source files. They can be assembled into object files by the Holtek Cross Assembler. Object files are combined by the Cross Linker to generate a task file.

A source program is made up of statements and look up tables, giving directions to the Cross As sembler at assembly time or to the processor at run time. Statements are constituted by mnemon ics (operations), operands and comments.

Notational Conventions

The following list describes the notations used by this document.

Example of Convention Description of Convention

[optional items]

{choice1 | choice2}

Syntax elements that are enclosed by a pair of brackets are optional. For example, the syntax of the command line is as follows:

HASM [options] filename [;]

In the above command line, options and semicolon; are both optional, but filename is required, except for the following case: Brackets in the instruction operands. In this case, the brackets refer to memory address.

Braces and vertical bars stand for a choice between two or more items. Braces enclose the choices whereas vertical bars separate the choices. Only one item can be chosen.

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I/O Type MCU

Example of Convention Description of Convention

Three dots following an item signify that more items with the same form may be entered. For example, the directive PUB LIC has the following form:

Repeating elements...

Statement Syntax

The construction of each statement is as follows:

All fields are optional.

Each field (except the comment field) must be separated from other fields by at least one space

or one tab character. Fields are not case-sensitive, i.e., lower-case characters are changed to upper-case characters

before processing.

Name

Statements can be assigned labels to enable easy access by other statements. A name consists of the following characters:

with the following restrictions :

PUBLIC name1 [,name2 [,...]]

In the above form, the three dots following name2 indicate that many names can be entered as long as each is pre ceded by a comma.

[name][operation][operands][;comment]

A~Za~z0~9?_@

· 0~9 cannot be the first character of a name

· ? cannot stand alone as a name

· Only the first 31 characters are recognized

Operation

The operation defines the statement action of which two types exist, directives and instructions. Di rectives give directions to the Cross Assembler, specifying the manner in which the Cross Assem bler is to generate the object code at assembly time. Instructions, on the other hand, give directions tothe processor. They are translated to object code at assembly time, the object codein turn controls the behavior of the processor at run time.

Operand

Operands define the data used by directives and instructions. They can be made up of symbols, constants, expressions and registers.

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Comment

Comments are the descriptions of codes. They are used for documentation only and are ignored by the Cross Assembler. Any text following a semicolon is considered a comment.

Assembly Directives

Directives give direction to the Cross Assembler, specifying the manner in which the Cross Assem bler generates object code at assembly time. Directives can be further classified according to their behavior as described below.

Conditional Assembly Directives

The conditional block has the following form:

statements

[ELSE statements]

ENDIF

Syntax

IF expression IFE expression

Description

The directives IF and IFE test the expression following them. The IF directive grants assembly if the value of the expression is true, i.e. non-zero. The IFE directive grants assembly if the value of the expression is false, i.e. zero.

· Example

IF debugcase

ENDIF

In this example, the value of the variable ACC1 is set to 5 and the username is declared as an external variable if the symbol debugcase is evaluated as true, i.e. nonzero.

ACC1 equ 5 extern username: byte

Syntax

IFDEF name IFNDEF name

Description The directives IFDEF and IFNDEF test whether or not the given name has been defined. The IFDEF directive grants assembly only if the name is a label, a variable or a symbol. The IFNDEF di rective grants assembly only if the name has not yet been defined. The conditional assembly direc tives support a nesting structure, with a maximum nesting level of 7.

Example

IFDEF buf_flag

ENDIF

In this example, the buffer is allocated only if the buf_flag has been previously defined.

buffer DB 20 dup(?)

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I/O Type MCU

File Control Directives

Syntax

INCLUDE file-name

INCLUDE ²file-name²

Description

This directive inserts source codes from the source file given by file-name into the current source file during assembly. Cross Assembler supports at most 7 nesting levels. Example

INCLUDE macro.def

In this example, the Cross Assembler inserts the source codes from the file macro.def into the current source file.

Syntax

PAGE size

Description

This directive specifies the number of the lines in a page of the program listing file. The page size must be within the range from 10 to 255, the default page size is 60. Example

PAGE 57

This example sets the maximum page size of the listing file to 57 lines.

Syntax

.LIST .NOLIST

· Description

The directives .LIST and .NOLIST decide whether or not the source program lines are to be copied to the program listing file. .NOLIST suppresses copying of subsequent source lines to the program listing file. .LIST restores the copying of subsequent source lines to the program listing file. The default is .LIST.

· Example

.NOLIST mov a, 1 mov b1, a .LIST

In this example, the two instructions in the block enclosed by .NOLIST and .LIST are sup pressed from copying to the source listing file.

Syntax

.LISTMACRO .NOLISTMACRO

Description The directive .LISTMACRO causes the Cross Assembler to list all the source statements, in cluding comments, in a macro. The directive .NOLISTMACRO suppresses the listing of all macro expansions. The default is .NOLISTMACRO.

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Syntax

.LISTINCLUDE .NOLISTINCLUDE

Description

The directive .LISTINCLUDE inserts the contents of all included files into the program listing. The directive .NOLISTINCLUDE suppresses the addition of included files. The default is .NOLISTINCLUDE.

Syntax

MESSAGE ¢text-string¢

Description

The directive MESSAGE directs the Cross Assembler to display the text-string on the screen. The characters in the text-string must be enclosed by a pair of single quotation marks.

Syntax

ERRMESSAGE ¢error-string¢

Description

The directive ERRMESSAGE directs the Cross Assembler to issue an error. The characters in the error-string must be enclosed by a pair of single quotation marks.

Program Directives

Syntax (comment)

; text

Description

A comment consists of characters preceded by a semicolon (;) and terminated by an embedded carriage-return/line-feed.

® Syntax

name .SECTION [align][combine] ¢class¢

· Description

The .SECTION directive marks the beginning of a program section. A program section is a collection ofinstructions and/or data whose addresses are relative to the section beginning withthe name which defines that section. The name of a section can be unique or be the same as the name given to other sections in the program. Sections with the same complete names are treated as the same section. The optional align type defines the alignment of the given section. It can be one of the follow ing:

BYTE uses any byte address (the default align type) WORD uses any word address PARA uses a paragraph address PAGE uses a page address

For the CODE section, the byte address is in a single instruction unit. BYTE aligns the section at any instruction address, WORD aligns the section at any even instruction address, PARA aligns the section at any instruction address which is a multiple of 16, and PAGE aligns the section at any instruction address with a multiple of 256.

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I/O Type MCU

For DATAsections, the byte address is in one byte units (8 bits/byte). BYTE aligns the section at any byte address, WORD aligns the section at any even address, PARA aligns the section at any address which is a multiple of 16, and PAGE aligns the section at any address which is a multiple of 256. The optional combine type defines the way of combining sections having the same complete name (section and class name). It can be any one of the following:

COMMON

Creates overlapping sections by placing the start of all sections with the same complete name at the same address. The length of the resulting area is the length of the longest section. AT address

Causes all label and variable addresses defined in a section to be relative to the given ad dress. The address can be any valid expression except a forward reference. It is an absolute address in a specified ROM/RAM bank and must be within the ROM/RAM range.

If no combine type is given, the section is combinative, i.e., this section can be concatenated with all sections having the same complete name to form a single, contiguous section.

The class type defines the sections that are to be loaded in the contiguous memory. Sections with thesame class name are loaded into the memory one after another. The class name CODE is used for sections stored in ROM, and the class name DATA is used for sections stored in RAM. Thecomplete name of a section consists of a section name and a class name. The named section includes all codes and data below (after) it until the next section is defined.

Syntax

ROMBANK banknum section-name [,section-name,...]

Description

This directive declares which sections are allocated to the specified ROM bank. The banknum specifies the ROM bank, ranging from 0 to the maximum bank number of the destination MCU. The section-name is the name of the section defined previously in the program. More than one section can be declared in a bank as long as the total size of the sections does not exceed the bank size of 8K words. If this directive is not declared, bank 0 is assumed and all CODE sections defined in this program will be in bank 0. If a CODE section is not declared in any ROM bank, then bank 0 is assumed.

® Syntax

RAMBANK banknum section-name [,section-name,...]

· Description

This directive is similar to ROMBANK except that it specifies the RAM bank, the size of RAM bank is 256 bytes.

Syntax

END

Description This directive marks the end of a program. Adding this directive to any included file should be avoided.

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Syntax

ORG expression

Description

This directive sets the location counter to expression. The subsequent code and data offsets begin at the new offset specified by expression. The code or data offset is relative to the be ginning of the section where the directive ORG is defined. The attribute of a section determines the actual value of offset, absolute or relative. Example

ORG 8 mov A, 1

In this example, the statement mov A, 1 begins at location 8 in the current section.

Syntax

PUBLIC name1 [,name2 [,...]] EXTERN name1:type [,name2:type [, ...]]

Description

The PUBLIC directive marks the variable or label specified by a name that is available to other modules in the program. The EXTERN directive, on the other hand, declares an external vari able, label or symbol of the specified name and type. The type can be one of the four types: BYTE, WORD and BIT (these three types are for data variables), and NEAR (a label type and used by call or jmp). Example

PUBLIC start, setflag EXTERN tmpbuf:byte

CODE .SECTION ¢CODE¢ start:

mov a, 55h call setflag

....

setflag proc

mov tmpbuf, a

ret setflag endp end

In this example, both the label start and the procedure setflag are declared as public variables. Programs in other sources may refer to these variables. The variable tmpbuf is also declared as external. There should be a source file defining a byte that is named tmpbuf and is declared as a public variable.

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Syntax

name PROC

name ENDP

Description

The PROC and ENDP directives mark a block of code which can be called or jumped to from other modules. The PROC creates a label name which stands for the address of the first instruction of a procedure. The Cross Assembler will set the value of the label to the current value of the location counter. Example

toggle PROC mov tmpbuf, a mov a, 1 xorm a, flag mov a, tmpbuf ret toggle ENDP

Syntax

[label:] DC expression1 [,expression2 [,...]]

Description

The DC directive stores the value of expression1, expression2 etc. in consecutive mem ory locations. This directive is used for the CODE section only. The bit size of the result value is dependent on the ROM size of the MCU. The Cross Assembler will clear any redundant bits; expression1 has to be a value or a label. This directive may also be employed to setup the ta ble in the code section. Example

table1: DC 0128h, 025CH

In this example, the Cross Assembler reserves two units of ROM space and also stores 0128H and 025CH into these two ROM units.

I/O Type MCU

Data Definition Directives

An assembly language program consists of one or more statements and comments. A statement or comment is a composition of characters, numbers, and names. The assembly language supports integer numbers. An integer number is a collection of binary, octal, decimal, or hexadecimal digits along with an optional radix. If no radix is given, the Cross Assembler uses the default radix (decimal). The table lists the digits that can be used with each radix.

Radix

Type Digits

Binary 01

Octal 01234567

Decimal 0123456789

Hexadecimal 0123456789ABCDEF

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Syntax

[name] DB value1 [,value2 [, ...]] [name] DW value1 [,value2 [, ...]] [name] DBIT [name] DB repeated-count DUP(?) [name] DW repeated-count DUP(?)

Description

These directives reserve the number of bytes/words specified by the repeated-count or reserve bytes/words only. value1 and value2 should be ? due to the microcontroller RAM. The Cross Assembler will not initialize the RAM data. DBIT reserves a bit. The content ? denotes uninitialized data, i.e., reserves the space of the data. The Cross Assembler will gather every 8 DBIT together and reserve a byte for these 8 DBIT variables. Example

DATA .SECTION ¢DATA¢ tbuf DB ? chksum DW ? flag1 DBIT sbuf DB ? cflag DBIT

In this example, the Cross Assembler reserves byte location 0 for tbuf, location 1 and 2 for chksum, bit 0 of location 3 for flag1, location 4 for sbuf and bit 1 of location 3 for cflag.

Syntax

name LABEL {BIT|BYTE|WORD}

Description

The name with the data type has the same address as the following data variable Example

lab1 LABEL WORD d1 DB ? d2 DB ?

In this example, d1 is the low byte of lab1 and d2 is the high byte of lab1.

® Syntax

name EQU expression

· Description The EQU directive creates absolute symbols, aliases, or text symbols by assigning an expres- sion to name. An absolute symbol is a name standing for a 16-bit value; an alias is a name representing another symbol; a text symbol is a name for another combination of characters. The name must be unique, i.e.not having been defined previously. The expression can be an inte ger, a string constant, an instruction mnemonic, a constant expression, or an address expres sion.

Example

accreg EQU 5 bmove EQU mov

In this example, the variable accreg is equal to 5, and bmove is equal to the instruction mov.

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I/O Type MCU

Macro Directives

Macro directives enable a block of source statements to be named, and then that name to be re-used inthe source file to represent the statements.During assembly, the Cross Assemblerauto matically replaces each occurrence of the macroname with the statements in the macro definition.

A macro can be defined at any place in the source file as long as the definition precedes the first source line that calls this macro. In the macro definition, the macro to be defined may refer to other macros which have been previously defined. The Cross Assembler supports a maximum of 7 nest ing levels.

Syntax

name MACRO [dummy-parameter [, ...]]

The Cross Assembler supports a directive LOCAL for the macro definition.

Syntax

name LOCAL dummy-name [, ...]

statements

ENDM

Description The LOCAL directive defines symbols available only in the defined macro. It must be the first line following the MACRO directive, if it is present. The dummy-name is a temporary name that is re placed by a unique name when the macro is expanded. The Cross Assembler creates a new ac tual name for dummy-name each time the macro is expanded. The actual name has the form ??digit, where digit is a hexadecimal number within the range from 0000 to FFFF. A label should be added to the LOCAL directive when labels are used within the MACRO/ENDM block. Otherwise, the Cross Assembler will issue an error if this MACRO is referred to more than once in the source file. In the following example, tmp1 and tmp2 are both dummy parameters, and are replaced by actual parameters when calling this macro. label1 and label2 are both declared LOCAL, and are replaced by ??0000 and ??0001 respectively at the first reference, if no other MACRO is referred. If no LOCAL declaration takes place, label1 and label2 will be referred to labels, similar to the declaration in the source program. At the second reference of this macro, a multiple define error message is displayed.

Delay MACRO tmp1, tmp2

LOCAL label1, label2 mov a, 70h mov tmp1, a

label1:

mov tmp2, a

label2:

clr wdt1 clr wdt2 sdz tmp2 jmp label2 sdz tmp1 jmp label1 ENDM

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The following source program refers to the macro Delay ...

; T . A S M ; S a m p l e p r o g r a m f o r M A C R O . . L i s t M a c r o D e l a y M A C R O t m p 1 , t m p 2 L O C A L l a b e l 1 , l a b e l 2 m o v a , 7 0 h m o v t m p 1 , a l a b e l 1 : m o v t m p 2 , a l a b e l 2 : c l r w d t 1 c l r w d t 2 s d z t m p 2 j m p l a b e l 2 s d z t m p 1 j m p l a b e l 1 E N D M

d a t a . s e c t i o n ' d a t a ' B C n t d b ? S C n t d b ?

c o d e . s e c t i o n a t 0 ' c o d e ' D e l a y B C n t , S C n t e n d

The Cross Assembler will expand the macro Delay as shown in the following listing file. Note that the offset of each line in the macro body, from line 4 to line 17, is 0000. Line 24 is expanded to 11 lines and forms the macro body. In addition the formal parameters, tmp1 and tmp2, are replaced with the actual parameters, BCnt and SCnt, respectively.

F i l e : T . a s m H o l t e k C r o s s - A s s e m b l e r V e r s i o n 2 . 8 0 P a g e 1

1 0 0 0 0 ; T . A S M 2 0 0 0 0 ; S a m p l e p r o g r a m f o r M A C R O . 3 0 0 0 0 . L i s t M a c r o 4 0 0 0 0 D e l a y M A C R O t m p 1 , t m p 2 5 0 0 0 0 L O C A L l a b e l 1 , l a b e l 2 6 0 0 0 0 m o v a , 7 0 h 7 0 0 0 0 m o v t m p 1 , a 8 0 0 0 0 l a b e l 1 : 9 0 0 0 0 m o v t m p 2 , a 1 0 0 0 0 0 l a b e l 2 : 1 1 0 0 0 0 c l r w d t 1 1 2 0 0 0 0 c l r w d t 2 1 3 0 0 0 0 s d z t m p 2 1 4 0 0 0 0 j m p l a b e l 2 1 5 0 0 0 0 s d z t m p 1 1 6 0 0 0 0 j m p l a b e l 1 1 7 0 0 0 0 E N D M 1 8 0 0 0 0 1 9 0 0 0 0 d a t a . s e c t i o n ' d a t a ' 2 0 0 0 0 0 0 0 B C n t d b ? 2 1 0 0 0 1 0 0 S C n t d b ? 2 2 0 0 0 2 2 3 0 0 0 0 c o d e . s e c t i o n a t 0 ' c o d e ' 2 4 0 0 0 0 D e l a y B C n t , S C n t 2 4 0 0 0 0 0 F 7 0 1 m o v a , 7 0 h 2 4 0 0 0 1 0 0 8 0 R 1 m o v B C n t , a 2 4 0 0 0 2 1 ? ? 0 0 0 0 : 2 4 0 0 0 2 0 0 8 0 R 1 m o v S C n t , a 2 4 0 0 0 3 1 ? ? 0 0 0 1 :

2 4 0 0 0 3 0 0 0 1 1 c l r w d t 1 2 4 0 0 0 4 0 0 0 5 1 c l r w d t 2 2 4 0 0 0 5 1 7 8 0 R 1 s d z S C n t 2 4 0 0 0 6 2 8 0 3 1 j m p ? ? 0 0 0 1 2 4 0 0 0 7 1 7 8 0 R 1 s d z B C n t 2 4 0 0 0 8 2 8 0 2 1 j m p ? ? 0 0 0 0 2 5 0 0 0 9 e n d

0 E r r o r s

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Assembly Instructions

The syntax of an instruction has the following form:

[name:] mnemonic [operand1[,operand2]] [;comment]

where

name: ® label name mnemonic ® instruction name (keywords) operand1 ® registers

operand2 ® registers

Name

A name is made up of letters, digits, and special characters, and is used as a label.

Mnemonic

Mnemonic is an instruction name dependent upon the type of the MCU used in the source pro gram.

I/O Type MCU

memory address

memory address immediate value

Operand, Operator and Expression

Operands (source or destination) are the argument defining values that are to be acted on by instructions. They can be constants, variables, registers, expressions or keywords. When using the instruction statements, care must be taken to select the correct operand type, i.e. source operand or destination operand. The dollar sign $ is a special operand, namely, the current location operand.

An expression consists of many operands that are combined to describe a value or a memory location. The combined operators are evaluated at assembly time. They can contain constants, symbols, or any combination of constants and symbols that are separated by arithmetic operators.

Operators specify the operations to be performed while combining the operands of an expression. The Cross Assembler provides many operators to combine and evaluate operands. Some opera tors work with integer constants, some with memory values, and some with both. Operators han dle thecalculation of constant values that are known at the assembly time. The following are some operators provided by the Cross Assembler.

Arithmetic operators+-*/%(MOD)

SHL and SHR operators

Syntax

expression SHR count expression SHL count

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The values of these shift bit operators are all constant values. The expression is shifted right SHR or left SHL by the number of bits specified by count. If bits are shifted out of position, the corresponding bits that are shifted in are zero-filled. The following are such examples:

mov A, 01110111b SHR 3 ; result ACC=00001110b

mov A, 01110111b SHL 4 ; result ACC=01110000b

Bitwise operators NOT, AND, OR, XOR

Syntax

NOT expression expression1 AND expression2 expression1 OR expression2 expression1 XOR expression2

NOT is a bitwise complement. AND is a bitwise AND. OR is a bitwise inclusive OR. XOR is a bitwise exclusive OR.

OFFSET operator

Syntax

OFFSET expression

The OFFSET operator returns the offset address of an expression. The expression can be a label,a variable, or other direct memory operand. The value returned by the OFFSET operator is an immediate operand.

LOW, MID and HIGH operator

Syntax

LOW expression MID expression HIGH expression

The LOW/MID/HIGH operator returns the value of an expression if the result of the expression is an immediate value. The LOW/MID/HIGH operators will then take the low/middle/high

byte of this value. But if the expression is a label, the LOW/MID/HIGH operator will take the values of the low/middle/high byte of the program count of this label.

· BANK operator

- Syntax

BANK name

The BANK operator returns the bank number allocated to the section of the name declared. If the name is a label then it returns the rom bank number. If the name is a data variable then it returns

the ram bank number. The format of the bank number is the same as the BP defined. For more information of the format please refer to the data sheets of the corresponding MCUs. (Note: The format of the BP might be different between MCUs.) Example 1:

mov A, BANK start mov BP,A jmp start

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Miscellaneous

Forward References

The Cross Assembler allows reference to labels, variable names, and other symbols before they are declared in the source code (forward named references). But symbols to the right of EQU are not allowed to be forward referenced.

Example 2:

mov A, BANK var mov BP,A mov A, OFFSET var mov MP1,A mov A,IAR1

Operator precedence

Precedence Operators

1 (Highest) 2 3 4 5

6 7 8 9 (Lowest)

I/O Type MCU

(),[] +, - (unary), LOW, MID, HIGH, OFFSET, BANK *, /, %, SHL, SHR +, - (binary) > (greater than), >= (greater than or equal to), < (less than), <= (less than or equal to) == (equal to), != (not equal to)

! (bitwise NOT)

& (bitwise AND) |(bitwise OR), ^(bitwise XOR)

Local Labels

A local label is a label with a fixed form such as $number. The number can be 0~29. The function of a local label is the same as a label except that the local label can be used repeatedly. The local label should be used between any two consecutive labels and the same local label name may used between other two consecutive labels. The Cross Assembler will transfer every local label into a unique label before assembling the source file. At most 30 local labels can be defined between two consecutive labels. Example.

Label1: ; label

Label2: ; label

Label3:

$1: ;; local label

mov a, 1 jmp $3

$2: ;; local label

mov a, 2 jmp $1

$3: ;; local label

jmp $2

jmp $1

$0: ;; local label

jmp Label1

$1: jmp $0

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Reserved Assembly Language Words

The following tables list all reserved words used by the assembly language.

Reserved Names (directives, operators)

$ DUP INCLUDE NOT

* DW LABEL OFFSET

+ ELSE .LIST OR

. ENDIF .LISTMACRO PAGE

/ ENDM LOCAL PARA

= ENDP LOW PROC

? EQU MACRO PUBLIC

[ ] ERRMESSAGE MESSAGE RAMBANK

AND EXTERN MID ROMBANK

BANK HIGH MOD .SECTION

BYTE IF NEAR SHL

DB IFDEF .NOLIST SHR

DBIT IFE .NOLISTINCLUDE WORD

DC IFNDEF .NOLISTMACRO XOR

Reserved Names (instruction mnemonics)

ADC HALT RLCA SUB

ADCM INC RR SUBM

ADD INCA RRA SWAP

ADDM JMP RRC SWAPA

AND MOV RRCA SZ

ANDM NOP SBC SZA

CALL OR SBCM TABRDC

CLR ORM SDZ TABRDL

CPL RET SDZA XOR

CPLA RETI SET XORM

DAA RL SIZ

DEC RLA SIZA

DECA RLC SNZ

END .LISTINCLUDE ORG

Reserved Names (registers names) A WDT WDT1 WDT2

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Cross Assembler Options

The Cross Assembler options can be set via the Options menu Project command in HT-IDE3000. The Cross Assembler Options is located on the center part of the Project Option dialog box.

The symbols could be defined in the Define Symbol edit box.

Syntax

symbol1[=value1][, symbol2[=value2] [, ...]]

Example,

debugflag=1, newver=3

The check box of the Generate listing file is used to decide whether the listing file should be gener ated or not. If the check box is checked, the listing file will be generated. Otherwise, it won¢tbegen erated.

Assembly Listing File Format

The Assembly Listing File contains the source program listing and summary information. The first line of each page is a title line which include company name, the Cross Assembler version num ber, source file name, date/time of assembly and page number.

Source Program Listing

Each line in the source program has the following syntax:

I/O Type MCU

line-number offset [code] statement

· Line-number is the number of the line starting from the first statement in the assembly source file (4 decimal digits).

· The 2nd field - offset - is the offset from the beginning of the current section to the code (4 hexadecimal digits)

· The 3rd field - code - is present only if the statement generates code or data (two hexadecimal 4-digit data) The code shows the numeric value in hexadecimal if the value is known at assembly time. Otherwise, a proper flag will indicate the action required to compute the value. The following two flags may appear behind the code field.

R ® relocatable address (Cross Linker must resolve) E ® external symbol (Cross Linker must resolve)

The following flag may appear before the code field

= ® EQU or equal-sign directive

The following 2 flags may appear in the code field

---- ® section address (Cross Linker must resolve) nn[xx] ® DUP expression: nn DUP(?)

The 4th field - statement - is the source statement shown exactly as it appears in the source file, or as expanded by a macro. The following flags may appear before a statement.

n ® Macro-expansion nesting level C ® line from INCLUDE file

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Summary

0 1 2 3 4 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0

o o o o h h h h h h h h

l l l l

s o u r c

E C R n

e - p r o

g r a m-s t a t e m

llll® line number (4 digits, right alignment) oooo ® offset of code (4 digits) hhhh ® two 4-digits for opcode

E ® external reference C ® statement from included file R ® relocatable name n ® Macro-expansion nesting level

Summary of Assembly

The total warning number and total error number is the information provided at the end of the Cross Assembler listing file.

Miscellaneous

If any errors occur during assembly, each error message and error number will appear directly be low the statement where the error occurred.

5 6

e n t

. . .

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Example of assembly listing file

F i l e : S A M P L E . A S M H o l t e k C r o s s - A s s e m b l e r V e r s i o n 2 . 8 6 P a g e 1

I/O Type MCU

0 0 0 0

1 0

0 0 0 0

1 1

0 0 0 0

1 2

0 0 0 0

1 3

0 0 0 0

1 4

0 0 0 0

1 5

0 0 0 0

1 6

0 0 0 0

1 7

0 0 0 0

1 8

0 0 0 0

1 9

0 0 0 0

2 0

0 0 0 0

2 1

0 0 0 0

2 2

0 0 0 0 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 3 3 3 3 3 3 3 3 4 3 5 3 6 3 7 3 8 3 9

4 0

0 0 0 0

0 0 0 1

0 0 0 2

0 0 0 3

0 0 0 0

0 0 0 1

0 0 0 2

0 0 0 3

0 0 0 4

0 0 0 5

0 0 0 6

0 0 0 7

0 0 0 8

0 0 0 9

0 0 0 A

0 0 0 B

0 0 0 C

0 0 1 0

0 0 0 0 0 0

0 F 5 5 0 0 8 0 0 0 8 0 0 F A A 0 0 9 3

0 F 0 0 0 0 9 2

1 F 1 4 0 7 0 0 0 F 0 0 0 F 0 0 2 8 0 0

1 2 3 4 A B C D

E r r o r s

5 6 7 8 E F 1 2

p a g e 6 0 m e s s a g e

. l i s t i n c l u d e . l i s t m a c r o

# i n c l u d e

p a

p a c

p b

p b c

C C

p c p c c

C C

e x t e r n e x t e r n

c l r p b c l r p b e n d m

c l r p a m o v a , m o v p a , c l r p b e n d m

d a t a b 1 b 2 b i t 1

c o d e m o v m o v

m o v

m o v m o v c l r p a m o v a

m o v

c l r p b

c l r

m o v

j m p

d w

e n d

' S a m p l e P r o g r a m 1 '

" s a m p l e . i n c "

e x t l a b e x t b 1

0 0 h

[ 1 2 h ] [ 1 3 h ] [ 1 4 h ] [ 1 5 h ] [ 1 6 h ] [ 1 7 h ]

b y t e

n e a r

e q u e q u e q u e q u e q u e q u

m a c r o

. s e c t i o n ' d a t a ' d b ? d b ? d b i t

. s e c t i o n ' c o d e ' a , 0 5 5 h b 1 , a e x t b 1 , a a , 0 a a h p a c , a

, 0 0 h

[ 1 2 h ] , a

[ 1 4 h ]

a , b 1 a , b a n k e x t l a b a , o f f s e t e x t b 1 e x t l a b

1 2 3 4 h , 5 6 7 8 h , 0 a b c d h , 0 e f 1 2 h

Holtek HT48R10A-1, HT48R30A-1, HT48R50A-1, HT48R70A-1 Handbook

Specifications and Main Features

Frequently Asked Questions

User Manual