HOLTEK HT48F06E User Manual

I/O Type 8-Bit Flash MCU With EEPROM

Technical Document

Tools Information

FAQs

Application Note

Features

Operating voltage: f

=4MHz: 2.2V~5.5V

SYS

=8MHz: 3.3V~5.5V

SYS

Low voltage reset function

13 bidirectional I/O lines (max.)

Interrupt input shared with an I/O line

8-bit programmable timer/event counter with overflow interrupt and 8-stage prescaler

On-chip crystal and RC oscillator

Watchdog Timer

100,000 erase/write cycles Flash program memory

1024´14 program memory ROM (Flash)

128´8 data memory EEPROM

64´8 data memory RAM

Buzzer driving pair and PFD supported

HT48F06E

HALT function and wake-up feature reduce power consumption

2-level subroutine nesting

Up to 0.5ms instruction cycle with 8MHz system clock at V

=5V

Bit manipulation instruction

14-bit table read instruction

63 powerful instructions

106erase/write cycles EEPROM data memory

EEPROM data retention > 10 years

All instructions in one or two machine cycles

In system programming (ISP)

18-pin DIP/SOP package 20-pin SSOP package

General Description

The HT48F06E is an 8-bit high performance, RISC architecture microcontroller device specifically designed for multiple I/O control product applications.

The advantages of low power consumption, I/O flexibil ity, timer functions, oscillator options, HALT and

wake-up functions, watchdog timer, buzzer driver, as well aslow cost,enhance theversatility ofthese devices to suit a wide range of application possibilities such as industrial control, consumer products, subsystem con-

trollers, etc.

Rev. 1.00 1 January 9, 2007

Block Diagram

P r o g r a m

M e m o r y

P r o g r a m

C o u n t e r

S T A C K 0

S T A C K 1

I N T / P C 0

I n t e r r u p t

C i r c u i t

I N T C

T M R

T M R C

HT48F06E

P r e s c a l e r

U X

T M R / P C 1

S Y S

I n s t r u c t i o n

R e g i s t e r

I n s t r u c t i o n

D e c o d e r

T i m i n g

G e n e r a t o r

O S C 2 O S C 1

R E S V D D V S S

Pin Assignment

P C 0 / I N T

P A 3

P A 2

P A 1

P A 0

P B 2

P B 1 / B Z

P B 0 / B Z

V S S

M P

M U X

A L U

S h i f t e r

A C C

D a t a M e m o r y

E E P R O M

1 8

1 7

1 6

1 5

1 4

1 3

1 2

1 1

1 0

H T 4 8 F 0 6 E

1 8 D I P - A / S O P - A

M U X

D A T A

M e m o r y

S T A T U S

P A 4

P A 5

P A 6

P A 7

O S C 2

O S C 1

V D D

R E S

P C 1 / T M R

E E C R

P C 0

W D T S

W D T P r e s c a l e r

P O R T C

P C C

P C

B Z / B Z

P B C

P O R T B

P B

P A C

P O R T A

P A

P A 3

P A 2

P A 1

P A 0

P B 2

P B 1 / B Z

P B 0 / B Z

V S S

P C 0 / I N T

N C

W D T

1 0

H T 4 8 F 0 6 E

2 0 S S O P - A

P C 1

P C 0 ~ P C 1

P B 0 ~ P B 2

P A 0 ~ P A 7

2 0

1 9

1 8

1 7

1 6

1 5

1 4

1 3

1 2

1 1

M U X

R C O S C

P A 4

P A 5

P A 6

P A 7

O S C 2

O S C 1

V D D

R E S

P C 1 / T M R

N C

/ 4

S Y S

Rev. 1.00 2 January 9, 2007

Pin Description

Pin Name I/O Options Description

PA0~PA7 I/O

PB0/BZ PB1/BZ PB2

VSS

PC0/INT PC1/TMR

RES

VDD

OSC1 OSC2

Note:

²*² All pull-high resistors are controlled by an option bit.

Pull-high*

Wake-up

Pull-high*

I/O

PB0 or BZ PB1 or BZ

¾¾

I/O Pull-high*

¾¾

Crystal or RC

Bidirectional 8-bit input/output port. Each pin can be configured as a wake-up input by options. Software instructions determine the CMOS output or Schmitt trigger input with pull-high resistor (determined by pull-high options).

Bidirectional 3-bit input/output port. Software instructions determine the CMOS out put orSchmitt triggerinput with pull-high resistor (determined by pull-high options). The PB0 and PB1 are pin-shared with BZ and BZ selected as buzzer driving output, the output signals come from an internal PFD generator (shared with timer/event counter).

Negative power supply, ground

Bidirectional I/O lines. Software instructions determine the CMOS output or Schmitt trigger input with pull-high resistor (determined by pull-high options). The external interrupt and timer input are pin-shared with PC0 and PC1, respectively. The exter nal interrupt input is activated on a high to low transition.

Schmitt trigger reset input. Active low.

Positive power supply

OSC1and OSC2 are connected to an RC network or Crystal (determined by op tions) for the internal system clock. In the case of RC operation, OSC2 is the output terminal for 1/4 system clock.

HT48F06E

, respectively. Once PB0 or PB1 is

Absolute Maximum Ratings

Supply Voltage...........................VSS-0.3V to VSS+6.0V

Input Voltage..............................V

Total ..............................................................150mA

-0.3V to VDD+0.3V

Total Power Dissipation .....................................500mW

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may

cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.

D.C. Characteristics

Symbol Parameter

DD1

DD2

DD3

STB1

Operating Voltage

Operating Current (Crystal OSC)

Operating Current (RC OSC)

Operating Current (Crystal OSC, RC OSC)

Standby Current (WDT Enabled)

Storage Temperature ............................-50°Cto125°C

Operating Temperature...........................-40°Cto85°C

Total............................................................-100mA

Test Conditions

Conditions

=4MHz

SYS

=8MHz

SYS

No load, f

SYS

=4MHz

=8MHz

No load*,system HALT

Min. Typ. Max. Unit

2.2

3.3

0.6 1.5 mA

24mA

0.8 1.5 mA

2.5 4 mA

48mA

¾¾

Ta=25°C

5.5 V

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HT48F06E

Symbol Parameter

STB2

IL1

IH1

IL2

IH2

LVR

Standby Current (WDT Disabled)

Input Low Voltage for I/O Ports

Input High Voltage for I/O Ports

Input Low Voltage (RES)

Input High Voltage (RES)

Low Voltage Reset Voltage

I/O Port Sink Current

I/O Port Source Current

Pull-high Resistance

Test Conditions

Conditions

No load*,system HALT

¾¾

LVR enabled 2.7 3.0 3.3 V

=0.1V

=0.9V

5V 10 20

Min. Typ. Max. Unit

¾¾

0.7V

0.9V

-2 -4 ¾

-5 -10 ¾

20 60 100

10 30 50

Note: ²*² All tests are conducted with the I/O pins setup as outputs and set to a low value.

A.C. Characteristics

Symbol Parameter

SYS1

SYS2

TIMER

WDTOSC

WDT1

WDT2

RES

SST

INT

System Clock (Crystal OSC)

System Clock (RC OSC)

Timer I/P Frequency (TMR)

Watchdog Oscillator Period

Watchdog Time-out Period (WDT OSC)

Watchdog Time-out Period (System Clock)

External Reset Low Pulse Width

System Start-up Timer Period

Interrupt Pulse Width

Test Conditions

5V 8 17 33 ms

Conditions

2.2V~5.5V 400

3.3V~5.5V 400

2.2V~5.5V 400

3.3V~5.5V 400

2.2V~5.5V 0

3.3V~5.5V 0

Without WDT prescaler

¾¾

Wake-up from HALT

¾¾

Min. Typ. Max. Unit

45 90 180

32 65 130

11 23 46 ms

0.3V

0.4V

4000 kHz

8000 kHz

4000 kHz

8000 kHz

4000 kHz

8000 kHz

1024

¾¾ms

1024

¾¾ms

Ta=25°C

SYS

Rev. 1.00 4 January 9, 2007

Functional Description

Execution Flow

The HT48F06E system clock is derived from either a crystal or an RC oscillator and is internally divided into four non-overlapping clocks. One instruction cycle con sists of four system clock cycles.

Instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while de coding and execution takes the next instruction cycle. This pipelining scheme ensures that instructions are ef fectively executed in one cycle. If an instruction changes the contents of the program counter, such as subroutine calls or jumps, in which case, two cycles are required to complete the instruction.

Program Counter - PC

The program counter (PC) controls the sequence in which the instructions stored in the program ROM are executed and its contents specify a full range of pro gram memory.

After accessing a program memory word to fetch an in struction code, the contents of the program counter are

HT48F06E

incremented byone. Theprogram counter then points to the memory word containing the next instruction code.

When executing a jump instruction, conditional skip ex

ecution, loading into the PCL register, subroutine call or return from subroutine, initial reset, internal interrupt, external interrupt or return from interrupt, the PC man ages the program transfer by loading the address corre

sponding to each instruction.

The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise proceed with the next instruction.

The lower byte of the program counter (PCL) is a read able and writeable register (06H). Moving data into the PCL performs a short jump. The destination will be within the 256 locations.

When a control transfer takes place, an additional

dummy cycle is required.

S y s t e m C l o c k

O S C 2 ( R C o n l y )

T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4

P C

P C P C + 1 P C + 2

F e t c h I N S T ( P C )

E x e c u t e I N S T ( P C - 1 )

F e t c h I N S T ( P C + 1 )

E x e c u t e I N S T ( P C )

F e t c h I N S T ( P C + 2 )

E x e c u t e I N S T ( P C + 1 )

Execution Flow

Mode

*9 *8 *7 *6 *5 *4 *3 *2 *1 *0

Program Counter

Initial Reset 0000000000

External Interrupt 0000000100

Timer/Event Counter Overflow 0000001000

Skip Program Counter+2

Loading PCL *9 *8 @7 @6 @5 @4 @3 @2 @1 @0

Jump, Call Branch #9 #8 #7 #6 #5 #4 #3 #2 #1 #0

Return from Subroutine S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

Program Counter

Note: *9~*0: Program counter bits S9~S0: Stack register bits

#9~#0: Instruction code bits @7~@0: PCL bits

Rev. 1.00 5 January 9, 2007

In System Programming

In system programming allows programming and repro gramming of HT48FXXE microcontroller on application circuit board, this will save time and money, both during development in the lab. Using a simple 3-wire interface, the ISP communicates serially with the HT48FXXE microcontroller, reprogramming program memory and EEPROM data memory on the chip.

Pin Name Function Description

PA0 SDATA Serial data input/output

PA4 SCLK Serial clock input

RES RESET Device reset

VDD VDD Power supply

VSS VSS Ground

ISP Pin Assignments

Program Memory - ROM

The program memory is used to store the program in structions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 1024´14 bits,addressed by the program counter and ta ble pointer.

Certain locations in the program memory are reserved for special usage:

0 0 0 H

0 0 4 H

0 0 8 H

n 0 0 H

n F F H

3 0 0 H

3 F F H

D e v i c e I n i t i a l i z a t i o n P r o g r a m

E x t e r n a l I n t e r r u p t S u b r o u t i n e

T i m e r / E v e n t C o u n t e r

I n t e r r u p t S u b r o u t i n e

L o o k - u p T a b l e ( 2 5 6 w o r d s )

1 4 b i t s

N o t e : n r a n g e s f r o m 0 t o 3

P r o g r a m M e m o r y

Program Memory

HT48F06E

Location 000H

This area is reserved for program initialization. After a chip reset, the program always begins execution at lo cation 000H.

Location 004H This area is reserved for the external interrupt service program. If the INT

input pin is activated, the interrupt is enabled and the stack is not full, the program begins execution at location 004H.

Location 008H This area is reserved for the timer/event counter inter rupt service program. If a timer interrupt results from a timer/event counter overflow, and if the interrupt is en abled and the stack is not full, the program begins exe cution at location 008H.

Table location Any location in the program memory space can be used as look-up tables. The instructions ²TABRDC [m]² (the current page, one page=256 words) and ²TABRDL [m]² (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are trans ferred to the lower portion of TBLH, any unused bits will have uncertain values. The Table Higher-order byte register (TBLH) is read only. The table pointer (TBLP) is a read/write register (07H), which indicates the table location. Before accessing the table, the location must be placed in the TBLP. The TBLH is read only and cannot be restored. If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR. Errors can occur. In other words, using the table read instruction in the main rou tine and the ISR simultaneously should be avoided. However, if the table read instruction has to be applied in both the main routine and the ISR, the interrupt is supposed to be disabled prior to the table read in struction. It will not be enabled until the TBLH has been backed up. All table related instructions require two cycles to complete the operation. These areas may function as normal program memory depending on the requirements.

Instruction

*9 *8 *7 *6 *5 *4 *3 *2 *1 *0

Table Location

TABRDC [m] P9 P8 @7 @6 @5 @4 @3 @2 @1 @0

TABRDL [m] 1 1 @7 @6 @5 @4 @3 @2 @1 @0

Table Location

Note: *9~*0: Table location bits P9~P8: Current program counter bits

@7~@0: Table pointer bits

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HT48F06E

Stack Register - STACK

This is a special part of the memory which is used to save the contents of the Program Counter only. The stack is organized into 2 levels and is neither part of the data nor part of the program space, and is neither read able nor writeable. The activated level is indexed by the stack pointer (SP) and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the pro gram counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack.

If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the stack pointer is decremented (by RET or RETI), the interrupt will be serviced. This feature prevents stack overflow al lowing the programmer to use the structure more easily.

In a similar case, if the stack is full and a ²CALL² is sub sequently executed, stack overflow occurs and the first entry will be lost (only the most recent 2 return ad dresses are stored).

Data Memory - RAM

The data memory has a capacity of 81´8 bits and is divided into two functional groups: special function regis-

ters and general purpose data memory (64´ 8). Most are read/write, but some are read only.

The unused space before 40H is reserved for future expanded usage and reading these locations will return

the result ²00H². The general purpose data memory, addressed from 40H to 7FH, is used for data and control information under instruction commands. All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be

set and reset by ²SET [m].i² and ²CLR [m].i². They are also indirectly accessible through memory pointer regis ters (MP). The control register of the EEPROM data memory is located at [40H] in Bank 1.

I n d i r e c t A d d r e s s i n g R e g i s t e r 0

0 0 H

0 1 H

I n d i r e c t A d d r e s s i n g R e g i s t e r 1

0 2 H

0 3 H

0 4 H

0 5 H

0 6 H

0 7 H

0 8 H

0 9 H

0 A H

0 B H

0 C H

0 D H

0 E H

0 F H

1 0 H

1 1 H

1 2 H

1 3 H

1 4 H

1 5 H

1 6 H

1 7 H

1 8 H

3 F H

4 0 H

7 F H

M P 0

M P 1

B P

A C C

P C L

T B L P

T B L H

W D T S

S T A T U S

I N T C

T M R

T M R C

P A

P A C

P B

P B C

P C

P C C

G e n e r a l P u r p o s e

D a t a M e m o r y

( 6 4 B y t e s )

B a n k 0 B a n k 1

S p e c i a l P u r p o s e D a t a M e m o r y

R e a d a s " 0 0 "

4 0 H

: U n u s e d

RAM Mapping

The memory pointer registers, MP0 and MP1, are both 7-bit registers used to access the RAM by combining corresponding indirect addressing registers. MP0.7 and MP1.7 are always ²1². MP0 can only be applied to data memory in Bank 0, while MP1 can be applied to data memory in Bank 0 and Bank 1.

Accumulator

The accumulator is closely related to ALU operations. It is also mapped to location 05H of the data memory and can carry out immediate data operations. The data

movement between two data memory locations must

pass through the accumulator.

E E C R

Indirect Addressing Register

Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write op eration on [00H] and [02H] access the RAM pointed to by MP0 (01H) and MP1 (03H), respectively. Reading lo cation 00H or 02H indirectly returns the result 00H. Writ ing indirectly results in no operation. The function of data movement between two indirect addressing regis ters is not supported.

Arithmetic and logic unit - ALU

This circuit performs 8-bit arithmetic and logic opera tions. The ALU provides the following functions:

Arithmetic operations (ADD, ADC, SUB, SBC, DAA)

Logic operations (AND, OR, XOR, CPL)

Rotation (RL, RR, RLC, RRC)

Increment and Decrement (INC, DEC)

Branch decision (SZ, SNZ, SIZ, SDZ...)

The ALU not only saves the results of a data operation but also changes the status register.

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HT48F06E

Status Register - STATUS

This 8-bit register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). It also records the status information and controls the operation sequence.

With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addi tion, operations related to the status register may give different results from those intended. The TO flag can be affected only by a system power-up, a WDT time-out or executing the ²CLR WDT² or ²HALT² instruction. The PDF flag can be affected only by executing the ²HALT² or ²CLR WDT² instruc tion or during a system power-up.

The Z, OV, AC and C flags generally reflect the status of the latest operations.

In addition, on entering the interrupt sequence or exe cuting the subroutine call, the status register will not be automatically pushed onto the stack. If the contents of the status are important and if the subroutine may cor rupt the status register, precautions must be taken to save it properly.

Interrupt

The device provides an external interrupt and internal timer/event counter interrupts. The Interrupt Control Register (INTC;0BH) contains the interrupt control bits to set the enable or disable and the interrupt request flags.

Once an interrupt subroutine is serviced, all the other in terrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may occur during this interval but only the interrupt request flag is recorded. If a certain inter rupt requires servicing within the service routine, the EMI bit and the corresponding bit of the INTC may be set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related in terrupt is enabled, until the Stack Pointer is decremented.

If immediate service is desired, the stack must be pre

vented from becoming full.

All these kinds of interrupts have a wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at specified location in the pro

gram memory. Only the program counter is pushed onto

the stack. If the contents of the register or status register (STATUS) are altered by the interrupt service program which corrupts the desired control sequence, the con tents should be saved in advance.

External interrupts are triggered by a high to low transi tion ofthe INT

bit 4 of the INTC) will be set. When the interrupt is en abled, the stack is not full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag (EIF) and EMI bits will be cleared to disable other interrupts.

The internal timer/event counter interrupt is initialized by setting the timer/event counter interrupt request flag (TF; bit 5 of the INTC), caused by a timer overflow. When the interrupt is enabled, the stack is not full and the TF bit is set, a subroutine call to location 08H will occur. The related interrupt request flag (TF) will be reset and the EMI bit cleared to disable further interrupts.

and therelated interruptrequest flag(EIF;

Bit No. Label Function

1AC

2 Z Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.

3OV

4 PDF

5TO

6~7

Rev. 1.00 8 January 9, 2007

C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction.

AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared.

OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared.

PDF is cleared by a system power-up or executing the ²CLR WDT² instruction. PDF is set by executing the ²HALT² instruction.

TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is set by a WDT time-out.

¾ Unused bit, read as ²0²

Status (0AH) Register

Bit No. Label Function

0 EMI Controls the master (global) interrupt (1= enable; 0= disable)

1 EEI Controls the external interrupt (1= enable; 0= disable)

2 ETI Controls the Timer/Event Counter 0 interrupt (1= enable; 0= disable)

3, 6~7

¾ Unused bit, read as ²0²

4 EIF External interrupt request flag (1= active; 0= inactive)

5 TF Internal Timer/Event Counter 0 request flag (1= active; 0= inactive)

INTC (0BH)Register

HT48F06E

During the execution of an interrupt subroutine, other in terrupt acknowledge signals are held until the ²RETI² in struction is executed or the EMI bit and the related interrupt control bit are set to 1 (if the stack is not full). To return from the interrupt subroutine, ²RET² or ²RETI² may be invoked. RETI will set the EMI bit to enable an in terrupt service, but RET will not.

Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding inter rupts are enabled. In the case of simultaneous requests the following table shows the priority that is applied. These can be masked by resetting the EMI bit.

Interrupt Source Priority Vector

External Interrupt 1 04H

Timer/Event Counter Overflow 2 08H

Once the interrupt request flags (TF, EIF) are set, they will remain in the INTC register until the interrupts are serviced or cleared by a software instruction. It is recommended that a program does not use the ²CALL subroutine² within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced imme diately in some applications. If only one stack is left and enabling the interrupt is not well controlled, the original control sequence will be damaged once the ²CALL² op erates in the interrupt subroutine.

Oscillator Configuration

There are 2 oscillator circuits in the microcontroller.

D D

All of them are designed for system clocks, namely, ex

ternal RC oscillator and external Crystal oscillator,

which are determined by options. No matter what oscil lator type is selected, the signal provides the system clock. The HALT mode stops the system oscillator and ignores an external signal to conserve power.

If an RC oscillator is used, an external resistor between OSC1 and VDD is required and the resistance must range from 24kW to 1MW. The system clock, divided by 4, is available on OSC2, which can be used to synchro

nize external logic. The RC oscillator provides the most cost effective solution. However, the frequency of oscil lation may vary with VDD, temperatures and the chip itself due to process variations. It is, therefore, not suitable for timing sensitive operations where an accurate oscillator frequency is desired.

If a Crystal oscillator is used, a crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator. No other external components are required. In stead of a crystal, a resonator can also be connected between OSC1 and OSC2 to obtain a frequency reference, but two external capacitors in

OSC1 and OSC2 are required.

The tor, and no external components are required. Even if

the system enters the power down mode and the sys

oscillator is a free running on-chip RC oscilla

WDT

tem clock is stopped, the oscillator still works within a period of 65ms at 5V. The WDT oscillator can be dis abled by options to conserve power.

O S C 1

O S C 2

C r y s t a l O s c i l l a t o r R C O s c i l l a t o r

4 7 0 p F

/ 4

S Y S

N M O S O p e n D r a i n

O S C 1

O S C 2

System Oscillator

Rev. 1.00 9 January 9, 2007

HT48F06E

Watchdog Timer - WDT

The WDT clock source is implemented by a dedicated RC oscillator (WDT oscillator), instruction clock (system clock divided by 4), determines the options. This timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. The Watchdog Timer can be disabled by op tions. If the Watchdog Timer is disabled, all the execu tions related to the WDT result in no operation.

Once the internal WDT oscillator (RC oscillator with a period of 65ms at 5V normally) is selected, it is first di vided by 256 (8-stage) to get the nominal time-out pe riod of 16.6ms at 5V. This time-out period may vary with temperatures, VDD and process variations. By invoking the WDT prescaler, longer time-out periods can be real ized. Writing data to WS2, WS1, WS0 (bit 2, 1, 0 of the WDTS) can give different time-out periods. If WS2, WS1, and WS0 are all equal to 1, the division ratio is up to 1:128, and the maximum time-out period is 2.2s at 5V. If the WDT oscillator is disabled, the WDT clock may still come from the instruction clock and operates in the same manner ex cept that in the HALT state the WDT may stop counting and lose its protecting purpose. In this situation the logic can only be restarted by an external logic. The high nibble and bit 3 of the WDTS are reserved for user¢s defined flags, which can be used to indicate some specified status.

If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock.

WS2 WS1 WS0 Division Ratio

000 1:1

001 1:2

010 1:4

011 1:8

1 0 0 1:16

1 0 1 1:32

1 1 0 1:64

1 1 1 1:128

WDTS (09H) Register

The WDT overflow under normal operation will initialize a ²chip reset² and set the status bit ²TO². But in the HALT mode, the overflow will initialize a ²warm reset² and only the Program Counter and SP are reset to zero. To clear the contents of WDT (including the WDT prescaler), three methods are adopted; external reset (a

low level to RES

struction. The software instruction includes ²CLR WDT²

), software instruction and a ²HALT² in

and the other set -²CLR WDT1² and ²CLR WDT2².Of these twotypes ofinstruction, onlyone can be active de pending on the option -²CLR WDT times selection op

tion².Ifthe²CLR WDT² is selected (i.e. CLRWDT times

is equal to one), any execution of the ²CLR WDT² in

struction will clear the WDT. In the case that ²CLR

WDT1² and ²CLR WDT2² are chosen (i.e. CLRWDT times is equal to two), these two instructions must be ex ecuted to clear the WDT; otherwise, the WDT may reset the chip as a result of time-out.

Power Down Operation - HALT

The HALT mode is initialized by the ²HALT² instruction

and results in the following:

The system oscillator will be turned off but the WDT oscillator remains running (if the WDT oscillator is se lected).

The contents of the on chip RAM and registers remain unchanged.

WDT and WDT prescaler will be cleared and recounted again (if the WDT clock is from the WDT oscillator).

All of the I/O ports maintain their original status.

The PDF flag is set and the TO flag is cleared.

The system can leave the HALT mode by means of an external reset, an interrupt, an external falling edge sig nal on port A or a WDT overflow. An external reset causes a device initialization and the WDT overflow per forms a ²warm reset². After the TO and PDF flags are examined, the cause for chip reset can be determined. The PDF flag is cleared by a system power-up or exe cuting the ²CLR WDT² instruction and is set when exe cuting the ²HALT² instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and SP; the others remain in their original status.

S y s t e m C l o c k / 4

W D T

O S C

O p t i o n S e l e c t

8 - b i t C o u n t e r

W D T P r e s c a l e r

7 - b i t C o u n t e r

8 - t o - 1 M U X

W D T T i m e - o u t

W S 0 ~ W S 2

Watchdog Timer

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HT48F06E

The port A wake-up and interrupt methods can be con sidered as a continuation of normal execution. Each bit in port A can be independently selected to wake-up the device by options. Awakening from an I/O port stimulus, the program will resume execution of the next instruc tion. If it awakens from an interrupt, two sequence may occur. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. If the interrupt is en abled and the stack is not full, a regular interrupt re sponse takes place. If an interrupt request flag is set to ²1² before entering the HALT mode, the wake-up func tion of the related interrupt will be disabled. Once a wake-up event occurs, it takes 1024 (system clock pe riod) to resume to normal operation. In other words, a dummy period will be inserted after a wake-up. If the wake-up results from an interrupt acknowledge signal, the actual interrupt subroutine execution will be delayed by one or more cycles. If the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished.

To minimize power consumption, all the I/O pins should be carefully managed before entering the HALT status.

Reset

There are three ways in which areset can occur:

RES reset during normal operation

RES reset during HALT

WDT time-out reset during normal operation

The time-out during HALT is different from other chip reset conditions, since it can perform a ²warm reset² that resets only the Program Counter and SP, leaving the other circuits in their original state. Some registers remain unchanged during other reset conditions. Most registers are reset to the ²initial condition² when the re set conditions are met. By examining the PDF and TO flags, the program can distinguish between different ²chip resets².

TO PDF RESET Conditions

0 0 RES

u u RES

0 1 RES

reset during power-up

reset during normal operation

wake-up HALT

1 u WDT time-out during normal operation

1 1 WDT wake-up HALT

Note: ²u² stands for unchanged”

To guarantee that the system oscillator is started and stabilized, the SST (System Start-up Timer) provides an extra delay of 1024 system clock pulses when the sys tem reset (power-up, WDT time-out or RES

reset) or the

system awakes from the HALT state.

When a system reset occurs, the SST delay is added

during the reset period. Any wake-up from HALT will en able an SST delay.

An extra option load time delay is added during system

reset (power-up, WDT time-out at normal mode or RES

reset).

The functional unit chip reset status are shown below.

Program Counter 000H

Interrupt Disable

Prescaler Clear

WDT

Clear. After master reset, WDT begins counting

Timer/Event Counter Off

Input/Output Ports Input mode

Stack Pointer Points to the top of the stack

V D D

R E S

S S T T i m e - o u t

C h i p R e s e t

S S T

Reset Timing Chart

D D

0 . 0 1mF *

1 0 0 k

R E S

1 0 k

0 . 1mF *

Reset Circuit

Note:

²*² Make the length of the wiring, which is con nected to the RES

pin as short as possible, to

avoid noise interference.

H A L T

W D T

R E S

O S C 1

S S T

1 0 - b i t R i p p l e

C o u n t e r

S y s t e m R e s e t

W a r m R e s e t

C o l d R e s e t

Reset Configuration

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HT48F06E

The registers status is summarized in the following table.

Reset

(Power-on)

WDT Time-out

(Normal Operation)

RES

Reset

MP0 -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu

MP1 -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu

BP 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu

ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

Program Counter

000H 000H 000H 000H 000H

TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

TBLH xxxx xxxx xxuu uuuu xxuu uuuu xxuu uuuu xxuu uuuu

WDTS 0000 0111 0000 0111 0000 0111 0000 0111 uuuu uuuu

STATUS --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu

INTC --00 -000 --00 -000 --00 -000 --00 -000 --uu -uuu

TMR xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

TMRC 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu

PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu

PAC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu

PB ---- -111 ---- -111 ---- -111 ---- -111 ---- -uuu

PBC ---- -111 ---- -111 ---- -111 ---- -111 ---- -uuu

PC ---- --11 ---- --11 ---- --11 ---- --11 ---- --uu

PCC ---- --11 ---- --11 ---- --11 ---- --11 ---- --uu

EECR 1000 ---- 1000 ---- 1000 ---- 1000 ---- uuuu ----

RES Reset

(HALT)

WDT Time-out

(HALT)*

Note:

²*² stands for ²warm reset² ²u² stands for ²unchanged² ²x² stands for ²unknown²

Timer/Event Counter

A timer/event counter (TMR) is implemented in the microcontroller. The timer/event counter contains an 8-bit programmable count-up counter and the clock may come froman externalsource or from the system clock.

Using an external clock input allows the user to count external events, measure time internals or pulse widths, or generate an accurate time base. Using the internal clock allowsthe user to generate an accurate time base.

The timer/event counter can generate PFD signals by using external or internal clock and the PFD frequency

is determine by the equation f

/[2´(256-N)].

INT

There are two registers related to the timer/event coun ter; TMR ([0DH]), TMRC ([0EH]). Two physical registers are mapped to TMR location; writing to TMR makes the starting value be placed in the timer/event counter preload register and reading TMR retrieves the contents of the timer/event counter. The TMRC is a timer/event counter control register, which defines some options.

The TM0, TM1 bits define the operating mode. The event count mode is used to count external events, which means that the clock source comes from an exter

nal (TMR) pin. The timer mode functions as a normal timer with the clock source coming from the f The pulse width measurement mode can be used to count the high or low level duration of the external signal (TMR). The counting is based on the f

INT

clock.

In the event count or timer mode, once the timer/event counter starts counting, it will count from the current contents in the timer/event counter to FFH. Once over flow occurs, the counter is reloaded from the timer/event counter preload register and generates the interrupt re quest flag (TF; bit 5 of the INTC) at the same time.

In the pulse width measurement mode with the TON and TE bits equal to one, once the TMR has received a tran

sient from low to high (or high to low if the TE bit is ²0²)it

will start counting until the TMR returns to the original level and resets the TON. The measured result will re main in the timer/event counter even if the activated transient occurs again. In other words, only one cycle measurement can be done. Until setting the TON, the cycle measurement will function again as long as it re ceives further transient pulse. Note that, in this operat ing mode, the timer/event counter starts counting not

according to the logic level but according to the transient

INT

clock.

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HT48F06E

edges. In the case of counter overflows, the counter is reloaded from the timer/event counter preload register and issues the interrupt request just like the other two modes. To enable the counting operation, the timer ON bit (TON; bit 4 of the TMRC) should be set to ²1². In the pulse width measurement mode, the TON will be cleared automatically after the measurement cycle is completed. Butin the other two modes the TON canonly be reset by instructions. The overflow of the timer/event counter is one of the wake-up sources. No matter what the operation mode is, writing a ²0² to ETI can disable the corresponding interrupt services.

In the case of timer/event counter OFF condition, writing

reload that data to the timer/event counter. But if the timer/event counter is turned on, data written to it will only be kept in the timer/event counter preload register. The timer/event counter will still operate until overflow occurs. When the timer/event counter (reading TMR) is read, the clock will be blocked to avoid errors. As clock blocking may result in a counting error, this must be taken into consideration by the programmer.

Bit0~bit2 of the TMRC can be used to define the pre-scaling stages of the internal clock sources of the timer/event counter. The definitions are as shown. The overflow signal of the timer/event counter can be used to generate PFD signals for buzzer driving.

data to the timer/event counter preload register will also

Bit No. Label Function

Defines the prescaler stages, PSC2, PSC1, PSC0=

0~2 PSC0~PSC2

000: f 001: f 010: f 011: f 100: f 101: f 110: f 111: f

INT=fSYS

/2 /4 /8 /16 /32 /64 /128 /256

Defines the TMR active edge of the timer/event counter: In Event Counter Mode (TM1,TM0)=(0,1): 1:count on falling edge;

3TE

0:count on rising edge In Pulse Width measurement mode (TM1,TM0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge

4 TON

¾ Unused bit, read as ²0²

Enable or disable timer 0 counting (0=disable; 1=enable)

Defines the operating mode

6 7

TM0 TM1

01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused

TMRC (0EH) Register

( 1 / 2 ~ 1 / 2 5 6 )

S Y S

8 - s t a g e P r e s c a l e r

8 - 1 M U X

P S C 2 ~ P S C 0

T M R

T M 1 T M 0

T O N

I N T

T M 1 T M 0

T E

P u l s e W i d t h

M e a s u r e m e n t

M o d e C o n t r o l

T i m e r / E v e n t C o u n t e r

P r e l o a d R e g i s t e r

T i m e r / E v e n t

C o u n t e r

D a t a B u s

R e l o a d

1 / 2

O v e r f l o w t o I n t e r r u p t

B Z

Timer/Event Counter

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+ 29 hidden pages

HOLTEK HT48F06E User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Technical Document

Features

General Description

Block Diagram

Pin Assignment

Pin Description

Absolute Maximum Ratings

D.C. Characteristics

A.C. Characteristics

Functional Description