Holtek HT46R46, HT46C48A, HT46C46, HT46R49, HT46C47 User Manual

...

HT46R46/C46/R47/C47/R48A/C48A/R49

Cost-Effective A/D Type 8-Bit MCU

Rev. 1.41 1 December 30, 2008

General Description

The Cost-Effective A/D Type MCU Devices are a series of 8-bit high performance RISC architecture microcontrollers, designed especially for applications that interface directly to analog signals, such as those from sensors. All devices include an integrated multi-channel Analog to Digital Converter in addition to one or two Pulse Width Modulation outputs. The usual Holtek MCU features such as power down and wake-up functions, oscillator options, programmable frequency divider, etc. combineto ensure user applications require a minimum of external components.

The benefits of integrated A/D and PWM functions, in addition to low power consumption, high performance, I/O flexibility and low-cost, provide these devices with the versatility to suit a wide range of application possibilities such as sensor signal processing, motor driving, industrial control, consumer products, subsystem controllers, etc. Many features are common to all devices, however, they differ in areas such as I/O pin count, Program Memory capacity, A/D resolution, stack capacity and package types.

Features

Operating voltage: f

SYS

=4MHz: 2.2V~5.5V

SYS

=8MHz: 3.3V~5.5V

13 to 23 bidirectional I/O lines

External interrupt input shared with an I/O line

8-bit programmable Timer/Event Counter with overflow interrupt and 7-stage prescaler

On-chip crystal and RC oscillator

Watchdog Timer function

PFD for audio frequency generation

Power down and wake-up functions to reduce power consumption

Up to 0.5ms instruction cycle with 8MHz system clock at V

=5V

4 or 6-level subroutine nesting

4 channels 8 or 9-bit resolution A/D converter

1 or2 channel 8-bit PWM output shared with I/O lines

Bit manipulation instruction

Table read instructions

63 powerful instructions

All instructions executed in one or two machine cycles

Low voltage reset function

Range of packaging types

Part No. VDD

Program

Memory

Data

Memory

I/O Timer Int. A/D PWM Stack Package Types

HT46R46 HT46C46

2.2V~

5.5V

1K´14 64´8

8-bit´1

8-bit´4 8-bit´1

16NSOP, 18DIP/SOP,

20SSOP

HT46R47 HT46C47

2.2V~

5.5V

2K´14 64´8

8-bit´1

9-bit´4 8-bit´1

16NSOP, 18DIP/SOP,

20SSOP

HT46R48A HT46C48A

2.2V~

5.5V

2K´14 88´8

8-bit´1

9-bit´4 8-bit´1

20DIP/SOP,

24SKDIP/SOP/SSOP

HT46R49

2.2V~

5.5V

4K´15 128´8

8-bit´1

9-bit´4 8-bit´2

20DIP/SOP,

24/28SKDIP/SOP

Note:

Part numbers including ²C² are mask version devices, ²R² are OTP devices.

For devices that exist in two package formats, the table reflects the situation for the larger package.

Block Diagram

Note: This block diagram represents the OTP devices, for the mask devices there is no Device Programming

Circuitry.

HT46R46/C46/R47/C47/R48A/C48A/R49

Rev. 1.41 2 December 30, 2008

T i m i n g

G e n e r a t o r

S y s t e m R C /

X ' t a l O s c i l l a t o r

I n s t r u c t i o n

D e c o d e r

I n s t r u c t i o n

R e g i s t e r

W D T

O s c i ll a t o r

D a t a

M e m o r y

A d d r e s s D e c o d e r

M e m o r y

P o i n t e r

M U X

A C C

L o o k - u p

T a b l e

R e g i s t e r

R e s e t &

L V R

C o n f i g .

R e g i s t e r

T i m e r /

C o u n t e r

C o n f i g .

R e g i s t e r

I n t e r r u p t

C i r c u i t

C o n f i g .

R e g i s t e r

I / O

P o r t s

D e v i c e

P r o g r a m m i n g

C i r c u i t r y

C o n f i g u r a t i o n

O p t i o n

P r o g r a m M e m o r y

A d d r e s s D e c o d e r

S t a c k

S t a c k P o i n t e r

P r o g r a m

C o u n t e r

L o o k - u p

T a b l e

P o i n t e r

T o P r o g r a m

M e m o r y

A L U

S h i f t e r

M U X

C o n f i g .

R e g i s t e r

P W M

P F D

A / D

C o n v e r t e r

Device Types

Devices which have the letter ²R² within their part number, indicate that they are OTP devices offering the advantages of easy and effective program updates, using the Holtek range of development and programming tools. These devices provide the designer with the means for fast and low-cost product development cycles. Devices which have the letter

²C² within their part number indicate that they are mask version devices. These devices offer a complementary device for applications that are at a mature state in their design process and have high volume and low cost demands.

Fully pin and functionally compatible with their OTP sister devices, the mask version devices provide the ideal substi

tute for products which have gone beyond their development cycle and are facing cost-down demands.

In this datasheet, for convenience, when describing device functions, only the OTP types are mentioned by name, however the same described functions also apply to the Mask type devices.

Selection Table

Most features are common to all devices, the main feature distinguishing them are Program Memory capacity, I/O count, A/Dresolution, stack capacityand package types.The following table summarises the main features of each de

vice.

Pin Assignment

Pin Description

HT46R46, HT46R47

Pin Name I/O

Configuration

Option

Description

PA0~PA2 PA3/PFD PA4/TMR PA5/INT PA6~PA7

I/O

Pull-high Wake-up

PA3 or

PFD

Bidirectional 8-bit input/output port. Each individual pin on this port can be configured as a wake-up input by a configuration option. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine which pins on the port have pull-high resistors. Pins PA3, PA4 and PA5 are pin-shared with PFD, TMR and INT

, respectively.

PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3

I/O Pull-high

Bidirectional 4-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine which pins on the port have pull-high resistors. PB is pin-shared with the A/D input pins. The A/D inputs are selected via software instructions. Once selected as an A/D input, the I/O function and pull-high resistor options are disabled automatically.

PD0/PWM I/O

Pull-high

PD0 or

PWM

Bidirectional 1-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. A configuration option determines if this pin has a pull-high resistor. The PWM out

put is pin-shared with pin PD0 selected via a configuration option.

OSC1 OSC2

Crystal

or RC

OSC1, OSC2 are connected to an external RC network or external crystal, deter

mined by configuration option, for the internalsystem clock. If the RC system clock op

tion is selected, pin OSC2 can beused to measure the system clock at 1/4frequency.

RES I

Schmitt Trigger reset input. Active low.

VDD

¾¾

Positive power supply

VSS

¾¾

Negative power supply, ground

Note: 1. Each pin on PA can be programmed through a configuration option to have a wake-up function.

2. Individual pins can be selected to have a pull-high resistor.

3. Pins PB2/AN2~PB3/AN3 exist but are not bonded out on the 16-pin package.

4. unbonded pins should be setup as outputs or as inputs with pull-high resistors to conserve power.

HT46R46/C46/R47/C47/R48A/C48A/R49

Rev. 1.41 3 December 30, 2008

H T 4 6 R 4 6 / H T 4 6 C 4 6 H T 4 6 R 4 7 / H T 4 6 C 4 7

2 0 S S O P - A

P A 4 / T M R

P A 5 / I N T

P A 6

P A 7

O S C 2

O S C 1

V D D

R E S

P D 0 / P W M

N C

2 0

1 9

1 8

1 7

1 6

1 5

1 4

1 3

1 2

1 1

1 0

P A 3 / P F D

P A 2

P A 1

P A 0

P B 3 / A N 3

N C

P B 2 / A N 2

P B 1 / A N 1

P B 0 / A N 0

V S S

H T 4 6 R 4 6 / H T 4 6 C 4 6 H T 4 6 R 4 7 / H T 4 6 C 4 7

1 8 D I P - A / S O P - A

P A 4 / T M R

P A 5 / I N T

P A 6

P A 7 O S C 2

O S C 1

V D D

R E S

P D 0 / P W M

P A 3 / P F D

P A 2

P A 1

P A 0 P B 3 / A N 3

P B 2 / A N 2

P B 1 / A N 1

P B 0 / A N 0

V S S

1 8

1 7

1 6

1 5

1 4

1 3

1 2

1 1

1 0

H T 4 6 R 4 8 A / H T 4 6 C 4 8 A

2 0 D I P - A / S O P - A

P B 5

P A 4 / T M R

P A 5 / I N T

P A 6

P A 7

O S C 2

O S C 1

V D D

R E S

P D 0 / P W M

2 0

1 9

1 8

1 7

1 6

1 5

1 4

1 3

1 2

1 1

1 0

P B 4

P A 3 / P F D

P A 2

P A 1

P A 0

P B 3 / A N 3

P B 2 / A N 2

P B 1 / A N 1

P B 0 / A N 0

V S S

H T 4 6 R 4 8 A / H T 4 6 C 4 8 A

2 4 S K D I P - A / S O P - A / S S O P - A

P B 5

P B 4

P A 3 / P F D

P A 2

P A 1

P A 0

P B 3 / A N 3

P B 2 / A N 2

P B 1 / A N 1

P B 0 / A N 0

V S S

P C 0

P B 6

P B

P A 4 / T M R

P A 5 / I N T

P A 6

P A 7

O S C 2

O S C 1

V D D

R E S

P D 0 / P W M

P C 1

2 4

2 3

2 2

2 1

2 0

1 9

1 8

1 7

1 6

1 5

1 4

1 3

1 0

1 1

1 2

H T 4 6 R 4 9

2 8 S K D I P - A / S O P - A

P B 6

P B 7

P A 4 / T M R

P A 5 / I N T

P A 6

P A 7

O S C 2

O S C 1

V D D

R E S

P D 1 / P W M 1

P D 0 / P W M 0

P C 4

P C 3

2 8

2 7

2 6

2 5

2 4

2 3

2 2

2 1

2 0

1 9

1 8

1 7

1 6

1 5

1 0

1 1

1 2

1 3

1 4

P B 5

P B 4

P A 3 / P F D

P A 2

P A 1

P A 0

P B 3 / A N 3

P B 2 / A N 2

P B 1 / A N 1

P B 0 / A N 0

V S S

P C 0

P C 1

C 2

P B 5

P B 4

P A 3 / P F D

P A 2

P A 1

P A 0

P B 3 / A N 3

P B 2 / A N 2

P B 1 / A N 1

P B 0 / A N 0

V S S

P C 0

P B 6

P B 7

P A 4 / T M R

P A 5 / I N T

P A 6

P A 7

O S C 2

O S C 1

V D D

R E S

P D 1 / P

W M 1

P D 0 / P W M 0

2 4

2 3

2 2

2 1

2 0

1 9

1 8

1 7

1 6

1 5

1 4

1 3

1 0

1 1

1 2

H T 4 6 R 4 9

2 4 S K D I P - B / S O P - B

H T 4 6 R 4 6 / H T 4 6 C 4 6 H T 4 6 R 4 7 / H T 4 6 C 4 7

1 6 N S O P - A

P A 4 / T M R

P A 5 / I N T

P A 6

P A 7 O S C 2

O S C 1

V D D

R E S

P A 3 / P F D

P A 2

P A 1

P A 0

P B 1 / A N 1

P B 0 / A N 0

V S S

1 6

1 5

1 4

1 3

1 2

1 1

1 0

P D 0 / P W M

H T 4 6 R 4 9

2 0 D I P - A / S O P - A

P A 4 / T M R

P A 5 / I N T

P A 6

P A 7

O S C 2

O S C 1

V D D

R E S

P D 1 / P W M 1

P D 0 / P W M 0

2 0

1 9

1 8

1 7

1 6

1 5

1 4

1 3

1 2

1 1

1 0

P A 3 / P F D

P A 2

P A 1

P A 0

P B 3 / A N 3

P B 2 / A N 2

P B 1 / A N 1

P B 0 / A N 0

V S S

P C 0

HT46R48A

Pin Name I/O

Configuration

Option

Description

PA0~PA2 PA3/PFD PA4/TMR PA5/INT PA6~PA7

I/O

Pull-high

Wake-up

PA3 or PFD

Bidirectional 8-bit input/output port. Each individual pin on this port can be config

ured as a wake-up input by a configuration option. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options deter

mine which pins on the port have pull-high resistors. Pins PA3, PA4 and PA5 are pin-shared with PFD, TMR and INT

, respectively.

PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4~PB7

I/O Pull-high

Bidirectional 8-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine which pins on the port have pull-high resistors. PB is pin-shared with the A/D input pins. The A/D inputs are selected via software instructions. Once selected as an A/D input, the I/O function and pull-high resistor options are disabled automatically.

PC0~PC1 I/O Pull-high

Bidirectional 2-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine which pins on the port have pull-high resistors.

PD0/PWM I/O

Pull-high

I/O or PWM

Bidirectional 1-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration option determines if this pin has a pull-high resistor. The PWM output is pin-shared with pin PD0 selected via a configuration option.

OSC1 OSC2

Crystal or RC

OSC1, OSC2 are connected to an external RC network or external crystal, deter

mined by configuration option, for the internal system clock. If the RC system clock option is selected, pin OSC2 can be used to measure the system clock at 1/4 fre

quency.

RES I

Schmitt Trigger reset input. Active low.

VDD

¾¾

Positive power supply

VSS

¾¾

Negative power supply, ground

Note: 1. Each pin on PA can be programmed through a configuration option to have a wake-up function.

2. Individual pins can be selected to have a pull-high resistor.

3. Pins PB4~PB7 exist but are not bonded out on the 20-pin package.

4. Unbonded pins should be setup as outputs or as inputs with pull-high resistors to conserve power.

HT46R46/C46/R47/C47/R48A/C48A/R49

Rev. 1.41 4 December 30, 2008

HT46R49

Pin Name I/O

Configuration

Option

Description

PA0~PA2 PA3/PFD PA4/TMR PA5/INT PA6~PA7

I/O

Pull-high Wake-up

PA3 or PFD

Bidirectional 8-bit input/output port. Each individual pin on this port can be config

ured as a wake-up input by a configuration option. Software instructions deter

mine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine which pins on the port have pull-high resistors. Pins PA3, PA4 and PA5 are pin-shared with PFD, TMR and INT

, respectively.

PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4~PB7

I/O Pull-high

put, the I/O function and pull-high resistor options are disabled automatically.

PC0~PC4 I/O Pull-high

Bidirectional 5-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine which pins on the port have pull-high resistors.

PD0/PWM0 PD1/PWM1

I/O

Pull-high

I/O or PWM

Bidirectional 2-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration option determines if this pin has a pull-high resistor. The PWM output are pin-shared with pins PD0 and PD1 selected via a configuration option.

OSC1 OSC2

Crystal or RC

OSC1, OSC2 are connected to an external RC network or external crystal, deter

mined by configuration option, for the internal system clock. If the RC system clock option is selected, pin OSC2 can be used to measure the system clock at 1/4 frequency.

RES I

Schmitt Trigger reset input. Active low.

VDD

¾¾

Positive power supply

VSS

¾¾

Negative power supply, ground

Note: 1. Each pin on PA can be programmed through a configuration option to have a wake-up function.

2. Individual pins can be selected to have a pull-high resistor.

3. Pins PC1~PC4 exist but are not bonded out on the 20-pin and 24-pin package. Pins PB4~PB7 exist but are not bonded out on the 20-pin package.

4. Unbonded pins should be setup as outputs or as inputs with pull-high resistors to conserve power.

Absolute Maximum Ratings

Supply Voltage...........................VSS-0.3V to VSS+6.0V

Storage Temperature ............................-50°Cto125°C

Input Voltage..............................V

-0.3V to VDD+0.3V

Operating Temperature...........................-40°Cto85°C

Total ..............................................................150mA

Total............................................................-100mA

Total Power Dissipation .....................................500mW

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may

cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.

HT46R46/C46/R47/C47/R48A/C48A/R49

Rev. 1.41 5 December 30, 2008

D.C. Characteristics

Ta=25°C

Symbol Parameter

Test Conditions

Min. Typ. Max. Unit

Conditions

Operating Voltage

SYS

=4MHz

2.2

5.5 V

SYS

=8MHz

3.3

5.5 V

DD1

Operating Current (Crystal OSC)

No load, f

SYS

=4MHz

ADC disable

0.6 1.5 mA

24mA

DD2

Operating Current (RC OSC)

No load, f

SYS

=4MHz

ADC disable

0.8 1.5 mA

2.5 4 mA

DD3

Operating Current (Crystal OSC, RC OSC)

No load, f

SYS

=8MHz

ADC disable

48mA

STB1

Standby Current (WDT Enabled)

No load, system HALT

¾¾

STB2

Standby Current (WDT Disabled)

No load, system HALT

¾¾

IL1

Input Low Voltage for I/O Ports, TMR and INT

¾¾

0.3V

IH1

Input High Voltage for I/O Ports, TMR and INT

¾¾

0.7V

IL2

Input Low Voltage (RES)

¾¾

0.4V

IH2

Input High Voltage (RES)

¾¾

0.9V

LVR

Low Voltage Reset

¾¾

2.7 3.0 3.3 V

I/O Port Sink Current

=0.1V

10 20

I/O Port Source Current

=0.9V

-2 -4 ¾

=0.9V

-5 -10 ¾

Pull-high Resistance

20 60 100

10 30 50

A/D Input Voltage

¾¾

A/D Conversion Error

¾¾ ¾±0.5 ±1

LSB

ADC

Additional Power Consumption if A/D Converter is Used

0.5 1 mA

1.5 3 mA

HT46R46/C46/R47/C47/R48A/C48A/R49

Rev. 1.41 6 December 30, 2008

A.C. Characteristics

Ta=25°C

Symbol Parameter

Test Conditions

Min. Typ. Max. Unit

Conditions

SYS

System Clock

2.2V~5.5V 400

4000 kHz

3.3V~5.5V 400

8000 kHz

TIMER

Timer I/P Frequency (TMR)

2.2V~5.5V 0

4000 kHz

3.3V~5.5V 0

8000 kHz

WDTOSC

Watchdog Oscillator Period

45 90 180

32 65 130

WDT1

Watchdog Time-out Period (RC)

¾¾

WDTOSC

WDT2

Watchdog Time-out Period (System Clock)

¾¾

SYS

RES

External Reset Low Pulse Width

¾¾

¾¾ms

SST

System Start-up Timer Period

Wake-up from HALT

1024

SYS

LVR

Low Voltage Reset Time

¾¾

0.25 1 2 ms

INT

Interrupt Pulse Width

¾¾

¾¾ms

AD1

A/D Clock Period HT46R46

¾¾

0.5

¾¾ms

AD2

A/D Clock Period HT46R47/HT46R48A/HT46R49

¾¾

¾¾ms

ADC1

A/D Conversion Time HT46R46

¾¾ ¾64¾

AD1

ADC2

A/D Conversion Time HT46R47/HT46R48A/HT46R49

¾¾ ¾76¾

AD2

ADCS1

A/D Sampling Time HT46R46

¾¾ ¾32¾

AD1

ADCS2

A/D Sampling Time HT46R47/HT46R48A/HT46R49

¾¾ ¾32¾

AD2

Note: *t

SYS

=1/f

SYS

HT46R46/C46/R47/C47/R48A/C48A/R49

Rev. 1.41 7 December 30, 2008

HT46R46/C46/R47/C47/R48A/C48A/R49

Rev. 1.41 8 December 30, 2008

System Architecture

A key factor in the high-performance features of the Holtek range of Cost-Effective A/D Type microcontrollers is attributed to the internal system ar

chitecture. The range of devices take advantage of the usual features found within RISC microcontrollers pro

viding increased speed of operation and enhanced per

formance. The pipelining scheme is implemented in such a way that instruction fetching and instruction exe

cution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all operations of the instruction set. It carries out arith

metic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumula

tor and the ALU. Certain internal registers are imple

mented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural fea

tures ensure that a minimum of external components is required to provide a functional I/O and A/D control sys

tem with maximum reliability and flexibility. This makes these devices suitable for low-cost, high-volume pro

duction for controller applications requiring from 1K up to 4K words of Program Memory and 64 to 128 bytes of Data Memory storage.

Clocking and Pipelining

The main system clock, derived from either a Crys

tal/Resonator or RC oscillator is subdivided into four in

ternally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecutive in

struction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute.

When the RC oscillator is used, OSC2 is freed for use as a T1 phase clock synchronizing pin. This T1 phase clock has afrequency of f

SYS

/4 witha 1:3 high/low duty cycle.

For instructions involving branches, such as jump or call instructions, two machine cycles are required to com

plete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications

F e t c h I n s t . ( P C )

E x e c u t e I n s t . ( P C - 1 )

F e t c h I n s t . ( P C + 1 )

E x e c u t e I n s t . ( P C )

F e t c h I n s t . ( P C + 2 )

E x e c u t e I n s t . ( P C + 1 )

P C P C + 1 P C + 2

O s c i l l a t o r C l o c k

( S y s t e m C l o c k )

P h a s e C l o c k T 1

P r o g r a m C o u n t e r

P h a s e C l o c k T 2

P h a s e C l o c k T 3

P h a s e C l o c k T 4

P i p e l i n i n g

System Clocking and Pipelining

F e t c h I n s t . 1 E x e c u t e I n s t . 1

F e t c h I n s t . 2

F l u s h P i p e l i n e

D E L A Y :

M O V A , [ 1 2 H ]

C A L L D E L A Y

C P L [ 1 2 H ]

N O P

E x e c u t e I n s t . 2

F e t c h I n s t . 3

F e t c h I n s t . 6 E x e c u t e I n s t . 6

F e t c h I n s t . 7

Instruction Fetching

HT46R46/C46/R47/C47/R48A/C48A/R49

Rev. 1.41 9 December 30, 2008

Program Counter

During program execution, the Program Counter is used to keep track of the address of the next instruction to be executed. It is automatically incremented by one each time an instruction is executed except for instructions,

such as ²JMP² or ²CALL² that demand a jump to a non-consecutive Program Memory address. For the Cost-Effective A/D Type series of microcontrollers, note that the Program Counter width varies with the Program Memory capacity depending upon which device is se

lected. However, it must be noted that only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by user.

When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the Program Counter. For condi

tional skip instructions, once the condition has been

met, the next instruction, which has already been fetched during the present instruction execution, is dis

carded and a dummy cycle takes its place while the cor

rect instruction is obtained.

The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and is a readable and writable register. By transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be in

serted.

The lower byte of the Program Counter is fully accessi

ble under program control. Manipulating the PCL might cause program branching, so an extra cycle is needed to pre-fetch. Further information on the PCL register can be found in the Special Function Register section.

Mode

Program Counter Bits

b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

Initial Reset 000000000000

External Interrupt 000000000100

Timer/Event Counter Overflow

000000001000

A/D Converter Interrupt 000000001100

Skip Program Counter + 2

Loading PCL PC11 PC10 PC9 PC8 @7 @6 @5 @4 @3 @2 @1 @0

Jump, Call Branch #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0

Return from Subroutine S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

Program Counter

Note: PC11~PC8: Current Program Counter bits

@7~@0: PCL bits #11~#0: Instruction code address bits S11~S0: Stack register bits For the HT46R49, the Program Counter is 12 bits wide, i.e. from b11~b0. For the HT46R47 and HT46R48A, the Program Counter is 11 bits wide, i.e. From b10~b0, therefore the b11 column in the table is not applicable.

For the HT46R46, the Program Counter is 10 bits wide, i.e. from b9~b0, therefore the b11 and b10 the columns in the table are not applicable.

HT46R46/C46/R47/C47/R48A/C48A/R49

Rev. 1.41 10 December 30, 2008

Stack

This is a special part of the memory which is used to save the contents of the Program Counter only. The stack can have either 4 or 6 levels depending upon which device is selected and is neither part of the data nor part of the program space, and is neither readable nor writable. The activated level is indexed by the Stack Pointer, SP, and is neither readable nor writable. At a subroutine call or interrupt acknowledge signal, the con

tents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, sig

naled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack.

If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching.

Note: Forthe HT46R46, 4levels of stackare available

and for the HT46R47,HT46R48A and HT46R49, 6 levels of stack are available.

Arithmetic and Logic Unit - ALU

The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic op

erations of the instruction set. Connected to the main microcontroller data bus, the ALU receives related in

struction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or oper

ations may result in carry, borrow or other status changes, the status register will be correspondingly up

dated to reflect these changes. The ALU supports the following functions:

Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA

Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA

Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC

Increment and Decrement INCA, INC, DECA, DEC

Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI

Program Memory

The Program Memory is the location wherethe user code or program is stored. For microcontrollers, two types of Program Memory are usually supplied. The first type is the One-Time Programmable, OTP, memory where us

ers can program their application code into the device.

Devices with OTP memory are denoted by having an ²R²

within their device name. By using the appropriate pro

gramming tools, OTP devices offer users the flexibility to freely develop their applications which may be useful during debug or for products requiring frequent upgrades or program changes. OTP devices are also applicable for use in applications that require low or medium volume production runs. The other type of memory is the mask

ROM memory, denoted by having a ²C² within the device name. These devices offer the most cost effective solu

tions for high volume products.

Structure

The Program Memory has a capacity of 1K by 14, 2K by 14 or 4K by 15 bits depending upon which device is selected. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries. Table data, which can be setup in any location within the Program Memory, is addressed by separate table pointer registers.

Special Vectors

Within the Program Memory, certain locations are re

served for special usage such as reset and interrupts.

Location 000H This vector is reserved for use by the device reset for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution.

Location 004H This vector is used by the external interrupt. If the ex

ternal interrupt pin on the device goes low, the pro

gram will jump to this location and begin execution if the external interrupt is enabled and the stack is not full.

Location 008H This internal vector is used by the Timer/Event Coun

ter. If a counter overflow occurs, the program will jump to this location and begin execution if the timer/event counter interrupt is enabled and the stack is not full.

Location 00CH This internal vector is used by the A/D converter. When an A/D conversion cycle is complete, the pro

gram will jump to this location and begin execution if the A/D interrupt is enabled and the stack is not full.

P r o g r a m C o u n t e r

S t a c k L e v e l 1

S t a c k L e v e l 2

S t a c k L e v e l 3

S t a c k L e v e l N

P r o g r a m M e m o r y

T o p o f S t a c k

S t a c k

P o i n t e r

B o t t o m o f S t a c k

HT46R46/C46/R47/C47/R48A/C48A/R49

Rev. 1.41 11 December 30, 2008

Look-up Table

Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, the table pointer must first be setup by placing the lower order address of the look up data to be retrieved in the table pointer register, TBLP. This register defines the lower 8-bit address of the look-up table.

After setting up the table pointer, the table data can be retrieved from the current Program Memory page or last

Program Memory page using the ²TABRDC[m]² or

²TABRDL[m]² instructions, respectively. When these in

structions are executed, the lower order table byte from the Program Memory will be transferred to the user de

fined Data Memory register [m] as specified in the in

struction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order

byte will be read as ²0².

The following diagram illustrates the addressing/data flow of the look-up table:

Table Program Example

The following example shows how the table pointer and table data is defined and retrieved from the HT46R47 microcontroller. This example uses raw table data located in the last page which is stored there using the ORG statement. The value at this ORG statement is

²700H² which refers to the start address of the last page within the 2K Program Memory of the HT46R47 microcontroller. The table pointer is setup here to have

an initial value of ²06H². This will ensure that the first data read from the data table will be at the Program

Memory address ²706H² or 6 locations after the start of the last page. Note that the value for the table pointer is referenced to the first address of the present page if the

²TABRDC [m]² instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when

the ²TABRDL [m]² instruction is executed.

3 F F H

N o t I m p l e m e n t e d

1 5 b i t s

1 4 b i t s1 4 b i t s

8 0 0 H

F F F H

0 1 4 H

I n i t i a l i s a t i o n

V e c t o r

E x t e r n a l

I n t e r r u p t V e c t o r

I n i t i a l i s a t i o n

V e c t o r

E x t e r n a l

I n t e r r u p t V e c t o r

T i m e r / E v e n t C o u n t e r

I n t e r r u p t V e c t o r

I n i t i a l i s a t i o n

V e c t o r

E x t e r n a l

I n t e r r u p t V e c t o r

T i m e r / E v e n t C o u n t e r

I n t e r r u p t V e c t o r

H T 4 6 R 4 7 H T 4 6 R 4 8 A H T 4 6 R 4 9H T 4 6 R 4 6

A / D C o n v e r t e r

I n t e r r u p t V e c t o r

A / D C o n v e r t e r

I n t e r r u p t V e c t o r

A / D C o n v e r t e r

I n t e r r u p t V e c t o r

T i m e r / E v e n t C o u n t e r

I n t e r r u p t V e c t o r

0 0 0 H

0 0 4 H

0 0 8 H

0 0 C H

0 1 0 H

3 0 0 H

7 F F H

4 0 0 H

Program Memory Structure

P r o g r a m M e m o r y

P r o g r a m C o u n t e r H i g h B y t e

T B L P

T B L H S p e c i f i e d b y [ m ]

T a b l e C o n t e n t s H i g h B y t e

T a b l e C o n t e n t s L o w B y

t e

HT46R46/C46/R47/C47/R48A/C48A/R49

Rev. 1.41 12 December 30, 2008

tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2

: :

mov a,06h ; initialise table pointer - note that this address

; is referenced

mov tblp,a ; to the last page or present page

: :

tabrdl tempreg1 ; transfers value in table referenced by table pointer

; to tempregl ; data at prog. memory address ²706H² transferred to

; tempreg1 and TBLH

dec tblp ; reduce value of table pointer by one

tabrdl tempreg2 ; transfers value in table referenced by table pointer

; to tempreg2 ; data at prog.memory address ²705H² transferred to

; tempreg2 and TBLH ; in this example the data ²1AH² is transferred to ; tempreg1 and data ²0FH² to register tempreg2 ; the value ²00H² will be transferred to the high byte

; register TBLH : :

org 700h ; sets initial address of last page (for HT46R47)

Dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh

: :

Because the TBLH register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation.

Data Memory

The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. Divided into two sections, the first of these is an area of RAM where special function registers are located. These registers have fixed locations and are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. The second area of Data Memory is reserved for general purpose use. All locations within this area are read and write accessible under program control.

Instruction

Table Location Bits

b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

TABRDC

[m] PC11 PC10 PC9 PC8 @7 @6 @5 @4 @3 @2 @1 @0

TABRDL

[m]1111@7@6@5@4@3@2@1@0

Table Location

Note: PC11~PC8: Current Program Counter bits

@7~@0: Table Pointer TBLP bits

For the HT46R49 the Table address location is 12 bits, i.e. from b11~b0.

For the HT46R47 and HT46R48A, the Table address location is 11 bits, i.e. from b10~b0.

For the HT46R46, the Table address location is 10 bits, i.e. from b9~b0.

HT46R46/C46/R47/C47/R48A/C48A/R49

Rev. 1.41 13 December 30, 2008

Structure

The two sections of Data Memory, the Special Purpose and General Purpose Data Memory are located at con

secutive locations. All are implemented in RAM and are 8 bits wide but the length of each memory section is dic

tated by the type of microcontroller chosen. The start address of the Data Memory for all devices is the ad

dress ²00H². Registers which are common to all microcontrollers, such as ACC, PCL, etc., have the same Data Memory address.

General Purpose Data Memory

All microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. It is this area of RAM memory that is known as General Purpose Data Memory. This area of Data Memory is fully accessible by the user pro

gram for both read and write operations. By using the

²SET [m].i² and ²CLR [m].i² instructions individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the Data Memory.

Special Purpose Data Memory

This area of Data Memory is where registers, necessary for the correct operation of the microcontroller, are stored. Most of the registers are both readable and writable but some are protected and are readable only, the details of which are located under the relevant Spe

cial Function Register section. Note that for locations that areunused, any readinstruction to these addresses

will return the value ²00H².

Special Function Registers

To ensure successful operation of the microcontroller, certain internal registers are implemented in the Data Memory area. These registers ensure correct operation

of internal functions such as timers, interrupts, etc., as well as external functions such as I/O data control and A/D converter operation. The location of these registers within the Data Memory begins at the address 00H. Any unused Data Memory locations between these special function registers and the point where the General Pur

pose Memory begins is reserved for future expansion purposes, attempting to read data from these locations will return a value of 00H.

Indirect Addressing Register - IAR

The IAR register, located at Data Memory address

²00H², is not physically implemented. This special register allows what is known as indirect addressing, which permits data manipulation using Memory Pointers instead of the usual direct memory addressing method where the actual memory address is defined. Any ac

tions on the IAR register will result in corresponding read/write operations to the memory location specified by the Memory Pointer MP. Reading the IAR register in

directly will return a result of ²00H² and writing to the register indirectly will result in no operation.

Memory Pointer - MP

One Memory Pointer, known as MP, is physically imple

mented in Data Memory. The Memory Pointer can be written to and manipulated in the same way as normal registers providing an easy way of addressing and tracking data. When using any operation on the indirect addressing register IAR, it is actually the address speci

fied by the Memory Pointer that the microcontroller will be directed to.

For devices with 64 or 88 bytes of RAM Data Memory, bit 7 of the Memory Pointer is not implemented. How

ever, it must be noted that when the Memory Pointer for these devices is read, bit 7 will be read as high.

G e n e r a l P u r p o s e D a t a M e m o r y

S p e c i a l P u r p o s e D a t a M e m o r y

0 0 H

4 0 H

B F H

3 F H

G e n e r a l P u r p o s e D a t a M e m o r y

S p e c i a l P u r p o s e D a t a M e m o r y

0 0 H

4 0 H

7 F H

3 F H

H T 4 6 R 4 6 a n d H T 4 6 R 4 7

H T 4 6 R 4 9

G e n e r a l P u r p o s e D a t a M e m o r y

S p e c i a l P u r p o s e D a t a M e m o r y

0 0 H

2 8 H

7 F H

2 7 H

H T 4 6 R 4 8 A

Data Memory Structure

Note:

Most ofthe Data Memorybits can be directly manipulated using the ²SET [m].i² and ²CLR [m].i² with the excep

tion ofa few dedicated bits. The Data Memory can also be accessed through thememory pointer register MP.

HT46R46/C46/R47/C47/R48A/C48A/R49

Rev. 1.41 14 December 30, 2008

The following example shows how to clear a section of four RAM locations already defined as locations adres1 to adres4.

data .section ¢data¢ adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ?

code .section at 0 ¢code¢ org 00h

start:

mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; Accumulator loaded with first RAM address mov mp,a ; setup memory pointer with first RAM address

loop:

clr IAR ; clear the data at address defined by MP inc mp ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop

continue:

The importantpoint to note here is that in the example shownabove, no reference is made to specific RAM addresses.

0 0 H 0 1 H 0 2 H 0 3 H 0 4 H 0 5 H 0 6 H 0 7 H 0 8 H

0 9 H 0 A H 0 B H 0 C H 0 D H 0 E H

0 F H

1 0 H

1 1 H

1 2 H

1 3 H

1 4 H

1 5 H

1 6 H

1 7 H

1 8 H

1 9 H 1 A H 1 B H 1 C H 1 D H 1 E H

1 F H

2 0 H

2 1

H 2 2 H 2 3 H : U n u s e d , r e a d a s " 0 0 "

I A R

M P

A C C

P C L T B L P T B L H

S T A T U S

I N T C

T M R

T M R C

P A

P A C

P B

P B C

P D

P D C P W M

A D R

A D C R A C S R

H T 4 6 R 4 6

I A R M P

A C C

P C L T B L P T B L H

S T A T U S

I N T C

T M R

T M R C

P A

P A C

P B

P B C

P D

P D C P W M

A D R L A D R H A D C R A C S R

H T 4 6 R 4 7

I A R M P

A C C

P C L T B L P T B L H

S T A T U S

I N T C

T M R

T M R C

P A

P A C

P B

P B C

P C

P C C

P D

P D C

P W M

A D R L

A D R H A D C R A C S R

H T 4 6 R 4 8 A

I A R M P

A C C

P C L T B L P T B L H

S T A T U S

I N T C

T M R

T M R C

P A

P A C

P B

P B C

P C

P C C

P D

P D C

P W M 0 P W M 1

A D R L

A D R H A D C R A C S R

H T 4 6 R 4 9

Special Purpose Data Memory

HT46R46/C46/R47/C47/R48A/C48A/R49

Rev. 1.41 15 December 30, 2008

Accumulator - ACC

The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of the Accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted.

Program Counter Low Register - PCL

To provide additional program control functions, the low byte of the Program Counter is made accessible to pro

grammers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily imple

mented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory lo

cation, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted.

Look-up Table Registers - TBLP, TBLH

These two special function registers are used to control operation of the look-up table which is stored in the Program Memory. TBLP is the table pointer and indicates the location where the table data is located. Its value must be setup before any table read commands are ex

ecuted. Its value can be changed, for example using the

²INC² or ²DEC² instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user de

fined location.

Status Register - STATUS

This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation and system manage

ment flagsare used to record the status and operation of the microcontroller.

With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, opera

tions related to the status register may give different re

sults due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT

time-out or by executing the ²CLR WDT² or ²HALT² in

struction. The PDF flag is affected only by executing the

²HALT² or ²CLR WDT² instruction or during a system power-up.

The Z, OV, AC and C flags generally reflect the status of the latest operations.

C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction.

AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared.

Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.

OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit,or vice versa; otherwise OV is cleared.

PDF is cleared by a system power-up or executing the ²CLR WDT² instruction. PDF is set by executing the ²HALT² instruction.

TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is set by a WDT time-out.

T O P D F O V Z A C C

S T A T U S R e g i s t e r

A r i t h m e t i c / L o g i c O p e r a t i o n F l a g s

C a r r y f l a g A u x i l i a r y c a r r y f l a g Z e r o f l a g O v e r f l o w f l a g

S y s t e m M a n a g e m e n t F l a g s

P o w e r d o w n f l a g W a t c h d o g t i m e - o u t f l a g N o t i m p l e m e n t e d , r e a d a s " 0 "

b 7 b 0

Status Register

HT46R46/C46/R47/C47/R48A/C48A/R49

Rev. 1.41 16 December 30, 2008

In addition, on entering an interrupt sequence or execut

ing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it.

Interrupt Control Register - INTC

This 8-bit register, known as the INTC register, controls the operation of both external and internal timer inter

rupts. By setting various bits within this register using standard bit manipulation instructions, the enable/disable function of each interrupt can be independently con

trolled. A master interrupt bit within this register, the EMI bit, acts like a global enable/disable and is used to set all of the interrupt enable bits on or off. This bit is cleared when an interrupt routine is entered to disable further in

terrupt and is set by executing the ²RETI² instruction.

Timer/Event Counter Registers - TMR, TMRC

All devices possess a single internal 8-bit count-up timer. An associated register known as TMR is the loca

tion where the timer¢s 8-bit value is located. This register can also be preloaded with fixed data to allow different time intervals to be setup. An associated control regis

ter, known as TMRC, contains the setup information for this timer, which determines in what mode the timer is to be used as well as containing the timer on/off control function.

Input/Output Ports and Control Registers

Within the area of Special Function Registers, the I/O registers and their associated control registers play a prominent role. All I/O ports have a designated register correspondingly labeled as PA, PB, PC and PD. These labeled I/O registers are mapped to specific addresses within the Data Memory as shown in the Data Memory table, which are used to transfer the appropriate output or input data on that port. With each I/O port there is an associated control register labeled PAC, PBC, PCC and PDC, also mapped to specific addresses with the Data Memory. The control register specifies which pins of that port are set as inputs and which are set as outputs. To setup a pin as an input, the corresponding bit of the con

trol register must be set high, for an output it must be set low. During program initialization, it is important to first setup the control registers to specify which pins are out

puts and which are inputs before reading data from or writing data to the I/O ports. One flexible feature of these registers is the ability to directly program single bits us

ing the ²SET [m].i² and ²CLR [m].i² instructions. The ability to change I/O pins from output to input and vice versa by manipulating specific bits of the I/O control reg

isters during normal program operation is a useful fea

ture of these devices.

Pulse Width Modulator Registers PWM, PWM0, PWM1

Each device in the Cost-Effective A/D Type microcontroller range contains either one or two Pulse Width Modulators. Each one has its own related inde

pendent control register. For devices with a single PWM function this is register is known as PWM, while for de

vices with two PWM functions, their control register names are PWM0 and PWM1. The 8-bit contents of these registers, defines the duty cycle value for the modulation cycle of the corresponding Pulse Width Modulator.

A/D Converter Registers ADR, ADRL, ADRH, ADCR, ACSR

Each device in the Cost-Effective A/D Type microcontroller range contains a 4-channel 8-bit or 9-bit A/D converter. The correct operation of the A/D requires the use of one or two data registers, a control register and a clock source register. For the HT46R46 device, which has an 8-bit A/D converter, there is a single data register, known as ADR. For the other devices, which contain a 9-bit A/D converter, there are two data regis

ters, a high byte data register known as ADRH, and a low byte data register known as ADRL. These are the register locations where the digital value is placed after the completion of an analog to digital conversion cycle. The channel selection and configuration of the A/D con

verter is setup via the control register ADCR while the A/D clock frequency is defined by the clock source reg

ister, ACSR.

HT46R46/C46/R47/C47/R48A/C48A/R49

Rev. 1.41 17 December 30, 2008

Input/Output Ports

Holtek microcontrollers offer considerable flexibility on their I/Oports. With theinput or output designation of ev

ery pin fully under user program control, pull-high op

tions for all ports and wake-up options on certain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities.

Depending upon which device or package is chosen, the microcontroller range provides from 13 to 23 bidirectional input/output lines labeled with port names PA, PB, PC and PD. These I/O ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose Data Memory table. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of

instruction ²MOV A,[m]², where m denotes the port ad

dress. For output operation, all the data is latched and remains unchanged until the output latch is rewritten.

Pull-high Resistors

Many product applications require pull-high resistors for their switch inputs usually requiring the use of an exter

nal resistor. To eliminate the need for these external re

sistors, all I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor. These pull-high resistors are selectable via configuration options and are implemented using a weak PMOS transistor.

Port A Wake-up

Each device has a HALT instruction enabling the microcontroller to enter a Power Down Mode and preserve power, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port Apins from high to

low. After a ²HALT² instruction forces the microcontroller into entering a HALT condition, the processor will re

main idle or in a low-power state until the logic condition of the selected wake-up pin on Port Achanges from high to low. This function is especially suitable for applica

tions that can be woken up via external switches. Note that each pin on Port A can be selected individually to have this wake-up feature.

I/O Port Control Registers

Each I/O port has its own control register PAC, PBC, PCC and PDC, to control the input/output configuration. With this control register, each CMOS output or input with or without pull-high resistor structures can be re

configured dynamicallyunder software control.Each pin

of the I/O ports is directly mapped to a bit in its associ

ated port control register. For the I/O pin to function as an input, the corresponding bit of the control register

must be written as a ²1². This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is

written as a ²0², the I/O pin will be setup as a CMOS out

put. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin.

Pin-shared Functions

The flexibility of the microcontroller range is greatly en

hanced by the use of pins that have more than one func

tion. Limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be over

come. For some pins, the chosen function of the multi-function I/O pins is set by configuration options while for others the function is set by application pro

gram control.

External Interrupt Input The external interrupt pin INT

is pin-shared with the I/O pin PA5. For applications not requiring an external interrupt input, the pin-shared external interrupt pin can be used as a normal I/O pin, however to do this, the external interrupt enable bits in the INTC register must be disabled.

External Timer Clock Input The external timer pin TMR is pin-shared with the I/O pin PA4. To configure it to operate as a timer input, the corresponding control bits in the timer control register must be correctly set. For applications that do not re

quire an external timer input, the pin can be used as a normal I/O pin. Note that if used as a normal I/O pin the timer mode control bits in the timer control register must select the timer mode, which has an internal clock source, to prevent the input pin from interfering with the timer operation.

PFD Output Each device contains a PFD function whose single output is pin-shared with PA3. The output function of this pin is chosen via a configuration option and re

mains fixed after the device is programmed. Note that the corresponding bit of the port control register, PAC.3, must setup the pin as an output to enable the PFD output. If the PAC port control register has setup the pin as an input, then the pin will function as a nor

mal logic input with the usual pull-high option, even if the PFD configuration option has been selected.

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Rev. 1.41 18 December 30, 2008

PWM Outputs All devices contain one or two PWM outputs pin shared with pins PD0 and PD1. The PWM output functions are chosen via configuration options and re

main fixed after the device is programmed. Note that the corresponding bit or bits of the port control regis

ter, PDC, must setup the pin as an output to enable the PWM output. If the PDC port control register has setup the pin as an input, then the pin will function as a normal logic input with the usual pull-high option, even if the PWM configuration option has been selected.

A/D Inputs Each device has four A/D converter inputs. All of these analog inputs are pin-shared with I/O pins on Port B. If these pins are to be used as A/D inputs and not as normal I/O pins then the corresponding bits in the A/D Converter Control Register, ADCR, must be properly set. There are no configuration options asso

ciated with the A/D function. If used as I/O pins, then full pull-high resistor configuration options remain, however if used as A/D inputs then any pull-high resis

tor options associated with these pins will be automat

ically disconnected.

D D

M U X

W a k e - u p O p t i o n

S y s t e m W a k e - u p

R e a d D a t a R e g i s t e r

C o n t r o l B i t

P u l l - H i g h O p t i o n

D a t a B u s

W r i t e C o n t r o l R e g i s t e r

C h i p R e s e t

R e a

d C o n t r o l R e g i s t e r

W r i t e D a t a R e g i s t e r

D a t a B i t

I / O P i n

W e a k P u l l - u p

C K

P A o n l y

Non-pin-shared Function Input/Output Ports

D D

M U X

R e a d D a t a R e g i s t e r

C o n t r o l B i t

P u l l - H i g h O p t i o n

D a t a B u s

W r i t e C o n t r o l R e g i s t e r

C h i p R e s e t

R e a d C o n t r o l R e g i s t e r

W r i t e D a t a R e g i s t e r

D a t a B

i t

I N T f o r P A 5 o n l y T M R f o r P A 4 o n l y

P A 4 / T M R P A 5 / I N T

W a k e - u p O p t i o n

S y s t e m W a k e - u p

W e a k P u l l - u p

C K

PA4/PA5 Input/Output Ports

HT46R46/C46/R47/C47/R48A/C48A/R49

Rev. 1.41 19 December 30, 2008

D D

U X

R e a d D a t a R e g i s t e r

C o n t r o l B i t

P u l l - H i g h O p t i o n

D a t a B u s

W r i t e C o n t r o l R e g i s t e r

C h i p R e s e t

R e a d C o n t r o l R e g i s t e r

W r i t e D a t a R e g i s t e r

D a t a B

i t

P B 0 / A N 0 ~ P B 3 / A N 3

A C S 2 ~ A C S 0

T o A / D C o n v e r t e r

P C R 2 P C R 1 P C R 0

W e a k P u l l - u p

A n a l o g

I n p u t

S e l e c t o r

C K

PB Input/Output Ports

D D

P F D o r P W M W a v e f o r m

M U

R e a d D a t a R e g i s t e r

C o n t r o l B i t

P u l l - H i g h O p t i o n

D a t a B u s

W r i t e C o n t r o l R e g i s t e r

C h i p R e s e t

R e a d C o n t r o l R e g i s t e r

W r i t e D a t a R e g i s t e r

D a t a B

i t

P F D / P W M O p t i o n

M U X

W e a k P u l l - u p

C K

P A 3 / P F D P D 0 / P W M

P D 0 / P W M 0 P D 1 / P W M 1

( H T 4 6 R 4 9 2 8 - p i n p a c k a g e o n l y )

PA3/PFD and PD/PWM Input/Output Ports

HT46R46/C46/R47/C47/R48A/C48A/R49

Rev. 1.41 20 December 30, 2008

I/O Pin Structures

The following diagrams illustrate the I/O pin internal structures. As the exact logical construction of the I/O pin may differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins.

Programming Considerations

Within the user program, one of the first things to con

sider is port initialization. After a reset, all of the I/O data and port control registers will be set high. This means that all I/O pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high options have been selected. If the port control registers, PAC, PBC, PCC and PDC, are then programmed to setup some pins as outputs, these out

put pins will have an initial high output value unless the associated port data registers, PA, PB, PC and PD, are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control regis

ter or by programming individual bits in the port control

tions. Note that when using these bit control instruc

tions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports.

Port Ahas the additional capability of providing wake-up functions. When the device is in the Power Down Mode, various methods are available to wake the device up. One of these is a high to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function.

Note that some devices have different package types which may result in some I/O pins not being bonded out.

If these pins are setup as inputs they may oscillate and increase power consumption, especially notable if the device isin the PowerDown Mode. It is therefore recom

mended that any unbonded pins should be setup as out

puts, or if setup as inputs, then they should be connected to pull-high resistors.

Timer/Event Counters

The provision of timers form an important part of any microcontroller giving the designer a means of carrying out time related functions. Each device contains an in

ternal 8-bit count-up timer. With three operating modes, the timers can be configured to operate as a general timer, external event counter or as a pulse width mea

surement device. The provision of an internal 8-stage prescaler to the timer clock circuitry gives added range to the timer.

There are two registers related to the Timer/Event Counter, TMR and TMRC. The TMR register is the reg

ister that contains the actual timing value. Writing to TMR places an initial starting value in the Timer/Event Counter preload register while reading TMR retrieves the contents of the Timer/Event Counter. The TMRC register is a Timer/Event Counter control register, which defines the timer options, and determines how the timer is to be used. The timer clock source can be configured to come from the internal system clock source or from an external clock on shared pin PA4/TMR.

Configuring the Timer/Event Counter Input Clock Source

The internal timer¢s clock source can originate from either the system clock or from an external clock source. The system clock input timer source is used when the timer is in the timer mode or in the pulse width measure

ment mode. The internal timer clock also passes through a prescaler, the value of which is conditioned by the bits PSC0, PSC1 and PSC2.

An external clock source is used when the timer is in the event counting mode, the clock source being provided on pin-shared pin PA4/TMR. Depending upon the condi

tion of the TE bit, each high to low, or low to high transi

tion on the PA4/TMR pin will increment the counter by one.

T 1 T 2

T 3 T 4

T 1 T 2

T 3 T 4

W r i t e t o P o r t R e a d f r o m P o r t

S y s t e m C l o c k

P o r t D a t a

Read/Write Timing

P A 4 / T M R I n p u t

T i m e r / E v e n t C o u n t e r

M o d e C o n t r o l

T O N

P r e l o a d R e g i s t e r

T i m e r / E v e n t C o u n t e r

D a t a B u s

R e l o a d

O v e r f l o w t o I n t e r r u p t

8 - S t a g e P r e s c a l e r

P S C 2 ~ P S C 0

( 1 / 1 ~ 1 / 1 2 8 )

8 - B i t T i m e r / E v e n t C o u n t e r

T M 1 T M 0

f S Y S

P F D

8-bit Timer/Event Counter Structure

HT46R46/C46/R47/C47/R48A/C48A/R49

Rev. 1.41 21 December 30, 2008

Timer Register - TMR

The TMR register is an 8-bit special function register lo

cation within the special purpose Data Memory where the actual timer value is stored. The value in the timer registers increases by one each time an internal clock pulse is received or an external transition occurs on the PA4/TMR pin. The timer will count from the initial value loaded by the preload register to the full count value of FFH at which point the timer overflows and an internal interrupt signal generated. The timer value will then be reset with the initial preload register value and continue counting. For a maximum full range count of 00H to FFH the preload register must first be cleared to 00H. It should be noted that after power-on the preload register will be in an unknown condition. Note that if the Timer/Event Counter is not running and data is written to its preload register, this data will be immediately written into the actual counter. However, if the counter is en

abled and counting, any new data written into the preload register during this period will remain in the preload register and will only be written into the actual counter the next time an overflow occurs.

Timer Control Register - TMRC

The flexible features of the Holtek microcontroller Timer/Event Counters enable them to operate in three different modes, the options of which are determined by the contents of the Timer Control Register TMRC. To

gether with the TMR register, these two registers control the full operation of the Timer/Event Counters. Before the timer can be used, it is essential that the TMRC reg

ister is fully programmed with the right data to ensure its correct operation, a process that is normally carried out during program initialisation.

To choose which of the three modes the timer is to oper

ate in, the timer mode, the event counting mode or the pulse width measurement mode, bits TM0 and TM1 must be set to the required logic levels. The timer-on bit TON or bit 4 of the TMRC register provides the basic on/off control of the timer, setting the bit high allows the counter to run, clearing the bit stops the counter. Bits 0~2 of the TMRC register determine the division ratio of the input clock prescaler. The prescaler bit settings have no effect if an external clock source is used. If the timer is in the event count or pulse width measurement mode the active transition edge level type is selected by the logic level of the TE or bit 3 of the TMRC register.

T M R C R e g i s t e r

N o t i m p l e m e n t e d , r e a d a s " 0 "

b 7

E v e n t C o u n t e r A c t i v e E d g e S e l e c t 1 : c o u n t o n f a l l i n g e d g e 0 : c o u n t o n r i s i n g e d g e

T ET O NT M 0T M 1

T i m e r P r e s c a l e r R a t e S e l e c t

b 0

P S C 2

P S C 1 P S C 0

P S C 1

0 0 1 1 0 0 1 1

P S C 2

0 0 0 0 1 1 1 1

P S C 0

0 1 0 1 0 1 0 1

T i m e r R a t e 1 : 1 1 : 2 1 : 4 1 : 8 1 : 1 6 1 : 3 2 1 : 6 4

1 : 1 2 8

T i m e r / E v e n t C o u n t e r C o u n t i n g E n a b l e 1 : e n a b l e 0 : d i s a b l e

O p e r a t i n g M o d e S e l e c t T M 1

0 0 1 1

T M 0

0 1 0 1

n o m o d

e a v a i l a b l e e v e n t c o u n t e r m o d e t i m e r m o d e p u l s e w i d t h m e a s u r e m e n t m o d e

P u l s e W i d t h M e a s u r e m e n t A c t i v e E d g e S e l e c t 1 : s t a r t c o u n t i n g o n r i s i n g e d g e , s t o p o n f a l l i n g e d g e 0 : s t

a r t c o u n t i n g o n f a l l i n g e d g e , s t o p o n r i s i n g e d g e

Timer/Event Counter Control Register

HT46R46/C46/R47/C47/R48A/C48A/R49

Rev. 1.41 22 December 30, 2008

Configuring the Timer Mode

In this mode, the timer can be utilised to measure fixed time intervals, providing an internal interrupt signal each time the counter overflows. To operate in this mode, bits TM1 and TM0 of the TMRC register must be set to 1 and 0 respectively. In this mode, the internal clock is used as the timer clock. The input clock frequency to the timer is f

SYS

divided by the value programmed into the timer prescaler, the value of which is determined by bits PSC0~PSC2 of the TMRC register. The timer-on bit, TON must be set high to enable the timer to run. Each time an internal clock high to low transition occurs, the timer increments by one. When the timer is full andover

flows, the timer will be reset to the value already loaded into the preload register and continue counting. If the timer interrupt is enabled, an interrupt signal will also be generated. Thetimer interrupt canbe disabled by ensur

ing that the ETI bit in the INTC register is cleared to zero. It should be noted that a timer overflow is one of the wake-up sources.

Configuring the Event Counter Mode

In this mode, a number of externally changing logic events, occurring on external pin PA4/TMR, can be re

corded by the internal timer. For the timer to operate in the event counting mode, bits TM1 and TM0 of the TMRC register must be set to 0 and 1 respectively. The timer-on bit, TON must be set high to enable the timer to count. With TE low, the counter will increment each time the PA4/TMR pin receives a low to high transition. If the TE bit is high, the counter will increment each time TMR receives a high to low transition. As in the case of the other two modes, when the counter is full and overflows, the timer will be reset to the value already loaded into the preload register and continue counting. If the timer interrupt is enabled, an interrupt signal will also be gen

erated. The timer interrupt can be disabled by ensuring that the ETI bit in the INTC register is cleared to zero. To ensure that the external pin PA4/TMR is configured to operate asan event counter input pin, two things have to happen. The first is to ensure that the TM0 and TM1 bits place the timer/event counter in the event counting

mode, the second is to ensure that the port control regis

ter configures the pin as an input. It should be noted that a timer overflow is one of the wake-up sources. Also in the Event Counting mode, the Timer/Event Counter will continue to record externally changing logic events on the timer input pin, even if the microcontroller is in the Power Down Mode. As a result when the timer over

flows it will generate a wake-up and if the interrupts are enabled also generate a timer interrupt signal.

Configuring the Pulse Width Measurement Mode

In this mode, the width of external pulses applied to the pin-shared external pin PA4/TMR can be measured. In the Pulse Width Measurement Mode, the timer clock source is supplied by the internal clock. For the timer to operate in this mode, bits TM0 and TM1 must both be set high. If the TE bit is low, once a high to low transition has been received on the PA4/TMR pin, the timer will start counting until the PA4/TMR pin returns to its origi

nal high level. At this point the TON bit will be automati

cally reset to zero and the timer will stop counting. If the TE bit is high, the timer will begin counting once a low to high transition has been received on the PA4/TMR pin and stop counting when the PA4/TMR pin returns to its original lowlevel. As before,the TON bit will be automat

ically reset to zero and the timer will stop counting. It is important to note that in the Pulse Width Measurement Mode, the TON bit is automatically reset to zero when the external control signal on the external timer pin returns to its original level, whereas in the other two modes the TON bit can only be reset to zero under program control. The residual value in the timer, which can now be read by the program, therefore represents the length of the pulse received on pin PA4/TMR. As the TON bit has now been reset any further transitions on the PA4/TMR pin will be ignored. Not until the TON bit is again set high by the program can the timer begin fur

ther pulse width measurements. In this way single shot pulse measurements can be easily made. It should be noted that in this mode the counter is controlled by logi

cal transitions on the PA4/TMR pin and not by the logic level.

I n c r e m e n t

T i m e r C o n t r o l l e r

P r e s c a l e r O u t p u t

T i m e r + 1

T i m e r + 2

T i m e r + N T i m e r + N + 1

Timer Mode Timing Chart

T i m e r + 2

E x t e r n a l E v e n t

I n c r e m e n t

T i m e r C o u n t e r

T i m e r + 3T i m e r + 1

Event Counter Mode Timing Chart

HT46R46/C46/R47/C47/R48A/C48A/R49

Rev. 1.41 23 December 30, 2008

As in the case of the other two modes, when the counter is full and overflows, the timer will be reset to the value already loaded into the preload register. If the timer in

terrupt is enabled, an interrupt signal will also be gener

ated. To ensure that the external pin PA4/TMR is configured to operate as a pulse width measuring input pin, two things have to happen. The first is to ensure that the TM0 and TM1 bits place the timer/event counter in the pulse width measuring mode, the second is to en

sure that the port control register configures the pin as an input. It should be noted that a timer overflow is one of the wake-up sources.

Programmable Frequency Divider - PFD

The PFD output is pin-shared with the I/O pin PA3. The PFD function is selected via configuration option, how

ever, if not selected, the pin can operate as a normal I/O pin. The timer overflow signal is the clock source for the PFD circuit. The output frequency is controlled by load

ing the required values into the timer prescaler registers to give the required division ratio. The counter, driven by the system clock which is divided by the prescaler value, will begin to count-up from this preload register value until full, at which point an overflow signal is generated, causing the PFD output to change state. The counter will then be automatically reloaded with the preload reg

ister value and continue counting-up.

For the PFD output to function, it is essential that the corresponding bit of the Port A control register PAC bit 3 is setup as an output. If setup as an input the PFD output will not function, however, the pin can still be used as a normal input pin. The PFD output will only be activated if

bit PA3 is set to ²1². This output data bit is used as the on/off control bit for the PFD output. Note that the PFD output will be low if the PA3 output data bit is cleared to

²0².

Using this method of frequency generation, and if a crystal oscillator is used for the system clock, very pre

cise values of frequency can be generated.

Prescaler

Bits PSC0~PSC2 of the TMRC register can be used to define the pre-scaling stages of the internal clock sources of the Timer/Event Counter. The Timer/Event Counter overflow signal can be used to generate signals for the PFD and Timer Interrupt.

I/O Interfacing

The Timer/Event Counter, when configured to run in the event counter or pulse width measurement mode, re

quire the use of the external PA4/TMR pin for correct op

eration. As this pin is a shared pin it must be configured correctly to ensure it is setup for use as a Timer/Event Counter input and not as a normal I/O pin. This is imple

mented by ensuring that the mode select bits in the Timer/Event Counter control register, select either the event counter or pulse width measurement mode. Addi

tionally the Port Control Register PAC bit 4 must be set high to ensure that the pin is setup as an input. Any pull-high resistor configuration option on this pin will remain valid even if the pin is used as a Timer/Event Counter input.

+ 1 + 2 + 3 + 4

T i m e r

E x t e r n a l T M R

P i n I n p u t

T O N ( w i t h T E = 0 )

P r e s c a l e r O u t p u t

I n c r e m e n t

T i m e r C o u n t e r

P r e s c a l e r O u t p

u t i s s a m p l e d a t e v e r y f a l l i n g e d g e o f T 1 .

Pulse Width Measure Mode Timing Chart

T i m e r O v e r f l o w

P F D C l o c k

P A 3 D a t a

P F D O u t p u t a t P A 3

PFD Output Control

HT46R46/C46/R47/C47/R48A/C48A/R49

Rev. 1.41 24 December 30, 2008

Programming Considerations

When configured to run in the timer mode, the internal system clock is used as the timer clock source and is therefore synchronized with the overall operation of the microcontroller. In this mode when the appropriate timer register is full, the microcontroller will generate an internal interrupt signal directing the program flow to the respec

tive internal interrupt vector. For the pulse width mea

surement mode, the internal system clock is also used as the timer clock source but the timer will only run when the correct logic condition appears on the external timer input pin. As this is an external event and not synchronized with the internal timer clock, the microcontroller will only see this external event when the next timer clock pulse arrives. As a result, there may be small differences in measured values requiring programmers to take this into account during programming. The same applies if the timer is configured to be in the event counting mode, which again is an external event and not synchronized with the internal system or timer clock.

When the Timer/Event Counter is read, or if data is writ

ten to the preload register, the clock is inhibited to avoid errors, however as this may result in a counting error, this should be taken into account by the programmer. Care must be taken to ensure that the timers are properly in

itialised before using them for the first time. The associated timer enable bits in the interrupt control register must be properly set otherwise the internal interrupt associated with the timer will remain inactive. The edge select, timer mode and clock source control bits in timer control register must also be correctly set to ensure the timer is properly configured for the required application. It is also important to ensure that an initial value is first loaded into the timer registers before the timer is switched on; this is because after power-on the initial values of the timer reg

isters are unknown. After the timer has been initialised

the timer can be turned on and off by controlling the en

able bit in the timer control register. Note that setting the

timer enable bit high to turn the timer on, should only be executed after the timer mode bits have been properly setup. Setting the timer enable bit high together with a mode bit modification, may lead to improper timer oper

ation if executed as a single timer control register byte write instruction.

When the Timer/Event counter overflows, its corre

sponding interrupt request flag in the interrupt control register will be set. If the timer interrupt is enabled this will in turn generate an interrupt signal. However irre

spective of whether the interrupts are enabled or not, a Timer/Event counter overflow will also generate a wake-up signal if the device is in a Power-down condi

tion. This situation may occur if the Timer/Event Counter is in the Event Counting Mode and if the external signal continues to change state. In such a case, the Timer/Event Counter will continue to count these exter

nal events and if an overflow occurs the device will be woken up from its Power-down condition. To prevent such a wake-up from occurring, the timer interrupt re

quest flag should first be set high before issuing the HALT instruction to enter the Power Down Mode.

Timer Program Example

This program example shows how the Timer/Event Counter registers are setup, along with how the interrupts are enabled and managed. Note how the Timer/Event Counter is turned on, by setting bit 4 of the Timer Control Register. The Timer/Event Counter can be turned off in a similar way by clearing the same bit. This example program sets the Timer/Event Counter to be in the timer mode, which uses the internal system clock as the clock source.

org 04h ; external interrupt vector reti org 08h ; Timer/Event Counter interrupt vector jmp tmrint ; jump here when Timer overflows : org 20h ; main program ;internal Timer/Event Counter interrupt routine tmrint: : ; Timer/Event Counter main program placed here : reti : :

begin: ;setup Timer registers mov a,09bh ; setup Timer preload value mov tmr,a; mov a,081h ; setup Timer control register mov tmrc,a ; timer mode and prescaler set to /2 ; setup interrupt register mov a,005h ; enable master interrupt and timer interrupt mov intc,a set tmrc.4 ; start Timer - note mode bits must be previously setup

+ 53 hidden pages

Holtek HT46R46, HT46C48A, HT46C46, HT46R49, HT46C47 User Manual

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User Manual