HOLTEK HT46R32, HT46R34 User Manual

HT46R32/HT46R34

A/D Type 8-Bit OTP MCU with OPA

Technical Document

Tools Information

FAQs

Application Note

HA0003E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM

HA0049E Read and Write Control of the HT1380

HA0051E Li Battery Charger Demo Board - Using the HT46R47

HA0052E Microcontroller Application - Battery Charger

HA0083E Li Battery Charger Demo Board - Using the HT46R46

Features

Operating voltage: f

=4MHz: 2.2V~5.5V

SYS

=8MHz: 3.3V~5.5V

SYS

20 bidirectional I/O lines (max.)

Single interrupt input shared with an I/O line

8-bit programmable timer/event counter with overflow interrupt and 7-stage prescaler

Integrated crystal and RC oscillator

Watchdog Timer

2048´14 Program Memory capacity - HT46R32 4096´15 Program Memory capacity - HT46R34

88´8 Data Memory capacity - HT46R32 192´8 Data Memory capacity - HT46R34

Integrated PFD function for sound generation

Power-down and wake-up functions reduce power consumption

Up to 0.5ms instruction cycle with 8MHz system clock at V

=5V

6-level subroutine nesting

4 channel 12-bit resolution A/D converter

Integrated single operational amplifier or comparator selectable via configuration option

Dual 8-bit PWM outputs shared with I/O lines

Bit manipulation instruction

Full table read instruction

63 powerful instructions

All instructions executed in one or two machine cycles

Low voltage reset function

28-pin SKDIP/SOP/SSOP package

General Description

The HT46R32 and HT46R34 are 8-bit, high perfor mance, RISC architecture microcontroller devices. With their fully integrated A/D converter they are especially suitable for applications which interface to analog sig nals, such as those from sensors. The addition of an in ternal operational amplifier/comparator and PWM modulation functions further adds to the analog capabil ity of these devices.

Rev. 1.10 1 March 16, 2007

With the comprehensive features of low power con sumption, I/O flexibility, programmable frequency di vider, timer functions, oscillator options, multi-channel

A/D Converter OP/Comparator, Pulse Width Modula

tion function, Power-down and wake-up functions etc, the application scope of these devices is broad and en

compasses areas such as sensor signal processing, motor driving, industrial control, consumer products, subsystem controllers, etc.

Block Diagram

P r o g r a m

R O M

I n s t r u c t i o n

R e g i s t e r

I n s t r u c t i o n

D e c o d e r

T i m i n g

G e n e r a t o r

P r o g r a m

C o u n t e r

M P

A L U

S h i f t e r

M U X

S T A C K

M U X

D A T A

M e m o r y

S T A T U S

P A 5 / I N T

I n t e r r u p t

C i r c u i t

I N T C

P A 3 , P A 5

T M R C

T M R

P A 3 / P F D

W D T

P W M

P D C

P D

4 - C h a n n e l

A / D C o n v e r t e r

P B C

P B

P o r t D

P o r t B

HT46R32/HT46R34

P r e s c a l e r f U X

P A 4

M U X

P D 0 / P W M 0 P D 1 / P W M 1 P D 2 P D 3

P B 0 / A N 0 ~ P B 3 / A N 3 P B 4 ~ P B 7

P A 4 / T M R

S Y S

W D T O S C

S Y SM

/ 4

O S C 2 O S C 1

R E S V D D V S S

L V RA C C

A P N

A P P

A P O

P A C

P o r t A

P A

P A 0 ~ P A 2 P A 3 / P F D P A 4 / T M R P A 5 / I N T P A 6 ~ P A 7

Rev. 1.10 2 March 16, 2007

Pin Assignment

HT46R32/HT46R34

P B 5

P B 4

P A 3 / P F D

P B 3 / A N 3

P B 2 / A N 2

P B 1 / A N 1

P B 0 / A N 0

P A 2

P A 1

P A 0

1 0

A P O

1 1

A P N

1 2

A P P

1 3

V S S

1 4

H T 4 6 R 3 2 / H T 4 6 R 3 4

2 8 S K D I P - A / S O P - A / S S O P - A

2 8

2 7

2 6

2 5

2 4

2 3

2 2

2 1

2 0

1 9

1 8

1 7

1 6

1 5

P B 6

P B 7

P A 4 / T M R

P A 5 / I N T

P A 6

P A 7

O S C 2

O S C 1

V D D

R E S

P D 0 / P W M 0

P D 1 / P W M 1

P D 2

P D 3

Pin Description

Pin Name I/O Options Description

PA0~PA2 PA3/PFD PA4/TMR PA5/INT PA6, PA7

PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4~PB7

PD0/PWM0 PD1/PWM1 PD2 PD3

APO APN APP

RES

VDD

VSS

OSC1 OSC2

I/O

Wake-up

PA3 or PFD

I/O Pull-high

Pull-high

I/O

PD0 or PWM0 PD1 or PWM1

¾¾

Crystal

or RC

Bidirectional 8-bit input/output port. Each pin can be configured as wake-up input by configuration options. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. Configuration options determine which pins on the port have pull-high resistors. The PFD, TMR and INT pin-shared with PA3, PA4 and PA5, respectively.

Bidirectional 8-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. Configuration options determine which pins on the port have pull-high resistors. Pins PB0~PB3 are pin-shared with the A/D input pins. The A/D inputs are selected via software instructions. Once selected as an A/D input, the I/O function and pull-high resistor are disabled automatically.

Bi-directional 4-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. Configuration options determine which pins on this port have pull-high resistors. PD0/PD1 are pin-shared with the PWM0/PWM1 outputs selected via configuration option.

APO, APN and APP are the internal operational amplifier, output pin, nega tive input pin and positive input pin respectively .

Schmitt trigger reset input. Active low.

Positive power supply

Negative power supply, ground.

OSC1, OSC2 are connected to an external RC network or external crystal, determined by configuration option, for the internal system clock. If the RC system clock option is selected, pin OSC2 can be used to measure the sys tem clock at 1/4 frequency.

pins are

Rev. 1.10 3 March 16, 2007

HT46R32/HT46R34

Absolute Maximum Ratings

Supply Voltage...........................VSS-0.3V to VSS+6.0V

Input Voltage..............................V

Total ..............................................................150mA

-0.3V to VDD+0.3V

Total Power Dissipation .....................................500mW

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may

cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.

Storage Temperature ............................-50°Cto125°C

Operating Temperature...........................-40°Cto85°C

Total............................................................-100mA

D.C. Characteristics

Symbol Parameter

DD1

DD2

DD3

STB1

STB2

IL1

IH1

IL2

IH2

LVR

ADC

DNL ADC Differential Non-Linearity 5V

INL ADC Integral Non-Linearity 5V

RESOLU Resolution

Operating Voltage

Operating Current (Crystal OSC)

Operating Current (RC OSC)

Operating Current (Crystal OSC, RC OSC)

Standby Current (WDT Enabled)

Standby Current (WDT Disabled)

Input Low Voltage for I/O Ports, TMR and INT

Input High Voltage for I/O Ports, TMR and INT

Input Low Voltage (RES)

Input High Voltage (RES)

Low Voltage Reset

I/O Port Sink Current

I/O Port Source Current

Pull-high Resistance

A/D Input Voltage

Additional Power Consumption if A/D Converter is Used

Operating Temperature: 40°C~+85°C, Ta=25°C

Test Conditions

Conditions

=4MHz

SYS

=8MHz

SYS

No load, f

SYS

ADC disable

No load, f

SYS

ADC disable

No load, f

SYS

ADC disable

No load, system HALT

=4MHz

=8MHz

¾¾

=0.1V

=0.9V

¾¾

=1ms ¾¾±2

=1ms ¾±2.5

¾¾ ¾¾

Min. Typ. Max. Unit

2.2

3.3

0.6 1.5 mA

24mA

0.8 1.5 mA

2.5 4 mA

48mA

¾¾

0.7V

0.9V

5.5 V

0.3V

0.4V

2.7 3.0 3.3 V

10 20

-2 -4 ¾

-5 -10 ¾

20 60 100

10 30 50

0.5 1 mA

1.5 3 mA

4mA

12 Bits

Rev. 1.10 4 March 16, 2007

HT46R32/HT46R34

A.C. Characteristics

Symbol Parameter

SYS

TIMER

WDTOSC

WDT1

WDT2

RES

SST

LVR

INT

ADC

ADCS

System Clock (Crystal OSC, RC OSC)

Timer I/P Frequency (TMR)

Watchdog Oscillator Period

Watchdog Time-out Period (WDT OSC)

Watchdog Time-out Period (System Clock)

External Reset Low Pulse Width

System Start-up Timer Period

Low Voltage Width to Reset

Interrupt Pulse Width

A/D Clock Period

A/D Conversion Time

A/D Sampling Time

Test Conditions

Conditions

2.2V~5.5V 400

3.3V~5.5V 400

2.2V~5.5V 0

3.3V~5.5V 0

¾¾

Wake-up from HALT

¾¾

Min. Typ. Max. Unit

45 90 180

32 65 130

¾¾ms

1024

0.25 1 2 ms

¾¾ms

¾¾ ¾80¾

¾¾ ¾32¾

Ta=25°C

4000 kHz

8000 kHz

4000 kHz

8000 kHz

WDTOSC

SYS

Note: *t

SYS

=1/f

SYS

OP Amplifier Electrical Characteristics

Symbol Parameter

D.C. Electrical Characteristic

OPOS1

OPOS2

Operating Voltage

Input Offset Voltage 5V

Input Offset Voltage 5V By Calibration

Common Mode Voltage Range

PSRR Power Supply Rejection Ratio

CMRR Common Mode Rejection Ratio 5V

RES

Response Time (Comparator)

A.C. Electrical Characteristic

OPOS1

Open Loop Gain

SR Slew Rate +, Slew Rate -

GBW Gain Band Width

¾¾

¾ Input overdrive=±10mV ¾¾

¾¾

Test Conditions

Conditions

¾-10 ¾

=0~VDD-1.4V

No load

=1M, CL=100p

Ta=25°C

Min. Typ. Max. Unit

5.5 V

10 mV

-2 ¾

60 80

0.1

¾¾

2mV

1.4V

¾ V/ms

100 kHz

Rev. 1.10 5 March 16, 2007

Functional Description

Execution Flow

The system clock for the microcontroller is derived from either a crystal or an RC oscillator. The system clock is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles.

Instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while de coding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruc tion to effectively execute in a cycle. If an instruction changes theprogram counter, two cycles are required to complete the instruction.

Program Counter - PC

The programcounter controls the sequence in which the instructions stored in program memory are executed and whose contents specify full range of program mem ory.

After accessing a program memory word to fetch an in struction code, the contents of the program counter are

HT46R32/HT46R34

incremented byone. The program counter then points to the memory word containing the next instruction code.

When executing a jump instruction, conditional skip ex ecution, loading PCL register, subroutine call, initial re set, internal interrupt, external interrupt or return from subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction.

The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during

the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise proceed with the next instruction.

The lower byte of the program counter, PCL, is a read able and writeable register. Moving data into the PCL performs a short jump. The destination will be within 256 locations.

When a control transfer takes place, an additional

dummy cycle is required.

S y s t e m C l o c k

O S C 2 ( R C o n l y )

T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4

P C

P C P C + 1 P C + 2

F e t c h I N S T ( P C )

E x e c u t e I N S T ( P C - 1 )

F e t c h I N S T ( P C + 1 )

E x e c u t e I N S T ( P C )

F e t c h I N S T ( P C + 2 )

E x e c u t e I N S T ( P C + 1 )

Execution Flow

Mode

*11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0

Program Counter

Initial Reset 000000000000

External Interrupt 000000000100

Timer/Event Counter Overflow 000000001000

A/D Converter Interrupt 000000001100

Skip Program Counter+2

Loading PCL *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0

Jump, Call Branch #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0

Return from Subroutine S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

Program Counter

Note: PC11~PC8: Current Program Counter bits S11~S0: Stack register bits

#11~#0: Instruction Code bits @7~@0: PCL bits For the HT46R32 device the Program Counter is 11 bits wide, i.e. from b10~b0, therefore the b11 column in the table is not applicable.

Rev. 1.10 6 March 16, 2007

HT46R32/HT46R34

Program Memory - ROM

The program memory is used to store the program in structions which are to be executed as well as table data and interrupt entries. It is structured into 2K´14 bits for the HT46R32 device and 4K x 15 bits for the HT46R34 device, which can be addressed by both the program counter and table pointer.

Certain locations in the program memory are reserved for use by the reset and by the interrupt vectors.

Location 000H This vector is reserved for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution.

Location 004H This vector is used by the external interrupt INT

.Ifthe external interrupt pin on the device receives a low go ing edge,the program willjump to this location and be gin execution if the external interrupt is enabled and the stack is not full.

Location 008H This vector is used by the Timer/Event Counter. If a timer overflow occurs, the program will jump to this loca tion and begin execution if the timer interrupt is enabled and the stack is not full.

Location 00CH This vector is used by the A/D converter. When an A/D cycle conversion is complete, the program will jump to this location and begin execution if the A/D interrupt is enabled and the stack is not full.

Table location Any location in the Program Memory space can be used as a look-up table. The instructions ²TABRDC [m]² (the current page, 1 page=256 words) and ²TABRDL [m]² (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH. Only the destina tion of the lower-order byte in the table is well-defined, the other bits of the table word are transferred to the lower portion of TBLH, and the remaining bits are read as ²0². The Table Higher-order byte register (TBLH) is read only. The table pointer (TBLP) is a read/write reg ister, which indicates the table location. Before ac cessing the table, the location must be placed in TBLP. The TBLH register is read only and cannot be

0 0 0 H

0 0 4 H

0 0 8 H

0 0 C H

n 0 0 H

n F F H

7 0 0 H

7 F F H

D e v i c e I n i t i a l i z a t i o n P r o g r a m

E x t e r n a l I n t e r r u p t S u b r o u t i n e

T i m e r / E v e n t C o u n t e r I n t e r r u p t S u b r o u t i n e

A / D C o n v e r t e r I n t e r r u p t S u b r o u t i n e

L o o k - u p T a b l e ( 2 5 6 w o r d s )

1 4 b i t s

N o t e : n r a n g e s f r o m 0 t o 7

P r o g r a m M e m o r y

Program Memory - HT46R32

0 0 0 H

0 0 4 H

0 0 8 H

0 0 C H

n 0 0 H

n F F H

F 0 0 H

F F F H

D e v i c e I n i t i a l i z a t i o n P r o g r a m

E x t e r n a l I n t e r r u p t S u b r o u t i n e

T i m e r / E v e n t C o u n t e r I n t e r r u p t S u b r o u t i n e

A / D C o n v e r t e r I n t e r r u p t S u b r o u t i n e

L o o k - u p T a b l e ( 2 5 6 w o r d s )

1 5 b i t s

N o t e : n r a n g e s f r o m 0 t o F

P r o g r a m M e m o r y

Program Memory - HT46R34

restored. If the main routine and the ISR, Interrupt Service Routine, both employ the table read instruc tion, the contents of the TBLH in the main routine are

likely to be changed by the table read instruction used

Instruction

*11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0

Table Location

TABRDC [m] P11 P10 P9 P8 @7 @6 @5 @4 @3 @2 @1 @0

TABRDL [m] 1111@7@6@5@4@3@2@1@0

Table Location

Note: *11~*0: Table location bits P11~P8: Current program counter bits

@7~@0: Table pointer bits For the HT46R32 device the Table address is 11 bits wide, i.e. from b10~b0, therefore the b11 column in the table is not applicable.

Rev. 1.10 7 March 16, 2007

HT46R32/HT46R34

in the ISR. In such a case errors can occur. Therefore, using the table read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read instruction has to be used in both the main routine and the ISR, the interrupt is should be disabled prior to the table read instruction. It should not be re-enabled until the TBLH has been backed up. All table related instructions require two cycles to complete their operation. These areas may function as normal program memory depending upon require ments.

Stack Register - STACK

This is a special part of the memory which is used to save the contents of the program counter only. The stack is organized into 6 levels and is neither part of the data nor part of the program space, and is neither read able nor writeable. The activated level is indexed by the stack pointer, known as stack pointer, and is also neither readable nor writeable. At a subroutine call or interrupt acknowledgment, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the program counter is restored to its pre vious value from the stack. After a device reset, the stack pointer will point to the top of the stack.

If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledgment will be inhibited. When the stack pointer is decremented, using a RET or RETI instruction, the interrupt will be serviced. This feature prevents a stack overflow allowing the programmer to use the structure more easily. In a similar case, if the stack is full and a ²CALL² is subsequently executed, stack overflow occurs and the first entry will be lost. Only the most recent 6 return addresses are stored.

Data Memory - RAM

The data memory has a structure of 110´8 bits for the HT46R32 device and 215 x 8 bits for the HT46R34 de vice. The data memory is divided into two functional groups: special function registers and general purpose data memory. The general purpose memory has a structure of 88 x 8 bits for the HT46R32 device and 192bits x 8 bits for the HT46R34 device. Most locations are read/write, but some are read only.

The remaining space between the end of the Special Purpose Data Memory and the beginning of the General Purpose Data Memory is reserved for future expanded usage, reading these locations will obtain a result of ²00H². The general purpose data memory, addressed from 28H to 7FH in the HT46R32, and from 40H to FFH in the HT46R34, is used for user data and control infor mation under instruction commands. All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can

be set and reset by the ²SET [m].i² and ²CLR [m].i² in structions. They are also indirectly accessible through memory pointer register, MP.

I n d i r e c t A d d r e s s i n g R e g i s t e r

0 0 H

0 1 H

0 2 H

0 3 H

0 4 H

0 5 H

0 6 H

0 7 H

0 8 H

0 9 H

0 A H

0 B H

0 C H

0 D H

0 E H

0 F H

1 0 H

1 1 H

1 2 H

1 3 H

1 4 H

1 5 H

1 6 H

1 7 H

1 8 H

1 9 H

1 A H

1 B H

1 C H

1 D H

1 E H

1 F H

2 0 H

2 1 H

2 2 H 2 3 H

2 4 H

2 7 H 2 8 H

7 F H

M P

A C C

P C L

T B L P

T B L H

S T A T U S

I N T C

T M R

T M R C

S p e c i a l P u r p o s e

P A

P A C

P B

P B C

P D

P D C

P W M 0

P W M 1

O P A C

A D R L

A D R H

A D C R

A C S R

H T 4 6 R 3 2 / H T 4 6 R 3 4

G e n e r a l P u r p o s e

D a t a M e m o r y

( 8 8 B y t e s )

H T 4 6 R 3 2 H T 4 6 R 3 4

D a t a M e m o r y

: U n u s e d

R e a d a s " 0 0 "

2 4 H

3 9 H 4 0 H

F F H

G e n e r a l P u r p o s e

D a t a M e m o r y

RAM Mapping

Indirect Addressing Register

Location 00H is an indirect addressing register that is

not physicallyimplemented. Any read/write operation on [00H] accesses data memory pointed to by the MP register. Reading location 00H itself indirectly will return the result00H. Writing indirectly results in no operation.

For the HT46R32 device the memory pointer register, MP, is a 7-bit register, while for the HT46R34 device it is an 8-bit register. For the HT46R32 device, bit 7 of MP is un defined and if read will return the result ²1², any write op eration will only transfer the lower 7-bits of data to MP.

Accumulator

The accumulator is closely related to ALU operations

and can carry out immediate data operations. Any data

movement between two data memory locations must pass through the accumulator.

( 1 9 2 B y t e s )

Rev. 1.10 8 March 16, 2007

HT46R32/HT46R34

Arithmetic and Logic Unit - ALU

This circuit performs 8-bit arithmetic and logic opera tions. The ALU provides the following functions:

Arithmetic operations - ADD, ADC, SUB, SBC, DAA

Logic operations - AND, OR, XOR, CPL

Rotation - RL, RR, RLC, RRC

Increment and Decrement - INC, DEC

Branch decision - SZ, SNZ, SIZ, SDZ ....

The ALU not only saves the results of a data operation but also changes the status register.

Status Register - STATUS

This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power

tion operations related to the status register may give different results from those intended. The TO flag

can be affected only by system power-up, a WDT time-out or executing the ²CLR WDT² or ²HALT² in struction. The PDF flag can be affected only by exe cuting the ²HALT² or ²CLR WDT² instruction or a system power-up.

The Z, OV, AC and C flags generally reflect the status of the latest operations.

In addition, on entering the interrupt sequence or exe cuting the subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status are important and if the subroutine can cor rupt the status register, precautions must be taken to

save it properly. down flag (PDF), and watchdog time-out flag (TO). It also records the status information and controls the op eration sequence.

With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addi

Interrupt

The devices provide an external interrupt, an internal

timer/event counter interrupt and an A/D converter inter

rupt. The Interrupt Control Register, INTC, contains the

interrupt control bits to set the enable or disable and the

interrupt request flags.

Bit No. Label Function

C is set if an operation results in a carry during an addition operation or if a borrow does not

take place during a subtraction operation, otherwise C is cleared. C is also affected by a rotate through carry instruction.

1AC

AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction, otherwise AC is cleared.

2 Z Z is set if the result of an arithmetic or logic operation is zero, otherwise Z is cleared.

3OV

4 PDF

5TO

6, 7

OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa, otherwise OV is cleared.

PDF iscleared by a system power-up or executing the ²CLR WDT² instruction. PDF is set by executing the ²HALT² instruction.

TO is cleared by a system power-up or executing the ²CLR WDT²or ²HALT²instruction. TO is set by a WDT time-out.

¾ Unused bit, read as ²0²

Status (0AH) Register

Bit No. Label Function

0 EMI Controls the master (global) interrupt (1=enabled; 0=disabled)

1 EEI Controls the external interrupt (1=enabled; 0=disabled)

2 ETI Controls the Timer/Event Counter interrupt (1=enabled; 0=disabled)

3 EADI Controls the A/D converter interrupt (1=enabled; 0=disabled)

4 EIF External interrupt request flag (1=active; 0=inactive)

5 TF Internal Timer/Event Counter request flag (1=active; 0=inactive)

6 ADF A/D converter request flag (1=active; 0=inactive)

¾ Unused bit, read as ²0²

INTC (0BH) Register

Rev. 1.10 9 March 16, 2007

HT46R32/HT46R34

Once an interrupt subroutine is serviced, all the other in terrupts will be blocked by clearing the EMI bit. This scheme may prevent any further interrupt nesting. Other interrupt requests may happen during this interval but only the interrupt request flag is recorded. If a certain in terrupt requires servicing within the service routine, the EMI bit and the corresponding bit in INTC may be set to allow interrupt nesting. If the stack is full, the interrupt re quest will not be acknowledged, even if the related inter rupt is enabled, until the stack pointer is decremented. If immediate service is desired, the stack must be pre vented from becoming full.

All interrupts have a wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the pro gram counter onto the stack, followed by a branch to a subroutine at a specified location in the program mem ory. Only the program counter is pushed onto the stack. If the contents of the register or status register are al tered by the interrupt service program which corrupts the desired control sequence, the contents should be saved in advance.

External interrupts are triggered by a high to low transi tion on the INT

pin, which will set the related interrupt re quest flag, EIF, which is bit 4 of INTC. When the interrupt is enabled, the stack is not full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag, EIF, and EMI bits will be cleared to disable other interrupts.

The internal timer/event counter interrupt is initialised by setting the timer/event counter interrupt request flag, TF, which is bit 5 of INTC, caused by a timer overflow. When the interrupt is enabled, the stack is not full and the TF bit is set, a subroutine call to location 08H will occur. The related interrupt request flag, TF, will be reset and the EMI bit cleared to disable further interrupts.

The A/D converter interrupt is initialised by setting the A/D converter request flag, ADF, which is bit 6 of INTC, caused by an end of A/D conversion. When the interrupt is enabled, the stack is not full and the ADF bit is set, a subroutine call to location 0CH will occur. The related in terrupt request flag, ADF, will be reset and the EMI bit cleared to disable further interrupts.

During the execution of an interrupt subroutine, other in terrupt acknowledgments are held until the RETI in struction is executed or the EMI bit and the related interrupt control bit are set to 1. Of course, the stack must not be full. To return from the interrupt subroutine, a RET or RETI instruction may be executed. A RETI in struction will set the EMI bit to enable an interrupt ser vice, but a RET instruction will not.

Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding inter rupts are enabled. In the case of simultaneous requests the following table shows the priority that is applied.

These can be masked by resetting the EMI bit.

Interrupt Source Priority Vector

External Interrupt 1 004H

Timer/Event Counter Overflow 2 008H

A/D Converter Interrupt 3 00CH

Once the interrupt request flags, TF, EIF, ADF, are set,

they will remain in the INTC register until the interrupts are serviced or cleared by a software instruction.

It is recommended that a program does not use the CALL subroutine within the interrupt subroutine. Interrupts of ten occur in an unpredictable manner or need to be ser

viced immediately in some applications. If only one stack is left and enabling the interrupt is not well controlled, the

original control sequence will be damaged once the ²CALL² operates in the interrupt subroutine.

Oscillator Configuration

There are two oscillator circuits in the microcontroller, namely an RC oscillator and a crystal oscillator, the

choice of which is determined by a configuration option.

When the system enters the Power-down mode the sys tem oscillator stops and ignores external signals to con serve power.

If an RC oscillator is used, an external resistor between OSC1 and VSS is required whose resistance value must range from 24kW to 1MW. The system clock, divided by 4, can be monitored on pin OSC2 if a pull-high resistor is connected. This signal can be used to synchronise external logic. The RC oscillator provides the most cost effective solution, however the frequency of oscillation may vary with VDD, temperature and the process variations. It is, therefore, not suitable for tim ing sensitive operations where an accurate oscillator frequency is desired.

If the Crystal oscillator is used, a crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator; no other external compo

nents are required. Instead of a crystal, a resonator can also be connected between OSC1 and OSC2 to get a frequency reference, but two external capacitors in

OSC1 and OSC2 are required, If the oscillating fre

quency is less than 1MHz.

The WDT oscillator is a free running on-chip RC oscilla tor, and requires no external components. Even if the system enters the power down mode, the system clock

O S C 1

O S C 2

C r y s t a l O s c i l l a t o r R C O s c i l l a t o r

D D

4 7 0 p F

/ 4

S Y S

System Oscillator

O S C 1

O S C 2

Rev. 1.10 10 March 16, 2007

HT46R32/HT46R34

is stopped, but the WDT oscillator keeps running with a period of approximately 65ms at 5V. The WDT oscillator can be disabled by a configuration option to conserve power.

Watchdog Timer - WDT

The WDT clock source comes from either its own inte grated RC oscillator,known as the WDT oscillator, or the instruction clock, which is the system clock divided by 4. The choice of which one is used is decided by a configuration option. This timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. The Watchdog Timer can be disabled by a configuration op tion. If the Watchdog Timer is disabled, all the execu tions related to the WDT result in no operation.

Once the internal WDT oscillator (RC oscillator with a period of 65ms at 5V nominal) is selected, it is divided by 32768~65536 to get a time-out period of approximately

2.1s~4.3s. This time-out period may vary with tempera tures, VDD and process variations. If the WDT oscillator is disabled, the WDT clock may still come from the in struction clock and operate in the same manner except that in the Power-down state the WDT may stop count ing and lose its protecting purpose. In this situation the logic can only be restarted by external logic.

If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT instruction will stop the system clock.

The WDT overflow under normal operation will initialise a ²chip reset² and set the status bit ²TO². But in the Power-down mode, the overflow will initialisze a ²warm reset², andonly the programcounter and SPare reset to zero. To clear the contents of the WDT, three methods are adopted; external reset (a low level on the RES

pin),

a software instruction and a HALT instruction. The soft ware instruction include ²CLR WDT² and the other set ²CLR WDT1² and ²CLR WDT2². Of these two types of instruction, only one can be active depending on the

configuration option -²CLR WDT times selection op tion².Ifthe²CLR WDT² is selected (i.e. CLR WDT times equal one), any execution of the ²CLR WDT² instruction will clear the WDT. In the case that ²CLR WDT1² and ²CLR WDT2² are chosen (i.e. CLR WDT times equal two), these two instructions must be executed to clear

the WDT; otherwise, the WDT may reset the chip as a result of time-out.

Power Down Operation - HALT

The HALT mode is initialised by the ²HALT² instruction and results in the following...

The system oscillator will be turned off but the WDT oscillator keeps running (if the WDT oscillator is se lected).

The contents of the on chip Data Memory and regis ters remain unchanged.

WDT will be cleared and start counting again (if the WDT clock is from the WDT oscillator).

All of the I/O ports maintain their original status.

The PDF flag is set and the TO flag is cleared.

The system can leave the HALT mode by means of an external reset, an interrupt, an external falling edge sig

nal on port A or a WDT overflow. An external reset causes a device initialisation and the WDT overflow performs a ²warm reset². After the TO and PDF flags are examined, the reason for the chip reset can be determined. The PDF flag is cleared by a system power-up or executing the ²CLR WDT² instruction and is set when executing the ²HALT² instruction. The TO flag is set if the WDT time-out occurs, and causes a wake-up that only resets the program counter and Stack Pointer; the others keep their original status.

The port A wake-up and interrupt methods can be con sidered as a continuation of normal execution. Each bit in port A can be independently selected to wake up the

device by the options. Awakening from an I/O port stim ulus, the program will resume execution of the next in struction. If it is awakening from an interrupt, two sequences may happen. If the related interrupt is dis

S y s t e m C l o c k / 4

W D T

O S C

O p t i o n S e l e c t

8 - b i t C o u n t e r

7 - b i t C o u n t e r

W D T T i m e - o u t

1 5 1 6

/ 2 ~ fS/ 2

C L R W D T

Watchdog Timer

Rev. 1.10 11 March 16, 2007

HT46R32/HT46R34

abled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. If the interrupt is enabled and the stack is not full, the regu lar interrupt response takes place. If an interrupt request flag is set to ²1² before entering the HALT mode, the wake-up functionof the related interrupt will be disabled. Once a wake-up event occurs, it takes 1024 t

SYS

(sys tem clock period) to resume normal operation. In other words, a dummy period will be inserted after wake-up. If the wake-up results from an interrupt acknowledgment, the actual interrupt subroutine execution will be delayed by one or more cycles. If the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished.

To minimise power consumption, all the I/O pins should be carefully managed before entering the status.

Reset

There are three ways in which a reset can occur:

RES reset during normal operation

RES reset during HALT

WDT time-out reset during normal operation

The WDT time-out during HALT is different from other chip reset conditions, since it can perform a ²warm re set² that resets only the program counter and stack pointer, leaving the other circuits in their original state. Some registers remain unchanged during other reset conditions. Most registers are reset to the ²initial condition² when the reset conditions are met. By examining the PDF and TO flags, the program can distinguish between different ²chip resets².

TO PDF RESET Conditions

0 0 RES

u u RES

0 1 RES

reset during power-up

reset during normal operation

wake-up HALT

1 u WDT time-out during normal operation

1 1 WDT wake-up HALT

Note: ²u² means ²unchanged²

To guarantee that the system oscillator is started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses when the sys tem reset (power-up, WDT time-out or RES reset) or the system awakes from the HALT state.

When a system reset occurs, the SST delay is added during the reset period. Any wake-up from HALT will en able the SST delay.

An extra option load time delay is added during system reset (power-up, WDT time-out at normal mode or RES reset).

The functional unit chip reset status are shown below.

Program Counter 000H

Interrupt Disable

WDT

Timer/Event Counter Off

Clear. After master reset, WDT begins counting

Input/Output Ports Input mode

Stack Pointer Points to the top of the stack

V D D

R E S

S S T T i m e - o u t

C h i p R e s e t

S S T

Reset Timing Chart

D D

0 . 0 1mF *

1 0 0 k

R E S

1 0 k

0 . 1mF *

Reset Circuit

Note:

²*² Ensure that the length of the wiring, which is connected to the RES

pin is as short as possi-

ble, to avoid noise interference.

H A L T

W D T

R E S

O S C 1

S S T

1 0 - b i t R i p p l e

C o u n t e r

S y s t e m R e s e t

Reset Configuration

W a r m R e s e t

C o l d R e s e t

Rev. 1.10 12 March 16, 2007

The registers¢ states are summarised in the following table.

HT46R32/HT46R34

MP - HT46R32 1xxx xxxx 1uuu uuuu 1uuu uuuu 1uuu uuuu 1uuu uuuu

MP - HT46R34 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

PCL 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000

TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

TBLH - HT46R32 --xx xxxx --uu uuuu --uu uuuu --uu uuuu --uu uuuu

TBLH - HT46R34 -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu

STATUS --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu

INTC -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu

TMR xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

TMRC 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu

PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu

PAC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu

PB 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu

PBC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu

PD ---- 1111 ---- 1111 ---- 1111 ---- 1111 ---- uuuu

PDC ---- 1111 ---- 1111 ---- 1111 ---- 1111 ---- uuuu

PWM0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

PWM1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

OPAC 0000 1000 0000 1000 0000 1000 0000 1000 uuuu uuuu

ADRL xxxx ---- xxxx ---- xxxx ---- xxxx ---- uuuu ----

ADRH xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

ADCR 0100 0000 0100 0000 0100 0000 0100 0000 uuuu uuuu

ACSR 1--- --00 1--- --00 1--- --00 1--- --00 u--- --uu

Reset

(Power On)

WDT Time-out

(Normal Operation)

RES

(Normal Operation)

Reset

RES Reset

(HALT)

WDT Times-out

(HALT)*

Note:

²*² stands for warm reset ²u² stands for unchanged ²x² stands for unknown

Rev. 1.10 13 March 16, 2007

+ 30 hidden pages

HOLTEK HT46R32, HT46R34 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Technical Document

Features

General Description

Block Diagram

Pin Assignment

Pin Description

Absolute Maximum Ratings

D.C. Characteristics

A.C. Characteristics

OP Amplifier Electrical Characteristics

Functional Description