Holtek HT46R47, HT46R22, HT46R23, HT46R24 Handbook

Page 1

HT46R47, HT46R22, HT46R23, HT46R24

A/D Type MCU

Handbook

October 2004

Copyright Ó 2003 by HOLTEK SEMICONDUCTOR INC. All rights reserved. Printed in Taiwan. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form by any means, electronic, mechanical photo copying, recording, or otherwise without the prior written permission of HOLTEK SEMICONDUCTOR INC.

Page 2

Contents

Part I Microcontroller Profile ................................................................... 1

Contents

Chapter 1 Hardware Structure ......................................................................................... 3

Introduction ....................................................................................................................3

Features ......................................................................................................................... 4

Technology Features ............................................................................................... 4

Kernel Features ....................................................................................................... 4

Peripheral Features ................................................................................................. 4

Selection Table .............................................................................................................. 5

Block Diagram ............................................................................................................... 6

Pin Assignment .............................................................................................................. 7

Pin Description ............................................................................................................... 8

Absolute Maximum Ratings ......................................................................................... 12

D.C. Characteristics ..................................................................................................... 12

A.C. Characteristics ..................................................................................................... 14

System Architecture ..................................................................................................... 15

Clocking and Pipelining ......................................................................................... 15

Program Counter ................................................................................................... 16

Stack ..................................................................................................................... 18

Arithmetic and Logic Unit - ALU ........................................................................... 18

Program Memory ......................................................................................................... 19

Organization .......................................................................................................... 19

Special Vectors ..................................................................................................... 20

Look-up Table ........................................................................................................ 20

Table Program Example ........................................................................................ 21

Data Memory ............................................................................................................... 22

Organization .......................................................................................................... 22

General Purpose Data Memory ............................................................................ 23

Special Purpose Data Memory ............................................................................. 24

Page 3

A/D Type MCU

Special Function Registers .......................................................................................... 25

Indirect Addressing Registers - IAR, IAR0, IAR1 ................................................. 25

Memory Pointers - MP, MP0, MP1 ....................................................................... 25

Bank Pointer - BP ................................................................................................. 26

Accumulator - ACC ............................................................................................... 26

Program Counter Low Register - PCL ................................................................. 26

Look-up Table Registers - TBLP, TBLH ................................................................ 27

Status Register - STATUS .................................................................................... 27

Interrupt Control Registers - INTC, INTC0, INTC1 ............................................... 28

Timer/Event Counter Registers ............................................................................. 28

Input/Output Ports and Control Registers ............................................................. 28

Pulse Width Modulator Registers - PWM, PWM0, PWM1, PWM2, PWM3 .......... 29

C Bus Registers - HADR, HCR, HSR, HDR ....................................................... 29

A/D Converter Registers - ADRL, ADRH, ADCR, ADSR ..................................... 29

Input/Output Ports ........................................................................................................ 29

Pull-high Resistors ................................................................................................ 30

Port A Wake-up ..................................................................................................... 30

I/O Port Control Registers ..................................................................................... 30

Pin-shared Functions ............................................................................................ 30

Programming Considerations ................................................................................ 34

Timer/Event Counters .................................................................................................. 34

Configuring the Timer/Event Counter Input Clock Source .................................... 35

Timer Registers - TMR, TMRL/TMRH, TMR0L/TMR0H, TMR1L/TMR1H ............ 36

Timer Control Registers - TMRC, TMR0C, TMR1C ............................................. 37

Configuring the Timer Mode .................................................................................. 39

Configuring the Event Counter Mode .................................................................... 39

Configuring the Pulse Width Measurement Mode ................................................. 40

Programmable Frequency Divider - PFD ............................................................. 41

Prescaler ............................................................................................................... 42

I/O Interfacing ........................................................................................................ 42

Programming Considerations ................................................................................ 42

Pulse Width Modulator ................................................................................................. 42

6+2 PWM Mode .................................................................................................... 43

7+1 PWM Mode .................................................................................................... 44

PWM Output Control ............................................................................................. 45

Analog to Digital Converter .......................................................................................... 46

A/D Converter Data Registers - ADRL/ADRH ...................................................... 46

A/D Converter Control Register - ADCR .............................................................. 47

A/D Converter Clock Source Register - ACSR ..................................................... 49

A/D Input Pins ....................................................................................................... 49

Summary of A/D Conversion Steps ...................................................................... 50

A/D Transfer Function ........................................................................................... 52

C Bus Serial Interface ............................................................................................... 54

C Bus Slave Address Register - HADR ............................................................. 55

C Bus Input/Output Data Register - HDR ........................................................... 55

C Bus Control Register - HCR ........................................................................... 55

C Bus Status Register - HSR ............................................................................. 55

Page 4

Contents

I2C Bus Communication ........................................................................................ 56

Interrupts ......................................................................................................................60

External Interrupt ................................................................................................... 63

Timer/Event Counter Interrupt ............................................................................... 63

A/D Interrupt .......................................................................................................... 64

C Interrupt ........................................................................................................... 64

Interrupt Priority ..................................................................................................... 64

Programming Considerations ................................................................................ 65

Reset and Initialization ................................................................................................. 65

Reset ..................................................................................................................... 65

Oscillator ......................................................................................................................72

System Clock Configurations ................................................................................ 72

System Crystal/Ceramic Oscillator ........................................................................ 72

System RC Oscillator ............................................................................................ 73

Watchdog Timer Oscillator .................................................................................... 73

HALT and Wake-up in Power Down Mode .................................................................. 73

Watchdog Timer ........................................................................................................... 74

Configuration Options .................................................................................................. 76

Application Circuits .......................................................................................................77

Part II Programming Language ............................................................. 81

Chapter 2 Instruction Set Introduction ......................................................................... 83

Instruction Set .............................................................................................................. 83

Instruction Timing .................................................................................................. 83

Moving and Transferring Data ............................................................................... 84

Arithmetic Operations ............................................................................................ 84

Logical and Rotate Operations .............................................................................. 84

Branches and Control Transfer ............................................................................. 84

Bit Operations ....................................................................................................... 84

Table Read Operations ......................................................................................... 85

Other Operations ................................................................................................... 85

Instruction Set Summary ............................................................................................. 85

Convention ............................................................................................................ 85

Chapter 3 Instruction Definition .................................................................................... 89

Chapter 4 Assembly Language and Cross Assembler .............................................. 101

Notational Conventions .............................................................................................. 101

Statement Syntax ...................................................................................................... 102

Name ................................................................................................................... 102

Operation ............................................................................................................ 102

Operand .............................................................................................................. 102

Comment ............................................................................................................. 103

iii

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A/D Type MCU

Assembly Directives .................................................................................................. 103

Conditional Assembly Directives ......................................................................... 103

File Control Directives ......................................................................................... 104

Program Directives .............................................................................................. 105

Data Definition Directives .................................................................................... 108

Macro Directives .................................................................................................. 110

Assembly Instructions ................................................................................................ 112

Name ................................................................................................................... 112

Mnemonic ............................................................................................................ 112

Operand, Operator and Expression ..................................................................... 112

Miscellaneous ........................................................................................................... 114

Forward References ............................................................................................ 114

Local Labels ........................................................................................................ 114

Reserved Assembly Language Words ................................................................ 115

Cross Assembler Options .......................................................................................... 116

Assembly Listing File Format ..................................................................................... 116

Source Program Listing ....................................................................................... 116

Summary of Assembly ......................................................................................... 117

Miscellaneous ...................................................................................................... 117

Part III Development Tools ................................................................... 119

Chapter 5 MCU Programming Tools ............................................................................ 121

HT-IDE Development Environment ............................................................................ 121

Holtek In-Circuit Emulator - HT-ICE .......................................................................... 122

HT-ICE Interface Card ......................................................................................... 122

OTP Programmer................................................................................................. 123

OTP Adapter Card .............................................................................................. 123

System Configuration ................................................................................................ 123

HT-ICE Interface Card Settings.............................................................................124

Installation .................................................................................................................. 125

System Requirement ........................................................................................... 125

Hardware Installation .......................................................................................... 125

Software Installation ............................................................................................ 125

Chapter 6 Quick Start ................................................................................................... 129

Step 1 - Create a New Project ............................................................................ 129

Step 2 - Add Source Program Files to the Project ............................................. 129

Step 3 - Build the Project .................................................................................... 129

Step 4 - Programming the OTP Device .............................................................. 129

Step 5 - Transmit Code to Holtek ....................................................................... 130

Page 6

Contents

Appendix ................................................................................................. 131

Appendix A Device Characteristic Graphics .............................................................. 133

Appendix B Package Information ................................................................................ 143

Page 7

A/D Type MCU

Page 8

Preface

Since the founding of the company, sign efforts in the area of microcontroller development. Although supplying a wide range of semi conductor devices, the microcontroller category has always been a key product category within the Holtek range, and one which will continue to expand as their devices increase in functionality and maturity. By capitalizing on the substantial accumulated skills within its dedicated microcontroller development department, Holtek has been able to release a comprehensive range of high quality low-cost microcontroller devices for a wide range of application areas. Many important applications need to process analog signals such as those which interface to external sensors. All of these applications require analog to digital signal conversion by an A/D converter before they can be processed by the microcontroller. To address these needs, oped its range of A/D microcontrollers, which in addition to having all the features and functions of the I/O range of devices, also include integrated multi-channel A/D converters of varying resolution and channel capacity. The inclusion of PWM functions and an I the features and application possibilities of the A/D series of microcontrollers.

This handbook is divided into three parts for user convenience. Most details regarding general datasheet information and device specification is located within Part I. Information related to microcontroller programming such as device instruction set, instruction definition, and assembly language directivesis found within Part II. Part III relates to the Holtek rangeof Development Tools where information can be found on their installation and use.

By compiling all relevant data together in one handbook, we hope users of the Holtek range of A/D Type microcontroller devices will have at their fingertips a useful, complete and simple means to ef ficiently implementtheir microcontroller applications. Holtek¢s efforts to combine information on de vice specifications, programming and development tools into one publication have produced a handbook which with careful use by the user should result in trouble free designs and the maxi mum benefit being gained from the many features of Holtek microcontroller devices. We welcome feedback and comments from our customers regarding further improvements.

Semiconductor Inc. has concentrated much of its de

Holtek

C interface further enhance

has devel

vii

Page 9

A/D Type MCU

viii

Page 10

Part I

Part I Microcontroller Profile

Microcontroller Profile

Page 11

A/D Type MCU

Page 12

Chapter 1

Hardware Structure

This section is the main datasheet section of the A/D Type microcontroller handbook and contains all the parameters and information related to the hardware. The information contained provides de signers with details on all the main hardware features of the A/D Type microcontroller range which together with the programming section contains the information to enable swift and successful im plementation of user microcontroller applications. By proper consultation of the relevant parts of this section, users can ensure that they make the most efficient use of the flexible and multi-function features within the A/D Type microcontroller series.

Introduction

The HT46R47/HT46C47, HT46R22/HT46C22, HT46R23/HT46C23 and HT46R24/HT46C24 form the series of 8-bit high performance RISC architecture microcontrollers, designed especially for applications that interface directly to analog signals, such as those from sensors. All devices include an integrated multi-channel Analog to Digital Converter in addition to one or more Pulse Width Modulation outputs. Device flexibility is enhanced with the usual features of the other microcontroller range such as HALT and wake-up functions, oscillator options, programmable frequency divider etc. These features combine to ensure applications require a minimum of external components and therefore reduce overall product costs. Having the benefits of integrated A/D and PWM functions, in addition to the advantages of low power consumption, high performance, I/O flexibility, as well as low cost, these devices have the versatility to suit a wide range of application possibilities such as sensor signal processing, motor driving, industrial control, consumer prod ucts, subsystem controllers, etc. Many features are common to all devices however, they differ in areas such as I/O pin count, RAM and ROM capacity, timer number and size, A/D channels, PWM outputs, etc.

Chapter 1 Hardware Structure

The HT46R47, HT46R22, HT46R23 and HT46R24 are OTP devices offering the advantages of easy and effective program updates, using the Holtek range of development and programming tools. These devices provide the designer with the means for fast and low cost product develop ment cycles. However, for applications that are at a mature state in their design process, the HT46C47, HT46C22, HT46C23 and HT46C24 mask version devices offer a complementary de vice for products with high volume and low cost demands. Fully pin and functionally compatible with their OTP sister devices, such mask version devices provide the ideal substitute for products which have gone beyond their development cycle and are facing cost down demands.

Page 13

Features

Technology Features

High-performance RISC Architecture

Low-power Fully Static CMOS Design

Operating Voltage:

=4MHz: 2.2V~5.5V

SYS

=8MHz: 3.3V~5.5V

SYS

Power Consumption:

2mA Typical at 5V 4MHz (for Crystal Oscillator with ADC Disabled) Maximum of 1mA Standby Current at 3V with WDT Disabled

Temperature Range:

Operating Temperature -40°Cto85°C (Industrial Grade) Storage Temperature -50°Cto125°C

Kernel Features

Program Memory:

2K´14 OTP/Mask ROM (HT46R47/HT46C47, HT46R22/HT46C22) 4K´15 OTP/Mask ROM (HT46R23/HT46C23) 8K´16 OTP/Mask ROM (HT46R24/HT46C24)

Data Memory:

64´8 SRAM (HT46R47/HT46C47, HT46R22/HT46C22) 192´8 SRAM (HT46R23/HT46C23) 384´8 SRAM (HT46R24/HT46C24)

· Table Read Function

· Multi-level Hardware Stack:

6-level (HT46R47/HT46C47, HT46R22/HT46C22) 8-level (HT46R23/HT46C23) 16-level (HT46R24/HT46C24)

· Direct and Indirect Data Addressing Mode

· Bit Manipulation Instructions

63 Powerful Instructions

Most Instructions Implemented in 1 Machine Cycle

A/D Type MCU

Peripheral Features

From 13 to 40 Bidirectional I/O with Pull-high Options

Multi-channel 9 or 10-bit A/D Converter

Pulse Width Modulator Outputs

Port A Wake-up Options

External Interrupt Input

Event Counter Input

Full Timer Functions with Prescaler and Interrupt

Watchdog Timer (WDT)

Page 14

HALT and Wake-up Feature for Power Saving Operation

PFD Output

On-chip Crystal and RC Oscillator

Low Voltage Reset (LVR) Feature for Brown-out Protection

Programming Interface with Code Protection

Mask Version Devices Available for High Volume Production

Full Suite of Supported Hardware and Software Tools Available

Selection Table

The series of A/D microcontrollers include a comprehensive range of features, some of which are standard and some of which are device dependent. Most features are common to all devices, the main feature distinguishing them are Program Memory, Data Memory capacity, I/O count, timer functions, A/D channels and PWM outputs. To assist users in their selection of the most appropri ate device for their application, the following table, which summarizes the main features of each device, is provided.

C Interface (excluding HT46R47/HT46C47)

Chapter 1 Hardware Structure

Part No.

HT46R47 HT46C47

HT46R22 HT46C22

HT46R23 HT46C23

HT46R24 HT46C24

Note

Part numbers including ²C² are mask version devices while ²R² are OTP devices.

VDD

2.2V~

5.5V

2.2V~

5.5V

2.2V~

5.5V

2.2V~

5.5V

Program

Memory

2K´14 64´8

4K´15

8K´16 384´8

Data

Memory

192x8

I/O Timer Interrupt I

8-bit´1

16-bit´1

16-bit´2

C A/D

¾ 9-bit´4 8-bit´1

Ö 9-bit´8 8-bit´1

Ö 10-bit´8

PWM

8-bit´1

8-bit´2

8-bit´4

Stack

Package

Types

18DIP, 18SOP

24SKDIP,

24SOP

24SKDIP,

24SOP

28SKDIP,

28SOP

28SKDIP,

28SOP

48SSOP

Page 15

Block Diagram

The following block diagram illustrates the main functional blocks of the A/D Type microcontroller series of devices.

A/D Type MCU

P r o g r a m M e m o r y

L o o k - u p

R e g i s t e r

C o n f i g .

R e g i s t e r

A d d r e s s D e c o d e r

L o o k - u p

T a b l e

I n t e r r u p t

C i r c u i t

C interface. The Bank Pointer

T a b l e

P o i n t e r

C o n f i g .

R e g i s t e r

P r o g r a m C o u n t e r

S t a c k

S t a c k P o i n t e r

S y s t e m R C /

X ' t a l O s c i l l a t o r

W D T

O s c i l l a t o r

R e s e t &

L V R

A / D

I2C

C o n v e r t e r

Note

This block diagram represents the OTP devices, for the mask device there is no Device Pro

M e m o r y

C o n f i g .

R e g i s t e r

T i m i n g

G e n e r a t o r

D a t a

I n s t r u c t i o n

D e c o d e r

A d d r e s s D e c o d e r

U X

B a n k

P o i n t e r

C o n f i g .

P W M

R e g i s t e r

M e m o r y

P o i n t e r

W a t c h d o g

T i m e r

I n s t r u c t i o n

R e g i s t e r

M U X

S h i f t e r

C o n f i g .

R e g i s t e r

A C C

A L U

T i m e r ( s ) /

P F D

C o u n t e r

gramming Circuitry. The HT46R47/HT46C47 does not contain an I only exists in the HT46R24/HT46C24.

P o r t s

T o P r o g r a m

M e m o r y

C o n f i g u r a t i o n

O p t i o n

D e v ic e

P r o g r a m m i n g

I / O

C i r c u i t r y

Page 16

Pin Assignment

Chapter 1 Hardware Structure

P A 3 / P F D

P B 3 / A N 3

P B 2 / A N 2

P B 1 / A N 1

P B 0 / A N 0

P A 2

P A 1

P A 0

V S S

H T 4 6 R 4 7 / H T 4 6 C 4 7

1 8 D I P - A / S O P - A

P B 5 / A N 5

P B 4 / A N 4

P A 3 / P F D

P B 3 / A N 3

P B 2 / A N 2

P B 1 / A N 1

P B 0 / A N 0

P A 2

P A 1

P A 0

1 0

V S S

1 1

P C 0

1 2

P C 1

1 3

P C 2

1 4

H T 4 6 R 2 3 / H T 4 6 C 2 3 2 8 S K D I P - A / S O P - A

1 8

1 7

1 6

1 5

1 4

1 3

1 2

1 1

1 0

2 8

2 7

2 6

2 5

2 4

2 3

2 2

2 1

2 0

1 9

1 8

1 7

1 6

1 5

P A 4 / T M R

P A 5 / I N T

P A 6

P A 7 O S C 2

O S C 1

V D D

R E S

P D 0 / P W M

P B 6 / A N 6

P B 7 / A N 7

P A 4 / T M R

P A 5 / I N T

P A 6 / S D A

P A 7 / S C L

O S C 2

O S C 1

V D D

R E S

P D 1 / P W M 1

P D 0 / P W M 0

P C 4

P C 3

P B 5 / A N 5

P B 4 / A N 4

P A 3 / P F D

P B 3 / A N 3

P B 2 / A N 2

P B 1 / A N 1

P B 0 / A N 0

P A 2

P A 1

P A 0

1 0

V S S

1 1

P C 0

1 2

H T 4 6 R 2 2 / H T 4 6 C 2 2

2 4 S K D I P - A / S O P - A

P B 5 / A N 5

P B 4 / A N 4

P A 3 / P F D

P B 3 / A N 3

P B 2 / A N 2

P B 1 / A N 1

P B 0 / A N 0

P A 2

P A 1

P A 0

1 0

V S S

1 1

P C 0

1 2

P C 1

1 3

P C 2

1 4

H T 4 6 R 2 4 / H T 4 6 C 2 4 2 8 S K D I P - A / S O P - A

P B 6 / A N 6

2 4

P B 7 / A N 7

2 3

P A 4 / T M R

2 2

P A 5 / I N T

2 1

P A 6 / S D A

2 0

P A 7 / S C L

1 9

O S C 2

1 8

O S C 1

1 7

V D D

1 6

R E S

1 5

P D 0 / P W M

1 4

P C 1

1 3

P B 6 / A N 6

2 8

P B 7 / A N 7

2 7

P A 4

2 6

P A 5 / I N T

2 5

P A 6 / S D A

2 4

P A 7 / S C L

2 3

O S C 2

2 2

O S C 1

2 1

V D D

2 0

R E S

1 9

P D 1 / P W M 1 / T M R 1

1 8

P D 0 / P W M 0

1 7

P C 4

1 6

P C 3

1 5

P B 5 / A N 5

P B 4 / A N 4

P A 3 / P F D

P B 3 / A N 3

P B 2 / A N 2

P B 1 / A N 1

P B 0 / A N 0

P A 2

P A 1

P A 0

1 0

V S S

1 1

P C 0

1 2

H T 4 6 R 2 3 / H T 4 6 C 2 3

2 4 S K D I P - A / S O P - A

P B 5 / A N 5

P B 4 / A N 4

P A 3 / P F D

P B 3 / A N 3

P B 2 / A N 2

P B 1 / A N 1

P B 0 / A N 0

T M R 0

P A 2

P A 1

P A 0

1 0

N C

1 1

P F 3

1 2

P F 2

1 3

P F 1

1 4

P D 7

1 5

P D 6

1 6

P D 5

1 7

P D 4

1 8

V S S

1 9

P F 0

2 0

2 1

P C 0

2 2

P C 1

2 3

P C 2

2 4

H T 4 6 R 2 4 / H T 4 6 C 2 4

4 8 S S O P - A

2 4

2 3

2 2

2 1

2 0

1 9

1 8

1 7

1 6

1 5

1 4

1 3

4 8

4 7

4 6

4 5

4 4

4 3

4 2

4 1

4 0

3 9

3 8

3 7

3 6

3 5

3 4

3 3

3 2

3 1

3 0

2 9

2 8

2 7

2 6

2 5

P B 6 / A N 6

P B 7 / A N 7

P A 4 / T M R

P A 5 / I N T

P A 6 / S D A

P A 7 / S C L

O S C 2

O S C 1

V D D

R E S

P D 0 / P W M

P C 1

P B 6 / A N 6

P B 7 / A N 7

P A 4

P A 5 / I N T

P A 6 / S D A

P A 7 / S C L

P F 4

P F 5

P F 6

P F 7

O S C 2

O S C 1

V D D

R E S

T M R 1

P D 3 / P W M 3

P D 2 / P W M 2

P D 1 / P W M 1

P D 0 / P W M 0

P C 7

P C 6

P C 5

P C 4

P C 3

Note The pin compatibility features of the microcontroller SKDIP/SOP packages allow for straightfor

ward upgrading to devices of higher functionality with minimal changes to application hardware.

Page 17

Pin Description

HT46R47/HT46C47

Pin Name I/O

PA0~PA2 PA3/PFD PA4/TMR PA5/INT PA6~PA7

PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3

PD0/PWM I/O

OSC1 OSC2

RES I

VDD

VSS

Configuration

Option

Pull-high Wake-up

I/O

PA3 or

PFD

I/O Pull-high

Pull-high

I/O or

PWM

Crystal or RC

¾¾

A/D Type MCU

Description

Bidirectional 8-bit input/output port. Each individual bit on this port can be configured as a wake-up input by a configuration option. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. A configuration option deter mines which bits on the port have pull-high resistors. Pins PA3, PA4 and PA5 are pin-shared with PFD, TMR and INT respectively.

Bidirectional 4-bit input/output port. Software instructions de termine ifthe pin is a CMOS output or Schmitt Trigger input. A configuration option determines which bits on the port have pull-high resistors. PB is pin-shared with the A/D input pins. The A/D inputs are selected via software instructions. Once selected as an A/D input, the I/O function and pull-high resis tor functions are disabled automatically.

Bidirectional 1-bit input/output port. Software instructions de termine ifthe pin is a CMOS output or Schmitt Trigger input. A configuration option determines if this pin has a pull-high re sistor. The PWM output is pin-shared with pin PD0 selected via configuration option.

OSC1, OSC2are connected to an external RC network or external crystal (determined by configuration option) for the internal system clock. For external RC system clock operation, OSC2 is an output pin for 1/4 system clock.

Schmitt Trigger reset input. Active low.

Positive power supply

Negative power supply, ground

Note 1. Each pin on PAcan be programmed through a configuration option to have a wake-up function.

2. Each pin on each port can be individually configured to have a pull-high resistor.

Page 18

HT46R22/HT46C22

Pin Name I/O

PA0~PA2 PA3/PFD PA4/TMR PA5/INT PA6/SDA PA7/SCL

PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4/AN4 PB5/AN5 PB6/AN6 PB7/AN7

PC0~PC1 I/O Pull-high

PD0/PWM I/O

OSC1 OSC2

RES I

VDD

VSS

Configuration

Option

Pull-high

Wake-up

PA3 or PFD

I/O

PA6/PA7 or

SDA/SCL

I/O Pull-high

Pull-high

I/O or PWM

Crystal or RC

¾¾

Chapter 1 Hardware Structure

Description

Bidirectional 8-bit input/output port. Each individual bit on this port can be configured as a wake-up input by a configu ration option. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. A configuration op tion determines which bits on the port have pull-high resis tors. Pins PA3, PA4 and PA5 are pin-shared with PFD, TMR and INT pin-shared with SDA and SCL respectively and are used to implement the I

Bidirectional 8-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt Trigger in put. A configuration option determines if all pins on the port have pull-high resistors. PB is pin-shared with the A/D input pins. The A/D inputs are selected via software instructions. Once selected as an A/D input, the I/O function and pull-high resistor functions are disabled automatically.

Bidirectional 1-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt Trigger in put. A configuration option determines if this pin has a pull-high resistor. The PWM output is pin-shared with pin PD0 selected via configuration option.

OSC1, OSC2 are connected to an external RC network or external crystal (determined by configuration option) for the internal system clock. For external RC system clock operation, OSC2 is an output pin for 1/4 system clock.

Schmitt Trigger reset input. Active low.

Positive power supply

Negative power supply, ground

respectively. Pins PA6 and PA7 are

C bus function.

Note 1. Each pin on PA can be programmed through a configuration option to have a wake-up function.

2. Individual pins on PA can be selected to have a pull-high resistors. However, individual pins on Port Band Port C cannot be selected to have pull-high resistors. If the pull-high configuration is chosen for a particular PB or PC port, then all input pins on this port will be connected to pull-high resistors.

Page 19

HT46R23/HT46C23

Pin Name I/O

PA0~PA2 PA3/PFD PA4/TMR PA5/INT PA6/SDA PA7/SCL

PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4/AN4 PB5/AN5 PB6/AN6 PB7/AN7

PC0~PC4 I/O Pull-high

PD0/PWM0 PD1/PWM1

OSC1 OSC2

RES I

VDD

VSS

Configuration

Option

Pull-high

Wake-up

PA3 or PFD

I/O

PA6/PA7 or

SDA/SCL

I/O Pull-high

Pull-high

I/O

I/O or PWM

Crystal or RC

¾¾

A/D Type MCU

Description

Bidirectional 8-bit input/output port. Software instructions de termine ifthe pin is a CMOS output or Schmitt Trigger input. A configuration option determines if all pins on the port have pull-high resistors. PB is pin-shared with the A/D input pins. The A/D inputs are selected via software instructions. Once selected as an A/D input, the I/O function and pull-high resis tor functions are disabled automatically.

Bidirectional 5-bit input/output port. Software instructions de termine ifthe pin is a CMOS output or Schmitt Trigger input. A configuration option determines if all pins on this port have pull-high resistors.

Bidirectional 2-bit input/output port. Software instructions de termine ifthe pin is a CMOS output or Schmitt Trigger input. A configuration option determines if both pins on this port have pull-high resistors. The PWM0 output is pin-shared with pin PD0 and the PWM1 output is pin-shared with PD1, selected via configuration options.

OSC1, OSC2 are connected to an external RC network or external crystal (determined by configuration option) for the internal system clock. For external RC system clock operation, OSC2 is an output pin for 1/4 system clock.

Schmitt Trigger reset input. Active low.

Positive power supply

Negative power supply, ground

C bus function.

respec

Note 1. Each pin on PA can be programmed through a configuration option to have a wake-up function.

2. Individual pins on PA can be selected to have a pull-high resistors. However, individual pins on

Port B, Port C and Port D cannot be selected to have pull-high resistors. If the pull-high configuration is chosen for a particular PB, PC or PD port, then all input pins on this port will be connected to pull-high resistors.

3. The pin description table is based on the 28-pin device. Due to packaging limitations some pins

may not exist on the 24-pin package.

Page 20

HT46R24/HT46C24

Pin Name I/O

PA0~PA2 PA3/PFD PA4 PA5/INT PA6/SDA PA7/SCL

PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4/AN4 PB5/AN5 PB6/AN6 PB7/AN7

PC0~PC7 I/O Pull-high

PD0/PWM0 PD1/PWM1 PD2/PWM2 PD3/PWM3 PD4~PD7

PF0~PF7 I/O Pull-high

TMR0 I

TMR1 I

OSC1 OSC2

RES I

VDD

VSS

Configuration

Option

Pull-high

Wake-up

PA3 or PFD

I/O

PA6/PA7 or

SDA/SCL

I/O Pull-high

Pull-high

I/O

I/O or PWM

Crystal or RC

¾¾

Chapter 1 Hardware Structure

Description

Bidirectional 8-bit input/output port. Each individual bit on this port can be configured as a wake-up input by a configu ration option. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. A configuration op tion determines which bits on the port have pull-high resis tors. Pins PA3 and PA5 are pin-shared with PFD and INT respectively. Pins PA6 and PA7 are pin-shared with SDA and SCLrespectively and are used to implement the I function.

Bidirectional 8-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt Trigger in put. A configuration option determines which bits on the port have pull-high resistors. PB is pin-shared with the A/D input pins. The A/D inputs are selected via software instructions. Once selected as an A/D input, the I/O function and pull-high resistor functions are disabled automatically.

Bidirectional 8-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt Trigger in put. A configuration option determines if all pins on this port have pull-high resistors. The PWM0/PWM1/PWM2 and PWM3 output pins are pin-shared with pins PD0/PD1/PD2 and PD3 respectively, selected via configuration options.

Timer/Event Counter 0 Schmitt Trigger input. No pull-high resistor connected.

Timer/Event Counter 1 Schmitt Trigger input. No pull-high resistor connected.

OSC1, OSC2 are connected to an external RC network or external crystal (determined by configuration option) for the internal system clock. For external RC system clock opera tion, OSC2 is an output pin for 1/4 system clock.

Schmitt Trigger reset input. Active low.

Positive power supply

Negative power supply, ground

C bus

Page 21

Note 1. Each pin on PA can be programmed through a configuration option to have a wake-up function.

2. Individual pins on PA and PB can be selected to have pull-high resistors. However, individual pins on Port C, Port D and Port F cannot be selected to have pull-high resistors. If the pull-high configuration is chosen for a particular PC, PD or PF port, then all input pins on the corresponding port will have pull-high resistors connected.

3. The pin description table is based on the 48-pin package. Due to packaging limitations some

I/O pins may not exist on the 28-pin package. The TMR0 external pin is not available on the 28-pin package. The TMR1 pin is available on the 28-pin package as the pin-shared PD1/PWM1/TMR1.

Absolute Maximum Ratings

Supply Voltage.............................................................................................VSS-0.3V to VSS+6.0V

Input Voltage ...............................................................................................V

Storage Temperature.............................................................................................-50°Cto125°C

Operating Temperature............................................................................................-40°Cto85°C

These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to ex treme conditions may affect device reliability.

A/D Type MCU

-0.3V to VDD+0.3V

D.C. Characteristics

Symbol Parameter

DD1

DD2

DD3

STB1

STB2

Operating Voltage

Operating Current (Crystal OSC)

Operating Current (RC OSC)

Operating Current (Crystal OSC, RC OSC)

Standby Current (WDT Enabled)

Standby Current (WDT and A/D Disabled)

Test Conditions

Conditions

SYS

=4MHz

=8MHz

3V No load,

=4MHz

SYS

ADC off

3V No load,

=4MHz

SYS

ADC off

No load,

=8MHz

SYS

ADC off

No load, system HALT

Ta=25°C

Min. Typ. Max. Unit

2.2

3.3

¾¾

5.5 V

0.6 1.5 mA

24mA

0.8 1.5 mA

2.5 4 mA

48mA

Page 22

Chapter 1 Hardware Structure

Symbol Parameter

ADC

Input Low Voltage for I/O Ports,

IL1

TMR, TMR0, TMR1, INT

Input HighVoltage for I/O Ports,

IH1

TMR, TMR0, TMR1, INT

Input Low Voltage (RES)

IL2

Input High Voltage (RES)

IH2

Low Voltage Reset

LVR

I/O Port Sink Current

I/O Port Source Current

Pull-high Resistance

A/D Input Voltage

A/D Conversion Integral

Non-Linearity Error

Additional Power Consumption if A/D Converter is Used

Test Conditions

Conditions

¾¾

=0.1V

=0.9V

¾¾

Min. Typ. Max. Unit

0.7V

0.9V

2.7 3 3.3 V

10 20

-2 -4 ¾

-5 -10 ¾

20 60 100

10 30 50

0.3V

0.4V

¾¾ ¾±0.5 ±1

0.5 1 mA

1.5 3 mA

LSB

Page 23

A/D Type MCU

A.C. Characteristics

Symbol Parameter

SYS

TIMER

WDTOSC

RES

SST

LVR

INT

ADC

ADCS

IIC

= 1/f

SYS

System Clock

Timer I/P Frequency (TMR)

Watchdog Oscillator Period

External Reset Low Pulse Width

System Start-up Timer Period

Low Voltage Width to Reset

Interrupt Pulse Width

A/D Clock Period

A/D Conversion Time

A/D Sampling Time

I2C Bus Clock Period

Test Conditions

Conditions

2.2V~5.5V 400

3.3V~5.5V 400

2.2V~5.5V 0

3.3V~5.5V 0

¾¾

Wake-up from HALT

¾¾

Min. Typ. Max. Unit

45 90 180

32 65 130

¾¾ms

1024

¾¾

¾¾ms

¾¾ ¾76¾

¾¾ ¾32¾

Connect to external

pull-high resistor 2kW

¾¾

Ta=25°C

4000 kHz

8000 kHz

4000 kHz

8000 kHz

SYS

Page 24

System Architecture

A key factor in the high performance features of the Holtek range of A/D Type microcontrollers is at tributed to the internal system architecture. The range of devices take advantage of the usual fea tures found within RISC microcontrollers providing increased speed of operation and enhanced performance. The pipelining scheme is implemented in such a way that instruction fetching and in struction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all operations of the instruction set. It carries out arithmetic operations, logic operations, rotation, increment, dec rement, branch decisions, etc. The internal data path is simplified by moving data through the Ac cumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to pro vide a functional I/O and A/D control system with maximum reliability and flexibility. This makes these devices suitable for low cost, high-volume production for controller applications requiring from 2K up to 8K words of program memory and from 64 to 384 bytes of data storage.

Clocking and Pipelining

The mainsystem clock, derived from either a Crystal/Resonator or RC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecu tive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the con tents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute.

Chapter 1 Hardware Structure

Note

When the RC oscillator is used, OSC2 is freed for use as a T1 phase clock synchronizing pin. This T1 phase clock has a frequency of f

O s c i l l a t o r C l o c k

( S y s t e m C l o c k )

P h a s e C l o c k T 1

P h a s e C l o c k T 2

P h a s e C l o c k T 3

P h a s e C l o c k T 4

P r o g r a m C o u n t e r

P i p e l i n i n g

F e t c h I n s t . ( P C )

E x e c u t e I n s t . ( P C - 1 )

/4 with a 1:3 high/low duty cycle.

SYS

P C P C + 1 P C + 2

F e t c h I n s t . ( P C + 1 )

E x e c u t e I n s t . ( P C )

F e t c h I n s t . ( P C + 2 )

E x e c u t e I n s t . ( P C + 1 )

System Clocking and Pipelining

Page 25

A/D Type MCU

For instructions involving branches, such as jump or call instructions, two machine cycles are re quired to complete instruction execution. An extra cycle is required as the program takes one cy cle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in tim ing sensitive applications

D E L A Y :

M O V A , [ 1 2 H ]

C A L L D E L A Y

C P L [ 1 2 H ]

N O P

F e t c h I n s t . 1 E x e c u t e I n s t . 1

F e t c h I n s t . 2

E x e c u t e I n s t . 2

F e t c h I n s t . 3

F l u s h P i p e l i n e

F e t c h I n s t . 6 E x e c u t e I n s t . 6

F e t c h I n s t . 7

Program Counter

During program execution, the Program Counter is used to keep track of the address of the next in struction to be executed. It is automatically incremented by one each time an instruction is exe cuted except for instructions such as JMP or CALL that demand a jump to a non-consecutive Program Memory address. For the A/D series of microcontrollers, note that the Program Counter width varies with the Program Memory capacity depending upon which device is selected. How ever, it must be noted that only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by user.

When executing instructions requiring jumps to non-consecutive addresses such as a jump in struction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the Program Counter. For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained.

The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and is a readable and writable register. By transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted.

Note

The lower byte of the Program Counter is fully accessible under program control. The use of the PCL might cause program branching, so an extra cycle is needed to pre-fetch. Further information on the PCL register can be found in the Special Function Register section.

Page 26

Chapter 1 Hardware Structure

Mode

Initial Reset 0 0 0 0000000000

External Interrupt 0 0 0 0000000100

Timer/Event Counter 0 Overflow 0 0 0 0000001000

Timer/Event Counter 1 Overflow (HT46R24/HT46C24 only)

A/D Converter Interrupt (except HT46R24/HT46C24)

A/D Converter Interrupt (HT46R24/HT46C24 only)

C Bus Interrupt

I (except HT46R24/HT46C24)

C Bus Interrupt

I (HT46R24/HT46C24 only)

Skip Program Counter + 2

Loading PCL PC12 PC11 PC10 PC9 PC8 @7 @6 @5 @4 @3 @2 @1 @0

Jump, Call Branch #12 #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0

Return from Subroutine S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

0 0 0 0000001100

0 0 0 0000010000

0 0 0 0000010100

Program Counter Bits

Note 1. PC12~PC8: Current Program Counter bits

2. @7~@0: PCL bits

3. #12~#0: Instruction code bits

4. S12~S0: Stack register bits

5. For the HT46R24/HT46C24, the Program Counter is 13 bits wide, i.e. from b12~b0.

6. For the HT46R23/HT46C23, since its Program Counter is 12 bits wide, the b12 column in the table is not applicable.

7. For the HT46R47/HT46C47, HT46R22/HT46C22, since its Program Counter is 11 bits wide, the b11 and b12 columns in the table are not applicable.

8. The Timer/Event Counter 1 Overflow row is available only for the HT46R24/HT46C24.

9. For the HT46R47/HT46C47, HT46R22/HT46C22 and HT46R23/HT46C23 the Timer/Event Counter 0 represents the single timer, known as TMR.

Page 27

A/D Type MCU

Stack

This is a special part of the memory which is used to save the contents of the Program Counter only. The stack can have between 6, 8 or 16 levels depending upon which deviceis selected and is neither partof the data nor part of the program space, and is neither readable nor writable. The acti vated level is indexed by the stack pointer (SP) and is neither readable nor writeable. At a subrou tine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the Program Counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack.

If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the stack pointer is decremented (by RET or RETI), the interrupt will be serviced. This feature prevents stack overflow allowing the program mer to use the structure more easily. However, when the stack is full, a CALL subroutine instruc tion can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching.

P r o g r a m C o u n t e r

T o p o f S T A C K

S t a c k

P o i n t e r

B o t t o m o f S T A C K

1. For the HT46R47/HT46C47 and HT46R22/HT46C22, N=6, i.e. 6 levels of stack available.

Note

S t a c k L e v e l 1

S t a c k L e v e l 2

S t a c k L e v e l 3

S t a c k L e v e l N

P r o g r a m

M e m o r y

2. For the HT46R23/HT46C23, N=8, i.e. 8 levels of stack available.

3. For the HT46R24/HT46C24, N=16, i.e. 16 levels of stack available.

Arithmetic and Logic Unit - ALU

The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or opera tions may result in carry, borrow or other status changes, the status register will be correspond ingly updated to reflect these changes. The ALU supports the following functions:

Arithmetic operations ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA

Logic operations AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA

Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC

Increment and Decrement INCA, INC, DECA, DEC

Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI

Page 28

Program Memory

The Program Memory is the location where the user code or program is stored. For microcontrollers, two types of Program Memory are usually supplied. The first type is the OneTime Programmable (OTP) Memory where users can program their application code into the de vice. Devices with OTP memory are denoted by having an ²R² within their device name. By using the appropriate programming tools, OTP devices offer users the flexibility to freely develop their applications which may be useful during debug or for products requiring frequent upgrades or pro gram changes. OTP devices are also applicable for use in applications that require low or medium volume production runs. The other type of memory is the mask ROM memory, denoted by having a ²C²within the device name. These devices offer the most cost effective solutions for high volume products.

Organization

The Program Memory has a capacity of 2K by 14 to 8K by 16 bits depending upon which device is selected. The Program Memory is addressed by the Program Counter and also contains data, ta ble information and interrupt entries. Table data, which can be setup in any location within the Pro gram Memory, is addressed by separate table pointer registers.

The following diagram shows the Program Memory for the A/D Type microcontroller series.

Chapter 1 Hardware Structure

0 0 0 H

0 0 4 H

0 0 8 H

0 0 C H

0 1 0 H

0 1 4 H

3 F F H

4 0 0 H

7 F F H

8 0 0 H

F F F H

1 0 0 0 H

1 F F F H

H T 4 6 R 4 7 H T 4 6 C 4 7

I n i t i a l i z a t i o n

V e c t o r

E x t e r n a l

I n t e r r u p t V e c t o r

T i m e r / C o u n t e r

I n t e r r u p t V e c t o r

A / D C o n v e r t e r

I n t e r r u p t V e c t o r

H T 4 6 R 2 2 H T 4 6 C 2 2

I n i t i a l i z a t i o n

V e c t o r

E x t e r n a l

I n t e r r u p t V e c t o r

T i m e r / C o u n t e r

I n t e r r u p t V e c t o r

A / D C o n v e r t e r

I n t e r r u p t V e c t o r

I2C B u s

I n t e r r u p t V e c t o r

1 4 b i t s1 4 b i t s

H T 4 6 R 2 3 H T 4 6 C 2 3

I n i t i a l i z a t i o n

V e c t o r

E x t e r n a l

I n t e r r u p t V e c t o r

T i m e r / C o u n t e r

I n t e r r u p t V e c t o r

A / D C o n v e r t e r

I n t e r r u p t V e c t o r

C B u s

I n t e r r u p t V e c t o r

H T 4 6 R 2 4 H T 4 6 C 2 4

I n i t i a l i z a t i o n

V e c t o r

E x t e r n a l

I n t e r r u p t V e c t o r

T i m e r / C o u n t e r 0

I n t e r r u p t V e c t o r

T i m e r / C o u n t e r 1

I n t e r r u p t V e c t o r

A / D C o n v e r t e r

I n t e r r u p t V e c t o r

I2C B u s

I n t e r r u p t V e c t o r

1 6 b i t s1 5 b i t s

N o t I m p l e m e n t e d

Page 29

A/D Type MCU

Special Vectors

Within the Program Memory, certain locations are reserved for special usage such as reset and in terrupts.

Location 000H

This vector is reserved for use by the chip reset for program initialization. After a chip reset is ini tiated, the program will jump to this location and begin execution.

Location 004H

This vector is used by the external interrupt. If the external interrupt pin on the device goes low, the program will jump to this location and begin execution if the external interrupt is enabled and the stack is not full.

Location 008H

This internal vector is used by the Timer/Event Counter. If a counter overflow occurs, the pro gram will jump to this location and begin execution if the timer interrupt is enabled and the stack is not full. For the HT46R24/HT46C24 devices, which has dual timers, this timer is known as Timer/Event Counter 0 or TMR0, for the other devices the timer is known as TMR.

Location 00CH

With the exception of the HT46R24/HT46C24 devices, this internal vector is used by the A/D converter. When an A/D conversion cycle is complete, the program will jump to this location and begin execution if the A/D interrupt is enabled and the stack is not full. For the HT46R24/HT46C24 devices, this internal vector is used by its Timer/Event Counter 1. If a TMR1 counter overflow occurs, the program will jump to this location and begin execution if the internal interrupt is enabled and the stack is not full.

Location 010H

With the exception of the HT46R47/HT46C47 and HT46R24/HT46C24 devices, this internal vector is used by the I jump to this location and begin execution if the I

For the HT46R24/HT46C24 devices this internal vector is used by its A/D converter interrupt. When the A/D conversion cycle in the HT46R24/HT46C24 is complete, the program will jump to this location and begin execution if the A/D interrupt is enabled and the stack is not full.

· Location 014H

This vector, only available for the HT46R24/HT46C24 devices, is used by its I When the I

C bus of the HT46R24/HT46C24 requires data transfer, the program will jump to this

location and begin execution if the I

C bus interface. When the I2C bus requires data transfer, the program will

C interrupt is enabled and the stack is not full.

C interruptis enabled and the stack is not full.

C bus interface.

Look-up Table

Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, the table pointer must first be setup by placing the lower-order address of the look-up data to be retrieved in the Table Pointer Register TBLP. This register defines the lower 8-bit address of the look-up table. After setting up the table pointer, the table data can be retrieved from the current Program Memory page or last Program Memory page using the ²TABRDC [m]² or ²TABRDL [m]² instructions respectively. When these instructions are executed, the lower order table byte from the Program Memory will be transferred to the user de fined Data Memory register [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will be read as ²0².

Page 30

Chapter 1 Hardware Structure

The following diagram illustrates the addressing/data flow of the look-up table:

P r o g r a m C o u n t e r h i g h b y t e

T B L P

T B L H S p e c i f i e d b y [ m ]

H i g h b y t e o f t a b l e c o n t e n t s

Table Program Example

The following example shows how the table pointer and table data is defined and retrieved from the HT46R47A/D microcontroller. This example uses raw table datalocated in the last page which is stored there using the ORG statement. The value at this ORG statement is ²700² hex which re fers to the start address of the last page within the 2K Program Memory of the HT46R47 microcontroller. The table pointer is setup here to have an initial value of 06 hex. This will ensure that the first data read from the data table will be at the Program Memory address 706 hex or 6 locations after the start of the last page. Note that the value for the table pointer is ref erenced to the first address of the present page if the ²TABRDC [m]²instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH regis ter automatically when the ²TABRDL [m]² instruction is executed.

P r o g r a m

M e m o r y

L o w b y t e o f t a b l e c o n t e n t s

tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2

: :

mov a,06h ; initialize table pointer - note that this address

mov tblp,a ; to the last page or present page

: :

tabrdl tempreg1 ; transfers value in table referenced by table pointer

; is referenced

; to tempregl ; data at prog. memory address 706H transferred to ; tempreg1 and TBLH

dec tblp ; reduce value of table pointer by one

tabrdl tempreg2 ; transfers value in table referenced by table pointer

; to tempreg2 ; data at prog.memory address 705H transferred to ; tempreg2 and TBLH

; in this example the data ²1A² is transferred to ; tempreg1 and data ²0F² to register tempreg2 ; the value ²0² will be transferred to the high byte

: :

; register TBLH

org 700h ; sets initial address of last page (for HT46R47)

dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh

: :

Page 31

Note 1. PC12~PC8: Current Program Counter bits

Data Memory

A/D Type MCU

Because the TBLH register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use table read instruc tions. If using the table read instructions, the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is recom mended that simultaneous use of the table read instructions should be avoided. However, in situa tions where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions re quire two instruction cycles to complete their operation.

Instruction

TABRDC

TABRDL

2. @7~@0: Table Pointer TBLP bits

3. For the HT46R24/HT46C24, the Table address location is 13 bits, i.e. from b12~b0.

4. For the HT46R23/HT46C23, the Table address location is 12 bits, i.e. from b11~b0.

5. For the HT46R47/HT46C47 and HT46R22/HT46C22, the Table address location is 11 bits, i.e. from b10~b0.

The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. Divided into two sections, the first of these is an area of RAM where special function registers are located. These registers have fixed locations and are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. The second area of Data Memory is reserved for general purpose use. All locations within this area are read and write accessible under program control.

b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

[m] PC12 PC11 PC10 PC9 PC8 @7 @6 @5 @4 @3 @2 @1 @0

[m]11111@7@6@5@4@3@2@1@0

Table Location Bits

Organization

The two sections of Data Memory, the Special Purpose and General Purpose Data Memory are located at consecutive locations. All are implemented in RAM and are 8 bits wide but the length of each memory section is dictated by the type of microcontroller chosen. The start address of the Data Memory for all devices is the address 00H. The last Data Memory address is 7FH for the HT46R47/HT46C47 and HT46R22/HT46C22 devices, and FFH for the HT46R23/HT46C23 and HT46R24/HT46C24 devices. Registers which are common to all microcontrollers, such as ACC, PCL etc., have the same Data Memory address.

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Chapter 1 Hardware Structure

0 0 H

S p e c i a l P u r p o s e D a t a M e m o r y

3 F H 4 0 H

G e n e r a l P u r p o s e D a t a M e m o r y

7 F H / F F H

Note

Most of the Data Memory bits can be directly manipulated using the ²SET [m].i² and ²CLR [m].i² with the exception of a few dedicated bits. The Data Memory can also be accessed through the memory pointer register MP.

General Purpose Data Memory

All microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. It is this area of RAM memory that is known as General Purpose Data Memory. This area of Data Memory is fully accessible by the user program for both read and write operations. By using the ²SET [m].i² and ²CLR [m].i² instructions, individual bits can be set or reset under program control, giving the user a large range of flexibility for bit manipulation in the Data Memory.

H T 4 6 R 4 7 H T 4 6 C 4 7

4 0 H

7 F H

Note

The 384 bytes of General Purpose Data Memory in the HT46R24/HT46C24 are stored in two indi

H T 4 6 R 2 2 H T 4 6 C 2 2

4 0 H

7 F H

F F H

H T 4 6 R 2 3 H T 4 6 C 2 3

4 0 H

7 F H 8 0 H

4 0 H

7 F H 8 0 H

F F H

H T 4 6 R 2 4 H T 4 6 C 2 4

B a n k 0

B a n k 1

vidual memory banks. Before reading from or writing to the General Purpose Data Memory it is es sential to first ensure that the correct Data Memory bank is selected by setting up the Bank Pointer. Bank 1 can only be addressed indirectly using the memory pointer MP1 and indirect ad dressing register IAR1.

Page 33

A/D Type MCU

Special Purpose Data Memory

This area of Data Memory is where registers, necessary for the correct operation of the microcontroller, are stored. Most of the registers are both readable and writable but some are pro tected and are readable only, the details of which are located under the relevant Special Function Register section. Note that for locations that are unused, any read instruction to these addresses will return the value ²00H².

0 A H 0 B H 0 C H 0 D H 0 E H

1 A H 1 B H 1 C H 1 D H 1 E H

H T 4 6 R 4 7 H T 4 6 C 4 7

I A R

0 0 H

M P

0 1 H 0 2 H 0 3 H 0 4 H

A C C

0 5 H

P C L

0 6 H

T B L P

0 7 H

T B L H

0 8 H 0 9 H

S T A T U S

I N T C

T M R

T M R C 0 F H 1 0 H 1 1 H 1 2 H 1 3 H 1 4 H 1 5 H 1 6 H 1 7 H 1 8 H 1 9 H

1 F H 2 0 H 2 1 H 2 2 H 2 3 H 2 4 H 2 5 H 2 6 H 2 7 H 2 8 H 2 9 H

3 F H

P A

P A C

P B

P B C

P D

P D C

P W M

A D R L A D R H A D C R A C S R

H T 4 6 R 2 2 H T 4 6 C 2 2

I A R M P

A C C

P C L T B L P T B L H

S T A T U S

I N T C 0

T M R

T M R C

P A

P A C

P B

P B C

P C

P C C

P D

P D C P W M

I N T C 1

H A D R

H C R

H S R

H D R A D R L

A D R H A D C R A C S R

H T 4 6 R 2 3 H T 4 6 C 2 3

I A R 0

M P 0

I A R 1

M P 1

A C C

P C L T B L P T B L H

S T A T U S

I N T C 0 T M R H T M R L T M R C

P A

P A C

P B

P B C

P C

P C C

P D

P D C

P W M 0 P W M 1

I N T C 1

H A D R

H C R

H S R

H D R A D R L

A D R H A D C R A C S R

H T 4 6 R 2 4 H T 4 6 C 2 4

I A R 0 M P 0 I A R 1 M P 1

B P

A C C

P C L T B L P T B L H

S T A T U S

I N T C 0 T M R 0 H T M R 0 L T M R 0 C T M R 1 H T M R 1 L T M R 1 C

P A

P A C

P B

P B C

P C

P C C

P D

P D C P W M 0 P W M 1 P W M 2 P W M 3 I N T C 1

H A D R

H C R

H S R

H D R

A D R L A D R H A D C R A C S R

P F

P F C

S p e c i a l P u r p o s e D a t a M e m o r y

: U n u s e d

R e a d a s " 0 0 "

Page 34

Special Function Registers

To ensure successful operation of the microcontroller, certain internal registers are implemented in the Data Memory area. These registers ensure correct operation of internal functions such as timers, interrupts, etc. as well as external functions such as I/O data control and A/D converter op eration. The location of these registers within the Data Memory begins at the address 00H. Any un used Data Memory locations between these special function registers and the point where the General Purpose Memory begins is reserved for future expansion purposes, attempting to read data from these locations will return a value of 00H.

Indirect Addressing Registers - IAR, IAR0, IAR1

The method of indirect addressing allows data manipulation using memory pointers instead of the usual direct memory addressing method where the actual memory address is defined. Any action on the Indirect Addressing Registers will result in corresponding read/write operations to the mem ory location specified by the corresponding memory pointer. For the HT46R47/HT46C47 and HT46R22/HT46C22 devices, one Indirect Addressing Register, IAR, and one Memory Pointer, MP, is provided. For the HT46R23/HT46C23 and HT46R24/HT46C24 devices, two Indirect Ad dressing Registers, IAR0 and IAR1, and two Memory Pointers, MP0 and MP1, are provided. Note that these Indirect Addressing Registers are not physically implemented and that reading the Indi rect Addressing Registers indirectly will return a result of 00H and writing to the registers indirectly will result in no operation.

Memory Pointers - MP, MP0, MP1

For the HT46R47/HT46C47 and HT46R22/HT46C22 devices, one memory pointer known as MP is provided, whereas for the HT46R23/HT46C23 and HT46R24/HT46C24 devices, two memory pointers known as MP0 and MP1 are provided. These memory pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller is directed to is the address specified by the related Memory Pointer.

Chapter 1 Hardware Structure

Note

For theHT46R47/HT46C47 and HT46R22/HT46C22 devices, bit 7 of the memory pointers are not implemented. However, it must be noted that when the memory pointers in these devices are read, a value of ²1² will be read.

The following example shows how to clear a section of four RAM locations already defined as loca tions adres1 to adres4.

data .section ¢data¢ adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ?

code .section at 0 ¢code¢ org 00h

Page 35

A/D Type MCU

start:

mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; Accumulator loaded with first RAM address mov mp,a ; setup memory pointer with first RAM address

loop:

clr IAR ; clear the data at address defined by mp inc mp ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop

continue:

The important point to note here is that in the example shown above, no reference is made to spe cific RAM addresses.

Bank Pointer - BP

The Bank Pointer only exists in the HT46R24/HT46C24 devices. The existence of the Bank Pointer enables the HT46R24/HT46C24 devices to have a higher capacity of General Purpose Data Memory compared to other devices in the A/D series. The address of the General Purpose Data Memory bank in the HT46R24/HT46C24 microcontrollers ranges from 40H to FFH, a range that would normally provide only 192 bytes of General Purpose Data Memory. However by locat ing the memory into two banks, known as Bank 0 and Bank 1, the General Purpose Data Memory capacity can be expanded to 384 bytes. Bit 0 of the Bank Pointer, is utilized to set the present bank of the General Purpose Data Memory. The General Purpose Data Memory is initialized to bank 0 after reset, except for the WDT Time-out reset in the HALT Mode, in which case, the General Pur pose Data Memory bank remains unchanged. When it is required to read from or write to the Gen eral Purpose Data Memory in the HT46R24/HT46C24 microcontrollers, it is necessary to first setup the bank pointer to ensure that the correct memory bank is selected. It should be noted that the Special Function Data Memory is not affected by the bank selection, which means the Special Function Registers can be accessed from within either bank 0 or bank 1.

Accumulator - ACC

The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc. to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the tempo rary storage function of the Accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the Accumula tor as no direct transfer between two registers is permitted.

Program Counter Low Register - PCL

To provide additional program control functions, the low byte of the Program Counter is made ac cessible to programmers by locating it within the Special Purpose area of the Data Memory. By ma nipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted.

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Chapter 1 Hardware Structure

Look-up Table Registers - TBLP, TBLH

These two special function registers are used to control operation of the look-up table which is stored inthe Program Memory. TBLP is the table pointer and indicates the location wherethe table is located. Its value must be setup before any table read commands are executed. Its value can be changed, for example using the INC or DEC instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location.

Status Register - STATUS

This 8-bit register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). It also records the status infor mation and controls the operation sequence.

With the exception of the TO and PDF flags, bits in the status register can be altered by in structions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different re sults due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the ²CLR WDT² or ²HALT² instruction. The PDF flag is affected only by executing the ²HALT² or ²CLR WDT² instruction or during a system power-up.

The Z, OV, AC and C flags generally reflect the status of the latest operations.

C is set if an operation results in a carry during an addition operation or if a borrow does not take

place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction.

· AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the

high nibble into the low nibble in subtraction; otherwise AC is cleared.

· Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.

· OV is set if an operation results in a carry into the highest-order bit but not a carry out of the high-

est-order bit, or vice versa; otherwise OV is cleared

· PDF is cleared by a system power-up or executing the ²CLR WDT² instruction. PDF is set by executing the ²HALT² instruction.

TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is set by a WDT time-out.

b 7 b 0

T O P D F O V Z A C C

S T A T U S R e g i s t e r

A r i t h m e t i c / l o g i c o p e r a t i o n f l a g s

C a r r y F l a g A u x i l i a r y C a r r y F l a g Z e r o F l a g O v e r f l o w F l a g

S y s t e m m a n a g e m e n t f l a g s

P o w e r d o w n f l a g W a t c h d o g t i m e - o u t f l a g

N o t i m p l e m e n t e d , r e a d a s " 0 "

Page 37

A/D Type MCU

In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it.

Interrupt Control Registers - INTC, INTC0, INTC1

These 8-bit registers known as INTC, INTC0 and INTC1, control the operation of the various exter nal and internal interrupt functions. By setting various bits within these registers using standard bit manipulation instructions, the enable/disable function of each of the interrupts can be independ ently controlled. The various interrupt functions include those used by the internal timers, the ana log to digital converter and the I2C bus in addition to the external interrupt pin INT. For the HT46R47/HT46C47 devices, only one 8-bit interrupt control register, known as INTC, is required to control all its interrupt functions, while the additional features of the other devices require two in terrupt control registers, INTC0 and INTC1. A master interrupt bit within the INTC or INTC0 regis ter, the EMI bit, acts like a global enable/disable and is used to set all of the interrupt bits either on or off. This bit is cleared when an interrupt routine is entered to disable all further interrupts and is set by executing the ²RETI² instruction.

Note

In situations where other interrupts may require servicing within present interrupt service routines, the EMI bit can be manually set by the program after the present interrupt service routine has been entered.

Timer/Event Counter Registers

Depending upon which device is selected, all devices contain one or two integrated Timer/Event Counters of either 8-bit or 16-bit size. For devices with a single timer counter, an associated register, known as TMR, is the location where the timer value is located. An associated control register, known as TMRC, contains the setup information for the TMR register. For the HT46R24/HT46C24 devices which have two 16-bit timers, the individual timers are known as TMR0 and TMR1 with their respective control registers known as TMR0C and TMR1C. In the case of 16-bit timers, the actual value stored in the timer requires two bytes, a high byte and a low byte. These register pairs are known as TMRL/TMRH or TMR0L/TMR0H and TMR1L/TMR1H. Note that the timer registers can be directly written to in order to preload their contents with fixed data to allow different time intervals to be setup.

Input/Output Ports and Control Registers

Within the area of Special Function Registers, the I/O registers and their associated control regis ters play a prominent role. All I/O ports have a designated register correspondingly labeled as PA, PB, PC, etc. These labeled I/O registers are mapped to specific addresses within the Data Mem ory as shown in the Data Memory table which are used to transfer the appropriate output or input data on that port. With each I/O port there is an associated control register labeled PAC, PBC, PCC, etc. also mapped to specific addresses with the Data Memory. The control register specifies which pins of that port are set as inputs and which are set as outputs. To setup a pin as an input, the corresponding bit of the control register must be set high, for an output it must be set low. Dur ing program initialization, it is important to first setup the control registers to specify which pins are outputs and which are inputs before reading data from or writing data to the I/O ports. One flexible feature of these registers is the ability to directly program single bits using the ²SET [m].i² and

Page 38

Chapter 1 Hardware Structure

²CLR [m].i² instructions. The ability to change I/O pins from output to input and vice-versa by ma nipulating specific bits of the I/O control registers during normal program operation is a useful fea ture of these devices.

Pulse Width Modulator Registers - PWM, PWM0, PWM1, PWM2, PWM3

Each devicein the A/D microcontroller range contains either 1, 2 or 4 integrated Pulse Width Modu lators or PWM. Each one has its own independent control register. For devices which contain a sin gle PWM, the control register is known as PWM, for devices with two PWMs, the control registers are known as PWM0 and PWM1 while for devices with 4 PWMs, the control registers are known as PWM0~PWM3. The 8-bit contents of each of these registers define the duty cycle value for the modulation cycle of the corresponding pulse width modulator.

I2C Bus Registers - HADR, HCR, HSR, HDR

With the exception of the HT46R47/HT46C47, all devices contain an integrated I2C bus which in terfaces to the external shared pins SDA and SCL on the microcontroller. The correct setup and data transfer operation of this 2-line bidirectional bus utilizes 4 special function registers. The HADR register sets the slave address of the device while the HCR is the control register that en ables or disables the device as well as defines whether it is in transmit or receive mode. The HSR register is the status register while the HDR register is the input/output data register.

A/D Converter Registers - ADRL, ADRH, ADCR, ADSR

Each device in the A/D microcontroller range contains eithera4or8-channel A/D converter. The correct operation of the A/D requires the use of 4 registers. The high byte data register ADRH and low byte data register ADRL, are the two locations where the digital value is placed after the completion of an analog to digital conversion cycle. The channel selection and configuration of the A/D converter is setup via the control register ADCR while the A/D clock frequency is defined by the clock source register, ADSR.

Input/Output Ports

Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin fully under user program control, pull-high options for all pins and wake up options oncertain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities.

Depending upon which device or package is chosen, the microcontroller range provides from 13 to 40 bidirectional input/output lines labeled with port names PA, PB, PC, etc. These I/O ports are mapped to the Data Memory with specific addresses as shown in the Special Purpose Data Memory table. All of these I/O ports can be used for input and output operations. For input opera tion, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of in struction ²MOV A,[m]², where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten.

Page 39

A/D Type MCU

Pull-high Resistors

Many product applications require pull-high resistors for their switch inputs usually requiring the use ofan external resistor. To eliminate the need for theseexternal resistors, all I/O pins, when con figured as an input have the capability of being connected to an internal pull-high resistor. These pull-high resistors are selectable via configuration option and are implemented using a weak PMOS transistor. Note that on some ports, individual pins can be selected to have pull-high resis tors, while on other ports all pins or no pins must be selected to have pull-high resistors.

Port A Wake-up

Each device has a HALT feature enabling the microcontroller to enter a power down mode and pre serve power, a feature that is important for battery and other low power applications. Various meth ods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port A pins from high to low. After a ²HALT² instruction forces the microcontroller into entering a HALT condition, the processor will remain idle or in a low-power state until the logic condition of the selected wake-up pin on Port A changes from high to low. This function is especially suitable for applications that can be woken up via external switches. Note that each pin on Port Acan be se lected individually to have this wake-up feature.

I/O Port Control Registers

Each I/O line has its own control register (PAC, PBC, PCC, etc.) to control the input/output configu ration. With this control register, each CMOS output or Schmitt Trigger input with or without pull-high resistor structures can be reconfigured dynamically under software control. Each pin of the I/O ports is directly mapped to a bit in its associated port control register. For the I/O pin to func tion as an input, the corresponding bit of the control register must be written as a ²1². This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as a ²0², the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin.

Pin-shared Functions

The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be overcome. For some pins, the chosen function of the multi-function I/O pins is set by configuration options while for others the function is set by application program control.

External Interrupt Input

The external interrupt pin INT external interrupt input, the pin can be used as a normal I/O pin, however, to do this, the external interrupt enable bits in the INTC register must be disabled.

is pin-shared with the I/O pin PA5. For applications not requiring an

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Chapter 1 Hardware Structure

External Timer Clock Input

Each device in the A/D series contains either one or two timers depending upon which one is cho sen. In the case of devices with a single timer, this pin is known as TMR, which is pin-shared with PA4. However, for the 48-pin package HT46R24/HT46C24 devices, which have two internal tim ers, there are two independent input pins known as TMR0 and TMR1. For the 28-pin package HT46R24/HT46C24 devices, which also have two internal timers, due to packaging limitations the TMR0 pin is not available. On this package only the TMR1 external timer pin is available which is pin-shared with PD1/PWM1/TMR1. If the PA4/TMR or PD1/PWM1/TMR1 pin is to be configured as a timer input, the corresponding control bits in the timer control register must be correctly set. The PA4/TMR and PD1/PWM1/TMR1 pin can be used as a normal I/O pin for applications that do not require external timer inputs. For such applications, the timer mode control bits in the timer control register must select the timer mode, which has an internal clock source, to prevent the I/O from interfering with the timer counter operation.

PFD, PWM Outputs, I

Each device in the A/D series contains a PFD output, pin-shared with PA3, and one or more PWM outputs, pin-shared with pins PD0~PD3. The number of PWM outputs depends upon which de vice is chosen. With the exception of the HT46R47/HT46C47 devices, there are two pins associ ated with an internal I of these pins is chosen via configuration options and remains fixed after the device is pro grammed. Note that the correct software options within the application program must also be se lected to enable correct operation. If the I options associated with these pins will be automatically disconnected. For all pins, if chosen to function as I/O pins, then full pull-high options remain.

C Bus

C Bus, which are pin-shared with I/O pins PA6 and PA7. The function of all

C option is chosen, then note that any pull-high resistor

A/D Inputs

Each device in the A/D series has either four or eight inputs for the A/D converter. All of these ana log inputs are pin-shared with I/O pins on Port B. If these pins are to be used as A/D inputs and not as normal I/O pins then the corresponding bits in the A/D Converter Control Register, ADCR, must be properly set. There are no configuration options associated with the A/D function. If chosen as I/O pins, then full pin-high resistor configuration options remain, however if used as A/D inputs then any pull-high resistor options associated with these pins will be automatically disconnected.

D D

W e a k P u l l - u p

I / O P i n

D a t a B u s

W r i t e C o n t r o l R e g i s t e r

C h i p R e s e t

R e a d C o n t r o l R e g i s t e r

W r i t e D a t a R e g i s t e r

R e a d D a t a R e g i s t e r

S y s t e m W a k e - u p

( w a k e - u p f o r P A o n l y )

C o n t r o l B i t

C K

D a t a B i t

C K

P u l l - H i g h O p t i o n

U X

W a k e - u p O p t i o n

Non-pin-shared Function Input/Output Ports

Page 41

D a t a B u s

W r i t e C o n t r o l R e g i s t e r

C h i p R e s e t

R e a d C o n t r o l R e g i s t e r

W r i t e D a t a R e g i s t e r

P F D o r P W M W a v e f o r m

R e a d D a t a R e g i s t e r

C o n t r o l B i t

C K

D a t a B i t

C K

P u l l - H i g h O p t i o n

P F D / P W M O p t i o n U X

A/D Type MCU

D D

W e a k P u l l - u p

P A 3 / P F D P D 0 / P W M 0 P D 1 / P W M 1 P D 2 / P W M 2 P D 3 / P W M 3

P D 1 / P W M 1 / T M R 1

M U X

( H T 4 6 R 2 4 / H T 4 6 C 2 4 2 8 - p i n p a c k a g e o n l y )

( H T 4 6 R 2 4 / H T 4 6 C 2 4

2 8 - p i n p a c k a g e o n l y )

PA3/PFD and PD0/PWM0~PD3/PWM3 Input/Output Ports

D a t a B u s

W r i t e C o n t r o l R e g i s t e r

C h i p R e s e t

R e a d C o n t r o l R e g i s t e r

W r i t e D a t a R e g i s t e r

R e a d D a t a R e g i s t e r

I N T ( P A 5 o n l y ) T M R ( P A 4 o n l y )

S y s t e m W a k e - u p

T M R 1

C o n t r o l B i t

C K

P u l l - H i g h O p t i o n

D a t a B i t

C K

M U X

PA4/PA5 Input/Output Ports

W a k e - u p O p t i o n

D D

W e a k P u l l - u p

P A 4 / T M R ( e x c e p t H T 4 6 R 2 4 / H T 4 6 C 2 4 )

P A 5 / I N T

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D a t a B u s

C o n t r o l B i t

Chapter 1 Hardware Structure

P u l l - H i g h O p t i o n

D D

W e a k P u l l - u p

W r i t e C o n t r o l R e g i s t e r

C h i p R e s e t

R e a d C o n t r o l R e g i s t e r

W r i t e D a t a R e g i s t e r

T o I2C C i r c u i t

R e a d D a t a R e g i s t e r

S y s t e m W a k e - u p

T o I2C C i r c u i t

D a t a B u s

W r i t e C o n t r o l R e g i s t e r

C h i p R e s e t

R e a d C o n t r o l R e g i s t e r

W r i t e D a t a R e g i s t e r

R e a d D a t a R e g i s t e r

T o A / D C o n v e r t e r

C K

D a t a B i t

C K

M U X

M U

W a k e - u p O p t i o n

PA6/SDA, PA7/SCL Input/Output Ports

A n a l o g

I n p u t

S e l e c t o r

M U X

P u l l - H i g h O p t i o n

C o n t r o l B i t

P C R 2 P C R 1 P C R 0

C K

D a t a B i t

C K

D D

W e a k P u l l - u p

M U X

P A 6 / S D A , P A 7 / S C L ( e x c e p t H T 4 6 R 4 7 / H T 4 6 C 4 7 )

I2C C o n f i g u r a t i o n O p t i o n

P B 0 / A N 0 ~ P B 7 / A N 7 ( H T 4 6 R 4 7 / H T 4 6 C 4 7 w i t h P B 0 / A N 0 ~ P B 3 / A N 3 o n l y )

A C S 2 ~ A C S 0

PB Input/Output Ports

Page 43

A/D Type MCU

Programming Considerations

Within the user program, one of the first things to consider is port initialization. After a reset, all of the I/O data and port control registers will be set high. This means that all I/O pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high op tions have been selected. If the port control registers, PAC, PBC, PCC, etc., are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the as sociated port data registers, PA, PB, PC, etc., are first programmed. Selecting which pins are in puts and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the ²SET [m].i² and ²CLR [m].i² instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the en tire port,modify it to the required new bit values and then rewrite this data back to the output ports.

S y s t e m C l o c k

T 1 T 2

P o r t D a t a

Port A has the additional capability of providing wake-up functions. When the chip is in the HALT state, various methods are available to wake the device up. One of these is a high to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function.

T 3 T 4

W r i t e t o p o r t R e a d f r o m p o r t

T 1 T 2

T 3 T 4

Timer/Event Counters

The provision of timers form an important part of any microcontroller, giving the designer a means of carrying out time related functions. The devices in the A/D Type MCU series contain either one or two count up timers of either 8 or 16-bit capacity depending upon which device is selected. As each timer has three different operating modes, they can be configured to operate as a general timer, an external event counter or as a pulse width measurement device. With the exception of TMR1 in the HT46R24/HT46C24 devices, the provision of an internal 8-stage prescaler to the timer clock circuitry gives added range to the timer.

There are two types of registers related to the Timer/Event Counters. The first is the register that contains the actual value of the timer and into which an initial value can be preloaded. Reading from this register retrieves the contents of the Timer/Event Counter. The second type of associ ated register is the timer control register which defines the timer options and determines how the timer is to be used. All devices can have the timer clock configured to come from the internal clock source. In addition, with the exception of TMR0 in the 28-pin package in the HT46R24/HT46C24 devices, the timer clock source can also be configured to come from an external timer pin. The ac companying table lists the associated timer register names.

Page 44

Chapter 1 Hardware Structure

HT46R47 HT46C47

No. of 8-bit Timers 11

Timer Register Name TMR TMR

Timer Control Register TMRC TMRC

No. of 16-bit Timers

Timer Register Name

Timer Control Register

¾¾

HT46R22 HT46C22

HT46R23 HT46C23

¾¾

TMRL/TMRH

TMRC

HT46R24 HT46R24

TMR0L/TMR0H TMR1L/TMR1H

TMR0C TMR1C

An external clock source is used when the timer is in the event counting mode, the clock source be ing provided on the external timer pin known as TMR, TMR0 or TMR1 depending on which device is selected. These external pins may be pin-shared with other I/O pins depending upon which de vice and package is chosen. Depending upon the condition of the TE, T0E or T1E bit in the corre sponding timer control register, each high to low, or low to high transition on the external timer input pin will increment the counter by one. Note that the 28-pin package HT46R24/HT46C24 de vices, although having two internal Timer/Event Counters, have only one external timer pin TMR1; due to packaging limitations the TMR0 pin is not available.

Configuring the Timer/Event Counter Input Clock Source

The internal timer¢s clock source can originate from either the system clock or from an external clock source, with the exception of TMR0 in the 28-pin package HT46R24/HT46C24 devices. The system clock input timer source is used when the timer is in the timer mode or in the pulse width measurement mode. With the exception of TMR1 in the HT46R24/HT46C24 devices, whose timer clock source is f prescaler, the division ratio of which is conditioned by the bits PSC2~PSC0 or T0PSC2~T0PSC0.

/4 and has no prescaler, the timer clock source is f

SYS

divided by the value in the

SYS

An external clock source is used when the timer is in the event counting mode, the clock source being provided on an external timer pin, TMR, TMR0 or TMR1 depending upon which device and which timer is used. Depending upon the condition of the TE, T0E or T1E bit, each high to low, or low to high transition on the external timer pin will increment the counter by one. Note that as the 28-pin package HT46R24/HT46C24 devices has only one TMR1 external timer pin, its TMR0 internal timer cannot have an external clock source.

D a t a B u s

R e l o a d

O v e r f l o w t o I n t e r r u p t

P F D

S Y S

T M R i n p u t

P S C 2 ~ P S C 0

8 - s t a g e p r e s c a l e r

( 1 / 1 ~ 1 / 1 2 8 )

T E

T M 1 T M 0

T i m e r / E v e n t C o u n t e r

M o d e C o n t r o l

P r e l o a d R e g i s t e r

T O N

8 - B i t T i m e r / E v e n t C o u n t e r

T i m e r / E v e n t

C o u n t e r

8-bit Timer/Event Counter Structure - HT46R47/HT46C47 and HT46R22/HT46C22 TMR

Page 45

A/D Type MCU

D a t a B u s

L o w B y t e

B u f f e r

P S C 2 ~ P S C 0

S Y S

8 - s t a g e p r e s c a l e r

T M R

16-bit Timer/Event Counter Structure - HT46R23/HT46C23 TMR

S Y S

( 4 8 - p i n p a c k a g e o n l y )

T M R 0

16-bit Timer/Event Counter Structure - HT46R24/HT46C24 TMR0

( 1 / 1 ~ 1 / 1 2 8 )

T E

T 0 P S C 2 ~ T 0 P S C 0

8 - s t a g e p r e s c a l e r

T 0 E

T i m e r / E v e n t C o u n t e r

( 1 / 1 ~ 1 / 1 2 8 )

T M 1 T M 0

M o d e C o n t r o l

T 0 M 1 T 0 M 0

T i m e r / E v e n t C o u n t e r

M o d e C o n t r o l

H i g h B y t e

T O N

1 6 - B i t T i m e r / E v e n t C o u n t e r

T 0 O N

1 6 - B i t

P r e l o a d R e g i s t e r

L o w B y t e

B u f f e r

1 6 - B i t

P r e l o a d R e g i s t e r

H i g h B y t e

1 6 - B i t T i m e r / E v e n t C o u n t e r

L o w B y t e

B u f f e r

L o w B y t e

R e l o a d

D a t a B u s

O v e r f l o w t o I n t e r r u p t

P F D

D a t a B u s

R e l o a d

O v e r f l o w t o I n t e r r u p t

P F D

T M R 1

1 6 - B i t

T 1 M 1 T 1 M 0

/ 4

S Y S

T i m e r / E v e n t C o u n t e r

M o d e C o n t r o l

T 1 E

T 1 O N

P r e l o a d R e g i s t e r

H i g h B y t e

1 6 - B i t T i m e r / E v e n t C o u n t e r

L o w B y t e

R e l o a d

O v e r f l o w t o I n t e r r u p t

P F D

16-bit Timer/Event Counter Structure - HT46R24/HT46C24 TMR1

Timer Registers - TMR, TMRL/TMRH, TMR0L/TMR0H, TMR1L/TMR1H

The timer register is a special function register located in the special purpose Data Memory and is the place where the actual timer value is stored. For the 8-bit timer, this register is known as TMR. For the 16-bit timer, a pair of 8-bit registers are required to store the 16-bit timer value. In the case of the HT46R23/HT46C23 devices, this register pair is known as TMRL and TMRH. In the case of the HT46R24/HT46C24 device which has two 16-bit timers, the register pair for TMR0 is known as TMR0L and TMR0H, while the register pair for TMR1 is known as TMR1L and TMR1H. The value

Page 46

Chapter 1 Hardware Structure

in the timer registers increases by one each time an internal clock pulse is received or an external transition occurs on the external timer pin. The timer will count from the initial value loaded by the preload register to the full count of FFH for the 8-bit timer or FFFFH for the 16-bit timers at which point the timer overflows and an internal interrupt signal is generated. The timer value will then be reset with the initial preload register value and continue counting. Note that to achieve a maximum full range count of FFH for the 8-bit timer or FFFFH for the 16-bit timers, the preload registers must first becleared to all zeros. It should be noted that after power on, the preload registers will be in an unknown condition.

Note that if the Timer/Event Counters are in an OFF condition and data is written to their preload registers, this data will be immediately written into the actual counter. However, if the counter is en abled and counting, any new data written into the preload data register during this period will re main in the preload register and will only be written into the actual counter the next time an overflow occurs. Note also that when the timer registers are read, the timer clock will be blocked to avoid errors, however, as this may result in certain timing errors, programmers must take this into account.

For devices with 16-bit timers, which have both low byte and high byte timer registers, accessing these registers is carried out in a specific way. It must be noted that when using instructions to preload data into the low byte register, namely, TMRL, TMR0L or TMR1L, the data will only be placed in a low byte buffer and not directly into the low byte register. The actual transfer of the data into the low byte register is only carried out when a write to its associated high byte register, namely, TMRH, TMR0H or TMR1H, is executed. On the other hand, using instructions to preload data into the high byte timer register will result in the data being directly written to the high byte reg ister. At the same time the data in the low byte buffer will be transferred into its associated low byte register. For this reason, when preloading data into the 16-bit timer registers, the low byte should be written first. It must also be noted that to read the contents of the low byte register, a read to the high byte register must first be executed to latch the contents of the low byte buffer into its associated low byte register. After this has been done, the low byte register can be read in the normal way. Note that reading the low byte timer register will only result in reading the previously latched contents of the low byte buffer and not the actual contents of the low byte timer register.

Timer Control Registers - TMRC, TMR0C, TMR1C

The flexible features of the Holtek microcontroller Timer/Event Counters enable them to operate in three different modes, the options of which are determined by the contents of their respective con trol register. For devices with only one timer, the single timer control register is known as TMRC while for devices with two timers, there are two timer control registers known as TMR0C and TMR1C. It is the timer control register together with its corresponding timer registers that control the full operation of the Timer/Event Counters. Before the timers can be used, it is essential that the appropriate timer control register is fully programmed with the right data to ensure its correct operation, a process that is normally carried out during program initialization.

To choose which of the three modes the timer is to operate in, either in the timer mode, the event counting mode or the pulse width measurement mode, bits 7 and 6 of the Timer Control Register, which are known as the bit pair TM1/TM0, T0M1/T0M0 or T1M1/T1M0 respectively, depending upon which timer is used, must be set to the required logic levels. The timer-on bit, which is bit 4 of the Timer Control Register and known as TON, T0ON or T1ON, depending upon which timer is

Page 47

A/D Type MCU

used, provides the basic on/off control of the respective timer. Setting the bit high allows the coun ter to run, clearing the bit stops the counter. For timers that have prescalers, bits 0~2 of the Timer Control Register determine the division ratio of the input clock prescaler. The prescaler bit settings have no effect if an external clock source is used. If the timer is in the event count or pulse width measurement mode,the active transition edge level type is selected by the logic level of bit 3 of the Timer ControlRegister which is known as TE, T0E or T1E, depending upon which timer is used.

b 7

T ET O NT M 0T M 1

P S C 2 P S C 1 P S C 0

b 0

T i m e r / E v e n t C o u n t e r C o n t r o l R e g i s t e r T M R C

T i m e r p r e s c a l e r r a t e s e l e c t P S C 2

P S C 1

P S C 0

E v e n t C o u n t e r a c t i v e e d g e s e l e c t 1 : c o u n t o n f a l l i n g e d g e 0 : c o u n t o n r i s i n g e d g e

P u l s e W i d t h M e a s u r e m e n t a c t i v e e d g e s e l e c t 1 : s t a r t c o u n t i n g o n r i s i n g e d g e , s t o p o n f a l l i n g e d g e 0 : s t a r t c o u n t i n g o n f a l l i n g e d g e , s t o p o n r i s i n g e d g e

T i m e r / E v e n t C o u n t e r c o u n t i n g e n a b l e 1 : e n a b l e 0 : d i s a b l e

N o t i m p l e m e n t e d , r e a d a s " 0 "

O p e r a t i n g m o d e s e l e c t T M 1

T M 0

T i m e r R a t e

1 : 1

1 : 2

1 : 4

1 : 8

1 : 1 6

1 : 3 2

1 : 6 4

1 : 1 2 8

n o m o d e a v a i l a b l e e v e n t c o u n t e r m o d e t i m e r m o d e p u l s e w i d t h m e a s u r e m e n t m o d e

b 7

T 0 ET 0 O NT 0 M 0T 0 M 1

T 0 P S C 2 T 0 P S C 1 T 0 P S C 0

b 0

T i m e r / E v e n t C o u n t e r C o n t r o l R e g i s t e r T M R 0 C

T i m e r p r e s c a l e r r a t e s e l e c t

T 0 P S C 1

T 0 P S C 2

0 0 0 0 1 1 1

1 E v e n t C o u n t e r a c t i v e e d g e s e l e c t 1 : c o u n t o n f a l l i n g e d g e 0 : c o u n t o n r i s i n g e d g e

T i m e r / E v e n t C o u n t e r c o u n t i n g e n a b l e 1 : e n a b l e 0 : d i s a b l e

N o t i m p l e m e n t e d , r e a d a s " 0 "

O p e r a t i n g m o d e s e l e c t

T 0 M 1

T 0 M 0 0 0 1 1

T 0 P S C 0 0 0 1 1 0 0 1 1

n o m o d e a v a i l a b l e

e v e n t c o u n t e r m o d e

t i m e r m o d e

p u l s e w i d t h m e a s u r e m e n t m o d e

T i m e r R a t e

1 : 1

1 : 2

1 : 4

1 : 8

1 : 1 6

1 : 3 2

1 : 6 4

1 : 1 2 8

Page 48

Chapter 1 Hardware Structure

The HT46R24/HT46C24 devices have two internal timers, TMR0 and TMR1, and therefore re quire an additional timer control register TMR1C.

b 7

T 1 ET 1 O NT 1 M 0T 1 M 1

b 0

T i m e r / E v e n t C o u n t e r C o n t r o l R e g i s t e r T M R 1 C

N o t i m p l e m e n t e d , r e a d a s " 0 "

E v e n t C o u n t e r a c t i v e e d g e s e l e c t 1 : c o u n t o n f a l l i n g e d g e 0 : c o u n t o n r i s i n g e d g e

T i m e r / E v e n t C o u n t e r c o u n t i n g e n a b l e 1 : e n a b l e 0 : d i s a b l e

N o t i m p l e m e n t e d , r e a d a s " 0 "

O p e r a t i n g m o d e s e l e c t

T 1 M 1

T 1 M 0 0 0 1 1

n o m o d e a v a i l a b l e

e v e n t c o u n t e r m o d e

t i m e r m o d e

p u l s e w i d t h m e a s u r e m e n t m o d e

Configuring the Timer Mode

In this mode, the timer can be utilized to measure fixed time intervals, providing an internal inter rupt signal each time the counter overflows. To operate in this mode, the bit pair, TM1/TM0, T0M1/T0M0 or T1M1/T1M0, depending upon which timer is used, must be set to 1 and 0 respec tively. In this mode the internal clock is used as the timer clock. With the exception of TMR1 in the HT46R24/HT46C24, the input clock frequency is f prescaler, the value of which is determined by bits PSC2~PSC0 or T0PSC2~T0PSC0 in the timer control register. For TMR1 in theHT46R24/HT46C24, which has no prescaler, the input clock frequency is f

/4. The timer-on bit, TON, T0ON or T1ON, depending upon which timer is used,

SYS

must be set high to enable the timer to run. Each time an internal clock high to low transition occurs, the timer increments by one; when the timer is full and overflows, an interrupt signal is generated and the timer will preload the value already loaded into the preload register and continue counting. A timer overflow condition and corresponding internal interrupt is one of the wake-up sources, however, the internal interrupts can be disabled by ensuring that the ETI or ET0I and ET1I bits of the INTC register are reset to zero.

T i m e r C l o c k o r

P r e s c a l e r O u t p u t

divided by the value programmed into the

SYS

I n c r e m e n t

T i m e r C o n t r o l l e r

T i m e r + 1 T i m e r + 2

T i m e r + N T i m e r + N + 1

Timer Mode Timing Chart

Configuring the Event Counter Mode

In thismode, a number of externally changing logic events, occurring on the external timer pin, can be recorded by the internal timer. For the timer to operate in the event counting mode, the bit pair, TM1/TM0, T0M1/T0M0 or T1M1/T1M0, depending upon which timer is used, must be set to 0 and 1 respectively. The timer-on bit, TON, T0ON or T1ON, depending upon which timer is used, must be set high to enable the timer to count. Depending upon which counter is used, if TE, T0E or T1E is low, the counter will increment each time the external timer pin receives a low to high transition.

Page 49

A/D Type MCU

If TE, T0E or T1E is high, the counter will increment each time the external timer pin receives a high to low transition. As in the case of the other two modes, when the counter is full, the timer will overflow and generate an internal interrupt signal. The counter will then preload the value already loaded into the preload register. As the external timer pins are pin-shared with other I/O pins, to en sure that the pin is configured to operate as an event counter input pin, two things have to happen. The first is to ensure that the TM1/TM0, T0M1/T0M0 or T1M1/T1M0 bits place the Timer/Event Counter in the event counting mode, the second is to ensure that the port control register configures the pin as an input. Note that the 28-pin package HT46R24/HT46C24 devices, al though having two internal timers, only one TMR1 external control pin is available. As a result TMR0 cannot be used in the Event Counter Mode.

E x t e r n a l E v e n t

I n c r e m e n t

T i m e r C o u n t e r

T i m e r + 1

Event Counter Mode Timing Chart

Configuring the Pulse Width Measurement Mode

In this mode, the width of external pulses applied to the external timer pin can be measured. In the Pulse Width Measurement Mode the timer clock source is supplied by the internal clock. For the timer to operate in this mode, the bit pair, TM1/TM0, T0M1/T0M0 or T1M1/T1M0, depending upon which timer is used, must both be set high. Depending upon which counter is used, if TE, T0E or T1E is low, once a high to low transition has been received on the external timer pin, the timer will start counting until the external timer pin returns to its original high level. At this point the TON, T0ON or T1ON bit, depending upon which counter is used, will be automatically reset to zero and the timer will stop counting. If the TE, T0E or T1E bit is high, the timer will begin counting once a low to high transition has been received on the external timer pin and stop counting when the external timerpin returns to its original low level. As before, the TON, T0ON or T1ON bit will be automatically reset to zero and the timer will stop counting. It is important to note that in the Pulse Width Measurement Mode, the TON, T0ON or T1ON bit is automatically reset to zero when the external control signal on the external timer pin returns to its original level, whereas in the other two modes the TON, T0ON or T1ON bit can only be reset to zero under program control. The residual value in the timer, which can now be read by the program, therefore represents the length of the pulse received on the external timer pin. As the TON, T0ON or T1ON bit has now been reset, any further transitions on the external timer pin, will be ignored. Not until the TON, T0ON or T1ON bit is again set high by the program can the timer begin further pulse width measurements. In this way, single shot pulse measurements can be easily made. It should be noted that in this mode the counter is controlled by logical transitions on the external timer pin and not by the logic level.

T i m e r + 2 T i m e r + 3

As in the case of the other two modes, when the counter is full, the timer will overflow and generate an internal interrupt signal. The counter will also be reset to the value already loaded into the preload register. If the external timer pin is pin-shared with other I/O pins, to ensure that the pin is configured to operate as a pulse width measuring input pin, two things have to happen. The first is to ensure that the TM1/TM0, T0M1/T0M0 or T1M1/T1M0 bits place the Timer/Event Counter in the pulse width measuring mode, the second is to ensure that the port control register configures the pin as an input. Note that the 28-pin package HT46R24/HT46C24 devices, although having two internal timers, only one TMR1 external control pin is available. As a result TMR0 cannot be used in the Pulse Width Measurement Mode.

Page 50

Chapter 1 Hardware Structure

E x t e r n a l T i m e r

P i n I n p u t

T O N , T 0 O N o r T 1 O N

( w i t h T E , T 0 E o r T 1 E = 0 )

P r e s c a l e r O u t p u t ( w i t h c l o c k = f

T i m e r C o u n t e r

Programmable Frequency Divider - PFD

The PFD output is pin-shared with the I/O pin PA3. The function is selected via configuration op tion, however, if not selected, the pin can operate as a normal I/O pin. Note that for the HT46R24/ HT46C24 devices,which have two internal timers, the timer source for the PFD can be chosen, via configuration option, to come from either one of the two timers.

The timer overflow signal is the clock source for the PFD circuit. The output frequency is controlled by loading the required values into the timer prescaler registers to give the required division ratio. The counter, driven by the system clock which is divided by the prescaler value, will begin to count-up from this preload register value until full, at which point an overflow signal is generated, causing the PFD output to change state. The counter will then be automatically reloaded with the preload register value and continue counting-up. Refer to the relevant Timer/Event Counters sec tion for details of its settings and operations.

S Y S

I n c r e m e n t

)

T i m e r

P r e s c a l e r O u t p u t i s s a m p l e d a t e v e r y f a l l i n g e d g e o f T 1 .

+ 1 + 2 + 3 + 4

Pulse Width Measurement Mode Timing Chart

For the PFD output to function, it is essential that the corresponding bit of the Port A control register PAC bit 3 is setup as an output. If setup as an input the PFD output will not function, however, the pin can still be used as a normal input pin. The PFD output will only be activated if bit PA3 is set to ²1². This output data bit is used as the on/off control bit for the PFD output. Note that the PFD output will be low if the PA3 output data bit is cleared to ²0².

T i m e r O v e r f l o w

P F D C l o c k

P A 3 D a t a

P F D O u t p u t a t P A 3

Using this method of frequency generation, and if a crystal oscillator is used for the system clock, very precise values of frequency can be generated.

Page 51

A/D Type MCU

Prescaler

With the exception of TMR1C, bits 0~2 of the timer control register can be used to define the pre-scaling stages of the internal clock sources of the Timer/Event Counter. The Timer/Event Counter overflow signal can be used to generate signals for the PFD and as a Timer Interrupt.

I/O Interfacing

The Timer/Event Counter when configured to run in the event counter or pulse width measure ment mode, require the use of the external timer pin for correct operation. This external timer pin may be pin-shared with other I/O pins, depending upon which device is selected. Pull-high resis tors can be selected for connection to the timer input pins. The timers can also be setup to drive the PFDpin. When the PFD output is selected by selecting the correct configuration option, the out put of the chosen timer can be made to drive this at a frequency determined by the contents of the timer register and the timer.

Programming Considerations

When configured to run in the timer mode, the internal system clock is used as the timer clock source and is therefore synchronized with the overall operation of the microcontroller. In this mode when the appropriate timer register is full, the microcontroller will generate an internal interrupt sig nal directing the program flow to the respective internal interrupt vector. For the pulse width mea surement mode, the internal system clock is also used as the timer clock source but the timer will only run when the correct logic condition appears on the external timer input pin. As this is an exter nal event and not synchronized with the internal timer clock, the microcontroller will only see this external event when the next timer clock pulse arrives. As a result, there may be small differences in measured values requiring programmers to take this into account during programming. The same applies if the timer is configured to be in the event counting mode which again is an external event and not synchronized with the internal system or timer clock.

Pulse Width Modulator

Each microcontroller in the A/D series is provided with one or more Pulse Width Modulation (PWM) outputs. Useful for such applications such as motor speed control, the PWM function provides outputs with a fixed frequency but with a duty cycle that can be varied by setting particular values into the corresponding PWM register.

A single register, located in the Data Memory is assigned to each PWM. For devices with a single PWM output, this register is known as PWM. For devices with two PWM outputs, the registers as sume the names PWM0 and PWM1 while devices with four PWM outputs require a further addi tional two registers known as PWM2 and PWM3. It is here that the 8-bit value, which represents the overall duty cycle of one modulation cycle of the output waveform, should be placed. To in crease the PWM modulation frequency, each modulation cycle is modulated into two or four indi vidual modulation sub-sections, known as the 7+1 mode or 6+2 mode respectively. With the exception of the HT46R47/HT46C47 devices, which have a fixed 6+2 mode, each device can choose which mode to use by selecting the appropriate configuration option. When a mode config uration option is chosen, it applies to all PWM outputs on that device. Note that when using the PWM it is only necessary to write the required value into the appropriate PWM register and select the required mode configuration option, the subdivision of the waveform into its sub-modulation cy cles is done automatically within the microcontroller hardware.

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Chapter 1 Hardware Structure

For all devices, the PWM clock source is the system clock f

Device Channels

HT46R47/HT46C47 1 6+2 PD0

HT46R22/HT46C22 1 6+2 or 7+1 PD0

HT46R23/HT46C23 (24-pin package)

HT46R23/HT46C23 (28-pin package)

HT46R24/HT46C24 (28-pin package)

HT46R24/HT46C24 (48-pin package)

1 6+2 or 7+1 PD0 PWM0

2 6+2 or 7+1 PD0/PD1 PWM0/PWM1

4 6+2 or 7+1 PD0/PD1/PD2/PD3

Mode Output Pin PWM Register Name

PWM

SYS

PWM

PWM0/PWM1/

PWM2/PWM3

PWM Function Table

This method of dividing the original modulation cycle into a further 2 or 4 sub-cycles enables the generation of higher PWM frequencies, which allow a wider range of applications to be served. As long as the periods of the generated PWM pulses are less than the time constants of the load, the PWM output will be suitable as such long time constant loads will average out the pulses of the PWM output. The difference between what is known as the PWM cycle frequency and the PWM

/256

, and as

SYS

modulation frequency should be understood. As the PWM clock is the system clock, f the PWM value is 8-bits wide, the overall PWM cycle frequency is f 7+1 mode of operation the PWM modulation frequency will be f tion frequency for the 6+2 mode of operation will be f

PWM Modulation Frequency PWM Cycle Frequency PWM Cycle Duty

/64 for (6+2) bits mode

SYS

/128 for (7+1) bits mode

SYS

/64.

SYS

/256

SYS

/256. However, when in the

SYS

/128, while the PWM modula

SYS

[PWM]

6+2 PWM Mode

Each full PWM cycle, as it is controlled by an 8-bit PWM register, has 256 clock periods. However, in the 6+2 PWM Mode, each PWM cycle is subdivided into four individual sub-cycles known as modulation cycle 0 ~ modulation cycle 3, denoted as ²i² in the table. Each one of these four sub-cycles contains 64 clock cycles. In this mode, a modulation frequency increase by a factor of four is achieved. The 8-bit PWM register value, which represents the overall duty cycle of the PWM waveform, is divided into two groups. The first group which consists of bit2~bit7 is denoted here as the DC value. The second group which consists of bit0~bit1 is known as the AC value. In the 6+2 PWM mode, the duty cycle value of each of the four modulation sub-cycles is shown in the following table.

Parameter AC (0~3) DC (Duty Cycle)

DC 164+

Modulation cycle i

(i=0~3)

i<AC

i³AC

6+2 Mode Modulation Cycle Values

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A/D Type MCU

The following diagram illustrates the waveforms associated with the 6+2 mode of PWM operation. It is important to note how the single PWM cycle is subdivided into 4 individual modulation cycles, numbered from 0~3 and how the AC value is related to the PWM value.

/ 2

S Y S

[ P W M ] = 1 0 0

P W M

[ P W M ] = 1 0 1

P W M

[ P W M ] = 1 0 2

P W M

[ P W M ] = 1 0 3

P W M

2 5 / 6 4

2 6 / 6 4

P W M m o d u l a t i o n p e r i o d : 6 4 / f

M o d u l a t i o n c y c l e 0

2 5 / 6 4 2 5 / 6 4 2 5 / 6 4

2 5 / 6 4

2 6 / 6 4

S Y S

M o d u l a t i o n c y c l e 1 M o d u l a t i o n c y c l e 2 M o d u l a t i o n c y c l e 3 M o d u la t i o n c y c l e 0

P W M c y c l e : 2 5 6 / f

2 5 / 6 4

2 6 / 6 4 2 5 / 6 4

S Y S

2 5 / 6 4

2 6 / 6 4

6+2 PWM Mode

b 7 b 0

P W M R e g i s t e r ( 6 + 2 ) M o d e

A C v a l u e

D C v a l u e

PWM Register for 6+2 Mode

7+1 PWM Mode

Each full PWM cycle, as it is controlled by an 8-bit PWM register has 256 clock periods. However, in the 7+1 PWM mode, each PWM cycle is subdivided into two individual sub-cycles, known as modulation cycle 0 and modulation cycle 1, denoted as ²i² in the table. Each one of these two sub-cycles contains 128 clock cycles. In this mode, a modulation frequency increase by a factor of two is achieved. The 8-bit PWM register value, which represents the overall duty cycle of the PWM waveform, is divided into two groups. The first group which consists of bit1~bit7 is denoted here as the DC value. The second group which consists of bit0 is known as the AC value. In the 7+1 PWM mode, the duty cycle value of each of the two modulation sub-cycles is shown in the following table.

Parameter AC (0~1) DC (Duty Cycle)

DC 1

128

Modulation cycle i

(i=0~1)

i<AC

i³AC

7+1 Mode Modulation Cycle Values

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Chapter 1 Hardware Structure

The following diagram illustrates the waveforms associated with the 7+1 mode of PWM operation. It is important to note how the single PWM cycle is subdivided into 2 individual modulation cycles, numbered 0 and 1 and how the AC value is related to the PWM value.

/ 2

S Y S

[ P W M ] = 1 0 0

P W M

[ P W M ] = 1 0 1

P W M

[ P W M ] = 1 0 2

P W M

[ P W M ] = 1 0 3

P W M

5 0 / 1 2 8

5 1 / 1 2 8

5 2 / 1 2 8

P W M m o d u l a t i o n p e r i o d : 1 2 8 / f

M o d u l a t i o n c y c l e 0

S Y S

P W M c y c l e : 2 5 6 / f

5 0 / 1 2 8

5 1 / 1 2 8

M o d u l a t i o n c y c l e 1 M o d u l a t i o n c y c l e 0

S Y S

7+1 PWM Mode

5 0 / 1 2 8

5 1 / 1 2 8

5 2 / 1 2 8

b 7 b 0

P W M R e g i s t e r ( 7 + 1 ) M o d e

A C v a l u e

D C v a l u e

PWM Register for 7+1 Mode

PWM Output Control

On all devices, the PWM outputs are pin-shared with the Port D I/O pins. To operate as PWM outputs and not as I/O pins, the correct PWM configuration options must be selected. A ²0² must also be written to the corresponding bits in the I/O port control register PDC to ensure that the required PWM output pins are setup as outputs. After these two initial steps have been carried out, and of course after the required PWM value has been written into the PWM register, writing a ²1² to the corresponding bit in the PD output data register will enable the PWM data to appear on the pin. Writing a ²0² to the corresponding bit in the PD output data register will disable the PWM output function and force the output low. In this way, the Port D data output register can be used as an on/off control for the PWM function. Note that if the configuration options have selected the PWM function, but a ²1² has been written to its corresponding bit in the PDC control register to configure the pin as an input, then the pin can still function as a normal input line, with pull-high resistor op tions.

clr PDC.0 ; set pin PD0 as output clr PDC.1 ; set pin PD1 as output clr PDC.2 ; set pin PD2 as output clr PDC.3 ; set pin PD3 as output

Page 55

set pd.0 ; PD.0=1; enable pin ²PD0/PWM0² to be the PWM channel 0 mov a,64h ; PWM0=100D=64H mov pwm0,a

set pd.1 ; PD.1=1; enable pin ²PD1/PWM1² to be the PWM channel 1 mov a,65h ; PWM1=101D=65H mov pwm1,a

set pd.2 ; PD.2=1; enable pin ²PD2/PWM2² to be the PWM channel 2 mov a,66h ; PWM2=102D=66H mov pwm2,a

set pd.3 ; PD.3=1; enable pin ²PD3/PWM3² to be the PWM channel 3 mov a,67h ; PWM3=103D=67H mov pwm3,a

clr pd.0 ; disable PWM0 output - PD.0 will remain low clr pd.1 ; disable PWM1 output - PD.1 will remain low clr pd.2 ; disable PWM2 output - PD.2 will remain low clr pd.3 ; disable PWM3 output - PD.3 will remain low

Analog to Digital Converter

The need to interface to real world analog signals is a common requirement for many electronic systems. However, to properly process these signals by a microcontroller, they must first be con verted into digital signals by A/D converters. By integrating the A/D conversion electronic circuitry into the microcontroller, the need for external components is reduced significantly with the corre sponding follow-on benefits of lower costs and reduced component space requirements. Each of the devices in the Holtek A/D series of microcontrollers contains either a 4-channel or 8-channel analog to digital converter which can directly interface to external analog signals such as that from sensors or other control signals and convert these signals directly into either a 9-bit or 10-bit digital value.

Device Input Channels Conversion Bits Input Pins

HT46R47/HT46C47 4 9 PB0~PB3

HT46R22/HT46C22 8 9 PB0~PB7

HT46R23/HT46C23 8 10 PB0~PB7

HT46R24/HT46C24 8 10 PB0~PB7

A/D Type MCU

A/D Converter Data Registers - ADRL/ADRH

To store the actual 9-bit or 10-bit digital value, obtained after the completion of the conversion pro cess, a high byte register ADRH and low byte register ADRL are assigned. After the conversion process takes place, these two registers can be directly read by the microcontroller to obtain the digitized conversion value. Note that only the high byte register ADRH utilizes its full 8-bit con tents. The low byte register utilizes only 1 or 2 bits of its 8-bit contents as it contains only the lowest one or two bits of the 9 or 10-bit converted value.

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Chapter 1 Hardware Structure

In the following tables, D0~D8 or D9 are the A/D conversion data result bits.

ADRL

ADRH

ADRL

ADRH

A/D Converter Control Register - ADCR

To control the function and operation of the A/D converter, a control register known as ADCR is pro vided. This 8-bit register defines functions such as the selection of which analog channel is con nected to the internal A/D converter, which pins are used as analog inputs and which are used as normal I/Os as well as controlling and monitoring the A/D converter start and reset functions.

One section of this register contains the bits ACS2~ACS0 which define the channel number. As each of the devices contains only one actual analog to digital converter circuit, each of the individ ual 4 or 8 analog inputs must be routed to the converter. It is the function of the ACS2~ACS0 bits in the ADCR register to determine which analog channel is actually connected to the internal A/D converter. For the HT46R22/HT46C22, HT46R23/HT46C23 and HT46R24/HT46C24 devices which have eight analog input channels, the full three bits are required for channel selection, how ever, for the HT46R47/HT46C47 devices, which have only four analog input channels, bit ACS2 is not used and should be kept at a ²0² value. For the HT46R47/HT46C47 devices, if ACS2 is set to ²1² the function of ACS2~ACS0 will be undefined.

D8 D7 D6 D5 D4 D3 D2 D1

¾¾¾¾¾¾¾

A/D Data Register - HT46R47/HT46C47 and HT46R22/HT46C22

D1 D0

D9 D8 D7 D6 D5 D4 D3 D2

¾¾¾¾¾¾

A/D Data Register - HT46R23/HT46C23 and HT46R24/HT46C24

The ADCR control register also contains the PCR2~PCR0 bits which determine which pins on Port B are used as analog inputs for the A/D converter and which pins are to be used as normal I/Os. For the HT46R22/HT46C22, HT46R23/HT46C23 and HT46R24/HT46C24 devices which have eight analog input channels, the full three bits are required to fully configure the function of the bits on Port B. However, for the HT46R47/HT46C47 devices, which have only four analog input channels, if the 3-bit address on PCR2~PCR0 has a value of ²101² or higher, then the same function as the value ²100² will apply, that is AN0, AN1, AN2 and AN3 will all be set as analog in puts. Note that if the PCR2~PCR0 bits are all set to zero, then all the Port B pins will be setup as normal I/Os and the internal A/D converter circuitry will be powered off to reduce the power con sumption.

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A/D Type MCU

b 7 b 0

S T A R T

b 7 b 0

S T A R T

E O C B

P C R 2

P C R 1 P C R 0

A C S 2 A C S 1

A C S 2 A C S 1 A C S 0

A D C R R e g i s t e r ( e x c l u d i n g H T 4 6 R 4 7 / H T 4 6 C 4 7 )

A C S 0

S e l e c t A / D c h a n n e l

A C S 2

0 0 0 0 1 1 1 1

P o r t B A / D c h a n n e l c o n f i g u r a t i o n s

P C R 2

0 0 0 0 1 1 1 1

E n d o f A / D c o n v e r s i o n f l a g 1 : n o t e n d o f A / D c o n v e r s i o n - A / D c o n v e r s i o n w a i t i n g o r i n p r o g r e s s 0 : e n d o f A / D c o n v e r s i o n - A / D c o n v e r s i o n e n d e d

S t a r t t h e A / D c o n v e r s i o n 0

1 : R e s e t A / D c o n v e r t e r a n d s e t E O C B t o " 1 "

A D C R R e g i s t e r ( H T 4 6 R 4 7 / H T 4 6 C 4 7 )

S e l e c t A / D c h a n n e l

A C S 2

0 0 0 0 1

P o r t B A / D c h a n n e l c o n f i g u r a t i o n s

P C R 2

0 0 0 0 1

S t a r t t h e A / D c o n v e r s i o n 0

1 : R e s e t A / D c o n v e r t e r a n d s e t E O C B t o " 1 "

A C S 1

0 0 1 1 0 0 1 1

P C R 1

0 0 1 1 0 0 1 1

0 : S t a r t

A C S 1

P C R 1

0 : S t a r t

A C S 0

: A N 0

: A N 1

: A N 2

: A N 3

: A N 4

: A N 5

: A N 6

: A N 7

P C R 0

: P o r t B A / D c h a n n e l s - a l l o f f

: P B 0 e n a b l e d a s A N 0

: P B 0 ~ P B 1 e n a b l e d a s A N 0 ~ A N 1

: P B 0 ~ P B 2 e n a b l e d a s A N 0 ~ A N 2

: P B 0 ~ P B 3 e n a b l e d a s A N 0 ~ A N 3

: P B 0 ~ P B 4 e n a b l e d a s A N 0 ~ A N 4

: P B 0 ~ P B 5 e n a b l e d a s A N 0 ~ A N 5

: P B 0 ~ P B 7 e n a b l e d a s A N 0 ~ A N 7

A C S 0 0 0 1 1 X

0 0 1 1 X

: A N 0

: A N 1

: A N 2

: A N 3

: u n d e f i n e d , c a n n o t b e u s e d

P C R 0

: P o r t B A / D c h a n n e l s - a l l o f f

: P B 0 e n a b l e d a s A N 0

: P B 0 ~ P B 1 e n a b l e d a s A N 0 ~ A N 1

: P B 0 ~ P B 2 e n a b l e d a s A N 0 ~ A N 2

: P B 0 ~ P B 3 e n a b l e d a s A N 0 ~ A N 3

The START bit in the ADCR register is used to start and reset the A/D converter. When the microcontroller sets this bit from low to high and then low again, an analog to digital conversion cy cle willbe initiated. When the START bit is brought from low to high but not low again, the EOCBbit in the ADCR register will be set to a ²1² and the analog to digital converter will be reset. It is the START bit that is used to control the overall on/off operation of the internal analog to digital con verter.

The EOCB bit in the ADCR register is used to indicate when the analog to digital conversion pro cess is complete. This bit will be automatically set to ²0² by the microcontroller after a conversion cycle has ended. In addition, the corresponding A/D interrupt request flag will be set in the inter

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Chapter 1 Hardware Structure

rupt control register, and if the interrupts are enabled, an appropriate internal interrupt signal will be generated.This A/D internal interrupt signal will direct the program flow to the associated A/D in ternal interrupt address for processing. If the A/D internal interrupt is disabled, the microcontroller can be used to poll the EOCB bit in the ADCR register to check whether it has been cleared as an alternative method of detecting the end of an A/D conversion cycle.

A/D Converter Clock Source Register - ACSR

The clock source for the A/D converter, which originates from the system clock f by a division ratio, the value of which is determined by the ADCS1 and ADCS0 bits in the ACSR register.

b 7 b 0

T E S T

A D C S 1 A D C S 0

A C S R R e g i s t e r

S e l e c t A / D c o n v e r t e r c l o c k s o u r c e

A D C S 1

A D C S 0

N o t i m p l e m e n t e d , r e a d a s " 0 "

F o r t e s t m o d e u s e o n l y

, is first divided

SYS

: s y s t e m c l o c k / 2 : s y s t e m c l o c k / 8 : s y s t e m c l o c k / 3 2 : u n d e f i n e d

Although the A/D clock source is determined by the system clock f

, and by bits ADCS1 and

SYS

ADCS0, there are some limitations on the maximum A/D clock source speed that can be selected.

As the minimum value of permissible A/D clock period t

is 1ms, for system clock speeds in ex

cess of 2MHz, the ADCS1 and ADCS0 bits should not be set to ²00². Doing so will give A/D clock periods that are less than 1ms which may result in inaccurate A/D conversion values. Refer to the following table for examples, where values marked with an asterisk * are not permissible as they are less than the specified minimum A/D Clock Period.

A/D Clock Period (tAD)

SYS

ADCS1, ADCS0=00

SYS

1MHz

2MHz

4MHz 500ns*

8MHz 250ns*

2ms8ms32ms

1ms4ms16ms

/2)

ADCS1, ADCS0=01

/8)

SYS

2ms8ms

1ms4ms

ADCS1, ADCS0=10

/32)

SYS

ADCS1, ADCS0=11

Undefined

A/D Clock Period Examples

A/D Input Pins

All of the A/D analog input pins are pin-shared with the I/O pins on Port B. The PCR2~PCR0 bits in the ADCR register, not configuration options, determine whether the input pins are setup as nor mal Port B input/output pins or whether they are setup as analog inputs. In this way, pins can be changed under program control to change their function from normal I/O operation to analog in puts and vice versa. Pull-high resistors, which are setup through configuration options, apply to the input pins only when they are used as normal I/O pins, if setup as A/D inputs the pull-high resis tors will be automatically disconnected. Note that it is not necessary to first setup the A/D pin as an

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A/D Type MCU

input in the PBC port control register to enable the A/D input, when the PCR2~PCR0 bits enable an A/D input, the status of the port control register will be overridden. The VDD power supply pin is used as the A/D converter reference voltage, and as such analog inputs must not be allowed to ex ceed this value. Appropriate measures should also be taken to ensure that the VDD pin remains as stable and noise free as possible.

Summary of A/D Conversion Steps

The following summarizes the individual steps that should be executed in order to implement an A/D conversion process.

Step 1

Select which pins on Port B are to be used as A/D inputs and configure them as A/D input pins by correctly programming the PCR2~PCR0 bits in the ADCR register.

Step 2

Select which channel is to be connected to the internal A/D converter by correctly programming the ACS2~ACS0 bits which are also contained in the ADCR register.

Step 3

Select the required A/D conversion clock by correctly programming bits ADCS1 and ADCS0 in the ACSR register.

Step 4

If the interrupts are to be used, the interrupt control registers must be correctly configured to en sure the A/D converter interrupt function is active. Depending upon which device is used, the master interrupt control bit, EMI, in either the INTC or INTC0 interrupt control register must be set to ²1² and the A/D converter interrupt bit, EADI, in either the INTC, INTC0 or INTC1 register must also be set to ²1².

Note

· Step 5

The analog to digital conversion process can now be initialized by setting the START bit in the ADCR register to from ²0² to ²1² and then to ²0² again. Note that this bit should have been originally set to ²0².

· Step 6

To check when the analog to digital conversion process is complete, the EOCB bit in the ADCR register can be polled. The conversion process is complete when this bit goes low. When this occurs the A/D data registers ADRL and ADRH can be read to obtain the conversion value. As an alternative method if the interrupts are enabled and the stack is not full, the program can wait for an A/D interrupt to occur.

When checking for the end of the conversion process, if the method of polling the EOCB bit in the ADCR register is used, step 4 above can be omitted.

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Chapter 1 Hardware Structure

The following timing diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing.

M i n i m u m o n e i n s t r u c t i o n c y c l e n e e d e d

S T A R T

E O C B

P C R 2 ~ P C R 0

A C S 2 ~ A C S 0

0 0 0 B

P o w e r - o n R e s e t

1 : D e f i n e P B c o n f i g u r a t i o n 2 : S e l e c t a n a l o g c h a n n e l

A / D c l o c k m u s t b e f

N o t e :

R e s e t A / D c o n v e r t e r

A / D s a m p l i n g t i m e 3 2 t

A D

1 0 0 B

0 1 0 B

S t a r t o f A / D c o n v e r s i o n

E n d o f A / D c o n v e r s i o n

7 6 t

A D

A / D c o n v e r s i o n t i m e

/ 2 , f

/ 8 o r f

S Y S

/ 3 2

S Y S

A/D Conversion Timing

R e s e t A / D c o n v e r t e r

A / D s a m p l i n g t i m e 3 2 t

A D

1 0 0 B

0 0 0 B

S t a r t o f A / D c o n v e r s i o n

7 6 t

A / D c o n v e r s i o n t i m e

E n d o f A / D c o n v e r s i o n

A D

0 0 0 B

1 . P B p o r t s e t u p a s I / O s 2 . A / D c o n v e r t e r i s p o w e r e d o f f t o r e d u c e p o w e r c o n s u m p t i o n

d o n ' t c a r e

The setting up and operation of the A/D converter function is fully under the control of the applica tion program as there are no configuration options associated with the A/D converter. After an A/D conversion process has been initiated by the application program, the microcontroller internal hardware will begin to carry out the conversion, during which time the program can continue with other functions. There are two methods to determine when the A/D conversion process is complete. The first is for the application program to poll the EOCB bit in the ADCR register, while the second method is to await an A/D internal interrupt to occur. The following two short program examples illustrate both of these methods. Note that the program is based on the HT46R22/ HT46C22 devices.

Example: using EOCB Polling Method to detect end of conversion

clr INTC0.3 ; disable A/D interrupt in interrupt control

; register mov a,00100000B mov ADCR,a ; setup ADCR register to configure Port PB0~PB3

; as A/D inputs and select AN0 to be connected

; to the A/D converter mov a,00000001B mov ACSR,a ; setup the ACSR register to select f

; the A/D clock

SYS

/8 as

Start_conversion:

clr ADCR.7 set ADCR.7 ; reset A/D clr ADCR.7 ; start A/D

Polling_EOC:

sz ADCR.6 ; poll the ADCR register EOCB bit to detect end

; of A/D conversion jmp polling_EOC ; continue polling

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A/D Type MCU

mov a,ADRH ; read conversion result from the high byte

; ADRH register mov adrh_buffer,a ; save result to user defined register mov a,ADRL ; read conversion result from the low byte ADRL

; register mov adrl_buffer,a ; save result to user defined register

: :

jmp start_conversion ; start next A/D conversion

Example: using Interrupt method to detect end of conversion

set INTC0.0 ; interrupt global enable set INTC0.3 ; enable A/D interrupt in interrupt control

; register mov a,00100000B mov ADCR,a ; setup ADCR register to configure Port PB0~PB3

; as A/D inputs and select AN0 to be connected

; to the A/D converter mov a,00000001B mov ACSR,a ; setup the ACSR register to select f

; the A/D clock

SYS

start_conversion:

clr ADCR.7 set ADCR.7 ; reset A/D clr ADCR.7 ; start A/D

: :

; interrupt service routine EOC_service routine:

mov a_buffer,a ; save ACC to user defined register mov a,ADRH ; read conversion result from the high byte

; ADRH register mov adrh_buffer,a ; save result to user defined register mov a,ADRL ; read conversion result from the low byte ADRL

; register mov adrl_buffer,a ; save result to user defined register

clr ADCR.7 set ADCR.7 ; reset A/D clr ADCR.7 ; start A/D

mov a,a_buffer ; restore ACC from temporary storage reti

/8 as

A/D Transfer Function

As the HT46R47/HT46C47 and HT46R22/HT46C22 devices each contain a 9-bit A/D converter, their full-scale converted digitized value is equal to 1FFH. Since the full-scale analog input value is equal to the VDD voltage, this gives a single bit analog input value of V HT46R23/HT46C23 and HT46R24/HT46C24 devices, which each contain a 10-bit A/D converter, their full-scale converted digitized value is equal to 3FFH, giving a single bit analog input value of V

/1024. The following graphs show the ideal transfer function between the analog input value

and the digitized output value for both the 9-bit and 10-bit A/D converters.

/512. In the case of the

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Chapter 1 Hardware Structure

1 . 5 L S B

1 F F H

1 F E H

1 F D H

A / D C o n v e r s i o n R e s u l t

0 3 H

0 2 H

0 1 H

Ideal A/D Transfer Function - HT46R47/HT46C47 and HT46R22/HT46C22

A / D C o n v e r s i o n R e s u l t

3 F F H

3 F E H

3 F D H

0 3 H

0 2 H

0 1 H

0 . 5 L S B

1 2 3

0 . 5 L S B

2 3

5 1 0 5 1 1 5 1 2

5 0 9

A n a l o g I n p u t V o l t a g e

1 0 2 1

A n a l o g I n p u t V o l t a g e

1 . 5 L S B

1 0 2 2 1 0 2 3 1 0 2 4

D D

( )

5 1 2

( )

1 0 2 4

D D

Ideal A/D Transfer Function - HT46R23/HT46C23 and HT46R24/HT46C24

Note that to reduce the quantization error, a 0.5 LSB offset is added to the A/D Converter input. Except for the digitized value 0, the subsequent digitized values will change at a point 0.5 LSB below where they would change without the offset , and the last full scale digitized value will change at a point 1.5 LSB below the VDD.

The A/D Converter has a maximum of ±1

Integral Non-Linearity Error which describes the de

LSB parture from the ideal linear transfer function. For the HT46R47/HT46C47 and HT46R22/HT46C22, their 9-bit resolution A/D Converter is achieved with 8-bit accuracy while for the HT46R23/HT46C23 and HT46R24/HT46C24, their 10-bit resolution A/D Converter is achieved with 9-bit accuracy.

Page 63

I2C Bus Serial Interface

The I2C bus is a bidirectional 2-wire communication interface originally developed by Philips Semi conductors. The possibility of transmitting and receiving data on only 2 lines offers many new appli cation possibilities for microcontroller based applications and for this reason, with the exception of the HT46R47/HT46C47 devices, an I Holtek A/D MCU range. The I

A/D Type MCU

C bus is implemented in each of the microcontrollers in the

C bus function is selectable via a configuration option.

D a t a B u s

I2C D a t a R e g i s t e r

H T X

T r a n s m i t / R e c e i v e

S h i f t R e g i s t e r

C o n t r o l U n i t

S D A

S C L

D i r e c t i o n C o n t r o l

D a t a I n ( T o L S B ) D a t a O u t ( F r o m M S B )

M U

T X A K , E n a b l e / D i s a b l e A c k n o w l e d g e

There are two lines associated with the I

( H D R )

C bus, the first is known as SDA and is the Serial Data

S l a v e A d d r e s s R e g i s t e r

( H A D R )

A d d r e s s

C o m p a r a t o r

S R W , R e a d / w r i t e S l a v e

H C F , 8 - b i t D a t a C o m p l e t e

H B B , D e t e c t S t a r t o r S t o p

A d d r e s s M a t c h ( H A A S )

C I n t e r r u p t

line, the second is known as SCL line and is the Serial Clock line. As many devices may be con nected together on the same bus, their outputs are both open drain types. For this reason it is nec essary that external pull-high resistors are connected to these outputs. Note that no chip select line exists, as each device on the I ted and received on the I

C bus.

When two devices communicate with each other on the bidirectional I

C bus is identified by a unique address which will be transmit-

C bus, one is known as the master device and one as the slave device. Both master and slave can transmit and receive data, however, it is the master device that has overall control of the bus. For the Holtek microcontrollers, which only operate in slave mode, there are two methods of transferring data on the I slave transmit mode and the slave receive mode. Four registers exist to control the I associated data transfer, HADR, HCR, HSR and HDR. Communication on the I

C bus, the

C bus and its

C bus requires four steps, a START signal, a slave address transmission, a data transmission and finally a STOP signal.

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Chapter 1 Hardware Structure

I2C Bus Slave Address Register - HADR

The HADR register is the location where the slave address of the microcontroller is stored. Bits 1~7 ofthe HADR register define the microcontroller slave address. Bit 0 is not implemented. When a masterdevice, which is connected to the I address in the HADR register, the microcontroller slave device will be selected.

b 7 b 0

I2C Bus Input/Output Data Register - HDR

The HDRregister is the I2C businput/output data register. Before the microcontroller writes data to

the I

C bus, the actual data to be transmitted must be placed in the HDR register. After the data is received from the I of data to the I

C bus, the microcontroller can read it from the HDR register. Any transmission

C bus or reception of data from the I2C bus must be made via the HDR register.

I2C Bus Control Register - HCR

The I2C bus control register HCR contains three bits. Bit 7, known as the HEN bit, determines if the

C bus function is enabled or disabled, this bit must be set if the I2C bus requires data transfer. Bit 4, known as the HTX bit, determines whether the device is in the transmit mode or receive mode, and must be set high if the device is to be setup as a transmitter. Bit 3, known as the TXAK bit, is the transmit acknowledge bit. After the receipt of 8 bits of data, this bit will be transmitted to the I

bus on the 9th clock. To continue receiving more data, this bit has to be reset to ²0² before more data is received.

b 7 b 0

H E N T X A K

H T X

C bus,sends out an address which matches the slave

0 ) , 4  4 A C E I J A H

N o t i m p l e m e n t e d , r e a d a s " 0 "

S l a v e a d d r e s s

0 + 4  4 A C E I J A H

N o t i m p l e m e n t e d , r e a d a s " 0 "

T r a n s m i t a c k n o w l e d g e f l a g 1 : d o n ' t a c k n o w l e d g e 0 : a c k n o w l e d g e

T r a n s m i t / r e c e i v e m o d e 1 : t r a n s m i t m o d e 0 : r e c e i v e m o d e

N o t i m p l e m e n t e d , r e a d a s " 0 "

I2C B u s f u n c t i o n 1 : e n a b l e 0 : d i s a b l e

I2C Bus Status Register - HSR

The I2C bus register HSR is an 8-bit status register in which five bits are utilized. Bit 7, known as

HCF, is set to ²0² when a data byte is being transferred, after completion of the data transfer the bit

will be set to ²1². The HAAS bit, which is bit 6, will be set to ²1² if the transmitted address and the

slave address of the device match and if the I are enabled and the stack is not full, a subroutine call to 10H will occur. Writing data to the I

C interrupt request flag is set to ²1². If the interrupts

C bus

Page 65

A/D Type MCU

will clear the HAAS bit. Also, if the transmitted address on the bus and the slave address of the de vice do not match, then the HAAS bit will be reset to ²0².

Bit 5, known as HBB, will be set to ²1² if the I

C bus is busy, which will occur when a START signal

is detected. The HBB bit will be cleared to ²0² if the bus is free which will occur when a STOP sig nal is detected. Bit 2, which is the SRW or Slave Read/Write bit, determines whether the master de vice wishes to transmit or receive data from the I

C bus. When the transmitted address and slave

address match, that is when the HAAS bit is set to ²1², the device will check the SRW bit to deter mine whether it should be in transmit mode or receive mode. If the SRW bit is equal to ²1² the mas ter is requesting to read data from the bus, so the device should be in transmit mode. When the SRW bit is equal to ²0², the master will write data to the bus, therefore the device should be in re ceive mode to read this data.

b 7 b 0

H A A S

H C F H B B

S R W

H S R R e g i s t e r

R X A K

R e c e i v e a c k n o w l e d g e f l a g 1 : n o t a c k n o w l e d g e d 0 : a c k n o w l e d g e d

N o t i m p l e m e n t e d , r e a d a s " 0 " M a s t e r d a t a r e a d / w r i t e r e q u e s t f l a g

1 : r e q u e s t d a t a r e a d 0 : r e q u e s t d a t a w r i t e

N o t i m p l e m e n t e d , r e a d a s " 0 "

I2C B u s b u s y f l a g 1 : b u s y 0 : n o t b u s y

C a l l i n g a d d r e s s m a t c h e d f l a g 1 : m a t c h e d 0 : n o t m a t c h e d

D a t a t r a n s f e r f l a g 1 : t r a n s f e r c o m p l e t e 0 : t r a n s f e r n o t c o m p l e t e

Bit 0, is the Receive Acknowledge bit and known as RXAK. When the RXAK bit has been reset to ²0² it means that a correct acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. When in the transmit mode, the transmitter checks the RXAK bit to determine if the receiver wishes to receive the next byte. The transmitter will therefore continue sending out data until the RXAK bit is set to ²1². When this occurs, the transmitter will release the SDA line to allow the master to send a STOP signal to release the bus.

I2C Bus Communication

Communication on the I2C bus requires four separate steps, a START signal, a slave device ad dress transmission, a data transmission and finally a STOP signal. When a START signal is placed on the I arrival of data on the bus. The first seven bits of the data will be the slave address with the first bit being the MSB. If the address of the microcontroller matches that of the transmitted address, the HAAS bit in the HSR register will be set and an I terrupt service routine, the microcontroller slave device must first check the condition of the HAAS bit to determine whether the interrupt source originates from an address match or from the comple tion of an 8-bit data transfer. During a data transfer, note that after the 7-bit slave address has

C bus, all devices on the bus will receive this signal and be notified of the imminent

C interrupt will be generated. After entering the in

Page 66

Chapter 1 Hardware Structure

S T A R T s i g n a l

f r o m M a s t e r

S e n d s l a v e a d d r e s s

a n d R / W b i t f r o m M a s t e r

A c k n o w l e d g e

f r o m s l a v e

S e n d d a t a b y t e

f r o m M a s t e r

A c k n o w l e d g e

f r o m s l a v e

S T O P s i g n a l

f r o m M a s t e r

been transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the SRW bit. This bit will be checked by the microcontroller to determine whether to go into transmit or receive mode. Before any transfer of data to or from the I microcontroller must initialize the bus, the following are steps to achieve this:

Step 1

Write the slave address of the microcontroller to the I

Step 2

Set the HEN bit in the I

C bus control register to ²1² to enable the I2C bus.

· Step 3

Set the EHI bit of the interrupt control register to enable the I

C bus address register HADR.

C bus interrupt.

C bus, the

® Start Signal

The START signal can only be generated by the master device connected to the I by the microcontroller, which is only a slave device. This START signal will be detected by all devices connected to the I

C bus. When detected, this indicates that the I2C bus is busy and there-

fore theHBB bit will be set. A STARTcondition occurs when a high to low transition on the SDA line takes place when the SCL line remains high.

Slave Address

The transmission of a START signal by the master will be detected by all devices on the I To determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the START signal. All slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. If the address sent out by the master matches the internal address of the microcontroller slave device, then an internal I bus interrupt signal will be generated. The next bit following the address, which is the 8th bit, de fines the read/write status and will be saved to the SRW bit of the HSR register. The device will then transmit an acknowledge bit, which is a low level, as the 9th bit. The microcontroller slave de vice will also set the status flag HAAS when the addresses match.

As an I

C bus interrupt can come from two sources, when the program enters the interrupt subrou

tine, the HAAS bit should be examined to see whether the interrupt source has come from a

C bus and not

C bus.

Page 67

A/D Type MCU

matching slave address or from the completion of a data byte transfer. When a slave address is matched, the device must be placed in either the transmit mode and then write data to the HDR register, or in the receive mode where it must implement a dummy read from the HDR register to release the SCL line.

S R W

A C K

A C K S t o p

M D A D A P

S l a v e A d d r e s s

D a t a

0 1 0 1 0

S S A S R

S t a r t

S C L

S D A

S C L

S D A

S = S t a r t ( 1 b i t ) S A = S l a v e A d d r e s s ( 7 b i t s ) S R = S R W b i t ( 1 b i t ) M = S l a v e d e v i c e s e n d a c k n o w l e d g e b i t ( 1 b i t ) D = D a t a ( 8 b i t s ) A = A C K ( R X A K b i t f o r t r a n s m i t t e r , T X A K b i t f o r r e c e i v e r 1 b i t ) P = S t o p ( 1 b i t )

S S A S R

1 0 1 0 0 1 00

M D A D A

I2C Communication Timing Diagram

® SRW Bit

The SRW bit in the HSR register defines whether the microcontroller slave device wishes to read data from the I determine if it is to be a transmitter or a receiver. If the SRW bit is set to ²1² then this indicates that the master wishes to read data from the I

be setup to send data to the I the master wishes to send data to the I setup to read data from the I

C bus or write data to the I2C bus. The microcontroller should examine this bit to

C bus as a transmitter. If the SRW bit is ²0² then this indicates that

C bus as a receiver.

C bus, therefore the microcontroller slave device must

C bus, therefore the microcontroller slave device must be

Acknowledge Bit

After the master has transmitted a calling address, any slave device on the I

C bus, whose own in ternal address matches the calling address, must generate an acknowledge signal. This acknowl edge signal will inform the master that a slave device has accepted its calling address. If no acknowledge signalis received by the master then a STOP signal must be transmitted by the mas ter to end the communication. When the HAAS bit is high, the addresses have matched and the microcontroller slave device must check the SRW bit to determine if it is to be a transmitter or a re ceiver. If the SRW bit is high, the microcontroller slave device should be setup to be a transmitter so the HTX bit in the HCR register should be set to ²1², if the SRW bit is low then the microcontroller slave device should be setup as a receiver and the HTX bit in the HCR register should be set to ²0².

Page 68

Chapter 1 Hardware Structure

Data Byte

The transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged re ceipt of its slave address. The order of serial bit transmission is the MSB first and the LSB last. Af ter receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level ²0², before it can receive the next data byte. If the transmitter does not receive an acknowledge bit signal from the receiver, then it will release the SDA line and the master will send out a STOP signal to release control of the I transmitter, the microcontroller slave device must first write the data to be transmitted into the HDR register. If setup as a receiver, the microcontroller slave device must read the transmitted data from the HDR register.

C bus. The corresponding data will be stored in the HDR register. If setup as a

S C L

S D A

S t a r t b i t D a t a

s t a b l e

D a t a a l l o w c h a n g e

S t o p b i t

Data Timing Diagram

Receive Acknowledge Bit

When the receiver wishes to continue to receive the next data byte, it must generate an acknowl edge bit, known as TXAK, on the 9th clock. The microcontroller slave device, which is setup as a transmitter will check the RXAK bit in the HSR register to determine if it is to send another data byte, ifnot then it will release the SDA lineand await the receipt of a STOP signal from the master.

S t a r t

W r i t e S l a v e

A d d r e s s t o H A D R

S E T H E N

C L R E H I

P o l l H I F t o d e c i d e

w h e n t o g o t o I

C B u s I S R

I2C B u s I n t e r r u p t = ?

E n a b l eD i s a b l e

S E T E H I

W a i t f o r I n t e r r u p t

G o t o M a i n P r o g r a m

I2C Bus Initialization Flow Chart

G o t o M a i n P r o g r a m

Page 69

S t a r t

A/D Type MCU

Interrupts

N o

R e a d f r o m H D R

R E T I

C L R T X A K

D u m m y R e a d

C L R H T X

f r o m H D R

R E T I

H T X = 1 ?

N o

Y e s

R X A K = 1

N o

W r i t e t o H D R

R E T I

H A A S = 1

W r i t e t o H D R

Y e s

S R W = 1 ?

S E T H T X

R E T I R E T I

C L R T X A K

D u m m y R e a d

N o

C L R H T X

F r o m H D R

I2C Bus ISR Flow Chart

The A/D series of microcontrollers each contain a range of both external and internal interrupt functions. The external interrupt is controlled by the action of the external pin INT all devices. Internal functions such as the timer counter, A/D converter and I

which is present on

C interface all utilize

the internal interrupt function for their operation.

For the HT46R47/HT46C47 devices, which do not contain an internal I

C interface and contain only a single timer, one 8-bit interrupt control register, known as INTC, is sufficient to control all the required operations.As the HT46R22/HT46C22, HT46R23/HT46C23 and HT46R24/HT46C24 de vices both contain an I

C interface, a single 8-bit interrupt control register is insufficient to control all theinterrupt control features. For this reason two interrupt control registers are provided, known as INTC0 and INTC1.

Once an interrupt subroutine is serviced, all the other interrupts will be blocked, by clearing the EMI bit. This scheme may prevent any further interrupt nesting. Other interrupt requests may oc cur during this interval but only the interrupt request flag is recorded. If another interrupt requires servicing while the program is in the interrupt service routine, the EMI bit should be set after enter ing theroutine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowl edged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must be prevented from becoming full.

Page 70

Chapter 1 Hardware Structure

b 7 b 0

E I F T F

b 7 b 0

E A D IA D F

E T I E E I E M I

I N T C R e g i s t e r H T 4 6 R 4 7 / H T 4 6 C 4 7 I N T C 0 R e g i s t e r H T 4 6 R 2 2 / H T 4 6 C 2 2 H T 4 6 R 2 3 / H T 4 6 C 2 3

M a s t e r I n t e r r u p t g l o b a l e n a b l e 1 : g l o b a l e n a b l e 0 : g l o b a l d i s a b l e

E x t e r n a l i n t e r r u p t e n a b l e 1 : e n a b l e 0 : d i s a b l e T i m e r / E v e n t C o u n t e r i n t e r r u p t e n a b l e 1 : e n a b l e 0 : d i s a b l e

A / D C o n v e r t e r i n t e r r u p t e n a b l e 1 : e n a b l e 0 : d i s a b l e

E x t e r n a l i n t e r r u p t r e q u e s t f l a g 1 : a c t i v e 0 : i n a c t i v e T i m e r / E v e n t C o u n t e r i n t e r r u p t r e q u e s t f l a g 1 : a c t i v e 0 : i n a c t i v e A / D c o n v e r t e r r e q u e s t f l a g 1 : a c t i v e 0 : i n a c t i v e

N o t i m p l e m e n t e d , r e a d a s " 0 "

I N T C 1 R e g i s t e r H T 4 6 R 2 2 / H T 4 6 C 2 2

E H IH I F

H T 4 6 R 2 3 / H T 4 6 C 2 3

I2C B u s I n t e r r u p t e n a b l e 1 : e n a b l e 0 : d i s a b l e

N o t i m p l e m e n t e d , r e a d a s " 0 "

C B u s i n t e r r u p t r e q u e s t f l a g

I 1 : a c t i v e 0 : i n a c t i v e

N o t i m p l e m e n t e d , r e a d a s " 0 "

Differing from the other devices in the A/D series, the HT46R24/HT46C24 devices contain two internal timer counters. Although all the interrupt control functions can still be controlled by two interrupt control registers, also known as INTC0 and INTC1, they have a slightly different structure from the other devices.

Page 71

A/D Type MCU

The external interrupt has the capability of waking up the processor when in the HALT mode. As an interrupt is serviced, a control transfer occurs by pushing the Program Counter onto the stack, followed by a branch to a subroutine at a specified location in the Program Memory. Only the Pro gram Counter is pushed onto the stack. If the contents of the accumulator, status register or other registers are altered by the interrupt service routine, which may corrupt the desired control se quence, then the contents should be saved in advance.

b 7 b 0

A D F H I F

E T 0 I E E I E M IE I F T 0 F

E T 1 IT 1 F

E H I

I N T C 0 R e g i s t e r H T 4 6 R 2 4 / H T 4 6 C 2 4

M a s t e r I n t e r r u p t g l o b a l e n a b l e 1 : g l o b a l e n a b l e 0 : g l o b a l d i s a b l e

E x t e r n a l i n t e r r u p t e n a b l e 1 : e n a b l e 0 : d i s a b l e

T i m e r / E v e n t C o u n t e r 0 i n t e r r u p t e n a b l e 1 : e n a b l e 0 : d i s a b l e

T i m e r / E v e n t C o u n t e r 1 i n t e r r u p t e n a b l e 1 : e n a b l e 0 : d i s a b l e

E x t e r n a l i n t e r r u p t r e q u e s t f l a g 1 : a c t i v e 0 : i n a c t i v e

T i m e r / E v e n t C o u n t e r 0 i n t e r r u p t r e q u e s t f l a g 1 : a c t i v e 0 : i n a c t i v e

T i m e r / E v e n t C o u n t e r 1 i n t e r r u p t r e q u e s t f l a g 1 : a c t i v e 0 : i n a c t i v e

N o t i m p l e m e n t e d , r e a d a s " 0 "

E A D I

I N T C 1 R e g i s t e r H T 4 6 R 2 4 / H T 4 6 C 2 4

A / D C o n v e r t e r I n t e r r u p t e n a b l e 1 : e n a b l e 0 : d i s a b l e

I2C B u s I n t e r r u p t 1 : e n a b l e 0 : d i s a b l e

N o t i m p l e m e n t e d , r e a d a s " 0 "

A / D C o n v e r t e r r e q u e s t f l a g 1 : a c t i v e 0 : i n a c t i v e

C B u s I n t e r r u p t r e q u e s t f l a g

I 1 : a c t i v e 0 : i n a c t i v e

N o t i m p l e m e n t e d , r e a d a s " 0 "

Page 72

Chapter 1 Hardware Structure

The various interrupt enable bits, together with their associated request flags, are shown in the fol lowing diagram with their order of priority.

A u t o m a t i c a l l y C l e a r e d b y I S R

M a n u a l l y S e t o r C l e a r e d b y S o f t w a r e

E x t e r n a l I n t e r r u p t R e q u e s t F l a g E I F

T i m e r / E v e n t C o u n t e r 0

I n t e r r u p t R e q u e s t F l a g T 0 F

T i m e r / E v e n t C o u n t e r 1

I n t e r r u p t R e q u e s t F l a g T 1 F

A / D C o n v e r t e r

I n t e r r u p t R e q u e s t F l a g A D F

I n t e r r u p t R e q u e s t F l a g H I F

In the figure, the T1F interrupt request flag and the ET1I interrupt enable bit refer to the HT46R24/

Note

C B u s

A u t o m a t i c a l l y D i s a b l e d b y I S R

C a n b e E n a b l e d M a n u a l l y

E E I

E T 0 I

E T 1 I

E A D I

E H I

E M I

P r i o r i t y

H i g h

L o w

HT46C24 devices, which have two timers. For the HT46R47/HT46C47, HT46R22/HT46C22 and HT46R23/HT46C23, which only have one timer, the Timer/Event Counter 0 represents the single timer, known as TMR and has interrupt request flag known as TF and enable bit known as ETI.

External Interrupt

For an external interrupt to occur, the corresponding external interrupt enable bit must be first set. This is bit 1 of the INTC or INTC0 register and shown as EEI. An external interrupt is triggered by a high to low transition of the INT INTC or INTC0) will be set. When the interrupt is enabled, the stack is not full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag EIF will be reset and the EMI bit will be cleared to disable other interrupts.

line, after which the related interrupt request flag (EIF; bit 4 of the

I n t e r r u p t

P o l l i n g

Timer/Event Counter Interrupt

For a timer generated internal interrupt to occur, the corresponding internal interrupt enable bit must befirst set. In the case of devices with a single timer, this is bit 2 of the INTC or INTC0 register and is known as ETI. For devices with two timers, the Timer 0 interrupt enable is bit 2 and known as ET0I while the Timer 1 interrupt enable is bit 3 and known as ET1I. An actual Timer/Event Coun ter interruptwill be initialized when the Timer/Event Counter interrupt request flag is set, caused by a timer overflow. In the case of devices with a single timer, this is bit 5 of the INTC or INTC0 regis ter and is known as TF. In the case of devices with two timers, the Timer 0 request flag is bit 5 and known as T0F, while the Timer 1 request flag is bit 6 and known as T1F. When the master interrupt global enable bit is set, the stack is not full and the corresponding internal interrupt enable bit is set, an internal interrupt will be generated when the timer overflows. This will create a subroutine call to location 08H for devices with a single timer. For devices with two timers, a subroutine call to location 08H will occur for Timer 0 and a subroutine call to location 0CH for Timer 1. When an inter

Page 73

A/D Type MCU

nal interrupt occurs, the interrupt request flag, TF, T0F or T1F will be reset and the EMI bit will be cleared to disable other interrupts.

A/D Interrupt

For an A/D interrupt to occur, the corresponding interrupt enable bit EADI must be first set. For the HT46R47/HT46C47 devices, this is bit 3 of the INTC register, while for the HT46R22/HT46C22 and HT46R23/HT46C23devices, this is bit 3 of the INTC0 register. For the HT46R24/HT46C24 de vices, this is bit 0 of the INTC1 register. An actual A/D interrupt will be initialized when the A/D con verter request flag ADF is set, a situation that will occur when an A/D conversion process has completed. In the case of the HT46R47/HT46C47 devices, this is bit 6 of the INTC register, while for the HT46R22/HT46C22 and HT46R23/HT46C23 devices, this is bit 6 of the INTC0 register. For the HT46R24/HT46C24 devices, this is bit 4 of the INTC1 register. When the master interrupt global enable bit is set, the stack is not full and the corresponding A/D interrupt enable bit is set, an internal interrupt will be generated when the previously requested A/D conversion process fin ishes. With the exception of the HT46R24/HT46C24 devices, this will create a subroutine call to lo cation 0CH. For the HT46R24/HT46C24 devices, a subroutine call to location 10H will be created. When an A/D interrupt occurs, the interrupt request flag ADF will be reset and the EMI bit will be cleared to disable other interrupts.

I2C Interrupt

For an I2C interrupt to occur, the corresponding interrupt enable bit EHI must be first set. For the HT46R22/HT46C22 and HT46R23/HT46C23 devices, this is bit 0 of the INTC1 register, while for the HT46R24/HT46C24 devices, this is bit 1 of the INTC1 register. An actual I tialized when the I

C slave address is received or from the completion of an I2C data byte transfer. In the case of the

C interrupt request flag HIF is set, a situation that will occur when a matching

HT46R22/HT46C22 and HT46R23/HT46C23 devices, this is bit 4 of the INTC1 register, while for the HT46R24/HT46C24 devices, this is bit 5 of the INTC1 register. Note that as the HT46R47/HT46C47 devices do not contain an I has no associated I the stack is not full and the corresponding I generated when a matching I

C enable bit or request flag. When the master interrupt global enable bit is set,

C slave address is received or from the completion of an I2C data

C interface, their interrupt control register INTC

C interrupt enable bit is set, an internal interrupt will be

byte transfer. For the HT46R22/HT46C22 and HT46R23 HT46C23 devices, this will create a subroutine call to location 10H, while for the HT46R24/HT46C24 devices, a subroutine call to location 14H will be created. When an I

C interrupt occurs, the interrupt request flag HIF will be reset and

the EMI bit will be cleared to disable other interrupts.

C interrupt will be ini

Interrupt Priority

Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In case of simultaneous requests,the following table shows the priority that is applied. These can be masked by resetting the EMI bit.

Interrupt Source

External Interrupt 1111

HT46R47 HT46C47

Priority

HT46R22 HT46C22

Priority

HT46R23 HT46C23

Priority

HT46R24 HT46C24

Priority

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Chapter 1 Hardware Structure

Interrupt Source

TMR/TMR0 Overflow 2222

TMR1 Overflow N/A N/A N/A 3

A/D Converter Interrupt 3334

C Bus Interrupt N/A 4 4 5

HT46R47 HT46C47

Priority

HT46R22 HT46C22

Priority

HT46R23 HT46C23

Priority

HT46R24 HT46C24

Priority

Note Only the HT46R24/HT46C24 devices have two internal timers, known as TMR0 and TMR1. The

other devices in the series have only one internal timer, which is known as TMR.

In cases where both external and internal interrupts are enabled and where an external and inter nal interrupt occurs simultaneously, the external interrupt will always have priority and will there fore be serviced first. Suitable masking of the individual interrupts using the INTC register can prevent simultaneous occurrences.

Programming Considerations

The interrupt request flags, TF, T0F, T1F, EIF, ADF and HIF together with the interrupt enable bits ETI, ET0I, ET1I, EEI, EADI and EHI form the interrupt control registers INTC, INTC0 and INTC1, which are located in the Data Memory. By disabling the interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the INTC, INTC0 or INTC1 register until the corresponding interrupt is serviced or until the request flag is cleared by a software instruction.

It is recommended that programs do not use the ²CALLsubroutine² instruction within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and the interrupt is not well controlled, the original control sequencewill be damaged once a ²CALLsubroutine² is executed in the interrupt subroutine.

Reset and Initialization

A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condi tion is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address.

In addition to the power-on reset, situations may arise where it is necessary to forcefully apply a re set condition when the microcontroller is running. One example of this is where after power has been applied and the microcontroller is already running, the RES such a case, known as a normal operation reset, some of the microcontroller registers remain un changed allowing the microcontroller to proceed with normal operation after the reset line is al

line is forcefully pulled low. In

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A/D Type MCU

lowed to return high. Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup.

Another reset exists in the form of a Low Voltage Reset, LVR, where a full reset, similar to the RES reset isimplemented in situations where the power supply voltage falls below a certain threshold.

Reset

There are five ways in which a microcontroller reset can occur, through events occurring both inter nally and externally:

Power-on Reset

The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. As well as ensuring that the Program Memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs.

Although the microcontroller has an internal RC reset function, due to unstable power on condi tions, an external RC network connected to the RES lay created by the RC network ensures that the RES

pin is generally recommended. This time de

pin remains low for an extended period while the power supply stabilizes. During this time, normal operation of the microcontroller is inhibited. After the RES

line reaches a certain voltage value, the reset delay time t

is invoked to provide

RSTD

an extra delay time after which the microcontroller can begin normal operation. The abbreviation SST in the figures stands for System Start-up Timer.

V D D

R E S

S S T T i m e - o u t

I n t e r n a l R e s e t

0 . 9 V

D D

R S T D

Power-On Reset Timing Chart

RES Pin Reset

This type of reset occurs when the microcontroller is already running and the RES pulled low by external hardware such as an external switch. In this case as in the case of other re set, the Program Counter will reset to zero and program execution initiated from this point.

0 . 9 V

R E S

S S T T i m e - o u t

0 . 4 V

D D

R S T D

pin is forcefully

I n t e r n a l R e s e t

RES Reset Timing Chart

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Chapter 1 Hardware Structure

Low Voltage Reset - LVR

The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. Ifthe supply voltage of the device drops to within a range of 0.9V~V when changingthe battery, the LVR will automatically reset the device internally. The LVR includes the following specifications: For a valid LVR signal, a low voltage, i.e. a voltage in the range be tween 0.9V~V

must exist for greater than 1ms. If the low voltage state does not exceed 1ms,

LVR

the LVR will ignore it and will not perform a reset function.

E x t e r n a l E v e n t

such asmight occur

LVR

I n c r e m e n t

T i m e r C o u n t e r

T i m e r + 1

T i m e r + 2 T i m e r + 3

Low Voltage Reset Timing Chart

Watchdog Time-out Reset during Normal Operation

The Watchdog Time-out Reset during normal operation is the same as RES

reset except that the

Watchdog Time-out flag TO will be set to 1.

W D T T i m e - o u t

S S T T i m e - o u t

I n t e r n a l R e s e t

R S T D

WDT Time-out Reset during Normal Operation Timing Chart

® Watchdog Time-out Reset during HALT

The Watchdog Time-out Reset during HALT is a little different from other kinds of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to 0 and the TO flag will be set to 1. Refer to the A.C. Characteristics for t

W D T T i m e - o u t

S S T

S S T T i m e - o u t

WDT Time-out Reset during HALT Timing Chart

SST

details.

The different types of resets described affect the reset flags in different ways. These flags known as PDF and TO are located in the status register and are controlled by various microcontroller op erations such as the HALT function or Watchdog Timer. The reset flags are shown in the table:

0 0 RES

u u RES

1 u WDT time-out reset during normal operation

1 1 WDT time-out reset during HALT

²u² stands for unchanged

PDF

reset during power on

or LVR reset during normal operation

RESET Conditions

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A/D Type MCU

The following table indicates the way in which the various components of the microcontroller are af fected after a power-on reset occurs.

Item Condition After RESET

Program Counter Reset to zero

Interrupts All interrupts will be disabled

WDT

Timer/Event Counter All Timer Counters will be turned off

Prescaler

Input/Output Ports All I/O ports will be setup as inputs

Stack Pointer Stack pointer will point to the top of the stack

Clear after reset, WDT begins counting

The Timer Counter Prescaler will be cleared

The different kinds of reset all affect the internal registers of the microcontroller in different ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table de scribes how each type of reset affects each of the microcontroller internal registers.

HT46R47/HT46C47

ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu

PCL

TBLP

TBLH

STATUS

INTC

TMR

TMRC

PA 1111 1111 1111 1111 1111 1111 uuuu uuuu

PAC 1111 1111 1111 1111 1111 1111 uuuu uuuu

PBC

PDC

PWM

ADRL

ADRH

ADCR

ACSR

²u² stands for unchanged ²x² stands for unknown ²-² stands for unimplemented

Reset

(Power On)

- xxx xxxx - uuu uuuu - uuu uuuu - uuu uuuu

0000 0000 0000 0000 0000 0000 0000 0000

xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu

--xx xxxx --uu uuuu --uu uuuu --uu uuuu

--00 xxxx --uu uuuu --1u uuuu --11 uuuu

- 000 0000 - 000 0000 - 000 0000 - uuu uuuu

xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

00- 0 1000 00- 0 1000 00- 0 1000 uu- u uuuu

- - - - 1111 - - - - 1111 - - - - 1111 - - - - uuuu

--- - ---1 --- - ---1 --- - ---1 --- - ---u

xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

x -- - ---- x -- - ---- x -- - ---- u -- - ----

xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

0100 0000 0100 0000 0100 0000 uuuu uuuu

1 - - - - - 00 1- - - - - 00 1- - - - - 00 u- - - - - uu

RES

or LVR

Reset

Time-out

WDT

(Normal Operation)

WDT

Time-out

(HALT)

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Chapter 1 Hardware Structure

HT46R22/HT46C22

ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu

PCL

TBLP

TBLH

STATUS

INTC0

INTC1

TMR

TMRC

PA 1111 1111 1111 1111 1111 1111 uuuu uuuu

PAC

PB 1111 1111 1111 1111 1111 1111 uuuu uuuu

PBC

PCC

PDC

PWM

HADR

HCR

HSR

HDR

ADRL

ADRH

ADCR

ACSR

²u² stands for unchanged ²x² stands for unknown ²-² stands for unimplemented

Reset

(Power On)

- xxx xxxx - uuu uuuu - uuu uuuu - uuu uuuu

0000 0000 0000 0000 0000 0000 0000 0000

xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu

--xx xxxx --uu uuuu --uu uuuu --uu uuuu

--00 xxxx --uu uuuu --1u uuuu --11 uuuu

- 000 0000 - 000 0000 - 000 0000 - uuu uuuu

---0 ---0 ---0 ---0 ---0 ---0 ---u ---u

xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

00- 0 1000 00- 0 1000 00- 0 1000 uu- u uuuu

1111 1111 1111 1111 1111 1111 uuuu uuuu

--- - --11 --- - --11 --- - --11 --- - --uu

--- - ---1 --- - ---1 --- - ---1 --- - ---u

xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

xxxx xxx- xxxx xxx- xxxx xxx- uuuu uuu-

0 - - 00--- 0 - - 00--- 0 - - 00--- u - - uu---

100--0 - 1 100--0 - 1 100--0 - 1 uuu--u - u

xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

x -- - ---- x -- - ---- x -- - ---- u -- - ----

xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

0100 0000 0100 0000 0100 0000 uuuu uuuu

1 - - - - - 00 1- - - - - 00 1- - - - - 00 u- - - - - uu

RES

or LVR

Reset

WDT Time-out

(Normal Operation)

WDT

Time-out

(HALT)

Page 79

A/D Type MCU

HT46R23/HT46C23

MP0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu

MP1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu

ACC

PCL

TBLP

TBLH

STATUS

INTC0

INTC1

TMRL

TMRH

TMRC

PA 1111 1111 1111 1111 1111 1111 uuuu uuuu

PAC 1111 1111 1111 1111 1111 1111 uuuu uuuu

PB 1111 1111 1111 1111 1111 1111 uuuu uuuu

PBC

PCC

PDC

PWM0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

PWM1 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

HADR

HCR

HSR

HDR

ADRL

ADRH

ADCR

ACSR

²u² stands for unchanged ²x² stands for unknown ²-² stands for unimplemented

Reset

(Power On)

xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu

0000 0000 0000 0000 0000 0000 0000 0000

xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu

- xxx xxxx - uuu uuuu - uuu uuuu - uuu uuuu

--00 xxxx --uu uuuu --1u uuuu --11 uuuu

- 000 0000 - 000 0000 - 000 0000 - uuu uuuu

---0 ---0 ---0 ---0 ---0 ---0 ---u ---u

xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

00- 0 1000 00- 0 1000 00- 0 1000 uu- u uuuu

1111 1111 1111 1111 1111 1111 uuuu uuuu

---1 1111 ---1 1111 ---1 1111 ---u uuuu

--- - --11 --- - --11 --- - --11 --- - --uu

xxxx xxx- xxxx xxx- xxxx xxx- uuuu uuu0 - - 00--- 0 - - 00--- 0 - - 00--- u - - uu--100--0 - 1 100--0 - 1 100--0 - 1 uuu--u - u

xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xx- - ---- xx- - ---- xx- - ---- uu-- ----

xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

0100 0000 0100 0000 0100 0000 uuuu uuuu

1 - - - - - 00 1- - - - - 00 1- - - - - 00 u- - - - - uu

RES

or LVR

Reset

Time-out

WDT

(Normal Operation)

WDT

Time-out

(HALT)

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Chapter 1 Hardware Structure

HT46R24/HT46C24

MP0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu

MP1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu

ACC

PCL

TBLP

TBLH

STATUS

INTC0

INTC1

TMR0H xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

TMR0L xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

TMR0C

TMR1H xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

TMR1L xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

TMR1C

PAC

PBC

PCC

PDC

PFC

PWM0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

PWM1 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

PWM2 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

PWM3 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

HADR

HCR

HSR

HDR

ADRL

ADRH

ADCR

ACSR

²u² stands for unchanged ²x² stands for unknown ²-² stands for unimplemented

Reset

(Power On)

xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu

0000 0000 0000 0000 0000 0000 0000 0000

---- ---0 ---- ---0 ---- ---0 ---- ---u

xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu

--00 xxxx --uu uuuu --1u uuuu --11 uuuu

- 000 0000 - 000 0000 - 000 0000 - uuu uuuu

--00 --00 --00 --00 --00 --00 --uu --uu

00- 0 1000 00- 0 1000 00- 0 1000 uu- u uuuu

00- 01--- 00- 01--- 00- 01--- uu- uu---

1111 1111 1111 1111 1111 1111 uuuu uuuu

xxxx xxx- xxxx xxx- xxxx xxx- uuuu uuu0 - - 00--- 0 - - 00--- 0 - - 00--- u - - uu--100--0 - 1 100--0 - 1 100--0 - 1 uuu--u - u

xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xx- - ---- xx- - ---- xx- - ---- uu-- ----

xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

0100 0000 0100 0000 0100 0000 uuuu uuuu

1 - - - - - 00 1- - - - - 00 1- - - - - 00 u- - - - - uu

RES

or LVR

Reset

Time-out

WDT

(Normal Operation)

WDT

Time-out

(HALT)

Page 81

Oscillator

A/D Type MCU

Various oscillator options offer the user a wide range of functions according to their various applica tion requirements. Two types of system clocks can be selected while various clock source options for the Watchdog Timer are provided for maximum flexibility. All oscillator options are selected through the configuration options.

System Clock Configurations

There are two methods of generating the system clock, using an external crystal/ceramic oscilla tor oran external RC network. The chosen method is selected through the configuration options.

System Crystal/Ceramic Oscillator

For the crystal oscillator configuration, the simple connection of a crystal across OSC1 and OSC2 will create the necessary phase shift and feedback for oscillation with no other external compo nents required. A ceramic resonator can be used instead of a crystal but two small value capaci tors should be connected between OSC1, OSC2 and ground.

C 1

R 1

O S C 1

C 2

Crystal/Ceramic Oscillator

The table below shows the C1, C2 and R1 values for various crystal/ceramic oscillating frequencies.

Crystal or Resonator C1, C2 R1

4MHz Crystal 0pF

4MHz Resonator 10pF

3.58MHz Crystal 0pF

3.58MHz Resonator 25pF

2MHz Crystal & Resonator 25pF

1MHz Crystal 35pF

480kHz Resonator 300pF

455kHz Resonator 300pF

429kHz Resonator 300pF

The function of the resistor R1 is to ensure that the oscillator will switch off should low voltage conditions occur. Such a low voltage, as mentioned here, is one which is less than the lowest value of the MCU operating voltage. Note however that if the LVR is enabled then R1 can be re moved.

O S C 2

10kW 12kW 10kW 10kW 10kW 27kW

9.1kW 10kW 10kW

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Chapter 1 Hardware Structure

System RC Oscillator

Using the external RC network as an oscillator requires that a resistor, with a value between 30kW and 750kW, is connected between OSC1 and GND. The generated system clock divided by 4 will be provided on OSC2 as an output which can be used for external synchronization purposes. Al though this is a cost effective oscillator configuration, the oscillation frequency can vary with VDD, temperature and process variations on the chip itself and is therefore not suitable for applications where timing is critical or where accurate oscillator frequencies are required. For the value of the external resistor R ture and V

characteristics graphics.

please refer to the Appendix section for typical RC Oscillator vs. Tempera

OSC

D D

4 7 0 p F

O S C 1

O S C

/ 4 N M O S O p e n D r a i n

S Y S

RC Oscillator

Note

An internal capacitor together with the external resistor, R mine the frequency of the oscillator. The external capacitor shown on the diagram does not influ ence the frequency of oscillation. This external capacitor should be added to improve oscillator stability if the open-drain OSC2 output is utilized in the application circuit.

Watchdog Timer Oscillator

The WDT oscillator is a fully self-contained free running on-chip RC oscillator with a typical period of 65ms at 5V requiring no external components. When the device enters the power down mode, the system clock will stop running but the WDT oscillator continues to free-run and to keep the watchdog active. However, to preserve power in certain applications the WDT oscillator can be disabled via a configuration option.

HALT and Wake-up in Power Down Mode

The HALT mode is initialized by the ²HALT² instruction and results in the following:

The system oscillator will be turned off

The contents of the on chip RAM and registers remain unchanged

The WDT will be cleared and resume counting if the WDT clock source is selected to come from the WDT oscillator

All of the I/O ports remain unchanged

The

flag is set and the TO flag is cleared

PDF

O S C 2

, are the components which deter

OSC

Page 83

A/D Type MCU

When the system enters the HALT mode the system oscillator will be stopped to reduce power con sumption. However, it is important to remember that if the internal WDT oscillator is enabled this will keep running and result in a small amount of power being consumed. In addition if the A/D con verter is used, even though the system oscillator has been stopped there will still be some power consumption associated with the A/D circuitry. Therefore to minimize power consumption when in the HALT mode, the A/D converter should be first disabled by clearing all the PCR bits in the ADCR register.

The system can leave the HALT mode by means of a reset, an external interrupt, an external fall ing edge signal on Port A or a WDT overflow. A reset will initialize a chip reset and a WDT overflow will initialize a WDT time-out Reset from HALT but by examining the TO and PDF flags the source of the reset can be determined. The PDF flag is cleared by a system power-up or executing the ²CLR WDT² instruction and is set when executing the ²HALT² instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and SP; the other flags remain in their original status.

Port A wake-up and external interrupt wake-up methods can be considered as a continuation of normal execution. Each bit in Port A can be independently selected to wake-up the device by con figuration option. Awakening from an I/O port stimulus, the program will resume execution at the next instruction. If the system is woken up via an external interrupt, two possibilities may occur. If the external interrupt is disabled or the external interrupt is enabled but the stack is full, the pro gram will resume execution at the next instruction. If the external interrupt is enabled and the stack is not full, the regular interrupt response takes place. If the external interrupt request flag is set to ²1² before entering the HALT mode, the wake-up function of the related interrupt will be disabled. Once a wake-up event occurs, it takes 1024 system clock periods to resume normal operation. In other words, a dummy period will be inserted after a wake-up. If the wake-up results from an exter nal interrupt acknowledge signal, the actual interrupt subroutine execution will be delayed by one or more cycles. If the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished.

Watchdog Timer

The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. It operates by providing a ²chip reset² when the WDT counter overflows. The WDT clock is supplied by one of two sources selected by configuration option: its own self contained dedicated internal WDT oscillator or the instruction clock which is the system clock divided by 4. Note that if the WDT configuration option has been disabled, then any instruction relating to its operation will result in no operation.

In the A/D series of microcontrollers, all watchdog timer options, such as enable/disable, WDT clock source, and if applicable clock source division ratios are all selected through configuration options. There are no internal registers associated with the WDT in the A/D series. One of the WDT clock sources is an internal oscillator which has an approximate period of 65ms at a supply voltage of 5V. However, it should be noted that this specified internal clock period can vary with VDD, temperature and process variations. The other WDT clock source option is the instruction clock which is the system clock divided by four (f from its own internal WDT oscillator, or from the instruction clock, it is further divided by an internal

/4). Whether the WDT clock source comes

SYS

Page 84

Chapter 1 Hardware Structure

counter togive longer watchdog time-outs. In the case of the HT46R47/HT46C47 devices, this divi sion ratio is fixed by an internal counter which gives a 2 other devices, the division ratio can be varied by selecting different configuration options to give a

to 215division ratio range. As the clear instruction only resets the last stage of the counter

fixed division ratio. In the case of the

chain, for this reason the actual division ratio and corresponding WDT time-out can vary by a fac tor of two. The exact division ratio depends upon the residual value in the WDT counter before the clear instruction is executed. As an example, if a WDT time out value of 2 configuration options, the actual time out value can range from f

(4096) is chosen in the

/212to fS/213, where fSrepresents the WDT clock source. As mentioned earlier this clock source can come from either the internal WDT oscillator or from the system clock divided by four.

If the instruction clock is used as the clock source, it should be noted that when the system enters the power-down mode, then the instruction clock is stopped and the WDT will lose its protecting purposes. In such cases, the system can only be restarted via external logic. For systems that op erate in noisy environments, using the internal WDT oscillator is strongly recommended.

Under normal program operation, the WDT time-out will initialize a ²chip reset² and set the status bit ²TO². However, if the system is in the power-down mode, only a WDT time-out reset from ²HALT² will be initialized which will only reset the Program Counter and SP. Three methods can be adopted to clear the contents of the WDT. The first is an external hardware reset (a low level on the RES

pin),

the second is via software instructions and the third is via a ²HALT² instruction. There are two meth ods of using software instructions to clear the Watchdog Timer, one of which must be chosen by con figuration option. The first option is to use the single ²CLR WDT² instruction while the second is to use the two commands ²CLR WDT1² and ²CLR WDT2². For the first option, a simple execution of ²CLR WDT² will clear the WDT while for the second option, both ²CLR WDT1² and ²CLR WDT2² must both be executed to successfully clear the WDT. Note that for this second option, if ²CLR WDT1² is used to clear the WDT, successive executions of this instruction will have no effect, only the execution of a ²CLR WDT2² instruction will clear the WDT. Similarly after the ²CLR WDT2² instruction has been executed, only a successive ²CLR WDT1² instruction can clear the Watchdog Timer.

C L R W D T 1 F l a g

C L R W D T 2 F l a g

1 o r 2 I n s t r u c t i o n s

S Y S

W D T O S C O u t p u t

W D T S o u r c e S e l e c t

C o n t r o l

L o g i c

/ 4

C o n f i g .

O p t i o n S e l e c t

8 - b i t D i v i d e r

fS/ 2

7 - b i t P r e s c a l e r

C o n f i g O p t i o n

1 2

1 3

, fS/ 2

1 4

o r fS/ 2

C L R

W D T T i m e - o u t

1 5

1 3

1 4

1 5

( 2

/ fS, 2

/ fS o r 2

1 6

/ fS)

Note

1. The 4-to-1 configuration option to select fS/212,fS/213,fS/214or fS/215is not applicable in the

HT46R47/HT46C47, which has a fixed f

2. Becauseonly the last stage of counter chain is cleared by instructions, the WDT time-out period

varies. As an example, the selected value of 2

Watchdog Timer

/215division ratio.

/fSmay range from 216/fSto 215/f

Page 85

Configuration Options

The various microcontroller configuration options selected using the HT-IDE are stored in the op tion memory. All bits must be defined for proper system function, the details of which are shown in the table. After the configuration options have been programmed into the microcontroller by the user, it is important to note that they cannot be altered later by the application program. For the mask version devices, these configuration options, once defined, are implemented into the microcontroller during the manufacturing process and therefore cannot be reconfigured by the user.

No. Option

1 WDT clock source: WDT oscillator or f

2 CLRWDT instructions: 1 or 2 instructions

3 PA0~PA7 wake-up: enable or disable (by bit)

PA, PB, PC, PD, PF pull-high enable or disable

(Number of ports is device dependent. Pull-high bit or port is also device dependent.)

5 PD0~PD3: PWM function selection. Number of PWM channels are device dependent.

PWM mode selection: (7+1) or (6+2) mode

(excluding HT46R47/HT46C47, which is fixed at (6+2) mode)

7 OSC type selection: RC or crystal

PA3 PFD function: enable or disable

PFD source selection: from timer 0 or timer 1 PFD output (for HT46R24/HT46C24 only)

9 WDT division ratio: 2

10 PA6, PA7 I

11 LVR function: enable or disable

/4 or disable

SYS

12,213,214

C bus function: enable or disable (excluding HT46R47/HT46C47)

or 215(excluding HT46R47/HT46C47)

A/D Type MCU

Page 86

Application Circuits

0 . 1mF

D D

4 7 0 p F

1 0 0 k

S e e B e l o w

O S C

C 1

C 2

O S C

C i r c u i t

S Y S

R 1

D D

0 . 0 1mF

1 0 k

0 . 1mF

/ 4

V D D

R E S

V S S

O S C 1

O S C 2

O S C 1

O S C 2

O S C 1

O S C 2

Chapter 1 Hardware Structure

P A 0 ~ P A 2

P A 3 / P F D

P A 4 / T M R

P A 5 / I N T

P A 6 ~ P A 7

P B 0 / A N 0

P B 3 / A N 3

P D 0 / P W M

H T 4 6 R 4 7 / H T 4 6 C 4 7

R C S y s t e m O s c i l l a t o r

< R

3 0 k

C r y s t a l S y s t e m O s c i l l a t o r

F o r c o m p o n e n t v a l u e s , c o n s u l t O s c i l l a t o r s e c t i o n

< 7 5 0 k

O S C

O S C C i r c u i t

Page 87

0 . 1mF

D D

1 0 0 k

S e e B e l o w

4 7 0 p F

O S C

C 1

C 2

D D

O S C

C i r c u i t

S Y S

R 1

0 . 0 1mF

1 0 k

0 . 1mF

/ 4

V D D

R E S

V S S

O S C 1

O S C 2

O S C 1

O S C 2

O S C 1

O S C 2

P A 0 ~ P A 2

P A 3 / P F D

P A 4 / T M R

P A 5 / I N T

P A 6 / S D A

P A 7 / S C L

P B 0 / A N 0

P B 7 / A N 7

P C 0 ~ P C 1

P D 0 / P W M

H T 4 6 R 2 2 / H T 4 6 C 2 2

R C S y s t e m O s c i l l a t o r

< R

3 0 k

< 7 5 0 k

O S C

C r y s t a l S y s t e m O s c i l l a t o r

F o r c o m p o n e n t v a l u e s , c o n s u l t O s c i l l a t o r s e c t i o n

A/D Type MCU

O S C C i r c u i t

Page 88

0 . 1mF

D D

1 0 0 k

S e e B e l o w

4 7 0 p F

O S C

C 1

C 2

D D

O S C

C i r c u i t

S Y S

R 1

0 . 0 1mF

1 0 k

0 . 1mF

/ 4

V D D

R E S

V S S

O S C 1

O S C 2

O S C 1

O S C 2

O S C 1

O S C 2

Chapter 1 Hardware Structure

P A 0 ~ P A 2

P A 3 / P F D

P A 4 / T M R

P A 5 / I N T

P A 6 / S D A

P A 7 / S C L

P B 0 / A N 0

P B 7 / A N 7

P C 0 ~ P C 4

P D 0 / P W M 0

P D 1 / P W M 1

H T 4 6 R 2 3 / H T 4 6 C 2 3

R C S y s t e m O s c i l l a t o r

3 0 k

< R

< 7 5 0 k

O S C

C r y s t a l S y s t e m O s c i l l a t o r

F o r c o m p o n e n t v a l u e s , c o n s u l t O s c i l l a t o r s e c t i o n

O S C C i r c u i t

Page 89

0 . 1mF

D D

1 0 0 k

S e e B e l o w

4 7 0 p F

O S C

C 1

C 2

D D

O S C

C i r c u i t

S Y S

R 1

0 . 0 1mF

1 0 k

0 . 1mF

/ 4

V D D

R E S

V S S

O S C 1

O S C 2

O S C 1

O S C 2

O S C 1

O S C 2

P A 0 ~ P A 2

P A 3 / P F D

P A 4

P A 5 / I N T

P A 6 / S D A

P A 7 / S C L

P B 0 / A N 0

P B 7 / A N 7

P C 0 ~ P C 7

P D 0 / P W M 0

P D 3 / P W M 3

P D 4 ~ P D 7

P F 0 ~ P F 7

T M R 0 T M R 1

H T 4 6 R 2 4 / H T 4 6 C 2 4

R C S y s t e m O s c i l l a t o r

< R

3 0 k

< 7 5 0 k

O S C

C r y s t a l S y s t e m O s c i l l a t o r

F o r c o m p o n e n t v a l u e s , c o n s u l t O s c i l l a t o r s e c t i o n

A/D Type MCU

O S C C i r c u i t

Page 90

Part II

Programming Language

Part II Programming Language

Page 91

A/D Type MCU

Page 92

Chapter 2 Instruction Set Introduction

Chapter 2

Instruction Set Introduction

Instruction Set

Central to the successful operation of any microcontroller is its instruction set, which is a set of pro gram instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to en able programmers to implement their application with the minimum of programming overheads.

For easier understanding of the various instruction codes, they have been subdivided into several functional groupings.

Instruction Timing

Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCLwill imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be ²CLR PCL² or ²MOV PCL, A². For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required.

Page 93

A/D Type MCU

Moving and Transferring Data

The transfer of data within the microcontroller program is one of the most frequently used opera tions. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator andvice-versa as well as being able tomove specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports.

Arithmetic Operations

The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of Carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the val ues in the destination specified.

Logical and Rotate Operations

The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional pro gramming steps.In all logical data operations, the zeroflag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application where rotate data operations are used is to implement multiplication and division calculations.

Branches and Control Transfer

Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction RET in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruc tion, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condi tion of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instruc tions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.

Bit Operations

The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where in

Page 94

Chapter 2 Instruction Set Introduction

dividual bits or port pins can bedirectly set high or low using either the ²SET [m].i² or ²CLR [m].i²in structions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used.

Table Read Operations

Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in in dividual memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be setup as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory.

Other Operations

In addition to the above functional instructions, a range of other instructions also exist such as ²HALT² instruction for Power-down operation and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic envi ronment. For their relevant operations, refer to the functional related sections.

Instruction Set Summary

Convention

x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address

Mnemonic Description Cycles Flag Affected

Arithmetic

ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m]

Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract DataMemory fromACC withCarry, resultin DataMemory Decimal adjust ACC for Addition with result in Data Memory

Note

1 1

Note

Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV

Page 95

A/D Type MCU

Mnemonic Description Cycles Flag Affected

Logic Operation

AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m]

Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC

Increment & Decrement

INCA [m] INC [m] DECA [m] DEC [m]

Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory

Rotate

RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m]

Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry

Data Move

MOV A,[m] MOV [m],A MOV A,x

Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC

Bit Operation

CLR [m].i SET [m].i

Clear bit of Data Memory Set bit of Data Memory

Note

1 1 1

Note

Z Z Z Z Z Z Z Z Z Z Z

Z Z Z Z

None None

C None None

None None None

None None

Page 96

Chapter 2 Instruction Set Introduction

Mnemonic Description Cycles Flag Affected

Branch

JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI

Table Read

TABRDC [m] TABRDL [m]

Miscellaneous

NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT

Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt

Read table (current page) to TBLH and Data Memory Read table (last page) to TBLH and Data Memory

No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode

Note

note

Note

2 2 2 2

Note

1 1 1

Note

1 1

None None None None None None None None None None None None None

None None

None None None

TO, PDF TO, PDF TO, PDF

None None

TO, PDF

Note 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,

if no skip takes place only one cycle is required.

2. Anyinstruction which changes the contents of the PCL will also require 2 cycles for execution.

3. Forthe ²CLR WDT1² and ²CLRWDT2² instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and ²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged.

Page 97

A/D Type MCU

Page 98

Chapter 3 Instruction Definition

Chapter 3

Instruction Definition

ADC A,[m] Add Data Memory to ACC with Carry

Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The

result is stored in the Accumulator.

Operation

Affected flag(s) OV, Z, AC, C

ADCM A,[m] Add ACC to Data Memory with Carry

Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The

Operation

Affected flag(s) OV, Z, AC, C

ACC ¬ ACC+[m]+C

result is stored in the specified Data Memory.

[m] ¬ ACC+[m]+C

ADD A,[m] Add Data Memory to ACC

Description The contents of the specified Data Memory and the Accumulator are added. The result is

stored in the Accumulator.

Operation

Affected flag(s) OV, Z, AC, C

ADD A,x Add immediate data to ACC

Description The contents of the Accumulator and the specifiedimmediate data are added. The result is

Operation

Affected flag(s) OV, Z, AC, C

ADDM A,[m] Add ACC to Data Memory

Description The contents of the specified Data Memory and the Accumulator are added. The result is

Operation

Affected flag(s) OV, Z, AC, C

ACC ¬ ACC + [m]

stored in the Accumulator.

ACC ¬ ACC+x

stored in the specified Data Memory.

[m] ¬ ACC + [m]

Page 99

A/D Type MCU

AND A,[m] Logical AND Data Memory to ACC

Description Data in the Accumulator and the specified Data Memory perform a bitwise logical AND op

eration. The result is stored in the Accumulator.

Operation

Affected flag(s) Z

AND A,x Logical AND immediate data to ACC

Description Data in the Accumulator and the specified immediate data perform a bitwise logical AND

Operation

Affected flag(s) Z

ANDM A,[m] Logical AND ACC to Data Memory

Description Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op

Operation

Affected flag(s) Z

CALL addr Subroutine call

Description Unconditionally calls a subroutine at the specified address. The Program Counter then in

Operation

Affected flag(s) None

ACC ¬ ACC ²AND² [m]

operation. The result is stored in the Accumulator.

ACC ¬ ACC ²AND² x

eration. The result is stored in the Data Memory.

[m] ¬ ACC ²AND² [m]

crements by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruc tion.

Stack ¬ Program Counter + 1 Program Counter ¬ addr

CLR [m] Clear Data Memory

Description Each bit of the specified Data Memory is cleared to 0.

Operation

Affected flag(s) None

CLR [m].i Clear bit of Data Memory

Description Bit i of the specified Data Memory is cleared to 0.

Operation

Affected flag(s) None

[m] ¬ 00H

[m].i ¬ 0

Page 100

Chapter 3 Instruction Definition

CLR WDT Clear Watchdog Timer

Description The TO, PDF flags and the WDT are all cleared.

Operation WDT cleared

TO ¬ 0 PDF ¬ 0

Affected flag(s) TO, PDF

CLR WDT1 Pre-clear Watchdog Timer

Description The TO, PDF flags and the WDT are all cleared. Note thatthis instruction works in conjunc

tion with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Re petitively executing this instruction without alternately executing CLR WDT2 will have no effect.

Operation WDT cleared

TO ¬ 0 PDF ¬ 0

Affected flag(s) TO, PDF

CLR WDT2 Pre-clear Watchdog Timer

Description The TO, PDF flags and the WDT are all cleared. Note thatthis instruction works in conjunc

tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re petitively executing this instruction without alternately executing CLR WDT1 will have no effect.

Operation WDT cleared

TO ¬ 0 PDF ¬ 0

Affected flag(s) TO, PDF

CPL [m] Complement Data Memory

Description

Operation

Affected flag(s) Z

CPLA [m] Complement Data Memory with result in ACC

Description

Operation

Affected flag(s) Z

Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits which previously contained a 1 are changed to 0 and vice versa.

[m] ¬ [m]

Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged.

ACC ¬ [m]