HOLTEK HT46R22, HT46C22 User Manual

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Features

Operating voltage: f

=4MHz: 2.2V~5.5V

SYS

=8MHz: 4.5V~5.5V

SYS

19 bidirectional I/O lines (max.)

1 interrupt input shared with an I/O line

8-bit programmable timer/event counter with over flow interrupt and 7-stage prescaler

On-chip crystal and RC oscillator

Watchdog Timer

2048´14 program memory ROM

64´8 data memory RAM

Supports PFD for sound generation

HALT function and wake-up feature reduce power consumption

General Description

The device is an 8-bit high performance RISC-like microcontroller designed for multiple I/O product appli cations. It is particularly suitable for use in products

HT46R22/HT46C22

8-Bit A/D Type MCU

Up to 0.5ms instruction cycle with 8MHz system clock at V

=5V

6-level subroutine nesting

8 channels 9-bit resolution (8-bit accuracy) A/D con verter

1-channel (6+2)/(7+1)-bit PWM output shared with two I/O lines

Bit manipulation instruction

14-bit table read instruction

63 powerful instructions

All instructions in one or two machine cycles

Low voltage reset function

I2C BUS (slave mode)

24-pin SKDIP/SOP package

such as washing machine controllers and home appli ances. A HALT feature is included to reduce power con sumption.

I2C is a trademark of Philips Semiconductors

Rev. 1.10 1 October 2, 2002

Block Diagram

HT46R22/HT46C22

P A 5 / I N T

P r o g r a m

R O M

I n s t r u c t i o n

R e g i s t e r

I n s t r u c t i o n

D e c o d e r

T i m i n g

G e n e r a t o r

O S C 2 O S C 1

R E S V D D V S S

P r o g r a m

C o u n t e r

M P

A L U

S h i f t e r

A C C

M U X

S T A C K

M U X

L V R

D A T A

M e m o r y

S T A T U S

I n t e r r u p t

C i r c u i t

I N T C

P A 3 , P A 5

T M R

T M R C

P A 3 / P F D

W D T

P r e s c a l e r

P W M

P O R T D

P D C

P D

8 - C h a n n e l

A / D C o n v e r t e r

P B C

P O R T B

P B

P A C

P A

I C B U S

S l a v e M o d e

P C

P C C

P O R T A

P r e s c a l e r

U X

W D T

P A 4 / T M R

P A 4

S Y S C L K / 4

P D 0 / P W M

P B 0 / A N 0 ~ P B 7 / A N 7

P A 0 ~ P A 2 P A 3 / P F D P A 4 / T M R P A 5 / I N T P A 6 / S D A P A 7 / S C L

P C 0 ~ P C 1

M U X

R C O S C

S Y S

Pin Assignment

P B 5 / A N 5

P B 4 / A N 4

P A 3 / P F D

P B 3 / A N 3

P B 2 / A N 2

P B 1 / A N 1

P B 0 / A N 0

Rev. 1.10 2 October 2, 2002

P A 2

P A 1

P A 0

V S S

P C 0

1 0

1 1

1 2

2 4

2 3

2 2

2 1

2 0

1 9

1 8

1 7

1 6

1 5

1 4

1 3

H T 4 6 R 2 2 / H T 4 6 C 2 2

2 4 S K D I P - A / S O P - A

P B 6 / A N 6

P B 7 / A N 7

P A 4 / T M R

P A 5 / I N T

P A 6 / S D A

P A 7 / S C L

O S C 2

O S C 1

V D D

R E S

P D 0 / P W M

P C 1

Pad Assignment

HT46C22

HT46R22/HT46C22

P A 3 / P F D

P B 4 / A N 4

P A 2

P B 6 / A N 6

P B 5 / A N 5

P A 4 / T M R

P B 7 / A N 7

P A 5 / I N T

P A 1

P A 0

P B 3 / A N 3

P B 2 / A N 2

P B 1 / A N 1

P B 0 / A N 0

2 8

V S S

2 7

P C 0

2 9

2 5

1 1 1 2

P D 0 / P W M

2 4

2 3

1 5

1 3

1 4

R E S

V D D

2 6

( 0 , 0 )

1 0

P C 1

* The IC substrate should be connected to VSS in the PCB layout artwork.

Pad Description

Pad Name I/O Options Description

PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4/AN4

I/O Pull-high

PB5/AN5 PB6/AN6 PB7/AN7

PA0~PA2 PA3/PFD PA4/TMR PA5/INT PA6/SDA

I/O

Pull-high Wake-up

PA3 or PFD

I/O or Serial Bus

PA7/SCL

VSS

¾¾

PC0~PC1 I/O Pull-high

Bidirectional 8-bit input/output port. Software instructions deter mine the CMOS output, Schmitt trigger input with or without pull-high resistor (determined by pull-high option: port option) or A/D input. Once a PB line is selected as an A/D input (by using software control), the I/O function and pull-high resistor are disabled auto matically.

Bidirectional 8-bit input/output port. Each bit can be configured as wake-up input by options. Software instructions determine the CMOS output or Schmitt trigger input with or without pull-high resis tor (determined by pull-high options: bit option). The PFD, TMR and INT

are pin-shared with PA3, PA4 and PA5, respectively. Once

the I

C BUS function is used, the internal registers related to PA6

and PA7 can not be used.

Negative power supply, ground.

Bidirectional 2-bit input/output port. Software instructions deter mine the CMOS output, Schmitt trigger input with or without pull-high resistor (determine by pull-high option: port option).

2 2

2 1

2 0

1 9

1 8

V D D

1 6

T E S T 1

T E S T 2

P A 6 / S D A

P A 7 / S C L

O S C 2

O S C 1

1 7

T E S T 3

Rev. 1.10 3 October 2, 2002

HT46R22/HT46C22

Pad Name I/O Options Description

Bidirectional 1-bit input/output port. Software instructions deter mine the CMOS output, Schmitt trigger input with or without a pull-high resistor (determined by pull-high option: port option). The PWM output function is pin-shared with PD0 (dependent on

PD0/PWM I/O

Pull-high

I/O or PWM

PWM optios).

RES

VDD

OSC1 OSC2

TEST1 TEST2 TEST3

¾¾

Crystal or RC

Schmitt trigger reset input. Active low.

Positive power supply

OSC1, OSC2 are connected to an RC network or a Crystal (de termined by options) for the internal system clock. In the case of RC operation, OSC2 is the output terminal for 1/4 system clock.

TEST mode input pin It disconnects in normal operation

Absolute Maximum Ratings

Supply Voltage...........................VSS-0.3V to VSS+5.5V

Input Voltage..............................V

-0.3V to VDD+0.3V

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may

cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil ity.

Storage Temperature ............................-50°Cto125°C

Operating Temperature...........................-40°Cto85°C

D.C. Characteristics

Symbol Parameter

DD1

DD2

DD3

ADC

STB1

STB2

DD1

DD2

IL1

Operating Voltage

Operating Current (Crystal OSC)

Operating Current (RC OSC)

Operating Current 5V

Only ADC Enable, Others Disable

Standby Current (WDT Enabled)

Standby Current (WDT Disabled)

A/D Input Voltage

Input Low Voltage for I/O Ports, TMR and INT

Test Conditions

Conditions

=4MHz

SYS

=8MHz

SYS

No load, f

SYS

ADC disable

No load, f

SYS

ADC disable

No load, f

SYS

=4MHz

=8MHz

ADC disable

No load

No load, system HALT

¾¾

Ta=25°C

Min. Typ. Max. Unit

2.2

4.5

0.6 1.5 mA

0.8 1.5 mA

2.5 4 mA

0.5 1 mA

1.5 3 mA

¾¾

5.5 V

24mA

35mA

0.3V

0.3 V

Rev. 1.10 4 October 2, 2002

HT46R22/HT46C22

Symbol Parameter

IH1

IL2

IH2

LVR

Input High Voltage for I/O Ports, TMR and INT

Input Low Voltage (RES)

Input High Voltage (RES)

Low Voltage Reset

I/O Port Sink Current

I/O Port Source Current

Pull-high Resistance

A/D Conversion Error

A.C. Characteristics

Symbol Parameter

SYS1

SYS2

TIMER

ADC

WDTOSC

RES

SST

INT

IIC

OPT

Note: *t

System Clock (Crystal OSC)

System Clock (RC OSC)

Timer I/P Frequency (TMR)

A/D Clock Period 5V

A/D Conversion Time

Watchdog Oscillator

External Reset Low Pulse Width

System Start-up Timer Period

Interrupt Pulse Width

I2C BUS Clock Period

Option Load Time During Reset

=1/f

SYS

Test Conditions

Conditions

¾¾

=0.1V

=0.9V

¾¾ ¾±0.5 ±1

Min. Typ. Max. Unit

0.7V

0.9V

0.4V

2.7 3 3.3 V

10 20

-2 -4 ¾

-5 -10 ¾

40 60 80

10 30 50

LSB

Ta=25°C

Test Conditions

Conditions

Min. Typ. Max. Unit

400

4000 kHz

8000 kHz

4000 kHz

8000 kHz

4000 kHz

8000 kHz

¾¾ms

¾¾ ¾76¾

¾¾

Wake-up from HALT

¾¾

Connect to external

pull-high resistor 2kW

3V System power on, WDT

time-out at normal mode,

5V 35 70 140 ms

RES

is reset

43 86 168

35 65 130

¾¾ms

1024

¾¾ms

¾¾

45 90 180 ms

SYS

Rev. 1.10 5 October 2, 2002

Functional Description

Execution flow

The system clock for the microcontroller is derived from either a crystal or an RC oscillator. The system clock is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles.

Instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while de coding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruc tion to effectively execute in a cycle. If an instruction changes theprogram counter, two cyclesare required to complete the instruction.

Program counter - PC

The program counter (PC) controls the sequence in which the instructions stored in program ROM are exe cuted and its contents specify full range of program memory.

After accessing a program memory word to fetch an in struction code, the contents of the program counter are in

HT46R22/HT46C22

cremented by 1. The program counter then points to the memory word containing the next instruction code.

When executing a jump instruction, conditional skip ex ecution, loading PCL register, subroutine call, initial re set, internal interrupt, external interrupt or return from subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction.

The conditional skip is activated by instructions. Once

the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise proceed with the next instruction.

The lower byte of the program counter (PCL) is a read able and writeable register (06H). Moving data into the PCL performs a short jump. The destination will be

within 256 locations.

When a control transfer takes place, an additional dummy cycle is required.

S y s t e m C l o c k

O S C 2 ( R C o n l y )

T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4

P C

P C P C + 1 P C + 2

F e t c h I N S T ( P C )

E x e c u t e I N S T ( P C - 1 )

F e t c h I N S T ( P C + 1 )

E x e c u t e I N S T ( P C )

F e t c h I N S T ( P C + 2 )

E x e c u t e I N S T ( P C + 1 )

Execution flow

Mode

*10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0

Program Counter

Initial Reset 00000000000

External Interrupt 00000000100

Timer/Event Counter Overflow 00000001000

A/D Converter Interrupt 00000001100

C BUS Interrupt 00000010000

Skip PC+2

Loading PCL *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0

Jump, Call Branch #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0

Return from Subroutine S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

Program counter

Note: *10~*0: Program counter bits S10~S0: Stack register bits

#10~#0: Instruction code bits @7~@0: PCL bits

Rev. 1.10 6 October 2, 2002

Program memory - ROM

The program memory is used to store the program in structions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 2048´14 bits,addressed by the program counter and ta ble pointer.

Certain locations in the program memory are reserved for special usage:

Location 000H

This area is reserved for program initialization. After chip reset, the program always begins execution at lo cation 000H.

Location 004H This area is reserved for the external interrupt service program. If the INT

input pin is activated, the interrupt is enabled and the stack is not full, the program begins execution at location 004H.

Location 008H This area is reserved for the timer/event counter inter rupt service program. If a timer interrupt results from a timer/event counter overflow, and if the interrupt is en abled and the stack is not full, the program begins exe cution at location 008H.

0 0 0 H

0 0 4 H

0 0 8 H

0 0 C H

0 1 0 H

n 0 0 H

n F F H

7 0 0 H

7 F F H

D e v i c e I n i t i a l i z a t i o n P r o g r a m

E x t e r n a l I n t e r r u p t S u b r o u t i n e

T i m e r / E v e n t C o u n t e r I n t e r r u p t S u b r o u t i n e

A / D C o n v e r t e r I n t e r r u p t S u b r o u t i n e

H - B U S I n t e r r u p t S u b r o u t i n e

L o o k - u p T a b l e ( 2 5 6 w o r d s )

1 4 b i t s

N o t e : n r a n g e s f r o m 0 t o 7

P r o g r a m M e m o r y

HT46R22/HT46C22

Location 00CH

This area is reserved for the A/D converter interrupt service program. If an A/D converter interrupt results from an end of A/D conversion, and if the interrupt is enabled and the stack is not full, the program begins execution at location 00CH.

Location 010H This area is reserved for the I program. If the I

C BUS interrupt resulting from a

C BUS interrupt service

slave address is match or completed 1 byte of data transfer, and if the interrupt is enable and the stack is not full, the program begins execution at location 010H.

Table location Any location in the ROM space can be used as look-up tables. The instructions ²TABRDC [m]² (the current page, 1 page=256 words) and ²TABRDL [m]² (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are transferred to the lower portion of TBLH, and the remaining 2 bit is read as ²0². The Table Higher-order byte register (TBLH) is read only. The table pointer (TBLP) is a read/write register (07H), which indicates the table location. Before accessing the table, the location must be placed in TBLP. The TBLH is read only and cannot be restored. If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR. Errors can occur. In other words, using the table read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read instruction has to be applied in both the main routine and the ISR, the interrupt is supposed to be disabled prior to the table read instruction. It will not be enabled until the TBLH has been backed up. All table related instructions require two cycles to complete the opera tion. These areas may function as normal program memory depending upon the requirements.

Program memory

Instruction

*10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0

Table Location

TABRDC [m] P10 P9 P8 @7 @6 @5 @4 @3 @2 @1 @0

TABRDL [m] 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0

Table location

Note: *10~*0: Table location bits P10~P8: Current program counter bits

@7~@0: Table pointer bits

Rev. 1.10 7 October 2, 2002

HT46R22/HT46C22

Stack register - STACK

This is a special part of the memory which is used to save the contents of the program counter (PC) only. The stack is organized into 6 levels and is neither part of the data nor part of the program space, and is neither read able nor writeable. The activated level is indexed by the stack pointer (SP) and is neither readable nor writeable. At a subroutine call or interrupt acknowledgment, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the pro gram counter is restored to its previous value from the stack. Aftera chip reset, the SP will point to the top of the stack.

If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledgment will be inhibited. When the stack pointer is decremented (by RET or RETI), the interrupt will be serviced. This feature prevents stack overflow al lowing the programmer to use the structure more easily.

In a similar case, if the stack is full and a ²CALL² is sub sequently executed, stack overflow occurs and the first entry will be lost (only the most recent 6 return ad dresses are stored).

Data memory - RAM

The data memory is designed with 92´8 bits. The data memory is divided into two functional groups: special function registers and general purpose data memory

(64´8). Most are read/write, but some are read only.

The special function registers include the indirect addressing register (00H), timer/event counter register (TMR;0DH), timer/event counter control register (TMRC;0EH), program counter lower-order byte regis ter (PCL;06H), memory pointer register (MP;01H), ac cumulator (ACC;05H), table pointer (TBLP;07H), table higher-order byte register (TBLH;08H), status register (STATUS;0AH), interrupt control register 0 (INTC0; 0BH), PWM data register (PWM;1AH), the I slave address register (HADR;20H), the I trol register (HCR;21H), the I (HSR;22H), the I

C BUS data register (HDR;23H), the

C BUS status register

C BUS

C BUS con

A/D result lower-order byte register (ADRL;24H), the A/D result higher-order byte register (ADRH;25H), the A/D control register (ADCR;26H), the A/D clock setting register (ACSR;27H), I/O registers (PA;12H, PB;14H, PC;16H, PD;18H) and I/O control registers (PAC;13H, PBC;15H, PCC;17H, PDC;19H). The remaining space before the 40H is reserved for future expanded usage

and reading these locations will get ²00H². The general purpose data memory, addressed from 40H to 7FH, is used for data and control information under instruction commands.

I n d i r e c t A d d r e s s i n g R e g i s t e r

0 0 H

0 1 H

0 2 H

0 3 H

0 4 H

0 5 H

0 6 H

0 7 H

0 8 H

0 9 H

0 A H

0 B H

0 C H

0 D H

0 E H

0 F H

1 0 H

1 1 H

1 2 H

1 3 H

1 4 H

1 5 H

1 6 H

1 7 H

1 8 H

1 9 H

1 A H

1 B H

1 C H

1 D H

1 E H

1 F H

2 0 H

2 1 H

2 2 H

2 3 H

2 4 H

2 5 H

2 6 H

2 7 H

2 8 H

3 F H 4 0 H

7 F H

M P

A C C

P C L

T B L P

T B L H

S T A T U S

I N T C 0

T M R

T M R C

P A

P A C

P B

P B C

P C

P C C

P D

P D C

P W M

I N T C 1

H A D R

H C R

H S R

H D R

A D R L

A D R H

A D C R

A C S R

G e n e r a l P u r p o s e D A T A M E M O R Y

( 6 4 B y t e s )

R e a d a s " 0 0 "

RAM mapping

All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations di rectly. Except for some dedicated bits, each bit in the

data memory can be set and reset by ²SET [m].i² and

²CLR [m].i². They are also indirectly accessible through memory pointer register (MP;01H).

S p e c i a l P u r p o s e

D A T A M E M O R Y

: U n u s e d

Rev. 1.10 8 October 2, 2002

HT46R22/HT46C22

Indirect addressing register

Location 00H is an indirect addressing register that is not physically implemented. Any read/write operation of [00H] accesses data memory pointed to by MP (01H). Reading location 00H itself indirectly will return the re sult 00H. Writing indirectly results in no operation.

The memory pointer register MP (01H) is a 7-bit register. The bit 7 of MP is undefined and reading will return the result ²1². Any writing operation to MP will only transfer the lower 7-bit data to MP.

Accumulator

The accumulator is closely related to ALU operations. It is also mapped to location 05H of the data memory and can carry out immediate data operations. The data movement between two data memory locations must pass through the accumulator.

Arithmetic and logic unit - ALU

This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following functions:

Arithmetic operations (ADD, ADC, SUB, SBC, DAA)

Logic operations (AND, OR, XOR, CPL)

Rotation (RL, RR, RLC, RRC)

Increment and Decrement (INC, DEC)

Branch decision (SZ, SNZ, SIZ, SDZ ....)

The ALU not only saves the results of a data operation but also changes the status register.

Status register - STATUS

This 8-bit register (0AH) contains the 0 flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PD), and watchdog time-out flag (TO). It also records the status information and controls the operation sequence.

With the exception of the TO and PD flags, bits in the status register can be altered by instructions like

most other registers. Any data written into the status register will not change the TO or PD flag. In addition operations related to the status register may give dif ferent results from those intended. The TO flag can be affected only by system power-up, a WDT

time-out or executing the ²CLR WDT² or ²HALT² in struction. The PD flag can be affected only by exe cuting the ²HALT² or ²CLR WDT² instruction or a system power-up.

The Z, OV, AC and C flags generally reflect the status of the latest operations.

In addition, on entering the interrupt sequence or exe cuting the subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status are important and if the subroutine can cor rupt the status register, precautions must be taken to save it properly.

Interrupt

The device provides an external interrupt, an internal timer/event counterinterrupt, the A/D converter interrupt

and the I

C BUS interrupts. The interrupt control register 0 (INTC0;0BH) and interrupt control register 1 (INTC1;1EH) contains the interrupt control bits to set the enable or disable and the interrupt request flags.

Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may happen during this interval but only the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the EMI bit and the corresponding bit of INTC0 and INTC1 may be set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must be pre vented from becoming full.

Labels Bits Function

C is set if the operation results in a carry during an addition operation or if a borrow does not take

place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction.

AC 1

AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared.

Z 2 Z is set if the result of an arithmetic or logic operation is 0; otherwise Z is cleared.

OV 3

PD 4

TO 5

OV is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared.

PD is cleared by system power-up or executing the ²CLR WDT² instruction. PD is set by execut ing the ²HALT² instruction.

TO is cleared by system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is set by a WDT time-out.

6, 7

Unused bit, read as ²0²

Status register

Rev. 1.10 9 October 2, 2002

HT46R22/HT46C22

All these kinds of interrupts have a wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at specified location in the pro gram memory. Only the program counter is pushed onto the stack. If the contents of the register or status register (STATUS) are altered by the interrupt service program which corrupts the desired control sequence, the con tents should be saved in advance.

External interrupts are triggered by a high to low transi tion of INT

and the related interrupt request flag (EIF; bit 4 of INTC0) will be set. When the interrupt is enabled, the stack is not full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag (EIF) and EMI bits will be cleared to disable other interrupts.

The internal timer/event counter interrupt is initialized by setting the timer/event counter interrupt request flag (TF; bit 5 of INTC0), caused by a timer overflow. When the interrupt is enabled, the stack is not full and the TF bit is set, a subroutine call to location 08H will occur. The related interrupt request flag (TF) will be reset and the EMI bit cleared to disable further interrupts.

The A/D converter interrupt is initialized by setting the A/D converter request flag (ADF; bit 6 of INTC0), caused by an end of A/D conversion. When the interrupt is enabled, the stack is not full and the ADF is set, a subroutine call to location 0CH will occur. The related interrupt request flag (ADF) will be reset and the EMI bit cleared to disable further interrupts.

Controls the master (global)

0 EMI

interrupt (1= enabled; 0= disabled)

1 EEI

Controls the external interrupt (1= enabled; 0= disabled)

Controls the timer/event

2 ETI

counter interrupt (1= enabled; 0= disabled)

INTC0

(0BH)

3 EADI

4 EIF

Controls the A/D converter interrupt (1= enabled; 0= disabled)

External interrupt request flag (1= active; 0= inactive)

Internal timer/event counter

5TF

request flag (1= active; 0= inactive)

6 ADF

A/D converter request flag (1= active; 0= inactive)

¾ Unused bit, read as ²0²

INTC0 register

C BUS interrupt is initialized by setting the I2C

The I BUS interrupt request flag (HIF; bit 4 of INTC1), caused by a slave address match (HAAS=²1²) or 1 byte of data

transfer is completed. When the interrupt is enabled, the stack is not full and the HIF bit is set, a subroutine call to lo cation 10H will occur. The related interrupt request flag (HIF) will be reset and the EMI bit cleared to disable further

interrupts.

During the execution of an interrupt subroutine, other in terrupt acknowledgments are held until the ²RETI² in

struction is executed or the EMI bit and the related

interrupt control bit are set to 1 (of course, if the stack is

not full). To return from the interrupt subroutine, ²RET² or ²RETI² may be invoked. RETI will set the EMI bit to en able an interrupt service, but RET will not.

Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding inter rupts are enabled. In the case of simultaneous requests the following table shows the priority that is applied. These can be masked by resetting the EMI bit.

No. Interrupt Source Priority Vector

a External Interrupt 1 04H

b Timer/Event Counter Overflow 2 08H

c A/D Converter Interrupt 3 0CH

C BUS Interrupt 4 10H

The timer/event counter interrupt request flag (TF), external interrupt request flag (EIF), A/D converter request flag (ADF), the I

C BUS interrupt request flag (HIF), enable timer/event counter bit (ETI), enable external interrupt bit (EEI), enable A/D converter interrupt bit (EADI),

enable I

C BUS interrupt bit (EHI) and enable master interrupt bit (EMI) constitute an interrupt control register 0 (INTC0) and an interrupt control register 1 (INTC1) which are located at 0BH and 1EH in the data memory. EMI, EEI, ETI, EADI, EHI are used to control the en abling/disabling of interrupts. These bits prevent the re quested interrupt from being serviced. Once the interrupt request flags (TF, EIF, ADF, HIF) are set, they will remain in the INTC0 and INTC1 register until the in terrupts are serviced or cleared by a software instruc tion.

Controls the I rupt (1=enabled;0=disabled)

¾ Unused bit, read as ²0²

C BUS interrupt request

flag (1=active; 0=inactive)

¾ Unused bit, read as ²0²

INTC1 (1EH)

0 EHI

4 HIF

INTC1 register

C BUS inter

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HT46R22/HT46C22

It is recommended that a program does not use the

²CALL subroutine² within the interrupt subroutine. In terrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and enabling the interrupt is not well controlled, the original control sequence will be dam

aged once the ²CALL² operates in the interrupt subrou tine.

Oscillator configuration

There are two oscillator circuits in the microcontroller.

D D

O S C 1

/ 4

O S C 2

C r y s t a l O s c i l l a t o r R C O s c i l l a t o r

S Y S

N M O S O p e n D r a i n

O S C 1

O S C 2

System oscillator

Both are designed for system clocks, namely the RC os cillator and the Crystal oscillator, which are determined by the options. No matter what oscillator type is se lected, the signal provides the system clock. The HALT mode stops the system oscillator and ignores an exter nal signal to conserve power.

If an RC oscillator is used, an external resistor between OSC1 and VSS is required and the resistance must range from 30kW to 750kW. The system clock, divided by 4, is available on OSC2, which can be used to synchronize external logic. The RC oscillator provides the most cost effective solution. However, the frequency of oscillation may vary with VDD, temperatures and the chip itself due to process variations. It is, therefore, not suitable for timing sensitive operations where an accurate oscillator frequency is desired.

If the Crystal oscillator is used, a crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator, and no other external components are required. Instead of a crystal, a resona tor can also be connected between OSC1 and OSC2 to get a frequency reference, but two external capacitors in OSC1 and OSC2 are required (If the oscillating fre quency is less than 1MHz).

The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if the sys

tem enters the power down mode, the system clock is stopped, but the WDT oscillator still works with a period of

approximately 65ms/5V. The WDT oscillator can be dis abled by options to conserve power.

Watchdog Timer - WDT

The clocksource of the WDT is implemented by an dedi cated RC oscillator (WDT oscillator) or instruction clock (system clock divided by 4) decided by options. This timer is designed to prevent a software malfunction or sequence jumping to an unknown location with unpre dictable results. The watchdog Timer can be disabled by an option. If the watchdog Timer is disabled, all the exe cutions related to the WDT result in no operation.

Once an internal WDT oscillator (RC oscillator with pe

riod 65ms normally) is selected, it is divided by 2 (by option to get the WDT time-out period). The mini mum period of WDT time-out period is about

300ms~600ms. This time-out period may vary with tem

perature, VDD and process variations. By selection the

WDT options, longer time-out periods can be realized. If

the WDTtime-out is selected 2

period is divided by 2

15~216

, themaximum time-out

about 2.3s~4.7s.

If the WDT oscillator is disabled, the WDT clock may still come from the instruction clock and operate in the same manner except that in the halt state the WDT may stop counting and lose its protecting purpose. In this situation the logic can only be restarted by external logic. If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock.

The WDT overflow under normal operation will initialize

²chip reset² and set the status bit TO. Whereas in the

HALT mode, the overflow will initialize a ²warm reset² only the PC and SP are reset to 0. To clear the contents of WDT, three methods are adopted; external reset (a low

level to RES

), software instructions, or a HALT instruction. The software instructions include CLR WDT and the other

set - CLR WDT1 and CLR WDT2. Of these two types of

instruction, only one can be active depending on the op

12~215

S y s t e m C l o c k / 4

fS/ 2

W D T P r e s c a l e r

M a s k O p t i o n

W D T C l e a r

C KRT C KRT

T i m e - o u t R e s e t

1 5

/ 2 ~ fS/ 2

1 4

/ 2 ~ fS/ 2

1 3

/ 2 ~ fS/ 2

1 2

/ 2 ~ fS/ 2

1 6

1 5

1 4

1 3

W D T O S C

O p t i o n

S e l e c t

D i v i d e r

Watchdog Timer

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HT46R22/HT46C22

tions -²CLR WDT times selection option².Ifthe²CLR WDT² is selected (i.e. CLRWDT times equal 1), any exe cution of the CLR WDT instruction will clear the WDT. In case ²CLR WDT1² and ²CLR WDT2² are chosen (i.e. CLRWDT times equal two), these two instructions must be executed to clear the WDT; otherwise, the WDT may reset the chip because of time-out.

If the WDT time-out period is selected f WDT time-out period ranges from f

/212(options), the

/212~fs/213, since the

²CLR WDT² or ²CLR WDT1² and ²CLR WDT2² instruc tions only clear the last two stages of the WDT.

Power down operation - HALT

The HALT mode is initialized by the ²HALT² instruction and results in the following...

The system oscillator will be turned off but the WDT oscillator keeps running (if the WDT oscillator is se lected).

The contents of the on chip RAM and registers remain unchanged.

WDT will be cleared and recounted again (if the WDT clock is from the WDT oscillator).

All of the I/O ports maintain their original status.

The PD flag is set and the TO flag is cleared.

The system can leave the HALT mode by means of an external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset causes a device initialization and the WDT overflow performs a ²warm reset². After the TO and PD flags are examined, the reason for chip reset can be determined.

The PD flag is cleared by system power-up or executing the ²CLR WDT² instruction and is set when executing the ²HALT² instruction. The TO flag is set if the WDT time-out occurs, and causes a wake-up that only resets the PC and SP; the others keep their original status.

The port A wake-up and interrupt methods can be con sidered as a continuation of normal execution. Each bit in port A can be independently selected to wake up the device by the options. Awakening from an I/O port stim ulus, the program will resume execution of the next in struction. If it is awakening from an interrupt, two sequences may happen. If the related interrupt is dis abled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. If the interrupt is enabled and the stack is not full, the regu lar interrupt response takes place. If an interrupt request flag is set to ²1² before entering the HALT mode, the wake-up functionof the related interrupt will be disabled. Once a wake-up event occurs, it takes 1024 t

SYS

(sys tem clock period) to resume normal operation. In other words, a dummy period will be inserted after wake-up. If the wake-up results from an interrupt acknowledgment, the actual interrupt subroutine execution will be delayed by one or more cycles. If the wake-up results in the next instruction execution, this will be executed immediately

after the dummy period is finished.

To minimize power consumption, all the I/O pins should be carefully managed before entering the HALT status.

Reset

There are three ways in which a reset canoccur:

RES reset during normal operation

RES reset during HALT

WDT time-out reset during normal operation

The WDT time-out during HALT is different from other chip reset conditions, since it can perform a ²warm re set² that resets only the PC and SP, leaving the other cir cuits in their original state. Some registers remain un changed during other reset conditions. Most registers are reset to the ²initial condition² when the reset condi tions are met. By examining the PD and TO flags, the

program can distinguish between different ²chip resets².

TO PD RESET Conditions

0 0 RES

u u RES

0 1 RES

reset during power-up

reset during normal operation

wake-up HALT

1 u WDT time-out during normal operation

1 1 WDT wake-up HALT

Note: ²u² means ²unchanged²

To guarantee that the system oscillator is started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses when the system reset (power-up, WDT time-out or RES system awakes from the HALT state.

When a system reset occurs, the SST delay is added during the reset period. Any wake-up from HALT will enable the SST delay.

An extra option load time delay is added during system reset (power-up, WDT time-out at normal mode or RES

reset).

The functional unit chip reset status are shown below.

PC 000H

Interrupt Disable

WDT

Clear. After master reset, WDT begins counting

Timer/Event Counter Off

Input/Output Ports Input mode

SP Points to the top of the stack

V D D

R E S

S S T T i m e - o u t

C h i p R e s e t

S S T

Reset timing chart

reset) or the

Rev. 1.10 12 October 2, 2002

HT46R22/HT46C22

D D

Reset circuit

R E S

H A L T

R E S

O S C 1

W D T

S S T

1 0 - b i t R i p p l e

C o u n t e r

S y s t e m R e s e t

Reset configuration

W a r m R e s e t

The registers states are summarized in the following table.

Reset

(Power On)

WDT Time-out

(Normal Operation)

RES

Reset

(Normal Operation)

RES Reset

(HALT)

WDT Time-out

(HALT)*

TMR xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

TMRC 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu

Program Counter

000H 000H 000H 000H 000H

MP -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu

ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

TBLH --xx xxxx --uu uuuu --uu uuuu --uu uuuu --uu uuuu

STATUS --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu

INTC0 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu

INTC1 ---0 ---0 ---0 ---0 ---0 ---0 ---0 ---0 ---u ---u

PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu

PAC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu

PB 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu

PBC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu

PC ---- --11 ---- --11 ---- --11 ---- --11 ---- --uu

PCC ---- --11 ---- --11 ---- --11 ---- --11 ---- --uu

PD ---- ---1 ---- ---1 ---- ---1 ---- ---1 ---- ---u

PDC ---- ---1 ---- ---1 ---- ---1 ---- ---1 ---- ---u

PWM xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

HADR xxxx xxx- xxxx xxx- xxxx xxx- xxxx xxx- uuuu uuu-

HCR 0--0 0--- 0--0 0--- 0--0 0--- 0--0 0--- u--u u---

HSR 100- -0-1 100- -0-1 100- -0-1 100- -0-1 uuu- -u-u

HDR xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

ADRL x--- ---- x--- ---- x--- ---- x--- ---- u--- ----

ADRH xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

ADCR 0100 0000 0100 0000 0100 0000 0100 0000 uuuu uuuu

ACSR 1--- --00 1--- --00 1--- --00 1--- --00 u--- --uu

C o l d R e s e t

Note:

²*² stands for ²warm reset² ²u² stands for ²unchanged² ²x² stands for ²unknown²

Rev. 1.10 13 October 2, 2002

HT46R22/HT46C22

Timer/Event Counter

A timer/event counter (TMR) is implemented in the microcontroller. The timer/event counter contains an 8-bit programmable count-up counter and the clock may come from an external source or the system clock.

Using the internal system clock, there is only one refer ence time-base. The internal clock source comes from f

. Using external clock input allows the user to count

SYS

external events, measure time internals or pulse widths, or generate an accurate time base. While using the in ternal clock allows the user to generate an accurate time base.

There are two registers related to the timer/event counter; TMR ([0DH]), TMRC ([0EH]). Two physical registers are mapped to TMR location; writing TMR makes the starting value be placed in the timer/event counter preload register and reading TMR gets the contents of the timer/event counter. The TMRC is a timer/event counter control regis ter, which defines some options.

The TM0, TM1 bits define the operating mode. The event count mode is used to count external events, which means the clock source comes from an external (TMR) pin. The timer mode functions as a normal timer with the clock source coming from the f

clock. The

INT

pulse width measurement mode can be used to count the high or low level duration of the external signal (TMR). The counting is based on the f

INT

In the event count or timer mode, once the timer/event counter starts counting, it will count from the current contents in the timer/event counter to FFH. Once overflow occurs, the counter is reloaded from the timer/event counter preload register and generates the interrupt request flag (TF; bit 5 of INTC) at the same time.

In the pulse width measurement mode with the TON and TE bits equal to 1, once the TMR has received a transient from low to high (or high to low if the TE bits is ²0²) it will start counting until the TMR returns to the orig inal level and resets the TON. The measured result will remain in the timer/event counter even if the activated transient occurs again. In other words, only 1 cycle mea surement can be done. Until setting the TON, the cycle measurement will function again as long as it receives further transientpulse. Note that, in this operating mode, the timer/event counter starts counting not according to the logic level but according to the transient edges. In the case of counter overflows, the counter is reloaded from the timer/event counter preload register and issues the interrupt request just like the other two modes. To enable the counting operation, the timer ON bit (TON; bit 4 of TMRC) should be set to 1. In the pulse width measurement mode, the TON will be cleared automati cally after the measurement cycle is completed. But in the other two modes the TON can only be reset by in structions. The overflow of the timer/event counter is one of the wake-up sources. No matter what the opera

tion mode is, writinga0toETIcandisable the interrupt service.

In the case of timer/event counter OFF condition, writ ing data to the timer/event counter preload register will also reloadthat data to the timer/event counter. But if the timer/event counter is turned on, data written to it will

only be kept in the timer/event counter preload register. The timer/event counter will still operate until overflow oc curs. When the timer/event counter (reading TMR) is read,

the clock will be blocked to avoid errors. As clock blocking may results in a counting error, this must be taken into con sideration by the programmer.

The bit0~bit2 of the TMRC can be used to define the pre-scaling stages of the internal clock sources of timer/event counter. The definitions are as shown. The overflow signal of timer/event counter can be used to generate the PFD signal.

Label

(TMRC)

Bits Function

To define the prescaler stages, PSC2, PSC1, PSC0= 000: f

INT=fSYS

PSC0~ PSC2

0~2

001: f 010: f 011: f 100: f 101: f 110: f 111: f

INT=fSYS

/2 /4 /8 /16 /32 /64 /128

To define the TMR active edge of

TE 3

timer/event counter (0=active on low to high; 1=active on high to low)

To enable or disable timer counting (0=disabled; 1=enabled)

Unused bit, read as ²0²

To define the operating mode 01=Event count mode (external clock)

10=Timer mode (internal clock)

11=Pulse width measurement mode

TON 4

TM0 TM1

00=Unused

TMRC register

Input/output ports

There are 19 bidirectional input/output lines in the microcontroller, labeled as PA, PB, PC and PD, which are mapped to the data memory of [12H], [14H], [16H] and [18H] respectively. All of these I/O ports can be used for input and output operations. For input opera tion, these ports are non-latching, that is, the inputs

must be ready at the T2 rising edge of instruction ²MOV A,[m]² (m=12H, 14H, 16H or 18H). For output operation,

all the data is latched and remains unchanged until the output latch is rewritten.

Rev. 1.10 14 October 2, 2002

+ 32 hidden pages

HOLTEK HT46R22, HT46C22 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual