HOLTEK HT36F2 User Manual

Music Synthesizer 8-Bit MCU

Technical Document

·

Tools Information

·

FAQs

·

Application Note

Features

·

Operating voltage: 2.4V~5.0V

·

Operating frequency:
Xtal: 6MHz~8MHz
R

: typ. 6MHz

OSC

·

Built-in 32K´16-bit (0.5M-bit) ROM for program/data
shared

·

Built-in 8 bit MCU with 208´8 bits RAM

·

Two 8bit programmabletimer with 8 stage prescaler

·

16 bidirectional I/O lines

·

Four polyphonic synthesizer

·

Mono 16-bit DAC

HT36F2

·

Oscillation modes: XTAL/RCOSC

·

Low voltage reset

·

Eight-level subroutine nesting

·

Watchdog timer

·

Supports 8-bit table read instruction (TBLP)

·

HALT function and wake-up feature reduce power
consumption

·

Bit manipulation instructions

·

63 powerful instructions

·

All instructions in 1 or 2 machine cycles

·

16/28-pin SOP package

General Description

The HT36F2 is an 8-bit high performance RISC archi­tecture microcontroller specifically designed for various
music applications. It provides an 8-bit MCU and a
4-channel Wavetable synthesizer. It has a built-in 8-bit

Block Diagram

P A 0 ~ P A 7
P B 0 ~ P B 7

O S C 1

O S C 2

R E S

8 - B i t
M C U

3 2 K´1 6 - b i t

M u l t i p l i e r / P h a s e

microprocessor which controls the synthesizer to gen­erate the melody by setting the special register. A HALT
feature is provided to reduce power consumption.

R O M

2 0 8´8

R A M

G e n e r a l

1 6 - B i t

D A C

V D D

V S S
V D D A
V S S A

A U D

Rev. 1.00 1 August 15, 2005

Pin Assignment

2

HT36F2

A U D

V D D A

V S S A

O S C 2

O S C 1

V S S

V D D

R E S

Pad Assignment

A U D

T E S T

V D D A

V S S A

1

2

3

4

5

6

7

8

H T 3 6 F 2

1 6 S O P - A

1

2

3

4

P B 1

1

P B 0

2

A U D

3

T E S T

4

V D D A

V S S A

P A 7

1 6

P A 6

1 5

P A 5

1 4

P A 4

1 3

P A 3

1 2

P A 2

1 1

P A 1

1 0

P A 0

9

O S C 2

O S C 1

P B 0

2 5 2 4

5

6

7

8

V S S

9

V D D

1 0

R E S

1 1

N C

1 2

N C

1 3

N C

1 4

H T 3 6 F 2

2 8 S O P - A

P B 5

P B 4

P B 3

P B 2

P B 1

2 22 3

2 1

2 0

P B 2

2 8

P B 3

2 7

P B 4

2 6

P B 5

2 5

P B 6

2 4

P B 7

2 3

P A 7

2 2

P A 6

2 1

P A 5

2 0

P A 4

1 9

P A 3

1 8

P A 2

1 7

P A 1

1 6

P A 0

1 5

1 9

P B 6

1 8

P B 7

1 7

P A 7

1 6

P A 6

1 5

P A 5

1 4

P A 4

1 3

P A 3

( 0 , 0 )

V S S

V D D

R E S

5

6

7

8

9

Chip size: 2135 ´ 2385 (mm)

2

1 0

P A0P A 1

1 1

1 2

P A

O S C 2

O S C 1

* The IC substrate should be connected to VSS in the PCB layout artwork.

Rev. 1.00 2 August 15, 2005

HT36F2

Pad Coordinates

Pad No. X Y Pad No. X Y

1

2

3

4

5

6

7

8

9

10 710.500

11 810.500

12 921.100

13 916.350 414.500

-876.150

-876.150

-876.150

-876.150

-916.350 -63.124

-916.350 -740.976

-916.350 -842.650

-916.350 -942.650

-916.350 -1044.324

1043.000 14 916.350 514.500

931.200 15 916.350 625.100

817.560 16 916.350 725.100

715.600 17 916.350 835.700

18 916.350 935.700

19 916.350 1046.300

20 704.250 1041.550

21 593.650 1041.550

22 493.650 1041.550

-1041.350

-1041.350

-1041.350

23 383.050 1041.550

24 283.050 1041.550

25 172.450 1041.550

Pad Description

Pad No. Pad Name I/O

8, 7 VDD, VSS

3,4 VDDA, VSSA

10~17 PA0~PA7 I/O

25~18 PB0~PB7 I/O

9 RESET

6 OSC1 I

5 OSC2 O

1 AUD O

Internal

Connection

¾¾

¾¾

Wake-up,

Pull-high or

None

Pull-high or

None

I

¾

X¢tal/Resistor XIN for X¢tal or ROSCIN for resistor by mask option

¾

¾

Digital power supply, ground

DAC power supply

Bidirectional 8-bit I/O port, wake-up by mask option

Bidirectional 8-bit I/O port

Reset input, active low

XOUT or T1

DAC output interface

Function

Unit: mm

Absolute Maximum Ratings

Supply Voltage ..........................VSS-0.3V to VSS+5.5V

Input Voltage .............................V

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may

cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil
ity.

Rev. 1.00 3 August 15, 2005

3V to VDD+0.3V

SS-0.

Storage Temperature ...........................-50°Cto125°C

Operating Temperature ..........................-25°Cto70°C

-

HT36F2

Electrical Characteristics

Symbol Parameter

V

I

I

I

I

V

V

DD

DD

STB

OH

OL

IH

IL

Operating Voltage

Operating Current

Standby Current

Flag Source Current

Flag Sink Current

Input High Voltage for I/O Ports

Input Low Voltage for I/O Ports

Test Conditions

V

DD

Conditions

¾¾

3V

No load(OSC= 6MHz)

4.5V

3V

4.5V

¾

3V

4.5V

¾

3V

4.5V

¾

¾¾

¾¾

Ta=25°C

Min. Typ. Max. Unit

2.4 4.5 5 V

¾

¾

¾

¾

5

5

0.8V

0

28

810

1

13

¾¾

¾¾

¾

DD

¾

V

0.2V

¾

DD

DD

mA

mA

mA

mA

V

V

Rev. 1.00 4 August 15, 2005

Function Description

Execution Flow

The system clock for the HT36F2 is derived from either
a crystal or an RC oscillator. The oscillator frequency di
vided by 2 is the system clock for the MCU and it is inter
nally divided into four non-overlapping clocks. One
instruction cycle consists of four system clock cycles.

Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while de
coding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruc
tion to effectively execute in one cycle. If an instruction
changes the program counter, two cycles are required
to complete the instruction.

Program Counter - PC

The 13-bit program counter (PC) controls the sequence
in which the instructions stored in program ROM are ex
ecuted and its contents specify a maximum of 8192 ad
dresses for each bank.

After accessing a program memory word to fetch an in
struction code, the contents of the program counter are
incremented by one. The program counter then points
to the memory word containing the next instruction
code.

When executing a jump instruction, conditional skip ex
ecution, loading PCL register, subroutine call, initial re
set, internal interrupt, external interrupt or return from

­subroutine, the PC manipulates the program transfer by

­loading the address corresponding to each instruction.

The conditional skip is activated by instruction. Once the
condition is met, the next instruction, fetched during the
current instruction execution, is discarded and a dummy

­cycle replaces it to retrieve the proper instruction. Other

wise proceed with the next instruction.

-

The lower byte of the program counter (PCL) is a read
able and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within 256 locations.

Once a control transfer takes place, an additional
dummy cycle is required.

-

-

Program ROM

HT36F2 provides 16 address lines WA15~WA0 to read

-

the Program ROM which is up to 0.5M bits, and is com
monly used for the

wavetable

voice codes and the pro
gram memory. It provides two address types, one type is
for program ROM, which is addressed by a bank pointer
PF1~PF0 and a 13-bit program counter PC12~PC0;

HT36F2

-

-

-

-

-

-

S y s t e m C l o c k o f M C U

( S y s t e m C l o c k / 2 )

T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4

P C

P C P C + 1 P C + 2

F e t c h I N S T ( P C )

E x e c u t e I N S T ( P C - 1 )

F e t c h I N S T ( P C + 1 )

E x e c u t e I N S T ( P C )

F e t c h I N S T ( P C + 2 )

E x e c u t e I N S T ( P C + 1 )

Execution Flow

Mode

*14 *13 *12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0

Program Counter

Initial Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Timer/Event Counter 0 Overflow PF1 PF0 0 0 0 0 0 0 0 0 0 1 0 0 0

Timer/Event Counter 1 Overflow PF1 PF0 0 0 0 0 0 0 0 0 0 1 1 0 0

Skip Program Counter+2

Loading PCL PF1 PF0 *12 *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0

Jump, Call Branch PF1 PF0 #12 #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0

Return From Subroutine PF1 PF0 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

Program Counter

Note: *12~*0: Bits of Program Counter

@7~@0: Bits of PCL

#12~#0: Bits of Instruction Code

S12~S0: Bits of Stack Register

@7~@0: Bits of PCL

PF1~PF0: Bits of Bank Register

Rev. 1.00 5 August 15, 2005

HT36F2

and the other type is for wavetable code, which is ad
dressed by the start address ST15~ST0. On the pro

13

gram type, WA15~WA0=PF1~PF0´2

+PC12~PC0.

On the wave table ROM type, WA15~WA0=
ST15~ST0´2

5

.

Program Memory - ROM

The program memory is used to store the program in
structions which are to be executed. It also contains
data, table, and interrupt entries, and is organized into
8192´16 bits, addressed by the bank pointer, program
counter and table pointer.

Certain locations in the program memory of each bank
are reserved for special usage:

·

Location 000H on bank0
This area is reserved for the initialization program. Af
ter chip reset, the program always begins execution at
location 000H on bank0.

·

Location 008H
This area is reserved for the Timer Counter 0 interrupt
service program on each bank. If timer interrupt results
from a timer counter 0 overflow, and if the interrupt is en
abled and the stack is not full, the program begins exe
cution at location 008H corresponding to its bank.

·

Location 00CH
This area is reserved for the Timer Counter 1 interrupt
service program on each bank. If a timer interrupt re­sults from a Timer Counter 1 overflow, and if the inter­rupt is enabled and the stack is not full, the program
begins execution at location 00CH corresponding to
its bank.

·

Table location
Any location in the ROM space can be used as
look-up tables. The instructions ²TABRDC [m]² (the
current page, 1 page=256 words) and ²TABRDL [m]²
(the last page) transfer the contents of the lower-order
byte to the specified data memory, and the
higher-order byte to TBLH (08H). Only the destination
of the lower-order byte in the table is well-defined, the
higher-order byte of the table word are transferred to
the TBLH. The Table Higher-order byte register
(TBLH) is read only. The Table Pointer (TBLP) is a
read/write register (07H), which indicates the table lo
cation. Before accessing the table, the location must

0 0 0 0 H

-

-

0 0 0 8 H

0 0 0 C H

n 0 0 H

-

n F F H

1 F F F H

D e v i c e i n i t i a l i z a t i o n p r o g r a m

T i m e r C o u n t e r 0 i n t e r r u p t s u b r o u t i n e

T i m e r C o u n t e r 1 i n t e r r u p t s u b r o u t i n e

L o o k - u p t a b l e ( 2 5 6 w o r d s )

L o o k - u p t a b l e ( 2 5 6 w o r d s )

1 6 b i t s

N o t e : n r a n g e s f r o m 0 0 t o 3 F .

Program Memory for Each Bank

­be placed in TBLP. The TBLH is read only and cannot

be restored. If the main routine and the ISR (Interrupt
Service Routine) both employ the table read instruc
tion, the contents of the TBLH in the main routine are
likely to be changed by the table read instruction used
in the ISR. Errors can occur. In this case, using the ta

-

-

ble read instruction in the main routine and the ISR si
multaneously should be avoided. However, if the
table read instruction has to be applied in both the
main routine and the ISR, the interrupt should be dis­abled prior to the table read instruction. It will not be
enabled until the TBLH has been backed up. All table
related instructions need 2 cycles to complete the op­eration. These areas may function as normal program
memory depending upon user requirements.

·

Bank pointer
The program memory is organized into 4 banks and
each bank into 8192´16 bits of program ROM.
PF1~PF0 is used as the bank pointer. After an instruc
tion has been executed to write data to the PF register
to select a different bank, note that the new bank will
not be selected immediately. It is not until the following
instruction has completed execution that the bank will
be actually selected. It should be note that the PF reg
ister hasto becleared before setting to output mode.

Wavetable ROM

The ST15~ST0 is used to defined the start address of

-

each sample on the wavetable and read the waveform
data from the location. HT36F2 provides 16 output ad

P r o g r a m
R O M

-

-

-

-

-

-

Instruction (s)

*14 *13 *12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0

Table Location

TABRDC [m] P14 P13 P12 P11 P10 P9 P8 @7 @6 @5 @4 @3 @2 @1 @0

TABRDL [m] P14 P13 11111@7@6@5@4@3@2@1@0

Table Location

Note: *12~*0: Bits of table location

@7~@0: Bits of table pointer

P12~P8: Bits of current Program Counter

P14~P13: Bits of Bank PF1~PF0

Rev. 1.00 6 August 15, 2005

dress lines from WA15~WA0, the ST15~ST0 is used to
locate the major 11 bits i.e. WA15~WA5 and the unde
fined data from WA4~WA0 is always set to 00000b. So
the start address of each sample have to be located at a
multiple of 32. Otherwise, the sample will not be read
out correctly because it has a wrong starting code.

Stack Register - Stack

This is a special part of the memory which is used to
save the contents of the program counter only. The
stack is organized into 8 levels and is neither part of the
data nor part of the program space, and is neither read
able nor writeable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor writeable.
At a subroutine call or interrupt acknowledgment, the
contents of the program counter are pushed onto the
stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction (RET or RETI), the pro
gram counter is restored to its previous value from the
stack. Aftera chip reset, the SP will point tothe top of the
stack.

If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledgment will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow al­lowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a CALL is subse­quently executed, a stack overflow occurs and the first
entry will be lost (only the most recent eight return ad­dress are stored).

Data Memory - RAM

The datamemory is designed with 256 ´8 bits. The data
memory is divided into three functional groups: special
function registers, wavetable function register, and gen
eral purpose data memory (208´8). Most of them are
read/write, but some are read only.

The special function registers include the Indirect Ad
dressing register 0 (00H), the Memory Pointer register 0
(MP0;01H), the Indirect Addressing register 1 (02H), the
Memory Pointer register 1 (MP1;03H), the Accumulator
(ACC;05H), the Program Counter Lower-byte register
(PCL;06H), the Table Pointer (TBLP;07H), the Table
Higher-order byte register (TBLH;08H), the Watchdog
Timer option Setting register (WDTS;09H), the Status
register (STATUS;0AH), the Interrupt Control register
(INTC;0BH), the Timer Counter 0 Lower-order byte reg
ister (TMR0L;0DH), the Timer Counter 0 Control regis
ter (TMR0C;0EH), the Timer Counter 1 Lower-order
byte register (TMR1L;10H), the Timer Counter 1 Control
register (TMR1C;11H), the I/O registers (PA;12H,
PB;14H) and the I/O control registers (PAC;13H,
PBC;15H, PCC;17H). The program ROM bank select
(PF;1CH). The DAC High byte (DAH;1DH). The DAC
low byte (DAL;1EH). The DAC control (DAC;1FH). The

I n d i r e c t A d d r e s s i n g R e g i s t e r 0

0 0 H

0 1 H

-

0 2 H

I n d i r e c t A d d r e s s i n g R e g i s t e r 1

0 3 H

0 4 H

0 5 H

0 6 H

0 7 H

0 8 H

0 9 H

0 A H

0 B H

0 C H

-

0 D H

0 E H

0 F H

1 0 H

1 1 H

1 2 H

1 3 H

-

1 4 H

1 5 H

1 6 H

1 7 H
1 8 H

1 9 H

1 A H

1 B H

1 C H

1 D H
1 E H

1 F H

2 0 H

C h a n n e l N u m b e r S e l e c t ( C H A N )

F r e q u e n c y N u m b e r H i g h B y t e ( F r e q N H )

2 1 H

F r e q u e n c y N u m b e r L o w B y t e ( F r e q N L )

2 2 H

S t a r t A d d r e s s H i g h B y t e ( A d d r H )

2 3 H

2 4 H

S t a r t A d d r e s s L o w B y t e ( A d d r L )

2 5 H

R e p e a t N u m b e r H i g h B y t e ( R e H )

2 6 H

R e p e a t N u m b e r L o w B y t e ( R e L )

V o l u m e C o n t r o l H i g h ( V o l H )

2 7 H

2 8 H

-

2 9 H

2 A H
2 B H

M P 0

M P 1

A C C

P C L

T B L P

T B L H

W D T S

S T A T U S

I N T C

T M R 0 L

T M R 0 C

T M R 1 L
T M R 1 C

P A

P A C

P B

P B C

P F

D A C H i g h B y t e ( D A H )

D A C L o w B y t e ( D A L )

D A C C o n t r o l ( D A C )

V o l u m C o n t r o l ( V o l L )

S p e c i a l P u r p o s e
D A T A M E M O R Y

W a v e t a b l e F u n c t i o n
R e g i s t e r

-

2 F H

3 0 H

G e n e r a l P u r p o s e
D A T A M E M O R Y

( 2 0 8 B y t e s )

F F H

-

-

RAM Mapping

: U n u s e d .
R e a d a s " 0 0 "

wavetable function registers is defined between
20H~2AH. The remaining space before the 30H is re
served for future expanded usage and reading these lo
cations will return the result 00H. The general purpose
data memory, addressed from 30H to FFH, is used for
data and control information under instruction com
mand.

HT36F2

-

-

-

Rev. 1.00 7 August 15, 2005

HT36F2

All data memory areas can handle arithmetic, logic, in
crement, decrement and rotate operations directly. Ex
cept for some dedicated bits, each bit in the data
memory can be set and reset by the ²SET [m].i² and
²CLR [m].i²instructions, respectively. They are also indi
rectly accessible through Memory pointer registers
(MP0:01H, MP1:03H).

Indirect Addressing Register

Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write op
eration of [00H] and [02H] access data memory pointed
to by MP0 (01H) and MP1 (03H) respectively. Reading
location 00H or 02H directly will return the result 00H.
And writing directly results in no operation.

The function of data movement between two indirect ad
dressing registers, is not supported. The memory
pointer registers, MP0 and MP1, are 8-bit register which
can be used to access the data memory by combining
corresponding indirect addressing registers.

-

Status Register - STATUS

-

This 8-bit register (0AH) contains the zero flag (Z), carry
flag (C), auxiliary carry flag (AC), overflow flag (OV),
power down flag (PDF) and Watchdog time-out flag

-

(TO). It also records the status information and controls the
operation sequence.

With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like any
other register. Any data written into the status register
will not change the TO or PDF flags. In addition it should

-

be noted that operations related to the status register
may give different results from those intended. The TO
and PDF flags can only be changed by system power
up, Watchdog Timer overflow, executing the ²HALT² in
struction and clearing the Watchdog Timer.

-

The Z, OV, AC and C flags generally reflect the status of
the latest operations.

In addition, on entering the interrupt sequence or exe
cuting a subroutine call, the status register will not be
automatically pushed onto the stack. If the contents of

Accumulator

The accumulator closely relates to ALU operations. It is
mapped to location 05H of the data memory and it can
operate with immediate data. The data movement be
tween two data memory locations must pass through
the accumulator.

status are important and the subroutine can corrupt the
status register, the programmer must take precautions
to save it properly.

-

Interrupt

The HT36F2 provides two internal timer counter inter­rupts on each bank. The Interrupt Control register

Arithmetic and Logic Unit - ALU

This circuit performs 8-bit arithmetic and logic operation.
The ALU provides the following functions:

·

Arithmetic operations (ADD, ADC, SUB, SBC, DAA)

·

Logic operations (AND, OR, XOR, CPL)

·

Rotation (RL, RR, RLC, RRC)

·

Increment & Decrement (INC, DEC)

·

Branch decision (SZ, SNZ, SIZ, SDZ ....)

The ALU not only saves the results of a data operation but
can also change the status register.

(INTC;0BH) contains the interrupt control bits that sets
the enable/disable and the interrupt request flags.

Once an interrupt subroutine is serviced, all other inter­rupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may occur during this interval but only
the interrupt request flag is recorded. If a certain inter
rupt needs servicing within the service routine, the pro
grammer may set the EMI bit and the corresponding bit
of the INTC to allow interrupt nesting. If the stack is full,
the interrupt request will not be acknowledged, even if

Bit No. Label Function

C is set if an operation results in a carry during an addition operation or if a borrow does not

0C

take place during a subtraction operation; otherwise C is cleared. Also it is affected by a ro
tate through carry instruction.

1AC

AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.

2 Z Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.

3OV

4 PDF

5TO

6~7

OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.

PDF is cleared by either a system power-up or executing the ²CLR WDT² instruction. PDF
is set by executing the ²HALT² instruction.

TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO
is set by a WDT time-out.

¾ Unused bit, read as ²0²

Status (0AH) Register

-

-

-

-

-

Rev. 1.00 8 August 15, 2005

HT36F2

the related interrupt is enabled, until the SP is decre
mented. If immediate service is desired, the stack must
be prevented from becoming full.

All these kinds of interrupt have a wake-up capability. As
an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack and then
branching to subroutines at specified locations in the
program memory. Only the program counter is pushed
onto the stack. If the contents of the register and Status
register (STATUS) are altered by the interrupt service
program which may corrupt the desired control se
quence, then the programmer must save the contents
first.

The internal Timer Counter 0 interrupt is initialized by
setting the Timer Counter 0 interrupt request flag (T0F;
bit 5 of INTC), caused by a Timer Counter 0 overflow.
When the interrupt is enabled, and the stack is not full
and the T0F bit is set, a subroutine call to location 08H
will occur. The related interrupt request flag (T0F) will be
reset and the EMI bit cleared to disable further inter
rupts.

The Timer Counter 1 interrupt is operated in the same
manner as Timer Counter 0. The related interrupt con
trol bits ET1I and T1F of the Timer Counter 1 are bit 3
and bit 6 of the INTC respectively.

During the execution of an interrupt subroutine, other in­terrupt acknowledgments are held until the ²RETI² in­struction is executed or the EMI bit and the related
interrupt control bit are set to 1 (if the stack is not full). To
return from the interrupt subroutine, the ²RET² or
²RETI² instruction may be invoked. RETI will set the
EMI bit to enable an interrupt service, but RET will not.

Interrupts occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter
rupts are enabled. In the case of simultaneous requests
the priorities in the following table apply. These can be
masked by resetting the EMI bit.

Interrupt Source Priority Vector

Timer Counter 0 overflow 1 08H

Timer Counter 1 overflow 2 0CH

The Timer Counter 0/1 interrupt request flag (T0F/T1F),

­Enable Timer Counter 0/1 bit (ET0I/ET1I) and Enable
Master Interrupt bit (EMI) constitute an interrupt control
register (INTC) which is located at 0BH in the data mem
ory. EMI, ET0I, ET1I are used to control the en
abling/disabling of interrupts. These bits prevent the
requested interrupt from being serviced. Once the inter
rupt request flags (T0F, T1F) are set, they will remain in
the INTC register until the interrupts are serviced or
cleared by a software instruction.

-

It is recommended that a program does not use the
²CALL subroutine² within the interrupt subroutine. Be
cause interrupts often occur in an unpredictable manner
or need to be serviced immediately in some applica
tions, if only one stack is left and enabling the interrupt is
not well controlled, once the ²CALL subroutine² operates
in the interrupt subroutine, it may damage the original
control sequence.

Oscillator Configuration

­The HT36F2 provides two types of oscillator circuit for

the system clock,i.e., RC oscillator and crystal oscillator.
No matter what type of oscillator, the signal divided by 2

­is used for the system clock. The HALT mode stops the

system oscillator and ignores external signal to con
serve power. If the RC oscillator is used, an external re­sistor between OSC1 and VSS is required. The system
clock, divided by 4, is available on OSC2 with pull-high
resistor, which can be used to synchronize external
logic. The RC oscillator provides the most cost effective
solution. However, the frequency of the oscillation may
vary with VDD, temperature, and the chip itself due to
process variations. It is therefore, not suitable for timing
sensitive operations where accurate oscillator fre­quency is desired.

-

O S C 1

O S C 2

C r y s t a l O s c i l l a t o r R C O s c i l l a t o r

V

D D

f

S Y S

/ 8

System Oscillator

-

-

-

-

-

-

O S C 1

O S C 2

Bit No. Label Function

0 EMI Controls the Master (Global) interrupt (1=enabled; 0=disabled)

1, 4, 7

¾ Unused bit, read as ²0²

2 ET0I Controls the Timer Counter 0 interrupt (1=enabled; 0=disabled)

3 ET1I Controls the Timer Counter 1 interrupt (1=enabled; 0=disabled)

5 T0F Internal Timer Counter 0 request flag (1=active; 0=inactive)

6 T1F Internal Timer Counter 1 request flag (1=active; 0=inactive)

INTC (0BH) Register

Rev. 1.00 9 August 15, 2005

HT36F2

On the other hand, if the crystal oscillator is selected, a
crystal across OSC1 and OSC2 is needed to provide the
feedback and phase shift required for the oscillator, and
no other external components are required. A resonator
may be connected between OSC1 and OSC2 to replace
the crystal and to get a frequency reference, but two ex
ternal capacitors in OSC1 and OSC2 are required.

The WDT oscillator is a free running on-chip RC oscilla
tor, and no external components are required. Even if
the system enters the Power Down Mode, the system
clock is stopped, but the WDT oscillator still works with a
period of approximately 78ms. The WDT oscillator can
be disabled by mask option to conserve power.

Watchdog Timer - WDT

The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator) or instruction clock (sys
tem clock of the MCU divided by 4), determined by mask
options. This timer is designed to prevent a software
malfunction or sequence jumping to an unknown loca
tion withunpredictable results.The Watchdog Timer can
be disabled by mask option. If the Watchdog Timer is
disabled, all the executions related to the WDT result in
no operation.

Once the internal WDT oscillator (RC oscillator with a
period of 78ms normally) is selected, it is first divided by
256 (8-stages) to get the nominal time-out period of ap­proximately 20ms. This time-out period may vary with
temperature, VDD and process variations. By invoking
the WDT prescaler, longer time-out periods can be real­ized. Writing data to WS2, WS1, WS0 (bit 2,1,0 of the
WDTS) can give different time-out periods. If WS2,
WS1, WS0 all equal to 1, the division ratio is up to 1:128,
and the maximum time-out period is 2.6 seconds.

If the WDT oscillator is disabled, the WDT clock may still
come from the instruction clock and operate in the same
manner except that in the HALT state the WDT may stop
counting and lose its protecting purpose. In this situation

the logic can only be restarted by external logic. The
high nibble and bit 3 of the WDTS are reserved for user
defined flags, and the programmer may use these flags
to indicate some specified status.

-

-

WS2 WS1 WS0 Division Ratio

000 1:1

001 1:2

010 1:4

011 1:8

1 0 0 1:16

1 0 1 1:32

1 1 0 1:64

1 1 1 1:128

If the device operates in a noisy environment, using the

­on-chip RC oscillator (WDT OSC) is strongly recom

mended, since the HALT will stop the system clock.

The WDT overflow under normal operation will initialize

­a ²chip reset² and set the status bit TO. Whereas in the

HALT mode, the overflow will initialize a ²warm reset²
only the Program Counter and SP are reset to zero. To
clear the WDT contents (including the WDT prescaler ),
3 methods are implemented; external reset (a low level

to RES

), software instructions, or a ²HALT² instruction.
The software instructions include ²CLR WDT² and the
other set -²CLR WDT1² and ²CLR WDT2². Of these
two types of instructions, only one can be active de­pending on the mask option -²CLR WDT times selec-
tion option².Ifthe²CLR WDT²is selected (i.e. CLRWDT
times equal one), any execution of the ²CLR WDT² in­struction will clear the WDT. In case ²CLR WDT1² and
²CLR WDT2² are chosen (i.e. CLRWDT times equal
two), these two instructions must be executed to clear
the WDT; otherwise, the WDT may reset the chip be
cause of time-out.

-

-

S y s t e m C l o c k / 8

W D T P r e s c a l e r

7 - b i t C o u n t e r

8 - t o - 1 M U X

W D T T i m e - o u t

W S 0 ~ W S 2

W D T
O S C

M a s k
O p t i o n
S e l e c t

8 - b i t C o u n t e r

Watchdog Timer

Rev. 1.00 10 August 15, 2005

HT36F2

Power Down Operation - HALT

The HALT mode is initialized by a ²HALT² instruction
and results in the following...

·

The system oscillator will turn off but the WDT oscilla
tor keeps running (If the WDT oscillator is selected).
Watchdog Timer - WDT

·

The contents of the on-chip RAM and registers remain
unchanged

·

The WDT and WDT prescaler will be cleared and
starts to count again (if the clock comes from the WDT
oscillator).

·

All I/O ports maintain their original status.

·

The PDF flag is set and the TO flag is cleared.

·

The HALT pin will output a high level signal to disable
the external ROM.

The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge sig
nal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow per
forms a ²warm reset². By examining the TO and PDF
flags, the cause for a chip reset can be determined. The
PDF flag is cleared when there is a system power-up or by
executing the ²CLR WDT² instruction and it is set when a
²HALT² instruction is executed. The TO flag is set if the
WDT time-out occurs, and causes a wake-up that only re­sets the Program Counter and SP, the others remain in
their original status.

The port A wake-up and interrupt methods can be con­sidered as a continuation of normal execution. Each bit
in port A can be independently selected to wake-up the
device bymask option.Awakening from an I/O port stim­ulus, the program will resume execution of the next in­struction. If awakening from an interrupt, two sequences
may occur. If the related interrupts is disabled or the in
terrupts is enabled but the stack is full, the program will
resume execution at the next instruction. If the interrupt
is enabled and the stack is not full, a regular interrupt re
sponse takes place.

Once a wake-up event occurs, it takes 1024 t

SYS

(sys
tem clock period) to resume to normal operation. In
other words, a dummy cycle period will be inserted after
the wake-up. If the wake-up results from an interrupt ac
knowledge, the actual interrupt subroutine will be de
layed by one more cycle. If the wake-up results in next
instruction execution, this will execute immediately after
a dummy period has finished. If an interrupt request flag
is set to ²1² before entering the HALT mode, the
wake-up function of the related interrupt will be disabled.

To minimize power consumption, all I/O pins should be
carefully managed before entering the HALT status.

Reset

There are 3 ways in which a reset can occur:

·

RES reset during normal operation

·

-

RES reset during HALT

·

WDT time-out reset during normal operation

The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a ²warm re
set² that just resets the Program Counter and SP, leav
ing the other circuits to maintain their state. Some regis
ters remain unchanged during any other reset
conditions. Most registers are reset to the ²initial condi
tion² when the reset conditions are met. By examining
the PDF and TO flags, the program can distinguish be
tween different ²chip resets².

TO PDF RESET Conditions

-

-

0 0 RES

u u RES

0 1 RES

reset during power-up

reset during normal operation

wake-up HALT

1 u WDT time-out during normal operation

1 1 WDT wake-up HALT

Note: ²u² stands for ²unchanged²

To guarantee that the system oscillator has started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses during system
power up or when the system awakes from a HALT
state.

When a system power-up occurs, the SST delay is
added during the reset period. But when the reset co­mes from the RES

pin, the SST delay is disabled. Any

wake-up from HALT will enable the SST delay.

­The functional units chip reset status are shown below.

Program Counter 000H

-

Interrupt Disable

Prescaler Clear

-

WDT

Timer Counter (0/1) Off

-

Input/output ports Input mode

-

Clear. After master reset,
WDT begins counting

Stack Pointer Points to the top of stack

V D D

R E S

S S T T i m e - o u t

C h i p R e s e t

t

Reset Timing Chart

-

-

-

-

-

S S T

Rev. 1.00 11 August 15, 2005

HT36F2

V

D D

R E S

Reset Circuit

The registers status is summarized in the following table:

Register

Reset

(Power On)

WDT Time-out

(Normal Operation)

MP0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

MP1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

Program Counter 0000H 0000H 0000H 0000H 0000H

TBLP

TBLH

xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

WDTS 0000 0111 0000 0111 0000 0111 0000 0111 uuuu uuuu

STATUS --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu

INTC -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu

TMR0L xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

TMR0C 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u 1uuu

TMR1L xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

TMR1C 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u 1uuu

PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu

PAC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu

PB 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu

PBC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu

PF ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu

DAH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

DAL xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

DAC

---- --00 ---- --00 ---- --00 ---- --00 ---- --uu

CHAN 00-- --00 uu-- --uu uu-- --uu uu-- --uu uu-- --uu

FreqNH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

FreqNL xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

AddrH ---x xxxx ---u uuuu ---u uuuu ---u uuuu ---u uuuu

AddrL xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

ReH x--x xxxx u--u uuuu u--u uuuu u--u uuuu u--u uuuu

ReL xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

VolH x--- xxxx u--- uuuu u--- uuuu u--- uuuu u--- uuuu

VolL xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu

H A L T

W D T

W D T

T i m e - o u t

R e s e t

R E S

S S T

O S C I

RES

1 0 - s t a g e

R i p p l e C o u n t e r

P o w e r - o n D e t e c t i n g

Reset

(Normal Operation)

Reset Configuration

RES Reset

(HALT)

W a r m R e s e t

WDT Time-out

(HALT)*

C o l d
R e s e t

Note:

²*² stands for warm reset
²u² stands for unchanged
²x² stands for unknown
²-² stands for unused

Rev. 1.00 12 August 15, 2005

HT36F2

Timer 0/1

Timer 0 is an 8-bit counter, and its clock source comes
from the system clock divided by an 8-stage prescaler.
There are two registers related to Timer 0; TMR0L(0DH)
and TMR0C(0EH). One physical registers are mapped
to TMR0L location; writing TMR0L makes the starting
value be placed in the Timer 0 preload register and
reading the TMR0 gets the contents of the Timer 0 coun
ter. The TMR0C is a control register, which defines the
division ration of the prescaler and counting enable or
disable.

Writing data to B2, B1 and B0 (bits 2, 1, 0 of TMR0C)
can yield various clock sources.

One the Timer 0 starts counting, it will count from the
current contents in the counter to FFH. Once an over
flow occurs, the counter is reloaded from a preload reg
ister, and generates an interrupt request flag (T0F; bit 2
of INTCH). To enable the counting operation, the timer
On bit (TON; bit 4 of TMR0C) should be set to ²1². For
proper operation, bit 7 of TMR0C should be set to ²1²
and bit 3, bit 6 should be set to ²0².

There are two registers related to the Timer Counter1;
TMR1L(10H), TMR1C(11H). The Timer Counter 1 oper
ates in the same manner as Timer Counter 0.

TMR0C/TMR1C

B2 B1 B0

T0F

0 0 0 SYS CLK/16

0 0 1 SYS CLK/32

0 1 0 SYS CLK/64

0 1 1 SYS CLK/128

1 0 0 SYS CLK/256

1 0 1 SYS CLK/512

1 1 0 SYS CLK/1024

1 1 1 SYS CLK/2048

TMR0C Bit 4 to enable/disable timer counting
(1=enable; 0=disable)

TMR0C Bit 3, always write ²0².
TMR0C Bit 5, always write ²0².
TMR0C Bit 6, always write ²0².
TMR0C Bit 7, always write ²1².

T i m e r 0 / 1

S y s t e m
C l o c k / 8

8 - s t a g e

P r e s c a l e r

T O N

T 0 F

-

P r e l o a d R e g i s t e r

T i m e r 0 / 1

Timer 0/1

Input/Output Ports

There are 20 bidirectional input/output lines labeled
from PA to PC0~3, which are mapped to the data mem
ory of[12H], [14H],[16H] respectively. All these I/O ports
can be used for input and output operations. For input
operation, these ports are non-latching, that is, the in

­puts must be ready at the T2 rising edge of instruction

­²MOV A,[m]² (m=12H, 14H or 16H). For output opera

tion, all data is latched and remains unchanged until the
output latch is rewritten.

Each I/O line has its own control register (PAC, PBC,
PCC0~3) to control the input/output configuration. With
this control register, CMOS output or Schmitt trigger in
put with or without pull-high resistor (mask option) struc

­tures can be reconfigured dynamically under software

control. To function as an input, the corresponding latch
of the control register must write a ²1². The pull-high re­sistance will exhibit automatically if the pull-high option
is selected. The input source also depends on the con­trol register. If the control register bit is ²1², input will
read the pad state. If the control register bit is ²0², the
contents of the latches will move to the internal bus. The
latter is possible in ²read-modify-write² instruction. For
output function, CMOS is the only configuration. These
control registers are mapped to locations 13H, 15H and
17H.

After a chip reset, these input/output lines remain at high
levels or floating (mask option). Each bit of these in
put/output latches can be set or cleared by the ²SET
[m].i² or ²CLR [m].i² (m=12H, 14H or 16H) instruction.

Some instructions first input data and then follow the
output operations. For example, the ²SET [m].i², ²CLR
[m].i², ²CPL [m]² and ²CPLA [m]² instructions read the
entire port states into the CPU, execute the defined op
erations (bit-operation), and then write the results back
to the latches or the accumulator. Each line of port A has
the capability to wake-up the device.

D a t a B u s

R e l o a d

O v e r f l o w

-

-

-

-

-

-

-

Rev. 1.00 13 August 15, 2005

D a t a B u s

W r i t e C o n t r o l R e g i s t e r

C h i p R e s e t

R e a d C o n t r o l R e g i s t e r

HT36F2

V

Q

D

C K

Q

S

Q

D

V

D D

D D

W e a k
P u l l - u p

M a s k O p t i o n

I / O L i n e

W r i t e I / O

R e a d I / O

S y s t e m W a k e - U p

C K

Q

S

M a s k O p t i o n

M
U
X

Input/Output Ports

Channel Wavetable Synthesizer

Name Function D7 D6 D5 D4 D3 D2 D1 D0

1DH DAC high byte (no default value) DA15 DA14 DA13 DA12 DA11 DA10 DA9 DA8

1EH DAC low byte (no default value) DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0

DAON=1: DAC ON

1FH

DAON=0: DAC OFF (default)
SELW=1: DACdata fromwavetable

¾¾¾¾¾¾

DAON SELW

SELW=0: DAC data from MCU

20H Channel number selection VM FR CH2 CH1 CH0

21H High byte frequency number BL3 BL2 BL1 BL0 FR11 FR10 FR9 FR8

22H Low byte frequency number FR7 FR6 FR5 FR4 FR3 FR2 FR1 FR0

23H High byte start address ST12 ST11 ST10 ST9 ST8

24H Low byte start address ST7 ST6 ST5 ST4 ST3 ST2 ST1 ST0

25H

Wave bit select,
High byte repeat number

WBS RE12 RE11 RE10 RE9 RE8

26H Low byte repeat number RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0

27H

Envelope control,
Volume control

A_R ENV1 ENV0 VR9 VR8

28H~29H Unused

2AH Volume control VR7 VR6 VR5 VR4 VR3 VR2 VR1 VR0

2BH~2FH Unused

30H~FFH Data memory (RAM) General purpose data memory (same as 8-Bit MCU)

Memory Map (20H~FFH) Register

Note:

²¾² No function, read only, read as ²0².
Unused: No function, read only, read as ²0².

·

CH1~CH0 channel number selection
The HT36F2 has a built-in 8 output channels and
CH1~CH0 is used to define which channel is selected.
When this register is written to, the wavetable synthe
sizer will automatically output the dedicated PCM
code. So this register is also used as a start playing
key and it has to be written to after all the other
wavetable function registers are already defined.

·

Change parameter selection
These two bits, VM and FR, are used to define which

-

register will be updated on this selected channel.
There are two modes that can be selected to reduce
the process of setting the register. Please refer to the
statements of the following table:

VM FR Function

0 0 Update all the parameter

0 1 Only update the frequency number

1 0 Only update the volume

Rev. 1.00 14 August 15, 2005

HT36F2

·

Output frequency definition
The data on BL3~BL0 and FR11~FR0 are used to de
fine the output speed of the PCM file, i.e. it can be
used to generate the tone scale. When the FR11~FR0
is 800H and BL3~BL0 is 6H, each sample data of the
PCM code will be sent out sequentially.
When the f

is 6.4MHz, the formula of a tone fre

OSC

quency is:

25kHz

f

OUT=fRECORD

where f

OUT

x

is the output signal frequency, f

SR

FR11~ FR0

x

(17 BL3~BL0)-

2

RECORD

SR is the frequency and sampling rate on the sample
code, respectively.
So if a voice code of C3 has been recorded which has
the f
frequency (f

of 261Hz and the SR of 11025Hz, the tone

RECORD

) of G3: f

OUT

OUT

=98Hz.

Can be obtained by using the fomula:

98Hz= 261Hz x

25kHz

11025Hz

FR11~ FR0

x

(17 BL3~BL0)-

2
A pair of the values FR11~FR0 and BL3~BL0 can be
determined when the f

·

Start address definition

is 6.4MHz.

OSC

The HT36F2 provides two address types for extended
use, one is the program ROM address which is pro
gram counter corresponding with PF value, the other
is the start address of the PCM code.
The ST15~ST0 is used to define the start address of
each PCM code and reads the waveform data from
this location. The HT36F2 provides 16 input data lines
from WA15~WA0, the ST15~ST0 is used to locate the
major 12 bits i.e. WA15~WA5 and the undefined data
from WA4~WA0 is always set as 00000b. In other
words, the WA15~WA0=ST15~ST0´2

5

. So each
PCM code has to be located at a multiple of 32. Other­wise, the PCM code will not be read out correctly be
cause it has a wrong start code.

·

Waveform format definition
The HT36F2 accepts two waveform formats to ensure
a more economical data space. WBS is used to define
the sample format of each PCM code.

¨

WBS=0 means the sample format is 8-bit

¨

WBS=1 means the sample format is 12-bit

The 12-bit sample format allocates location to each
sample data. Please refer to the waveform format
statement as shown below.

1 B 2 B 3 B 4 B 5 B

8 - B i t

A s a m p l i n g d a t a c o d e ; B m e a n s o n e d a t a b y t e .

1 2 - B i t

1 H 1 M 1 L 2 L

A s a m p l i n g d a t a c o d e

6 B 7 B 8 B

2 H 2 M 3 H 3 M

3 L

and

·

Repeat number definition

-

The repeat number is used to define the address
which is the repeat point of the sample. When the re

­peat number is defined, it will be output from the start
code to the end code once and always output the
range between the repeat address to the end code

-

(80H) until the volume become close.
The RE12~RE0 is used to calculate the repeat ad

­dress of the PCM code. The process for setting the
RE12~RE0 is to write the 2¢s complement of the re
peat length to RE12~RE0, with the highest carry ig

-

­nored. The HT36F2 will get the repeat address by
adding the RE12~RE0 to the address of the end code,
then jump to the address to repeat this range.

·

Volume control
The HT36F2 provides the volume control independ
ently. The volume are controlled by VR9~VR0 respec

-

­tively. The chip provides 1024 levels of controllable
volume, the 000H is the maximum and 3FFH is the
minimum output volume.

·

The PCM code definition
The HT36F2 can only solve the voice format of the

-

signed 8-bit or 12-bit raw PCM. And the MCU will take
the voice code 80H as the end code.
So each PCM code section must be ended with the
end code 80H.

·

Digital to Analog Converter - DAC
The HT36F2 provides one 16-bit voltage type DAC
device controlled by the MCU or Wavetable Synthe­sizer for driving the external speaker through an exter­nal NPN transistor. It is in fact an optional object used
for Wavetable Synthesizer DAC or general DAC, this
is chosen by Mask Option and DAC control register. If

-

the general DAC is chosen for application, then the
Wavetable Synthesizer is disabled since the DAC is
taken up and controlled by the MCU. If general DAC is
selected, the programmer must write the voice data to
register DAL and DAH to get the corresponding ana

­log data. If Mask Option enables the DAC register and
the SELW, then the following table comes useful.

Bit No. Label Function

Bit7~Bit3

Bit1 DAON

No used

¾

DAON=1: DAC ON
DAON=0: DAC OFF (Default)

SELWR=1, Right Channel

Bit0 SELWR

DAC data from Wavetable
SELWR=0, Right Channel
DAC datafrom MCU (Default)

N o t e : " 1 H " H i g h N i b b l e

" 1 M " M i d d l e N i b b l e
" 1 L " L o w N i b b l e

Waveform Format

Rev. 1.00 15 August 15, 2005

Mask Option

No. Mask Option Function

1 WDT source On-chip RC/Instruction clock/ disable WDT

2 CLRWDT times One time, two times (CLR WDT1/WDT2)

3 Wake-up PA only

4 Pull-High PA, PB, PC input

5 OSC mode Crystal or Resistor type

6 LVR Enable/disable

7 LVD 2.2V/3.3V

Application Circuit

V

D D

1 0

W

HT36F2

1 0 0 k

0 . 1mF

6 M H z

1 0 0 k

0 . 1mF

A U D

V S S

A U D

V S S

4 7mF

4 7mF

2 0 k

W

1 0

R 1

1 k

W

V D D V D D A

O S C 1
O S C 2

V

D D

W

R E S

H T 3 6 F 2

V

D D

1 0

V D D V D D A

O S C 1

O S C 2

V

D D

W

R E S

V S S A

W

V S S A

0 . 1mF

V

D D

4 7mF

F

0 . 1

m

2

V r e f

3

F

m

0 . 1mF

V

R 2

7 5 0

W

I N

H T 8 2 V 7 3 3

C E

D D

S P K
8

V D D

8

O U T N

1

7

V S S

O U T P

45

W

S P K
8

W

H T 3 6 F 2

N o t e : R 1 > R 2

Rev. 1.00 16 August 15, 2005

Instruction Set Summary

Mnemonic Description

Arithmetic

ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]

Logic Operation

AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]

Increment & Decrement

INCA [m]
INC [m]
DECA [m]
DEC [m]

Rotate

RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]

Data Move

MOV A,[m]
MOV [m],A
MOV A,x

Bit Operation

CLR [m].i
SET [m].i

Add data memory to ACC
Add ACC to data memory
Add immediate data to ACC
Add data memory to ACC with carry
Add ACC to data memory with carry
Subtract immediate data from ACC
Subtract data memory from ACC
Subtract data memory from ACC with result in data memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry and result in data memory
Decimal adjust ACC for addition with result in data memory

AND data memory to ACC
OR data memory to ACC
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
Exclusive-OR ACC to data memory
AND immediate data to ACC
OR immediate data to ACC
Exclusive-OR immediate data to ACC
Complement data memory
Complement data memory with result in ACC

Increment data memory with result in ACC
Increment data memory
Decrement data memory with result in ACC
Decrement data memory

Rotate data memory right with result in ACC
Rotate data memory right
Rotate data memory right through carry with result in ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
Rotate data memory left through carry with result in ACC
Rotate data memory left through carry

Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC

Clear bit of data memory
Set bit of data memory

Instruction

Cycle

1

(1)

1

1
1

(1)

1

1
1

(1)

1

1

(1)

1

(1)

1

1
1
1

(1)

1

(1)

1

(1)

1

1
1
1

(1)

1

1

1

(1)

1

1

(1)

1

1

(1)

1

1

(1)

1

1

(1)

1

1

(1)

1

1

(1)

1

1

(1)

1

(1)

1

HT36F2

Flag

Affected

Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV

C

Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z

Z
Z
Z
Z

None
None

C

C
None
None

C

C

None
None
None

None
None

Rev. 1.00 17 August 15, 2005

HT36F2

Mnemonic Description

Branch

JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI

Jump unconditionally
Skip if data memory is zero
Skip if data memory is zero with data movement to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result in ACC
Skip if decrement data memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt

Table Read

TABRDC [m]
TABRDL [m]

Read ROM code (current page) to data memory and TBLH
Read ROM code (last page) to data memory and TBLH

Miscellaneous

NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT

No operation
Clear data memory
Set data memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter Power Down Mode

Instruction

Cycle

2

(2)

1

(2)

1

(2)

1

(2)

1

(3)

1

(3)

1

(2)

1

(2)

1

2
2
2
2

(1)

2

(1)

2

1

(1)

1

(1)

1

1
1
1

(1)

1

1
1

Flag

Affected

None
None
None
None
None
None
None
None
None
None
None
None
None

None
None

None
None
None

TO,PDF

(4)

TO

,PDF

(4)

TO

,PDF
None
None

TO,PDF

(4)

(4)

Note: x: Immediate data

m: Data memory address

A: Accumulator

i: 0~7 number of bits

addr: Program memory address

Ö: Flag is affected

-: Flag is not affected

(1)

: Ifa loadingto the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle

(four system clocks).

(2)

: Ifa skippingto the next instruction occurs, the execution cycle of instructions will be delayed for one more

cycle (four system clocks). Otherwise the original instruction cycle is unchanged.

(3):(1)

(4)

(2)

and

: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the

²CLR WDT1² or ²CLR WDT2² instruction, the TO and PDF are cleared.
Otherwise the TO and PDF flags remain unchanged.

Rev. 1.00 18 August 15, 2005

HT36F2

Instruction Definition

ADC A,[m] Add data memory and carry to the accumulator

Description The contents of the specified data memory, accumulator and the carry flag are added si

multaneously, leaving the result in the accumulator.

Operation

Affected flag(s)

ADCM A,[m] Add the accumulator and carry to data memory

Description The contents of the specified data memory, accumulator and the carry flag are added si

Operation

Affected flag(s)

ADD A,[m] Add data memory to the accumulator

Description The contents of the specified data memory and the accumulator are added. The result is

Operation

Affected flag(s)

ACC ¬ ACC+[m]+C

TO PDF OV Z AC C

¾¾ÖÖÖÖ

multaneously, leaving the result in the specified data memory.

[m] ¬ ACC+[m]+C

TO PDF OV Z AC C

¾¾ÖÖÖÖ

stored in the accumulator.

ACC ¬ ACC+[m]

TO PDF OV Z AC C

¾¾ÖÖÖÖ

-

-

ADD A,x Add immediate data to the accumulator

Description The contents of the accumulator and the specified data are added, leaving the result in the

accumulator.

Operation

Affected flag(s)

ADDM A,[m] Add the accumulator to the data memory

Description The contents of the specified data memory and the accumulator are added. The result is

Operation

Affected flag(s)

Rev. 1.00 19 August 15, 2005

ACC ¬ ACC+x

TO PDF OV Z AC C

¾¾ÖÖÖÖ

stored in the data memory.

[m] ¬ ACC+[m]

TO PDF OV Z AC C

¾¾ÖÖÖÖ

HT36F2

AND A,[m] Logical AND accumulator with data memory

Description Data in the accumulator and the specified data memory perform a bitwise logical_AND op

eration. The result is stored in the accumulator.

Operation

Affected flag(s)

AND A,x Logical AND immediate data to the accumulator

Description Data in the accumulator and the specified data perform a bitwise logical_AND operation.

Operation

Affected flag(s)

ANDM A,[m] Logical AND data memory with the accumulator

Description Data in the specified data memory and the accumulator perform a bitwise logical_AND op

Operation

Affected flag(s)

ACC ¬ ACC ²AND² [m]

TO PDF OV Z AC C

¾¾¾ Ö ¾¾

The result is stored in the accumulator.

ACC ¬ ACC ²AND² x

TO PDF OV Z AC C

¾¾¾ Ö ¾¾

eration. The result is stored in the data memory.

[m] ¬ ACC ²AND² [m]

TO PDF OV Z AC C

¾¾¾ Ö ¾¾

-

-

CALL addr Subroutine call

Description The instruction unconditionally calls a subroutine located at the indicated address. The

program counter increments once to obtain the address of the next instruction, and pushes
this onto the stack. The indicated address is then loaded. Program execution continues
with the instruction at this address.

Operation

Affected flag(s)

CLR [m] Clear data memory

Description The contents of the specified data memory are cleared to 0.

Operation

Affected flag(s)

Stack ¬ Program Counter+1
Program Counter ¬ addr

TO PDF OV Z AC C

¾ ¾¾¾¾¾

[m] ¬ 00H

TO PDF OV Z AC C

¾¾¾¾¾¾

Rev. 1.00 20 August 15, 2005

HT36F2

CLR [m].i Clear bit of data memory

Description The bit i of the specified data memory is cleared to 0.

Operation

Affected flag(s)

CLR WDT Clear Watchdog Timer

Description The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are

Operation

Affected flag(s)

CLR WDT1 Preclear Watchdog Timer

Description Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution

Operation

Affected flag(s)

[m].i ¬ 0

TO PDF OV Z AC C

¾¾¾¾¾¾

cleared.

WDT ¬ 00H
PDF and TO ¬ 0

TO PDF OV Z AC C

00

of this instruction without the other preclear instruction just sets the indicated flag which im
plies this instruction has been executed and the TO and PDF flags remain unchanged.

WDT ¬ 00H*
PDF and TO ¬ 0*

TO PDF OV Z AC C

0* 0*

¾¾¾¾

¾¾¾¾

-

CLR WDT2 Preclear Watchdog Timer

Description Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution

of this instruction without the other preclear instruction, sets the indicated flag which im­plies this instruction has been executed and the TO and PDF flags remain unchanged.

Operation

Affected flag(s)

CPL [m] Complement data memory

Description

Operation

Affected flag(s)

WDT ¬ 00H*
PDF and TO ¬ 0*

TO PDF OV Z AC C

0* 0*

Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa.

[m] ¬ [m

]

TO PDF OV Z AC C

¾¾¾ Ö ¾¾

¾¾¾¾

Rev. 1.00 21 August 15, 2005

HT36F2

CPLA [m] Complement data memory and place result in the accumulator

Description

Operation

Affected flag(s)

DAA [m] Decimal-Adjust accumulator for addition

Description The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumu

Operation If ACC.3~ACC.0 >9 or AC=1

Affected flag(s)

Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa. The complemented result
is stored in the accumulator and the contents of the data memory remain unchanged.

ACC ¬ [m

lator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal
carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD ad
justment is done by adding 6 to the original value if the original value is greater than 9 or a
carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored
in the data memory and only the carry flag (C) may be affected.

then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C

]

TO PDF OV Z AC C

¾¾¾ Ö ¾¾

TO PDF OV Z AC C

¾¾¾¾¾ Ö

-

-

DEC [m] Decrement data memory

Description Data in the specified data memory is decremented by 1.

Operation

Affected flag(s)

DECA [m] Decrement data memory and place result in the accumulator

Description Data in the specified data memory is decremented by 1, leaving the result in the accumula

Operation

Affected flag(s)

[m] ¬ [m]-1

TO PDF OV Z AC C

¾¾¾ Ö ¾¾

tor. The contents of the data memory remain unchanged.

ACC ¬ [m]-1

TO PDF OV Z AC C

¾¾¾ Ö ¾¾

-

Rev. 1.00 22 August 15, 2005

HT36F2

HALT Enter Power Down Mode

Description This instruction stops program execution and turns off the system clock. The contents of

the RAM and registers are retained. The WDT and prescaler are cleared. The power down
bit (PDF) is set and the WDT time-out bit (TO) is cleared.

Operation

Affected flag(s)

INC [m] Increment data memory

Description Data in the specified data memory is incremented by 1

Operation

Affected flag(s)

INCA [m] Increment data memory and place result in the accumulator

Description Data in the specified data memory is incremented by 1, leaving the result in the accumula

Operation

Affected flag(s)

Program Counter ¬ Program Counter+1
PDF ¬ 1
TO ¬ 0

TO PDF OV Z AC C

01

[m] ¬ [m]+1

TO PDF OV Z AC C

¾¾¾ Ö ¾¾

tor. The contents of the data memory remain unchanged.

ACC ¬ [m]+1

TO PDF OV Z AC C

¾¾¾ Ö ¾¾

¾¾¾¾

-

JMP addr Directly jump

Description The program counter are replaced with the directly-specified address unconditionally, and

control is passed to this destination.

Operation

Affected flag(s)

MOV A,[m] Move data memory to the accumulator

Description The contents of the specified data memory are copied to the accumulator.

Operation

Affected flag(s)

Program Counter ¬addr

TO PDF OV Z AC C

¾¾¾¾¾¾

ACC ¬ [m]

TO PDF OV Z AC C

¾¾¾¾¾¾

Rev. 1.00 23 August 15, 2005

HT36F2

MOV A,x Move immediate data to the accumulator

Description The 8-bit data specified by the code is loaded into the accumulator.

Operation

Affected flag(s)

MOV [m],A Move the accumulator to data memory

Description The contents of the accumulator are copied to the specified data memory (one of the data

Operation

Affected flag(s)

NOP No operation

Description No operation is performed. Execution continues with the next instruction.

Operation

Affected flag(s)

ACC ¬ x

TO PDF OV Z AC C

¾¾¾¾¾¾

memories).

[m] ¬ACC

TO PDF OV Z AC C

¾¾¾¾¾¾

Program Counter ¬ Program Counter+1

TO PDF OV Z AC C

¾¾¾¾¾¾

OR A,[m] Logical OR accumulator with data memory

Description Data in the accumulator and the specified data memory (one of the data memories) per-

form a bitwise logical_OR operation. The result is stored in the accumulator.

Operation

Affected flag(s)

OR A,x Logical OR immediate data to the accumulator

Description Data in the accumulator and the specified data perform a bitwise logical_OR operation.

Operation

Affected flag(s)

ORM A,[m] Logical OR data memory with the accumulator

Description Data in the data memory (one of the data memories) and the accumulator perform a

Operation

Affected flag(s)

ACC ¬ ACC ²OR² [m]

TO PDF OV Z AC C

¾¾¾ Ö ¾¾

The result is stored in the accumulator.

ACC ¬ ACC ²OR² x

TO PDF OV Z AC C

¾¾¾ Ö ¾¾

bitwise logical_OR operation. The result is stored in the data memory.

[m] ¬ACC ²OR² [m]

TO PDF OV Z AC C

¾¾¾ Ö ¾¾

Rev. 1.00 24 August 15, 2005

HT36F2

RET Return from subroutine

Description The program counter is restored from the stack. This is a 2-cycle instruction.

Operation

Affected flag(s)

RET A,x Return and place immediate data in the accumulator

Description The program counter is restored from the stack and the accumulator loaded with the speci

Operation

Affected flag(s)

RETI Return from interrupt

Description The program counter is restored from the stack, and interrupts are enabled by setting the

Operation

Affected flag(s)

Program Counter ¬ Stack

TO PDF OV Z AC C

¾¾¾¾¾¾

fied 8-bit immediate data.

Program Counter ¬ Stack
ACC ¬ x

TO PDF OV Z AC C

¾¾¾¾¾¾

EMI bit. EMI is the enable master (global) interrupt bit.

Program Counter ¬ Stack
EMI ¬ 1

TO PDF OV Z AC C

¾¾¾¾¾¾

-

RL [m] Rotate data memory left

Description The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.

Operation

Affected flag(s)

RLA [m] Rotate data memory left and place result in the accumulator

Description Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the

Operation

Affected flag(s)

[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7

TO PDF OV Z AC C

¾¾¾¾¾¾

rotated result in the accumulator. The contents of the data memory remain unchanged.

ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7

TO PDF OV Z AC C

¾¾¾¾¾¾

Rev. 1.00 25 August 15, 2005

HT36F2

RLC [m] Rotate data memory left through carry

Description The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 re

places the carry bit; the original carry flag is rotated into the bit 0 position.

Operation

Affected flag(s)

RLCA [m] Rotate left through carry and place result in the accumulator

Description Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the

Operation

Affected flag(s)

[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7

TO PDF OV Z AC C

¾¾¾¾¾ Ö

carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored
in the accumulator but the contents of the data memory remain unchanged.

ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7

TO PDF OV Z AC C

¾¾¾¾¾ Ö

-

RR [m] Rotate data memory right

Description The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.

Operation

Affected flag(s)

RRA [m] Rotate right and place result in the accumulator

Description Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving

Operation

Affected flag(s)

RRC [m] Rotate data memory right through carry

Description The contents of the specified data memory and the carry flag are together rotated 1 bit

Operation

Affected flag(s)

[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0

TO PDF OV Z AC C

¾¾¾¾¾¾

the rotatedresult in the accumulator. The contents of the data memory remain unchanged.

ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0

TO PDF OV Z AC C

¾¾¾¾¾¾

right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.

[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0

TO PDF OV Z AC C

¾¾¾¾¾ Ö

Rev. 1.00 26 August 15, 2005

HT36F2

RRCA [m] Rotate right through carry and place result in the accumulator

Description Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces

the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is
stored in the accumulator. The contents of the data memory remain unchanged.

Operation

Affected flag(s)

SBC A,[m] Subtract data memory and carry from the accumulator

Description The contents of the specified data memory and the complement of the carry flag are sub

Operation

Affected flag(s)

SBCM A,[m] Subtract data memory and carry from the accumulator

Description The contents of the specified data memory and the complement of the carry flag are sub

Operation

Affected flag(s)

ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0

TO PDF OV Z AC C

¾¾¾¾¾ Ö

tracted from the accumulator, leaving the result in the accumulator.

ACC ¬ ACC+[m

TO PDF OV Z AC C

¾¾ÖÖÖÖ

tracted from the accumulator, leaving the result in the data memory.

[m] ¬ ACC+[m

TO PDF OV Z AC C

¾¾ÖÖÖÖ

]+C

]+C

-

-

SDZ [m] Skip if decrement data memory is 0

Description The contents of the specified data memory are decremented by 1. If the result is 0, the next

instruction is skipped. If the result is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc
tion (2 cycles). Otherwise proceed with the next instruction (1 cycle).

Operation

Affected flag(s)

SDZA [m] Decrement data memory and place result in ACC, skip if 0

Description The contents of the specified data memory are decremented by 1. If the result is 0, the next

Operation

Affected flag(s)

Rev. 1.00 27 August 15, 2005

Skip if ([m]-1)=0, [m] ¬ ([m]-1)

TO PDF OV Z AC C

¾¾¾¾¾¾

instruction is skipped. The result is stored in the accumulator but the data memory remains
unchanged. If the result is 0, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy
cles). Otherwise proceed with the next instruction (1 cycle).

Skip if ([m]-1)=0, ACC ¬ ([m]-1)

TO PDF OV Z AC C

¾¾¾¾¾¾

-

-

HT36F2

SET [m] Set data memory

Description Each bit of the specified data memory is set to 1.

Operation

Affected flag(s)

SET [m]. i Set bit of data memory

Description Bit i of the specified data memory is set to 1.

Operation

Affected flag(s)

SIZ [m] Skip if increment data memory is 0

Description The contents of the specified data memory are incremented by 1. If the result is 0, the fol

Operation

Affected flag(s)

[m] ¬ FFH

TO PDF OV Z AC C

¾¾¾¾¾¾

[m].i ¬ 1

TO PDF OV Z AC C

¾¾¾¾¾¾

lowing instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with
the next instruction (1 cycle).

Skip if ([m]+1)=0, [m] ¬ ([m]+1)

TO PDF OV Z AC C

¾¾¾¾¾¾

-

SIZA [m] Increment data memory and place result in ACC, skip if 0

Description The contents of the specified data memory are incremented by 1. If the result is 0, the next

instruction is skipped and the result is stored in the accumulator. The data memory re­mains unchanged. If the result is 0, the following instruction, fetched during the current in­struction execution, is discarded and a dummy cycle is replaced to get the proper
instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).

Operation

Affected flag(s)

SNZ [m].i Skip if bit i of the data memory is not 0

Description If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data

Operation

Affected flag(s)

Skip if ([m]+1)=0, ACC ¬ ([m]+1)

TO PDF OV Z AC C

¾¾¾¾¾¾

memory is not 0, the following instruction, fetched during the current instruction execution,
is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Other
wise proceed with the next instruction (1 cycle).

Skip if [m].i¹0

TO PDF OV Z AC C

¾¾¾¾¾¾

-

Rev. 1.00 28 August 15, 2005

HT36F2

SUB A,[m] Subtract data memory from the accumulator

Description The specified data memory is subtracted from the contents of the accumulator, leaving the

result in the accumulator.

Operation

Affected flag(s)

SUBM A,[m] Subtract data memory from the accumulator

Description The specified data memory is subtracted from the contents of the accumulator, leaving the

Operation

Affected flag(s)

SUB A,x Subtract immediate data from the accumulator

Description The immediate data specified by the code is subtracted from the contents of the accumula

Operation

Affected flag(s)

ACC ¬ ACC+[m

TO PDF OV Z AC C

¾¾ÖÖÖÖ

result in the data memory.

[m] ¬ ACC+[m

TO PDF OV Z AC C

¾¾ÖÖÖÖ

tor, leaving the result in the accumulator.

ACC ¬ ACC+x

TO PDF OV Z AC C

¾¾ÖÖÖÖ

]+1

]+1

+1

-

SWAP [m] Swap nibbles within the data memory

Description The low-order and high-order nibbles of the specified data memory (1 of the data memo-

ries) are interchanged.

Operation

Affected flag(s)

SWAPA [m] Swap data memory and place result in the accumulator

Description The low-order and high-order nibbles of the specified data memory are interchanged, writ

Operation

Affected flag(s)

[m].3~[m].0 « [m].7~[m].4

TO PDF OV Z AC C

¾¾¾¾¾¾

ing the result to the accumulator. The contents of the data memory remain unchanged.

ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0

TO PDF OV Z AC C

¾¾¾¾¾¾

-

Rev. 1.00 29 August 15, 2005

HT36F2

SZ [m] Skip if data memory is 0

Description If the contents of the specified data memory are 0, the following instruction, fetched during

the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).

Operation Skip if [m]=0

Affected flag(s)

TO PDF OV Z AC C

¾¾¾¾¾¾

SZA [m] Move data memory to ACC, skip if 0

Description The contents of the specified data memory are copied to the accumulator. If the contents is

0, the following instruction, fetched during the current instruction execution, is discarded
and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed
with the next instruction (1 cycle).

Operation Skip if [m]=0

Affected flag(s)

TO PDF OV Z AC C

¾¾¾¾¾¾

SZ [m].i Skip if bit i of the data memory is 0

Description If bit i of the specified data memory is 0, the following instruction, fetched during the current

instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc
tion (2 cycles). Otherwise proceed with the next instruction (1 cycle).

Operation Skip if [m].i=0

Affected flag(s)

TO PDF OV Z AC C

¾¾¾¾¾¾

-

TABRDC [m] Move the ROM code (current page) to TBLH and data memory

Description The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved

to the specified data memory and the high byte transferred to TBLH directly.

Operation

Affected flag(s)

TABRDL [m] Move the ROM code (last page) to TBLH and data memory

Description The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to

Operation

Affected flag(s)

Rev. 1.00 30 August 15, 2005

[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)

TO PDF OV Z AC C

¾¾¾¾¾¾

the data memory and the high byte transferred to TBLH directly.

[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)

TO PDF OV Z AC C

¾¾¾¾¾¾

HT36F2

XOR A,[m] Logical XOR accumulator with data memory

Description Data in the accumulator and the indicated data memory perform a bitwise logical Exclu

sive_OR operation and the result is stored in the accumulator.

Operation

Affected flag(s)

XORM A,[m] Logical XOR data memory with the accumulator

Description Data in the indicated data memory and the accumulator perform a bitwise logical Exclu

Operation

Affected flag(s)

XOR A,x Logical XOR immediate data to the accumulator

Description Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op

Operation

Affected flag(s)

ACC ¬ ACC ²XOR² [m]

TO PDF OV Z AC C

¾¾¾ Ö ¾¾

sive_OR operation. The result is stored in the data memory. The 0 flag is affected.

[m] ¬ ACC ²XOR² [m]

TO PDF OV Z AC C

¾¾¾ Ö ¾¾

eration. The result is stored in the accumulator. The 0 flag is affected.

ACC ¬ ACC ²XOR² x

TO PDF OV Z AC C

¾¾¾ Ö ¾¾

-

-

-

Rev. 1.00 31 August 15, 2005

Package Information

16-pin SOP (300mil) Outline Dimensions

HT36F2

1 6

A

1

C

D

E F

Symbol

A 394

B 290

C14

C¢

D92

E

F4

G32

H4

9

B

8

C '

G

H

a

Dimensions in mil

Min. Nom. Max.

¾
¾
¾

390

¾
¾

¾

50

¾¾
¾
¾

a 0°¾10°

419

300

20

413

104

¾

38

12

Rev. 1.00 32 August 15, 2005

28-pin SOP (300mil) Outline Dimensions

HT36F2

2 8

A

1

C

C '

D

E

Symbol

A 394

B 290

C14

C¢

D92

E

F4

G32

H4

1 5

B

1 4

G

H

F

a

Dimensions in mil

Min. Nom. Max.

¾
¾
¾

697

¾
¾

¾

50

¾¾
¾
¾

a 0°¾10°

419

300

20

713

104

¾

38

12

Rev. 1.00 33 August 15, 2005

Product Tape and Reel Specifications

Reel Dimensions

HT36F2

T 2

A

B

T 1

D

SOP 16W (300mil)

Symbol Description Dimensions in mm

A Reel Outer Diameter

B Reel Inner Diameter

C Spindle Hole Diameter

D Key Slit Width

T1 Space Between Flange

T2 Reel Thickness

330±1

62±1.5

13±0.5

2±0.5

16.8+0.3

22.2±0.2

C

-0.2

-0.2

SOP 28W (300mil)

Symbol Description Dimensions in mm

A Reel Outer Diameter

B Reel Inner Diameter

C Spindle Hole Diameter

D Key Slit Width

T1 Space Between Flange

T2 Reel Thickness

330±1

62±1.5

13+0.5

-0.2

2±0.5

24.8+0.3

-0.2

30.2±0.2

Rev. 1.00 34 August 15, 2005

Carrier Tape Dimensions

HT36F2

D

E

F

PD 1

P 1P 0

W

A 0

B 0

C

SOP 16W (300mil)

Symbol Description Dimensions in mm

W Carrier Tape Width

P Cavity Pitch

E Perforation Position

F Cavity to Perforation (Width Direction)

16±0.2
12±0.1

1.75±0.1

7.5±0.1

D Perforation Diameter 1.5+0.1

D1 Cavity Hole Diameter 1.5+0.25

P0 Perforation Pitch

P1 Cavity to Perforation (Length Direction)

A0 Cavity Length

B0 Cavity Width

K0 Cavity Depth

t Carrier Tape Thickness

4±0.1
2±0.1

10.9±0.1

10.8±0.1
3±0.1

0.3±0.05

C Cover Tape Width 13.3

t

K 0

SOP 28W (300mil)

Symbol Description Dimensions in mm

W Carrier Tape Width

P Cavity Pitch

E Perforation Position

F Cavity to Perforation (Width Direction)

24±0.3
12±0.1

1.75±0.1

11.5±0.1

D Perforation Diameter 1.5+0.1

D1 Cavity Hole Diameter 1.5+0.25

P0 Perforation Pitch

P1 Cavity to Perforation (Length Direction)

A0 Cavity Length

B0 Cavity Width

K0 Cavity Depth

t Carrier Tape Thickness

4±0.1
2±0.1

10.85±0.1

18.34±0.1

2.97±0.1

0.35±0.01

C Cover Tape Width 21.3

Rev. 1.00 35 August 15, 2005

Holtek Semiconductor Inc. (Headquarters)

No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: [phone]
Fax: [phone]
http://www.holtek.com.tw

Holtek Semiconductor Inc. (Taipei Sales Office)

4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: [phone]
Fax: [phone]
Fax: [phone] (International sales hotline)

HT36F2

Holtek Semiconductor Inc. (Shanghai Sales Office)

7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233
Tel: [phone]
Fax: [phone]
http://www.holtek.com.cn

Holtek Semiconductor Inc. (Shenzhen Sales Office)

5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District,
Shenzhen, China 518057
Tel: [phone]
Fax: [phone]

Holtek Semiconductor Inc. (Beijing Sales Office)

Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031
Tel: [phone]
Fax: [phone]

Holtek Semiconductor Inc. (Chengdu Sales Office)

709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016
Tel: [phone]
Fax: [phone]

Holmate Semiconductor, Inc. (North America Sales Office)

46729 Fremont Blvd., Fremont, CA 94538
Tel: [phone]
Fax: [phone]
http://www.holmate.com

Copyright Ó 2005 by HOLTEK SEMICONDUCTOR INC.

The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as
sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.

-

Rev. 1.00 36 August 15, 2005