HOLTEK HT36F2 User Manual

Music Synthesizer 8-Bit MCU

Technical Document

·

Tools Information

·

FAQs

·

Application Note

Features

·

Operating voltage: 2.4V~5.0V

·

Operating frequency:
Xtal: 6MHz~8MHz
R

: typ. 6MHz

OSC

·

Built-in 32K´16-bit (0.5M-bit) ROM for program/data
shared

·

Built-in 8 bit MCU with 208´8 bits RAM

·

Two 8bit programmabletimer with 8 stage prescaler

·

16 bidirectional I/O lines

·

Four polyphonic synthesizer

·

Mono 16-bit DAC

HT36F2

·

Oscillation modes: XTAL/RCOSC

·

Low voltage reset

·

Eight-level subroutine nesting

·

Watchdog timer

·

Supports 8-bit table read instruction (TBLP)

·

HALT function and wake-up feature reduce power
consumption

·

Bit manipulation instructions

·

63 powerful instructions

·

All instructions in 1 or 2 machine cycles

·

16/28-pin SOP package

General Description

The HT36F2 is an 8-bit high performance RISC archi­tecture microcontroller specifically designed for various
music applications. It provides an 8-bit MCU and a
4-channel Wavetable synthesizer. It has a built-in 8-bit

Block Diagram

P A 0 ~ P A 7
P B 0 ~ P B 7

O S C 1

O S C 2

R E S

8 - B i t
M C U

3 2 K´1 6 - b i t

M u l t i p l i e r / P h a s e

microprocessor which controls the synthesizer to gen­erate the melody by setting the special register. A HALT
feature is provided to reduce power consumption.

R O M

2 0 8´8

R A M

G e n e r a l

1 6 - B i t

D A C

V D D

V S S
V D D A
V S S A

A U D

Rev. 1.00 1 August 15, 2005

Pin Assignment

2

HT36F2

A U D

V D D A

V S S A

O S C 2

O S C 1

V S S

V D D

R E S

Pad Assignment

A U D

T E S T

V D D A

V S S A

1

2

3

4

5

6

7

8

H T 3 6 F 2

1 6 S O P - A

1

2

3

4

P B 1

1

P B 0

2

A U D

3

T E S T

4

V D D A

V S S A

P A 7

1 6

P A 6

1 5

P A 5

1 4

P A 4

1 3

P A 3

1 2

P A 2

1 1

P A 1

1 0

P A 0

9

O S C 2

O S C 1

P B 0

2 5 2 4

5

6

7

8

V S S

9

V D D

1 0

R E S

1 1

N C

1 2

N C

1 3

N C

1 4

H T 3 6 F 2

2 8 S O P - A

P B 5

P B 4

P B 3

P B 2

P B 1

2 22 3

2 1

2 0

P B 2

2 8

P B 3

2 7

P B 4

2 6

P B 5

2 5

P B 6

2 4

P B 7

2 3

P A 7

2 2

P A 6

2 1

P A 5

2 0

P A 4

1 9

P A 3

1 8

P A 2

1 7

P A 1

1 6

P A 0

1 5

1 9

P B 6

1 8

P B 7

1 7

P A 7

1 6

P A 6

1 5

P A 5

1 4

P A 4

1 3

P A 3

( 0 , 0 )

V S S

V D D

R E S

5

6

7

8

9

Chip size: 2135 ´ 2385 (mm)

2

1 0

P A0P A 1

1 1

1 2

P A

O S C 2

O S C 1

* The IC substrate should be connected to VSS in the PCB layout artwork.

Rev. 1.00 2 August 15, 2005

HT36F2

Pad Coordinates

Pad No. X Y Pad No. X Y

1

2

3

4

5

6

7

8

9

10 710.500

11 810.500

12 921.100

13 916.350 414.500

-876.150

-876.150

-876.150

-876.150

-916.350 -63.124

-916.350 -740.976

-916.350 -842.650

-916.350 -942.650

-916.350 -1044.324

1043.000 14 916.350 514.500

931.200 15 916.350 625.100

817.560 16 916.350 725.100

715.600 17 916.350 835.700

18 916.350 935.700

19 916.350 1046.300

20 704.250 1041.550

21 593.650 1041.550

22 493.650 1041.550

-1041.350

-1041.350

-1041.350

23 383.050 1041.550

24 283.050 1041.550

25 172.450 1041.550

Pad Description

Pad No. Pad Name I/O

8, 7 VDD, VSS

3,4 VDDA, VSSA

10~17 PA0~PA7 I/O

25~18 PB0~PB7 I/O

9 RESET

6 OSC1 I

5 OSC2 O

1 AUD O

Internal

Connection

¾¾

¾¾

Wake-up,

Pull-high or

None

Pull-high or

None

I

¾

X¢tal/Resistor XIN for X¢tal or ROSCIN for resistor by mask option

¾

¾

Digital power supply, ground

DAC power supply

Bidirectional 8-bit I/O port, wake-up by mask option

Bidirectional 8-bit I/O port

Reset input, active low

XOUT or T1

DAC output interface

Function

Unit: mm

Absolute Maximum Ratings

Supply Voltage ..........................VSS-0.3V to VSS+5.5V

Input Voltage .............................V

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may

cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil
ity.

Rev. 1.00 3 August 15, 2005

3V to VDD+0.3V

SS-0.

Storage Temperature ...........................-50°Cto125°C

Operating Temperature ..........................-25°Cto70°C

-

HT36F2

Electrical Characteristics

Symbol Parameter

V

I

I

I

I

V

V

DD

DD

STB

OH

OL

IH

IL

Operating Voltage

Operating Current

Standby Current

Flag Source Current

Flag Sink Current

Input High Voltage for I/O Ports

Input Low Voltage for I/O Ports

Test Conditions

V

DD

Conditions

¾¾

3V

No load(OSC= 6MHz)

4.5V

3V

4.5V

¾

3V

4.5V

¾

3V

4.5V

¾

¾¾

¾¾

Ta=25°C

Min. Typ. Max. Unit

2.4 4.5 5 V

¾

¾

¾

¾

5

5

0.8V

0

28

810

1

13

¾¾

¾¾

¾

DD

¾

V

0.2V

¾

DD

DD

mA

mA

mA

mA

V

V

Rev. 1.00 4 August 15, 2005

Function Description

Execution Flow

The system clock for the HT36F2 is derived from either
a crystal or an RC oscillator. The oscillator frequency di
vided by 2 is the system clock for the MCU and it is inter
nally divided into four non-overlapping clocks. One
instruction cycle consists of four system clock cycles.

Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while de
coding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruc
tion to effectively execute in one cycle. If an instruction
changes the program counter, two cycles are required
to complete the instruction.

Program Counter - PC

The 13-bit program counter (PC) controls the sequence
in which the instructions stored in program ROM are ex
ecuted and its contents specify a maximum of 8192 ad
dresses for each bank.

After accessing a program memory word to fetch an in
struction code, the contents of the program counter are
incremented by one. The program counter then points
to the memory word containing the next instruction
code.

When executing a jump instruction, conditional skip ex
ecution, loading PCL register, subroutine call, initial re
set, internal interrupt, external interrupt or return from

­subroutine, the PC manipulates the program transfer by

­loading the address corresponding to each instruction.

The conditional skip is activated by instruction. Once the
condition is met, the next instruction, fetched during the
current instruction execution, is discarded and a dummy

­cycle replaces it to retrieve the proper instruction. Other

wise proceed with the next instruction.

-

The lower byte of the program counter (PCL) is a read
able and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within 256 locations.

Once a control transfer takes place, an additional
dummy cycle is required.

-

-

Program ROM

HT36F2 provides 16 address lines WA15~WA0 to read

-

the Program ROM which is up to 0.5M bits, and is com
monly used for the

wavetable

voice codes and the pro
gram memory. It provides two address types, one type is
for program ROM, which is addressed by a bank pointer
PF1~PF0 and a 13-bit program counter PC12~PC0;

HT36F2

-

-

-

-

-

-

S y s t e m C l o c k o f M C U

( S y s t e m C l o c k / 2 )

T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4

P C

P C P C + 1 P C + 2

F e t c h I N S T ( P C )

E x e c u t e I N S T ( P C - 1 )

F e t c h I N S T ( P C + 1 )

E x e c u t e I N S T ( P C )

F e t c h I N S T ( P C + 2 )

E x e c u t e I N S T ( P C + 1 )

Execution Flow

Mode

*14 *13 *12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0

Program Counter

Initial Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Timer/Event Counter 0 Overflow PF1 PF0 0 0 0 0 0 0 0 0 0 1 0 0 0

Timer/Event Counter 1 Overflow PF1 PF0 0 0 0 0 0 0 0 0 0 1 1 0 0

Skip Program Counter+2

Loading PCL PF1 PF0 *12 *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0

Jump, Call Branch PF1 PF0 #12 #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0

Return From Subroutine PF1 PF0 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

Program Counter

Note: *12~*0: Bits of Program Counter

@7~@0: Bits of PCL

#12~#0: Bits of Instruction Code

S12~S0: Bits of Stack Register

@7~@0: Bits of PCL

PF1~PF0: Bits of Bank Register

Rev. 1.00 5 August 15, 2005

HT36F2

and the other type is for wavetable code, which is ad
dressed by the start address ST15~ST0. On the pro

13

gram type, WA15~WA0=PF1~PF0´2

+PC12~PC0.

On the wave table ROM type, WA15~WA0=
ST15~ST0´2

5

.

Program Memory - ROM

The program memory is used to store the program in
structions which are to be executed. It also contains
data, table, and interrupt entries, and is organized into
8192´16 bits, addressed by the bank pointer, program
counter and table pointer.

Certain locations in the program memory of each bank
are reserved for special usage:

·

Location 000H on bank0
This area is reserved for the initialization program. Af
ter chip reset, the program always begins execution at
location 000H on bank0.

·

Location 008H
This area is reserved for the Timer Counter 0 interrupt
service program on each bank. If timer interrupt results
from a timer counter 0 overflow, and if the interrupt is en
abled and the stack is not full, the program begins exe
cution at location 008H corresponding to its bank.

·

Location 00CH
This area is reserved for the Timer Counter 1 interrupt
service program on each bank. If a timer interrupt re­sults from a Timer Counter 1 overflow, and if the inter­rupt is enabled and the stack is not full, the program
begins execution at location 00CH corresponding to
its bank.

·

Table location
Any location in the ROM space can be used as
look-up tables. The instructions ²TABRDC [m]² (the
current page, 1 page=256 words) and ²TABRDL [m]²
(the last page) transfer the contents of the lower-order
byte to the specified data memory, and the
higher-order byte to TBLH (08H). Only the destination
of the lower-order byte in the table is well-defined, the
higher-order byte of the table word are transferred to
the TBLH. The Table Higher-order byte register
(TBLH) is read only. The Table Pointer (TBLP) is a
read/write register (07H), which indicates the table lo
cation. Before accessing the table, the location must

0 0 0 0 H

-

-

0 0 0 8 H

0 0 0 C H

n 0 0 H

-

n F F H

1 F F F H

D e v i c e i n i t i a l i z a t i o n p r o g r a m

T i m e r C o u n t e r 0 i n t e r r u p t s u b r o u t i n e

T i m e r C o u n t e r 1 i n t e r r u p t s u b r o u t i n e

L o o k - u p t a b l e ( 2 5 6 w o r d s )

L o o k - u p t a b l e ( 2 5 6 w o r d s )

1 6 b i t s

N o t e : n r a n g e s f r o m 0 0 t o 3 F .

Program Memory for Each Bank

­be placed in TBLP. The TBLH is read only and cannot

be restored. If the main routine and the ISR (Interrupt
Service Routine) both employ the table read instruc
tion, the contents of the TBLH in the main routine are
likely to be changed by the table read instruction used
in the ISR. Errors can occur. In this case, using the ta

-

-

ble read instruction in the main routine and the ISR si
multaneously should be avoided. However, if the
table read instruction has to be applied in both the
main routine and the ISR, the interrupt should be dis­abled prior to the table read instruction. It will not be
enabled until the TBLH has been backed up. All table
related instructions need 2 cycles to complete the op­eration. These areas may function as normal program
memory depending upon user requirements.

·

Bank pointer
The program memory is organized into 4 banks and
each bank into 8192´16 bits of program ROM.
PF1~PF0 is used as the bank pointer. After an instruc
tion has been executed to write data to the PF register
to select a different bank, note that the new bank will
not be selected immediately. It is not until the following
instruction has completed execution that the bank will
be actually selected. It should be note that the PF reg
ister hasto becleared before setting to output mode.

Wavetable ROM

The ST15~ST0 is used to defined the start address of

-

each sample on the wavetable and read the waveform
data from the location. HT36F2 provides 16 output ad

P r o g r a m
R O M

-

-

-

-

-

-

Instruction (s)

*14 *13 *12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0

Table Location

TABRDC [m] P14 P13 P12 P11 P10 P9 P8 @7 @6 @5 @4 @3 @2 @1 @0

TABRDL [m] P14 P13 11111@7@6@5@4@3@2@1@0

Table Location

Note: *12~*0: Bits of table location

@7~@0: Bits of table pointer

P12~P8: Bits of current Program Counter

P14~P13: Bits of Bank PF1~PF0

Rev. 1.00 6 August 15, 2005

dress lines from WA15~WA0, the ST15~ST0 is used to
locate the major 11 bits i.e. WA15~WA5 and the unde
fined data from WA4~WA0 is always set to 00000b. So
the start address of each sample have to be located at a
multiple of 32. Otherwise, the sample will not be read
out correctly because it has a wrong starting code.

Stack Register - Stack

This is a special part of the memory which is used to
save the contents of the program counter only. The
stack is organized into 8 levels and is neither part of the
data nor part of the program space, and is neither read
able nor writeable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor writeable.
At a subroutine call or interrupt acknowledgment, the
contents of the program counter are pushed onto the
stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction (RET or RETI), the pro
gram counter is restored to its previous value from the
stack. Aftera chip reset, the SP will point tothe top of the
stack.

If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledgment will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow al­lowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a CALL is subse­quently executed, a stack overflow occurs and the first
entry will be lost (only the most recent eight return ad­dress are stored).

Data Memory - RAM

The datamemory is designed with 256 ´8 bits. The data
memory is divided into three functional groups: special
function registers, wavetable function register, and gen
eral purpose data memory (208´8). Most of them are
read/write, but some are read only.

The special function registers include the Indirect Ad
dressing register 0 (00H), the Memory Pointer register 0
(MP0;01H), the Indirect Addressing register 1 (02H), the
Memory Pointer register 1 (MP1;03H), the Accumulator
(ACC;05H), the Program Counter Lower-byte register
(PCL;06H), the Table Pointer (TBLP;07H), the Table
Higher-order byte register (TBLH;08H), the Watchdog
Timer option Setting register (WDTS;09H), the Status
register (STATUS;0AH), the Interrupt Control register
(INTC;0BH), the Timer Counter 0 Lower-order byte reg
ister (TMR0L;0DH), the Timer Counter 0 Control regis
ter (TMR0C;0EH), the Timer Counter 1 Lower-order
byte register (TMR1L;10H), the Timer Counter 1 Control
register (TMR1C;11H), the I/O registers (PA;12H,
PB;14H) and the I/O control registers (PAC;13H,
PBC;15H, PCC;17H). The program ROM bank select
(PF;1CH). The DAC High byte (DAH;1DH). The DAC
low byte (DAL;1EH). The DAC control (DAC;1FH). The

I n d i r e c t A d d r e s s i n g R e g i s t e r 0

0 0 H

0 1 H

-

0 2 H

I n d i r e c t A d d r e s s i n g R e g i s t e r 1

0 3 H

0 4 H

0 5 H

0 6 H

0 7 H

0 8 H

0 9 H

0 A H

0 B H

0 C H

-

0 D H

0 E H

0 F H

1 0 H

1 1 H

1 2 H

1 3 H

-

1 4 H

1 5 H

1 6 H

1 7 H
1 8 H

1 9 H

1 A H

1 B H

1 C H

1 D H
1 E H

1 F H

2 0 H

C h a n n e l N u m b e r S e l e c t ( C H A N )

F r e q u e n c y N u m b e r H i g h B y t e ( F r e q N H )

2 1 H

F r e q u e n c y N u m b e r L o w B y t e ( F r e q N L )

2 2 H

S t a r t A d d r e s s H i g h B y t e ( A d d r H )

2 3 H

2 4 H

S t a r t A d d r e s s L o w B y t e ( A d d r L )

2 5 H

R e p e a t N u m b e r H i g h B y t e ( R e H )

2 6 H

R e p e a t N u m b e r L o w B y t e ( R e L )

V o l u m e C o n t r o l H i g h ( V o l H )

2 7 H

2 8 H

-

2 9 H

2 A H
2 B H

M P 0

M P 1

A C C

P C L

T B L P

T B L H

W D T S

S T A T U S

I N T C

T M R 0 L

T M R 0 C

T M R 1 L
T M R 1 C

P A

P A C

P B

P B C

P F

D A C H i g h B y t e ( D A H )

D A C L o w B y t e ( D A L )

D A C C o n t r o l ( D A C )

V o l u m C o n t r o l ( V o l L )

S p e c i a l P u r p o s e
D A T A M E M O R Y

W a v e t a b l e F u n c t i o n
R e g i s t e r

-

2 F H

3 0 H

G e n e r a l P u r p o s e
D A T A M E M O R Y

( 2 0 8 B y t e s )

F F H

-

-

RAM Mapping

: U n u s e d .
R e a d a s " 0 0 "

wavetable function registers is defined between
20H~2AH. The remaining space before the 30H is re
served for future expanded usage and reading these lo
cations will return the result 00H. The general purpose
data memory, addressed from 30H to FFH, is used for
data and control information under instruction com
mand.

HT36F2

-

-

-

Rev. 1.00 7 August 15, 2005

HT36F2

All data memory areas can handle arithmetic, logic, in
crement, decrement and rotate operations directly. Ex
cept for some dedicated bits, each bit in the data
memory can be set and reset by the ²SET [m].i² and
²CLR [m].i²instructions, respectively. They are also indi
rectly accessible through Memory pointer registers
(MP0:01H, MP1:03H).

Indirect Addressing Register

Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write op
eration of [00H] and [02H] access data memory pointed
to by MP0 (01H) and MP1 (03H) respectively. Reading
location 00H or 02H directly will return the result 00H.
And writing directly results in no operation.

The function of data movement between two indirect ad
dressing registers, is not supported. The memory
pointer registers, MP0 and MP1, are 8-bit register which
can be used to access the data memory by combining
corresponding indirect addressing registers.

-

Status Register - STATUS

-

This 8-bit register (0AH) contains the zero flag (Z), carry
flag (C), auxiliary carry flag (AC), overflow flag (OV),
power down flag (PDF) and Watchdog time-out flag

-

(TO). It also records the status information and controls the
operation sequence.

With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like any
other register. Any data written into the status register
will not change the TO or PDF flags. In addition it should

-

be noted that operations related to the status register
may give different results from those intended. The TO
and PDF flags can only be changed by system power
up, Watchdog Timer overflow, executing the ²HALT² in
struction and clearing the Watchdog Timer.

-

The Z, OV, AC and C flags generally reflect the status of
the latest operations.

In addition, on entering the interrupt sequence or exe
cuting a subroutine call, the status register will not be
automatically pushed onto the stack. If the contents of

Accumulator

The accumulator closely relates to ALU operations. It is
mapped to location 05H of the data memory and it can
operate with immediate data. The data movement be
tween two data memory locations must pass through
the accumulator.

status are important and the subroutine can corrupt the
status register, the programmer must take precautions
to save it properly.

-

Interrupt

The HT36F2 provides two internal timer counter inter­rupts on each bank. The Interrupt Control register

Arithmetic and Logic Unit - ALU

This circuit performs 8-bit arithmetic and logic operation.
The ALU provides the following functions:

·

Arithmetic operations (ADD, ADC, SUB, SBC, DAA)

·

Logic operations (AND, OR, XOR, CPL)

·

Rotation (RL, RR, RLC, RRC)

·

Increment & Decrement (INC, DEC)

·

Branch decision (SZ, SNZ, SIZ, SDZ ....)

The ALU not only saves the results of a data operation but
can also change the status register.

(INTC;0BH) contains the interrupt control bits that sets
the enable/disable and the interrupt request flags.

Once an interrupt subroutine is serviced, all other inter­rupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may occur during this interval but only
the interrupt request flag is recorded. If a certain inter
rupt needs servicing within the service routine, the pro
grammer may set the EMI bit and the corresponding bit
of the INTC to allow interrupt nesting. If the stack is full,
the interrupt request will not be acknowledged, even if

Bit No. Label Function

C is set if an operation results in a carry during an addition operation or if a borrow does not

0C

take place during a subtraction operation; otherwise C is cleared. Also it is affected by a ro
tate through carry instruction.

1AC

AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.

2 Z Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.

3OV

4 PDF

5TO

6~7

OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.

PDF is cleared by either a system power-up or executing the ²CLR WDT² instruction. PDF
is set by executing the ²HALT² instruction.

TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO
is set by a WDT time-out.

¾ Unused bit, read as ²0²

Status (0AH) Register

-

-

-

-

-

Rev. 1.00 8 August 15, 2005

HT36F2

the related interrupt is enabled, until the SP is decre
mented. If immediate service is desired, the stack must
be prevented from becoming full.

All these kinds of interrupt have a wake-up capability. As
an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack and then
branching to subroutines at specified locations in the
program memory. Only the program counter is pushed
onto the stack. If the contents of the register and Status
register (STATUS) are altered by the interrupt service
program which may corrupt the desired control se
quence, then the programmer must save the contents
first.

The internal Timer Counter 0 interrupt is initialized by
setting the Timer Counter 0 interrupt request flag (T0F;
bit 5 of INTC), caused by a Timer Counter 0 overflow.
When the interrupt is enabled, and the stack is not full
and the T0F bit is set, a subroutine call to location 08H
will occur. The related interrupt request flag (T0F) will be
reset and the EMI bit cleared to disable further inter
rupts.

The Timer Counter 1 interrupt is operated in the same
manner as Timer Counter 0. The related interrupt con
trol bits ET1I and T1F of the Timer Counter 1 are bit 3
and bit 6 of the INTC respectively.

During the execution of an interrupt subroutine, other in­terrupt acknowledgments are held until the ²RETI² in­struction is executed or the EMI bit and the related
interrupt control bit are set to 1 (if the stack is not full). To
return from the interrupt subroutine, the ²RET² or
²RETI² instruction may be invoked. RETI will set the
EMI bit to enable an interrupt service, but RET will not.

Interrupts occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter
rupts are enabled. In the case of simultaneous requests
the priorities in the following table apply. These can be
masked by resetting the EMI bit.

Interrupt Source Priority Vector

Timer Counter 0 overflow 1 08H

Timer Counter 1 overflow 2 0CH

The Timer Counter 0/1 interrupt request flag (T0F/T1F),

­Enable Timer Counter 0/1 bit (ET0I/ET1I) and Enable
Master Interrupt bit (EMI) constitute an interrupt control
register (INTC) which is located at 0BH in the data mem
ory. EMI, ET0I, ET1I are used to control the en
abling/disabling of interrupts. These bits prevent the
requested interrupt from being serviced. Once the inter
rupt request flags (T0F, T1F) are set, they will remain in
the INTC register until the interrupts are serviced or
cleared by a software instruction.

-

It is recommended that a program does not use the
²CALL subroutine² within the interrupt subroutine. Be
cause interrupts often occur in an unpredictable manner
or need to be serviced immediately in some applica
tions, if only one stack is left and enabling the interrupt is
not well controlled, once the ²CALL subroutine² operates
in the interrupt subroutine, it may damage the original
control sequence.

Oscillator Configuration

­The HT36F2 provides two types of oscillator circuit for

the system clock,i.e., RC oscillator and crystal oscillator.
No matter what type of oscillator, the signal divided by 2

­is used for the system clock. The HALT mode stops the

system oscillator and ignores external signal to con
serve power. If the RC oscillator is used, an external re­sistor between OSC1 and VSS is required. The system
clock, divided by 4, is available on OSC2 with pull-high
resistor, which can be used to synchronize external
logic. The RC oscillator provides the most cost effective
solution. However, the frequency of the oscillation may
vary with VDD, temperature, and the chip itself due to
process variations. It is therefore, not suitable for timing
sensitive operations where accurate oscillator fre­quency is desired.

-

O S C 1

O S C 2

C r y s t a l O s c i l l a t o r R C O s c i l l a t o r

V

D D

f

S Y S

/ 8

System Oscillator

-

-

-

-

-

-

O S C 1

O S C 2

Bit No. Label Function

0 EMI Controls the Master (Global) interrupt (1=enabled; 0=disabled)

1, 4, 7

¾ Unused bit, read as ²0²

2 ET0I Controls the Timer Counter 0 interrupt (1=enabled; 0=disabled)

3 ET1I Controls the Timer Counter 1 interrupt (1=enabled; 0=disabled)

5 T0F Internal Timer Counter 0 request flag (1=active; 0=inactive)

6 T1F Internal Timer Counter 1 request flag (1=active; 0=inactive)

INTC (0BH) Register

Rev. 1.00 9 August 15, 2005

HT36F2

On the other hand, if the crystal oscillator is selected, a
crystal across OSC1 and OSC2 is needed to provide the
feedback and phase shift required for the oscillator, and
no other external components are required. A resonator
may be connected between OSC1 and OSC2 to replace
the crystal and to get a frequency reference, but two ex
ternal capacitors in OSC1 and OSC2 are required.

The WDT oscillator is a free running on-chip RC oscilla
tor, and no external components are required. Even if
the system enters the Power Down Mode, the system
clock is stopped, but the WDT oscillator still works with a
period of approximately 78ms. The WDT oscillator can
be disabled by mask option to conserve power.

Watchdog Timer - WDT

The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator) or instruction clock (sys
tem clock of the MCU divided by 4), determined by mask
options. This timer is designed to prevent a software
malfunction or sequence jumping to an unknown loca
tion withunpredictable results.The Watchdog Timer can
be disabled by mask option. If the Watchdog Timer is
disabled, all the executions related to the WDT result in
no operation.

Once the internal WDT oscillator (RC oscillator with a
period of 78ms normally) is selected, it is first divided by
256 (8-stages) to get the nominal time-out period of ap­proximately 20ms. This time-out period may vary with
temperature, VDD and process variations. By invoking
the WDT prescaler, longer time-out periods can be real­ized. Writing data to WS2, WS1, WS0 (bit 2,1,0 of the
WDTS) can give different time-out periods. If WS2,
WS1, WS0 all equal to 1, the division ratio is up to 1:128,
and the maximum time-out period is 2.6 seconds.

If the WDT oscillator is disabled, the WDT clock may still
come from the instruction clock and operate in the same
manner except that in the HALT state the WDT may stop
counting and lose its protecting purpose. In this situation

the logic can only be restarted by external logic. The
high nibble and bit 3 of the WDTS are reserved for user
defined flags, and the programmer may use these flags
to indicate some specified status.

-

-

WS2 WS1 WS0 Division Ratio

000 1:1

001 1:2

010 1:4

011 1:8

1 0 0 1:16

1 0 1 1:32

1 1 0 1:64

1 1 1 1:128

If the device operates in a noisy environment, using the

­on-chip RC oscillator (WDT OSC) is strongly recom

mended, since the HALT will stop the system clock.

The WDT overflow under normal operation will initialize

­a ²chip reset² and set the status bit TO. Whereas in the

HALT mode, the overflow will initialize a ²warm reset²
only the Program Counter and SP are reset to zero. To
clear the WDT contents (including the WDT prescaler ),
3 methods are implemented; external reset (a low level

to RES

), software instructions, or a ²HALT² instruction.
The software instructions include ²CLR WDT² and the
other set -²CLR WDT1² and ²CLR WDT2². Of these
two types of instructions, only one can be active de­pending on the mask option -²CLR WDT times selec-
tion option².Ifthe²CLR WDT²is selected (i.e. CLRWDT
times equal one), any execution of the ²CLR WDT² in­struction will clear the WDT. In case ²CLR WDT1² and
²CLR WDT2² are chosen (i.e. CLRWDT times equal
two), these two instructions must be executed to clear
the WDT; otherwise, the WDT may reset the chip be
cause of time-out.

-

-

S y s t e m C l o c k / 8

W D T P r e s c a l e r

7 - b i t C o u n t e r

8 - t o - 1 M U X

W D T T i m e - o u t

W S 0 ~ W S 2

W D T
O S C

M a s k
O p t i o n
S e l e c t

8 - b i t C o u n t e r

Watchdog Timer

Rev. 1.00 10 August 15, 2005

HT36F2

Power Down Operation - HALT

The HALT mode is initialized by a ²HALT² instruction
and results in the following...

·

The system oscillator will turn off but the WDT oscilla
tor keeps running (If the WDT oscillator is selected).
Watchdog Timer - WDT

·

The contents of the on-chip RAM and registers remain
unchanged

·

The WDT and WDT prescaler will be cleared and
starts to count again (if the clock comes from the WDT
oscillator).

·

All I/O ports maintain their original status.

·

The PDF flag is set and the TO flag is cleared.

·

The HALT pin will output a high level signal to disable
the external ROM.

The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge sig
nal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow per
forms a ²warm reset². By examining the TO and PDF
flags, the cause for a chip reset can be determined. The
PDF flag is cleared when there is a system power-up or by
executing the ²CLR WDT² instruction and it is set when a
²HALT² instruction is executed. The TO flag is set if the
WDT time-out occurs, and causes a wake-up that only re­sets the Program Counter and SP, the others remain in
their original status.

The port A wake-up and interrupt methods can be con­sidered as a continuation of normal execution. Each bit
in port A can be independently selected to wake-up the
device bymask option.Awakening from an I/O port stim­ulus, the program will resume execution of the next in­struction. If awakening from an interrupt, two sequences
may occur. If the related interrupts is disabled or the in
terrupts is enabled but the stack is full, the program will
resume execution at the next instruction. If the interrupt
is enabled and the stack is not full, a regular interrupt re
sponse takes place.

Once a wake-up event occurs, it takes 1024 t

SYS

(sys
tem clock period) to resume to normal operation. In
other words, a dummy cycle period will be inserted after
the wake-up. If the wake-up results from an interrupt ac
knowledge, the actual interrupt subroutine will be de
layed by one more cycle. If the wake-up results in next
instruction execution, this will execute immediately after
a dummy period has finished. If an interrupt request flag
is set to ²1² before entering the HALT mode, the
wake-up function of the related interrupt will be disabled.

To minimize power consumption, all I/O pins should be
carefully managed before entering the HALT status.

Reset

There are 3 ways in which a reset can occur:

·

RES reset during normal operation

·

-

RES reset during HALT

·

WDT time-out reset during normal operation

The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a ²warm re
set² that just resets the Program Counter and SP, leav
ing the other circuits to maintain their state. Some regis
ters remain unchanged during any other reset
conditions. Most registers are reset to the ²initial condi
tion² when the reset conditions are met. By examining
the PDF and TO flags, the program can distinguish be
tween different ²chip resets².

TO PDF RESET Conditions

-

-

0 0 RES

u u RES

0 1 RES

reset during power-up

reset during normal operation

wake-up HALT

1 u WDT time-out during normal operation

1 1 WDT wake-up HALT

Note: ²u² stands for ²unchanged²

To guarantee that the system oscillator has started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses during system
power up or when the system awakes from a HALT
state.

When a system power-up occurs, the SST delay is
added during the reset period. But when the reset co­mes from the RES

pin, the SST delay is disabled. Any

wake-up from HALT will enable the SST delay.

­The functional units chip reset status are shown below.

Program Counter 000H

-

Interrupt Disable

Prescaler Clear

-

WDT

Timer Counter (0/1) Off

-

Input/output ports Input mode

-

Clear. After master reset,
WDT begins counting

Stack Pointer Points to the top of stack

V D D

R E S

S S T T i m e - o u t

C h i p R e s e t

t

Reset Timing Chart

-

-

-

-

-

S S T

Rev. 1.00 11 August 15, 2005