HOLTEK HT36A2 User Manual

8-Bit Music Synthesizer MCU

Features

·
Operating voltage: 2.4V~5.0V
·
Operating frequency: 3.58MHz~12MHz (typ. 8MHz)
·
·
Two 8-bitprogrammable timer with 8 stage prescaler
·
Watchdog Timer
·
Built-in 8-bit MCU with 208´8 bits RAM
·
Built-in 64K´16-bit ROM for program/data shared
·
Mono output
·
High D/A converter resolution: 16 bits
·
Polyphonic up to 8 notes
·
Independent volume mix can be assigned to each sound component

General Description

The HT36A2 is an 8-bit high performance RISC-like microcontroller specifically designed for music applica tions. It provides an 8-bit MCU and a 8 channel wavetable synthesizer. The program ROM is composed of both program control codes and wavetable voice codes, and can be easily programmed.
HT36A2
·
Sampling rate of 25kHz as 6.4MHz for system frequency
·
Eight-level subroutine nesting
·
HALT function and wake-up feature to reduce power consumption
·
Bit manipulation instructions
·
16-bit table read instructions
·
63 powerful instructions
·
All instructions in 1 or 2 machine cycles
·
28-pin SOP, 48-pin SSOP package
The HT36A2 has a built-in 8-bit microprocessor which programs the synthesizer to generate the melody by
­setting the special register from 20H~2AH. A HALT fea ture is provided to reduce power consumption.
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Block Diagram

P A 0 ~ P A 7 P B 0 ~ P B 7
P C 0 ~ P C 3
O S C 1
O S C 2
R E S
8 - B i t M C U
6 4 K´1 6 - b i t
R O M
2 0 8´8
R A M
M u l t i p l i e r / P h a s e
G e n e r a l
1 6 - B i t
D A C
V D D
V S S V D D A V S S A
A U D
Rev. 1.00 1 June 19, 2003

Pin Assignment

A U D
T E S T
P A 4
P A 5
P A 6
P A 7
N C
N C
N C
N C
N C
N C
N C
N C
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
H T 3 6 A 2
2 8 S O P - A
HT36A2
P A 4
1
P A 5
2
P A 6
3
P A 7
4
N C
5
P B 0
6
P B 1
7
P B 2
8
P B 3
9
P B 4
1 0
2 8
P A 3
2 7
P A 2
2 6
P A 1
2 5
P A 0
2 4
N C
2 3
N C
2 2
O S C 2
2 1
N C
2 0
O S C 1
1 9
R E S
1 8
V S S
1 7
V S S A
1 6
V D D
1 5
V D D A
P B 5
1 1
P B 6
1 2
P B 7
1 3
N C
1 4
N C
1 5
N C
1 6
N C
1 7
N C
1 8
N C
1 9
N C
2 0
N C
2 1
N C
2 2
N C
2 3
N C
2 4
H T 3 6 A 2
4 8 S S O P - A
P A 3
4 8
P A 2
4 7
P A 1
4 6
P A 0
4 5
N C
4 4
N C
4 3
N C
4 2
N C
4 1
N C
4 0
N C
3 9
P C 0
3 8
P C 1
3 7
P C 2
3 6
P C 3
3 5
O S C 2
3 4
O S C 1
3 3
R E S
3 2
N C
3 1
V S S
3 0
V S S A
2 9
V D D
2 8
V D D A
2 7
T E S T
2 6
A U D
2 5

Pad Assignment

P B 0
P B 1 P B 2
P B 3 P B 4
P B 5 P B 6
P B 7
P A 4
P A 3
P A 7
P A 6
2 9
2 8
1
2
3
4
5
6
7
8
P A 2
P A 1
P A 5
2 6
2 7
2 5
P A 0
2 2
2 4
2 3
P C 0
2 1
P C 1
( 0 , 0 )
1 0
9
1 1
2 0
P C 2
1 9
P C 3
1 8
O S C 2
1 7
O S C 1
1 6
1 5
R E S
1 3 1 4
1 2
V D D A
T E S T
V D D
V S S A
A U D
V S S
Chip size: 87.2 ´ 118.3 (mil)
* The IC substrate should be connected to VSS in the PCB layout artwork.
Rev. 1.00 2 June 19, 2003
HT36A2

Pad Coordinates

Pad No. X Y Pad No. X Y
1
2
3
4
5
6
7
8
9 301.450
10 413.250
11 526.890
12 636.250
13 761.700
14 924.250
15 899.200
-939.550
-939.550
-939.550
-939.550
-939.550
-939.550
-939.550
-939.550
1222.175 16 899.200
1111.575 17 899.200
1011.575 18 938.800
900.975 19 938.800 9.925
800.975 20 938.800 109.925
690.375 21 938.800 220.525
590.375 22
479.775 23
-1303.400
-1303.400
-1303.400
-1303.400
-1296.750
-1296.750
-1078.450
24
25
26
27
28
29
-26.300
-136.900
-236.900
-347.500
-447.500
-558.100
-658.100
-768.700

Pad Description

Pad Name I/O
PB0~PB7 I/O
AUD O
TEST
VDDA
VDD
VSSA
VSS
RES
OSC1 OSC2
PC0~PC3 I/O
PA0~PA7 I/O
Internal
Connection
Pull-High
or None
¾
¾¾
¾¾
¾¾
¾¾
¾¾
I
I
O
¾
¾
Pull-High
or None
Pull-High
or None
Function
Bidirectional 8-bit Input/Output port
Audio output for driving a external transistor or for driving HT82V733
No connection (open)
DAC power supply
Positive power supply
Negative power supply of DAC, ground
Negative power supply, ground
Reset input, active low
OSC1 and OSC2 are connected to an RC network or a crystal (by mask option) for the internal system clock. In the case of RC operation, OSC2 is the output terminal for 1/8 system clock. The system clock may come from the crystal, the two pins cannot be floating.
Bidirectional 4-bit Input/Output port
Bidirectional 8-bit Input/Output port, wake-up by mask option
Unit: mm
-965.126
-287.274
-100.675
1336.775
1336.775
1336.775
1336.775
1336.775
1336.775
1336.775
1336.775

Absolute Maximum Ratings

Supply Voltage .............................VSS-0.3V to VSS+6V
Input Voltage .............................V
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil ity.
Rev. 1.00 3 June 19, 2003
3V to VDD+0.3V
SS-0.
Storage Temperature ...........................-50°Cto125°C
Operating Temperature ..........................-25°Cto70°C
-
HT36A2

D.C. Characteristics

Symbol Parameter
V
I
I
I
I
R
V
V
V
V
DD
DD
STB
OL
OH
PH
IH1
IL1
IH2
IL2
Operating Voltage
Operating Current 5V
Standby Current (WDT Disabled) 5V
I/O Ports Sink Current 5V
I/O Ports Source Current 5V
Pull-High Resistance of I/O Ports 5V
Input High Voltage for I/O Ports 5V
Input Low Voltage for I/O Ports 5V
Input High Voltage (RES)5V
Input Low Voltage (RES)5V

A.C. Characteristics

Symbol Parameter
MCU interface
f
OSC
f
SYS
t
WDT
t
RES
System Frequency 5V 8MHz crystal
System Clock 5V
Watchdog Time-Out Period (RC)
External Reset Low Pulse Width
Test Conditions
V
DD
Conditions
¾¾
No load, f
OSC
=8MHz
No load System HALT
=0.5V
V
OL
=4.5V
V
OH
=0V
V
IL
¾
¾
Min. Typ. Max. Unit
2.4 3 5 V
¾
¾
816mA
1
9.7 16.2
-5.2 -8.7 ¾
11 22 44
3.5
¾
0
¾
¾¾4¾
¾¾
Test Conditions
V
DD
Conditions
Min. Typ. Max. Unit
¾
¾
Without WDT prescaler 9 17 35 ms
¾
¾¾
2.5
8
4
¾
1
¾¾ms
Ta=25°C
¾mA
mA
¾
mA
kW
5V
1.5 V
V
¾
¾
V
MHz
8 MHz

Characteristics Curves

R vs F Characteristics Curve
1 4
1 2
1 0
8
F r e q u e n c y ( M H z )
6
4
2
1 2 0 1 5 0 1 8 0 2 0 0 2 2 0 2 4 0 2 7 0 3 0 0
Rev. 1.00 4 June 19, 2003
H T 3 6 A 2 R v s . F C h a r t
)
R ( k
W
3 . 0 V
4 . 5 V
V vs F Characteristics Curve
HT36A2
1 0
9
8
7
F r e q u e n c y ( M H z )
6
5
4
2 . 4 2 . 6 2 . 8 3 3 . 2 3 . 4 3 . 6 3 . 8 4 4 . 2 4 . 4 4 . 6 4 . 8 5
1 0
9
8
H T 3 6 A 2 V v s . F C h a r t ( F o r 3 . 0 V )
( V )
D D
V
H T 3 6 A 2 V v s . F C h a r t ( F o r 4 . 5 V )
1 5 5 k
2 0 0 k
1 4 5 k
/ 8 M H z
W
/ 6 M H z
W
/ 8 M H z
W
7
F r e q u e n c y ( M H z )
6
5
4
2 . 4 2 . 6 2 . 8 3 3 . 2 3 . 4 3 . 6 3 . 8 4 4 . 2 4 . 4 4 . 6 4 . 8 5
V
( V )
D D
1 9 0 k
/ 6 M H z
W
Rev. 1.00 5 June 19, 2003

Function Description

Execution Flow
The system clock for the HT36A2 is derived from either a crystal or an RC oscillator. The oscillator frequency di vided by 2 is the system clock for the MCU and it is inter nally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles.
Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while de coding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruc tion to effectively execute in one cycle. If an instruction changes the program counter, two cycles are required to complete the instruction.
Program Counter - PC
The 13-bit program counter (PC) controls the sequence in which the instructions stored in program ROM are ex ecuted and its contents specify a maximum of 8192 ad dresses for each bank.
After accessing a program memory word to fetch an in struction code, the contents of the program counter are incremented by one. The program counter then points to the memory word containing the next instruction code.
When executing a jump instruction, conditional skip ex ecution, loading PCL register, subroutine call, initial re set, internal interrupt, external interrupt or return from
-
subroutine, the PC manipulates the program transfer by
-
loading the address corresponding to each instruction.
The conditional skip is activated by instruction. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy
-
cycle replaces it to retrieve the proper instruction. Other wise proceed with the next instruction.
-
The lower byte of the program counter (PCL) is a read able and writeable register (06H). Moving data into the PCL performs a short jump. The destination will be within 256 locations.
Once a control transfer takes place, an additional dummy cycle is required.
-
-
Program ROM
HT36A2 provides 16 address lines WA[15:0] to read the
-
Program ROM which is up to 1M bits, and is commonly used for the wavetable voice codes and the program memory. It provides two address types, one type is for program ROM, which is addressed by a bank pointer PF2~0 and a 13-bit program counter PC 12~0; and the
HT36A2
-
-
-
-
S y s t e m C l o c k o f M C U
( S y s t e m C l o c k / 2 )
T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4
P C
P C P C + 1 P C + 2
F e t c h I N S T ( P C )
E x e c u t e I N S T ( P C - 1 )
F e t c h I N S T ( P C + 1 )
E x e c u t e I N S T ( P C )
F e t c h I N S T ( P C + 2 )
E x e c u t e I N S T ( P C + 1 )
Execution flow
Mode
*12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0
Program Counter
Initial Reset 0 0 0 0000000000
Timer/Event Counter 0 Overflow 0 0 0 0000001000
Timer/Event Counter 1 Overflow 0 0 0 0000001100
Skip PC+2
Loading PCL *12 *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0
Jump, Call Branch #12 #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0
Return From Subroutine S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
Program counter
Note: *12~*0: Bits of Program Counter
@7~@0: Bits of PCL
S12~S0: Bits of Stack Register
@7~@0: Bits of PCL
#12~#0: Bits of Instruction Code
Rev. 1.00 6 June 19, 2003
HT36A2
other type is for wavetable code, which is addressed by the start address ST11~0. On the program type,
13
WA15~0= PF2~0 ´ 2
ROM type, WA15~0=ST11~0 ´ 2
+ PC12~0. On the wave table
5
.
Program Memory - ROM
The program memory is used to store the program in structions which are to be executed. It also contains data, table, and interrupt entries, and is organized into
8192´16 bits, addressed by the bank pointer, program counter and table pointer.
Certain locations in the program memory of each bank are reserved for special usage:
·
Location 000H on bank0 This area is reserved for the initialization program. Af ter chip reset, the program always begins execution at location 000H on bank0.
·
Location 008H This area is reserved for the Timer Counter 0 interrupt service program on each bank. If timer interrupt results from a timer counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program begins ex ecution at location 008H corresponding to its bank.
·
Location 00CH This area is reserved for the Timer Counter 1 interrupt service program on each bank. If a timer interrupt re­sults from a Timer Counter 1 overflow, and if the inter­rupt is enabled and the stack is not full, the program begins execution at location 00CH corresponding to its bank.
·
Table location Any location in the ROM space can be used as look-up tables. The instructions TABRDC [m] (the cur­rent page, 1 page=256 words) and TABRDL [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the table is well-defined, the higher-order byte of the table word are transferred to the TBLH. The Table Higher-order byte register (TBLH) is read only. The Table Pointer (TBLP) is a read/write register (07H), which indicates the table lo cation. Before accessing the table, the location must be placed in TBLP. The TBLH is read only and cannot be restored. If the main routine and the ISR (Interrupt
0 0 0 0 H
0 0 0 8 H
0 0 0 C H
-
n 0 0 H
n F F H
1 F F F H
-
D e v i c e i n i t i a l i z a t i o n p r o g r a m
T i m e r C o u n t e r 0 i n t e r r u p t s u b r o u t i n e
T i m e r C o u n t e r 1 i n t e r r u p t s u b r o u t i n e
L o o k - u p t a b l e ( 2 5 6 w o r d s )
L o o k - u p t a b l e ( 2 5 6 w o r d s )
1 6 b i t s
N o t e : n r a n g e s f r o m 0 0 t o 1 F .
Program memory for each bank
Service Routine) both employ the table read instruc tion, the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR. Errors can occur. In this case, using the ta ble read instruction in the main routine and the ISR si
-
multaneously should be avoided. However, if the table read instruction has to be applied in both the main routine and the ISR, the interrupt should be dis abled prior to the table read instruction. It will not be enabled until the TBLH has been backed up. All table related instructions need 2 cycles to complete the op­eration. These areas may function as normal program memory depending upon user requirements.
·
Bank pointer The program memory is organized into 8 banks and
each bank into 8192 ´ 16 bits of program ROM. PF[2~0] is used as the bank pointer. After an instruc­tion has been executed to write data to the PF register to select a different bank, note that the new bank will not be selected immediately. It is not until the following instruction has completed execution that the bank will be actually selected. It should be note that the PF reg ister hasto becleared before setting to output mode.
Wavetable ROM
The ST[11~0] is used to defined the start address of
-
each sample on the wavetable and read the waveform data from the location. HT36A2 provides 16 output ad dress lines from WA[15~0], the ST[11~0] is used to lo
P r o g r a m R O M
-
-
-
-
-
-
-
Instruction(s)
*12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0
Table Location
TABRDC [m] P12 P11 P10 P9 P8 @7 @6 @5 @4 @3 @2 @1 @0
TABRDL [m] 11111@7@6@5@4@3@2@1@0
Table location
Note: *12~*0: Bits of table location
P12~P8: Bits of current Program Counter
@7~@0: Bits of table pointer
Rev. 1.00 7 June 19, 2003
HT36A2
cate the major 16 bits i.e. WA[15:5] and the undefined data from WA[4~0] is always set to 00000b. So the start address of each sample have to be located at a multiple of 32. Otherwise, the sample will not be read out cor rectly because it has a wrong starting code.
Stack Register - Stack
This is a special part of the memory which is used to save the contents of the program counter (PC) only. The stack is organized into 8 levels and is neither part of the data nor part of the program space, and is neither read able nor writeable. The activated level is indexed by the stack pointer (SP) and is neither readable nor writeable. At a subroutine call or interrupt acknowledgment, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the pro gram counter is restored to its previous value from the stack. Aftera chip reset, the SP will point tothe top of the stack.
If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledgment will be inhibited. When the stack pointer is decremented (by RET or RETI), the interrupt will be serviced. This feature prevents stack overflow al lowing the programmer to use the structure more easily. In a similar case, if the stack is full and a CALL is subse­quently executed, a stack overflow occurs and the first entry will be lost (only the most recent eight return ad­dress are stored).
Data Memory - RAM
The datamemory is designed with 256 ´ 8 bits. The data memory is divided into three functional groups: special function registers, wavetable function register, and gen
eral purpose data memory (208´8). Most of them are read/write, but some are read only.
The special function registers include the Indirect Ad dressing register 0 (00H), the Memory Pointer register 0 (MP0;01H), the Indirect Addressing register 1 (02H), the Memory Pointer register 1 (MP1;03H), the Accumulator (ACC;05H), the Program Counter Lower-byte register (PCL;06H), the Table Pointer (TBLP;07H), the Table Higher-order byte register (TBLH;08H), the Watchdog Timer option Setting register (WDTS;09H), the Status register (STATUS;0AH), the Interrupt Control register (INTC;0BH), the Timer Counter 0 Lower-order byte reg ister (TMR0L;0DH), the Timer Counter 0 Control regis ter (TMR0C;0EH), the Timer Counter 1 Lower-order byte register (TMR1L;10H), the Timer Counter 1 Control register (TMR1C;11H), the I/O registers (PA;12H, PB;14H, PC;16H) and the I/O control registers (PAC;13H, PBC;15H, PCC;17H). The program ROM bank select (PF;1CH). The DAC High byte (DAH;1DH). The DAC low byte (DAL;1EH). The DAC control (DAC;1FH). The wavetable function registers is defined
between 20H~2AH. The remaining space before the 30H is reserved for future expanded usage and reading these locations will return the result 00H. The general purpose data memory, addressed from 30H to FFH, is
-
used for data and control information under instruction command.
I n d i r e c t A d d r e s s i n g R e g i s t e r 0
0 0 H
0 1 H
0 2 H
I n d i r e c t A d d r e s s i n g R e g i s t e r 1
0 3 H
-
0 4 H
0 5 H
0 6 H
0 7 H
0 8 H
0 9 H
0 A H
-
0 B H
0 C H
0 D H
0 E H
0 F H
1 0 H
1 1 H
1 2 H
1 3 H
-
1 4 H
1 5 H
1 6 H
1 7 H 1 8 H
1 9 H
1 A H
1 B H
1 C H
1 D H 1 E H
-
1 F H
2 0 H
2 1 H
F r e q u e n c y n u m b e r h i g h b y t e
2 2 H
-
F r e q u e n c y n u m b e r l o w b y t e
2 3 H
2 4 H
2 5 H
2 6 H
2 7 H
2 8 H
2 9 H
2 A H 2 B H
R e p e a t n u m b e r h i g h b y t e
M P 0
M P 1
A C C
P C L
T B L P
T B L H
W D T S
S T A T U S
I N T C
T M R 0 L
T M R 0 C
T M R 1 L T M R 1 C
P A
P A C
P B
P B C
P C
P C C
P F
D A C h i g h b y t e
D A C l o w b y t e
D A C c o n t r o l
C h a n n e l n u m b e r s e l e c t
S t a r t a d d r e s s h i g h b y t e
S t a r t a d d r e s s l o w b y t e
R e p e a t n u m b e r l o w b y t e
V o l u m e c o n t r o l h i g h
V o l u m c o n t r o l l o w
S p e c i a l P u r p o s e D A T A M E M O R Y
W a v e t a b l e F u n c t i o n R e g i s t e r
-
-
2 F H 3 0 H
G e n e r a l P u r p o s e D A T A M E M O R Y
( 2 0 8 B y t e s )
F F H
: U n u s e d . R e a d a s " 0 0 "
RAM mapping
Rev. 1.00 8 June 19, 2003
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