Holtek HT32F52342, HT32F52352 User Manual

Holtek 32-Bit Microcontroller with Arm® Cortex®-M0+ Core

HT32F52342/HT32F52352

User Manual

Revision: V1.30 Date: September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Table of Contents

1 Introduction ........................................................................................................... 26

Overview .............................................................................................................................. 26

Features ............................................................................................................................... 27

Device Information ............................................................................................................... 32

Block Diagram ..................................................................................................................... 33

2 Document Conventions ....................................................................................... 34

3 System Architecture ............................................................................................. 35

Arm® Cortex®-M0+ Processor .............................................................................................. 35

Bus Architecture ................................................................................................................... 36

Memory Organization .......................................................................................................... 37

Memory Map ................................................................................................................................... 38

Embedded Flash Memory ............................................................................................................... 41

Embedded SRAM Memory ............................................................................................................. 41

AHB Peripherals ............................................................................................................................. 41

APB Peripherals ............................................................................................................................. 41

Table of Contents

4 Flash Memory Controller (FMC) .......................................................................... 42

Introduction .......................................................................................................................... 42

Features ............................................................................................................................... 42

Functional Descriptions ....................................................................................................... 43

Flash Memory Map ......................................................................................................................... 43

Flash Memory Architecture ............................................................................................................. 44

Wait State Setting ........................................................................................................................... 44

Booting Conguration ..................................................................................................................... 45

Page Erase ..................................................................................................................................... 46

Mass Erase ..................................................................................................................................... 47

Word Programming ......................................................................................................................... 48

Option Byte Description .................................................................................................................. 49

Page Erase/Program Protection ..................................................................................................... 49

Security Protection .......................................................................................................................... 51

Register Map ....................................................................................................................... 52

Register Descriptions ........................................................................................................... 53

Flash Target Address Register – TADR .......................................................................................... 53

Flash Write Data Register – WRDR ............................................................................................... 54

Flash Operation Command Register – OCMR ............................................................................... 55

Flash Operation Control Register – OPCR ..................................................................................... 56

Flash Operation Interrupt Enable Register – OIER ........................................................................ 57

Flash Operation Interrupt and Status Register – OISR .................................................................. 58

Flash Page Erase/Program Protection Status Register – PPSR .................................................... 60

Flash Security Protection Status Register – CPSR ........................................................................ 61

Rev. 1.30 2 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Flash Vector Mapping Control Register – VMCR ........................................................................... 62

Flash Manufacturer and Device ID Register – MDID ...................................................................... 63

Flash Page Number Status Register – PNSR ................................................................................ 64

Flash Page Size Status Register – PSSR ...................................................................................... 65

Flash Cache & Pre-fetch Control Register – CFCR ........................................................................ 66

Custom ID Register n – CIDRn, n = 0 ~ 3 ...................................................................................... 67

5 Power Control Unit (PWRCU) .............................................................................. 68

Introduction .......................................................................................................................... 68

Features ............................................................................................................................... 69

Functional Descriptions ....................................................................................................... 69

Backup Domain .............................................................................................................................. 69

VDD Power Domain .......................................................................................................................... 70

1.5 V Power Domain ....................................................................................................................... 72

Operation Modes ............................................................................................................................ 72

Register Map ....................................................................................................................... 74

Register Descriptions ........................................................................................................... 75

Backup Domain Status Register – BAKSR ..................................................................................... 75

Backup Domain Control Register – BAKCR ................................................................................... 76

Backup Domain Test Register – BAKTEST .................................................................................... 78

Low Voltage / Brown Out Detect Control and Status Register – LVDCSR ..................................... 79

Backup Register n – BAKREGn, n = 0 ~ 9 ..................................................................................... 81

Table of Contents

6 Clock Control Unit (CKCU) .................................................................................. 82

Introduction .......................................................................................................................... 82

Features ............................................................................................................................... 84

Function Descriptions .......................................................................................................... 84

High Speed External Crystal Oscillator – HSE ............................................................................... 84

High Speed Internal RC Oscillator – HSI ........................................................................................ 85

Auto Trimming of High Speed Internal RC Oscillator – HSI ............................................................ 85

Phase Locked Loop – PLL .............................................................................................................. 87

Low Speed External Crystal Oscillator – LSE ................................................................................. 89

Low Speed Internal RC Oscillator – LSI ......................................................................................... 89

Clock Ready Flag ........................................................................................................................... 89

System Clock (CK_SYS) Selection ................................................................................................ 90

HSE Clock Monitor ......................................................................................................................... 91

Clock Output Capability .................................................................................................................. 91

Register Map ....................................................................................................................... 92

Register Descriptions ........................................................................................................... 93

Global Clock Conguration Register – GCFGR .............................................................................. 93

Global Clock Control Register – GCCR .......................................................................................... 95

Global Clock Status Register – GCSR ........................................................................................... 97

Global Clock Interrupt Register – GCIR .......................................................................................... 98

PLL Conguration Register – PLLCFGR ........................................................................................ 99

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32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

PLL Control Register – PLLCR ....................................................................................................... 99

AHB Conguration Register – AHBCFGR .................................................................................... 100

AHB Clock Control Register – AHBCCR ...................................................................................... 101

APB Conguration Register – APBCFGR ..................................................................................... 103

APB Clock Control Register 0 – APBCCR0 .................................................................................. 104

APB Clock Control Register 1 – APBCCR1 .................................................................................. 106

Clock Source Status Register – CKST ......................................................................................... 108

APB Peripheral Clock Selection Register 0 – APBPCSR0 ........................................................... 109

APB Peripheral Clock Selection Register 1 – APBPCSR1 ............................................................111

HSI Control Register – HSICR .......................................................................................................113

HSI Auto Trimming Counter Register – HSIATCR .........................................................................114

Low Power Control Register – LPCR ............................................................................................115

MCU Debug Control Register – MCUDBGCR ...............................................................................116

7 Reset Control Unit (RSTCU) .............................................................................. 119

Introduction ........................................................................................................................ 119

Functional Descriptions ..................................................................................................... 120

Power On Reset ........................................................................................................................... 120

System Reset ............................................................................................................................... 120

AHB and APB Unit Reset .............................................................................................................. 120

Register Map ..................................................................................................................... 121

Register Descriptions ......................................................................................................... 121

Global Reset Status Register – GRSR ......................................................................................... 121

AHB Peripheral Reset Register – AHBPRSTR ............................................................................. 122

APB Peripheral Reset Register 0 – APBPRSTR0 ........................................................................ 123

APB Peripheral Reset Register 1 – APBPRSTR1 ........................................................................ 125

Table of Contents

8 General Purpose I/O (GPIO) ............................................................................... 127

Introduction ........................................................................................................................ 127

Features ............................................................................................................................. 128

Functional Descriptions ..................................................................................................... 128

Default GPIO Pin Conguration .................................................................................................... 128

General Purpose I/O – GPIO ........................................................................................................ 128

GPIO Locking Mechanism ............................................................................................................ 130

Register Map ..................................................................................................................... 130

Register Descriptions ......................................................................................................... 131

Port A Data Direction Control Register – PADIRCR ..................................................................... 131

Port A Input Function Enable Control Register – PAINER ............................................................ 132

Port A Pull-Up Selection Register – PAPUR ................................................................................. 133

Port A Pull-Down Selection Register – PAPDR ............................................................................ 134

Port A Open Drain Selection Register – PAODR .......................................................................... 135

Port A Output Current Drive Selection Register – PADRVR ......................................................... 136

Port A Lock Register – PALOCKR ................................................................................................ 137

Port A Data Input Register – PADINR ........................................................................................... 138

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32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Port A Output Data Register – PADOUTR .................................................................................... 139

Port A Output Set/Reset Control Register – PASRR .................................................................... 140

Port A Output Reset Register – PARR .......................................................................................... 141

Port B Data Direction Control Register – PBDIRCR ..................................................................... 142

Port B Input Function Enable Control Register – PBINER ........................................................... 143

Port B Pull-Up Selection Register – PBPUR ................................................................................ 144

Port B Pull-Down Selection Register – PBPDR ............................................................................ 145

Port B Open Drain Selection Register – PBODR ......................................................................... 146

Port B Output Current Drive Selection Register – PBDRVR ........................................................ 147

Port B Lock Register – PBLOCKR ................................................................................................ 148

Port B Data Input Register – PBDINR .......................................................................................... 149

Port B Output Data Register – PBDOUTR ................................................................................... 150

Port B Output Set/Reset Control Register – PBSRR .................................................................... 151

Port B Output Reset Register – PBRR ......................................................................................... 152

Port C Data Direction Control Register – PCDIRCR .................................................................... 153

Port C Input Function Enable Control Register – PCINER ........................................................... 154

Port C Pull-Up Selection Register – PCPUR ................................................................................ 155

Port C Pull-Down Selection Register – PCPDR ........................................................................... 156

Port C Open Drain Selection Register – PCODR ......................................................................... 157

Port C Output Current Drive Selection Register – PCDRVR ........................................................ 158

Port C Lock Register – PCLOCKR ............................................................................................... 159

Port C Data Input Register – PCDINR .......................................................................................... 160

Port C Output Data Register – PCDOUTR ................................................................................... 161

Port C Output Set/Reset Control Register – PCSRR ................................................................... 162

Port C Output Reset Register – PCRR ......................................................................................... 163

Port D Data Direction Control Register – PDDIRCR .................................................................... 164

Port D Input Function Enable Control Register – PDINER ........................................................... 165

Port D Pull-Up Selection Register – PDPUR ................................................................................ 166

Port D Pull-Down Selection Register – PDPDR ........................................................................... 167

Port D Open Drain Selection Register – PDODR ......................................................................... 168

Port D Output Current Drive Selection Register – PDDRVR ........................................................ 169

Port D Lock Register – PDLOCKR ............................................................................................... 170

Port D Data Input Register – PDDINR .......................................................................................... 171

Port D Output Data Register – PDDOUTR ................................................................................... 172

Port D Output Set/Reset Control Register – PDSRR ................................................................... 173

Port D Output Reset Register – PDRR ......................................................................................... 174

Table of Contents

9 Alternate Function Input/Output Control Unit (AFIO) ...................................... 175

Introduction ........................................................................................................................ 175

Features ............................................................................................................................. 176

Functional Descriptions ..................................................................................................... 176

External Interrupt Pin Selection .................................................................................................... 176

Alternate Function ......................................................................................................................... 177

Lock Mechanism .......................................................................................................................... 177

Register Map ..................................................................................................................... 177

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32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Register Descriptions ......................................................................................................... 178

EXTI Source Selection Register 0 – ESSR0 ................................................................................ 178

EXTI Source Selection Register 1 – ESSR1 ................................................................................ 179

GPIO x Conguration Low Register – GPxCFGLR, x = A, B, C, D ............................................... 180

GPIO x Conguration High Register – GPxCFGHR, x = A, B, C, D ............................................. 181

10 Nested Vectored Interrupt Controller (NVIC) .................................................. 182

Introduction ........................................................................................................................ 182

Features ............................................................................................................................. 183

Function Descriptions ........................................................................................................ 184

SysTick Calibration ....................................................................................................................... 184

Register Map ..................................................................................................................... 184

11 External Interrupt/Event Controller (EXTI) ...................................................... 185

Introduction ........................................................................................................................ 185

Features ............................................................................................................................. 185

Function Descriptions ........................................................................................................ 186

Wakeup Event Management......................................................................................................... 186

External Interrupt/Event Line Mapping ......................................................................................... 187

Interrupt and Debounce ................................................................................................................ 187

Register Map ..................................................................................................................... 188

Register Descriptions ......................................................................................................... 189

EXTI Interrupt Conguration Register n – EXTICFGRn, n = 0 ~ 15 ............................................. 189

EXTI Interrupt Control Register – EXTICR ................................................................................... 190

EXTI Interrupt Edge Flag Register – EXTIEDGEFLGR ................................................................ 191

EXTI Interrupt Edge Status Register – EXTIEDGESR ................................................................. 192

EXTI Interrupt Software Set Command Register – EXTISSCR .................................................... 193

EXTI Interrupt Wakeup Control Register – EXTIWAKUPCR ........................................................ 194

EXTI Interrupt Wakeup Polarity Register – EXTIWAKUPPOLR ................................................... 195

EXTI Interrupt Wakeup Flag Register – EXTIWAKUPFLG ........................................................... 196

Table of Contents

12 Analog to Digital Converter (ADC) .................................................................. 197

Introduction ........................................................................................................................ 197

Features ............................................................................................................................. 198

Function Descriptions ........................................................................................................ 199

ADC Clock Setup .......................................................................................................................... 199

Channel Selection ......................................................................................................................... 199

Conversion Mode .......................................................................................................................... 199

Start Conversion on External Event .............................................................................................. 202

Sampling Time Setting .................................................................................................................. 203

Data Format .................................................................................................................................. 203

Analog Watchdog.......................................................................................................................... 203

Interrupts ....................................................................................................................................... 204

PDMA Request ............................................................................................................................ 204

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32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Register Map ..................................................................................................................... 205

Register Descriptions ......................................................................................................... 206

ADC Conversion Control Register – ADCCR ............................................................................... 206

ADC Conversion List Register 0 – ADCLST0 ............................................................................... 208

ADC Conversion List Register 1 – ADCLST1 ............................................................................... 209

ADC Input Sampling Time Register – ADCSTR ........................................................................... 210

ADC Conversion Data Register y – ADCDRy, y = 0 ~ 7 ................................................................211

ADC Trigger Control Register – ADCTCR .................................................................................... 212

ADC Trigger Source Register – ADCTSR ..................................................................................... 213

ADC Watchdog Control Register – ADCWCR .............................................................................. 214

ADC Watchdog Threshold Register – ADCTR .............................................................................. 215

ADC Interrupt Enable Register – ADCIER .................................................................................... 216

ADC Interrupt Raw Status Register – ADCIRAW ......................................................................... 217

ADC Interrupt Status Register – ADCISR ..................................................................................... 218

ADC Interrupt Clear Register – ADCICLR .................................................................................... 219

ADC DMA Request Register – ADCDMAR ................................................................................... 220

Table of Contents

13 Comparator (CMP) ............................................................................................ 221

Introduction ........................................................................................................................ 221

Features ............................................................................................................................. 221

Function Descriptions ........................................................................................................ 222

Comparator Inputs and Output ..................................................................................................... 222

Comparator Voltage Reference .................................................................................................... 222

Interrupts and Wakeup.................................................................................................................. 223

Power Mode and Hysteresis ......................................................................................................... 224

Comparator Write-Protected mechanism ..................................................................................... 224

Register Map ..................................................................................................................... 224

Register Descriptions ......................................................................................................... 225

Comparator Control Register n – CMPCRn, n = 0 or 1 ................................................................ 225

Comparator Voltage Reference Value Register n – CVRVALRn, n = 0 or 1 ................................. 227

Comparator Interrupt Enable Register n – CMPIERn, n = 0 or 1 ................................................. 228

Comparator Transition Flag Register n – CMPTFRn, n = 0 or 1 .................................................. 229

14 General-Purpose Timer (GPTM) ...................................................................... 230

Introduction ........................................................................................................................ 230

Features ............................................................................................................................. 231

Functional Descriptions ..................................................................................................... 232

Counter Mode ............................................................................................................................... 232

Clock Controller ............................................................................................................................ 235

Trigger Controller .......................................................................................................................... 236

Slave Controller ............................................................................................................................ 237

Master Controller .......................................................................................................................... 240

Channel Controller ........................................................................................................................ 241

Input Stage ................................................................................................................................... 244

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32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Quadrature Decoder ..................................................................................................................... 246

Output Stage ................................................................................................................................. 248

Update Management .................................................................................................................... 252

Single Pulse Mode ........................................................................................................................ 253

Asymmetric PWM Mode ............................................................................................................... 255

Timer Interconnection ................................................................................................................... 256

Trigger ADC Start.......................................................................................................................... 259

PDMA Request ............................................................................................................................. 259

Register Map ..................................................................................................................... 260

Register Descriptions ......................................................................................................... 261

Timer Counter Conguration Register – CNTCFR ....................................................................... 261

Timer Mode Conguration Register – MDCFR ............................................................................. 263

Timer Trigger Conguration Register – TRCFR ............................................................................ 266

Timer Counter Register – CTR ..................................................................................................... 267

Channel 0 Input Conguration Register – CH0ICFR .................................................................... 268

Channel 1 Input Conguration Register – CH1ICFR .................................................................... 270

Channel 2 Input Conguration Register – CH2ICFR .................................................................... 272

Channel 3 Input Conguration Register – CH3ICFR .................................................................... 274

Channel 0 Output Conguration Register – CH0OCFR ............................................................... 276

Channel 1 Output Conguration Register – CH1OCFR ............................................................... 278

Channel 2 Output Conguration Register – CH2OCFR ............................................................... 280

Channel 3 Output Conguration Register – CH3OCFR ............................................................... 282

Channel Control Register – CHCTR ............................................................................................. 284

Channel Polarity Conguration Register – CHPOLR .................................................................... 285

Timer PDMA/Interrupt Control Register – DICTR ......................................................................... 286

Timer Event Generator Register – EVGR ..................................................................................... 288

Timer Interrupt Status Register – INTSR ...................................................................................... 290

Timer Counter Register – CNTR................................................................................................... 293

Timer Prescaler Register – PSCR ................................................................................................ 294

Timer Counter Reload Register – CRR ........................................................................................ 295

Channel 0 Capture/Compare Register – CH0CCR ...................................................................... 296

Channel 1 Capture/Compare Register – CH1CCR ...................................................................... 297

Channel 2 Capture/Compare Register – CH2CCR ...................................................................... 298

Channel 3 Capture/Compare Register – CH3CCR ...................................................................... 299

Channel 0 Asymmetric Compare Register – CH0ACR ................................................................. 300

Channel 1 Asymmetric Compare Register – CH1ACR ................................................................. 301

Channel 2 Asymmetric Compare Register – CH2ACR ................................................................. 302

Channel 3 Asymmetric Compare Register – CH3ACR ................................................................. 303

Table of Contents

15 Basic Function Timer (BFTM) .......................................................................... 304

Introduction ........................................................................................................................ 304

Features ............................................................................................................................. 304

Functional Description ....................................................................................................... 305

Repetitive Mode ............................................................................................................................ 305

One Shot Mode ............................................................................................................................. 306

Rev. 1.30 8 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Register Map ..................................................................................................................... 307

Register Descriptions ......................................................................................................... 307

BFTM Control Register – BFTMCR .............................................................................................. 307

BFTM Status Register – BFTMSR ................................................................................................ 308

BFTM Counter Register – BFTMCNTR ........................................................................................ 309

BFTM Compare Value Register – BFTMCMPR ........................................................................... 310

16 Motor Control Timer (MCTM) ........................................................................... 311

Introduction ........................................................................................................................ 311

Features ............................................................................................................................. 312

Functional Descriptions ..................................................................................................... 313

Counter Mode ............................................................................................................................... 313

Clock Controller ............................................................................................................................ 317

Trigger Controller .......................................................................................................................... 318

Slave Controller ............................................................................................................................ 319

Master Controller .......................................................................................................................... 321

Channel Controller ........................................................................................................................ 322

Input Stage ................................................................................................................................... 325

Output Stage ................................................................................................................................. 327

Update Management .................................................................................................................... 337

Single Pulse Mode ........................................................................................................................ 339

Asymmetric PWM Mode ............................................................................................................... 341

Timer Interconnection ................................................................................................................... 342

Trigger ADC Start.......................................................................................................................... 346

Lock Level Table ........................................................................................................................... 346

PDMA Request ............................................................................................................................. 347

Register Map ..................................................................................................................... 348

Register Descriptions ......................................................................................................... 349

Timer Counter Conguration Register – CNTCFR ....................................................................... 349

Timer Mode Conguration Register – MDCFR ............................................................................. 351

Timer Trigger Conguration Register – TRCFR ............................................................................ 354

Timer Counter Register – CTR ..................................................................................................... 355

Channel 0 Input Conguration Register – CH0ICFR .................................................................... 356

Channel 1 Input Conguration Register – CH1ICFR .................................................................... 358

Channel 2 Input Conguration Register – CH2ICFR .................................................................... 360

Channel 3 Input Conguration Register – CH3ICFR .................................................................... 362

Channel 0 Output Conguration Register – CH0OCFR ............................................................... 364

Channel 1 Output Conguration Register – CH1OCFR ............................................................... 366

Channel 2 Output Conguration Register – CH2OCFR ............................................................... 368

Channel 3 Output Conguration Register – CH3OCFR ............................................................... 370

Channel Control Register – CHCTR ............................................................................................. 372

Channel Polarity Conguration Register – CHPOLR .................................................................... 374

Channel Break Conguration Register – CHBRKCFR ................................................................. 376

Channel Break Control Register – CHBRKCTR ........................................................................... 377

Table of Contents

Rev. 1.30 9 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Timer PDMA/Interrupt Control Register – DICTR ......................................................................... 379

Timer Event Generator Register – EVGR ..................................................................................... 381

Timer Interrupt Status Register – INTSR ...................................................................................... 383

Timer Counter Register – CNTR................................................................................................... 386

Timer Prescaler Register – PSCR ................................................................................................ 387

Timer Counter Reload Register – CRR ........................................................................................ 388

Timer Repetition Register – REPR ............................................................................................... 389

Channel 0 Capture/Compare Register – CH0CCR ...................................................................... 390

Channel 1 Capture/Compare Register – CH1CCR ...................................................................... 391

Channel 2 Capture/Compare Register – CH2CCR ...................................................................... 392

Channel 3 Capture/Compare Register – CH3CCR ...................................................................... 393

Channel 0 Asymmetric Compare Register – CH0ACR ................................................................. 394

Channel 1 Asymmetric Compare Register – CH1ACR ................................................................. 395

Channel 2 Asymmetric Compare Register – CH2ACR ................................................................. 396

Channel 3 Asymmetric Compare Register – CH3ACR ................................................................. 397

Table of Contents

17 Single-Channel Timer (SCTM) ......................................................................... 398

Introduction ........................................................................................................................ 398

Features ............................................................................................................................. 399

Functional Descriptions ..................................................................................................... 399

Counter Mode ............................................................................................................................... 399

Clock Controller ............................................................................................................................ 400

Trigger Controller .......................................................................................................................... 401

Slave Controller ............................................................................................................................ 402

Channel Controller ........................................................................................................................ 404

Input Stage ................................................................................................................................... 406

Output Stage ................................................................................................................................. 407

Update Management .................................................................................................................... 409

Register Map ..................................................................................................................... 410

Register Descriptions ......................................................................................................... 411

Timer Counter Conguration Register – CNTCFR ........................................................................411

Timer Mode Conguration Register – MDCFR ............................................................................. 412

Timer Trigger Conguration Register – TRCFR ............................................................................ 413

Timer Counter Register – CTR ..................................................................................................... 414

Channel Input Conguration Register – CHICFR ......................................................................... 415

Channel Output Conguration Register – CHOCFR .................................................................... 417

Channel Control Register – CHCTR ............................................................................................. 418

Channel Polarity Conguration Register – CHPOLR .................................................................... 419

Timer Interrupt Control Register – DICTR .................................................................................... 420

Timer Event Generator Register – EVGR ..................................................................................... 421

Timer Interrupt Status Register – INTSR ...................................................................................... 422

Timer Counter Register – CNTR................................................................................................... 423

Timer Prescaler Register – PSCR ................................................................................................ 424

Timer Counter Reload Register – CRR ........................................................................................ 425

Channel Capture/Compare Register – CHCCR ........................................................................... 426

Rev. 1.30 10 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

18 Real Time Clock (RTC) ..................................................................................... 427

Introduction ........................................................................................................................ 427

Features ............................................................................................................................. 427

Functional Descriptions ..................................................................................................... 428

RTC Related Register Reset ........................................................................................................ 428

Reading RTC Register .................................................................................................................. 428

Low Speed Clock Conguration ................................................................................................... 428

RTC Counter Operation ................................................................................................................ 429

Interrupt and Wakeup Control ....................................................................................................... 429

RTCOUT Output Pin Conguration............................................................................................... 430

Register Map ..................................................................................................................... 431

Register Descriptions ......................................................................................................... 431

RTC Counter Register – RTCCNT ................................................................................................ 431

RTC Compare Register – RTCCMP ............................................................................................. 432

RTC Control Register – RTCCR ................................................................................................... 433

RTC Status Register – RTCSR..................................................................................................... 435

RTC Interrupt and Wakeup Enable Register – RTCIWEN ............................................................ 436

Table of Contents

19 Watchdog Timer (WDT) .................................................................................... 437

Introduction ........................................................................................................................ 437

Features ............................................................................................................................. 437

Functional Description ....................................................................................................... 438

Register Map ..................................................................................................................... 440

Register Descriptions ......................................................................................................... 440

Watchdog Timer Control Register – WDTCR ............................................................................... 440

Watchdog Timer Mode Register 0 – WDTMR0............................................................................. 441

Watchdog Timer Mode Register 1 – WDTMR1............................................................................. 442

Watchdog Timer Status Register – WDTSR ................................................................................. 443

Watchdog Timer Protection Register – WDTPR ........................................................................... 444

Watchdog Timer Clock Selection Register – WDTCSR ................................................................ 445

20 Inter-Integrated Circuit (I2C) ............................................................................. 446

Introduction ........................................................................................................................ 446

Features ............................................................................................................................. 447

Functional Descriptions ..................................................................................................... 447

Two Wire Serial Interface .............................................................................................................. 447

START and STOP Conditions ....................................................................................................... 447

Data Validity .................................................................................................................................. 448

Addressing Format ....................................................................................................................... 449

Data Transfer and Acknowledge ................................................................................................... 451

Clock Synchronization .................................................................................................................. 452

Arbitration ..................................................................................................................................... 452

General Call Addressing ............................................................................................................... 453

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32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Bus Error ....................................................................................................................................... 453

Address Mask Enable ................................................................................................................... 453

Address Snoop ............................................................................................................................. 453

Operation Mode ............................................................................................................................ 453

Conditions of Holding SCL Line .................................................................................................... 459

I2C Timeout Function .................................................................................................................... 460

PDMA Interface ............................................................................................................................. 460

Register Map ..................................................................................................................... 461

Register Descriptions ......................................................................................................... 462

I2C Control Register – I2CCR ....................................................................................................... 462

I2C Interrupt Enable Register – I2CIER ........................................................................................ 464

I2C Address Register – I2CADDR ................................................................................................. 466

I2C Status Register – I2CSR ......................................................................................................... 467

I2C SCL High Period Generation Register – I2CSHPGR .............................................................. 470

I2C SCL Low Period Generation Register – I2CSLPGR ............................................................... 471

I2C Data Register – I2CDR ........................................................................................................... 472

I2C Target Register – I2CTAR ....................................................................................................... 473

I2C Address Mask Register – I2CADDMR .................................................................................... 474

I2C Address Snoop Register – I2CADDSR ................................................................................... 475

I2C Timeout Register – I2CTOUT.................................................................................................. 476

Table of Contents

21 Serial Peripheral Interface (SPI) ...................................................................... 477

Introduction ........................................................................................................................ 477

Features ............................................................................................................................. 478

Function Descriptions ........................................................................................................ 478

Master Mode ................................................................................................................................. 478

Slave Mode ................................................................................................................................... 478

SPI Serial Frame Format .............................................................................................................. 479

Status Flags .................................................................................................................................. 483

Register Map ..................................................................................................................... 486

Register Descriptions ......................................................................................................... 486

SPI Control Register 0 – SPICR0 ................................................................................................. 486

SPI Control Register 1 – SPICR1 ................................................................................................. 488

SPI Interrupt Enable Register – SPIIER ....................................................................................... 490

SPI Clock Prescaler Register – SPICPR ...................................................................................... 491

SPI Data Register – SPIDR .......................................................................................................... 492

SPI Status Register – SPISR ........................................................................................................ 493

SPI FIFO Control Register – SPIFCR ........................................................................................... 495

SPI FIFO Status Register – SPIFSR ............................................................................................ 496

SPI FIFO Time Out Counter Register – SPIFTOCR ..................................................................... 497

22 Universal Synchronous Asynchronous Receiver Transmitter (USART) ..... 498

Introduction ........................................................................................................................ 498

Features ............................................................................................................................. 499

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32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Function Descriptions ........................................................................................................ 500

Serial Data Format ........................................................................................................................ 500

Baud Rate Generation .................................................................................................................. 501

Hardware Flow Control ................................................................................................................. 502

IrDA ............................................................................................................................................... 504

RS485 Mode ................................................................................................................................. 506

Synchronous Master Mode ........................................................................................................... 509

Interrupts and Status .....................................................................................................................511

PDMA Interface ..............................................................................................................................511

Register Map ..................................................................................................................... 511

Register Descriptions ......................................................................................................... 512

USART Data Register – USRDR .................................................................................................. 512

USART Control Register – USRCR .............................................................................................. 513

USART FIFO Control Register – USRFCR................................................................................... 515

USART Interrupt Enable Register – USRIER ............................................................................... 516

USART Status & Interrupt Flag Register – USRSIFR................................................................... 518

USART Timing Parameter Register – USRTPR ........................................................................... 520

USART IrDA Control Register – IrDACR ...................................................................................... 521

USART RS485 Control Register – RS485CR............................................................................... 522

USART Synchronous Control Register – SYNCR ........................................................................ 523

USART Divider Latch Register – USRDLR................................................................................... 524

USART Test Register – USRTSTR ............................................................................................... 525

Table of Contents

23 Universal Asynchronous Receiver Transmitter (UART) ................................ 526

Introduction ........................................................................................................................ 526

Features ............................................................................................................................. 527

Function Descriptions ........................................................................................................ 527

Serial Data Format ........................................................................................................................ 527

Baud Rate Generation .................................................................................................................. 528

Interrupts and Status .................................................................................................................... 529

PDMA Interface ............................................................................................................................. 529

Register Map ..................................................................................................................... 530

Register Descriptions ......................................................................................................... 530

UART Data Register – URDR ....................................................................................................... 530

UART Control Register – URCR ................................................................................................... 531

UART Interrupt Enable Register – URIER .................................................................................... 533

UART Status & Interrupt Flag Register – URSIFR ....................................................................... 534

UART Divider Latch Register – URDLR ....................................................................................... 536

UART Test Register – URTSTR .................................................................................................... 537

24 Smart Card Interface (SCI) ............................................................................... 538

Introduction ........................................................................................................................ 538

Features ............................................................................................................................. 539

Functional Descriptions ..................................................................................................... 539

Rev. 1.30 13 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Elementary Time Unit Counter ...................................................................................................... 539

Guard Time Counter ..................................................................................................................... 541

Waiting Time Counter ................................................................................................................... 542

Card Clock and Data Selection ..................................................................................................... 543

Card Detection ............................................................................................................................. 543

SCI Data Transfer Mode ............................................................................................................... 544

Interrupt Generator ....................................................................................................................... 546

PDMA Interface ............................................................................................................................. 547

Register Map ..................................................................................................................... 547

Register Descriptions ......................................................................................................... 548

SCI Control Register – CR ............................................................................................................ 548

SCI Status Register – SR ............................................................................................................. 550

SCI Contact Control Register – CCR ............................................................................................ 552

SCI Elementary Time Unit Register – ETUR ................................................................................ 553

SCI Guard Time Register – GTR .................................................................................................. 554

SCI Waiting Time Register – WTR................................................................................................ 555

SCI Interrupt Enable Register – IER ............................................................................................. 556

SCI Interrupt Pending Register – IPR ........................................................................................... 558

SCI Transmit Buffer – TXB............................................................................................................ 560

SCI Receive Buffer – RXB ............................................................................................................ 560

SCI Prescaler Register – PSCR ................................................................................................... 561

Table of Contents

25 USB Device Controller (USB) .......................................................................... 562

Introduction ........................................................................................................................ 562

Features ............................................................................................................................. 562

Functional Descriptions ..................................................................................................... 563

Endpoints ...................................................................................................................................... 563

EP-SRAM ..................................................................................................................................... 563

Serial Interface Engine – SIE ........................................................................................................ 564

Double-Buffering ........................................................................................................................... 564

Suspend Mode and Wake-up ....................................................................................................... 566

Remote Wake-up .......................................................................................................................... 566

Register Map ..................................................................................................................... 566

Register Descriptions ......................................................................................................... 568

USB Control and Status Register – USBCSR .............................................................................. 568

USB Interrupt Enable Register – USBIER .................................................................................... 570

USB Interrupt Status Register – USBISR ..................................................................................... 571

USB Frame Count Register – USBFCR ....................................................................................... 573

USB Device Address Register – USBDEVA ................................................................................. 574

USB Endpoint 0 Control and Status Register – USBEP0CSR ..................................................... 575

USB Endpoint 0 Interrupt Enable Register – USBEP0IER ........................................................... 576

USB Endpoint 0 Interrupt Status Register – USBEP0ISR ............................................................ 578

USB Endpoint 0 Transfer Count Register – USBEP0TCR ........................................................... 579

USB Endpoint 0 Conguration Register – USBEP0CFGR ........................................................... 580

Rev. 1.30 14 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

USB Endpoint 1 ~ 3 Control and Status Register – USBEPnCSR, n = 1 ~ 3 ............................... 581

USB Endpoint 1 ~ 3 Interrupt Enable Register – USBEPnIER, n = 1 ~ 3 ..................................... 582

USB Endpoint 1 ~ 3 Interrupt Status Register – USBEPnISR, n = 1 ~ 3 ...................................... 583

USB Endpoint 1 ~ 3 Transfer Count Register – USBEPnTCR, n = 1 ~ 3 ..................................... 584

USB Endpoint 1 ~ 3 Conguration Register – USBEPnCFGR, n = 1 ~ 3 ..................................... 585

USB Endpoint 4 ~ 7 Control and Status Register – USBEPnCSR, n = 4 ~ 7 ............................... 586

USB Endpoint 4 ~ 7 Interrupt Enable Register – USBEPnIER, n = 4 ~ 7 ..................................... 589

USB Endpoint 4 ~ 7 Interrupt Status Register – USBEPnISR, n = 4 ~ 7 ...................................... 590

USB Endpoint 4 ~ 7 Transfer Count Register – USBEPnTCR, n = 4 ~ 7 ..................................... 591

USB Endpoint 4 ~ 7 Conguration Register – USBEPnCFGR, n = 4 ~ 7 ..................................... 592

26 Peripheral Direct Memory Access (PDMA) ..................................................... 593

Introduction ........................................................................................................................ 593

Features ............................................................................................................................. 593

Functional Description ....................................................................................................... 594

AHB Master .................................................................................................................................. 594

PDMA Channel ............................................................................................................................. 594

PDMA Request Mapping .............................................................................................................. 594

Channel transfer ........................................................................................................................... 596

Channel Priority ............................................................................................................................ 596

Transfer Request .......................................................................................................................... 597

Address Mode ............................................................................................................................... 597

Auto-Reload .................................................................................................................................. 597

Transfer Interrupt .......................................................................................................................... 598

Register Map ..................................................................................................................... 598

Register Descriptions ......................................................................................................... 600

PDMA Channel n Control Register – PDMACHnCR, n = 0 ~ 5 .................................................... 600

PDMA Channel n Source Address Register – PDMACHnSADR, n = 0 ~ 5 .................................. 602

PDMA Channel n Destination Address Register – PDMACHnDADR, n=0~5 ............................... 603

PDMA Channel n Transfer Size Register – PDMACHnTSR, n = 0 ~ 5 ......................................... 604

PDMA Channel n Current Transfer Size Register – PDMACHnCTSR, n=0~5 ............................. 605

PDMA Interrupt Status Register – PDMAISR ............................................................................... 606

PDMA Interrupt Status Clear Register – PDMAISCR ................................................................... 607

PDMA Interrupt Enable Register – PDMAIER .............................................................................. 609

Table of Contents

27 Extend Bus Interface (EBI) ............................................................................... 610

Introduction ........................................................................................................................ 610

Features ............................................................................................................................. 610

Function Descriptions ........................................................................................................ 611

Non-multiplexed 8-bit Data 8-bit Address Mode ........................................................................... 612

Non-multiplexed 16-bit Data N-bit Address Mode ......................................................................... 613

Multiplexed 16-bit Data, 16-bit Address Mode .............................................................................. 614

Multiplexed 8-bit Data, 20-bit Address Mode ................................................................................ 615

Write Buffer and EBI Status .......................................................................................................... 616

Rev. 1.30 15 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Bus Turn-around and Idle Cycles ................................................................................................. 616

AHB Transaction Width Conversion ............................................................................................. 617

EBI Bank Access .......................................................................................................................... 619

PDMA Request ............................................................................................................................. 620

Register Map ..................................................................................................................... 620

Register Descriptions ......................................................................................................... 620

EBI Control Register – EBICR ...................................................................................................... 620

EBI Status Register – EBISR ........................................................................................................ 622

EBI Address Timing Register – EBIATR ....................................................................................... 623

EBI Read Timing Register – EBIRTR ........................................................................................... 624

EBI Write Timing Register – EBIWTR ........................................................................................... 625

EBI Parity Register – EBIPR ......................................................................................................... 626

28 Inter-IC Sound (I2S) ........................................................................................... 627

Introduction ........................................................................................................................ 627

Features ............................................................................................................................. 627

Functional Description ....................................................................................................... 628

I2S Master and Slave Mode .......................................................................................................... 628

I2S Clock Rate Generator ............................................................................................................. 629

I2S Interface Format ...................................................................................................................... 631

FIFO Control and Arrangement .................................................................................................... 638

PDMA and Interrupt ...................................................................................................................... 639

Register Map ..................................................................................................................... 639

Register Descriptions ......................................................................................................... 640

I2S Control Register – I2SCR ........................................................................................................ 640

I2S Interrupt Enable Register – I2SIER ......................................................................................... 642

I2S Clock Divider Register – I2SCDR ........................................................................................... 643

I2S TX Data Register – I2STXDR ................................................................................................. 644

I2S RX Data Register – I2SRXDR ................................................................................................. 644

I2S FIFO Control Register – I2SFCR ............................................................................................ 645

I2S Status Register – I2SSR ......................................................................................................... 646

I2S Rate Counter Value Register – I2SRCNTR ............................................................................ 648

Table of Contents

29 Cyclic Redundancy Check (CRC) .................................................................... 649

Introduction ....................................................................................................................... 649

Features ............................................................................................................................. 650

Function Descriptions ........................................................................................................ 650

CRC Computation ......................................................................................................................... 650

Byte and Bit Reversal for CRC Computation ................................................................................ 650

CRC with PDMA ........................................................................................................................... 651

Register Map ..................................................................................................................... 651

Register Descriptions ......................................................................................................... 652

CRC Control Register – CRCCR .................................................................................................. 652

CRC Seed Register – CRCSDR ................................................................................................... 653

Rev. 1.30 16 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

CRC Checksum Register – CRCCSR .......................................................................................... 654

CRC Data Register – CRCDR ...................................................................................................... 655

Table of Contents

Rev. 1.30 17 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

List of Tables

Table 1. Series Features and Peripheral List .......................................................................................... 32

Table 2. Document Conventions ............................................................................................................. 34

Table 3. Register Map ............................................................................................................................. 39

Table 4. Flash Memory and Option Byte ................................................................................................. 44

Table 5. Relationship Between Wait State Cycle and HCLK .................................................................. 44

Table 6. Booting Modes .......................................................................................................................... 45

Table 7. Option Byte Memory Map ......................................................................................................... 49

Table 8. Access Permission of Protected Main Flash Page .................................................................... 50

Table 9. Access Permission When Security Protection is Enabled ......................................................... 51

Table 10. FMC Register Map .................................................................................................................. 52

Table 11. Operation Mode Denitions ..................................................................................................... 72

Table 12. Enter/Exit Power Saving Modes .............................................................................................. 73

Table 13. Power Status After System Reset ........................................................................................... 74

Table 14. PWRCU Register Map ............................................................................................................ 74

Table 15. Output Divider2 Value Mapping............................................................................................... 88

Table 16. Feedback Divider2 Value Mapping.......................................................................................... 88

Table 17. CKOUT Clock Source ............................................................................................................. 91

Table 18. CKCU Register Map ............................................................................................................... 92

Table 19. RSTCU Register Map ........................................................................................................... 121

Table 20. AFIO, GPIO and IO Pad Control Signal True Table............................................................... 129

Table 21. GPIO Register Map ............................................................................................................... 130

Table 22. AFIO Selection for Peripheral Map Example ......................................................................... 177

Table 23. AFIO Register Map ................................................................................................................ 177

Table 24. Exception Types .................................................................................................................... 182

Table 25. NVIC Register Map ............................................................................................................... 184

Table 26. EXTI Register Map ................................................................................................................ 188

Table 27. Data format in ADCDR [15:0] ................................................................................................ 203

Table 28. A/D Converter Register Map ................................................................................................. 205

Table 29. CMP Register Map ................................................................................................................ 224

Table 30. Counting Direction and Encoding Signals ............................................................................. 247

Table 31. Compare Match Output Setup .............................................................................................. 248

Table 32. GPTM Register Map ............................................................................................................. 260

Table 33. GPTM Internal Trigger Connection ....................................................................................... 266

Table 34. BFTM Register Map .............................................................................................................. 307

Table 35. Compare Match Output Setup .............................................................................................. 328

Table 36. Output Control Bits for Complementary Output with a Break Event Occurrence .................. 336

Table 37. Lock Level Table.................................................................................................................... 346

Table 38. MCTM Register Map ............................................................................................................. 348

Table 39. MCTM Internal Trigger Connection ....................................................................................... 354

List of Tables

Rev. 1.30 18 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Table 40. Compare Match Output Setup .............................................................................................. 407

Table 41. SCTM Register Map .............................................................................................................. 410

Table 42. LSE Startup Mode Operating Current and Startup Time ....................................................... 428

Table 43. RTCOUT Output Mode and Active Level Setting .................................................................. 430

Table 44. RTC Register Map................................................................................................................. 431

Table 45. Watchdog Timer Register Map .............................................................................................. 440

Table 46. Conditions of Holding SCL line .............................................................................................. 459

Table 47. I2C Register Map ................................................................................................................... 461

Table 48. I2C Clock Setting Example .................................................................................................... 471

Table 49. SPI Interface Format Setup ................................................................................................... 479

Table 50. SPI Mode Fault Trigger Conditions ....................................................................................... 484

Table 51. SPI Master Mode SEL Pin Status ......................................................................................... 484

Table 52. SPI Register Map .................................................................................................................. 486

Table 53. Baud Rate Deviation Error Calculation – CK_USART = 40 MHz .......................................... 501

Table 54. Baud Rate Deviation Error Calculation – CK_USART = 48 MHz .......................................... 502

Table 55. USART Register Map .............................................................................................................511

Table 56. Baud Rate Deviation Error Calculation – CK_UART = 40 MHz ............................................ 528

Table 57. Baud Rate Deviation Error Calculation – CK_UART = 48 MHz ............................................ 529

Table 58. UART Register Map .............................................................................................................. 530

Table 59. DI Field Based Di Encoded Decimal Values ......................................................................... 540

Table 60. FI Field Based Fi Encoded Decimal Values .......................................................................... 540

Table 61. Possible ETU Values Obtained with the Fi/Di Ratio .............................................................. 540

Table 62. SCI Register Map ................................................................................................................. 547

Table 63. Endpoint Characteristics ....................................................................................................... 563

Table 64. USB Data Types and Buffer Size .......................................................................................... 563

Table 65. USB Register Map ................................................................................................................ 566

Table 66. Resume Event Detection ...................................................................................................... 569

Table 67. PDMA Channel Assignments ................................................................................................ 595

Table 68. PDMA Address Modes .......................................................................................................... 597

Table 69. PDMA Register Map .............................................................................................................. 598

Table 70. EBI Maps AHB Transactions Width to External Device Transactions. .................................. 618

Table 71. EBI Maps AHB Transactions Width to External Device Transactions Width ......................... 618

Table 72. EBI Register Map .................................................................................................................. 620

Table 73. Recommend FS List @ 8 MHz PCLK ................................................................................... 630

Table 74. Recommend FS List @ 48 MHz PCLK ................................................................................. 630

Table 75. I2S Register Map .................................................................................................................. 639

Table 76. CRC Register Map ................................................................................................................ 651

List of Tables

Rev. 1.30 19 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

List of Figures

Figure 1. Block Diagram ......................................................................................................................... 33

Figure 2. Cortex®-M0+ Block Diagram .................................................................................................... 36

Figure 3. Bus Architecture ...................................................................................................................... 37

Figure 4. Memory Map ............................................................................................................................ 38

Figure 5. Flash Memory Controller Block Diagram ................................................................................. 42

Figure 6. Flash Memory Map .................................................................................................................. 43

Figure 7. Vector Remapping ................................................................................................................... 45

Figure 8. Page Erase Operation Flowchart ............................................................................................ 46

Figure 9. Mass Erase Operation Flowchart ............................................................................................ 47

Figure 10. Word Programming Operation Flowchart .............................................................................. 48

Figure 11. PWRCU Block Diagram ......................................................................................................... 68

Figure 12. Power On Reset / Power Down Reset Waveform ................................................................. 71

Figure 13. CKCU Block Diagram ............................................................................................................ 83

Figure 14. External Crystal, Ceramic, and Resonators for HSE ............................................................. 84

Figure 15. HSI Auto Trimming Block Diagram ....................................................................................... 86

Figure 16. PLL Block Diagram ................................................................................................................ 87

Figure 17. External Crystal, Ceramic, and Resonators for LSE ............................................................ 89

Figure 18. RSTCU Block Diagram .........................................................................................................119

Figure 19. Power On Reset Sequence ................................................................................................. 120

Figure 20. GPIO Block Diagram ........................................................................................................... 127

Figure 21. AFIO/GPIO Control Signal ................................................................................................... 129

Figure 22. AFIO Block Diagram ............................................................................................................ 175

Figure 23. EXTI Channel Input Selection ............................................................................................. 176

Figure 24. EXTI Block Diagram ............................................................................................................ 185

Figure 25. EXTI Wake-up Event Management ..................................................................................... 186

Figure 26. EXTI Interrupt Debounce Function ...................................................................................... 187

Figure 27. ADC Block Diagram ............................................................................................................. 197

Figure 28. One Shot Conversion Mode ................................................................................................ 200

Figure 29. Continuous Conversion Mode ............................................................................................. 200

Figure 30. Discontinuous Conversion Mode ......................................................................................... 202

Figure 31. Comparator Block Diagram ................................................................................................. 221

Figure 32. 6-Bit Scaler for Comparator Voltage Reference Block Diagram .......................................... 222

Figure 33. Interrupt Signals of Comparators ......................................................................................... 223

Figure 34. Wakeup Signals of Comparators ......................................................................................... 223

Figure 35. GPTM Block Diagram .......................................................................................................... 230

Figure 36. Up-counting Example .......................................................................................................... 232

Figure 37. Down-counting Example ...................................................................................................... 233

Figure 38. Center-aligned Counting Example ....................................................................................... 234

Figure 39. GPTM Clock Selection Source ............................................................................................ 235

List of Figures

Rev. 1.30 20 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Figure 40. Trigger Controller Block ....................................................................................................... 236

Figure 41. Slave Controller Diagram .................................................................................................... 237

Figure 42. GPTM in Restart Mode ........................................................................................................ 237

Figure 43. GPTM in Pause Mode ......................................................................................................... 238

Figure 44. GPTM in Trigger Mode ........................................................................................................ 239

Figure 45. Master GPTMn and Slave GPTMm/MCTMm Connection ................................................... 240

Figure 46. MTO Selection ..................................................................................................................... 240

Figure 47. Capture/Compare Block Diagram ........................................................................................ 241

Figure 48. Input Capture Mode ............................................................................................................. 242

Figure 49. PWM Pulse Width Measurement Example .......................................................................... 243

Figure 50. Channel 0 and Channel 1 Input Stages ............................................................................... 244

Figure 51. Channel 2 and Channel 3 Input Stages ............................................................................... 245

Figure 52. TI0 Digital Filter Diagram with N = 2 .................................................................................... 245

Figure 53. Input Stage and Quadrature Decoder Block Diagram ......................................................... 246

Figure 54. Both TI0 and TI1 Quadrature Decoder Counting ................................................................. 247

Figure 55. Output Stage Block Diagram ............................................................................................... 248

Figure 56. Toggle Mode Channel Output Reference Signal (CHxPRE = 0) ......................................... 249

Figure 57. Toggle Mode Channel Output Reference Signal (CHxPRE = 1) ......................................... 249

Figure 58. PWM Mode Channel Output Reference Signal and Counter in Up-counting Mode ............ 250

Figure 59. PWM Mode Channel Output Reference Signal and Counter in Down-counting Mode ....... 250

Figure 60. PWM Mode Channel Output Reference Signal and Counter in Centre-align Mode ............ 251

Figure 61. Update Event Setting Diagram ............................................................................................ 252

Figure 62. Single Pulse Mode ............................................................................................................... 253

Figure 63. Immediate Active Mode Minimum Delay ............................................................................. 254

Figure 64. Asymmetric PWM mode versus center align counting mode .............................................. 255

Figure 65. Pausing GPTM1 using the GPTM0 CH0OREF Signal ........................................................ 256

Figure 66. Triggering GPTM1 with GPTM0 Update Event .................................................................... 257

Figure 67. Trigger GPTM0 and GPTM1 with the GPTM0 CH0 Input .................................................... 258

Figure 68. GPTM PDMA Mapping Diagram .......................................................................................... 259

Figure 69. BFTM Block Diagram .......................................................................................................... 304

Figure 70. BFTM – Repetitive Mode ..................................................................................................... 305

Figure 71. BFTM – One Shot Mode ...................................................................................................... 306

Figure 72. BFTM – One Shot Mode Counter Updating ....................................................................... 306

Figure 73. MCTM Block Diagram ..........................................................................................................311

Figure 74. Up-counting Example .......................................................................................................... 313

Figure 75. Down-counting Example ...................................................................................................... 314

Figure 76. Center-aligned Counting Example ....................................................................................... 315

Figure 77. Update Event 1 Dependent Repetition Mechanism Example .............................................. 316

Figure 78. MCTM Clock Selection Source ............................................................................................ 317

Figure 79. Trigger Controller Block ....................................................................................................... 318

Figure 80. Slave Controller Diagram .................................................................................................... 319

List of Figures

Rev. 1.30 21 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Figure 81. MCTM in Restart Mode ....................................................................................................... 319

Figure 82. MCTM in Pause Mode ......................................................................................................... 320

Figure 83. MCTM in Trigger Mode ........................................................................................................ 320

Figure 84. Master MCTMn and Slave GPTMm Connection ................................................................. 321

Figure 85. MTO Selection ..................................................................................................................... 321

Figure 86. Capture/Compare Block Diagram ........................................................................................ 322

Figure 87. Input Capture Mode ............................................................................................................. 323

Figure 88. PWM Pulse Width Measurement Example .......................................................................... 324

Figure 89. Channel 0 and Channel 1 Input Stages ............................................................................... 325

Figure 90. Channel 2 and Channel 3 Input Stages ............................................................................... 325

Figure 91. TI0 Digital Filter Diagram with N = 2 .................................................................................... 326

Figure 92. Output Stage Block Diagram ............................................................................................... 327

Figure 93. Toggle Mode Channel Output Reference Signal – CHxPRE = 0 ......................................... 328

Figure 94. Toggle Mode Channel Output Reference Signal – CHxPRE = 1 ......................................... 329

Figure 95. PWM Mode Channel Output Reference Signal and Counter in Up-counting Mode ............ 329

Figure 96. PWM Mode Channel Output Reference Signal and Counter in Down-counting Mode ....... 330

Figure 97. PWM Mode 1 Channel Output Reference Signal and Counter in Centre-aligned Counting

Mode ...................................................................................................................................................... 330

Figure 98. Dead-time Insertion Performed for Complementary Outputs .............................................. 331

Figure 99. MCTM Break Signal Bolck Diagram .................................................................................... 332

Figure 100. MT_BRK Pin Digital Filter Diagram with N = 2 .................................................................. 332

Figure 101. Channel 3 Output with a Break Event Occurrence ............................................................ 333

Figure 102. Channel 0 ~ 2 Complementary Outputs with a Break Event Occurrence.......................... 334

Figure 103. Channel 0 ~ 2 Only One Output Enabled when Fault Event Occurs ................................. 334

Figure 104. Hardware Protection When Both CHxO and CHxNO Are in Active Condition ................... 335

Figure 105. Update Event 1 Setup Diagram ......................................................................................... 337

Figure 106. CHxE, CHxNE and CHxOM Updated by Update Event 2 ................................................. 338

Figure 107. Update Event 2 Setup Diagram ......................................................................................... 338

Figure 108. Single Pulse Mode ............................................................................................................. 339

Figure 109. Immediate Active Mode Minimum Delay ........................................................................... 340

Figure 110. Asymmetric PWM Mode versus Center-aligned Counting Mode ....................................... 341

Figure 111. Pausing GPTM using the MCTM CH0OREF Signal .......................................................... 342

Figure 112. Triggering GPTM with MCTM Update Event 1................................................................... 343

Figure 113. Trigger MCTM and GPTM with the MCTM CH0 Input ....................................................... 344

Figure 114. CH1XOR Input as Hall Sensor Interface............................................................................ 345

Figure 115. MCTM PDMA Mapping Diagram........................................................................................ 347

Figure 116. SCTM Block Diagram ........................................................................................................ 398

Figure 117. Up-counting Example......................................................................................................... 399

Figure 118. SCTM Clock Selection Source........................................................................................... 400

Figure 119. Trigger Controller Block ..................................................................................................... 401

Figure 120. Slave Controller Diagram .................................................................................................. 402

List of Figures

Rev. 1.30 22 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Figure 121. SCTM in Restart Mode ...................................................................................................... 402

Figure 122. SCTM in Pause Mode ....................................................................................................... 403

Figure 123. SCTM in Trigger Mode ...................................................................................................... 403

Figure 124. Capture/Compare Block Diagram ...................................................................................... 404

Figure 125. Input Capture Mode ........................................................................................................... 405

Figure 126. Channel Input Stages ........................................................................................................ 406

Figure 127. TI Digital Filter Diagram with N = 2 .................................................................................... 406

Figure 128. Output Stage Block Diagram ............................................................................................. 407

Figure 129. Toggle Mode Channel Output Reference Signal (CHPRE = 0) ......................................... 408

Figure 130. Toggle Mode Channel Output Reference Signal (CHPRE = 1) ......................................... 408

Figure 131. PWM Mode Channel Output Reference Signal ................................................................. 409

Figure 132. Update Event Setting Diagram .......................................................................................... 410

Figure 133. RTC Block Diagram ........................................................................................................... 427

Figure 134. Watchdog Timer Block Diagram ....................................................................................... 437

Figure 135. Watchdog Timer Behavior ................................................................................................. 439

Figure 136. I2C Module Block Diagram ................................................................................................. 446

Figure 137. START and STOP Condition ............................................................................................. 448

Figure 138. Data Validity ....................................................................................................................... 448

Figure 139. 7-bit Addressing Mode ....................................................................................................... 449

Figure 140. 10-bit Addressing Write Transmit Mode ............................................................................ 450

Figure 141. 10-bit Addressing Read Receive Mode ............................................................................ 450

Figure 142. I2C Bus Acknowledge ........................................................................................................ 451

Figure 143. Clock Synchronization during Arbitration ........................................................................... 452

Figure 144. Two Master Arbitration Procedure ..................................................................................... 452

Figure 145. Master Transmitter Timing Diagram .................................................................................. 454

Figure 146. Master Receiver Timing Diagram ...................................................................................... 456

Figure 147. Slave Transmitter Timing Diagram .................................................................................... 457

Figure 148. Slave Receiver Timing Diagram ........................................................................................ 458

Figure 149. SCL Timing Diagram .......................................................................................................... 471

Figure 150. SPI Block Diagram ............................................................................................................ 477

Figure 151. SPI Single Byte Transfer Timing Diagram – CPOL = 0, CPHA = 0 .................................... 479

Figure 152. SPI Continuous Data Transfer Timing Diagram – CPOL = 0, CPHA = 0 ........................... 480

Figure 153. SPI Single Byte Transfer Timing Diagram – CPOL = 0, CPHA = 1 .................................... 480

Figure 154. SPI Continuous Transfer Timing Diagram – CPOL = 0, CPHA = 1 .................................... 481

Figure 155. SPI Single Byte Transfer Timing Diagram – CPOL = 1, CPHA = 0 .................................... 481

Figure 156. SPI Continuous Transfer Timing Diagram – CPOL = 1, CPHA = 0 .................................... 482

Figure 157. SPI Single Byte Transfer Timing Diagram – CPOL = 1, CPHA = 1 .................................... 482

Figure 158. SPI Continuous Transfer Timing Diagram – CPOL = 1, CPHA = 1 .................................... 482

Figure 159. SPI Multi-Master Slave Environment ................................................................................. 484

Figure 160. USART Block Diagram ...................................................................................................... 498

Figure 161. USART Serial Data Format ............................................................................................... 500

List of Figures

Rev. 1.30 23 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Figure 162. USART Clock CK_USART and Data Frame Timing .......................................................... 501

Figure 163. Hardware Flow Control between 2 USARTs ...................................................................... 502

Figure 164. USART RTS Flow Control ................................................................................................. 503

Figure 165. USART CTS Flow Control ................................................................................................. 503

Figure 166. IrDA Modulation and Demodulation ................................................................................... 504

Figure 167. USART I/O and IrDA Block Diagram ................................................................................. 506

Figure 168. RS485 Interface and Waveform ........................................................................................ 507

Figure 169. USART Synchronous Transmission Example ................................................................... 509

Figure 170. 8-bit Format USART Synchronous Waveform ................................................................... 510

Figure 171. UART Block Diagram ......................................................................................................... 526

Figure 172. UART Serial Data Format .................................................................................................. 527

Figure 173. UART Clock CK_UART and Data Frame Timing ............................................................... 528

Figure 174. SCI Block Diagram ............................................................................................................ 538

Figure 175. Character Frame and Compensation Mode ...................................................................... 541

Figure 176. Guard Time Duration ......................................................................................................... 542

Figure 177. Character and Block Waiting Time Duration – CWT and BWT .......................................... 543

Figure 178. SCI Card Detection Diagram ............................................................................................. 544

Figure 179. SCI Interrupt Structure ....................................................................................................... 546

Figure 180. USB Block Diagram ........................................................................................................... 562

Figure 181. Endpoint Buffer Allocation Example................................................................................... 564

Figure 182. Double-buffering Operation Example ................................................................................ 565

Figure 183. PDMA Block Diagram ........................................................................................................ 593

Figure 184. PDMA Request Mapping Architecture ............................................................................... 595

Figure 185. PDMA Channel Arbitration and Scheduling Example ........................................................ 596

Figure 186. EBI Block Diagram .............................................................................................................611

Figure 187. EBI Non-multiplexed 8-bit Data, 8-bit Address Read Operation ........................................ 612

Figure 188. EBI Non-multiplexed 8-bit Data, 8-bit Address Write Operation ........................................ 612

Figure 189. EBI Non-multiplexed 16-bit Data, N-bit Address Read Operation ..................................... 613

Figure 190. EBI Non-multiplexed 16-bit Data, N-bit Address Write Operation...................................... 613

Figure 191. An EBI Address Latch Setup Diagram ............................................................................... 614

Figure 192. EBI Multiplexed 16-bit Data, 16-bit Address Read Operation ............................................ 614

Figure 193. EBI Multiplexed 16-bit Data, 16-bit Address Write Operation ............................................ 615

Figure 194. EBI Multiplexed 8-bit Data, 20-bit Address Read Operation .............................................. 615

Figure 195. EBI Multiplexed 8-bit Data, 20-bit Address Write Operation .............................................. 616

Figure 196. EBI Inserts an IDLE Cycle between Transactions in the Same Bank (NOIDLE = 0) ......... 617

Figure 197. EBI De-asserts an IDLE Cycle between Transactions in the Same Bank (NOIDLE = 1) .. 617

Figure 198. EBI Bank Memory Map ...................................................................................................... 619

Figure 199. I2S Block Diagram .............................................................................................................. 627

Figure 200. Simple I2S Master/Slave Conguration .............................................................................. 628

Figure 201. I2S Clock Generator Diagram ............................................................................................ 629

Figure 202. I2S-justied Stereo Mode Waveforms ................................................................................ 631

List of Figures

Rev. 1.30 24 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Figure 203. I2S-justied Stereo Mode Waveforms (32-bit Channel Enabled) ....................................... 631

Figure 204. Left-justied Stereo Mode Waveforms ............................................................................... 632

Figure 205. Left-justied Stereo Mode Waveforms (32-bit Channel Enabled) ...................................... 632

Figure 206. Right-justied Stereo Mode Waveforms ............................................................................ 633

Figure 207. Right-justied Stereo Mode Waveforms (32-bit Channel Enabled) ................................... 633

Figure 208. I2S-justied Mono Mode Waveforms .................................................................................. 634

Figure 209. I2S-justied Mono Mode Waveforms (32-bit Channel Enabled) ......................................... 634

Figure 210. Left-justied Mono Mode Waveforms ................................................................................ 635

Figure 211. Left-justied Mono Mode Waveforms (32-bit Channel Enabled) ....................................... 635

Figure 212. Right-justied Mono Mode Waveforms .............................................................................. 636

Figure 213. Right-justied Mono Mode Waveforms (32-bit Channel Enabled) ..................................... 636

Figure 214. I2S-justied Repeat Mode Waveforms ............................................................................... 637

Figure 215. I2S-justied Repeat Mode Waveforms (32-bit Channel Enabled) ...................................... 637

Figure 216. FIFO Data Content Arrangement for Various Modes ......................................................... 638

Figure 217. CRC Block Diagram .......................................................................................................... 649

Figure 218. CRC Data Bit and Byte Reversal Example ........................................................................ 651

List of Figures

Rev. 1.30 25 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

1

Overview

Introduction

This user manual provides detailed information including how to use the devices, system and
bus architecture, memory organization and peripheral instructions. The target audiences for this
document are software developers, application developers and hardware developers. For more
information regarding pin assignment, package and electrical characteristics, please refer to the
datasheet.

The devices are high performance and low power consumption 32-bit microcontrollers based
around an Arm® Cortex®-M0+ processor core. The Cortex®-M0+ is a next-generation processor
core which is tightly coupled with Nested Vectored Interrupt Controller (NVIC), SysTick timer,
and including advanced debug support.

The devices operate at a frequency of up to 48 MHz with a Flash accelerator to obtain maximum

efciency. It provides up to 128 KB of embedded Flash memory for code/data storage and 16 KB

of embedded SRAM memory for system operation and application program usage. A variety of
peripherals, such as ADC, I2C, USART, UART, SPI, I2S, GPTM, MCTM, SCI, CRC-16/32, RTC,

WDT, PDMA, EBI, USB2.0 FS, SW-DP (Serial Wire Debug Port), etc., are also implemented in
the device series. Several power saving modes provide the exibility for maximum optimization

between wakeup latency and power consumption, an especially important consideration in low
power applications.

Introduction

The above features ensure that the devices are suitable for use in a wide range of applications,
especially in areas such as white goods application control, power monitors, alarm systems,
consumer products, handheld equipment, data logging applications, motor control and so on.

Rev. 1.30 26 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Features

▄

Core

● 32-bit Arm® Cortex®-M0+ processor core

● Up to 48 MHz operating frequency

● 0.93 DMIPS/MHz (Dhrystone v2.1)

● Single-cycle multiplication

● Integrated Nested Vectored Interrupt Controller (NVIC)

● 24-bit SysTick timer

▄

On-chip Memory

● Up to 128 KB on-chip Flash memory for instruction/data and options storage

● 16 KB on-chip SRAM

● Supports multiple boot modes

▄

Flash Memory Controller – FMC

● Flash accelerator for maximum efciency

● 32-bit word programming with In System Programming Interface (ISP) and In Application

Programming (IAP)

● Flash protection capability to prevent illegal access

▄

Reset Control Unit – RSTCU

● Supply supervisor: Power On Reset / Power Down Reset (POR/PDR) and Programmable Low

Voltage Detector (LVD)

▄

Clock Control Unit – CKCU

● External 4 to 16 MHz crystal oscillator

● External 32,768 Hz crystal oscillator

● Internal 8MHz RC oscillator trimmed to ±2 % accuracy at 3.3 V operating voltage and 25 ºC

operating temperature

● Internal 32 kHz RC oscillator

● Integrated system clock PLL

● Independent clock divider and gating bits for peripheral clock sources

▄

Power management – PWRCU

● Single VDD power supply: 2.0 V to 3.6 V

● Integrated 1.5 V LDO regulator for CPU core, peripherals and memories power supply

● V

battery power supply for RTC and backup registers

BAT

● Three power domains: VDD, 1.5 V and Backup

● Four power saving modes: Sleep, Deep-Sleep1, Deep-Sleep2, Power-Down

▄

External Interrupt/Event Controller – EXTI

● Up to 16 EXTI lines with congurable trigger source and type

● All GPIO pins can be selected as EXTI trigger source

● Source trigger type includes high level, low level, negative edge, positive edge, or both edge

● Individual interrupt enable, wakeup enable and status bits for each EXTI line

● Software interrupt trigger mode for each EXTI line

● Integrated deglitch lter for short pulse blocking

Introduction

Rev. 1.30 27 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

▄

Analog to Digital Converter – ADC

● 12-bit SAR ADC engine

● Up to 1 MSPS conversion rate

● Up to 12 external analog input channels

▄

Analog Comparator – CMP

● Two rail-to-rail comparator

● Each comparator has congurable negative inputs used for exible voltage selection

● Dedicated I/O pin or internal voltage reference provided by 6-bit scaler.

● Programmable hysteresis

● Programming speed and consumption

● Comparator output can be output to I/O or to timers or ADC trigger inputs

● 6-bit scaler can be congurable to dedicated I/O for voltage reference.

● Comparator has interrupt generation capability with wakeup from Sleep or Deep Sleep modes

through the EXTI controller.

▄

IO ports – GPIO

● Up to 51 GPIOs

● Port A, B, C, D are mapped as 16 external interrupts – EXTI

● Almost I/O pins are congurable output driving current.

▄

Motor Control Timer – MCTM

● One 16-bit up, down, up/down auto-reload counter

● Up to 4 independent channels

● 16-bit programmable prescaler allowing dividing the counter clock frequency by any factor

between 1 and 65536

● Input Capture function

● Compare Match Output

● PWM waveform generation with Edge-aligned and Center-aligned Counting Modes

● Single Pulse Mode Output

● Complementary Outputs with programmable dead-time insertion

● Supports 3-phase motor control and hall sensor interface

● Break input to force the timer’s output signals into a reset or xed condition

▄

PWM Generation and Capture Timer – GPTM

● One 16-bit up, down, up/down auto-reload counter

● Up to 4 independent channels for each timer

● 16-bit programmable prescaler allowing dividing the counter clock frequency by any factor

between 1 and 65536

● Input Capture function

● Compare Match Output

● PWM waveform generation with Edge-aligned and Center-aligned Counting Modes

● Single Pulse Mode Output

● Encoder interface controller with two inputs using quadrature decoder

Introduction

Rev. 1.30 28 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

▄

Single Channel Generation and Capture Timers – SCTM

● One 16-bit up and auto-reload counter

● One channel for each timer

● 16-bit programmable prescaler allowing dividing the counter clock frequency by any factor

between 1 and 65536

● Input Capture function

● Compare Match Output

● PWM waveform generation with Edge-aligned

● Single Pulse Mode Output

▄

Basic Function Timer – BFTM

● One 32-bit compare/match count-up counter – no I/O control features

● One shot mode – counting stops after a match condition

● Repetitive mode – restart counter after a match condition

▄

Watchdog Timer

● 12-bit down counter with 3-bit prescaler

● Reset event for the system

● Programmable watchdog timer window function

● Registers write protection function

▄

Real Time Clock – RTC

● 32-bit up-counter with a programmable prescaler

● Alarm function

● Interrupt and Wake-up event

▄

Inter-integrated Circuit – I2C

● Supports both master and slave modes with a frequency of up to 1 MHz

● Provide an arbitration function and clock synchronization

● Supports 7-bit and 10-bit addressing modes and general call addressing

● Supports slave multi-addressing mode with maskable address

▄

Serial Peripheral Interface – SPI

● Supports both master and slave mode

● Frequency of up to (f

● FIFO Depth: 8 levels

● Multi-master and multi-slave operation

▄

Universal Synchronous Asynchronous Receiver Transmitter – USART

● Supports both asynchronous and clocked synchronous serial communication modes

● Asynchronous operating baud rate up to (f

(f

/8) MHz

PCLK

● Capability of full duplex communication

● Fully programmable characteristics of serial communication including: word length, parity bit,

stop bit and bit order

● Error detection: Parity, overrun, and frame error

● Support Auto hardware ow control mode – RTS, CTS

● IrDA SIR encoder and decoder

● RS485 mode with output enable control

● FIFO Depth: 8 × 9 bits for both receiver and transmitter

/2) MHz for master mode and (f

PCLK

/16) MHz and synchronous operating rate up to

PCLK

/3) MHz for slave mode

PCLK

Introduction

Rev. 1.30 29 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

▄

Universal Asynchronous Receiver Transmitter – UART

● Asynchronous serial communication operating baud-rate up to (f

● Capability of full duplex communication

● Fully programmable characteristics of serial communication including: word length, parity bit,

stop bit and bit order

● Error detection: Parity, overrun, and frame error

▄

Smart Card Interface – SCI

● Supports ISO 7816-3 Standard

● Character mode

● Single transmit buffer and single receive buffer

● 11-bit ETU (elementary time unit) counter

● 9-bit guard time counter

● 24-bit general purpose waiting time counter

● Parity generation and checking

● Automatic character retry on parity error detection in transmission and reception modes

▄

Inter-IC Sound – I2S

● Master or slave mode

● Mono and stereo

● I2S-justied, Left-justied, and Right-justied mode

● 8/16/24/32-bit sample size with 32-bit channel extended

● 8 × 32-bit TX & RX FIFO with PDMA supported

● 8-bit Fractional Clock Divider with rate control

▄

Cyclic Redundancy Check – CRC

● Support CRC16 polynomial: 0x8005, X16+X15+X2+1

● Support CCITT CRC16 polynomial: 0x1021, X16+X12+X5+1

● Support IEEE-802.3 CRC32 polynomial: 0x04C11DB7, X32+X26+X23+X22+X16+X12+X11+X10+

X8+X7+X5+X4+X2+X+1

● Support 1’s complement, byte reverse & bit reverse operation on data and checksum

● Support byte, half-word & word data size

● Programmable CRC initial seed value

● CRC computation done in 1 AHB clock cycle for 8-bit data and 4 AHB clock cycles for 32-bit

data

● Support PDMA to complete a CRC computation of a block of memory

▄

Peripheral Direct Memory Access – PDMA

● 6 channels with trigger source grouping

● 8/16/32-bit width data transfer

● Supports Address increment, decrement or xed mode

● 4-level programmable channel priority

● Auto reload mode

● Supports trigger sources:

ADC, SPI, USART, UART, I2C, I2S, EBI, GPTM, MCTM, SCI and software request

/16) MHz

PCLK

Introduction

Rev. 1.30 30 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

▄

External Bus Interface – EBI

● Programmable interface for various memory types

● Translate the AHB transactions into the appropriate external device protocol

● Individual chip select signal for per memory bank

● Programmable timing to support a wide range of devices

● Automatic translation when AHB transaction width and external memory interface width is

different

● Write buffer to decrease the stalling of the AHB write burst transaction

● Support multiplexed and non-multiplexed address and data line congurations

● Multiplexed address and data line congurations

● Up to 21 address lines

● Up to 16-bit data bus width

▄

Universal Serial Bus Device Controller – USB

● Complies with USB 2.0 full-speed (12Mbps) specication

● On-chip USB full-speed transceiver

● 1 control endpoint (EP0) for control transfer

● 3 single-buffered endpoints for bulk and interrupt transfer

● 4 double-buffered endpoints for bulk, interrupt and isochronous transfer

● 1KB EP-SRAM used as the endpoint data buffers

▄

Debug Support

● Serial Wire Debug Port – SW-DP

● 4 comparators for hardware breakpoint or code / literal patch

● 2 comparators for hardware watchpoints

▄

Package and Operation Temperature

● 33-pin QFN, 48/64-pin LQFP package

● Operation temperature range: -40 ˚C to +85 ˚C

Introduction

Rev. 1.30 31 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Device Information

Table 1. Series Features and Peripheral List

Peripherals HT32F52342 HT32F52352

Main Flash (KB) 64 127.5

Option Bytes Flash (KB) 0.5 0.5

SRAM (KB) 8 16

Timers

Communication

PDMA 6 channels

EBI 1

CRC-16/32 1

EXTI 16

12-bit ADC
Number of channels

Comparator 2

GPIO Up to 51

CPU frequency Up to 48 MHz

Operating voltage 2.0 V ~ 3.6 V

Operating temperature -40 ˚C ~ +85 ˚C

Package 33-pin QFN, 48/64-pin LQFP

MCTM 1

GPTM 2

SCTM 2

BFTM 2

RTC 1

WDT 1

USB 1

SPI 2

USART 2

UART 2

I2C 2

I2S 1

SCI (ISO7816-3) 2

Introduction

1

12 Channels

Rev. 1.30 32 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Block Diagram

TX, RX
RTS/TXE
CTS/SCK

TX, RX

MCLK, BCLK

WS, SDO, SDI

CH0 ~CH2

CH0N ~ CH2N

CH3, BRK

SCTM

ADC_IN0

ADC_IN11

CN0, CP0

COUT0

CN1, CP1

COUT1

V

DDA

V

SSA

DDA

PA ~ PC[15:0], PD[3:0]

IO Port

GPIO

System

USART0 ~ 1

UART0 ~ 1

UART0

SCTM0 ~ 1

Powered by V

DD15

Bus Matrix

I2S

AFIO

EXTI

MCTM

ADC

CMP

BOOT

AF

Flash Memory

Interface

FMC

PDMA

Control

Control

Registers

Registers

AHB

Peripherals

SRAM

Controller

External Bus

Interafce

AHB to APB

Bridge

APB

CRC

-16/32

Powered by V

Flash

Memory

CKCU/RSTCU

Control Registers

USB

Control/Data

Registers

SRAM

USB

Device

WDT

SPI1 ~ 0

SPI1 ~ 0

I2C0 ~ 1

GPTM0 ~ 1

BFTM0 ~ 1

SCI0 ~ 1

SCI0 ~ 1

RTC

PWRCU

Backup Domain

V

BAK

PORB

BREG

DD15

Clock and reset control

Powered by V

Power control

V

BAK

LSI

32 kHz

LSE

32,768 Hz

AF

X32KIN

X32KOUT

POR

/PDR

HSE

4 ~ 16 MHz

HSI

8 MHz

LDO

1.5 V

BOD

LVD

PLL

f

: 48 MHz

Max

PWRSW

DD

V

DD

V

SS

AF

XTALIN
XTALOUT

CLDO

AD0~AD15

AF

A0~A20
CS0~CS3
OE, WR, ALE

AF

DP
DM

AF

MOSI, MISO
SCK, SEL

AF

SDA
SCL

AF

CH3 ~ CH0

AF

CLK, DIO,
DET

AF AF

RTCOUT

V

BAT

V

DD33

V

SS33

WAKEUP

nRST

Introduction

CAP.

SWCLK SWDIO

AF

SW-DP

Cortex®-M0+

Processor

NVIC

Interrupt request

PDMA

6 Channels

DMA request

AF

AF

AF

AF

...

AFAF

12-bit

SAR ADC

Analog

CMP

Powered by V

Power supply:

Bus:

Control signal:

Alternate funct ion:

AF

Figure 1. Block Diagram

Rev. 1.30 33 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

2

Document Conventions

The conventions used in this document are shown in the following table.

Table 2. Document Conventions

Notation Example Description

0x 0x5a05

0xnnnn_nnnn 0x2000_0100 32-bit Hexadecimal address or data.

b b0101

NAME [n] ADDR [5]

NAME [m:n] ADDR [11:5]

X b10X1 Don’t care notation which means any value is allowed.

RW

RO

RC

WC

W0C

WO

Reserved

SERDYIE

HSIRDY

SERDYF

RO 0 W0C 0

LLRDY

PLLRDYIE

RW 0 RW 0

3 2

HSERDY

RO 1 RO 0

1 0

PDF

BAK_PORF

RC 0 RC 1

3 2

PLLRDYF

WC 0 WC 0

1 0

RXCF

WO 0 WO 0

RO 0

PARF

31 30

DB_CKSRC

1

Reserved

19 18

Word Data length of a word is 32-bit.

Half-word Data length of a half-word is 16-bit.

Byte Data length of a byte is 8-bit.

The number string with a 0x prex indicates a hexadecimal

number.

The number string with a lowercase b prex indicates a binary

number.

Specic bit of NAME. NAME can be a register or eld of register.
For example, ADDR [5] means bit 5 of ADDR register (eld).

Specic bits of NAME. NAME can be a register or eld of

register. For example, ADDR [11:5] means bit 11 to 5 of ADDR

register (eld).

Software can read and write to this bit.

Software can only read this bit. A write operation will have no
effect.

Software can only read this bit. Read operation will clear it to 0
automatically.

Software can read this bit or clear it by writing 1. Writing a 0 will
have no effect.

Software can read this bit or clear it by writing 0. Writing a 1 will
have no effect.

Software can only write to this bit. A read operation always
returns 0.

Reserved bit(s) for future use. Data read from these bits is not

0

well dened and should be treated as random data. Normally

these reserved bits should be set to a 0 value. Note that
reserved bit must be kept at reset value.

Document Conventions

Rev. 1.30 34 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

3

System Architecture

The system architecture of devices that includes the Arm® Cortex®-M0+ processor, bus architecture
and memory organization will be described in the following sections. The Cortex®-M0+ is a next
generation processor core which offers many new features. Integrated and advanced features make
the Cortex®-M0+ processor suitable for market products that require microcontrollers with high
performance and low power consumption. In brief, The Cortex®-M0+ processor includes AHB-Lite
bus interface. All memory accesses of the Cortex®-M0+ processor are executed on the AHB-Lite
bus according to the different purposes and the target memory spaces. The memory organization

uses a Harvard architecture, pre-dened memory map and up to 4 GB of memory space, making
the system exible and extendable.

Arm® Cortex®-M0+ Processor

The Cortex®-M0+ processor is a very low gate count, highly energy efficient processor that is
intended for microcontroller and deeply embedded applications that require an area optimized,

low-power processor. The processor is based on the ARMv6-M architecture and supports Thumb®
instruction sets; single-cycle I/O port; hardware multiplier and low latency interrupt respond time.

Some system peripherals listed below are also provided by Cortex®-M0+:

▄

Internal Bus Matrix connected with AHB-Lite Interface, Single-cycle I/O port and Debug

Accesses Port (DAP)

▄

Nested Vectored Interrupt Controller (NVIC)

▄

Optional Wakeup Interrupt Controller (WIC)

▄

Breakpoint and Watchpoint Unit

▄

Optional Memory Protection Unit (MPU)

▄

Serial Wire debug Port (SW-DP)

▄

Optional Micro Trace Buffer Interface (MTB)

The following gure shows the Cortex®-M0+ processor block diagram. For more information, refer

to the Arm® Cortex®-M0+ Technical Reference Manual.

System Architecture

Rev. 1.30 35 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

®

-M0+

Cortex
Components

Execution Trace Interface

Cortex®-M0+ Processor

Interrupts

‡ Wakeup

Interrupt

Controller (WIC)

‡ Optional Component

Nested

Vectored

Interrupt

Controller

(NVIC)

Figure 2. Cortex®-M0+ Block Diagram

Cortex®-M0+

Processor

Core

‡ Memory
Protection

Unit

Bus Matrix

AHB-Lite Interface

to System

Debug

‡ Breakpoint

and

Watchpoint

Unit

‡ Debugger

Interface

‡ Single-cycle

I/O Port

System Architecture

‡ Debug

Access Port

(DAP)

‡ Serial Wire or

JTAG Debug Port

Bus Architecture

The HT32F52342/52352 series consist of two masters and ve slaves in the bus architecture. The

Cortex®-M0+ AHB-Lite bus and Peripheral Direct Memory Access (PDMA) are the masters while

the internal SRAM access bus, the internal Flash memory access bus, the AHB peripherals access
bus, External Bus Interface (EBI) and the AHB to APB bridges are the slaves. The single 32-bit
AHB-Lite system interface provides simple integration to all system regions include the internal

SRAM region and the peripheral region. All of the master buses are based on 32-bit Advanced

High-performance Bus-Lite (AHB-Lite) protocol. The following gure shows the bus architecture
of the HT32F52342/52352 series.

Rev. 1.30 36 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

GPIO

I/O Port

Cortex®-M0+

Processor

System

NVIC

Interrupt request

PDMA

6 Channels

DMA request

Figure 3. Bus Architecture

Flash Memory

Interface

PDMA

Control

Registers

Bus Matrix

FMC

Control

Registers

AHB

Peripherals

GPIO

A~D

CRC

-16/32

SRAM

Controller

Flash

Memory

CKCU/RSTCU

Control Registers

USB

Control/Data

Registers

SRAM

System Architecture

USB

Device

External Bus

Interafce

AHB to APB

Bridge

APB IPs

Memory Organization

The Arm® Cortex®-M0+ processor accesses and debug accesses share the single external

interface to external AHB peripheral. The processor accesses take priority over debug accesses.

The maximum address range of the Cortex®-M0+ is 4 GB since it has 32-bit bus address width.
Additionally, a pre-defined memory map is provided by the Cortex®-M0+ processor to reduce
the software complexity of repeated implementation of different device vendors. However, some
regions are used by the Arm® Cortex®-M0+ system peripherals. Refer to the Arm® Cortex®-M0+

Technical Reference Manual for more information. The following gure shows the memory map
of HT32F52342/52352 series of devices, including Code, SRAM, peripheral, and other pre-dened

regions.

Rev. 1.30 37 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Memory Map

Peripheral

SRAM

Code

0xFFFF_FFFF

0xE010_0000

0xE000_0000

0x7000_0000

0x6000_0000

0x4010_0000

0x4008_0000

0x4000_0000

0x2000_4000

0x2000_0000

0x1FF0_0400

0x1FF0_0000

0x1F00_1000

0x1F00_0000

0x0001_0000

0x0000_0000

Reserved

Private peripheral bus

Reserved

EBI Selection Bank

Reserved

AHB peripherals

APB peripherals

Reserved

16 KB on-chip SRAM

Reserved

Option byte alias

Reserved

Boot loader

Reserved

Up to

128 KB on-chip Flash

64 MB x 4

512 KB

512 KB

16 KB

1 KB

4 KB

Up to
128 KB

0x400F_FFFF

0x400B_8000

0x400B_0000

0x400A_C000

0x400A_8000

0x4009_8000

0x4009_2000

0x4008_C000

0x4007_8000

0x4007_7000
0x4007_6000

0x4007_5000

0x4007_4000

0x4007_0000

0x4006_F000
0x4006_E000

0x4006_B000

0x4006_A000

0x4006_9000

0x4006_8000

0x4005_9000

0x4005_8000

0x4004_A000

0x4004_9000

0x4004_8000

0x4004_5000

0x4004_4000

0x4004_3000

0x4004_2000

0x4004_1000

0x4004_0000

0x4003_B000

0x4003_A000

0x4003_5000

0x4003_4000

0x4002_D000

0x4002_C000

0x4002_7000

0x4002_6000

0x4002_5000

0x4002_4000

0x4002_3000

0x4002_2000

0x4001_1000

0x4001_0000

0x4000_5000

0x4000_4000

0x4000_2000

0x4000_1000

0x4000_0000

Reserved

GPIO A ～ D

Reserved

USB SRAM0x400A_A000

USB

Reserved0x4009_A000

EBI

Reserved

PDMA0x4009_0000

Reserved

CRC0x4008_A000

CKCU/RSTCU0x4008_8000

Reserved0x4008_2000

FMC0x4008_0000

Reserved

BFTM1
BFTM0

Reserved

SCTM1

Reserved

GPTM1
GPTM0

Reserved

RTC & PWRCU

Reserved

WDT

Reserved

CMP

Reserved

I2C1
I2C0

Reserved

SPI1
SCI0

Reserved

UART1

USART1

Reserved

SCI1

Reserved

SCTM0

Reserved

MCTM

Reserved

I2S

Reserved

EXTI

Reserved

AFIO

Reserved

ADC

Reserved

SPI0

Reserved

UART0

USART0

System Architecture

AHB

APB

Figure 4. Memory Map

Rev. 1.30 38 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Table 3. Register Map

Start Address End Address Peripheral Bus

0x4000_0000 0x4000_0FFF USART0

0x4000_1000 0x4000_1FFF UART0

0x4000_2000 0x4000_3FFF Reserved

0x4000_4000 0x4000_4FFF SPI0

0x4000_5000 0x4000_FFFF Reserved

0x4001_0000 0x4001_0FFF ADC

0x4001_1000 0x4002_1FFF Reserved

0x4002_2000 0x4002_2FFF AFIO

0x4002_3000 0x4002_3FFF Reserved

0x4002_4000 0x4002_4FFF EXTI

0x4002_5000 0x4002_5FFF Reserved

0x4002_6000 0x4002_6FFF I2S

0x4002_7000 0x4002_BFFF Reserved

0x4002_C000 0x4002_CFFF MCTM

0x4002_D000 0x4003_3FFF Reserved

0x4003_4000 0x4003_4FFF SCTM0

0x4003_5000 0x4003_9FFF Reserved

0x4003_A000 0x4003_AFFF SCI1

0x4003_B000 0x4003_FFFF Reserved

0x4004_0000 0x4004_0FFF USART1

0x4004_1000 0x4004_1FFF UART1

0x4004_2000 0x4004_2FFF Reserved

0x4004_3000 0x4004_3FFF SCI0

0x4004_4000 0x4004_4FFF SPI1

0x4004_5000 0x4004_7FFF Reserved

0x4004_8000 0x4004_8FFF I2C0

0x4004_9000 0x4004_9FFF I2C1

0x4004_A000 0x4005_7FFF Reserved

0x4005_8000 0x4005_8FFF Comparator

0x4005_9000 0x4006_7FFF Reserved

0x4006_8000 0x4006_8FFF WDT

0x4006_9000 0x4006_9FFF Reserved

0x4006_A000 0x4006_AFFF RTC/PWRCU

0x4006_B000 0x4006_DFFF Reserved

0x4006_E000 0x4006_EFFF GPTM0

0x4006_F000 0x4006_FFFF GPTM1

0x4007_0000 0x4007_3FFF Reserved

0x4007_4000 0x4007_4FFF SCTM1

0x4007_5000 0x4007_5FFF Reserved

0x4007_6000 0x4007_6FFF BFTM0

0x4007_7000 0x4007_7FFF BFTM1

0x4007_8000 0x4007_FFFF Reserved

System Architecture

APB

Rev. 1.30 39 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Start Address End Address Peripheral Bus

0x4008_0000 0x4008_1FFF FMC

0x4008_2000 0x4008_7FFF Reserved

0x4008_8000 0x4008_9FFF CKCU/RSTCU

0x4008_A000 0x4008_BFFF CRC

0x4008_C000 0x4008_FFFF Reserved

0x4009_0000 0x4009_1FFF

0x4009_2000 0x4009_7FFF Reserved

0x4009_8000 0x4009_9FFF EBI Control Registers

0x4009_A000 0x400A_7FFF Reserved

0x400A_8000 0x400A_BFFF USB

0x400A_C000 0x400A_FFFF Reserved

0x400B_0000 0x400B_1FFF GPIOA

0x400B_2000 0x400B_3FFF GPIOB

0x400B_4000 0x400B_5FFF GPIOC

0x400B_6000 0x400B_7FFF GPIOD

0x400B_8000 0x400F_FFFF Reserved

PDMA Control
Registers

System Architecture

AHB

Rev. 1.30 40 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Embedded Flash Memory

The HT32F52342/52352 series provide up to 128 KB on-chip Flash memory which is located

at address 0x0000_0000. It supports byte, half-word, and word access operations. Note that the
Flash memory only supports read operations for the bus access. Any write operations to the Flash

memory will cause a bus fault exception. The Flash memory has up to capacity of 128 pages. Each
page has a memory capacity of 1 KB and can be erased independently. A 32-bit programming
interface provides the capability of changing bits from 1 to 0. A data storage or rmware upgrade

can be implemented using several methods such as In System Programming (ISP), In Application
Programming (IAP) or In Circuit Programming (ICP). For more information, refer to the Flash
Memory Controller section.

Embedded SRAM Memory

The HT32F52342/52352 series contain up to 16 KB on-chip SRAM which is located at address

0x2000_0000. It support byte, half-word and word access operations.

AHB Peripherals

The address of the AHB peripherals ranges from 0x4008_0000 to 0x400F_FFFF. Some peripherals

such as Clock Control Unit, Reset Control Unit and Flash Memory Controller are connected to the

AHB bus directly. The AHB peripherals clocks are always enabled after a system reset. Access to
registers for these peripherals can be achieved directly via the AHB bus. Note that all peripheral
registers in the AHB bus support only word access.

System Architecture

APB Peripherals

The address of APB peripherals ranges from 0x4000_0000 to 0x4007_FFFF. An APB to AHB
Bridge provides access capability between the CPU and the APB peripherals. Additionally, the
APB peripheral clocks are disabled after a system reset. Software must enable the peripheral clock
by setting up the APBCCRn register in the Clock Control Unit before accessing the corresponding
peripheral register. Note that the APB to AHB Bridge will duplicate the half-word or byte data to
word width when a half-word or byte access is performed on the APB peripheral registers. In other
words, the access result of a half-word or byte access on the APB peripheral register will vary

depending on the data bit width of the access operation on the peripheral registers.

Rev. 1.30 41 of 656 September 28, 2018

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HT32F52342/HT32F52352

4

Flash Memory Controller (FMC)

Introduction

The Flash Memory Controller (FMC) provides functions of ash operation and pre-fetch buffer

for the embedded on-chip Flash memory. Figure below shows the block diagram of FMC which
includes programming interface, control register, pre-fetch buffer, and access interface. Since the
access speed of Flash memory is slower than the CPU, a wide access interface with pre-fetch buffer
is provided to the Flash memory in order to reduce the wait state (which will cause instruction

gaps) of the CPU. The functions of word program/page erase are also provided for instruction/data

storage of Flash memory.

Peripheral Bus

AHB

System Bus

Flash Memory Controller

Control Register

Pre-fetch Buffer

Wait State

Control

Addressing

Data

Programming

Control

Flash Memory Controller (FMC)

Flash

Information

Block

Main Flash

Memory

Figure 5. Flash Memory Controller Block Diagram

Features

▄

Up to 128 KB of on-chip Flash memory for storing instruction/data and options

● 128 KB (instruction/data + Option Byte)

● 64 KB (instruction/data + Option Byte)

▄

Page size of 512 Bytes, totally up to 256 pages depending on the main Flash size

▄

Wide access interface with pre-fetch buffer to reduce instruction gaps

▄

Page erase and mass erase capability

▄

32-bit word programming

▄

Interrupt capability when ready or error occurs

▄

Flash read protection to prevent illegal code/data access

▄

Page erase/program protection to prevent unexpected operation

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HT32F52342/HT32F52352

Functional Descriptions

Flash Memory Map

The following figure is the Flash memory map of the system. The address ranges from

0x0000_0000 to 0x1FFF_FFFF (0.5 GB). The address from 0x1F00_0000 to 0x1F00_0FFF is
mapped to Boot Loader Block (4 KB). Besides, address 0x1FF0_0000 to 0x1FF0_01FF is the alias
of Option Byte block (0.5 KB) which locates at the last page of main Flash physically. The memory

mapping on system view is shown as below.

0x1FFF_FFFF

0x1FF0_0200

0x1FF0_0000

0x1F00_1000

Reserved

Option Byte

Reserved

Flash Memory Controller (FMC)

0.5 Kbytes

0x1F00_0000

0x0000_0000

Figure 6. Flash Memory Map

Boot Loader Block

Reserved

Main Flash Block

User Application

4 Kbytes

127.5 Kbytes

or

64 Kbytes

Rev. 1.30 43 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
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Flash Memory Architecture

The Flash memory consists of up to 128 KB main Flash with 512 Bytes per page and 4 KB
Information Block for Boot Loader. The main Flash memory contains totally 256 pages (or 128
pages for 64 KB device) which can be erased individually. The following table shows the base

address, size, and protection setting bit of each page.

Table 4. Flash Memory and Option Byte

Block Name Address Page Protection Bit Size

Page 0 0x0000_0000 ~ 0x0000_01FF

Page 1 0x0000_0200 ~ 0x0000_03FF 512 Bytes

Page 2 0x0000_0400 ~ 0x0000_05FF

Page 3 0x0000_0600 ~ 0x0000_07FF 512 Bytes

........

Main Flash
Block

Page 252 0x0001_F800 ~ 0x0001_F9FF

Page 253 0x0001_FA00 ~ 0x0001_FBFF 512 Bytes

Page 254 0x0001_FC00 ~ 0x0001_FDFF OB_PP [127] 512 Bytes

Page 255
(Option Byte)

Information Block Boot Loader 0x1F00_0000 ~ 0x1F00_0FFF NA 4 KB

Notes:

1. Information Block stores boot loader, this block can not be programmed or erased by user.

2. Option Byte is always located at last page of main Flash block.

Physical: 0x0001_FE00 ~ 0x0001_FFFF
Alias: 0x1FF0_0000 ~ 0x1FF0_01FF

........

OB_PP [0]

OB_PP [1]

........

OB_PP [126]

OB_CP [1] 512 Bytes

512 Bytes

512 Bytes

512 Bytes

Flash Memory Controller (FMC)

........

Wait State Setting

When the HCLK clock is greater than access speed of Flash memory, the wait state cycles must be

inserted during the CPU fetch instructions or load data from Flash memory. The wait state can be
changed by setting WAIT [2:0] of Flash Cache and Pre-fetch Control Register (CFCR). In order to

t the requirement of wait state, the following two rules shall be considered.

▄

HCLK clock is changed from lower to higher: Change the wait state setting rst and then change
the HCLK clock.

▄

HCLK clock is changed from higher to lower: Change the HCLK clock rst and then change the

wait state setting.

The following table shows the relationship between the wait state cycle and HCLK. The default
wait state is 0 since the HSI (8 MHz) is selected as HCLK clock source after system reset.

Table 5. Relationship Between Wait State Cycle and HCLK

Wait State Cycle HCLK

0 0 MHz < HCLK <= 24 MHz

1 24 MHz < HCLK <= 48 MHz

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32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Booting Conguration

The system provides two kinds of booting mode which can be selected through BOOT pin. The
value of BOOT pin is sampled during the power-on reset or system reset. Once the value is decided,
the rst 4 words of vector will be remapped to the corresponding source according to the booting

mode. The booting mode is shown in the following table.

Table 6. Booting Modes

Booting mode selection pin

BOOT

0 Boot Loader The source of Vector is Boot Loader

1 Main Flash The source of Vector is main Flash

The Vector Mapping Control Register (VMCR) is provided to change the setting of the vector
remapping temporarily after the chip reset. The reset value of VMCR is determined by the value of

BOOT pin which will be sampled during the reset.

Mode Descriptions

Flash Memory Controller (FMC)

Boot Setting

0xC

Hard Fault Handler

0x8

0x4

NMI Handler

Program Counter

Initial Stack Point0x0

Figure 7. Vector Remapping

1 : Main Flash 0 : Boot Loader

+ 0xC

+ 0x8

+ 0x4

0x0000 0000

+ 0xC

+ 0x8

+ 0x4

0x1F00 0000

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Page Erase

The FMC provides a page erase function which is used to reset partial content of Flash memory.
Any page can be erased independently without affecting others. The following steps show the
access sequence of the register for page erase.

▄

Check the OPCR register to conrm that no Flash memory operation is in progress (OPM [3:0]
equals to 0xE or 0x6). Otherwise, wait until the previous operation has been nished.

▄

Write the page address to TADR register

▄

Write page erase command to OCMR register (CMD [3:0] = 0x8).

▄

Commit page erase command to FMC by setting OPCR register (set OPM [3:0] = 0xA).

▄

Wait until all the operations have been completed by checking the value of OPCR register (OPM
[3:0] equals to 0xE).

▄

Read and verify the page if required.

Note that a correct address of the target page must be conrmed. Software may run away if the

target erase page is being used for fetching code or accessing data and FMC will not notify when

this happens. Besides, the page erase will be ignored on the protected pages. A Flash Operation

Error interrupt will be triggered by FMC if the OREIEN bit in the OIER register is set. Software
can check the PPEF bit in the OISR register to detect this condition in the interrupt handler. The

following gure displays the ow of page erase operation.

Flash Memory Controller (FMC)

No

No

Start

Is OPM equal to 0xE or 0x6 ?

Yes

Set TADR, OCMR

Commit command

by setting OPCR

Is OPM equal to 0xE ?

Yes

Finish

Figure 8. Page Erase Operation Flowchart

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32-Bit Arm® Cortex®-M0+ MCU
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Mass Erase

The FMC provides a complete erase function which is used for resetting all the main Flash memory
content. The following steps show the sequence of the register access for mass erase.

▄

Check the OPCR register to conrm that no Flash memory operation is in progress (OPM [3:0]
equals to 0xE or 0x6). Otherwise, wait until the previous operation has been nished.

▄

Write mass erase command to OCMR register (CMD [3:0] = 0xA).

▄

Commit mass erase command to FMC by setting OPCR register (set OPM [3:0] = 0xA).

▄

Wait until all operations have been nished by checking the value of OPCR register (OPM [3:0]

equals to 0xE).

▄

Read and verify the Flash memory if required.

Since all Flash data will be reset as 0xFFFF_FFFF, the mass erase operation can be done by the
program that runs in the SRAM or by the debugging tool that access FMC register directly. The
software function that is executed on the Flash memory shall not trigger a mass erase operation.

The following gure displays the ow of mass erase operation.

Flash Memory Controller (FMC)

No

No

Start

Is OPM equal to 0xE or 0x6 ?

Yes

Set OCMR = 0xA

Commit command

by setting OPCR

Is OPM equal to 0xE ?

Yes

Finish

Figure 9. Mass Erase Operation Flowchart

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32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Word Programming

The FMC provides a 32 bits word programming function which is used for modifying the Flash
memory content. The following steps show the sequence of register access for word programming.

▄

Check the OPCR register to conrm that no Flash memory operation is in progress (OPM [3:0]
equals to 0xE, or 0x6). Otherwise, wait until the previous operation has been nished.

▄

Write word address to TADR register. Write data to WRDR register.

▄

Write word program command to OCMR register (CMD [3:0] = 0x4).

▄

Commit word program command to FMC by setting OPCR register (set OPM [3:0] = 0xA).

▄

Wait until all operations have been nished by checking the value of OPCR register (OPM [3:0]

equals to 0xE).

▄

Read and verify the Flash memory if required.

Note that the word programming operation can not be applied to the same address twice.
Successive word programming operation to the same address must be separated by a page erase

operation. Besides, the word program will be ignored on protected pages. A Flash operation

error interrupt will be triggered by FMC if the OREIEN bit in the OIER register is set. Software
can check the PPEF bit in the OISR register to detect this condition in the interrupt handler. The

following gure displays the ow of word programming operation.

Flash Memory Controller (FMC)

No

No

Start

Is OPM equal to 0xE or 0x6 ?

Yes

Set TADR, WRDR

and OCMR

Commit command

by setting OPCR

Is OPM equal to 0xE ?

Yes

Finish

Figure 10. Word Programming Operation Flowchart

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32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Option Byte Description

The Option Byte can be treated as an independent Flash memory which base address is
0x1FF0_0000. The following table shows the function description and memory map of Option
Byte.

Table 7. Option Byte Memory Map

Option Byte Offset Description Reset Value

Option Byte Base Address = 0x1FF0_0000

0x000

OB_PP

OB_CP 0x010

OB_CK 0x020

0x004
0x008
0x00C

Flash Page Erase/Program Protection (page 254 ~ page 0)
OB_PP [n] (n = 0 ~ 127)

0: Flash Page 2n and 2n+1 Erase/Program Protection is

enabled

1: Flash Page 2n and 2n+1 Erase/Program Protection is

disabled

Flash Security Protection
OB_CP [0]

0: Flash Security protection is enabled

1: Flash Security protection is disabled
Option Byte Protection
OB_CP [1]

0: Option Byte protection is enabled

1: Option Byte protection is disabled
OB_CP [31:2]

Reserved

Flash Option Byte Checksum
OB_CK [31:0]
OB_CK should be set as the content value sum of 5
registers which offset address is form 0x000 to 0x010 in
Option Byte (0x000 + 0x004 + 0x008 + 0x00C + 0x010)
when the OB_PP or OB_CP register’s content is not equal
to 0xFFFF_FFFF. Otherwise, both page erase/program
protection and security protection will be enabled.

Flash Memory Controller (FMC)

0xFFFF_FFFF
0xFFFF_FFFF
0xFFFF_FFFF
0xFFFF_FFFF

0xFFFF_FFFF

0xFFFF_FFFF

Page Erase/Program Protection

FMC provides functions of page erase/program protection to prevent unexpected operation of Flash

memory. The page erase (CMD [3:0] = 0x8 in the OCMR register) or word program (CMD [3:0]
= 0x4) command will not be accepted by FMC on the protected pages, the PPEF bit in the OISR
register will then be set by FMC and the Flash operation error interrupt will be triggered to CPU
by FMC if the OREIEN bit in the OIER register is set. The page protection function can be enabled

for each page independently by setting the OB_PP registers of the Option Byte. The following table

shows the access permission of the main Flash page when the page protection is enabled.

Rev. 1.30 49 of 656 September 28, 2018

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HT32F52342/HT32F52352

Table 8. Access Permission of Protected Main Flash Page

Mode

Operation

Read O O

Program X X

Page Erase X X

Mass Erase O O

Notes:

1. Note that the setting of write protection is based on page. The above access permission
only affects the pages that enable protection function. Other pages are not affected.

2. Main Flash page protection is configured by OB_PP [126:0]. Option Byte is physically

located at the last page of main Flash. Option Byte page protection is congured by the

OB_CP [1] bit.

3. The page erase on Option Byte area can disable the page protection of main Flash.

4. The page protection of Option Byte can only be disabled by a mass erase operation.

The following steps show the register access sequence for page erase/program protection

procedure.

▄

Check the OPCR register to conrm that no Flash memory operation is in progress (OPM [3:0]
equals to 0xE or 0x6). Otherwise, wait until the previous operation has been nished.

▄

Write OB_PP address to TADR register (TADR = 0x1FF0_0000).

▄

Write WRDR register which indicates the protection function of corresponding page is enabled

or disabled (0: Enabled, 1: Disabled).

▄

Write word program command to OCMR register (CMD [3:0] = 0x4).

▄

Commit word program command to FMC by setting OPCR register (set OPM [3:0] = 0xA).

▄

Wait until all operations have been nished by checking the value of OPCR register (OPM [3:0]

equals to 0xE).

▄

Read and verify the Option Byte if required.

▄

Program the OB_CK Option Byte as sum of 5 words 0x000 ~ 0x010 according to the checksum
rule of Option Byte.

▄

Apply a system reset to active the new OB_PP setting.

ISP/IAP ICP/Debug Mode

Flash Memory Controller (FMC)

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HT32F52342/HT32F52352

Security Protection

FMC provides function of Security protection to prevent illegal code/data access of Flash memory.
This function is useful for protecting the software / rmware from the illegal users. The function is
activated by setting the Option Byte OB_CP [0]. Once the function has been enabled, all the main
Flash data access through ICP/Debug mode, programming, and page erase will not be allowed
except the user’s application. But the mass erase operation will still be accepted by FMC in order to

disable this function. The following table shows the access permission of Flash memory when the
security protection is enabled.

Table 9. Access Permission When Security Protection is Enabled

Mode

Operation

Read O X (read as 0)

Program O

Page Erase O

Mass Erase O O

Notes:

1. User application means the software that is executed or booted from main Flash memory
with the JTAG/SW debugger being disconnected. But Option Byte block and page 0 are
still in protection and can not Program/Page Erase.

2. Mass erase operation can erase Option Byte block and disable security protection.

User Application

(Note 1)

(Note 1)

(Note 1)

Flash Memory Controller (FMC)

ICP/Debug Mode

X

X

The following steps show the register access sequence for Security protection procedure.

▄

Check OPCR register to conrm that no Flash memory operation is ongoing (OPM [3:0] equal to
0xE or 0x6). Otherwise, wait until the previous operation has been nished.

▄

Write OB_CP address to TADR register (TADR = 0x1FF0_0010).

▄

Write WRDR register, set OB_CP [0] as 0.

▄

Write word program command to OCMR register (CMD [3:0] = 0x4).

▄

Commit word program command to FMC by setting OPCR register (set OPM = 0xA).

▄

Wait until all operations have been nished by checking the value of OPCR register (OPM [3:0]

equals to 0xE).

▄

Read and verify the Option Byte if required.

▄

Program the OB_CK Option Byte as sum of 5 words 0x000 ~ 0x010 according to the checksum
rule of Option Byte.

▄

Apply a system reset to active the new OB_CP setting.

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HT32F52342/HT32F52352

Register Map

The following table shows the FMC registers and reset values.

Table 10. FMC Register Map

Register Offset Description Reset Value

FMC Base Address = 0x4008_0000

TADR 0x000 Flash Target Address Register 0x0000_0000

WRDR 0x004 Flash Write Data Register 0x0000_0000

OCMR 0x00C Flash Operation Command Register 0x0000_0000

OPCR 0x010 Flash Operation Control Register 0x0000_000C

OIER 0x014 Flash Operation Interrupt Enable Register 0x0000_0000

OISR 0x018 Flash Operation Interrupt and Status Register 0x0001_0000

0x020

PPSR

CPSR 0x030 Flash Security Protection Status Register 0xXXXX_XXXX

VMCR 0x100 Flash Vector Mapping Control Register 0x0000_000X

MDID 0x180 Flash Manufacturer and Device ID Register 0x0376_XXXX

PNSR 0x184 Flash Page Number Status Register 0x0000_00X0

PSSR 0x188 Flash Page Size Status Register 0x0000_0200

CFCR 0x200 Flash Cache & Pre-fetch Control Register 0x0000_0051

CIDR0 0x310 Custom ID Register 0 0xXXXX_XXXX

CIDR1 0x314 Custom ID Register 1 0xXXXX_XXXX

CIDR2 0x318 Custom ID Register 2 0xXXXX_XXXX

CIDR3 0x31C Custom ID Register 3 0xXXXX_XXXX

0x024
0x028
0x02C

Flash Page Erase/Program Protection Status Register

Flash Memory Controller (FMC)

0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX

Note:

“X” means various reset values which depend on the Device, Flash value, option byte value, or

power on reset setting.

Rev. 1.30 52 of 656 September 28, 2018

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HT32F52342/HT32F52352

Register Descriptions

Flash Target Address Register – TADR

This register species the target address of page erase and word programming operation.

offset: 0x000

Reset value: 0x0000_0000

31 30 29 28 27 26 25 24

TADB

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

23 22 21 20 19 18 17 16

TADB

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

15 14 13 12 11 10 9 8

TADB

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

7 6 5 4 3 2 1 0

TADB

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

Bits Field Descriptions

[31:0] TADB Flash Target Address Bits

For programming operations, the TADR register species the address where the

data is written. Since the programming length is 32 bits, the TADR shall be set
as word-aligned (4 bytes). The TADB [1:0] will be ignored during programming
operations. For page erase operations, the TADR register contains the page
address which is going to be erased. Since the page size is 512 Byte, the TADB
[8:0] will be ignored in order to limit the target address as 512 Byte-aligned. For
128 KB main Flash addressing, TADB [31:17] should be zero and TADB [31:16]
should be zero for 64 KB. Address from 0x1FF0_0000 to 0x1FF0_03FF is the 1KB

Option Byte. This eld for available Flash address, it must be under 0x1FFF_FFFF.

Otherwise, the Invalid Target Address interrupt will be occurred if the corresponding
interrupt enable bit is set.

Flash Memory Controller (FMC)

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Flash Write Data Register – WRDR

This register species the data to be written for programming operation.

offset: 0x004

Reset value: 0x0000_0000

31 30 29 28 27 26 25 24

WRDB

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

23 22 21 20 19 18 17 16

WRDB

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

15 14 13 12 11 10 9 8

WRDB

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

7 6 5 4 3 2 1 0

WRDB

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

Flash Memory Controller (FMC)

Bits Field Descriptions

[31:0] WRDB Flash Write Data Bits

The data value for programming operation.

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Flash Operation Command Register – OCMR

This register is used to specify the Flash operation commands that include read, read ID, word program, page
erase and mass erase.

Offset: 0x00C

Reset value: 0x0000_0000

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved CMD

Type/Reset RW 0 RW 0 RW 0 RW 0

Bits Field Descriptions

[3:0] CMD Flash Operation Command

The following table shows definitions of CMD [3:0] which specify the Flash
operation. If an invalid command is set and IOCMIEN = 1, the Invalid Operation
Command interrupt will be occurred.

CMD [3:0] Description

0x0 Idle (default)

0x4 Word program

0x8 Page erase

0xA Mass erase

Others Reserved

Flash Memory Controller (FMC)

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Flash Operation Control Register – OPCR

This register is used for controlling the command commitment and checking the status of the FMC operations.

Offset: 0x010

Reset value: 0x0000_000C

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved OPM Reserved

Type/Reset RW 0 RW 1 RW 1 RW 0

Flash Memory Controller (FMC)

Bits Field Descriptions

[4:1] OPM Operation Mode

The following table shows the operation mode of FMC. User can commit command
which is set by the OCMR register to main flash according to the address alias
setting in TADR. The content of TADR, WRDR, and OCMR registers shall be

prepared before setting this register. After all the operation has been nished, the
OPM eld will be set as 0xE or 0xF by the FMC hardware. The Idle mode can be

set when all the operations have been finished for power saving. Note that the
operation status should be checked before the next action is applied to the FMC.
The content of TADR, WRDR, OCMR, and OPCR registers should not be changed

until the previous operation has been nished.

OPM [3:0] Description

0x6 Idle (default)

0xA Commit command to main Flash

0xE All operation nished on main Flash

Others Reserved

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Flash Operation Interrupt Enable Register – OIER

This register is used to enable or disable interrupt function of FMC. The FMC generates interrupt to the controller
when corresponding interrupt enable bits are set.

Offset: 0x014

Reset value: 0x0000_0000

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved OREIEN IOCMIEN OBEIEN ITADIEN ORFIEN

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0

Bits Field Descriptions

[4] OREIEN Operation Error Interrupt Enable

0: Operation error does not generate an interrupt
1: Operation error generates an interrupt

[3] IOCMIEN Invalid Operation Command Interrupt Enable

0: Invalid Operation Command does not generate an interrupt
1: Invalid Operation Command generates an interrupt

[2] OBEIEN Option Byte Check Sum Error Interrupt Enable

0: Option Byte Check Sum Error does not generate an interrupt
1: Option Byte Check Sum Error generates an interrupt

[1] ITADIEN Invalid Target Address Interrupt Enable

0: Invalid Target Address does not generate an interrupt
1: Invalid Target Address generates an interrupt

[0] ORFIEN Operation Finished Interrupt Enable

0: Operation Finish does not generate an interrupt
1: Operation Finish generates an interrupt

Flash Memory Controller (FMC)

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Flash Operation Interrupt and Status Register – OISR

This register indicates the status of the FMC interrupt to check if an operation has been nished or an error

occurs. The status bits (bit [4:0]) are available when the corresponding bits in the OIER register are set.

Offset: 0x018

Reset value: 0x0001_0000

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved PPEF RORFF

Type/Reset RO 0 RO 1

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved OREF IOCMF OBEF ITADF ORFF

Type/Reset WC 0 WC 0 WC 0 WC 0 WC 0

Bits Field Descriptions

[17] PPEF Page Erase/Program Protected Error Flag

0: Page Erase/Program Protected Error is not occurred
1: Operation error since an invalid erase/program operation is applied to a

protected page

This bit is reset by hardware once a new ash operation command is committed.

[16] RORFF Raw Operation Finished Flag

0: The last ash operation command is not nished
1: The last ash operation command is nished

RORFF is directly connected from Flash memory for debugging purpose.

[4] OREF Operation Error Flag

0: No ash operation error occurred
1: The last ash operation is failed

This bit will be set when any error of flash operation such as invalid command,
program error and erase error, etc. is occurred. The ORE interrupt occurs if the
OREIEN bit in the OIER register is set. Reset this bit by writing 1.

[3] IOCMF Invalid Operation Command Flag

0: No invalid ash operation command was set
1: An invalid ash operation command is set into the OCMR register.

The IOCM interrupt will be occurred if the IOCMIEN bit in the OIER register is set.
Reset this bit by writing 1.

[2] OBEF Option Byte Check Sum Error Flag

0: Check sum of Option Byte is correct
1: Check sum of Option Byte is incorrect

The OBE interrupt will be occurred if the OBEIEN bit in the OIER register is set. But
the Option Byte Check Sum Error Flag has to wait the interrupt condition is cleared
then reset this bit by software writes 1 , that means the Option Byte check sum

value has to modied to correct. Otherwise, the interrupt will be continually kept or

the software disables the interrupt enable bit to release the interrupt request.

Flash Memory Controller (FMC)

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Bits Field Descriptions

[1] ITADF Invalid Target Address Flag

0: The target address is valid
1: The target address TADR is invalid

TADR eld must be below 0x1FFF_FFFF. The ITAD interrupt will be occurred if the

ITADIEN bit in the OIER register is set. Reset this bit by writing 1.

[0] ORFF Operation Finished Flag

0: No operation nished interrupt occurred
1: Last ash operation command is nished

The ORF interrupt will be occurred if the ORFIEN bit in the OIER register is set.
Reset this bit by writing 1.

Flash Memory Controller (FMC)

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Flash Page Erase/Program Protection Status Register – PPSR

This register indicates the status of Flash page erase/program protection.

Offset: 0x020 (0) ~ 0x02C (3)

Reset value: 0xXXXX_XXXX

31 30 29 28 27 26 25 24

PPSBn

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

23 22 21 20 19 18 17 16

PPSBn

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

15 14 13 12 11 10 9 8

PPSBn

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

7 6 5 4 3 2 1 0

PPSBn

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

Flash Memory Controller (FMC)

Bits Field Descriptions

[127:0] PPSBn Page Erase/Program Protection Status Bits (n = 0 ~ 127)

PPSB[n] = OB_PP[n]

0: The corresponding pages are protected
1: The corresponding pages are not protected

The content of this register is not dynamically updated and will only be reloaded
from the Option Byte when any kind of reset occurs. The erase or program function

of specic pages is not allowed when the corresponding bits of the PPSR registers

are reset. The reset value of PPSR [127:0] is determined by the Option Byte OB_
PP [127:0]. Since the maximum page number of the main flash is various and
dependent on the chip specification. Therefore, the every page erase/program
protection status bit may protect one or two pages and dependent on the chip

specication. The other remained bits of OB_PP and PPSR registers are reserved.

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Flash Security Protection Status Register – CPSR

This register indicates the status of the Flash Security protection. The content of this register is not dynamically
updated and will only be reloaded by the Option Byte loader (which is active when any kind of reset occurs).

Offset: 0x030

Reset value: 0xXXXX_XXXX

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved OBPSB CPSB

Type/Reset RO X RO X

Bits Field Descriptions

[1] OBPSB Option Byte Page Erase/Program Protection Status Bit

0: The Option Byte page is protected.
1: The Option Byte page is not protected.

The reset value of OPBSB is determined by the Option Byte, OB_CP [1].

[0] CPSB Flash Security Protection Status Bit

0: Flash Security protection is enabled
1: Flash Security protection is not enabled

The reset value of CPSB is determined by the Option Byte, OB_CP [0].

Flash Memory Controller (FMC)

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Flash Vector Mapping Control Register – VMCR

This register is used to control the mapping of vector. The reset value of VMCR is determined by booting power
on the reset setting BOOT pin.

Offset: 0x100

Reset value: 0x0000_000X

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved VMCB Reserved

Type/Reset RW X 1

Bits Field Descriptions

[1] VMCB Vector Mapping Control Bit

The VMCB bits is used to control the mapping source of first 4-word vector
(address 0x0 ~ 0xC). The following table shows the vector mapping setting.

BOOT VMCB [1] Descriptions

Low 0

High 1

The reset value of VMCB is determined by the pins status of BOOT during power
on reset and system reset. The setting of the vector mapping can be changed
temporarily by setting the VMCB bit when the application is running.

Boot Loader mode
The source of the vector mapping is the boot loader area.

Main Flash mode
The source of the vector mapping is the main Flash area.

Flash Memory Controller (FMC)

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Flash Manufacturer and Device ID Register – MDID

This register species the manufacture ID and device part number information which can be used as the product

identity.

Offset: 0x180

Reset value: 0x0376_XXXX

31 30 29 28 27 26 25 24

MFID

Type/Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1

23 22 21 20 19 18 17 16

MFID

Type/Reset RO 0 RO 1 RO 1 RO 1 RO 0 RO 1 RO 1 RO 0

15 14 13 12 11 10 9 8

ChipID

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

7 6 5 4 3 2 1 0

ChipID

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

Bits Field Descriptions

[31:16] MFID Manufacturer ID

Read as 0x0376

[15:0] ChipID Chip ID

Read the last 4 digital codes of the MCU device part number.

Flash Memory Controller (FMC)

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Flash Page Number Status Register – PNSR

This register species the page number of Flash memory.

Offset: 0x184

Reset value: 0x0000_00XX

31 30 29 28 27 26 25 24

PNSB

Type/Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0

23 22 21 20 19 18 17 16

PNSB

Type/Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0

15 14 13 12 11 10 9 8

PNSB

Type/Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0

7 6 5 4 3 2 1 0

PNSB

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

Flash Memory Controller (FMC)

Bits Field Descriptions

[31:0] PNSB Flash Page Number Status Bits

0x0000_0010: Totally 16 pages for the on-chip Flash memory device.
0x0000_0020: Totally 32 pages for the on-chip Flash memory device.
0x0000_0040: Totally 64 pages for the on-chip Flash memory device.
0x0000_0080: Totally 128 pages for the on-chip Flash memory device.
0x0000_00FF: Totally 255 pages for the on-chip Flash memory device.

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Flash Page Size Status Register – PSSR

This register species the page size in bytes.

Offset: 0x188

Reset value: 0x0000_0200

31 30 29 28 27 26 25 24

PSSB

Type/Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0

23 22 21 20 19 18 17 16

PSSB

Type/Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0

15 14 13 12 11 10 9 8

PSSB

Type/Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0

7 6 5 4 3 2 1 0

PSSB

Type/Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0

Flash Memory Controller (FMC)

Bits Field Descriptions

[31:0] PSSB Status Bits of Flash Page Size

0x200: That means the page size is 512 Byte per page.
0x400: That means the page size is 1 KB per page.
0x800: That means the page size is 2 KB per page.

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Flash Cache & Pre-fetch Control Register – CFCR

This register is used for controlling the pre-fetch module of FMC.

Offset: 0x200

Reset value: 0x0000_13D1

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

Reserved CE Reserved

Type/Reset RW 1 0 0 1 1

7 6 5 4 3 2 1 0

Reserved PFBE Reserved WAIT

Type/Reset 1 1 0 RW 1 RW 0 RW 0 RW 1

Flash Memory Controller (FMC)

Bits Field Descriptions

[12] CE Branch Cache Enable Bit

0 = Cache is disabled.
1 = Cache is enabled (default).

[4] PFBE Pre-fetch Buffer Enable Bit

0: Pre-fetch buffer is disabled. The Instruction/Data is provided by Flash

memory directly.

1: Pre-fetch buffer is enabled (default).

[2:0] WAIT Flash Wait State Setting

The WAIT [2:0] is used to set the count of the HCLK wait clock during non­sequential address Flash access. The actual wait clock is (WAIT [2:0] - 1). Since
the wide access interface with pre-fetch buffer is provided, the wait state of
sequential Flash access is very close to zero.

WAIT [2:0] Wait Status Allowed HCLK Range

001 0 0 MHz < HCLK ≤ 24 MHz

010 1 24 MHz < HCLK ≤ 48 MHz

Others Reserved Reserved

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Custom ID Register n – CIDRn, n = 0 ~ 3

This register species the custom ID information which can be used as the custom identity.

Offset: 0x310 (0) ~ 0x31C (3)

Reset value: Various depending on Flash Manufacture Privilege Information Block.

31 30 29 28 27 26 25 24

CID

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

23 22 21 20 19 18 17 16

CID

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

15 14 13 12 11 10 9 8

CID

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

7 6 5 4 3 2 1 0

CID

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

Flash Memory Controller (FMC)

Bits Field Descriptions

[31:0] CIDn Custom ID

Read as the CIDn[31:0] (n=0 ~ 3) field in the Custom ID registers in Flash
Manufacture Privilege Block.

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5

Power Control Unit (PWRCU)

Introduction

The power consumption can be regarded as one of the most important issues for many embedded
system applications. Accordingly the Power Control Unit, PWRCU, provides many types of power

saving modes such as Sleep, Deep-Sleep1, Deep-Sleep2, and Power-Down modes. These modes

reduce the power consumption and allow the application to achieve the best trade-off between the

conicting demands of CPU operating time, speed and power consumption. The dash line in the
Figure 11 indicates the power supply source of three digital power domains.

V

DD

V

BAT

nRST

WAKEUP

RTCOUT

PWRSW

RTC

LSI

V

BAK

WKUP1

WKUP2

WKUP3

PORB

PWR_CTRL

LDOOFF

LCM

DMOSON

WKUP4

SLEEPDEEP

SLEEPING

V

DD

VDDDomain

LDO

DMOS

HSE

CPU Memories

POR/PDR

POR/PDR

1.5 V Domain

PLL

HSI

3.3 V

LVD

1.5 V

Power Control Unit (PWRCU)

V

DD15

LDOOUT

V

LSE

PORB: V
BREG: Backup Registers

BREG

Backup Domain

Power On Reset

BAK

Figure 11. PWRCU Block Diagram

LDO: Voltage Regulator
DMOS: Depletion MOS

APB

INTF

LVD: Low Voltage Detector
POR/PDR: Power On Reset/Power Down Reset

Digital

Peripheral

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Features

▄

Three power domains: Backup, VDD and 1.5 V power domains.

▄

Four power saving modes: Sleep, Deep-Sleep1, Deep-Sleep2 and Power-Down modes.

▄

Internal Voltage regulator supplies 1.5 V voltage source.

▄

Additional Depletion MOS supplies 1.5 V voltage source with low leakage and low operating

current.

▄

A power reset is generated when one of the following events occurs:

Power-on / Power-down reset (POR / PDR reset).

When exiting Power-Down mode.

The control bits BODEN = 1, BODRIS=0 and the supply power VDD ≤ V

▄

BOD Brown Out Detector can issue a system reset or an interrupt when VDD power source is
lower than the Brown Out Detector voltage V

▄

LVD Low Voltage Detector can issue an interrupt or wakeup event when VDD is lower than a

programmable threshold voltage V

▄

Switch Battery power (V

▄

40 bytes of backup registers powered by V
the Power-Down mode.

.

BOD

.

LVD

) for backup domain when VDD is lower than V

BAT

for data storage of user application data when in

BAK

BOD

PDR

Power Control Unit (PWRCU)

.

voltage.

Functional Descriptions

Backup Domain

Power Switch

The Backup Domain is powered by the VDD power source or the battery power source, V
is selected by the power switch PWRSW. The operating voltage range of the Back Domain is
from 2.0 V to 3.6 V. If VDD is lower than V

automatically switched from VDD to V
in the backup domain can operate normally. This means that the backup register contents will be
retained, the RTC circuitry will operate normally and the low speed oscillators can keep running.

Backup Domain Reset

The Backup Domain reset sources include the Backup Domain Power-On-Reset (PORB) and
the Backup Domain software reset which is activated by setting the BAKRST bit in the BAKCR
register. The PORB signal forces the device to stay in the reset mode until the V

V

. The application software can set the PORBDN bit in the BAKCR register to disable PORB

PORB

circuit to save the current consumption in the Backup Domain. Also the application software can
trigger Backup Domain software reset by setting the BAKRST bit in the BAKCR register. All
registers of PWRCU and RTC will be reset only by the Backup Domain reset.

, which

BAT

, then the power source of the Back Domain will be

PDR

. Therefore, even if VDD is powered down, all the circuitry

BAT

is greater than

BAK

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LSE, LSI and RTC

The Real Time Clock circuitry clock source can be derived from either the Low Speed Internal
RC oscillator, LSI, or the Low Speed External Crystal oscillator, LSE. Before entering the power
saving mode by executing WFI/WFE instruction, the MCU needs to setup the compare register

with an expected wakeup time and enable the wakeup function to achieve the RTC timer wakeup
event. After entering the power saving mode for a certain amount of time, the Compare Match

ag, CMFLAG, will be asserted to wakeup the device when the compare match event occurs. The
details of the RTC conguration for wakeup timer will be described in the RTC chapter.

Backup Registers and Isolation Cells

Ten 32-bit registers, up to 40 bytes, are located in the Backup Domain for user application data

storage. These registers are powered by V

core power is switched off. The Backup Registers are only reset by the Backup Domain power-on­reset, PORB, or the Backup Domain software reset, BAKRST. When the device resumes operation
from the 1.5 V power, either by Hardware or Software, access to the Backup registers and the RTC

registers are disabled by the isolation cells which protect these registers against possible parasitic
write accesses. To resume access operations, users must disable these isolation cells by setting the

BKISO bit to 1 in the LPCR register of the Clock Control Unit.

which constantly supplies power when the 1.5 V

BAK

Power Control Unit (PWRCU)

LDO Power Control

The LDO will be automatically switched off when one of the following conditions occurs:

▄

The Power-Down or Deep-Sleep 2 mode is entered.

▄

The control bits BODEN = 1, BODRIS=0 and the supply power VDD ≤ V

▄

The supply power V

DD33

≤ V

PDR

BOD

.

The LDO will be automatically switched on by hardware when the supply power VDD > V

of the following conditions occurs:

▄

Resume operation from the power saving mode - RTC wakeup, LVD wakeup and WAKEUP pin

rising edge.

▄

Detect a falling edge on the external reset pin (nRST).

▄

The control bit BODEN = 1 and the supply power VDD > V

BOD

.

To enter the Deep-Sleep1 mode, the PWRCU will request the LDO to operate in a low current
mode, LCM. To enter the Deep-Sleep 2 mode, the PWRCU will turn off the LDO and turn on the
DMOS to supply an alternative 1.5 V power.

VDD Power Domain

Voltage Regulator

The voltage regulator, LDO, Depletion MOS, DMOS, Low voltage Detector, LVD and High Speed

Internal oscillator, HSI are operated under the VDD power domain. The LDO can be congured to

operate in either normal mode (LDOOFF = 0, SLEEPDEEP = 0, I
current mode (LDOOFF = 0, SLEEPDEEP=1, I

= Low current mode) to supply the 1.5 V power.

OUT

An alternative 1.5 V power source is the output of the DMOS which has low static and driving
current characteristics. It is controlled using the DMOSON bit in the BAKCR register. The DMOS

output has weak output current and regulation capability and only operate in the Deep-Sleep 2
mode for data retention purposes in the V

power domain.

DD15

= High current mode) or low

OUT

POR

if any

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Power On Reset (POR) / Power Down Reset (PDR)

The device has an integrated POR/PDR circuitry that allows proper operation starting from/down

to 2.0 V. The device remains in Power-Down mode when VDD is below a specied threshold V

without the need for an external reset circuit. For more details the power on / power down reset

threshold voltage, refer to the electrical characteristics of the corresponding datasheet.

V

,

PDR

DD

V

POR

Hysteresis

V

PDR

Power Control Unit (PWRCU)

POR Delay Time

t

RESET

RSTD

Figure 12. Power On Reset / Power Down Reset Waveform

Low Voltage Detector / Brown Out Detector

The Low Voltage Detector, LVD, can detect whether the supply voltage VDD is lower than a

programmable threshold voltage V

. It is selected by the LVDS bits in the LVDCSR register.

LV D

When a low voltage on the VDD power pin is detected, the LVDF ag will be active and an interrupt

will be generated and sent to the MCU core if the LVDEN and LVDIWEN bits in the LVDCSR
register are set. For more details concerning the LVD programmable threshold voltage V

to the electrical characteristics of the corresponding datasheet.

The Brown Out Detector, BOD, is used to detect if the VDD supply voltage is equal to or lower

than V
is lower than V

. When the BODEN bit in the LVDCSR register is set to 1 and the VDD supply voltage

BOD

then the BODF ag is active. The PWRCU will regard this as a power down

BOD

reset situation and then immediately disable the internal LDO regulator when the BODRIS bit is

cleared to 0 or issue an interrupt to notify the CPU to execute a power down procedure when the

BODRIS bit is set to 1. For more details concerning the Brown Out Detector voltage V

the electrical characteristics of the corresponding datasheet.

Time

LV D

, refer to

BOD

, refer

High Speed Internal Oscillator

The High Speed Internal Oscillator, HSI, is located in the VDD power domain. When exiting from

the Deep-Sleep mode, the HSI clock will be congured as the system clock for a certain period
by setting the PSRCEN bit to 1 This bit is located in the Global Clock Control Register, GCCR, in
the Clock Control Unit, CKCU. The system clock will not be switched back to the original clock

source used before entering the Deep-Sleep mode until the original clock source, which may be

either sourced from the PLL or HSE stabilizes. Also the system will force the HSI oscillator to be
the system clock after a wake up from Power-Down mode since a 1.5 V power on reset will occur.

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High Speed External Oscillator

The High Speed External Oscillator, HSE, is located in the VDD power domain. The HSE crystal
oscillator can be switched on or off using the HSEEN bit in the Global Clock Control Register

(GCCR). The HSE clock can then be used directly as the system clock source or be used as the PLL

input clock.

1.5 V Power Domain

The main functions that include the APB interface for the backup domain, CPU core logic, AHB/
APB peripherals and memories and so on are located in this power domain. Once the 1.5 V is
powered up, the POR will generate a reset sequence (Refer to PORB) on 1.5 V power domain.

Subsequently, to enter the expected power saving mode, the associated control bits including

the LDOOFF, DMOSON, and SLEEPDEEP bits must be congured. Then, once a WFI or WFE

instruction is executed, the device will enter an expected power saving mode which will be
discussed in the following section.

Operation Modes

Run Mode

In the Run mode, the system operates with full functions and all power domains are active. There

are two ways to reduce the power consumption in this mode. The rst is to slow down the system
clock by setting the AHBPRE eld in the CKCU AHBCFGR register, and the second is to turn
off the unused peripherals clock by setting the APBCCR0 and APBCCR1 registers or slow down
peripherals clock by setting the APBPCSR0 and APBPCSR1 registers to meet the application

requirement. Reducing the system clock speed before entering the sleep mode will also help to
minimize power consumption.

Power Control Unit (PWRCU)

Additionally, there are several power saving modes to provide maximum optimization between
device performance and power consumption.

Table 11. Operation Mode Denitions

Mode name Hardware Action

Run After system reset, CPU fetches instructions to execute.

Sleep

Deep-Sleep1 ~ 2

Power-Down Shut down the 1.5 V power domain

1. CPU clock will be stopped.

2. Peripherals, Flash and SRAM clocks can be stopped by setting.

1. Stop all clocks in the 1.5 V power domain.

2. Disable HSI, HSE, and PLL.

3. Turning on the LDO low current mode or DMOS to reduce the 1.5 V power
domain current.

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Sleep Mode

By default, only the CPU clock will be stopped in the Sleep mode. Clearing the FMCEN or
SRAMEN bit in the CKCU AHBCCR register to 0 will have the effect of stopping the Flash clock

or SRAM clock after the system enters the Sleep mode. If it is not necessary for the CPU to access
the Flash memory and SRAM in the Sleep mode, it is recommended to clear the FMCEN and

SRAMEN bits in the AHBCCR register to minimize power consumption. To enter the Sleep mode,
it is only necessary to clear the SLEEPDEEP bit to 0 and execute a WFI or WFE instruction. The

system will exit from the Sleep mode via any interrupt or event trigger. The accompanying table
provides more information about the power saving modes.

Table 12. Enter/Exit Power Saving Modes

Mode Entry

Mode

Sleep

Deep-Sleep1 1 0 0

Deep-Sleep2 1 X 1

Power-Down 1 1 0

Notes:

1. Wakeup event means EXTI line in event mode, RTC, LVD, and WAKEUP pin rising edge

CPU

Instruction

WFI or WFE
(Takes effect)

CPU

SLEEPDEEP

0 X X

LDOOFF DMOSON

WFI: Any interrupt
WFE:

Any wakeup event
Any interrupt (NVIC on) or
Any interrupt with SEVONPEND = 1 (NVIC off)

Any EXTI in event mode or
RTC wakeup or
CMP Wakeup or
LVD wakeup
WAKEUP pin rising edge or
USB resume

RTC wakeup or
LVD wakeup
WAKEUP pin rising edge

RTC wakeup or
LVD wakeup
WAKEUP pin rising edge or
External reset (nRST)

(2)

or

(2)

or

(2)

or

2. If the system allows the LVD activity to wake it up after the system has entered the power saving mode,
the LVDEWEN and LVDEN bits in the LVDCSR register must be set to 1 to make sure that the system
can be waked up by a LVD event and then the LDO regulator can be turned on when system is woken
up from the Deep-Sleep2 and Power-Down modes.

Deep-Sleep Mode

To enter Deep-Sleep mode, configure the registers as shown in the preceding table and execute

the WFI or WFE instruction. In the Deep-Sleep mode, all clocks including PLL and high speed
oscillator, known as HSI and HSE, will be stopped. In addition, Deep-Sleep1 turns the LDO into
low current mode while Deep-Sleep2 turns off the LDO and uses a DMOS to keep 1.5 V power.

Once the PWRCU receives a wakeup event or an interrupt as shown in the preceding Mode-Exiting

table, the LDO will then operate in normal mode and the high speed oscillator will be enabled.
Finally, the CPU will return to Run mode to handle the wakeup interrupt if required. A Low

Voltage Detection also can be regarded as a wakeup event if the corresponding wakeup control bit

LVDEWEN in the LVDCSR register is enabled. The last wakeup event is a transition from low to
high on the external WAKEUP pin sent to the PWRCU to resume from Deep-Sleep mode. During

the Deep-Sleep mode, retaining the register and memory contents will shorten the wakeup latency.

Mode Exit

(1)

or

Power Control Unit (PWRCU)

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Power-Down Mode

The Power-Down mode is derived from the Deep-Sleep mode of the CPU together with the

additional control bits LDOOFF and DMOSON. To enter the Power-Down mode, users can
congure the registers shown in the preceding Mode-Entering table and execute the WFI or WFE
instruction. A RTC wakeup trigger event, a LVD wakeup, a low to high transition on the external
WAKEUP pin or an external reset (nRST) signal will force the MCU out of the Power-Down mode.
In the Power-Down mode, the 1.5 V power supply will be turned off. The remaining active power

supplies are the 3.3 V power (V

After a system reset, the PORSTF bit in the RSTCU GRSR register, the PDF and BAKPORF bits
in the BAKSR register should be checked by software to conrm if the device is being resumed
from the Power-Down mode by a backup domain power on reset, an unexpected loss of the 1.5

V power or other reset events (nRST, WDT,…). If the device has entered the Power-Down mode

under the correct rmware procedure, then the PDF bit will be set. The System information could
be saved in the Backup Registers and be retrieved when the 1.5 V power domain is powered on
again. More information about the PDF and BAKPORF bits in the BAKSR register and PORSTF

bit in the RSTCU GRSR register is shown in the following table.

DD

/ V

) and the Backup Domain power (V

DDA

BAK

).

Power Control Unit (PWRCU)

Table 13. Power Status After System Reset

BAKPORF PDF PORSTF Description

1 0 1

0 0 1

0 1 1 Restart from the Power-Down mode.

1 1 x Reserved

Register Map

The following table shows the PWRCU registers and reset values. Note all the registers in this unit
are located in the V

Table 14. PWRCU Register Map

Register Offset Description Reset Value

BAKSR 0x100 Backup Domain Status Register 0x0000_0001

BAKCR 0x104 Backup Domain Control Register 0x0000_0000

BAKTEST 0x108 Backup Domain Test Register 0x0000_0027

LVDCSR 0x110 Low Voltage/Brown Out Detect Control and Status Register 0x0000_0000

BAKREG0 0x200 Backup Register 0 0x0000_0000

BAKREG1 0x204 Backup Register 1 0x0000_0000

BAKREG2 0x208 Backup Register 2 0x0000_0000

BAKREG3 0x20C Backup Register 3 0x0000_0000

BAKREG4 0x210 Backup Register 4 0x0000_0000

BAKREG5 0x214 Backup Register 5 0x0000_0000

BAKREG6 0x218 Backup Register 6 0x0000_0000

BAKREG7 0x21C Backup Register 7 0x0000_0000

BAKREG8 0x220 Backup Register 8 0x0000_0000

BAKREG9 0x224 Backup Register 9 0x0000_0000

Power-up for the rst time after the backup domain is reset:

Power on reset when V
software reset command on the backup domain.

Restart from unexpected loss of the 1.5 V power or other reset
(nRST, WDT,…)

backup power domain.

BAK

is applied for the rst time or executing

BAK

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Register Descriptions

Backup Domain Status Register – BAKSR

This register indicates backup domain status.

Offset: 0x100

Reset value: 0x0000_0001 (Reset only by Backup Domain reset)

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

Reserved WUPF

Type/Reset RC 0

7 6 5 4 3 2 1 0

Reserved PDF BAKPORF

Type/Reset RC 0 RC 1

Bits Field Descriptions

[8] WUPF External WAKEUP Pin Flag

0: The Wakeup pin is not asserted
1: The Wakeup pin is asserted

This bit is set by hardware when the WAKEUP pin asserts and is cleared by
software read. Software should read this bit to clear it after a system wake up from
the power saving mode.

[1] PDF Power Down Flag

0: Wakeup from abnormal V
1: Wakeup from Power-Down mode. The loss of V

This bit is set by hardware when the system has successfully entered the Power­Down mode This bit is cleared by software read.

[0] BAKPORF Backup Domain Reset Flag

0: Backup Domain reset does not occur
1: Backup Domain reset occurs

This bit is set by hardware when Backup Domain reset occurs, either a Backup
Domain power on reset or Backup Domain software reset. The bit is cleared by

software read. This bit must be cleared after the system is rst powered, otherwise it

will be impossible to detect when a Backup Domain reset has been triggered. When
this bit is read as 1, a read software loop must be implemented until the bit returns

again to 0. This software loop is necessary to conrm that the Backup Domain is
ready for access. It must be implemented after the Backup Domain is rst powered

up.

shutdown (Loss of V

DD15

is unexpected)

DD15

is under expectation.

DD15

Power Control Unit (PWRCU)

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HT32F52342/HT32F52352

Backup Domain Control Register – BAKCR

This register provides power control bits for the Deep-Sleep and Power-Down modes.

Offset: 0x104

Reset value: 0x0000_0000 (Reset only by Backup Domain reset)

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

DMOSSTS Reserved V15RDYSC Reserved WUPIEN WUPEN

Type/Reset RO 0 RW 0 RW 0 RW 0

7 6 5 4 3 2 1 0

DMOSON Reserved LDOOFF LDOLCM Reserved BAKRST

Type/Reset RW 0 RW 0 RW 0 WO 0

Power Control Unit (PWRCU)

Bits Field Descriptions

[15] DMOSSTS Depletion MOS Status

This bit is set to 1 if the DMOSON bit in this register has been set to 1.
This bit is cleared to 0 if the DMOSON bit has been set to 0 or if a POR/PDR reset
occurred.

[12] V15RDYSC V

[9] WUPIEN External WAKEUP Pin Interrupt Enable

Ready Source Selection.

DD15

0: BKISO bit in the LPCR register located in the CKCU
1: V

DD15

POR

Setting this bit to determine what control signal of isolation cells is used to disable
the isolation function of the V

to VDD power domain level shifter.

DD15

0: Disable WAKEUP pin interrupt function
1: Enable WAKEUP pin interrupt function

The software can set the WUPIEN bit to 1 to assert the LPWUP interrupt in the
NVIC unit when both the WUPEN and WUPF bits are set to1.

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Bits Field Descriptions

[8] WUPEN External WAKEUP Pin Enable

0: Disable WAKEUP pin function.
1: Enable WAKEUP pin function.

The Software can set the WUPEN bit as 1 to enable the WAKEUP pin function
before entering the power saving mode. When WUPEN = 1, a rising edge on the
WAKEUP pin wakes up the system from the power saving mode. As the WAKEUP
pin is active high, this bit will set an input pull down mode when the bit is high. The
corresponding register bits which should be properly setup are the PBPD[12] to 1 in
the PBPDR register, the PBPU [12] to 0 in the PBPUR register and the PBCFG12

[3:0] eld to 0x0F in the GPBCFGHR register.

Note: This bit is reset by a system reset or a Backup Domain reset. Because this
bit is located in the Backup Domain, after reset activity there will be a delay until
the bit is active. The bit will not be active until the system reset finished and the
Backup Domain ISO signal has been disabled. This means that the bit can not be

immediately set by software after a system reset nished and the Backup domain

ISO signal disabled. The delay time needed is a minimum of three 32KHz clock

periods until the bit reset activity has nished.

[7] DMOSON DMOS Control

0: DMOS is OFF
1: DMOS is ON

A DMOS is implemented to provide an alternative voltage source for the 1.5 V power
domain when the CPU enters the Deep-Sleep mode (SLEEPDEEP = 1). The control
bit DMOSON is set by software and cleared by software or PORB. If the DMOSON
bit is set to 1, the LDO will automatically be turned off when the CPU enters the
Deep-Sleep mode.

[3] LDOOFF LDO Operating Mode Control

0: The LDO operates in a low current mode when CPU enters the Deep-Sleep

mode (SLEEPDEEP = 1). The V

1: The LDO is turned off when the CPU enters the Deep-Sleep mode

(SLEEPDEEP=1). The V

Note: This bit is only available when the DMOSON bit is cleared to 0.

[2] LDOLCM LDO Low Current Mode

0: The LDO is operated in normal current mode.
1: The LDO is operated in low current mode.

Note: This bit is only available when CPU is in the run mode. The LDO output

current capability will be limited at 10mA below and lower static current when
the LDOLCM bit is set. It is suitable for CPU is operated at lower speed
system clock to get a lower current consumption. This bit will be clear to 0
when the LDO is power down or VDD power domain reset.

[0] BAKRST Backup Domain Software Reset

0: No action
1: Backup Domain Software Reset is activated - includes all the related RTC and

PWRCU registers.

power is available.

DD15

power is not available.

DD15

Power Control Unit (PWRCU)

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Backup Domain Test Register – BAKTEST

This register specifies a read-only value for the software to recognize whether backup domain is ready for
access.

Offset: 0x108

Reset value: 0x0000_0027

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

BAKTEST

Type/Reset RO 0 RO 0 RO 1 RO 0 RO 0 RO 1 RO 1 RO 1

Bits Field Descriptions

[7:0] BAKTEST Backup Domain Test Bits

A constant 0x27 will be read when the Backup Domain is ready for CPU access.

Power Control Unit (PWRCU)

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Low Voltage / Brown Out Detect Control and Status Register – LVDCSR

This register species ags, enable bits and option bits for low voltage detector.

Offset: 0x110

Reset value: 0x0000_0000 (Reset only by Backup Domain reset)

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved LVDS [2] LVDEWEN LVDIWEN LVDF LVDS [1:0] LVDEN

Type/Reset RW 0 RW 0 RO 0 RW 0 RW 0 RW 0

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved BODF Reserved BODRIS BODEN

Type/Reset RO 0 RW 0 RW 0

Power Control Unit (PWRCU)

Bits Field Descriptions

[21] LVDEWEN LVD Event Wakeup Enable

0: LVD event wakeup is disabled
1: LVD event wakeup is enabled

Setting this bit to 1 will enable the LVD event wakeup function to wake up the
system when a LVD condition occurs which result in the LVDF bit being asserted. If
the system requires to be waked up from the Deep-Sleep or Power-Down mode by
a LVD condition, this bit must be set to 1.

[20] LVDIWEN LVD Interrupt Wakeup Enable

0: LVD interrupt wakeup is disabled
1: LVD interrupt wakeup is enabled

Setting this bit to 1 will enable the LVD interrupt function. When a LVD condition
occurs and the LVDIWEN bit is set to 1, a LVD interrupt will be generated and sent
to the CPU NVIC unit.

[19] LVDF Low Voltage Detect Status Flag

0: V

is higher than the specic voltage level

DDA

1: V

is equal to or lower than the specic voltage level

DDA

When the LVD condition occurs, the LVDF ag will be asserted. When the LVDF ag

is asserted, a LVD interrupt will be generated for CPU if the LVDIWEN bit is set to 1.
However, if the LVDEWEN bit is set to 1 and the LVDIWEN bit is cleared to 0, only

a LVD event will be generated rather than a LVD interrupt when the LVDF ag is

asserted.

[22], [18:17] LVDS [2:0] Low Voltage Detect Level Selection

For more details concerning the LVD programmable threshold voltage, refer to the
electrical characteristics of the corresponding datasheet.

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HT32F52342/HT32F52352

Bits Field Descriptions

[16] LVDEN Low Voltage Detect Enable

0: Disable Low Voltage Detect
1: Enable Low Voltage Detect

Setting this bit to 1 will generate a LVD event when the V
the voltage set by LVDS bits. Therefore when the LVD function is enabled before
the system is into the Deep-Sleep2 (DMOS is turn on and LDO is power down) or
Power-Down mode (DMOS and LDO is power down), the LVDEWEN bit has to
be enabled to avoid the LDO does not activate in the meantime when the CPU is
woken up by the low voltage detection activity.

[3] BODF Brown Out Detect Flag

0: VDD > V
1: VDD ≤ V

[1] BODRIS BOD Reset or Interrupt Selection

0: Reset the whole chip
1: Generate Interrupt

[0] BODEN Brown Out Detector Enable

0: Disable Brown Out Detector
1: Enable Brown Out Detector

BOD

BOD

power is lower than

DDA

Power Control Unit (PWRCU)

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32-Bit Arm® Cortex®-M0+ MCU
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Backup Register n – BAKREGn, n = 0 ~ 9

This register species backup register n for storing data during the VDD15 power-off period.

Offset: 0x200 ~ 0x224

Reset value: 0x0000_0000 (Reset only by Backup Domain reset)

31 30 29 28 27 26 25 24

BAKREGn

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

23 22 21 20 19 18 17 16

BAKREGn

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

15 14 13 12 11 10 9 8

BAKREGn

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

7 6 5 4 3 2 1 0

BAKREGn

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

Power Control Unit (PWRCU)

Bits Field Descriptions

[31:0] BAKREGn Backup Register n (n = 0 ~ 9)

These registers are used for data storage in general purpose. The contents of
BAKREGn registers will remain even if the V

power is lost.

DD15

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HT32F52342/HT32F52352

6

Clock Control Unit (CKCU)

Introduction

The Clock Control unit (CKCU) provides functions of high speed internal RC oscillator (HSI),
High speed external crystal oscillator (HSE), Low speed internal RC oscillator (LSI), Low speed
external crystal oscillator (LSE), Phase Lock Loop (PLL), HSE clock monitor, clock prescaler,
clock multiplexer and clock gating. The clock of AHB, APB, and CPU are derived from system
clock (CK_SYS) which can come from HSI, HSE or PLL. Watchdog Timer and Real Time Clock
(RTC) use either LSI or LSE as their clock source.

A variety of internal clocks can also be wired out though CKOUT for debugging purpose. The

clock monitor can be used to get clock failure detection of HSE. Once the clock of HSE does not

function (could be broken down or removed or etc), CKCU will force to switch the system clock

source to HSI clock to prevent system halt.

Clock Control Unit (CKCU)

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32-Bit Arm® Cortex®-M0+ MCU

4-16 MHz

HSE XTAL

8 MHz

HSI RC

32 kHz

LSI RC

Legend:
HSE = High Speed External clock
HSI = High Speed Internal clock
LSE = Low Speed External clock
LSI = Low Speed Internal clock

32.768 kHz
LSE OSC

WDTSRC

PLLSRC

AHB Prescaler

1,2,4,8,16,32

FCLK

( free running clock)

HCLKD

( to PDMA)

STCLK

(to SysTick)

CK_ADC IP

CK_WDT

WDTEN

CK_REF

CK_HSI/16

CK_HSE/16

CK_SYS/16

CKOUT

CKOUTSRC[2:0]

HSEEN

HSIEN

LSEEN

(Note1)

LSIEN

(Note1)

f

CK_SYS,max

= 48 MHz

CK_LSI

CK_LSE

HCLKC/16

CK_HSI

CK_HSE

PCLK ( CMPx, AFIO,
ADC, SPIx, USARTx,
UARTx, I2Cx, I2S,
GPTMx, MCTMx,
BFTMx, SCTMx, EXTI,
RTC, SCI, WDT)

PLL

Clock

Monitor

PLLEN

CK_LSE

CK_PLL

DMAEN

ADCEN

f

CK_PLL,max

= 48 MHz

CK_LSI

HCLKS

( to SRAM)

HCLKF

( to Flash)

CM0PEN

FMCEN

CM0PEN

SRAMEN

1
0

RTCSRC

(Note1)

CK_RTC

RTCEN

(Note1)

1
0

1

0

CK_AHB

000

001

010

011

100

101

110

CK_SYS

SW[2:0]

8

CK_USB

f

CK_USB

= 48 MHz

USBEN

HCLKC

( to Cortex

®

-M0+)CM0PEN

(control by HW)

Prescaler

1 ~ 32

CK_REF

CK_EBI

( to EBI)

EBIEN

Divider

2

CKREFPRE

HCLKBM

( to Bus Matrix)

CM0PEN

BMEN

HCLKAPB

( to APB Bridge)

CM0PEN

APBEN

CK_CRC
( to CRC)

CRCEN

Peripherals

Clock

Prescaler

1,2,4,8

ADC

Prescaler

1,2,3,4,8,...

00

01

10

11

PCLK

PCLK/2

PCLK/4

PCLK/8

SPIEN

SCIEN

CK_GPIO

( to GPIO port)

GPIODEN

GPIOAEN

CKREFEN

HSI Auto
Trimming
Controller

CK_LSE

USB REF Pulse

00x

011

010

111

110

HT32F52342/HT32F52352

Clock Control Unit (CKCU)

Figure 13. CKCU Block Diagram

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HT32F52342/HT32F52352

Features

▄

4 ~ 16 MHz external crystal oscillator (HSE)

▄

Internal 8 MHz RC oscillator (HSI) with conguration option calibration and custom trimming

capability.

▄

PLL with selectable clock source (from HSE or HSI) for system clock.

▄

32,768 Hz external crystal oscillator (LSE) for Watchdog Timer, RTC or system clock.

▄

Internal 32 kHz RC oscillator (LSI) for Watchdog Timer, RTC or system clock.

▄

HSE clock monitor

Function Descriptions

High Speed External Crystal Oscillator – HSE

The high speed external 4 to 16 MHz crystal oscillator (HSE) produces a highly accurate

clock source to the system clock. The related hardware configuration is shown in the following

gure. The crystal with specic frequency must be placed across the two HSE pins (XTALIN /
XTALOUT) and the external components such as resistors and capacitors are necessary to make it

oscillate properly.

Clock Control Unit (CKCU)

The following guidelines are provided to improve the stability of the crystal circuit PCB layout.

▄

The crystal oscillator should be located as close as possible to the MCU so that the trace lengths
are kept as short as possible to reduce any parasitic capacitances.

▄

Shield any lines in the vicinity of the crystal by using a ground plane to isolate signals and
reduce noise.

▄

Keep frequently switching signal lines away from the crystal area to prevent crosstalk.

OSC_EN

XTALOUTXTALIN

Crystal

4 MHz ~ 16 MHz

CL1 CL2

Figure 14. External Crystal, Ceramic, and Resonators for HSE

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HT32F52342/HT32F52352

The HSE crystal oscillator can be switched on or off using the HSEEN bit in the Global Clock

Control Register (GCCR). The HSERDY f lag in the Global Clock Status Register (GCSR) will

indicate if the high-speed external crystal oscillator is stable. When switching on the HSE oscillator

the HSE clock will still not be released until this HSERDY bit is set by the hardware. The specic

delay period is well-known as “Start-up time”. As the HSE becomes stable, an interrupt will be

generated if the related interrupt enable bit HSERDYIE in the Global Clock Interrupt Register

(GCIR) is set. The HSE clock can then be used directly as the system clock source or be used as the

PLL input clock.

High Speed Internal RC Oscillator – HSI

The high speed internal 8 MHz RC oscillator (HSI) is the default selection of clock source for the
CPU when the device is powered up. The HSI RC oscillator provides a clock source in a lower cost
because no external components are required. The HSI RC oscillator can be switched on or off

using the HSIEN bit in the Global Clock Control Register (GCCR). The HSIRDY ag in the Global

Clock Status Register (GCSR) will indicate if the internal RC oscillator is stable. The start-up
time of HSI is shorter then the HSE crystal oscillator. An interrupt can be generated if the related

interrupt enable bit HSIRDYIE in the Global Clock Interrupt Register (GCIR) is set as the HSI
becomes stable. The HSI clock can also be used as the PLL input clock.

Clock Control Unit (CKCU)

The accuracy of the frequency of the high speed internal RC oscillator HSI can be calibrated via the

conguration options, but it is still less accurate than the HSE crystal oscillator. The applications,

the environments and the cost will determine the use of the oscillators.

Software could congure PSRCEN bit (Power Saving Wakeup RC Clock Enable) to 1 to force HSI

clock to be system clock when wake-up from Deep-Sleep or Power-Down mode. Subsequently, the

system clock will be switched back to the original clock source (HSE or PLL) if the original clock
source ready ag is asserted. This function can reduce the wakeup time when using the HSE or
PLL clock as the system clock.

Auto Trimming of High Speed Internal RC Oscillator – HSI

The frequency accuracy of the high speed internal RC oscillator HSI can vary from one chip to
another due to manufacturing process variations, this is why each device is factory calibrated by
HOLTEK for ±2% accuracy at VDD = 3.3 V and TA = 25°C. But the accuracy is not enough for
some applications and environments requirement. Therefore, this device provides the trimming
mechanism for HSI frequency calibration using more accurate external reference clock. The detail
block diagram is shown as Fig ure 15.

After reset, the factory trimming value is loaded in the HSICOARSE[4:0] and HSIFINE[7:0] bits
in the HSI Control Register (HSICR). The HSI frequency accuracy may be affected by the voltage
or temperature variation. If the application has to be driven by more accurate HSI frequency, the
HSI frequency can be manually trimmed using the HSIFINE[7:0] bits in the HSI Control Register
(HSICR) or automatically adjusted via the Auto Trimming Controller together with an external
reference clock in the application. The reference clock can be provided from the low speed external

crystal or ceramic resonator oscillator LSE with a 32,768 Hz frequency or a 1ms USB frame

synchronous signal.

Rev. 1.30 85 of 656 September 28, 2018

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HT32F52342/HT32F52352

Auto Trimming HSI Block Diagram

1

0

TMSEL

USB Frame Pulse

LSE

32.768KHz

1

Factory

Trimming Bits

0

TRIMEN

/32

1

0

REFCLKSEL

Fine [7:0]

Coarse [4:0]

1KHz

/1.024KHz

Fine-Trimming

Write Register

ATCEN

Auto Trimming

Controller

Fine-Trimming

Read Register

8MHz HSI

Oscillator

8MHZ

AT
Counter
Register

Clock Control Unit (CKCU)

AHB Bus

Figure 15. HSI Auto Trimming Block Diagram

Coarse-Trimming

Read Register

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2

2*2*2

2*1*

NO

NF

NO

NF

NONONR

NFNF

HT32F52342/HT32F52352

Phase Locked Loop – PLL

This PLL can provide 4 ~ 48 MHz clock output which is 1 ~ 12 multiples of a fundamental
reference frequency of 4 ~ 16 MHz. The rationale of the clock synthesizer relies on the digital
Phase Locked Loop (PLL) which includes a reference divider, a feedback divider, a digital phase
frequency detector (PFD), a current-controlled charge pump, a built-in loop lter and a voltage-

controlled oscillator (VCO) to achieve a stable phase-locked state.

CLK

= 4 ~ 16MHz

Ref. Divider

in

(NR)

/2

PD

CP VCO

Loop
Filter

= 48 ~ 96 MHz

VCO

out

Output Divider 1

(NO1)

/2

Output Divider 2

(NO2)

S1~S0

PLL

out

= 4 ~ 48 MHz

Clock Control Unit (CKCU)

Feedback Divider 2

(NF2)

B3~B0

Figure 16. PLL Block Diagram

Frequency of the PLL output clock can be determined by the following formula:

*

CKPLL

where NR = Ref divider = 2, NF1 = Feedback Divider 1 = 4, NF2 = Feedback Divider 2 = 1 ~ 16,
NO1 = Output Divider 1 = 2, NO2 = Output Divider 2 = 1, 2, 4, or 8

Considering the duty cycle of 50%, both input and output frequencies are divided by 2. If a given

CLKin frequency as the PLL input generates a specic PLL output frequency, it is recommended
to load a larger value into the NF2 eld to increase the PLL stability and reduce the jitter with but

the expense of settling time. The output and feedback divider 2 setup values are described in Table

15 and Table 16. All the conguration bits (S1 ~ S0, B3 ~ B0) in Table 15 and Ta bl e 16 are dened
in the PLL Conguration Register (PLLCFGR) and PLL Control Register (PLLCR) in the section
of Register Denition. Note that the VCO
96 MHz. If the selected conguration exceeds this range, the PLL output frequency will not be
guaranteed to match the above PLL

Feedback Divider 1

(NF1)

/4

2*1

CK

OUT

formula.

OUT

*

2*4

CK

===

INININOUT

2

*

frequency should be in the range from 48 MHz to

The PLL can be switched on or off by using the PLLEN bit in the Global Clock Control Register
(GCCR). The PLLRDY ag in the Global Clock Status Register (GCSR) will indicate if the PLL
clock is stable. An interrupt can be generated if the related interrupt enable bit PLLRDYIE in the
Global Clock Interrupt Register (GCIR) is set as the PLL becomes stable.

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HT32F52342/HT32F52352

Table 15. Output Divider2 Value Mapping

Output divider 2 setup bits S[1:0]

(POTD bits in the PLLCFGR register)

Table 16. Feedback Divider2 Value Mapping

Feedback divider2 setup bits B[3:0]

(PFBD bits in the PLLCFGR register)

NO2 (Output divider 2 value)

00 1

01 2

10 4

11 8

NF2 (Feedback divider 2 value)

0000 16

0001 1

0010 2

0011 3

0100 4

0101 5

0110 6

0111 7

1000 8

1001 9

1010 10

1011 11

1100 12

:
:

1111 15

Clock Control Unit (CKCU)

:
:

Rev. 1.30 88 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Low Speed External Crystal Oscillator – LSE

The low speed external crystal or ceramic resonator oscillator with 32,768 Hz frequency produces

a low power but highly accurate clock source for the Real-Time-Clock peripheral, Watchdog Timer
or system clock. The associated hardware configuration is shown in the following figure. The

crystal or ceramic resonator must be placed across the two LSE pins (X32KIN / X32KOUT) and

the external components such as resistors and capacitors are necessary to make it oscillate properly.

The LSE oscillator can be switched on or off by using the LSEEN bit in the RTC Control Register
(RTCCR). The LSERDY ag in the Global Clock Status Register (GCSR) will indicate if the LSE
clock is stable. An interrupt can be generated if the related interrupt enable bit LSERDYIE in the
Global Clock Interrupt Register (GCIR) is set as the LSE becomes stable.

Clock Control Unit (CKCU)

X32KIN

C

L1

32.768KHZ

Figure 17. External Crystal, Ceramic, and Resonators for LSE

Low Speed Internal RC Oscillator – LSI

The low speed internal RC oscillator with a frequency of about 32 kHz produces a low power clock

source for the Real-Time-Clock peripheral, Watchdog Timer or system clock. The LSI offers a low
cost clock source because no external component is required to make it oscillates. The LSI RC
oscillator can be switched on or off by using the LSIEN bit in the RTC Control Register (RTCCR).
The LSI frequency accuracy is shown in the datasheet. The LSIRDY flag in the Global Clock
Status Register (GCSR) will indicate if the LSI clock is stable. An interrupt can be generated if the
related interrupt enable bit LSIRDYIE in the Global Clock Interrupt Register (GCIR) is set as the
LSI becomes stable.

Clock Ready Flag

The CKCU provides the corresponding clock ready flags for the HSI, HSE, PLL, LSI, and LSE
to indicate whether these clocks are stable. Before using them as the system clock source or
other purpose, it is necessary to conrm the specic clock ready ag is set. Software can check

the specific clock is ready or not by polling the individual clock ready status bits in GCSR

register. Additionally, the CKCU can trigger an interrupt to notify specific clock is ready if the

corresponding interrupt enable bit in the GCIR register is set. Software should clear the interrupt
status bit in the GCIR register by interrupt service routine.

X32KOUT

C

L2

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HT32F52342/HT32F52352

System Clock (CK_SYS) Selection

After the system reset occurs, the default system clock source CK_SYS will be the high speed
internal RC oscillator HSI. The CK_SYS may come from the HSI, HSE, LSE, LSI or PLL output

clock and it can be switched from one clock source to another by changing the System Clock
Switch bits, SW, in the Global Clock Control Register GCCR. The system will still run under
the original clock until the destination clock gets ready when the SW value is changed. The
corresponding clock ready status bit in the Global Clock Status Register (GCSR) will indicate

whether the selected clock is ready to use or not. The CKCU also contains the clock source status
bits in the Clock Source Status Register (CKST) to indicate which clock is currently used as the
system clock. If a clock source or the PLL output clock is uses as the system clock source, it is not

possible to stop it. More details about the clock enable function is described in the following.

If any event in the following occurs, the HSI will be enabled.

▄

Enable PLL and congure its source clock to HSI. (PLLEN, PLLSRC)

▄

Enable Clock monitor. (CKMEN)

▄

Congure clock switch register to HSI. (SW)

▄

Congure HSI enable register to 1. (HSIEN)

If any event in the following occurs, the HSE will be enabled.

Clock Control Unit (CKCU)

▄

Enable PLL and congure its source clock to HSE. (PLLEN, PLLSRC)

▄

Congure clock switch register to HSE. (SW)

▄

Congure HSE enable register to 1. (HSEEN)

If any event in the following occurs, the PLL will be enabled.

▄

Enable USB Enable register. (USBEN)

▄

Congure clock switch register to PLL (SW)

▄

Congure PLL enable register to 1. (PLLEN)

The system clock selection programming guide is listed in the following.

1. Enable any clock source which will become the system clock or PLL input clock.

2. Conguring the PLLSRC register after the ready ags of both HSI and HSE are asserted,

3. Conguring the SW register to change the system clock source will occur after the corresponding
ready ag of the clock source is asserted. Note that the system clock will be forced to HSI if
the clock monitor is enabled and the PLL output or HSE clock congured as the system clock is
stuck at 0 or 1.

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32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

HSE Clock Monitor

The HSE clock monitor function is enabled by the HSE Clock Monitor Enable bit CKMEN in the

Global Clock Control Register, GCCR. The HSE clock monitor function should be enabled after
the HSE oscillator start-up delay and disabled when the HSE oscillator is stopped. Once the HSE
oscillator failure is detected, the HSE oscillator will automatically be disabled. The HSE clock

stuck ag CKSF in the Global Clock Interrupt Register GCIR will be set and the HSE oscillator
failure event will be generated if the corresponding interrupt enable bit CKSIE in the GCIR is

set. This failure interrupt is connected to the CPU Non-Maskable Interrupt, NMI. When the HSE
oscillator failure occurs, the HSE will be turned off and the system clock will be switched to the

HSI automatically by the hardware. If the HSE is used as the clock input of the PLL circuit whose
output is used as the system clock, the PLL circuit will also be turned off as well as the HSE when

the failure happens.

Clock Output Capability

The device has the clock output capability to allow the clocks to be output on the specic external
output pin CKOUT. The configuration registers of the corresponding GPIO port must be well
congured in the Alternate Function I/O, AFIO, section to output the selected clock signal. There

are seven output clock signals to be selected via the device clock output source selection bits

CKOUTSRC in the Global Clock Conguration Register, GCFGR.

Clock Control Unit (CKCU)

Table 17. CKOUT Clock Source

CKOUTSRC[2:0] Clock Source

000 CK_REF = CK_PLL / (CKREFPRE + 1) / 2

001 HCLKC / 16

010 CK_SYS / 16

011 CK_HSE / 16

100 CK_HSI / 16

101 CK_LSE

110 CK_LSI

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32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Register Map

The following table shows the CKCU register and reset value.

Table 18. CKCU Register Map

Register Offset Description Reset Value

GCFGR 0x000 Global Clock Conguration Register 0x0000_0102

GCCR 0x004 Global Clock Control Register 0x0000_0803

GCSR 0x008 Global Clock Status Register 0x0000_0028

GCIR 0x00C Global Clock Interrupt Register 0x0000_0000

PLLCFGR 0x018 PLL Conguration Register 0x0000_0000

PLLCR 0x01C PLL Control Register 0x0000_0000

AHBCFGR 0x020 AHB Conguration Register 0x0000_0000

AHBCCR 0x024 AHB Clock Control Register 0x0000_0065

APBCFGR 0x028 APB Conguration Register 0x0000_0000

APBCCR0 0x02C APB Clock Control Register 0 0x0000_0000

APBCCR1 0x030 APB Clock Control Register 1 0x0000_0000

CKST 0x034 Clock Source Status Register 0x0100_0003

APBPCSR0 0x038 APB Peripheral Clock Selection Register 0 0x0000_0000

APBPCSR1 0x03C APB Peripheral Clock Selection Register 1 0x0000_0000

HSICR 0x040 HSI Control Register

HSIATCR 0x044 HSI Auto Trimming Counter Register 0x0000_0000

LPCR 0x300 Low Power Control Register 0x0000_0000

MCUDBGCR 0x304 MCU Debug Control Register 0x0000_0000

Clock Control Unit (CKCU)

0xXXXX_0000

where X is undened

Rev. 1.30 92 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Register Descriptions

Global Clock Conguration Register – GCFGR

This register species the clock source for PLL/USART/Watchdog Timer/CKOUT.

Offset: 0x000

Reset value: 0x0000_0102

31 30 29 28 27 26 25 24

LPMOD Reserved

Type/Reset RO 0 RO 0 RO 0

23 22 21 20 19 18 17 16

USBPRE Reserved

Type/Reset RW 0 RW 0

15 14 13 12 11 10 9 8

CKREFPRE Reserved PLLSRC

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 1

7 6 5 4 3 2 1 0

Reserved CKOUTSRC

Type/Reset RW 0 RW 1 RW 0

Bits Field Descriptions

[31:29] LPMOD Lower Power Mode Status

000: When Chip is in running mode
001: When Chip wants to enter Sleep mode
010: When Chip wants to enter Deep Sleep mode1
011: When Chip wants to enter Deep Sleep mode2
100: When Chip wants to enter Power Down mode
Others: Reserved

Set and reset by hardware.

[23:22] USBPRE USB Clock Prescaler Selection

00: CK_USB = CK_PLL
01: CK_USB = CK_PLL / 2
Others: Reserved

Set and reset by software to control the USB clock prescaler setting.

[15:11] CKREFPRE CK_REF Clock Prescaler Selection

CK_REF = CK_PLL / (CKREFPRE + 1) / 2

00000: CK_REF = CK_PLL / 2
00001: CK_REF = CK_PLL / 4
...
11111: CK_REF = CK_PLL / 64

Set and reset by software to the control CK_REF clock prescaler setting.

[8] PLLSRC PLL Clock Source Selection

0: External 4 ~ 16 MHz crystal oscillator clock is selected (HSE)
1: Internal 8 MHz RC oscillator clock is selected (HSI)

Set and reset by software to control the PLL clock source.

Clock Control Unit (CKCU)

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32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Bits Field Descriptions

[2:0] CKOUTSRC CKOUT Clock Source Selection

000: (CK_REF) is selected where CK_REF = CK_PLL / (CKREFPRE + 1) / 2
001: (HCLKC / 16) is selected
010: (CK_SYS / 16) is selected
011: (CK_HSE / 16) is selected
100: (CK_HSI / 16) is selected
101: CK_LSE is selected
110: CK_LSI is selected
111: Reserved

Set and reset by software.

Clock Control Unit (CKCU)

Rev. 1.30 94 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
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Global Clock Control Register – GCCR

This register species the clock enable bits.

Offset: 0x004

Reset value: 0x0000_0803

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved PSRCEN CKMEN

Type/Reset RW 0 RW 0

15 14 13 12 11 10 9 8

Reserved HSIEN HSEEN PLLEN HSEGAIN

Type/Reset RW 1 RW 0 RW 0 RW 0

7 6 5 4 3 2 1 0

Reserved SW

Type/Reset RW 0 RW 1 RW 1

Clock Control Unit (CKCU)

Bits Field Descriptions

[17] PSRCEN Power Saving Wakeup RC Clock Enable

0: No action
1: Use Internal 8 MHz RC clock (HSI) as system clock after power down wakeup.

The software can set the PSRCEN bit high before entering the power saving mode
in order to reduce the waiting time after a wakeup. When the PSRCEN bit is set
to 1, the HSI will be used as the CK_SYS clock source after waking up from the
power saving mode. This means that the instruction can be executed early before
the original CK_SYS source is stable since the HSI clock is provided to CPU. After
the original CK_SYS clock source is ready, the CK_SYS clock will automatically be
switched back to the originally selected clock source from the HSI clock.

[16] CKMEN HSE Clock Monitor Enable

0: Disable External 4 ~ 16 MHz crystal oscillator clock monitor
1: Enable External 4 ~ 16 MHz crystal oscillator clock monitor

When the hardware detects that the HSE clock is stuck at low or high state, the
internal hardware will switch the system clock to internal high speed HSI RC clock.

[11] HSIEN Internal High Speed Oscillator Enable

0: Internal 8 MHz RC oscillator is disabled
1: Internal 8 MHz RC oscillator is enabled

Set and reset by software. This bit can not be reset if the HSI clock is used as the
system clock.

[10] HSEEN External High Speed Oscillator Enable

0: External 4 ~ 16 MHz crystal oscillator is disabled
1: External 4 ~ 16 MHz crystal oscillator is enabled

Set and reset by software. This bit can not be reset if the HSE clock is used as the
system clock or the PLL input clock.

[9] PLLEN PLL Enable

0: PLL disabled
1: PLL enabled

Set and reset by software. This bit cannot be reset if the PLL clock is used as the
system clock.

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32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Bits Field Descriptions

[8] HSEGAIN External High Speed Oscillator Gain Selection

0: HSE in low gain mode
1: HSE in high gain mode

[2:0] SW System Clock Switch

00x: CK_PLL clock out as system clock
010: CK_HSE as system clock
011: CK_HSI as system clock
110: CK_LSE as system clock
111: CK_LSI as system clock
Other: CK_HSI as system clock

These bits are used to select the CK_SYS source. When switch the system clock
using the SW bit, the system clock will be not immediately switched and a certain
delay is necessary. The system clock source selected by the SW bits can be
indicated in the CKSWST bits in the clock source status register CKST to make sure
which clock is currently used as the system clock. Note that the HSI oscillator will be
forced as the system clock when the HSE clock failure is detected as the HSE clock
monitor function is enabled.

Clock Control Unit (CKCU)

Rev. 1.30 96 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Global Clock Status Register – GCSR

This register indicates the clock ready status.

Offset: 0x008

Reset value: 0x0000_0028

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved LSIRDY LSERDY HSIRDY HSERDY PLLRDY Reserved

Type/Reset RO 1 RO 0 RO 1 RO 0 RO 0

Clock Control Unit (CKCU)

Bits Field Descriptions

[5] LSIRDY Internal Low Speed Oscillator Ready Flag

0: Internal 32 kHz RC oscillator is not ready
1: Internal 32 kHz RC oscillator is ready

Set by hardware to indicate whether the LSI is stable to be used.

[4] LSERDY External Low Speed Oscillator Ready Flag

0: External 32,768 Hz crystal oscillator is not ready
1: External 32,768 Hz crystal oscillator is ready

Set by hardware to indicate whether the LSE is stable to be used.

[3] HSIRDY Internal High Speed Oscillator Ready Flag

0: Internal 8 MHz RC oscillator is not ready
1: Internal 8 MHz RC oscillator is ready

Set by hardware to indicate whether the HSI is stable to be used.

[2] HSERDY External High Speed Oscillator Ready Flag

0: External 4 ~ 16 MHz crystal oscillator is not ready
1: External 4 ~ 16 MHz crystal oscillator is ready

Set by hardware to indicate whether the HSE is stable to be used.

[1] PLLRDY PLL Clock Ready Flag

0: PLL is not ready
1: PLL is ready

Set by hardware to indicate whether the PLL output is stable to be used.

Rev. 1.30 97 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Global Clock Interrupt Register – GCIR

This register species the interrupt enable and ag bits.

Offset: 0x00C

Reset value: 0x0000_0000

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved CKSIE

Type/Reset RW 0

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved CKSF

Type/Reset WC 0

Clock Control Unit (CKCU)

Bits Field Descriptions

[16] CKSIE Clock Stuck Interrupt Enable

0: Disable clock failure interrupt
1: Enable clock failure interrupt

Set and reset by software to enable or disable the clock failure interrupt caused by
clock monitor.

[0] CKSF Clock Stuck Interrupt Flag

0: Clock works normally
1: HSE clock is stuck

Reset by software (Write 1 clear). Set by hardware when the HSE clock is stuck and
the CKMEN bit is set.

Rev. 1.30 98 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

PLL Conguration Register – PLLCFGR

This register species the PLL congurations.

Offset: 0x018

Reset value: 0x0000_0000

31 30 29 28 27 26 25 24

Reserved PFBD

Type/Reset RW 0 RW 0 RW 0

23 22 21 20 19 18 17 16

PFBD POTD Reserved

Type/Reset RW 0 RW 0 RW 0

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved

Type/Reset

Clock Control Unit (CKCU)

Bits Field Descriptions

[26:23] PFBD PLL VCO Output Clock Feedback Divider (B3 ~ B0 in Figure 16)

The feedback Divider divides the output clock from the PLL VCO.

[22:21] POTD PLL Output Clock Divider (S1 ~ S0 in Figure 16)

PLL Control Register – PLLCR

This register species the PLL Bypass mode.

Offset: 0x01C

Reset value: 0x0000_0000

31 30 29 28 27 26 25 24

PLLBPS Reserved

Type/Reset RW 0

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved

Type/Reset

Bits Field Descriptions

[31] PLLBPS PLL Bypass Mode Enable

0: Disable PLL Bypass mode
1: Enable PLL Bypass mode which acts as FOUT = FIN

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32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

AHB Conguration Register – AHBCFGR

This register species the system clock frequency.

Offset: 0x020

Reset value: 0x0000_0000

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved AHBPRE

Type/Reset RW 0 RW 0 RW 0

Clock Control Unit (CKCU)

Bits Field Descriptions

[2:0] AHBPRE AHB Pre-scaler

000: CK_AHB = CK_SYS
001: CK_AHB = CK_SYS / 2
010: CK_AHB = CK_SYS / 4
011: CK_AHB = CK_SYS / 8
100: CK_AHB = CK_SYS / 16
101: CK_AHB = CK_SYS / 32
110: CK_AHB = CK_SYS / 32
111: CK_AHB = CK_SYS / 32

Set and reset by software to control the division factor of the AHB clock.

Rev. 1.30 100 of 656 September 28, 2018