Holtek HT32F52342, HT32F52352 User Manual

Holtek 32-Bit Microcontroller with Arm® Cortex®-M0+ Core

HT32F52342/HT32F52352

User Manual

Revision: V1.30 Date: September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Table of Contents

1 Introduction ........................................................................................................... 26

Overview .............................................................................................................................. 26

Features ............................................................................................................................... 27

Device Information ............................................................................................................... 32

Block Diagram ..................................................................................................................... 33

2 Document Conventions ....................................................................................... 34

3 System Architecture ............................................................................................. 35

Arm® Cortex®-M0+ Processor .............................................................................................. 35

Bus Architecture ................................................................................................................... 36

Memory Organization .......................................................................................................... 37

Memory Map ................................................................................................................................... 38

Embedded Flash Memory ............................................................................................................... 41

Embedded SRAM Memory ............................................................................................................. 41

AHB Peripherals ............................................................................................................................. 41

APB Peripherals ............................................................................................................................. 41

Table of Contents

4 Flash Memory Controller (FMC) .......................................................................... 42

Introduction .......................................................................................................................... 42

Features ............................................................................................................................... 42

Functional Descriptions ....................................................................................................... 43

Flash Memory Map ......................................................................................................................... 43

Flash Memory Architecture ............................................................................................................. 44

Wait State Setting ........................................................................................................................... 44

Booting Conguration ..................................................................................................................... 45

Page Erase ..................................................................................................................................... 46

Mass Erase ..................................................................................................................................... 47

Word Programming ......................................................................................................................... 48

Option Byte Description .................................................................................................................. 49

Page Erase/Program Protection ..................................................................................................... 49

Security Protection .......................................................................................................................... 51

Register Map ....................................................................................................................... 52

Register Descriptions ........................................................................................................... 53

Flash Target Address Register – TADR .......................................................................................... 53

Flash Write Data Register – WRDR ............................................................................................... 54

Flash Operation Command Register – OCMR ............................................................................... 55

Flash Operation Control Register – OPCR ..................................................................................... 56

Flash Operation Interrupt Enable Register – OIER ........................................................................ 57

Flash Operation Interrupt and Status Register – OISR .................................................................. 58

Flash Page Erase/Program Protection Status Register – PPSR .................................................... 60

Flash Security Protection Status Register – CPSR ........................................................................ 61

Rev. 1.30 2 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Flash Vector Mapping Control Register – VMCR ........................................................................... 62

Flash Manufacturer and Device ID Register – MDID ...................................................................... 63

Flash Page Number Status Register – PNSR ................................................................................ 64

Flash Page Size Status Register – PSSR ...................................................................................... 65

Flash Cache & Pre-fetch Control Register – CFCR ........................................................................ 66

Custom ID Register n – CIDRn, n = 0 ~ 3 ...................................................................................... 67

5 Power Control Unit (PWRCU) .............................................................................. 68

Introduction .......................................................................................................................... 68

Features ............................................................................................................................... 69

Functional Descriptions ....................................................................................................... 69

Backup Domain .............................................................................................................................. 69

VDD Power Domain .......................................................................................................................... 70

1.5 V Power Domain ....................................................................................................................... 72

Operation Modes ............................................................................................................................ 72

Register Map ....................................................................................................................... 74

Register Descriptions ........................................................................................................... 75

Backup Domain Status Register – BAKSR ..................................................................................... 75

Backup Domain Control Register – BAKCR ................................................................................... 76

Backup Domain Test Register – BAKTEST .................................................................................... 78

Low Voltage / Brown Out Detect Control and Status Register – LVDCSR ..................................... 79

Backup Register n – BAKREGn, n = 0 ~ 9 ..................................................................................... 81

Table of Contents

6 Clock Control Unit (CKCU) .................................................................................. 82

Introduction .......................................................................................................................... 82

Features ............................................................................................................................... 84

Function Descriptions .......................................................................................................... 84

High Speed External Crystal Oscillator – HSE ............................................................................... 84

High Speed Internal RC Oscillator – HSI ........................................................................................ 85

Auto Trimming of High Speed Internal RC Oscillator – HSI ............................................................ 85

Phase Locked Loop – PLL .............................................................................................................. 87

Low Speed External Crystal Oscillator – LSE ................................................................................. 89

Low Speed Internal RC Oscillator – LSI ......................................................................................... 89

Clock Ready Flag ........................................................................................................................... 89

System Clock (CK_SYS) Selection ................................................................................................ 90

HSE Clock Monitor ......................................................................................................................... 91

Clock Output Capability .................................................................................................................. 91

Register Map ....................................................................................................................... 92

Register Descriptions ........................................................................................................... 93

Global Clock Conguration Register – GCFGR .............................................................................. 93

Global Clock Control Register – GCCR .......................................................................................... 95

Global Clock Status Register – GCSR ........................................................................................... 97

Global Clock Interrupt Register – GCIR .......................................................................................... 98

PLL Conguration Register – PLLCFGR ........................................................................................ 99

Rev. 1.30 3 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

PLL Control Register – PLLCR ....................................................................................................... 99

AHB Conguration Register – AHBCFGR .................................................................................... 100

AHB Clock Control Register – AHBCCR ...................................................................................... 101

APB Conguration Register – APBCFGR ..................................................................................... 103

APB Clock Control Register 0 – APBCCR0 .................................................................................. 104

APB Clock Control Register 1 – APBCCR1 .................................................................................. 106

Clock Source Status Register – CKST ......................................................................................... 108

APB Peripheral Clock Selection Register 0 – APBPCSR0 ........................................................... 109

APB Peripheral Clock Selection Register 1 – APBPCSR1 ............................................................111

HSI Control Register – HSICR .......................................................................................................113

HSI Auto Trimming Counter Register – HSIATCR .........................................................................114

Low Power Control Register – LPCR ............................................................................................115

MCU Debug Control Register – MCUDBGCR ...............................................................................116

7 Reset Control Unit (RSTCU) .............................................................................. 119

Introduction ........................................................................................................................ 119

Functional Descriptions ..................................................................................................... 120

Power On Reset ........................................................................................................................... 120

System Reset ............................................................................................................................... 120

AHB and APB Unit Reset .............................................................................................................. 120

Register Map ..................................................................................................................... 121

Register Descriptions ......................................................................................................... 121

Global Reset Status Register – GRSR ......................................................................................... 121

AHB Peripheral Reset Register – AHBPRSTR ............................................................................. 122

APB Peripheral Reset Register 0 – APBPRSTR0 ........................................................................ 123

APB Peripheral Reset Register 1 – APBPRSTR1 ........................................................................ 125

Table of Contents

8 General Purpose I/O (GPIO) ............................................................................... 127

Introduction ........................................................................................................................ 127

Features ............................................................................................................................. 128

Functional Descriptions ..................................................................................................... 128

Default GPIO Pin Conguration .................................................................................................... 128

General Purpose I/O – GPIO ........................................................................................................ 128

GPIO Locking Mechanism ............................................................................................................ 130

Register Map ..................................................................................................................... 130

Register Descriptions ......................................................................................................... 131

Port A Data Direction Control Register – PADIRCR ..................................................................... 131

Port A Input Function Enable Control Register – PAINER ............................................................ 132

Port A Pull-Up Selection Register – PAPUR ................................................................................. 133

Port A Pull-Down Selection Register – PAPDR ............................................................................ 134

Port A Open Drain Selection Register – PAODR .......................................................................... 135

Port A Output Current Drive Selection Register – PADRVR ......................................................... 136

Port A Lock Register – PALOCKR ................................................................................................ 137

Port A Data Input Register – PADINR ........................................................................................... 138

Rev. 1.30 4 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Port A Output Data Register – PADOUTR .................................................................................... 139

Port A Output Set/Reset Control Register – PASRR .................................................................... 140

Port A Output Reset Register – PARR .......................................................................................... 141

Port B Data Direction Control Register – PBDIRCR ..................................................................... 142

Port B Input Function Enable Control Register – PBINER ........................................................... 143

Port B Pull-Up Selection Register – PBPUR ................................................................................ 144

Port B Pull-Down Selection Register – PBPDR ............................................................................ 145

Port B Open Drain Selection Register – PBODR ......................................................................... 146

Port B Output Current Drive Selection Register – PBDRVR ........................................................ 147

Port B Lock Register – PBLOCKR ................................................................................................ 148

Port B Data Input Register – PBDINR .......................................................................................... 149

Port B Output Data Register – PBDOUTR ................................................................................... 150

Port B Output Set/Reset Control Register – PBSRR .................................................................... 151

Port B Output Reset Register – PBRR ......................................................................................... 152

Port C Data Direction Control Register – PCDIRCR .................................................................... 153

Port C Input Function Enable Control Register – PCINER ........................................................... 154

Port C Pull-Up Selection Register – PCPUR ................................................................................ 155

Port C Pull-Down Selection Register – PCPDR ........................................................................... 156

Port C Open Drain Selection Register – PCODR ......................................................................... 157

Port C Output Current Drive Selection Register – PCDRVR ........................................................ 158

Port C Lock Register – PCLOCKR ............................................................................................... 159

Port C Data Input Register – PCDINR .......................................................................................... 160

Port C Output Data Register – PCDOUTR ................................................................................... 161

Port C Output Set/Reset Control Register – PCSRR ................................................................... 162

Port C Output Reset Register – PCRR ......................................................................................... 163

Port D Data Direction Control Register – PDDIRCR .................................................................... 164

Port D Input Function Enable Control Register – PDINER ........................................................... 165

Port D Pull-Up Selection Register – PDPUR ................................................................................ 166

Port D Pull-Down Selection Register – PDPDR ........................................................................... 167

Port D Open Drain Selection Register – PDODR ......................................................................... 168

Port D Output Current Drive Selection Register – PDDRVR ........................................................ 169

Port D Lock Register – PDLOCKR ............................................................................................... 170

Port D Data Input Register – PDDINR .......................................................................................... 171

Port D Output Data Register – PDDOUTR ................................................................................... 172

Port D Output Set/Reset Control Register – PDSRR ................................................................... 173

Port D Output Reset Register – PDRR ......................................................................................... 174

Table of Contents

9 Alternate Function Input/Output Control Unit (AFIO) ...................................... 175

Introduction ........................................................................................................................ 175

Features ............................................................................................................................. 176

Functional Descriptions ..................................................................................................... 176

External Interrupt Pin Selection .................................................................................................... 176

Alternate Function ......................................................................................................................... 177

Lock Mechanism .......................................................................................................................... 177

Register Map ..................................................................................................................... 177

Rev. 1.30 5 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Register Descriptions ......................................................................................................... 178

EXTI Source Selection Register 0 – ESSR0 ................................................................................ 178

EXTI Source Selection Register 1 – ESSR1 ................................................................................ 179

GPIO x Conguration Low Register – GPxCFGLR, x = A, B, C, D ............................................... 180

GPIO x Conguration High Register – GPxCFGHR, x = A, B, C, D ............................................. 181

10 Nested Vectored Interrupt Controller (NVIC) .................................................. 182

Introduction ........................................................................................................................ 182

Features ............................................................................................................................. 183

Function Descriptions ........................................................................................................ 184

SysTick Calibration ....................................................................................................................... 184

Register Map ..................................................................................................................... 184

11 External Interrupt/Event Controller (EXTI) ...................................................... 185

Introduction ........................................................................................................................ 185

Features ............................................................................................................................. 185

Function Descriptions ........................................................................................................ 186

Wakeup Event Management......................................................................................................... 186

External Interrupt/Event Line Mapping ......................................................................................... 187

Interrupt and Debounce ................................................................................................................ 187

Register Map ..................................................................................................................... 188

Register Descriptions ......................................................................................................... 189

EXTI Interrupt Conguration Register n – EXTICFGRn, n = 0 ~ 15 ............................................. 189

EXTI Interrupt Control Register – EXTICR ................................................................................... 190

EXTI Interrupt Edge Flag Register – EXTIEDGEFLGR ................................................................ 191

EXTI Interrupt Edge Status Register – EXTIEDGESR ................................................................. 192

EXTI Interrupt Software Set Command Register – EXTISSCR .................................................... 193

EXTI Interrupt Wakeup Control Register – EXTIWAKUPCR ........................................................ 194

EXTI Interrupt Wakeup Polarity Register – EXTIWAKUPPOLR ................................................... 195

EXTI Interrupt Wakeup Flag Register – EXTIWAKUPFLG ........................................................... 196

Table of Contents

12 Analog to Digital Converter (ADC) .................................................................. 197

Introduction ........................................................................................................................ 197

Features ............................................................................................................................. 198

Function Descriptions ........................................................................................................ 199

ADC Clock Setup .......................................................................................................................... 199

Channel Selection ......................................................................................................................... 199

Conversion Mode .......................................................................................................................... 199

Start Conversion on External Event .............................................................................................. 202

Sampling Time Setting .................................................................................................................. 203

Data Format .................................................................................................................................. 203

Analog Watchdog.......................................................................................................................... 203

Interrupts ....................................................................................................................................... 204

PDMA Request ............................................................................................................................ 204

Rev. 1.30 6 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Register Map ..................................................................................................................... 205

Register Descriptions ......................................................................................................... 206

ADC Conversion Control Register – ADCCR ............................................................................... 206

ADC Conversion List Register 0 – ADCLST0 ............................................................................... 208

ADC Conversion List Register 1 – ADCLST1 ............................................................................... 209

ADC Input Sampling Time Register – ADCSTR ........................................................................... 210

ADC Conversion Data Register y – ADCDRy, y = 0 ~ 7 ................................................................211

ADC Trigger Control Register – ADCTCR .................................................................................... 212

ADC Trigger Source Register – ADCTSR ..................................................................................... 213

ADC Watchdog Control Register – ADCWCR .............................................................................. 214

ADC Watchdog Threshold Register – ADCTR .............................................................................. 215

ADC Interrupt Enable Register – ADCIER .................................................................................... 216

ADC Interrupt Raw Status Register – ADCIRAW ......................................................................... 217

ADC Interrupt Status Register – ADCISR ..................................................................................... 218

ADC Interrupt Clear Register – ADCICLR .................................................................................... 219

ADC DMA Request Register – ADCDMAR ................................................................................... 220

Table of Contents

13 Comparator (CMP) ............................................................................................ 221

Introduction ........................................................................................................................ 221

Features ............................................................................................................................. 221

Function Descriptions ........................................................................................................ 222

Comparator Inputs and Output ..................................................................................................... 222

Comparator Voltage Reference .................................................................................................... 222

Interrupts and Wakeup.................................................................................................................. 223

Power Mode and Hysteresis ......................................................................................................... 224

Comparator Write-Protected mechanism ..................................................................................... 224

Register Map ..................................................................................................................... 224

Register Descriptions ......................................................................................................... 225

Comparator Control Register n – CMPCRn, n = 0 or 1 ................................................................ 225

Comparator Voltage Reference Value Register n – CVRVALRn, n = 0 or 1 ................................. 227

Comparator Interrupt Enable Register n – CMPIERn, n = 0 or 1 ................................................. 228

Comparator Transition Flag Register n – CMPTFRn, n = 0 or 1 .................................................. 229

14 General-Purpose Timer (GPTM) ...................................................................... 230

Introduction ........................................................................................................................ 230

Features ............................................................................................................................. 231

Functional Descriptions ..................................................................................................... 232

Counter Mode ............................................................................................................................... 232

Clock Controller ............................................................................................................................ 235

Trigger Controller .......................................................................................................................... 236

Slave Controller ............................................................................................................................ 237

Master Controller .......................................................................................................................... 240

Channel Controller ........................................................................................................................ 241

Input Stage ................................................................................................................................... 244

Rev. 1.30 7 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Quadrature Decoder ..................................................................................................................... 246

Output Stage ................................................................................................................................. 248

Update Management .................................................................................................................... 252

Single Pulse Mode ........................................................................................................................ 253

Asymmetric PWM Mode ............................................................................................................... 255

Timer Interconnection ................................................................................................................... 256

Trigger ADC Start.......................................................................................................................... 259

PDMA Request ............................................................................................................................. 259

Register Map ..................................................................................................................... 260

Register Descriptions ......................................................................................................... 261

Timer Counter Conguration Register – CNTCFR ....................................................................... 261

Timer Mode Conguration Register – MDCFR ............................................................................. 263

Timer Trigger Conguration Register – TRCFR ............................................................................ 266

Timer Counter Register – CTR ..................................................................................................... 267

Channel 0 Input Conguration Register – CH0ICFR .................................................................... 268

Channel 1 Input Conguration Register – CH1ICFR .................................................................... 270

Channel 2 Input Conguration Register – CH2ICFR .................................................................... 272

Channel 3 Input Conguration Register – CH3ICFR .................................................................... 274

Channel 0 Output Conguration Register – CH0OCFR ............................................................... 276

Channel 1 Output Conguration Register – CH1OCFR ............................................................... 278

Channel 2 Output Conguration Register – CH2OCFR ............................................................... 280

Channel 3 Output Conguration Register – CH3OCFR ............................................................... 282

Channel Control Register – CHCTR ............................................................................................. 284

Channel Polarity Conguration Register – CHPOLR .................................................................... 285

Timer PDMA/Interrupt Control Register – DICTR ......................................................................... 286

Timer Event Generator Register – EVGR ..................................................................................... 288

Timer Interrupt Status Register – INTSR ...................................................................................... 290

Timer Counter Register – CNTR................................................................................................... 293

Timer Prescaler Register – PSCR ................................................................................................ 294

Timer Counter Reload Register – CRR ........................................................................................ 295

Channel 0 Capture/Compare Register – CH0CCR ...................................................................... 296

Channel 1 Capture/Compare Register – CH1CCR ...................................................................... 297

Channel 2 Capture/Compare Register – CH2CCR ...................................................................... 298

Channel 3 Capture/Compare Register – CH3CCR ...................................................................... 299

Channel 0 Asymmetric Compare Register – CH0ACR ................................................................. 300

Channel 1 Asymmetric Compare Register – CH1ACR ................................................................. 301

Channel 2 Asymmetric Compare Register – CH2ACR ................................................................. 302

Channel 3 Asymmetric Compare Register – CH3ACR ................................................................. 303

Table of Contents

15 Basic Function Timer (BFTM) .......................................................................... 304

Introduction ........................................................................................................................ 304

Features ............................................................................................................................. 304

Functional Description ....................................................................................................... 305

Repetitive Mode ............................................................................................................................ 305

One Shot Mode ............................................................................................................................. 306

Rev. 1.30 8 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Register Map ..................................................................................................................... 307

Register Descriptions ......................................................................................................... 307

BFTM Control Register – BFTMCR .............................................................................................. 307

BFTM Status Register – BFTMSR ................................................................................................ 308

BFTM Counter Register – BFTMCNTR ........................................................................................ 309

BFTM Compare Value Register – BFTMCMPR ........................................................................... 310

16 Motor Control Timer (MCTM) ........................................................................... 311

Introduction ........................................................................................................................ 311

Features ............................................................................................................................. 312

Functional Descriptions ..................................................................................................... 313

Counter Mode ............................................................................................................................... 313

Clock Controller ............................................................................................................................ 317

Trigger Controller .......................................................................................................................... 318

Slave Controller ............................................................................................................................ 319

Master Controller .......................................................................................................................... 321

Channel Controller ........................................................................................................................ 322

Input Stage ................................................................................................................................... 325

Output Stage ................................................................................................................................. 327

Update Management .................................................................................................................... 337

Single Pulse Mode ........................................................................................................................ 339

Asymmetric PWM Mode ............................................................................................................... 341

Timer Interconnection ................................................................................................................... 342

Trigger ADC Start.......................................................................................................................... 346

Lock Level Table ........................................................................................................................... 346

PDMA Request ............................................................................................................................. 347

Register Map ..................................................................................................................... 348

Register Descriptions ......................................................................................................... 349

Timer Counter Conguration Register – CNTCFR ....................................................................... 349

Timer Mode Conguration Register – MDCFR ............................................................................. 351

Timer Trigger Conguration Register – TRCFR ............................................................................ 354

Timer Counter Register – CTR ..................................................................................................... 355

Channel 0 Input Conguration Register – CH0ICFR .................................................................... 356

Channel 1 Input Conguration Register – CH1ICFR .................................................................... 358

Channel 2 Input Conguration Register – CH2ICFR .................................................................... 360

Channel 3 Input Conguration Register – CH3ICFR .................................................................... 362

Channel 0 Output Conguration Register – CH0OCFR ............................................................... 364

Channel 1 Output Conguration Register – CH1OCFR ............................................................... 366

Channel 2 Output Conguration Register – CH2OCFR ............................................................... 368

Channel 3 Output Conguration Register – CH3OCFR ............................................................... 370

Channel Control Register – CHCTR ............................................................................................. 372

Channel Polarity Conguration Register – CHPOLR .................................................................... 374

Channel Break Conguration Register – CHBRKCFR ................................................................. 376

Channel Break Control Register – CHBRKCTR ........................................................................... 377

Table of Contents

Rev. 1.30 9 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Timer PDMA/Interrupt Control Register – DICTR ......................................................................... 379

Timer Event Generator Register – EVGR ..................................................................................... 381

Timer Interrupt Status Register – INTSR ...................................................................................... 383

Timer Counter Register – CNTR................................................................................................... 386

Timer Prescaler Register – PSCR ................................................................................................ 387

Timer Counter Reload Register – CRR ........................................................................................ 388

Timer Repetition Register – REPR ............................................................................................... 389

Channel 0 Capture/Compare Register – CH0CCR ...................................................................... 390

Channel 1 Capture/Compare Register – CH1CCR ...................................................................... 391

Channel 2 Capture/Compare Register – CH2CCR ...................................................................... 392

Channel 3 Capture/Compare Register – CH3CCR ...................................................................... 393

Channel 0 Asymmetric Compare Register – CH0ACR ................................................................. 394

Channel 1 Asymmetric Compare Register – CH1ACR ................................................................. 395

Channel 2 Asymmetric Compare Register – CH2ACR ................................................................. 396

Channel 3 Asymmetric Compare Register – CH3ACR ................................................................. 397

Table of Contents

17 Single-Channel Timer (SCTM) ......................................................................... 398

Introduction ........................................................................................................................ 398

Features ............................................................................................................................. 399

Functional Descriptions ..................................................................................................... 399

Counter Mode ............................................................................................................................... 399

Clock Controller ............................................................................................................................ 400

Trigger Controller .......................................................................................................................... 401

Slave Controller ............................................................................................................................ 402

Channel Controller ........................................................................................................................ 404

Input Stage ................................................................................................................................... 406

Output Stage ................................................................................................................................. 407

Update Management .................................................................................................................... 409

Register Map ..................................................................................................................... 410

Register Descriptions ......................................................................................................... 411

Timer Counter Conguration Register – CNTCFR ........................................................................411

Timer Mode Conguration Register – MDCFR ............................................................................. 412

Timer Trigger Conguration Register – TRCFR ............................................................................ 413

Timer Counter Register – CTR ..................................................................................................... 414

Channel Input Conguration Register – CHICFR ......................................................................... 415

Channel Output Conguration Register – CHOCFR .................................................................... 417

Channel Control Register – CHCTR ............................................................................................. 418

Channel Polarity Conguration Register – CHPOLR .................................................................... 419

Timer Interrupt Control Register – DICTR .................................................................................... 420

Timer Event Generator Register – EVGR ..................................................................................... 421

Timer Interrupt Status Register – INTSR ...................................................................................... 422

Timer Counter Register – CNTR................................................................................................... 423

Timer Prescaler Register – PSCR ................................................................................................ 424

Timer Counter Reload Register – CRR ........................................................................................ 425

Channel Capture/Compare Register – CHCCR ........................................................................... 426

Rev. 1.30 10 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

18 Real Time Clock (RTC) ..................................................................................... 427

Introduction ........................................................................................................................ 427

Features ............................................................................................................................. 427

Functional Descriptions ..................................................................................................... 428

RTC Related Register Reset ........................................................................................................ 428

Reading RTC Register .................................................................................................................. 428

Low Speed Clock Conguration ................................................................................................... 428

RTC Counter Operation ................................................................................................................ 429

Interrupt and Wakeup Control ....................................................................................................... 429

RTCOUT Output Pin Conguration............................................................................................... 430

Register Map ..................................................................................................................... 431

Register Descriptions ......................................................................................................... 431

RTC Counter Register – RTCCNT ................................................................................................ 431

RTC Compare Register – RTCCMP ............................................................................................. 432

RTC Control Register – RTCCR ................................................................................................... 433

RTC Status Register – RTCSR..................................................................................................... 435

RTC Interrupt and Wakeup Enable Register – RTCIWEN ............................................................ 436

Table of Contents

19 Watchdog Timer (WDT) .................................................................................... 437

Introduction ........................................................................................................................ 437

Features ............................................................................................................................. 437

Functional Description ....................................................................................................... 438

Register Map ..................................................................................................................... 440

Register Descriptions ......................................................................................................... 440

Watchdog Timer Control Register – WDTCR ............................................................................... 440

Watchdog Timer Mode Register 0 – WDTMR0............................................................................. 441

Watchdog Timer Mode Register 1 – WDTMR1............................................................................. 442

Watchdog Timer Status Register – WDTSR ................................................................................. 443

Watchdog Timer Protection Register – WDTPR ........................................................................... 444

Watchdog Timer Clock Selection Register – WDTCSR ................................................................ 445

20 Inter-Integrated Circuit (I2C) ............................................................................. 446

Introduction ........................................................................................................................ 446

Features ............................................................................................................................. 447

Functional Descriptions ..................................................................................................... 447

Two Wire Serial Interface .............................................................................................................. 447

START and STOP Conditions ....................................................................................................... 447

Data Validity .................................................................................................................................. 448

Addressing Format ....................................................................................................................... 449

Data Transfer and Acknowledge ................................................................................................... 451

Clock Synchronization .................................................................................................................. 452

Arbitration ..................................................................................................................................... 452

General Call Addressing ............................................................................................................... 453

Rev. 1.30 11 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Bus Error ....................................................................................................................................... 453

Address Mask Enable ................................................................................................................... 453

Address Snoop ............................................................................................................................. 453

Operation Mode ............................................................................................................................ 453

Conditions of Holding SCL Line .................................................................................................... 459

I2C Timeout Function .................................................................................................................... 460

PDMA Interface ............................................................................................................................. 460

Register Map ..................................................................................................................... 461

Register Descriptions ......................................................................................................... 462

I2C Control Register – I2CCR ....................................................................................................... 462

I2C Interrupt Enable Register – I2CIER ........................................................................................ 464

I2C Address Register – I2CADDR ................................................................................................. 466

I2C Status Register – I2CSR ......................................................................................................... 467

I2C SCL High Period Generation Register – I2CSHPGR .............................................................. 470

I2C SCL Low Period Generation Register – I2CSLPGR ............................................................... 471

I2C Data Register – I2CDR ........................................................................................................... 472

I2C Target Register – I2CTAR ....................................................................................................... 473

I2C Address Mask Register – I2CADDMR .................................................................................... 474

I2C Address Snoop Register – I2CADDSR ................................................................................... 475

I2C Timeout Register – I2CTOUT.................................................................................................. 476

Table of Contents

21 Serial Peripheral Interface (SPI) ...................................................................... 477

Introduction ........................................................................................................................ 477

Features ............................................................................................................................. 478

Function Descriptions ........................................................................................................ 478

Master Mode ................................................................................................................................. 478

Slave Mode ................................................................................................................................... 478

SPI Serial Frame Format .............................................................................................................. 479

Status Flags .................................................................................................................................. 483

Register Map ..................................................................................................................... 486

Register Descriptions ......................................................................................................... 486

SPI Control Register 0 – SPICR0 ................................................................................................. 486

SPI Control Register 1 – SPICR1 ................................................................................................. 488

SPI Interrupt Enable Register – SPIIER ....................................................................................... 490

SPI Clock Prescaler Register – SPICPR ...................................................................................... 491

SPI Data Register – SPIDR .......................................................................................................... 492

SPI Status Register – SPISR ........................................................................................................ 493

SPI FIFO Control Register – SPIFCR ........................................................................................... 495

SPI FIFO Status Register – SPIFSR ............................................................................................ 496

SPI FIFO Time Out Counter Register – SPIFTOCR ..................................................................... 497

22 Universal Synchronous Asynchronous Receiver Transmitter (USART) ..... 498

Introduction ........................................................................................................................ 498

Features ............................................................................................................................. 499

Rev. 1.30 12 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Function Descriptions ........................................................................................................ 500

Serial Data Format ........................................................................................................................ 500

Baud Rate Generation .................................................................................................................. 501

Hardware Flow Control ................................................................................................................. 502

IrDA ............................................................................................................................................... 504

RS485 Mode ................................................................................................................................. 506

Synchronous Master Mode ........................................................................................................... 509

Interrupts and Status .....................................................................................................................511

PDMA Interface ..............................................................................................................................511

Register Map ..................................................................................................................... 511

Register Descriptions ......................................................................................................... 512

USART Data Register – USRDR .................................................................................................. 512

USART Control Register – USRCR .............................................................................................. 513

USART FIFO Control Register – USRFCR................................................................................... 515

USART Interrupt Enable Register – USRIER ............................................................................... 516

USART Status & Interrupt Flag Register – USRSIFR................................................................... 518

USART Timing Parameter Register – USRTPR ........................................................................... 520

USART IrDA Control Register – IrDACR ...................................................................................... 521

USART RS485 Control Register – RS485CR............................................................................... 522

USART Synchronous Control Register – SYNCR ........................................................................ 523

USART Divider Latch Register – USRDLR................................................................................... 524

USART Test Register – USRTSTR ............................................................................................... 525

Table of Contents

23 Universal Asynchronous Receiver Transmitter (UART) ................................ 526

Introduction ........................................................................................................................ 526

Features ............................................................................................................................. 527

Function Descriptions ........................................................................................................ 527

Serial Data Format ........................................................................................................................ 527

Baud Rate Generation .................................................................................................................. 528

Interrupts and Status .................................................................................................................... 529

PDMA Interface ............................................................................................................................. 529

Register Map ..................................................................................................................... 530

Register Descriptions ......................................................................................................... 530

UART Data Register – URDR ....................................................................................................... 530

UART Control Register – URCR ................................................................................................... 531

UART Interrupt Enable Register – URIER .................................................................................... 533

UART Status & Interrupt Flag Register – URSIFR ....................................................................... 534

UART Divider Latch Register – URDLR ....................................................................................... 536

UART Test Register – URTSTR .................................................................................................... 537

24 Smart Card Interface (SCI) ............................................................................... 538

Introduction ........................................................................................................................ 538

Features ............................................................................................................................. 539

Functional Descriptions ..................................................................................................... 539

Rev. 1.30 13 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Elementary Time Unit Counter ...................................................................................................... 539

Guard Time Counter ..................................................................................................................... 541

Waiting Time Counter ................................................................................................................... 542

Card Clock and Data Selection ..................................................................................................... 543

Card Detection ............................................................................................................................. 543

SCI Data Transfer Mode ............................................................................................................... 544

Interrupt Generator ....................................................................................................................... 546

PDMA Interface ............................................................................................................................. 547

Register Map ..................................................................................................................... 547

Register Descriptions ......................................................................................................... 548

SCI Control Register – CR ............................................................................................................ 548

SCI Status Register – SR ............................................................................................................. 550

SCI Contact Control Register – CCR ............................................................................................ 552

SCI Elementary Time Unit Register – ETUR ................................................................................ 553

SCI Guard Time Register – GTR .................................................................................................. 554

SCI Waiting Time Register – WTR................................................................................................ 555

SCI Interrupt Enable Register – IER ............................................................................................. 556

SCI Interrupt Pending Register – IPR ........................................................................................... 558

SCI Transmit Buffer – TXB............................................................................................................ 560

SCI Receive Buffer – RXB ............................................................................................................ 560

SCI Prescaler Register – PSCR ................................................................................................... 561

Table of Contents

25 USB Device Controller (USB) .......................................................................... 562

Introduction ........................................................................................................................ 562

Features ............................................................................................................................. 562

Functional Descriptions ..................................................................................................... 563

Endpoints ...................................................................................................................................... 563

EP-SRAM ..................................................................................................................................... 563

Serial Interface Engine – SIE ........................................................................................................ 564

Double-Buffering ........................................................................................................................... 564

Suspend Mode and Wake-up ....................................................................................................... 566

Remote Wake-up .......................................................................................................................... 566

Register Map ..................................................................................................................... 566

Register Descriptions ......................................................................................................... 568

USB Control and Status Register – USBCSR .............................................................................. 568

USB Interrupt Enable Register – USBIER .................................................................................... 570

USB Interrupt Status Register – USBISR ..................................................................................... 571

USB Frame Count Register – USBFCR ....................................................................................... 573

USB Device Address Register – USBDEVA ................................................................................. 574

USB Endpoint 0 Control and Status Register – USBEP0CSR ..................................................... 575

USB Endpoint 0 Interrupt Enable Register – USBEP0IER ........................................................... 576

USB Endpoint 0 Interrupt Status Register – USBEP0ISR ............................................................ 578

USB Endpoint 0 Transfer Count Register – USBEP0TCR ........................................................... 579

USB Endpoint 0 Conguration Register – USBEP0CFGR ........................................................... 580

Rev. 1.30 14 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

USB Endpoint 1 ~ 3 Control and Status Register – USBEPnCSR, n = 1 ~ 3 ............................... 581

USB Endpoint 1 ~ 3 Interrupt Enable Register – USBEPnIER, n = 1 ~ 3 ..................................... 582

USB Endpoint 1 ~ 3 Interrupt Status Register – USBEPnISR, n = 1 ~ 3 ...................................... 583

USB Endpoint 1 ~ 3 Transfer Count Register – USBEPnTCR, n = 1 ~ 3 ..................................... 584

USB Endpoint 1 ~ 3 Conguration Register – USBEPnCFGR, n = 1 ~ 3 ..................................... 585

USB Endpoint 4 ~ 7 Control and Status Register – USBEPnCSR, n = 4 ~ 7 ............................... 586

USB Endpoint 4 ~ 7 Interrupt Enable Register – USBEPnIER, n = 4 ~ 7 ..................................... 589

USB Endpoint 4 ~ 7 Interrupt Status Register – USBEPnISR, n = 4 ~ 7 ...................................... 590

USB Endpoint 4 ~ 7 Transfer Count Register – USBEPnTCR, n = 4 ~ 7 ..................................... 591

USB Endpoint 4 ~ 7 Conguration Register – USBEPnCFGR, n = 4 ~ 7 ..................................... 592

26 Peripheral Direct Memory Access (PDMA) ..................................................... 593

Introduction ........................................................................................................................ 593

Features ............................................................................................................................. 593

Functional Description ....................................................................................................... 594

AHB Master .................................................................................................................................. 594

PDMA Channel ............................................................................................................................. 594

PDMA Request Mapping .............................................................................................................. 594

Channel transfer ........................................................................................................................... 596

Channel Priority ............................................................................................................................ 596

Transfer Request .......................................................................................................................... 597

Address Mode ............................................................................................................................... 597

Auto-Reload .................................................................................................................................. 597

Transfer Interrupt .......................................................................................................................... 598

Register Map ..................................................................................................................... 598

Register Descriptions ......................................................................................................... 600

PDMA Channel n Control Register – PDMACHnCR, n = 0 ~ 5 .................................................... 600

PDMA Channel n Source Address Register – PDMACHnSADR, n = 0 ~ 5 .................................. 602

PDMA Channel n Destination Address Register – PDMACHnDADR, n=0~5 ............................... 603

PDMA Channel n Transfer Size Register – PDMACHnTSR, n = 0 ~ 5 ......................................... 604

PDMA Channel n Current Transfer Size Register – PDMACHnCTSR, n=0~5 ............................. 605

PDMA Interrupt Status Register – PDMAISR ............................................................................... 606

PDMA Interrupt Status Clear Register – PDMAISCR ................................................................... 607

PDMA Interrupt Enable Register – PDMAIER .............................................................................. 609

Table of Contents

27 Extend Bus Interface (EBI) ............................................................................... 610

Introduction ........................................................................................................................ 610

Features ............................................................................................................................. 610

Function Descriptions ........................................................................................................ 611

Non-multiplexed 8-bit Data 8-bit Address Mode ........................................................................... 612

Non-multiplexed 16-bit Data N-bit Address Mode ......................................................................... 613

Multiplexed 16-bit Data, 16-bit Address Mode .............................................................................. 614

Multiplexed 8-bit Data, 20-bit Address Mode ................................................................................ 615

Write Buffer and EBI Status .......................................................................................................... 616

Rev. 1.30 15 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Bus Turn-around and Idle Cycles ................................................................................................. 616

AHB Transaction Width Conversion ............................................................................................. 617

EBI Bank Access .......................................................................................................................... 619

PDMA Request ............................................................................................................................. 620

Register Map ..................................................................................................................... 620

Register Descriptions ......................................................................................................... 620

EBI Control Register – EBICR ...................................................................................................... 620

EBI Status Register – EBISR ........................................................................................................ 622

EBI Address Timing Register – EBIATR ....................................................................................... 623

EBI Read Timing Register – EBIRTR ........................................................................................... 624

EBI Write Timing Register – EBIWTR ........................................................................................... 625

EBI Parity Register – EBIPR ......................................................................................................... 626

28 Inter-IC Sound (I2S) ........................................................................................... 627

Introduction ........................................................................................................................ 627

Features ............................................................................................................................. 627

Functional Description ....................................................................................................... 628

I2S Master and Slave Mode .......................................................................................................... 628

I2S Clock Rate Generator ............................................................................................................. 629

I2S Interface Format ...................................................................................................................... 631

FIFO Control and Arrangement .................................................................................................... 638

PDMA and Interrupt ...................................................................................................................... 639

Register Map ..................................................................................................................... 639

Register Descriptions ......................................................................................................... 640

I2S Control Register – I2SCR ........................................................................................................ 640

I2S Interrupt Enable Register – I2SIER ......................................................................................... 642

I2S Clock Divider Register – I2SCDR ........................................................................................... 643

I2S TX Data Register – I2STXDR ................................................................................................. 644

I2S RX Data Register – I2SRXDR ................................................................................................. 644

I2S FIFO Control Register – I2SFCR ............................................................................................ 645

I2S Status Register – I2SSR ......................................................................................................... 646

I2S Rate Counter Value Register – I2SRCNTR ............................................................................ 648

Table of Contents

29 Cyclic Redundancy Check (CRC) .................................................................... 649

Introduction ....................................................................................................................... 649

Features ............................................................................................................................. 650

Function Descriptions ........................................................................................................ 650

CRC Computation ......................................................................................................................... 650

Byte and Bit Reversal for CRC Computation ................................................................................ 650

CRC with PDMA ........................................................................................................................... 651

Register Map ..................................................................................................................... 651

Register Descriptions ......................................................................................................... 652

CRC Control Register – CRCCR .................................................................................................. 652

CRC Seed Register – CRCSDR ................................................................................................... 653

Rev. 1.30 16 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

CRC Checksum Register – CRCCSR .......................................................................................... 654

CRC Data Register – CRCDR ...................................................................................................... 655

Table of Contents

Rev. 1.30 17 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

List of Tables

Table 1. Series Features and Peripheral List .......................................................................................... 32

Table 2. Document Conventions ............................................................................................................. 34

Table 3. Register Map ............................................................................................................................. 39

Table 4. Flash Memory and Option Byte ................................................................................................. 44

Table 5. Relationship Between Wait State Cycle and HCLK .................................................................. 44

Table 6. Booting Modes .......................................................................................................................... 45

Table 7. Option Byte Memory Map ......................................................................................................... 49

Table 8. Access Permission of Protected Main Flash Page .................................................................... 50

Table 9. Access Permission When Security Protection is Enabled ......................................................... 51

Table 10. FMC Register Map .................................................................................................................. 52

Table 11. Operation Mode Denitions ..................................................................................................... 72

Table 12. Enter/Exit Power Saving Modes .............................................................................................. 73

Table 13. Power Status After System Reset ........................................................................................... 74

Table 14. PWRCU Register Map ............................................................................................................ 74

Table 15. Output Divider2 Value Mapping............................................................................................... 88

Table 16. Feedback Divider2 Value Mapping.......................................................................................... 88

Table 17. CKOUT Clock Source ............................................................................................................. 91

Table 18. CKCU Register Map ............................................................................................................... 92

Table 19. RSTCU Register Map ........................................................................................................... 121

Table 20. AFIO, GPIO and IO Pad Control Signal True Table............................................................... 129

Table 21. GPIO Register Map ............................................................................................................... 130

Table 22. AFIO Selection for Peripheral Map Example ......................................................................... 177

Table 23. AFIO Register Map ................................................................................................................ 177

Table 24. Exception Types .................................................................................................................... 182

Table 25. NVIC Register Map ............................................................................................................... 184

Table 26. EXTI Register Map ................................................................................................................ 188

Table 27. Data format in ADCDR [15:0] ................................................................................................ 203

Table 28. A/D Converter Register Map ................................................................................................. 205

Table 29. CMP Register Map ................................................................................................................ 224

Table 30. Counting Direction and Encoding Signals ............................................................................. 247

Table 31. Compare Match Output Setup .............................................................................................. 248

Table 32. GPTM Register Map ............................................................................................................. 260

Table 33. GPTM Internal Trigger Connection ....................................................................................... 266

Table 34. BFTM Register Map .............................................................................................................. 307

Table 35. Compare Match Output Setup .............................................................................................. 328

Table 36. Output Control Bits for Complementary Output with a Break Event Occurrence .................. 336

Table 37. Lock Level Table.................................................................................................................... 346

Table 38. MCTM Register Map ............................................................................................................. 348

Table 39. MCTM Internal Trigger Connection ....................................................................................... 354

List of Tables

Rev. 1.30 18 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Table 40. Compare Match Output Setup .............................................................................................. 407

Table 41. SCTM Register Map .............................................................................................................. 410

Table 42. LSE Startup Mode Operating Current and Startup Time ....................................................... 428

Table 43. RTCOUT Output Mode and Active Level Setting .................................................................. 430

Table 44. RTC Register Map................................................................................................................. 431

Table 45. Watchdog Timer Register Map .............................................................................................. 440

Table 46. Conditions of Holding SCL line .............................................................................................. 459

Table 47. I2C Register Map ................................................................................................................... 461

Table 48. I2C Clock Setting Example .................................................................................................... 471

Table 49. SPI Interface Format Setup ................................................................................................... 479

Table 50. SPI Mode Fault Trigger Conditions ....................................................................................... 484

Table 51. SPI Master Mode SEL Pin Status ......................................................................................... 484

Table 52. SPI Register Map .................................................................................................................. 486

Table 53. Baud Rate Deviation Error Calculation – CK_USART = 40 MHz .......................................... 501

Table 54. Baud Rate Deviation Error Calculation – CK_USART = 48 MHz .......................................... 502

Table 55. USART Register Map .............................................................................................................511

Table 56. Baud Rate Deviation Error Calculation – CK_UART = 40 MHz ............................................ 528

Table 57. Baud Rate Deviation Error Calculation – CK_UART = 48 MHz ............................................ 529

Table 58. UART Register Map .............................................................................................................. 530

Table 59. DI Field Based Di Encoded Decimal Values ......................................................................... 540

Table 60. FI Field Based Fi Encoded Decimal Values .......................................................................... 540

Table 61. Possible ETU Values Obtained with the Fi/Di Ratio .............................................................. 540

Table 62. SCI Register Map ................................................................................................................. 547

Table 63. Endpoint Characteristics ....................................................................................................... 563

Table 64. USB Data Types and Buffer Size .......................................................................................... 563

Table 65. USB Register Map ................................................................................................................ 566

Table 66. Resume Event Detection ...................................................................................................... 569

Table 67. PDMA Channel Assignments ................................................................................................ 595

Table 68. PDMA Address Modes .......................................................................................................... 597

Table 69. PDMA Register Map .............................................................................................................. 598

Table 70. EBI Maps AHB Transactions Width to External Device Transactions. .................................. 618

Table 71. EBI Maps AHB Transactions Width to External Device Transactions Width ......................... 618

Table 72. EBI Register Map .................................................................................................................. 620

Table 73. Recommend FS List @ 8 MHz PCLK ................................................................................... 630

Table 74. Recommend FS List @ 48 MHz PCLK ................................................................................. 630

Table 75. I2S Register Map .................................................................................................................. 639

Table 76. CRC Register Map ................................................................................................................ 651

List of Tables

Rev. 1.30 19 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

List of Figures

Figure 1. Block Diagram ......................................................................................................................... 33

Figure 2. Cortex®-M0+ Block Diagram .................................................................................................... 36

Figure 3. Bus Architecture ...................................................................................................................... 37

Figure 4. Memory Map ............................................................................................................................ 38

Figure 5. Flash Memory Controller Block Diagram ................................................................................. 42

Figure 6. Flash Memory Map .................................................................................................................. 43

Figure 7. Vector Remapping ................................................................................................................... 45

Figure 8. Page Erase Operation Flowchart ............................................................................................ 46

Figure 9. Mass Erase Operation Flowchart ............................................................................................ 47

Figure 10. Word Programming Operation Flowchart .............................................................................. 48

Figure 11. PWRCU Block Diagram ......................................................................................................... 68

Figure 12. Power On Reset / Power Down Reset Waveform ................................................................. 71

Figure 13. CKCU Block Diagram ............................................................................................................ 83

Figure 14. External Crystal, Ceramic, and Resonators for HSE ............................................................. 84

Figure 15. HSI Auto Trimming Block Diagram ....................................................................................... 86

Figure 16. PLL Block Diagram ................................................................................................................ 87

Figure 17. External Crystal, Ceramic, and Resonators for LSE ............................................................ 89

Figure 18. RSTCU Block Diagram .........................................................................................................119

Figure 19. Power On Reset Sequence ................................................................................................. 120

Figure 20. GPIO Block Diagram ........................................................................................................... 127

Figure 21. AFIO/GPIO Control Signal ................................................................................................... 129

Figure 22. AFIO Block Diagram ............................................................................................................ 175

Figure 23. EXTI Channel Input Selection ............................................................................................. 176

Figure 24. EXTI Block Diagram ............................................................................................................ 185

Figure 25. EXTI Wake-up Event Management ..................................................................................... 186

Figure 26. EXTI Interrupt Debounce Function ...................................................................................... 187

Figure 27. ADC Block Diagram ............................................................................................................. 197

Figure 28. One Shot Conversion Mode ................................................................................................ 200

Figure 29. Continuous Conversion Mode ............................................................................................. 200

Figure 30. Discontinuous Conversion Mode ......................................................................................... 202

Figure 31. Comparator Block Diagram ................................................................................................. 221

Figure 32. 6-Bit Scaler for Comparator Voltage Reference Block Diagram .......................................... 222

Figure 33. Interrupt Signals of Comparators ......................................................................................... 223

Figure 34. Wakeup Signals of Comparators ......................................................................................... 223

Figure 35. GPTM Block Diagram .......................................................................................................... 230

Figure 36. Up-counting Example .......................................................................................................... 232

Figure 37. Down-counting Example ...................................................................................................... 233

Figure 38. Center-aligned Counting Example ....................................................................................... 234

Figure 39. GPTM Clock Selection Source ............................................................................................ 235

List of Figures

Rev. 1.30 20 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Figure 40. Trigger Controller Block ....................................................................................................... 236

Figure 41. Slave Controller Diagram .................................................................................................... 237

Figure 42. GPTM in Restart Mode ........................................................................................................ 237

Figure 43. GPTM in Pause Mode ......................................................................................................... 238

Figure 44. GPTM in Trigger Mode ........................................................................................................ 239

Figure 45. Master GPTMn and Slave GPTMm/MCTMm Connection ................................................... 240

Figure 46. MTO Selection ..................................................................................................................... 240

Figure 47. Capture/Compare Block Diagram ........................................................................................ 241

Figure 48. Input Capture Mode ............................................................................................................. 242

Figure 49. PWM Pulse Width Measurement Example .......................................................................... 243

Figure 50. Channel 0 and Channel 1 Input Stages ............................................................................... 244

Figure 51. Channel 2 and Channel 3 Input Stages ............................................................................... 245

Figure 52. TI0 Digital Filter Diagram with N = 2 .................................................................................... 245

Figure 53. Input Stage and Quadrature Decoder Block Diagram ......................................................... 246

Figure 54. Both TI0 and TI1 Quadrature Decoder Counting ................................................................. 247

Figure 55. Output Stage Block Diagram ............................................................................................... 248

Figure 56. Toggle Mode Channel Output Reference Signal (CHxPRE = 0) ......................................... 249

Figure 57. Toggle Mode Channel Output Reference Signal (CHxPRE = 1) ......................................... 249

Figure 58. PWM Mode Channel Output Reference Signal and Counter in Up-counting Mode ............ 250

Figure 59. PWM Mode Channel Output Reference Signal and Counter in Down-counting Mode ....... 250

Figure 60. PWM Mode Channel Output Reference Signal and Counter in Centre-align Mode ............ 251

Figure 61. Update Event Setting Diagram ............................................................................................ 252

Figure 62. Single Pulse Mode ............................................................................................................... 253

Figure 63. Immediate Active Mode Minimum Delay ............................................................................. 254

Figure 64. Asymmetric PWM mode versus center align counting mode .............................................. 255

Figure 65. Pausing GPTM1 using the GPTM0 CH0OREF Signal ........................................................ 256

Figure 66. Triggering GPTM1 with GPTM0 Update Event .................................................................... 257

Figure 67. Trigger GPTM0 and GPTM1 with the GPTM0 CH0 Input .................................................... 258

Figure 68. GPTM PDMA Mapping Diagram .......................................................................................... 259

Figure 69. BFTM Block Diagram .......................................................................................................... 304

Figure 70. BFTM – Repetitive Mode ..................................................................................................... 305

Figure 71. BFTM – One Shot Mode ...................................................................................................... 306

Figure 72. BFTM – One Shot Mode Counter Updating ....................................................................... 306

Figure 73. MCTM Block Diagram ..........................................................................................................311

Figure 74. Up-counting Example .......................................................................................................... 313

Figure 75. Down-counting Example ...................................................................................................... 314

Figure 76. Center-aligned Counting Example ....................................................................................... 315

Figure 77. Update Event 1 Dependent Repetition Mechanism Example .............................................. 316

Figure 78. MCTM Clock Selection Source ............................................................................................ 317

Figure 79. Trigger Controller Block ....................................................................................................... 318

Figure 80. Slave Controller Diagram .................................................................................................... 319

List of Figures

Rev. 1.30 21 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Figure 81. MCTM in Restart Mode ....................................................................................................... 319

Figure 82. MCTM in Pause Mode ......................................................................................................... 320

Figure 83. MCTM in Trigger Mode ........................................................................................................ 320

Figure 84. Master MCTMn and Slave GPTMm Connection ................................................................. 321

Figure 85. MTO Selection ..................................................................................................................... 321

Figure 86. Capture/Compare Block Diagram ........................................................................................ 322

Figure 87. Input Capture Mode ............................................................................................................. 323

Figure 88. PWM Pulse Width Measurement Example .......................................................................... 324

Figure 89. Channel 0 and Channel 1 Input Stages ............................................................................... 325

Figure 90. Channel 2 and Channel 3 Input Stages ............................................................................... 325

Figure 91. TI0 Digital Filter Diagram with N = 2 .................................................................................... 326

Figure 92. Output Stage Block Diagram ............................................................................................... 327

Figure 93. Toggle Mode Channel Output Reference Signal – CHxPRE = 0 ......................................... 328

Figure 94. Toggle Mode Channel Output Reference Signal – CHxPRE = 1 ......................................... 329

Figure 95. PWM Mode Channel Output Reference Signal and Counter in Up-counting Mode ............ 329

Figure 96. PWM Mode Channel Output Reference Signal and Counter in Down-counting Mode ....... 330

Figure 97. PWM Mode 1 Channel Output Reference Signal and Counter in Centre-aligned Counting

Mode ...................................................................................................................................................... 330

Figure 98. Dead-time Insertion Performed for Complementary Outputs .............................................. 331

Figure 99. MCTM Break Signal Bolck Diagram .................................................................................... 332

Figure 100. MT_BRK Pin Digital Filter Diagram with N = 2 .................................................................. 332

Figure 101. Channel 3 Output with a Break Event Occurrence ............................................................ 333

Figure 102. Channel 0 ~ 2 Complementary Outputs with a Break Event Occurrence.......................... 334

Figure 103. Channel 0 ~ 2 Only One Output Enabled when Fault Event Occurs ................................. 334

Figure 104. Hardware Protection When Both CHxO and CHxNO Are in Active Condition ................... 335

Figure 105. Update Event 1 Setup Diagram ......................................................................................... 337

Figure 106. CHxE, CHxNE and CHxOM Updated by Update Event 2 ................................................. 338

Figure 107. Update Event 2 Setup Diagram ......................................................................................... 338

Figure 108. Single Pulse Mode ............................................................................................................. 339

Figure 109. Immediate Active Mode Minimum Delay ........................................................................... 340

Figure 110. Asymmetric PWM Mode versus Center-aligned Counting Mode ....................................... 341

Figure 111. Pausing GPTM using the MCTM CH0OREF Signal .......................................................... 342

Figure 112. Triggering GPTM with MCTM Update Event 1................................................................... 343

Figure 113. Trigger MCTM and GPTM with the MCTM CH0 Input ....................................................... 344

Figure 114. CH1XOR Input as Hall Sensor Interface............................................................................ 345

Figure 115. MCTM PDMA Mapping Diagram........................................................................................ 347

Figure 116. SCTM Block Diagram ........................................................................................................ 398

Figure 117. Up-counting Example......................................................................................................... 399

Figure 118. SCTM Clock Selection Source........................................................................................... 400

Figure 119. Trigger Controller Block ..................................................................................................... 401

Figure 120. Slave Controller Diagram .................................................................................................. 402

List of Figures

Rev. 1.30 22 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Figure 121. SCTM in Restart Mode ...................................................................................................... 402

Figure 122. SCTM in Pause Mode ....................................................................................................... 403

Figure 123. SCTM in Trigger Mode ...................................................................................................... 403

Figure 124. Capture/Compare Block Diagram ...................................................................................... 404

Figure 125. Input Capture Mode ........................................................................................................... 405

Figure 126. Channel Input Stages ........................................................................................................ 406

Figure 127. TI Digital Filter Diagram with N = 2 .................................................................................... 406

Figure 128. Output Stage Block Diagram ............................................................................................. 407

Figure 129. Toggle Mode Channel Output Reference Signal (CHPRE = 0) ......................................... 408

Figure 130. Toggle Mode Channel Output Reference Signal (CHPRE = 1) ......................................... 408

Figure 131. PWM Mode Channel Output Reference Signal ................................................................. 409

Figure 132. Update Event Setting Diagram .......................................................................................... 410

Figure 133. RTC Block Diagram ........................................................................................................... 427

Figure 134. Watchdog Timer Block Diagram ....................................................................................... 437

Figure 135. Watchdog Timer Behavior ................................................................................................. 439

Figure 136. I2C Module Block Diagram ................................................................................................. 446

Figure 137. START and STOP Condition ............................................................................................. 448

Figure 138. Data Validity ....................................................................................................................... 448

Figure 139. 7-bit Addressing Mode ....................................................................................................... 449

Figure 140. 10-bit Addressing Write Transmit Mode ............................................................................ 450

Figure 141. 10-bit Addressing Read Receive Mode ............................................................................ 450

Figure 142. I2C Bus Acknowledge ........................................................................................................ 451

Figure 143. Clock Synchronization during Arbitration ........................................................................... 452

Figure 144. Two Master Arbitration Procedure ..................................................................................... 452

Figure 145. Master Transmitter Timing Diagram .................................................................................. 454

Figure 146. Master Receiver Timing Diagram ...................................................................................... 456

Figure 147. Slave Transmitter Timing Diagram .................................................................................... 457

Figure 148. Slave Receiver Timing Diagram ........................................................................................ 458

Figure 149. SCL Timing Diagram .......................................................................................................... 471

Figure 150. SPI Block Diagram ............................................................................................................ 477

Figure 151. SPI Single Byte Transfer Timing Diagram – CPOL = 0, CPHA = 0 .................................... 479

Figure 152. SPI Continuous Data Transfer Timing Diagram – CPOL = 0, CPHA = 0 ........................... 480

Figure 153. SPI Single Byte Transfer Timing Diagram – CPOL = 0, CPHA = 1 .................................... 480

Figure 154. SPI Continuous Transfer Timing Diagram – CPOL = 0, CPHA = 1 .................................... 481

Figure 155. SPI Single Byte Transfer Timing Diagram – CPOL = 1, CPHA = 0 .................................... 481

Figure 156. SPI Continuous Transfer Timing Diagram – CPOL = 1, CPHA = 0 .................................... 482

Figure 157. SPI Single Byte Transfer Timing Diagram – CPOL = 1, CPHA = 1 .................................... 482

Figure 158. SPI Continuous Transfer Timing Diagram – CPOL = 1, CPHA = 1 .................................... 482

Figure 159. SPI Multi-Master Slave Environment ................................................................................. 484

Figure 160. USART Block Diagram ...................................................................................................... 498

Figure 161. USART Serial Data Format ............................................................................................... 500

List of Figures

Rev. 1.30 23 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Figure 162. USART Clock CK_USART and Data Frame Timing .......................................................... 501

Figure 163. Hardware Flow Control between 2 USARTs ...................................................................... 502

Figure 164. USART RTS Flow Control ................................................................................................. 503

Figure 165. USART CTS Flow Control ................................................................................................. 503

Figure 166. IrDA Modulation and Demodulation ................................................................................... 504

Figure 167. USART I/O and IrDA Block Diagram ................................................................................. 506

Figure 168. RS485 Interface and Waveform ........................................................................................ 507

Figure 169. USART Synchronous Transmission Example ................................................................... 509

Figure 170. 8-bit Format USART Synchronous Waveform ................................................................... 510

Figure 171. UART Block Diagram ......................................................................................................... 526

Figure 172. UART Serial Data Format .................................................................................................. 527

Figure 173. UART Clock CK_UART and Data Frame Timing ............................................................... 528

Figure 174. SCI Block Diagram ............................................................................................................ 538

Figure 175. Character Frame and Compensation Mode ...................................................................... 541

Figure 176. Guard Time Duration ......................................................................................................... 542

Figure 177. Character and Block Waiting Time Duration – CWT and BWT .......................................... 543

Figure 178. SCI Card Detection Diagram ............................................................................................. 544

Figure 179. SCI Interrupt Structure ....................................................................................................... 546

Figure 180. USB Block Diagram ........................................................................................................... 562

Figure 181. Endpoint Buffer Allocation Example................................................................................... 564

Figure 182. Double-buffering Operation Example ................................................................................ 565

Figure 183. PDMA Block Diagram ........................................................................................................ 593

Figure 184. PDMA Request Mapping Architecture ............................................................................... 595

Figure 185. PDMA Channel Arbitration and Scheduling Example ........................................................ 596

Figure 186. EBI Block Diagram .............................................................................................................611

Figure 187. EBI Non-multiplexed 8-bit Data, 8-bit Address Read Operation ........................................ 612

Figure 188. EBI Non-multiplexed 8-bit Data, 8-bit Address Write Operation ........................................ 612

Figure 189. EBI Non-multiplexed 16-bit Data, N-bit Address Read Operation ..................................... 613

Figure 190. EBI Non-multiplexed 16-bit Data, N-bit Address Write Operation...................................... 613

Figure 191. An EBI Address Latch Setup Diagram ............................................................................... 614

Figure 192. EBI Multiplexed 16-bit Data, 16-bit Address Read Operation ............................................ 614

Figure 193. EBI Multiplexed 16-bit Data, 16-bit Address Write Operation ............................................ 615

Figure 194. EBI Multiplexed 8-bit Data, 20-bit Address Read Operation .............................................. 615

Figure 195. EBI Multiplexed 8-bit Data, 20-bit Address Write Operation .............................................. 616

Figure 196. EBI Inserts an IDLE Cycle between Transactions in the Same Bank (NOIDLE = 0) ......... 617

Figure 197. EBI De-asserts an IDLE Cycle between Transactions in the Same Bank (NOIDLE = 1) .. 617

Figure 198. EBI Bank Memory Map ...................................................................................................... 619

Figure 199. I2S Block Diagram .............................................................................................................. 627

Figure 200. Simple I2S Master/Slave Conguration .............................................................................. 628

Figure 201. I2S Clock Generator Diagram ............................................................................................ 629

Figure 202. I2S-justied Stereo Mode Waveforms ................................................................................ 631

List of Figures

Rev. 1.30 24 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Figure 203. I2S-justied Stereo Mode Waveforms (32-bit Channel Enabled) ....................................... 631

Figure 204. Left-justied Stereo Mode Waveforms ............................................................................... 632

Figure 205. Left-justied Stereo Mode Waveforms (32-bit Channel Enabled) ...................................... 632

Figure 206. Right-justied Stereo Mode Waveforms ............................................................................ 633

Figure 207. Right-justied Stereo Mode Waveforms (32-bit Channel Enabled) ................................... 633

Figure 208. I2S-justied Mono Mode Waveforms .................................................................................. 634

Figure 209. I2S-justied Mono Mode Waveforms (32-bit Channel Enabled) ......................................... 634

Figure 210. Left-justied Mono Mode Waveforms ................................................................................ 635

Figure 211. Left-justied Mono Mode Waveforms (32-bit Channel Enabled) ....................................... 635

Figure 212. Right-justied Mono Mode Waveforms .............................................................................. 636

Figure 213. Right-justied Mono Mode Waveforms (32-bit Channel Enabled) ..................................... 636

Figure 214. I2S-justied Repeat Mode Waveforms ............................................................................... 637

Figure 215. I2S-justied Repeat Mode Waveforms (32-bit Channel Enabled) ...................................... 637

Figure 216. FIFO Data Content Arrangement for Various Modes ......................................................... 638

Figure 217. CRC Block Diagram .......................................................................................................... 649

Figure 218. CRC Data Bit and Byte Reversal Example ........................................................................ 651

List of Figures

Rev. 1.30 25 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

1

Overview

Introduction

This user manual provides detailed information including how to use the devices, system and
bus architecture, memory organization and peripheral instructions. The target audiences for this
document are software developers, application developers and hardware developers. For more
information regarding pin assignment, package and electrical characteristics, please refer to the
datasheet.

The devices are high performance and low power consumption 32-bit microcontrollers based
around an Arm® Cortex®-M0+ processor core. The Cortex®-M0+ is a next-generation processor
core which is tightly coupled with Nested Vectored Interrupt Controller (NVIC), SysTick timer,
and including advanced debug support.

The devices operate at a frequency of up to 48 MHz with a Flash accelerator to obtain maximum

efciency. It provides up to 128 KB of embedded Flash memory for code/data storage and 16 KB

of embedded SRAM memory for system operation and application program usage. A variety of
peripherals, such as ADC, I2C, USART, UART, SPI, I2S, GPTM, MCTM, SCI, CRC-16/32, RTC,

WDT, PDMA, EBI, USB2.0 FS, SW-DP (Serial Wire Debug Port), etc., are also implemented in
the device series. Several power saving modes provide the exibility for maximum optimization

between wakeup latency and power consumption, an especially important consideration in low
power applications.

Introduction

The above features ensure that the devices are suitable for use in a wide range of applications,
especially in areas such as white goods application control, power monitors, alarm systems,
consumer products, handheld equipment, data logging applications, motor control and so on.

Rev. 1.30 26 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

Features

▄

Core

● 32-bit Arm® Cortex®-M0+ processor core

● Up to 48 MHz operating frequency

● 0.93 DMIPS/MHz (Dhrystone v2.1)

● Single-cycle multiplication

● Integrated Nested Vectored Interrupt Controller (NVIC)

● 24-bit SysTick timer

▄

On-chip Memory

● Up to 128 KB on-chip Flash memory for instruction/data and options storage

● 16 KB on-chip SRAM

● Supports multiple boot modes

▄

Flash Memory Controller – FMC

● Flash accelerator for maximum efciency

● 32-bit word programming with In System Programming Interface (ISP) and In Application

Programming (IAP)

● Flash protection capability to prevent illegal access

▄

Reset Control Unit – RSTCU

● Supply supervisor: Power On Reset / Power Down Reset (POR/PDR) and Programmable Low

Voltage Detector (LVD)

▄

Clock Control Unit – CKCU

● External 4 to 16 MHz crystal oscillator

● External 32,768 Hz crystal oscillator

● Internal 8MHz RC oscillator trimmed to ±2 % accuracy at 3.3 V operating voltage and 25 ºC

operating temperature

● Internal 32 kHz RC oscillator

● Integrated system clock PLL

● Independent clock divider and gating bits for peripheral clock sources

▄

Power management – PWRCU

● Single VDD power supply: 2.0 V to 3.6 V

● Integrated 1.5 V LDO regulator for CPU core, peripherals and memories power supply

● V

battery power supply for RTC and backup registers

BAT

● Three power domains: VDD, 1.5 V and Backup

● Four power saving modes: Sleep, Deep-Sleep1, Deep-Sleep2, Power-Down

▄

External Interrupt/Event Controller – EXTI

● Up to 16 EXTI lines with congurable trigger source and type

● All GPIO pins can be selected as EXTI trigger source

● Source trigger type includes high level, low level, negative edge, positive edge, or both edge

● Individual interrupt enable, wakeup enable and status bits for each EXTI line

● Software interrupt trigger mode for each EXTI line

● Integrated deglitch lter for short pulse blocking

Introduction

Rev. 1.30 27 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

▄

Analog to Digital Converter – ADC

● 12-bit SAR ADC engine

● Up to 1 MSPS conversion rate

● Up to 12 external analog input channels

▄

Analog Comparator – CMP

● Two rail-to-rail comparator

● Each comparator has congurable negative inputs used for exible voltage selection

● Dedicated I/O pin or internal voltage reference provided by 6-bit scaler.

● Programmable hysteresis

● Programming speed and consumption

● Comparator output can be output to I/O or to timers or ADC trigger inputs

● 6-bit scaler can be congurable to dedicated I/O for voltage reference.

● Comparator has interrupt generation capability with wakeup from Sleep or Deep Sleep modes

through the EXTI controller.

▄

IO ports – GPIO

● Up to 51 GPIOs

● Port A, B, C, D are mapped as 16 external interrupts – EXTI

● Almost I/O pins are congurable output driving current.

▄

Motor Control Timer – MCTM

● One 16-bit up, down, up/down auto-reload counter

● Up to 4 independent channels

● 16-bit programmable prescaler allowing dividing the counter clock frequency by any factor

between 1 and 65536

● Input Capture function

● Compare Match Output

● PWM waveform generation with Edge-aligned and Center-aligned Counting Modes

● Single Pulse Mode Output

● Complementary Outputs with programmable dead-time insertion

● Supports 3-phase motor control and hall sensor interface

● Break input to force the timer’s output signals into a reset or xed condition

▄

PWM Generation and Capture Timer – GPTM

● One 16-bit up, down, up/down auto-reload counter

● Up to 4 independent channels for each timer

● 16-bit programmable prescaler allowing dividing the counter clock frequency by any factor

between 1 and 65536

● Input Capture function

● Compare Match Output

● PWM waveform generation with Edge-aligned and Center-aligned Counting Modes

● Single Pulse Mode Output

● Encoder interface controller with two inputs using quadrature decoder

Introduction

Rev. 1.30 28 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

▄

Single Channel Generation and Capture Timers – SCTM

● One 16-bit up and auto-reload counter

● One channel for each timer

● 16-bit programmable prescaler allowing dividing the counter clock frequency by any factor

between 1 and 65536

● Input Capture function

● Compare Match Output

● PWM waveform generation with Edge-aligned

● Single Pulse Mode Output

▄

Basic Function Timer – BFTM

● One 32-bit compare/match count-up counter – no I/O control features

● One shot mode – counting stops after a match condition

● Repetitive mode – restart counter after a match condition

▄

Watchdog Timer

● 12-bit down counter with 3-bit prescaler

● Reset event for the system

● Programmable watchdog timer window function

● Registers write protection function

▄

Real Time Clock – RTC

● 32-bit up-counter with a programmable prescaler

● Alarm function

● Interrupt and Wake-up event

▄

Inter-integrated Circuit – I2C

● Supports both master and slave modes with a frequency of up to 1 MHz

● Provide an arbitration function and clock synchronization

● Supports 7-bit and 10-bit addressing modes and general call addressing

● Supports slave multi-addressing mode with maskable address

▄

Serial Peripheral Interface – SPI

● Supports both master and slave mode

● Frequency of up to (f

● FIFO Depth: 8 levels

● Multi-master and multi-slave operation

▄

Universal Synchronous Asynchronous Receiver Transmitter – USART

● Supports both asynchronous and clocked synchronous serial communication modes

● Asynchronous operating baud rate up to (f

(f

/8) MHz

PCLK

● Capability of full duplex communication

● Fully programmable characteristics of serial communication including: word length, parity bit,

stop bit and bit order

● Error detection: Parity, overrun, and frame error

● Support Auto hardware ow control mode – RTS, CTS

● IrDA SIR encoder and decoder

● RS485 mode with output enable control

● FIFO Depth: 8 × 9 bits for both receiver and transmitter

/2) MHz for master mode and (f

PCLK

/16) MHz and synchronous operating rate up to

PCLK

/3) MHz for slave mode

PCLK

Introduction

Rev. 1.30 29 of 656 September 28, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52342/HT32F52352

▄

Universal Asynchronous Receiver Transmitter – UART

● Asynchronous serial communication operating baud-rate up to (f

● Capability of full duplex communication

● Fully programmable characteristics of serial communication including: word length, parity bit,

stop bit and bit order

● Error detection: Parity, overrun, and frame error

▄

Smart Card Interface – SCI

● Supports ISO 7816-3 Standard

● Character mode

● Single transmit buffer and single receive buffer

● 11-bit ETU (elementary time unit) counter

● 9-bit guard time counter

● 24-bit general purpose waiting time counter

● Parity generation and checking

● Automatic character retry on parity error detection in transmission and reception modes

▄

Inter-IC Sound – I2S

● Master or slave mode

● Mono and stereo

● I2S-justied, Left-justied, and Right-justied mode

● 8/16/24/32-bit sample size with 32-bit channel extended

● 8 × 32-bit TX & RX FIFO with PDMA supported

● 8-bit Fractional Clock Divider with rate control

▄

Cyclic Redundancy Check – CRC

● Support CRC16 polynomial: 0x8005, X16+X15+X2+1

● Support CCITT CRC16 polynomial: 0x1021, X16+X12+X5+1

● Support IEEE-802.3 CRC32 polynomial: 0x04C11DB7, X32+X26+X23+X22+X16+X12+X11+X10+

X8+X7+X5+X4+X2+X+1

● Support 1’s complement, byte reverse & bit reverse operation on data and checksum

● Support byte, half-word & word data size

● Programmable CRC initial seed value

● CRC computation done in 1 AHB clock cycle for 8-bit data and 4 AHB clock cycles for 32-bit

data

● Support PDMA to complete a CRC computation of a block of memory

▄

Peripheral Direct Memory Access – PDMA

● 6 channels with trigger source grouping

● 8/16/32-bit width data transfer

● Supports Address increment, decrement or xed mode

● 4-level programmable channel priority

● Auto reload mode

● Supports trigger sources:

ADC, SPI, USART, UART, I2C, I2S, EBI, GPTM, MCTM, SCI and software request

/16) MHz

PCLK

Introduction

Rev. 1.30 30 of 656 September 28, 2018