Holtek HT32F52220, HT32F52230 User Manual
Holtek 32-Bit Microcontroller with Arm® Cortex®-M0+ Core
HT32F52220/HT32F52230
User Manual
Revision: V1.10 Date: November 09, 2018
32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230
Table of Contents
1 Introduction ........................................................................................................... 17
Overview .............................................................................................................................. 17
Features ............................................................................................................................... 18
Device Information ............................................................................................................... 21
Block Diagram ..................................................................................................................... 22
2 Document Conventions ....................................................................................... 23
3 System Architecture ............................................................................................. 24
Arm® Cortex®-M0+ Processor .............................................................................................. 24
Bus Architecture ................................................................................................................... 25
Memory Organization .......................................................................................................... 26
Memory Map ................................................................................................................................... 27
Embedded Flash Memory ............................................................................................................... 29
Embedded SRAM Memory ............................................................................................................. 29
AHB Peripherals ............................................................................................................................. 29
APB Peripherals ............................................................................................................................. 29
Table of Contents
4 Flash Memory Controller (FMC) .......................................................................... 30
Introduction .......................................................................................................................... 30
Features ............................................................................................................................... 30
Functional Descriptions ....................................................................................................... 31
Flash Memory Map ......................................................................................................................... 31
Flash Memory Architecture ............................................................................................................. 32
Wait State Setting ........................................................................................................................... 32
Booting Conguration ..................................................................................................................... 33
Page Erase ..................................................................................................................................... 34
Mass Erase ..................................................................................................................................... 35
Word Programming ......................................................................................................................... 36
Option Byte Description .................................................................................................................. 37
Page Erase/Program Protection ..................................................................................................... 38
Security Protection .......................................................................................................................... 39
Register Map ....................................................................................................................... 40
Register Descriptions ........................................................................................................... 41
Flash Target Address Register – TADR ......................................................................................... 41
Flash Write Data Register – WRDR .............................................................................................. 42
Flash Operation Command Register – OCMR .............................................................................. 43
Flash Operation Control Register – OPCR .................................................................................... 44
Flash Operation Interrupt Enable Register – OIER ....................................................................... 45
Flash Operation Interrupt and Status Register – OISR ................................................................. 46
Flash Page Erase/Program Protection Status Register – PPSR ................................................... 48
Flash Security Protection Status Register – CPSR ....................................................................... 49
Rev. 1.10 2 of 366 November 09, 2018
32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230
Flash Vector Mapping Control Register – VMCR .......................................................................... 50
Flash Manufacturer and Device ID Register – MDID ..................................................................... 51
Flash Page Number Status Register – PNSR ............................................................................... 52
Flash Page Size Status Register – PSSR ..................................................................................... 53
Device ID Register – DID ............................................................................................................... 54
Flash Pre-fetch Control Register – CFCR ..................................................................................... 55
Custom ID Register n – CIDRn ( n = 0 ~3) ..................................................................................... 56
5 Power Control Unit (PWRCU) .............................................................................. 57
Introduction .......................................................................................................................... 57
Features ............................................................................................................................... 58
Functional Descriptions ....................................................................................................... 58
VDD Power Domain .......................................................................................................................... 58
1.5 V Power Domain ....................................................................................................................... 60
Operation Modes ............................................................................................................................ 60
Register Map ....................................................................................................................... 62
Register Descriptions ........................................................................................................... 63
Power Control Status Register – PWRSR ...................................................................................... 63
Power Control Register – PWRCR ................................................................................................. 64
V
Power Domain Test Register – PWRTEST ............................................................................... 66
DD
Low Voltage / Brown Out Detect Control and Status Register – LVDCSR ..................................... 67
Table of Contents
6 Clock Control Unit (CKCU) .................................................................................. 69
Introduction .......................................................................................................................... 69
Features ............................................................................................................................... 71
Function Descriptions .......................................................................................................... 71
High Speed External Crystal Oscillator – HSE ............................................................................... 71
High Speed Internal RC Oscillator – HSI ........................................................................................ 72
Phase Locked Loop – PLL .............................................................................................................. 73
Low Speed Internal RC Oscillator – LSI ......................................................................................... 74
Clock Ready Flag ........................................................................................................................... 74
System Clock (CK_SYS) Selection ................................................................................................ 75
HSE Clock Monitor ......................................................................................................................... 76
Clock Output Capability .................................................................................................................. 76
Register Map ....................................................................................................................... 77
Register Descriptions ........................................................................................................... 78
Global Clock Conguration Register – GCFGR .............................................................................. 78
Global Clock Control Register – GCCR .......................................................................................... 80
Global Clock Status Register – GCSR ........................................................................................... 82
Global Clock Interrupt Register – GCIR .......................................................................................... 83
PLL Conguration Register – PLLCFGR ........................................................................................ 84
PLL Control Register – PLLCR ....................................................................................................... 84
AHB Conguration Register – AHBCFGR ...................................................................................... 85
AHB Clock Control Register – AHBCCR ........................................................................................ 86
Rev. 1.10 3 of 366 November 09, 2018
32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230
APB Conguration Register – APBCFGR ....................................................................................... 87
APB Clock Control Register 0 – APBCCR0 .................................................................................... 88
APB Clock Control Register 1 – APBCCR1 .................................................................................... 89
Clock Source Status Register – CKST ........................................................................................... 90
APB Peripheral Clock Selection Register 0 – APBPCSR0 ............................................................. 91
APB Peripheral Clock Selection Register 1 – APBPCSR1 ............................................................. 93
Low Power Control Register – LPCR ............................................................................................. 95
MCU Debug Control Register – MCUDBGCR ................................................................................ 96
7 Reset Control Unit (RSTCU) ................................................................................ 98
Introduction .......................................................................................................................... 98
Functional Descriptions ....................................................................................................... 99
Power On Reset ............................................................................................................................. 99
System Reset ................................................................................................................................. 99
AHB and APB Unit Reset ................................................................................................................ 99
Register Map ..................................................................................................................... 100
Register Descriptions ......................................................................................................... 100
Global Reset Status Register – GRSR ......................................................................................... 100
AHB Peripheral Reset Register – AHBPRSTR ............................................................................. 101
APB Peripheral Reset Register 0 – APBPRSTR0 ........................................................................ 102
APB Peripheral Reset Register 1 – APBPRSTR1 ........................................................................ 103
Table of Contents
8 General Purpose I/O (GPIO) ............................................................................... 104
Introduction ........................................................................................................................ 104
Features ............................................................................................................................. 105
Functional Descriptions ..................................................................................................... 105
Default GPIO Pin Conguration .................................................................................................... 105
General Purpose I/O – GPIO ........................................................................................................ 105
GPIO Locking Mechanism ............................................................................................................ 107
Register Map ..................................................................................................................... 107
Register Descriptions ......................................................................................................... 108
Port A Data Direction Control Register – PADIRCR ..................................................................... 108
Port A Input Function Enable Control Register – PAINER ............................................................ 109
Port A Pull-Up Selection Register – PAPUR ..................................................................................110
Port A Pull-Down Selection Register – PAPDR .............................................................................111
Port A Open Drain Selection Register – PAODR ...........................................................................112
Port A Output Current Drive Selection Register – PADRVR ..........................................................113
Port A Lock Register – PALOCKR .................................................................................................114
Port A Data Input Register – PADINR ............................................................................................115
Port A Output Data Register – PADOUTR .....................................................................................116
Port A Output Set/Reset Control Register – PASRR .....................................................................117
Port A Output Reset Register – PARR ...........................................................................................118
Port B Data Direction Control Register – PBDIRCR ......................................................................119
Port B Input Function Enable Control Register – PBINER ........................................................... 120
Rev. 1.10 4 of 366 November 09, 2018
32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230
Port B Pull-Up Selection Register – PBPUR ................................................................................ 121
Port B Pull-Down Selection Register – PBPDR ............................................................................ 122
Port B Open Drain Selection Register – PBODR ......................................................................... 123
Port B Output Current Drive Selection Register – PBDRVR ........................................................ 124
Port B Lock Register – PBLOCKR ................................................................................................ 125
Port B Data Input Register – PBDINR .......................................................................................... 126
Port B Output Data Register – PBDOUTR ................................................................................... 127
Port B Output Set/Reset Control Register – PBSRR .................................................................... 128
Port B Output Reset Register – PBRR ......................................................................................... 129
9 Alternate Function Input/Output Control Unit (AFIO) ...................................... 130
Introduction ........................................................................................................................ 130
Features ............................................................................................................................. 131
Functional Descriptions ..................................................................................................... 131
External Interrupt Pin Selection .................................................................................................... 131
Alternate Function ......................................................................................................................... 132
Lock Mechanism .......................................................................................................................... 132
Register Map ..................................................................................................................... 132
Register Descriptions ......................................................................................................... 133
EXTI Source Selection Register 0 – ESSR0 ................................................................................ 133
EXTI Source Selection Register 1 – ESSR1 ................................................................................ 134
GPIO x Conguration Low Register – GPxCFGLR, x = A, B ........................................................ 135
GPIO x Conguration High Register – GPxCFGHR, x = A, B ...................................................... 136
Table of Contents
10 Nested Vectored Interrupt Controller (NVIC) .................................................. 137
Introduction ........................................................................................................................ 137
Features ............................................................................................................................. 138
Function Descriptions ........................................................................................................ 139
SysTick Calibration ....................................................................................................................... 139
Register Map ..................................................................................................................... 139
11 External Interrupt/Event Controller (EXTI) ...................................................... 140
Introduction ........................................................................................................................ 140
Features ............................................................................................................................. 140
Function Descriptions ........................................................................................................ 141
Wakeup Event Management......................................................................................................... 141
External Interrupt/Event Line Mapping ......................................................................................... 142
Interrupt and Debounce ................................................................................................................ 142
Register Map ..................................................................................................................... 143
Register Descriptions ......................................................................................................... 144
EXTI Interrupt Conguration Register n – EXTICFGRn, n = 0 ~ 15 ............................................. 144
EXTI Interrupt Control Register – EXTICR ................................................................................... 145
EXTI Interrupt Edge Flag Register – EXTIEDGEFLGR ................................................................ 146
EXTI Interrupt Edge Status Register – EXTIEDGESR ................................................................. 147
Rev. 1.10 5 of 366 November 09, 2018
32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230
EXTI Interrupt Software Set Command Register – EXTISSCR .................................................... 148
EXTI Interrupt Wakeup Control Register – EXTIWAKUPCR ........................................................ 149
EXTI Interrupt Wakeup Polarity Register – EXTIWAKUPPOLR ................................................... 150
EXTI Interrupt Wakeup Flag Register – EXTIWAKUPFLG ........................................................... 151
12 Analog to Digital Converter (ADC) .................................................................. 152
Introduction ........................................................................................................................ 152
Features ............................................................................................................................. 153
Function Descriptions ........................................................................................................ 154
ADC Clock Setup .......................................................................................................................... 154
Channel Selection ......................................................................................................................... 154
Conversion Mode .......................................................................................................................... 154
Start Conversion on External Event .............................................................................................. 157
Sampling Time Setting .................................................................................................................. 158
Data Format .................................................................................................................................. 158
Analog Watchdog.......................................................................................................................... 158
Interrupts ....................................................................................................................................... 159
Register Map ..................................................................................................................... 160
Register Descriptions ......................................................................................................... 161
ADC Conversion Control Register – ADCCR ............................................................................... 161
ADC Conversion List Register 0 – ADCLST0 ............................................................................... 163
ADC Conversion List Register 1 – ADCLST1 ............................................................................... 164
ADC Input Sampling Time Register – ADCSTR ........................................................................... 165
ADC Conversion Data Register y – ADCDRy, y = 0 ~ 7 ............................................................... 166
ADC Trigger Control Register – ADCTCR .................................................................................... 167
ADC Trigger Source Register – ADCTSR ..................................................................................... 168
ADC Watchdog Control Register – ADCWCR .............................................................................. 169
ADC Watchdog Threshold Register – ADCTR .............................................................................. 170
ADC Interrupt Enable Register – ADCIER ................................................................................... 171
ADC Interrupt Raw Status Register – ADCIRAW ......................................................................... 172
ADC Interrupt Status Register – ADCISR ..................................................................................... 173
ADC Interrupt Clear Register – ADCICLR .................................................................................... 174
Table of Contents
13 General-Purpose Timer (GPTM) ...................................................................... 175
Introduction ........................................................................................................................ 175
Features ............................................................................................................................. 176
Functional Descriptions ..................................................................................................... 177
Counter Mode ............................................................................................................................... 177
Clock Controller ............................................................................................................................ 180
Trigger Controller .......................................................................................................................... 181
Slave Controller ............................................................................................................................ 182
Master Controller .......................................................................................................................... 185
Channel Controller ........................................................................................................................ 186
Input Stage ................................................................................................................................... 189
Rev. 1.10 6 of 366 November 09, 2018
32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230
Quadrature Decoder ..................................................................................................................... 191
Output Stage ................................................................................................................................. 193
Update Management .................................................................................................................... 197
Single Pulse Mode ........................................................................................................................ 198
Asymmetric PWM Mode ............................................................................................................... 200
Trigger ADC Start.......................................................................................................................... 201
Register Map ..................................................................................................................... 201
Register Descriptions ......................................................................................................... 202
Timer Counter Conguration Register – CNTCFR ....................................................................... 202
Timer Mode Conguration Register – MDCFR ............................................................................. 203
Timer Trigger Conguration Register – TRCFR ............................................................................ 206
Timer Counter Register – CTR ..................................................................................................... 207
Channel 0 Input Conguration Register – CH0ICFR .................................................................... 208
Channel 1 Input Conguration Register – CH1ICFR .................................................................... 209
Channel 2 Input Conguration Register – CH2ICFR .....................................................................211
Channel 3 Input Conguration Register – CH3ICFR .................................................................... 212
Channel 0 Output Conguration Register – CH0OCFR ............................................................... 214
Channel 1 Output Conguration Register – CH1OCFR ............................................................... 216
Channel 2 Output Conguration Register – CH2OCFR ............................................................... 217
Channel 3 Output Conguration Register – CH3OCFR ............................................................... 219
Channel Control Register – CHCTR ............................................................................................. 221
Channel Polarity Conguration Register – CHPOLR .................................................................... 222
Timer Interrupt Control Register – DICTR .................................................................................... 223
Timer Event Generator Register – EVGR ..................................................................................... 224
Timer Interrupt Status Register – INTSR ...................................................................................... 225
Timer Counter Register – CNTR................................................................................................... 227
Timer Prescaler Register – PSCR ................................................................................................ 228
Timer Counter Reload Register – CRR ........................................................................................ 229
Channel 0 Capture/Compare Register – CH0CCR ...................................................................... 230
Channel 1 Capture/Compare Register – CH1CCR ...................................................................... 231
Channel 2 Capture/Compare Register – CH2CCR ...................................................................... 232
Channel 3 Capture/Compare Register – CH3CCR ...................................................................... 233
Channel 0 Asymmetric Compare Register – CH0ACR ................................................................. 234
Channel 1 Asymmetric Compare Register – CH1ACR ................................................................. 234
Channel 2 Asymmetric Compare Register – CH2ACR ................................................................. 235
Channel 3 Asymmetric Compare Register – CH3ACR ................................................................. 235
Table of Contents
14 Basic Function Timer (BFTM) .......................................................................... 236
Introduction ........................................................................................................................ 236
Features ............................................................................................................................. 236
Functional Description ....................................................................................................... 237
Repetitive Mode ............................................................................................................................ 237
One Shot Mode ............................................................................................................................. 238
Trigger ADC Start.......................................................................................................................... 238
Rev. 1.10 7 of 366 November 09, 2018
32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230
Register Map ..................................................................................................................... 239
Register Descriptions ......................................................................................................... 239
BFTM Control Register – BFTMCR .............................................................................................. 239
BFTM Status Register – BFTMSR ................................................................................................ 240
BFTM Counter Register – BFTMCNTR ........................................................................................ 241
BFTM Compare Value Register – BFTMCMPR ........................................................................... 241
15 Single-Channel Timer (SCTM) ......................................................................... 242
Introduction ........................................................................................................................ 242
Features ............................................................................................................................. 243
Functional Descriptions ..................................................................................................... 243
Counter Mode ............................................................................................................................... 243
Clock Controller ............................................................................................................................ 244
Trigger Controller .......................................................................................................................... 245
Slave Controller ............................................................................................................................ 246
Channel Controller ........................................................................................................................ 248
Input Stage ................................................................................................................................... 249
Output Stage ................................................................................................................................. 250
Update Management .................................................................................................................... 252
Register Map ..................................................................................................................... 253
Register Descriptions ......................................................................................................... 254
Timer Counter Conguration Register – CNTCFR ....................................................................... 254
Timer Mode Conguration Register – MDCFR ............................................................................. 255
Timer Trigger Conguration Register – TRCFR ............................................................................ 256
Timer Counter Register – CTR ..................................................................................................... 257
Channel Input Conguration Register – CHICFR ......................................................................... 258
Channel Output Conguration Register – CHOCFR ................................................................... 260
Channel Control Register – CHCTR ............................................................................................. 261
Channel Polarity Conguration Register – CHPOLR .................................................................... 262
Timer Interrupt Control Register – DICTR .................................................................................... 263
Timer Event Generator Register – EVGR ..................................................................................... 264
Timer Interrupt Status Register – INTSR ...................................................................................... 265
Timer Counter Register – CNTR................................................................................................... 266
Timer Prescaler Register – PSCR ................................................................................................ 266
Timer Counter Reload Register – CRR ........................................................................................ 267
Channel Capture/Compare Register – CHCCR ........................................................................... 268
Table of Contents
16 Watchdog Timer (WDT) .................................................................................... 269
Introduction ........................................................................................................................ 269
Features ............................................................................................................................. 269
Functional Description ....................................................................................................... 270
Register Map ..................................................................................................................... 272
Register Descriptions ......................................................................................................... 272
Watchdog Timer Control Register – WDTCR ............................................................................... 272
Rev. 1.10 8 of 366 November 09, 2018
32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230
Watchdog Timer Mode Register 0 – WDTMR0............................................................................. 273
Watchdog Timer Mode Register 1 – WDTMR1............................................................................. 274
Watchdog Timer Status Register – WDTSR ................................................................................. 275
Watchdog Timer Protection Register – WDTPR ........................................................................... 276
Watchdog Timer Clock Selection Register – WDTCSR ............................................................... 277
17 Inter-Integrated Circuit (I2C) ............................................................................. 278
Introduction ........................................................................................................................ 278
Features ............................................................................................................................. 279
Functional Descriptions ..................................................................................................... 279
Two Wire Serial Interface .............................................................................................................. 279
START and STOP Conditions ....................................................................................................... 279
Data Validity .................................................................................................................................. 280
Addressing Format ....................................................................................................................... 281
Data Transfer and Acknowledge ................................................................................................... 283
Clock Synchronization .................................................................................................................. 284
Arbitration ..................................................................................................................................... 284
General Call Addressing ............................................................................................................... 285
Bus Error ....................................................................................................................................... 285
Address Mask Enable ................................................................................................................... 285
Address Snoop ............................................................................................................................. 285
Operation Mode ............................................................................................................................ 285
Conditions of Holding SCL Line .................................................................................................... 291
I2C Timeout Function .................................................................................................................... 292
Register Map ..................................................................................................................... 292
Register Descriptions ......................................................................................................... 293
I2C Control Register – I2CCR ....................................................................................................... 293
I2C Interrupt Enable Register – I2CIER ........................................................................................ 294
I2C Address Register – I2CADDR ................................................................................................. 296
I2C Status Register – I2CSR ......................................................................................................... 297
I2C SCL High Period Generation Register – I2CSHPGR .............................................................. 300
I2C SCL Low Period Generation Register – I2CSLPGR ............................................................... 301
I2C Data Register – I2CDR ........................................................................................................... 302
I2C Target Register – I2CTAR ....................................................................................................... 303
I2C Address Mask Register – I2CADDMR .................................................................................... 304
I2C Address Snoop Register – I2CADDSR ................................................................................... 305
I2C Timeout Register – I2CTOUT.................................................................................................. 306
Table of Contents
18 Serial Peripheral Interface (SPI) ...................................................................... 307
Introduction ........................................................................................................................ 307
Features ............................................................................................................................. 308
Function Descriptions ........................................................................................................ 308
Master Mode ................................................................................................................................. 308
Slave Mode ................................................................................................................................... 308
Rev. 1.10 9 of 366 November 09, 2018
32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230
SPI Serial Frame Format .............................................................................................................. 309
Status Flags .................................................................................................................................. 313
Register Map ..................................................................................................................... 315
Register Descriptions ......................................................................................................... 316
SPI Control Register 0 – SPICR0 ................................................................................................. 316
SPI Control Register 1 – SPICR1 ................................................................................................. 317
SPI Interrupt Enable Register – SPIIER ....................................................................................... 319
SPI Clock Prescaler Register – SPICPR ...................................................................................... 320
SPI Data Register – SPIDR .......................................................................................................... 321
SPI Status Register – SPISR ........................................................................................................ 321
SPI FIFO Control Register – SPIFCR ........................................................................................... 323
SPI FIFO Status Register – SPIFSR ............................................................................................ 324
SPI FIFO Time Out Counter Register – SPIFTOCR ..................................................................... 325
19 Universal Synchronous Asynchronous Receiver Transmitter (USART) ..... 326
Introduction ........................................................................................................................ 326
Features ............................................................................................................................. 327
Function Descriptions ........................................................................................................ 328
Serial Data Format ........................................................................................................................ 328
Baud Rate Generation .................................................................................................................. 329
Hardware Flow Control ................................................................................................................. 331
IrDA ............................................................................................................................................... 332
RS485 Mode ................................................................................................................................. 335
Synchronous Master Mode ........................................................................................................... 338
Interrupts and Status .................................................................................................................... 340
Register Map ..................................................................................................................... 340
Register Descriptions ......................................................................................................... 341
USART Data Register – USRDR .................................................................................................. 341
USART Control Register – USRCR .............................................................................................. 342
USART FIFO Control Register – USRFCR................................................................................... 344
USART Interrupt Enable Register – USRIER ............................................................................... 345
USART Status & Interrupt Flag Register – USRSIFR................................................................... 346
USART Timing Parameter Register – USRTPR ........................................................................... 348
USART IrDA Control Register – IrDACR ...................................................................................... 349
USART RS485 Control Register – RS485CR............................................................................... 350
USART Synchronous Control Register – SYNCR ........................................................................ 351
USART Divider Latch Register – USRDLR................................................................................... 352
USART Test Register – USRTSTR ............................................................................................... 353
Table of Contents
20 Universal Asynchronous Receiver Transmitter (UART) ................................ 354
Introduction ........................................................................................................................ 354
Features ............................................................................................................................. 355
Function Descriptions ........................................................................................................ 355
Serial Data Format ........................................................................................................................ 355
Rev. 1.10 10 of 366 November 09, 2018
32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230
Baud Rate Generation .................................................................................................................. 356
Interrupts and Status .................................................................................................................... 358
Register Map ..................................................................................................................... 358
Register Descriptions ......................................................................................................... 359
UART Data Register – URDR ....................................................................................................... 359
UART Control Register – URCR ................................................................................................... 359
UART Interrupt Enable Register – URIER .................................................................................... 361
UART Status & Interrupt Flag Register – URSIFR ....................................................................... 362
UART Divider Latch Register – URDLR ....................................................................................... 364
UART Test Register – URTSTR .................................................................................................... 365
Table of Contents
Rev. 1.10 11 of 366 November 09, 2018
32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230
List of Tables
Table 1. Features and Peripheral List ..................................................................................................... 21
Table 2. Document Conventions ............................................................................................................. 23
Table 3. Register Map ............................................................................................................................. 28
Table 4. Flash Memory and Option Byte ................................................................................................. 32
Table 5. Relationship between Wait State Cycle and HCLK ................................................................... 32
Table 6. Boot Modes ............................................................................................................................... 33
Table 7. Option Byte Memory Map ......................................................................................................... 37
Table 8. Access Permission of Protected Main Flash Page .................................................................... 38
Table 9. Access Permission When Security Protection is Enabled ......................................................... 39
Table 10. FMC Register Map .................................................................................................................. 40
Table 11. Operation Mode Denitions ..................................................................................................... 60
Table 12. Enter/Exit Power Saving Modes .............................................................................................. 61
Table 13. Power Status After System Reset ........................................................................................... 62
Table 14. PWRCU Register Map ............................................................................................................ 62
Table 15. Output Divider2 Value Mapping............................................................................................... 74
Table 16. Feedback Divider2 Value Mapping.......................................................................................... 74
Table 17. CKOUT Clock Source ............................................................................................................. 76
Table 18. CKCU Register Map ............................................................................................................... 77
Table 19. RSTCU Register Map ........................................................................................................... 100
Table 20. AFIO, GPIO and IO Pad Control Signal True Table............................................................... 106
Table 21. GPIO Register Map ............................................................................................................... 107
Table 22. AFIO Selection for Peripheral Map Example ......................................................................... 132
Table 23. AFIO Register Map ................................................................................................................ 132
Table 24. Exception Types .................................................................................................................... 137
Table 25. NVIC Register Map ............................................................................................................... 139
Table 26. EXTI Register Map ................................................................................................................ 143
Table 27. Data format in ADCDR [15:0] ................................................................................................ 158
Table 28. A/D Converter Register Map ................................................................................................. 160
Table 29. Counting Direction and Encoding Signals ............................................................................. 192
Table 30. Compare Match Output Setup .............................................................................................. 193
Table 31. GPTM Register Map ............................................................................................................. 201
Table 32. GPTM Internal Trigger Connection ....................................................................................... 206
Table 33. BFTM Register Map .............................................................................................................. 239
Table 34. Compare Match Output Setup .............................................................................................. 250
Table 35. SCTM Register Map .............................................................................................................. 253
Table 36. Watchdog Timer Register Map .............................................................................................. 272
Table 37. Conditions of Holding SCL line .............................................................................................. 291
Table 38. I2C Register Map ................................................................................................................... 292
Table 39. I2C Clock Setting Example .................................................................................................... 302
List of Tables
Rev. 1.10 12 of 366 November 09, 2018
32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230
Table 40. SPI Interface Format Setup ................................................................................................... 309
Table 41. SPI Mode Fault Trigger Conditions ....................................................................................... 314
Table 42. SPI Master Mode SEL Pin Status ......................................................................................... 314
Table 43. SPI Register Map .................................................................................................................. 315
Table 44. Baud Rate Deviation Error Calculation – CK_USART = 8 MHz ............................................ 329
Table 45. Baud Rate Deviation Error Calculation – CK_USART = 20 MHz .......................................... 330
Table 46. Baud Rate Deviation Error Calculation – CK_USART = 24 MHz .......................................... 330
Table 47. Baud Rate Deviation Error Calculation – CK_USART = 40 MHz .......................................... 330
Table 48. USART Register Map ............................................................................................................ 340
Table 49. Baud Rate Deviation Error Calculation – CK_UART = 8 MHz .............................................. 356
Table 50. Baud Rate Deviation Error Calculation – CK_UART = 20 MHz ............................................ 357
Table 51. Baud Rate Deviation Error Calculation – CK_UART = 24 MHz ............................................ 357
Table 52. Baud Rate Deviation Error Calculation – CK_UART = 40 MHz ............................................ 357
Table 53. UART Register Map .............................................................................................................. 358
List of Tables
Rev. 1.10 13 of 366 November 09, 2018
32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230
List of Figures
Figure 1. Block Diagram ......................................................................................................................... 22
Figure 2. Cortex®-M0+ Block Diagram .................................................................................................... 25
Figure 3. Bus Architecture ...................................................................................................................... 26
Figure 4. Memory Map ............................................................................................................................ 27
Figure 5. Flash Memory Controller Block Diagram ................................................................................. 30
Figure 6. Flash Memory Map .................................................................................................................. 31
Figure 7. Vector Remapping ................................................................................................................... 33
Figure 8. Page Erase Operation Flowchart ............................................................................................ 34
Figure 9. Mass Erase Operation Flowchart ............................................................................................ 35
Figure 10. Word Programming Operation Flowchart .............................................................................. 36
Figure 11. PWRCU Block Diagram ......................................................................................................... 57
Figure 12. Power On Reset / Power Down Reset Waveform ................................................................. 59
Figure 13. CKCU Block Diagram ............................................................................................................ 70
Figure 14. External Crystal, Ceramic, and Resonators for HSE ............................................................. 71
Figure 15. PLL Block Diagram ................................................................................................................ 73
Figure 16. RSTCU Block Diagram .......................................................................................................... 98
Figure 17. Power On Reset Sequence ................................................................................................... 99
Figure 18. GPIO Block Diagram ........................................................................................................... 104
Figure 19. AFIO/GPIO Control Signal ................................................................................................... 106
Figure 20. AFIO Block Diagram ............................................................................................................ 130
Figure 21. EXTI Channel Input Selection ............................................................................................. 131
Figure 22. EXTI Block Diagram ............................................................................................................ 140
Figure 23. EXTI Wake-up Event Management ..................................................................................... 141
Figure 24. EXTI Interrupt Debounce Function ...................................................................................... 142
Figure 25. ADC Block Diagram ............................................................................................................ 152
Figure 26. One Shot Conversion Mode ................................................................................................ 155
Figure 27. Continuous Conversion Mode ............................................................................................. 155
Figure 28. Discontinuous Conversion Mode ......................................................................................... 157
Figure 29. GPTM Block Diagram .......................................................................................................... 175
Figure 30. Up-counting Example .......................................................................................................... 177
Figure 31. Down-counting Example ...................................................................................................... 178
Figure 32. Center-aligned Counting Example ....................................................................................... 179
Figure 33. GPTM Clock Selection Source ............................................................................................ 180
Figure 34. Trigger Controller Block ....................................................................................................... 181
Figure 35. Slave Controller Diagram .................................................................................................... 182
Figure 36. GPTM in Restart Mode ........................................................................................................ 182
Figure 37. GPTM in Pause Mode ......................................................................................................... 183
Figure 38. GPTM in Trigger Mode ........................................................................................................ 184
Figure 39. Master GPTMn and Slave GPTMm/MCTMm Connection ................................................... 185
List of Figures
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HT32F52220/HT32F52230
Figure 40. MTO Selection ..................................................................................................................... 185
Figure 41. Capture/Compare Block Diagram ........................................................................................ 186
Figure 42. Input Capture Mode ............................................................................................................. 187
Figure 43. PWM Pulse Width Measurement Example .......................................................................... 188
Figure 44. Channel 0 and Channel 1 Input Stages ............................................................................... 189
Figure 45. Channel 2 and Channel 3 Input Stages ............................................................................... 190
Figure 46. TI0 Digital Filter Diagram with N = 2 .................................................................................... 190
Figure 47. Input Stage and Quadrature Decoder Block Diagram ......................................................... 191
Figure 48. Both TI0 and TI1 Quadrature Decoder Counting ................................................................. 192
Figure 49. Output Stage Block Diagram ............................................................................................... 193
Figure 50. Toggle Mode Channel Output Reference Signal – CHxPRE = 0 ......................................... 194
Figure 51. Toggle Mode Channel Output Reference Signal – CHxPRE = 1 ......................................... 194
Figure 52. PWM Mode Channel Output Reference Signal and Counter in Up-counting Mode ............ 195
Figure 53. PWM Mode Channel Output Reference Signal and Counter in Down-counting Mode ....... 195
Figure 54. PWM Mode Channel Output Reference Signal and Counter in Centre-align Mode ............ 196
Figure 55. Update Event Setting Diagram ............................................................................................ 197
Figure 56. Single Pulse Mode ............................................................................................................... 198
Figure 57. Immediate Active Mode Minimum Delay ............................................................................. 199
Figure 58. Asymmetric PWM Mode versus Center Align Counting Mode ............................................. 200
Figure 59. BFTM Block Diagram .......................................................................................................... 236
Figure 60. BFTM – Repetitive Mode ..................................................................................................... 237
Figure 61. BFTM – One Shot Mode ...................................................................................................... 238
Figure 62. BFTM – One Shot Mode Counter Updating ....................................................................... 238
Figure 63. SCTM Block Diagram .......................................................................................................... 242
Figure 64. Up-counting Example .......................................................................................................... 243
Figure 65. SCTM Clock Selection Source ............................................................................................ 244
Figure 66. Trigger Control Block ........................................................................................................... 245
Figure 67. Slave Controller Diagram .................................................................................................... 246
Figure 68. SCTM in Restart Mode ........................................................................................................ 246
Figure 69. SCTM in Pause Mode ......................................................................................................... 247
Figure 70. SCTM in Trigger Mode ........................................................................................................ 247
Figure 71. Capture/Compare Block Diagram ........................................................................................ 248
Figure 72. Input Capture Mode ............................................................................................................. 248
Figure 73. Channel Input Stages .......................................................................................................... 249
Figure 74. TI Digital Filter Diagram with N = 2 ...................................................................................... 249
Figure 75. Output Stage Block Diagram ............................................................................................... 250
Figure 76. Toggle Mode Channel Output Reference Signal – CHPRE = 0 ........................................... 251
Figure 77. Toggle Mode Channel Output Reference Signal – CHPRE = 1 ........................................... 251
Figure 78. PWM Mode Channel Output Reference Signal ................................................................... 252
Figure 79. Update Event Setting Diagram ............................................................................................ 253
Figure 80. Watchdog Timer Block Diagram ......................................................................................... 269
List of Figures
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HT32F52220/HT32F52230
Figure 81. Watchdog Timer Behavior ................................................................................................... 271
Figure 82. I2C Module Block Diagram ................................................................................................... 278
Figure 83. START and STOP Condition ............................................................................................... 280
Figure 84. Data Validity ......................................................................................................................... 280
Figure 85. 7-bit Addressing Mode ......................................................................................................... 281
Figure 86. 10-bit Addressing Write Transmit Mode .............................................................................. 282
Figure 87. 10-bits Addressing Read Receive Mode ............................................................................ 282
Figure 88. I2C Bus Acknowledge .......................................................................................................... 283
Figure 89. Clock Synchronization during Arbitration ............................................................................. 284
Figure 90. Two Master Arbitration Procedure ....................................................................................... 284
Figure 91. Master Transmitter Timing Diagram .................................................................................... 286
Figure 92. Master Receiver Timing Diagram ........................................................................................ 288
Figure 93. Slave Transmitter Timing Diagram ...................................................................................... 289
Figure 94. Slave Receiver Timing Diagram .......................................................................................... 290
Figure 95. SCL Timing Diagram ............................................................................................................ 301
Figure 96. SPI Block Diagram .............................................................................................................. 307
Figure 97. SPI Single Byte Transfer Timing Diagram – CPOL = 0, CPHA = 0 ...................................... 309
Figure 98. SPI Continuous Data Transfer Timing Diagram – CPOL = 0, CPHA = 0 ............................. 310
Figure 99. SPI Single Byte Transfer Timing Diagram – CPOL = 0, CPHA = 1 ...................................... 310
Figure 100. SPI Continuous Transfer Timing Diagram – CPOL = 0, CPHA = 1 .....................................311
Figure 101. SPI Single Byte Transfer Timing Diagram – CPOL = 1, CPHA = 0 .....................................311
Figure 102. SPI Continuous Transfer Timing Diagram – CPOL = 1, CPHA = 0 .................................... 312
Figure 103. SPI Single Byte Transfer Timing Diagram – CPOL = 1, CPHA = 1 .................................... 312
Figure 104. SPI Continuous Transfer Timing Diagram – CPOL = 1, CPHA = 1 .................................... 312
Figure 105. SPI Multi-Master Slave Environment ................................................................................. 314
Figure 106. USART Block Diagram ...................................................................................................... 326
Figure 107. USART Serial Data Format ............................................................................................... 328
Figure 108. USART Clock CK_USART and Data Frame Timing .......................................................... 329
Figure 109. Hardware Flow Control between 2 USARTs ...................................................................... 331
Figure 110. USART RTS Flow Control.................................................................................................. 331
Figure 111. USART CTS Flow Control .................................................................................................. 332
Figure 112. IrDA Modulation and Demodulation ................................................................................... 333
Figure 113. USART I/O and IrDA Block Diagram .................................................................................. 335
Figure 114. RS485 Interface and Waveform ......................................................................................... 336
Figure 115. USART Synchronous Transmission Example .................................................................... 338
Figure 116. 8-bit Format USART Synchronous Waveform ................................................................... 339
Figure 117. UART Block Diagram ......................................................................................................... 354
Figure 118. UART Serial Data Format .................................................................................................. 355
Figure 119. UART Clock CK_UART and Data Frame Timing ............................................................... 356
List of Figures
Rev. 1.10 16 of 366 November 09, 2018
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HT32F52220/HT32F52230
1
Overview
Introduction
This user manual provides detailed information including how to use the devices, system and
bus architecture, memory organization and peripheral instructions. The target audiences for this
document are software developers, application developers and hardware developers. For more
information regarding pin assignment, package and electrical characteristics, please refer to the
datasheet.
The devices are high performance and low power consumption 32-bit microcontrollers based
around an Arm® Cortex®-M0+ processor core. The Cortex®-M0+ is a next-generation processor
core which is tightly coupled with Nested Vectored Interrupt Controller (NVIC), SysTick timer,
and including advanced debug support.
The devices operate at a frequency of up to 40 MHz for HT32F52220/52230 with a Flash
accelerator to obtain maximum efciency. It provides up to 32 KB of embedded Flash memory for
code/data storage and 4 KB of embedded SRAM memory for system operation and application
program usage. A variety of peripherals, such as ADC, I2C, USART, UART, SPI, GPTM, SCTM,
SW-DP (Serial Wire Debug Port), etc., are also implemented in the device series. Several power
saving modes provide the exibility for maximum optimization between wakeup latency and power
consumption, an especially important consideration in low power applications.
The above features ensure that the devices are suitable for use in a wide range of applications,
especially in areas such as white goods application control, power monitors, alarm systems,
consumer products, handheld equipment, data logging applications, motor control and so on.
Introduction
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HT32F52220/HT32F52230
Features
▄
Core
● 32-bit Arm® Cortex®-M0+ processor core
● Up to 40MHz operating frequency for HT32F52220/52230
● 0.93 DMIPS/MHz (Dhrystone v2.1)
● Single-cycle multiplication
● Integrated Nested Vectored Interrupt Controller (NVIC)
● 24-bit SysTick timer
▄
On-chip Memory
● Up to 32 KB on-chip Flash memory for instruction/data and options storage
● Up to 4 KB on-chip SRAM
● Supports multiple boot modes
▄
Flash Memory Controller – FMC
● Flash accelerator for maximum efciency
● 32-bit word programming with In System Programming Interface (ISP) and In Application
Programming (IAP)
● Flash protection capability to prevent illegal access
▄
Reset Control Unit – RSTCU
● Supply supervisor: Power On Reset / Power Down Reset (POR/PDR) and Programmable Low
Voltage Detector (LVD)
▄
Clock Control Unit – CKCU
● External 4 to 16 MHz crystal oscillator
● Internal 8 MHz RC oscillator trimmed to ±2 % accuracy at 3.3 V operating voltage and 25 ºC
operating temperature
● Internal 32 kHz RC oscillator
● Integrated system clock PLL
● Independent clock divider and gating bits for peripheral clock sources
▄
Power management – PWRCU
● Single VDD power supply: 2.0 V to 3.6 V
● Integrated 1.5 V LDO regulator for CPU core, peripherals and memories power supply
● Two power domains: VDD and 1.5 V
● Four power saving modes: Sleep, Deep-Sleep1, Deep-Sleep2, Power-Down
▄
External Interrupt/Event Controller – EXTI
● Up to 16 EXTI lines with congurable trigger source and type
● All GPIO pins can be selected as EXTI trigger source
● Source trigger type includes high level, low level, negative edge, positive edge, or both edge
● Individual interrupt enable, wakeup enable and status bits for each EXTI line
● Software interrupt trigger mode for each EXTI line
● Integrated deglitch lter for short pulse blocking
Introduction
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HT32F52220/HT32F52230
▄
Analog to Digital Converter – ADC
● 12-bit SAR ADC engine
● Up to 1 MSPS conversion rate – 1 μs at 28 MHz, 1.4 μs at 40 MHz
● Up to 8 external analog input channels
▄
IO ports – GPIO
● Up to 23 GPIOs
● Port A, B are mapped as 16 external interrupts – EXTI
● Almost I/O pins are congurable output driving current
▄
PWM Generation and Capture Timer – GPTM
● One 16-bit up, down, up/down auto-reload counter
● Up to 4 independent channels for each GPTM
● 16-bit programmable prescaler allowing dividing the counter clock frequency by any factor
between 1 and 65536
● Input Capture function
● Compare Match Output
● PWM waveform generation with Edge-aligned and Center-aligned Counting Modes
● Single Pulse Mode Output
● Encoder interface controller with two inputs using quadrature decoder
▄
Single Channel PWM Generation and Capture Timers – SCTM
● One 16-bit up and auto-reload counter
● One channels for each SCTM
● 16-bit programmable prescaler allowing dividing the counter clock frequency by any factor
between 1 and 65536
● Input Capture function
● Compare Match Output
● PWM waveform generation with Edge-aligned
● Single Pulse Mode Output
▄
Basic Function Timer – BFTM
● 32-bit compare/match count-up counter – no I/O control features
● One shot mode – counting stops after a match condition
● Repetitive mode – restart counter after a match condition
▄
Watchdog Timer
● 12-bit down counter with 3-bit prescaler
● Reset event for the system
● Programmable watchdog timer window function
● Registers write protection function
▄
Inter-integrated Circuit – I2C
● Supports both master and slave modes with a frequency of up to 1 MHz
● Provide an arbitration function and clock synchronization
● Supports 7-bit and 10-bit addressing modes and general call addressing
● Supports slave multi-addressing mode with maskable address
Introduction
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HT32F52220/HT32F52230
▄
Serial Peripheral Interface – SPI
● Supports both master and slave mode
● Frequency of up to (f
● FIFO Depth: 8 levels
● Multi-master and multi-slave operation
▄
Universal Synchronous Asynchronous Receiver Transmitter – USART
● Supports both asynchronous and clocked synchronous serial communication modes
● Asynchronous operating baud rate up to (f
(f
/8) MHz
PCLK
● Capability of full duplex communication
● Fully programmable characteristics of serial communication including: word length, parity bit,
stop bit and bit order
● Error detection: Parity, overrun, and frame error
● Support Auto hardware ow control mode – RTS, CTS
● IrDA SIR encoder and decoder
● RS485 mode with output enable control
● FIFO Depth: 8 × 9 bits for both receiver and transmitter
▄
Universal Asynchronous Receiver Transmitter – UART
● Asynchronous serial communication operating baud-rate up to (f
● Capability of full duplex communication
● Fully programmable characteristics of serial communication including: word length, parity bit,
stop bit and bit order
● Error detection: Parity, overrun, and frame error
▄
Debug Support
● Serial Wire Debug Port – SW-DP
● 4 comparators for hardware breakpoint or code / literal patch
● 2 comparators for hardware watchpoints
▄
Package and Operation Temperature
● 24/28-pin SSOP, 33-pin QFN package
● Operation temperature range: -40 °C to +85 °C
/2) MHz for master mode and (f
PCLK
/16) MHz and synchronous operating rate up to
PCLK
/3) MHz for slave mode
PCLK
/16) MHz
PCLK
Introduction
Rev. 1.10 20 of 366 November 09, 2018
32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230
Device Information
Table 1. Features and Peripheral List
Peripherals HT32F52220 HT32F52230
Main Flash (KB) 16 31
Option Bytes Flash (KB) 1 1
SRAM (KB) 4 4
GPTM 1
Timers
Communication
EXTI 16
12-bit ADC
Number of channels
GPIO Up to 23
CPU frequency Up to 40 MHz
Operating voltage 2.0 V ~ 3.6 V
Operating temperature -40 °C ~ +85 °C
Package 24/28-pin SSOP, 33-pin QFN
SCTM 2
BFTM 1
WDT 1
SPI 1
USART 1
UART 1
I2C 1
Introduction
1
8 Channels
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32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230
Block Diagram
TX, RX
RTS/TXE
CTS/SCK
TX, RX
SWCLK SWDIO
AF
SW-DP
Cortex® -M0+
Processor
NVIC
Interrupt request
AF
AF
PA; PB
IO Port
GPIO
System
Bus Matrix
USART
UART
AFIO
EXTI
BOOT
AF
Flash Memory
Interface
FMC
Control Registers
AHB Peripherals
SRAM Controller
AHB to APB
Bridge
APB
Powered by V
Flash
Memory
CKCU/RSTCU
Control Registers
SRAM
WDT
SPI
I2C
GPTM
BFTM
SCTM0 ~ 1
DD15
V
DD
DD
V
SS
AF
XTALIN
XTALOUT
CLDO
AF
MOSI, MISO
SCK, SEL
AF
SDA SCL
AF
CH3 ~ CH0
AF
SCTM0 ~
SCTM1
Introduction
CAP.
POR
/PDR
HSE
4 ~ 16
MHz
HSI
8 MHz
Clock and reset control
LDO
1.5 V
BOD
LVD
Powered by V
PLL
Power control
V
AF
ADC_IN0
...
ADC_IN11
V
DDA
V
SSA
Power supply:
Bus:
Control signal:
Alternate function:
12-bit SAR
ADC
Powered by V
AF
ADC
PWRCU
DDA
Powered by V
DD15
Powered by V
LSI
32 kHz
DD
V
AF
WAKEUP
nRST
DD
SS
Figure 1. Block Diagram
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HT32F52220/HT32F52230
2
Document Conventions
The conventions used in this document are shown in the following table.
Table 2. Document Conventions
Notation Example Description
0x 0x5a05
0xnnnn_nnnn 0x2000_0100 32-bit Hexadecimal address or data.
b b0101
NAME [n] ADDR [5]
NAME [m:n] ADDR [11:5]
X b10X1 Don’t care notation which means any value is allowed.
RW
RO
RC
WC
W0C
WO
Reserved
SERDYIE
HSIRDY
SERDYF
PLLRDYIE
RW 0 RW 0
3 2
RO 1 RO 0
WC 0 WC 0
RXCF
RO 0 W0C 0
WO 0 WO 0
LLRDY
RO 0
HSERDY
1 0
PDF
BAK_PORF
RC 0 RC 1
3 2
PLLRDYF
1 0
PARF
31 30
DB_CKSRC
1
Reserved
19 18
Word Data length of a word is 32-bit.
Half-word Data length of a half-word is 16-bit.
Byte Data length of a byte is 8-bit.
The number string with a 0x prefix indicates a hexadecimal
number.
The number string with a lowercase b prex indicates a binary
number.
Specic bit of NAME. NAME can be a register or eld of register.
For example, ADDR [5] means bit 5 of ADDR register (eld).
Specific bits of NAME. NAME can be a register or field of
register. For example, ADDR [11:5] means bit 11 to 5 of ADDR
register (eld).
Software can read and write to this bit.
Software can only read this bit. A write operation will have no
effect.
Software can only read this bit. Read operation will clear it to 0
automatically.
Software can read this bit or clear it by writing 1. Writing a 0 will
have no effect.
Software can read this bit or clear it by writing 0. Writing a 1 will
have no effect.
Software can only write to this bit. A read operation always
returns 0.
Reserved bit(s) for future use. Data read from these bits is not
0
well defined and should be treated as random data. Normally
these reserved bits should be set to a 0 value. Note that
reserved bit must be kept at reset value.
Document Conventions
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HT32F52220/HT32F52230
3
System Architecture
The system architecture of devices that includes the Arm® Cortex®-M0+ processor, bus architecture
and memory organization will be described in the following sections. The Cortex®-M0+ is a next
generation processor core which offers many new features. Integrated and advanced features make
the Cortex®-M0+ processor suitable for market products that require microcontrollers with high
performance and low power consumption. In brief, The Cortex®-M0+ processor includes AHB-Lite
bus interface. All memory accesses of the Cortex®-M0+ processor are executed on the AHB-Lite
bus according to the different purposes and the target memory spaces. The memory organization
uses a Harvard architecture, pre-dened memory map and up to 4 GB of memory space, making
the system exible and extendable.
Arm® Cortex®-M0+ Processor
The Cortex®-M0+ processor is a very low gate count, highly energy efficient processor that is
intended for microcontroller and deeply embedded applications that require an area optimized,
low-power processor. The processor is based on the ARMv6-M architecture and supports Thumb®
instruction sets; single-cycle I/O port; hardware multiplier and low latency interrupt respond time.
Some system peripherals listed below are also provided by Cortex®-M0+:
▄
Internal Bus Matrix connected with AHB-Lite Interface, Single-cycle I/O port and Debug
Accesses Port (DAP)
▄
Nested Vectored Interrupt Controller (NVIC)
▄
Optional Wakeup Interrupt Controller (WIC)
▄
Breakpoint and Watchpoint Unit
▄
Optional Memory Protection Unit (MPU)
▄
Serial Wire debug Port (SW-DP)
▄
Optional Micro Trace Buffer Interface (MTB)
The following gure shows the Cortex®-M0+ processor block diagram. For more information, refer
to the Arm® Cortex®-M0+ Technical Reference Manual.
System Architecture
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HT32F52220/HT32F52230
®
Cortex
-M0+ Components
Execution Trace Interface
Interrupts
‡ Wakeup
Interrupt
Controller (WIC)
‡ Optional Componect
Figure 2. Cortex®-M0+ Block Diagram
Bus Architecture
The HT32F52220/HT32F52230 series consists of one master and four slaves in the bus architecture.
The Cortex®-M0+ AHB-Lite bus is the master while the internal SRAM access bus, the internal
Flash memory access bus, the AHB peripherals access bus and the AHB to APB bridges are the
slaves. The single 32-bit AHB-Lite system interface provides simple integration to all system
regions include the internal SRAM region and the peripheral region. All of the master buses are
based on 32-bit Advanced High-performance Bus-Lite (AHB-Lite) protocol. The following gure
shows the bus architecture of the HT32F52220/HT32F52230 series.
Cortex-M0+ Processor
Nested
Vectored
Interrupt
Controller
(NVIC)
Cortex®-M0+
Processor
Core
‡ Memory
Protection
Unit
AHB-Lite Interface
to System
Bus Matrix
Debug
‡ Breakpoint
and
Watchpoint
Unit
‡ Debugger
Interface
‡ Single-cycle
I/O Port
‡ Debug
Access Port
(DAP)
‡ Serial Wire or JTAG
Debug Port
System Architecture
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HT32F52220/HT32F52230
GPIO
Cortex® -M0+
Processor
NVIC
Interrupt request
Figure 3. Bus Architecture
Memory Organization
I/O Port
System
Flash Memory
Interface
FMC
Control Registers
Bus Matrix
AHB Peripherals
SRAM Controller
AHB to APB
Bridge
Control Registers
Flash
Memory
CKCU/RSTCU
SRAM
APB IPs
System Architecture
The Arm® Cortex®-M0+ processor accesses and debug accesses share the single external
interface to external AHB peripheral. The processor accesses take priority over debug accesses.
The maximum address range of the Cortex®-M0+ is 4 GB since it has 32-bit bus address width.
Additionally, a pre-defined memory map is provided by the Cortex®-M0+ processor to reduce
the software complexity of repeated implementation of different device vendors. However, some
regions are used by the Arm® Cortex®-M0+ system peripherals. Refer to the Arm® Cortex®-M0+
Technical Reference Manual for more information. The following gure shows the memory map
of HT32F52220/HT32F52230 series of devices, including Code, SRAM, peripheral, and other predened regions.
Rev. 1.10 26 of 366 November 09, 2018
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HT32F52220/HT32F52230
Memory Map
0xFFFF_FFFF
0xE010_0000
0xE000_0000
0x4010_0000
Peripheral
SRAM
Code
0x4008_0000
0x4000_0000
0x2000_1000
0x2000_0000
0x1FF0_0400
0x1FF0_0000
0x1F00_0800
0x1F00_0000
0x000_8000
Reserved
Private peripheral bus
Reserved
AHB peripherals
APB peripherals
Reserved
Up to
4 KB on-chip SRAM
Reserved
Option byte alias
Reserved
Boot loader
Reserved
512 KB
512 KB
4 KB
1 KB
2 KB
0x400F_FFFF
0x400B_4000
0x400B_0000
0x4008_A000
0x4007_7000
0x4007_6000
0x4007_5000
0x4006_F000
0x4006_E000
0x4006_B000
0x4006_A000
0x4006_9000
0x4006_8000
0x4004_9000
0x4004_8000
0x4003_5000
0x4003_4000
0x4002_5000
0x4002_4000
0x4002_3000
0x4002_2000
0x4001_1000
0x4001_0000
0x4000_5000
0x4000_2000
0x4000_1000
0x4000_0000
Reserved
GPIO A ～ B
Reserved
CKCU/RSTCU0x4008_8000
Reserved0x4008_2000
FMC0x4008_0000
Reserved
BFTM
Reserved
SCTM10x4007_4000
Reserved
GPTM
Reserved
PWRCU
Reserved
WDT
Reserved
I2C
Reserved
SCTM0
Reserved
EXTI
Reserved
AFIO
Reserved
ADC
Reserved
SPI0x4000_4000
Reserved
UART
USART
System Architecture
AHB
APB
Up to
32 KB on-chip Flash
0x0000_0000
Up to
32 KB
Figure 4. Memory Map
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HT32F52220/HT32F52230
Table 3. Register Map
Start Address End Address Peripheral Bus
0x4000_0000 0x4000_0FFF USART
0x4000_1000 0x4000_1FFF UART
0x4000_2000 0x4000_3FFF Reserved
0x4000_4000 0x4000_4FFF SPI
0x4000_5000 0x4001_9FFF Reserved
0x4001_0000 0x4001_0FFF ADC
0x4001_1000 0x4002_1FFF Reserved
0x4002_2000 0x4002_2FFF AFIO
0x4002_3000 0x4002_3FFF Reserved
0x4002_4000 0x4002_4FFF EXTI
0x4002_5000 0x4003_3FFF Reserved
0x4003_4000 0x4003_4FFF SCTM0
0x4003_5000 0x4004_7FFF Reserved
0x4004_8000 0x4004_8FFF I2C
0x4004_9000 0x4006_7FFF Reserved
0x4006_8000 0x4006_8FFF WDT
0x4006_9000 0x4006_9FFF Reserved
0x4006_A000 0x4006_AFFF PWRCU
0x4006_B000 0x4006_DFFF Reserved
0x4006_E000 0x4006_EFFF GPTM
0x4006_F000 0x4007_3FFF Reserved
0x4007_4000 0x4007_4FFF SCTM1
0x4007_5000 0x4007_5FFF Reserved
0x4007_6000 0x4007_6FFF BFTM
0x4007_7000 0x4007_FFFF Reserved
0x4008_0000 0x4008_1FFF FMC
0x4008_2000 0x4008_7FFF Reserved
0x4008_8000 0x4008_9FFF CKCU/RSTCU
0x4008_A000 0x400A_FFFF Reserved
0x400B_0000 0x400B_1FFF GPIOA
0x400B_2000 0x400B_3FFF GPIOB
0x400B_4000 0x400F_FFFF Reserved
System Architecture
APB
AHB
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HT32F52220/HT32F52230
Embedded Flash Memory
The HT32F52220/HT32F52230 series provides up to 32 KB on-chip Flash memory which is
located at address 0x0000_0000. It supports byte, half-word, and word access operations. Note that
the Flash memory only supports read operations for the bus access. Any write operations to the
Flash memory will cause a bus fault exception. The Flash memory has up to capacity of 32 pages.
Each page has a memory capacity of 1 KB and can be erased independently. A 32-bit programming
interface provides the capability of changing bits from 1 to 0. A data storage or rmware upgrade
can be implemented using several methods such as In System Programming (ISP), In Application
Programming (IAP) or In Circuit Programming (ICP). For more information, refer to the Flash
Memory Controller section.
Embedded SRAM Memory
The HT32F52220/HT32F52230 series contain up to 4 KB on-chip SRAM which is located at
address 0x2000_0000. It support byte, half-word and word access operations.
AHB Peripherals
The address of the AHB peripherals ranges from 0x4008_0000 to 0x400F_FFFF. Some peripherals
such as Clock Control Unit, Reset Control Unit and Flash Memory Controller are connected to the
AHB bus directly. The AHB peripherals clocks are always enabled after a system reset. Access to
registers for these peripherals can be achieved directly via the AHB bus. Note that all peripheral
registers in the AHB bus support only word access.
System Architecture
APB Peripherals
The address of APB peripherals ranges from 0x4000_0000 to 0x4007_FFFF. An APB to AHB
Bridge provides access capability between the CPU and the APB peripherals. Additionally, the
APB peripheral clocks are disabled after a system reset. Software must enable the peripheral clock
by setting the APBCCRn register in the Clock Control Unit before accessing the corresponding
peripheral register. Note that the APB to AHB Bridge will duplicate the half-word or byte data to
word width when a half-word or byte access is performed on the APB peripheral registers. In other
words, the access result of a half-word or byte access on the APB peripheral register will vary
depending on the data bit width of the access operation on the peripheral registers.
Rev. 1.10 29 of 366 November 09, 2018
32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230
4
Flash Memory Controller (FMC)
Introduction
The Flash Memory Controller, FMC, provides all the necessary ash operation functions and pre-
fetch buffer for the embedded on-chip Flash memory. Figure below shows the block diagram of the
FMC which includes programming interface, control register, pre-fetch buffer and access interface.
Since the Flash memory access speed is slower than the CPU, a wide access interface with the
pre-fetch buffer is provided to the Flash memory in order to reduce the CPU waiting time which
will cause the CPU instruction execution delays. The Flash memory word program and page erase
functions are also provided for instruction/data storage.
Peripheral Bus
AHB
System Bus
Flash Memory Controller
Control Register
Pre-fetch Buffer
Wait State
Control
Addressing
Data
Programming
Control
Flash Memory Controller (FMC)
Flash
Information
Block
Main Flash
Memory
Figure 5. Flash Memory Controller Block Diagram
Features
▄
Up to 32 KB of on-chip Flash memory for storing instruction/data and options
● 32 KB (instruction/data + Option Byte)
● 16 KB (instruction/data + Option Byte)
▄
Page size of 1K Byte, totally up to 32 pages depending on the main Flash size
▄
Wide access interface with pre-fetch buffer to reduce instruction execution delay
▄
Page erase and mass erase capability
▄
32-bit word programming
▄
Interrupt function to indicate the end of Flash memory operation or an error occurs
▄
Flash read protection to prevent illegal code/data access
▄
Page erase/program protection to prevent unexpected operation
Rev. 1.10 30 of 366 November 09, 2018
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