Holtek HT32F52220, HT32F52230 User Manual

Holtek 32-Bit Microcontroller with Arm® Cortex®-M0+ Core

HT32F52220/HT32F52230

User Manual

Revision: V1.10 Date: November 09, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230

Table of Contents

1 Introduction ........................................................................................................... 17

Overview .............................................................................................................................. 17

Features ............................................................................................................................... 18

Device Information ............................................................................................................... 21

Block Diagram ..................................................................................................................... 22

2 Document Conventions ....................................................................................... 23

3 System Architecture ............................................................................................. 24

Arm® Cortex®-M0+ Processor .............................................................................................. 24

Bus Architecture ................................................................................................................... 25

Memory Organization .......................................................................................................... 26

Memory Map ................................................................................................................................... 27

Embedded Flash Memory ............................................................................................................... 29

Embedded SRAM Memory ............................................................................................................. 29

AHB Peripherals ............................................................................................................................. 29

APB Peripherals ............................................................................................................................. 29

Table of Contents

4 Flash Memory Controller (FMC) .......................................................................... 30

Introduction .......................................................................................................................... 30

Features ............................................................................................................................... 30

Functional Descriptions ....................................................................................................... 31

Flash Memory Map ......................................................................................................................... 31

Flash Memory Architecture ............................................................................................................. 32

Wait State Setting ........................................................................................................................... 32

Booting Conguration ..................................................................................................................... 33

Page Erase ..................................................................................................................................... 34

Mass Erase ..................................................................................................................................... 35

Word Programming ......................................................................................................................... 36

Option Byte Description .................................................................................................................. 37

Page Erase/Program Protection ..................................................................................................... 38

Security Protection .......................................................................................................................... 39

Register Map ....................................................................................................................... 40

Register Descriptions ........................................................................................................... 41

Flash Target Address Register – TADR ......................................................................................... 41

Flash Write Data Register – WRDR .............................................................................................. 42

Flash Operation Command Register – OCMR .............................................................................. 43

Flash Operation Control Register – OPCR .................................................................................... 44

Flash Operation Interrupt Enable Register – OIER ....................................................................... 45

Flash Operation Interrupt and Status Register – OISR ................................................................. 46

Flash Page Erase/Program Protection Status Register – PPSR ................................................... 48

Flash Security Protection Status Register – CPSR ....................................................................... 49

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32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230

Flash Vector Mapping Control Register – VMCR .......................................................................... 50

Flash Manufacturer and Device ID Register – MDID ..................................................................... 51

Flash Page Number Status Register – PNSR ............................................................................... 52

Flash Page Size Status Register – PSSR ..................................................................................... 53

Device ID Register – DID ............................................................................................................... 54

Flash Pre-fetch Control Register – CFCR ..................................................................................... 55

Custom ID Register n – CIDRn ( n = 0 ~3) ..................................................................................... 56

5 Power Control Unit (PWRCU) .............................................................................. 57

Introduction .......................................................................................................................... 57

Features ............................................................................................................................... 58

Functional Descriptions ....................................................................................................... 58

VDD Power Domain .......................................................................................................................... 58

1.5 V Power Domain ....................................................................................................................... 60

Operation Modes ............................................................................................................................ 60

Register Map ....................................................................................................................... 62

Register Descriptions ........................................................................................................... 63

Power Control Status Register – PWRSR ...................................................................................... 63

Power Control Register – PWRCR ................................................................................................. 64

V

Power Domain Test Register – PWRTEST ............................................................................... 66

DD

Low Voltage / Brown Out Detect Control and Status Register – LVDCSR ..................................... 67

Table of Contents

6 Clock Control Unit (CKCU) .................................................................................. 69

Introduction .......................................................................................................................... 69

Features ............................................................................................................................... 71

Function Descriptions .......................................................................................................... 71

High Speed External Crystal Oscillator – HSE ............................................................................... 71

High Speed Internal RC Oscillator – HSI ........................................................................................ 72

Phase Locked Loop – PLL .............................................................................................................. 73

Low Speed Internal RC Oscillator – LSI ......................................................................................... 74

Clock Ready Flag ........................................................................................................................... 74

System Clock (CK_SYS) Selection ................................................................................................ 75

HSE Clock Monitor ......................................................................................................................... 76

Clock Output Capability .................................................................................................................. 76

Register Map ....................................................................................................................... 77

Register Descriptions ........................................................................................................... 78

Global Clock Conguration Register – GCFGR .............................................................................. 78

Global Clock Control Register – GCCR .......................................................................................... 80

Global Clock Status Register – GCSR ........................................................................................... 82

Global Clock Interrupt Register – GCIR .......................................................................................... 83

PLL Conguration Register – PLLCFGR ........................................................................................ 84

PLL Control Register – PLLCR ....................................................................................................... 84

AHB Conguration Register – AHBCFGR ...................................................................................... 85

AHB Clock Control Register – AHBCCR ........................................................................................ 86

Rev. 1.10 3 of 366 November 09, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230

APB Conguration Register – APBCFGR ....................................................................................... 87

APB Clock Control Register 0 – APBCCR0 .................................................................................... 88

APB Clock Control Register 1 – APBCCR1 .................................................................................... 89

Clock Source Status Register – CKST ........................................................................................... 90

APB Peripheral Clock Selection Register 0 – APBPCSR0 ............................................................. 91

APB Peripheral Clock Selection Register 1 – APBPCSR1 ............................................................. 93

Low Power Control Register – LPCR ............................................................................................. 95

MCU Debug Control Register – MCUDBGCR ................................................................................ 96

7 Reset Control Unit (RSTCU) ................................................................................ 98

Introduction .......................................................................................................................... 98

Functional Descriptions ....................................................................................................... 99

Power On Reset ............................................................................................................................. 99

System Reset ................................................................................................................................. 99

AHB and APB Unit Reset ................................................................................................................ 99

Register Map ..................................................................................................................... 100

Register Descriptions ......................................................................................................... 100

Global Reset Status Register – GRSR ......................................................................................... 100

AHB Peripheral Reset Register – AHBPRSTR ............................................................................. 101

APB Peripheral Reset Register 0 – APBPRSTR0 ........................................................................ 102

APB Peripheral Reset Register 1 – APBPRSTR1 ........................................................................ 103

Table of Contents

8 General Purpose I/O (GPIO) ............................................................................... 104

Introduction ........................................................................................................................ 104

Features ............................................................................................................................. 105

Functional Descriptions ..................................................................................................... 105

Default GPIO Pin Conguration .................................................................................................... 105

General Purpose I/O – GPIO ........................................................................................................ 105

GPIO Locking Mechanism ............................................................................................................ 107

Register Map ..................................................................................................................... 107

Register Descriptions ......................................................................................................... 108

Port A Data Direction Control Register – PADIRCR ..................................................................... 108

Port A Input Function Enable Control Register – PAINER ............................................................ 109

Port A Pull-Up Selection Register – PAPUR ..................................................................................110

Port A Pull-Down Selection Register – PAPDR .............................................................................111

Port A Open Drain Selection Register – PAODR ...........................................................................112

Port A Output Current Drive Selection Register – PADRVR ..........................................................113

Port A Lock Register – PALOCKR .................................................................................................114

Port A Data Input Register – PADINR ............................................................................................115

Port A Output Data Register – PADOUTR .....................................................................................116

Port A Output Set/Reset Control Register – PASRR .....................................................................117

Port A Output Reset Register – PARR ...........................................................................................118

Port B Data Direction Control Register – PBDIRCR ......................................................................119

Port B Input Function Enable Control Register – PBINER ........................................................... 120

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32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230

Port B Pull-Up Selection Register – PBPUR ................................................................................ 121

Port B Pull-Down Selection Register – PBPDR ............................................................................ 122

Port B Open Drain Selection Register – PBODR ......................................................................... 123

Port B Output Current Drive Selection Register – PBDRVR ........................................................ 124

Port B Lock Register – PBLOCKR ................................................................................................ 125

Port B Data Input Register – PBDINR .......................................................................................... 126

Port B Output Data Register – PBDOUTR ................................................................................... 127

Port B Output Set/Reset Control Register – PBSRR .................................................................... 128

Port B Output Reset Register – PBRR ......................................................................................... 129

9 Alternate Function Input/Output Control Unit (AFIO) ...................................... 130

Introduction ........................................................................................................................ 130

Features ............................................................................................................................. 131

Functional Descriptions ..................................................................................................... 131

External Interrupt Pin Selection .................................................................................................... 131

Alternate Function ......................................................................................................................... 132

Lock Mechanism .......................................................................................................................... 132

Register Map ..................................................................................................................... 132

Register Descriptions ......................................................................................................... 133

EXTI Source Selection Register 0 – ESSR0 ................................................................................ 133

EXTI Source Selection Register 1 – ESSR1 ................................................................................ 134

GPIO x Conguration Low Register – GPxCFGLR, x = A, B ........................................................ 135

GPIO x Conguration High Register – GPxCFGHR, x = A, B ...................................................... 136

Table of Contents

10 Nested Vectored Interrupt Controller (NVIC) .................................................. 137

Introduction ........................................................................................................................ 137

Features ............................................................................................................................. 138

Function Descriptions ........................................................................................................ 139

SysTick Calibration ....................................................................................................................... 139

Register Map ..................................................................................................................... 139

11 External Interrupt/Event Controller (EXTI) ...................................................... 140

Introduction ........................................................................................................................ 140

Features ............................................................................................................................. 140

Function Descriptions ........................................................................................................ 141

Wakeup Event Management......................................................................................................... 141

External Interrupt/Event Line Mapping ......................................................................................... 142

Interrupt and Debounce ................................................................................................................ 142

Register Map ..................................................................................................................... 143

Register Descriptions ......................................................................................................... 144

EXTI Interrupt Conguration Register n – EXTICFGRn, n = 0 ~ 15 ............................................. 144

EXTI Interrupt Control Register – EXTICR ................................................................................... 145

EXTI Interrupt Edge Flag Register – EXTIEDGEFLGR ................................................................ 146

EXTI Interrupt Edge Status Register – EXTIEDGESR ................................................................. 147

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32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230

EXTI Interrupt Software Set Command Register – EXTISSCR .................................................... 148

EXTI Interrupt Wakeup Control Register – EXTIWAKUPCR ........................................................ 149

EXTI Interrupt Wakeup Polarity Register – EXTIWAKUPPOLR ................................................... 150

EXTI Interrupt Wakeup Flag Register – EXTIWAKUPFLG ........................................................... 151

12 Analog to Digital Converter (ADC) .................................................................. 152

Introduction ........................................................................................................................ 152

Features ............................................................................................................................. 153

Function Descriptions ........................................................................................................ 154

ADC Clock Setup .......................................................................................................................... 154

Channel Selection ......................................................................................................................... 154

Conversion Mode .......................................................................................................................... 154

Start Conversion on External Event .............................................................................................. 157

Sampling Time Setting .................................................................................................................. 158

Data Format .................................................................................................................................. 158

Analog Watchdog.......................................................................................................................... 158

Interrupts ....................................................................................................................................... 159

Register Map ..................................................................................................................... 160

Register Descriptions ......................................................................................................... 161

ADC Conversion Control Register – ADCCR ............................................................................... 161

ADC Conversion List Register 0 – ADCLST0 ............................................................................... 163

ADC Conversion List Register 1 – ADCLST1 ............................................................................... 164

ADC Input Sampling Time Register – ADCSTR ........................................................................... 165

ADC Conversion Data Register y – ADCDRy, y = 0 ~ 7 ............................................................... 166

ADC Trigger Control Register – ADCTCR .................................................................................... 167

ADC Trigger Source Register – ADCTSR ..................................................................................... 168

ADC Watchdog Control Register – ADCWCR .............................................................................. 169

ADC Watchdog Threshold Register – ADCTR .............................................................................. 170

ADC Interrupt Enable Register – ADCIER ................................................................................... 171

ADC Interrupt Raw Status Register – ADCIRAW ......................................................................... 172

ADC Interrupt Status Register – ADCISR ..................................................................................... 173

ADC Interrupt Clear Register – ADCICLR .................................................................................... 174

Table of Contents

13 General-Purpose Timer (GPTM) ...................................................................... 175

Introduction ........................................................................................................................ 175

Features ............................................................................................................................. 176

Functional Descriptions ..................................................................................................... 177

Counter Mode ............................................................................................................................... 177

Clock Controller ............................................................................................................................ 180

Trigger Controller .......................................................................................................................... 181

Slave Controller ............................................................................................................................ 182

Master Controller .......................................................................................................................... 185

Channel Controller ........................................................................................................................ 186

Input Stage ................................................................................................................................... 189

Rev. 1.10 6 of 366 November 09, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230

Quadrature Decoder ..................................................................................................................... 191

Output Stage ................................................................................................................................. 193

Update Management .................................................................................................................... 197

Single Pulse Mode ........................................................................................................................ 198

Asymmetric PWM Mode ............................................................................................................... 200

Trigger ADC Start.......................................................................................................................... 201

Register Map ..................................................................................................................... 201

Register Descriptions ......................................................................................................... 202

Timer Counter Conguration Register – CNTCFR ....................................................................... 202

Timer Mode Conguration Register – MDCFR ............................................................................. 203

Timer Trigger Conguration Register – TRCFR ............................................................................ 206

Timer Counter Register – CTR ..................................................................................................... 207

Channel 0 Input Conguration Register – CH0ICFR .................................................................... 208

Channel 1 Input Conguration Register – CH1ICFR .................................................................... 209

Channel 2 Input Conguration Register – CH2ICFR .....................................................................211

Channel 3 Input Conguration Register – CH3ICFR .................................................................... 212

Channel 0 Output Conguration Register – CH0OCFR ............................................................... 214

Channel 1 Output Conguration Register – CH1OCFR ............................................................... 216

Channel 2 Output Conguration Register – CH2OCFR ............................................................... 217

Channel 3 Output Conguration Register – CH3OCFR ............................................................... 219

Channel Control Register – CHCTR ............................................................................................. 221

Channel Polarity Conguration Register – CHPOLR .................................................................... 222

Timer Interrupt Control Register – DICTR .................................................................................... 223

Timer Event Generator Register – EVGR ..................................................................................... 224

Timer Interrupt Status Register – INTSR ...................................................................................... 225

Timer Counter Register – CNTR................................................................................................... 227

Timer Prescaler Register – PSCR ................................................................................................ 228

Timer Counter Reload Register – CRR ........................................................................................ 229

Channel 0 Capture/Compare Register – CH0CCR ...................................................................... 230

Channel 1 Capture/Compare Register – CH1CCR ...................................................................... 231

Channel 2 Capture/Compare Register – CH2CCR ...................................................................... 232

Channel 3 Capture/Compare Register – CH3CCR ...................................................................... 233

Channel 0 Asymmetric Compare Register – CH0ACR ................................................................. 234

Channel 1 Asymmetric Compare Register – CH1ACR ................................................................. 234

Channel 2 Asymmetric Compare Register – CH2ACR ................................................................. 235

Channel 3 Asymmetric Compare Register – CH3ACR ................................................................. 235

Table of Contents

14 Basic Function Timer (BFTM) .......................................................................... 236

Introduction ........................................................................................................................ 236

Features ............................................................................................................................. 236

Functional Description ....................................................................................................... 237

Repetitive Mode ............................................................................................................................ 237

One Shot Mode ............................................................................................................................. 238

Trigger ADC Start.......................................................................................................................... 238

Rev. 1.10 7 of 366 November 09, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230

Register Map ..................................................................................................................... 239

Register Descriptions ......................................................................................................... 239

BFTM Control Register – BFTMCR .............................................................................................. 239

BFTM Status Register – BFTMSR ................................................................................................ 240

BFTM Counter Register – BFTMCNTR ........................................................................................ 241

BFTM Compare Value Register – BFTMCMPR ........................................................................... 241

15 Single-Channel Timer (SCTM) ......................................................................... 242

Introduction ........................................................................................................................ 242

Features ............................................................................................................................. 243

Functional Descriptions ..................................................................................................... 243

Counter Mode ............................................................................................................................... 243

Clock Controller ............................................................................................................................ 244

Trigger Controller .......................................................................................................................... 245

Slave Controller ............................................................................................................................ 246

Channel Controller ........................................................................................................................ 248

Input Stage ................................................................................................................................... 249

Output Stage ................................................................................................................................. 250

Update Management .................................................................................................................... 252

Register Map ..................................................................................................................... 253

Register Descriptions ......................................................................................................... 254

Timer Counter Conguration Register – CNTCFR ....................................................................... 254

Timer Mode Conguration Register – MDCFR ............................................................................. 255

Timer Trigger Conguration Register – TRCFR ............................................................................ 256

Timer Counter Register – CTR ..................................................................................................... 257

Channel Input Conguration Register – CHICFR ......................................................................... 258

Channel Output Conguration Register – CHOCFR ................................................................... 260

Channel Control Register – CHCTR ............................................................................................. 261

Channel Polarity Conguration Register – CHPOLR .................................................................... 262

Timer Interrupt Control Register – DICTR .................................................................................... 263

Timer Event Generator Register – EVGR ..................................................................................... 264

Timer Interrupt Status Register – INTSR ...................................................................................... 265

Timer Counter Register – CNTR................................................................................................... 266

Timer Prescaler Register – PSCR ................................................................................................ 266

Timer Counter Reload Register – CRR ........................................................................................ 267

Channel Capture/Compare Register – CHCCR ........................................................................... 268

Table of Contents

16 Watchdog Timer (WDT) .................................................................................... 269

Introduction ........................................................................................................................ 269

Features ............................................................................................................................. 269

Functional Description ....................................................................................................... 270

Register Map ..................................................................................................................... 272

Register Descriptions ......................................................................................................... 272

Watchdog Timer Control Register – WDTCR ............................................................................... 272

Rev. 1.10 8 of 366 November 09, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230

Watchdog Timer Mode Register 0 – WDTMR0............................................................................. 273

Watchdog Timer Mode Register 1 – WDTMR1............................................................................. 274

Watchdog Timer Status Register – WDTSR ................................................................................. 275

Watchdog Timer Protection Register – WDTPR ........................................................................... 276

Watchdog Timer Clock Selection Register – WDTCSR ............................................................... 277

17 Inter-Integrated Circuit (I2C) ............................................................................. 278

Introduction ........................................................................................................................ 278

Features ............................................................................................................................. 279

Functional Descriptions ..................................................................................................... 279

Two Wire Serial Interface .............................................................................................................. 279

START and STOP Conditions ....................................................................................................... 279

Data Validity .................................................................................................................................. 280

Addressing Format ....................................................................................................................... 281

Data Transfer and Acknowledge ................................................................................................... 283

Clock Synchronization .................................................................................................................. 284

Arbitration ..................................................................................................................................... 284

General Call Addressing ............................................................................................................... 285

Bus Error ....................................................................................................................................... 285

Address Mask Enable ................................................................................................................... 285

Address Snoop ............................................................................................................................. 285

Operation Mode ............................................................................................................................ 285

Conditions of Holding SCL Line .................................................................................................... 291

I2C Timeout Function .................................................................................................................... 292

Register Map ..................................................................................................................... 292

Register Descriptions ......................................................................................................... 293

I2C Control Register – I2CCR ....................................................................................................... 293

I2C Interrupt Enable Register – I2CIER ........................................................................................ 294

I2C Address Register – I2CADDR ................................................................................................. 296

I2C Status Register – I2CSR ......................................................................................................... 297

I2C SCL High Period Generation Register – I2CSHPGR .............................................................. 300

I2C SCL Low Period Generation Register – I2CSLPGR ............................................................... 301

I2C Data Register – I2CDR ........................................................................................................... 302

I2C Target Register – I2CTAR ....................................................................................................... 303

I2C Address Mask Register – I2CADDMR .................................................................................... 304

I2C Address Snoop Register – I2CADDSR ................................................................................... 305

I2C Timeout Register – I2CTOUT.................................................................................................. 306

Table of Contents

18 Serial Peripheral Interface (SPI) ...................................................................... 307

Introduction ........................................................................................................................ 307

Features ............................................................................................................................. 308

Function Descriptions ........................................................................................................ 308

Master Mode ................................................................................................................................. 308

Slave Mode ................................................................................................................................... 308

Rev. 1.10 9 of 366 November 09, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230

SPI Serial Frame Format .............................................................................................................. 309

Status Flags .................................................................................................................................. 313

Register Map ..................................................................................................................... 315

Register Descriptions ......................................................................................................... 316

SPI Control Register 0 – SPICR0 ................................................................................................. 316

SPI Control Register 1 – SPICR1 ................................................................................................. 317

SPI Interrupt Enable Register – SPIIER ....................................................................................... 319

SPI Clock Prescaler Register – SPICPR ...................................................................................... 320

SPI Data Register – SPIDR .......................................................................................................... 321

SPI Status Register – SPISR ........................................................................................................ 321

SPI FIFO Control Register – SPIFCR ........................................................................................... 323

SPI FIFO Status Register – SPIFSR ............................................................................................ 324

SPI FIFO Time Out Counter Register – SPIFTOCR ..................................................................... 325

19 Universal Synchronous Asynchronous Receiver Transmitter (USART) ..... 326

Introduction ........................................................................................................................ 326

Features ............................................................................................................................. 327

Function Descriptions ........................................................................................................ 328

Serial Data Format ........................................................................................................................ 328

Baud Rate Generation .................................................................................................................. 329

Hardware Flow Control ................................................................................................................. 331

IrDA ............................................................................................................................................... 332

RS485 Mode ................................................................................................................................. 335

Synchronous Master Mode ........................................................................................................... 338

Interrupts and Status .................................................................................................................... 340

Register Map ..................................................................................................................... 340

Register Descriptions ......................................................................................................... 341

USART Data Register – USRDR .................................................................................................. 341

USART Control Register – USRCR .............................................................................................. 342

USART FIFO Control Register – USRFCR................................................................................... 344

USART Interrupt Enable Register – USRIER ............................................................................... 345

USART Status & Interrupt Flag Register – USRSIFR................................................................... 346

USART Timing Parameter Register – USRTPR ........................................................................... 348

USART IrDA Control Register – IrDACR ...................................................................................... 349

USART RS485 Control Register – RS485CR............................................................................... 350

USART Synchronous Control Register – SYNCR ........................................................................ 351

USART Divider Latch Register – USRDLR................................................................................... 352

USART Test Register – USRTSTR ............................................................................................... 353

Table of Contents

20 Universal Asynchronous Receiver Transmitter (UART) ................................ 354

Introduction ........................................................................................................................ 354

Features ............................................................................................................................. 355

Function Descriptions ........................................................................................................ 355

Serial Data Format ........................................................................................................................ 355

Rev. 1.10 10 of 366 November 09, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230

Baud Rate Generation .................................................................................................................. 356

Interrupts and Status .................................................................................................................... 358

Register Map ..................................................................................................................... 358

Register Descriptions ......................................................................................................... 359

UART Data Register – URDR ....................................................................................................... 359

UART Control Register – URCR ................................................................................................... 359

UART Interrupt Enable Register – URIER .................................................................................... 361

UART Status & Interrupt Flag Register – URSIFR ....................................................................... 362

UART Divider Latch Register – URDLR ....................................................................................... 364

UART Test Register – URTSTR .................................................................................................... 365

Table of Contents

Rev. 1.10 11 of 366 November 09, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230

List of Tables

Table 1. Features and Peripheral List ..................................................................................................... 21

Table 2. Document Conventions ............................................................................................................. 23

Table 3. Register Map ............................................................................................................................. 28

Table 4. Flash Memory and Option Byte ................................................................................................. 32

Table 5. Relationship between Wait State Cycle and HCLK ................................................................... 32

Table 6. Boot Modes ............................................................................................................................... 33

Table 7. Option Byte Memory Map ......................................................................................................... 37

Table 8. Access Permission of Protected Main Flash Page .................................................................... 38

Table 9. Access Permission When Security Protection is Enabled ......................................................... 39

Table 10. FMC Register Map .................................................................................................................. 40

Table 11. Operation Mode Denitions ..................................................................................................... 60

Table 12. Enter/Exit Power Saving Modes .............................................................................................. 61

Table 13. Power Status After System Reset ........................................................................................... 62

Table 14. PWRCU Register Map ............................................................................................................ 62

Table 15. Output Divider2 Value Mapping............................................................................................... 74

Table 16. Feedback Divider2 Value Mapping.......................................................................................... 74

Table 17. CKOUT Clock Source ............................................................................................................. 76

Table 18. CKCU Register Map ............................................................................................................... 77

Table 19. RSTCU Register Map ........................................................................................................... 100

Table 20. AFIO, GPIO and IO Pad Control Signal True Table............................................................... 106

Table 21. GPIO Register Map ............................................................................................................... 107

Table 22. AFIO Selection for Peripheral Map Example ......................................................................... 132

Table 23. AFIO Register Map ................................................................................................................ 132

Table 24. Exception Types .................................................................................................................... 137

Table 25. NVIC Register Map ............................................................................................................... 139

Table 26. EXTI Register Map ................................................................................................................ 143

Table 27. Data format in ADCDR [15:0] ................................................................................................ 158

Table 28. A/D Converter Register Map ................................................................................................. 160

Table 29. Counting Direction and Encoding Signals ............................................................................. 192

Table 30. Compare Match Output Setup .............................................................................................. 193

Table 31. GPTM Register Map ............................................................................................................. 201

Table 32. GPTM Internal Trigger Connection ....................................................................................... 206

Table 33. BFTM Register Map .............................................................................................................. 239

Table 34. Compare Match Output Setup .............................................................................................. 250

Table 35. SCTM Register Map .............................................................................................................. 253

Table 36. Watchdog Timer Register Map .............................................................................................. 272

Table 37. Conditions of Holding SCL line .............................................................................................. 291

Table 38. I2C Register Map ................................................................................................................... 292

Table 39. I2C Clock Setting Example .................................................................................................... 302

List of Tables

Rev. 1.10 12 of 366 November 09, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230

Table 40. SPI Interface Format Setup ................................................................................................... 309

Table 41. SPI Mode Fault Trigger Conditions ....................................................................................... 314

Table 42. SPI Master Mode SEL Pin Status ......................................................................................... 314

Table 43. SPI Register Map .................................................................................................................. 315

Table 44. Baud Rate Deviation Error Calculation – CK_USART = 8 MHz ............................................ 329

Table 45. Baud Rate Deviation Error Calculation – CK_USART = 20 MHz .......................................... 330

Table 46. Baud Rate Deviation Error Calculation – CK_USART = 24 MHz .......................................... 330

Table 47. Baud Rate Deviation Error Calculation – CK_USART = 40 MHz .......................................... 330

Table 48. USART Register Map ............................................................................................................ 340

Table 49. Baud Rate Deviation Error Calculation – CK_UART = 8 MHz .............................................. 356

Table 50. Baud Rate Deviation Error Calculation – CK_UART = 20 MHz ............................................ 357

Table 51. Baud Rate Deviation Error Calculation – CK_UART = 24 MHz ............................................ 357

Table 52. Baud Rate Deviation Error Calculation – CK_UART = 40 MHz ............................................ 357

Table 53. UART Register Map .............................................................................................................. 358

List of Tables

Rev. 1.10 13 of 366 November 09, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230

List of Figures

Figure 1. Block Diagram ......................................................................................................................... 22

Figure 2. Cortex®-M0+ Block Diagram .................................................................................................... 25

Figure 3. Bus Architecture ...................................................................................................................... 26

Figure 4. Memory Map ............................................................................................................................ 27

Figure 5. Flash Memory Controller Block Diagram ................................................................................. 30

Figure 6. Flash Memory Map .................................................................................................................. 31

Figure 7. Vector Remapping ................................................................................................................... 33

Figure 8. Page Erase Operation Flowchart ............................................................................................ 34

Figure 9. Mass Erase Operation Flowchart ............................................................................................ 35

Figure 10. Word Programming Operation Flowchart .............................................................................. 36

Figure 11. PWRCU Block Diagram ......................................................................................................... 57

Figure 12. Power On Reset / Power Down Reset Waveform ................................................................. 59

Figure 13. CKCU Block Diagram ............................................................................................................ 70

Figure 14. External Crystal, Ceramic, and Resonators for HSE ............................................................. 71

Figure 15. PLL Block Diagram ................................................................................................................ 73

Figure 16. RSTCU Block Diagram .......................................................................................................... 98

Figure 17. Power On Reset Sequence ................................................................................................... 99

Figure 18. GPIO Block Diagram ........................................................................................................... 104

Figure 19. AFIO/GPIO Control Signal ................................................................................................... 106

Figure 20. AFIO Block Diagram ............................................................................................................ 130

Figure 21. EXTI Channel Input Selection ............................................................................................. 131

Figure 22. EXTI Block Diagram ............................................................................................................ 140

Figure 23. EXTI Wake-up Event Management ..................................................................................... 141

Figure 24. EXTI Interrupt Debounce Function ...................................................................................... 142

Figure 25. ADC Block Diagram ............................................................................................................ 152

Figure 26. One Shot Conversion Mode ................................................................................................ 155

Figure 27. Continuous Conversion Mode ............................................................................................. 155

Figure 28. Discontinuous Conversion Mode ......................................................................................... 157

Figure 29. GPTM Block Diagram .......................................................................................................... 175

Figure 30. Up-counting Example .......................................................................................................... 177

Figure 31. Down-counting Example ...................................................................................................... 178

Figure 32. Center-aligned Counting Example ....................................................................................... 179

Figure 33. GPTM Clock Selection Source ............................................................................................ 180

Figure 34. Trigger Controller Block ....................................................................................................... 181

Figure 35. Slave Controller Diagram .................................................................................................... 182

Figure 36. GPTM in Restart Mode ........................................................................................................ 182

Figure 37. GPTM in Pause Mode ......................................................................................................... 183

Figure 38. GPTM in Trigger Mode ........................................................................................................ 184

Figure 39. Master GPTMn and Slave GPTMm/MCTMm Connection ................................................... 185

List of Figures

Rev. 1.10 14 of 366 November 09, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230

Figure 40. MTO Selection ..................................................................................................................... 185

Figure 41. Capture/Compare Block Diagram ........................................................................................ 186

Figure 42. Input Capture Mode ............................................................................................................. 187

Figure 43. PWM Pulse Width Measurement Example .......................................................................... 188

Figure 44. Channel 0 and Channel 1 Input Stages ............................................................................... 189

Figure 45. Channel 2 and Channel 3 Input Stages ............................................................................... 190

Figure 46. TI0 Digital Filter Diagram with N = 2 .................................................................................... 190

Figure 47. Input Stage and Quadrature Decoder Block Diagram ......................................................... 191

Figure 48. Both TI0 and TI1 Quadrature Decoder Counting ................................................................. 192

Figure 49. Output Stage Block Diagram ............................................................................................... 193

Figure 50. Toggle Mode Channel Output Reference Signal – CHxPRE = 0 ......................................... 194

Figure 51. Toggle Mode Channel Output Reference Signal – CHxPRE = 1 ......................................... 194

Figure 52. PWM Mode Channel Output Reference Signal and Counter in Up-counting Mode ............ 195

Figure 53. PWM Mode Channel Output Reference Signal and Counter in Down-counting Mode ....... 195

Figure 54. PWM Mode Channel Output Reference Signal and Counter in Centre-align Mode ............ 196

Figure 55. Update Event Setting Diagram ............................................................................................ 197

Figure 56. Single Pulse Mode ............................................................................................................... 198

Figure 57. Immediate Active Mode Minimum Delay ............................................................................. 199

Figure 58. Asymmetric PWM Mode versus Center Align Counting Mode ............................................. 200

Figure 59. BFTM Block Diagram .......................................................................................................... 236

Figure 60. BFTM – Repetitive Mode ..................................................................................................... 237

Figure 61. BFTM – One Shot Mode ...................................................................................................... 238

Figure 62. BFTM – One Shot Mode Counter Updating ....................................................................... 238

Figure 63. SCTM Block Diagram .......................................................................................................... 242

Figure 64. Up-counting Example .......................................................................................................... 243

Figure 65. SCTM Clock Selection Source ............................................................................................ 244

Figure 66. Trigger Control Block ........................................................................................................... 245

Figure 67. Slave Controller Diagram .................................................................................................... 246

Figure 68. SCTM in Restart Mode ........................................................................................................ 246

Figure 69. SCTM in Pause Mode ......................................................................................................... 247

Figure 70. SCTM in Trigger Mode ........................................................................................................ 247

Figure 71. Capture/Compare Block Diagram ........................................................................................ 248

Figure 72. Input Capture Mode ............................................................................................................. 248

Figure 73. Channel Input Stages .......................................................................................................... 249

Figure 74. TI Digital Filter Diagram with N = 2 ...................................................................................... 249

Figure 75. Output Stage Block Diagram ............................................................................................... 250

Figure 76. Toggle Mode Channel Output Reference Signal – CHPRE = 0 ........................................... 251

Figure 77. Toggle Mode Channel Output Reference Signal – CHPRE = 1 ........................................... 251

Figure 78. PWM Mode Channel Output Reference Signal ................................................................... 252

Figure 79. Update Event Setting Diagram ............................................................................................ 253

Figure 80. Watchdog Timer Block Diagram ......................................................................................... 269

List of Figures

Rev. 1.10 15 of 366 November 09, 2018

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HT32F52220/HT32F52230

Figure 81. Watchdog Timer Behavior ................................................................................................... 271

Figure 82. I2C Module Block Diagram ................................................................................................... 278

Figure 83. START and STOP Condition ............................................................................................... 280

Figure 84. Data Validity ......................................................................................................................... 280

Figure 85. 7-bit Addressing Mode ......................................................................................................... 281

Figure 86. 10-bit Addressing Write Transmit Mode .............................................................................. 282

Figure 87. 10-bits Addressing Read Receive Mode ............................................................................ 282

Figure 88. I2C Bus Acknowledge .......................................................................................................... 283

Figure 89. Clock Synchronization during Arbitration ............................................................................. 284

Figure 90. Two Master Arbitration Procedure ....................................................................................... 284

Figure 91. Master Transmitter Timing Diagram .................................................................................... 286

Figure 92. Master Receiver Timing Diagram ........................................................................................ 288

Figure 93. Slave Transmitter Timing Diagram ...................................................................................... 289

Figure 94. Slave Receiver Timing Diagram .......................................................................................... 290

Figure 95. SCL Timing Diagram ............................................................................................................ 301

Figure 96. SPI Block Diagram .............................................................................................................. 307

Figure 97. SPI Single Byte Transfer Timing Diagram – CPOL = 0, CPHA = 0 ...................................... 309

Figure 98. SPI Continuous Data Transfer Timing Diagram – CPOL = 0, CPHA = 0 ............................. 310

Figure 99. SPI Single Byte Transfer Timing Diagram – CPOL = 0, CPHA = 1 ...................................... 310

Figure 100. SPI Continuous Transfer Timing Diagram – CPOL = 0, CPHA = 1 .....................................311

Figure 101. SPI Single Byte Transfer Timing Diagram – CPOL = 1, CPHA = 0 .....................................311

Figure 102. SPI Continuous Transfer Timing Diagram – CPOL = 1, CPHA = 0 .................................... 312

Figure 103. SPI Single Byte Transfer Timing Diagram – CPOL = 1, CPHA = 1 .................................... 312

Figure 104. SPI Continuous Transfer Timing Diagram – CPOL = 1, CPHA = 1 .................................... 312

Figure 105. SPI Multi-Master Slave Environment ................................................................................. 314

Figure 106. USART Block Diagram ...................................................................................................... 326

Figure 107. USART Serial Data Format ............................................................................................... 328

Figure 108. USART Clock CK_USART and Data Frame Timing .......................................................... 329

Figure 109. Hardware Flow Control between 2 USARTs ...................................................................... 331

Figure 110. USART RTS Flow Control.................................................................................................. 331

Figure 111. USART CTS Flow Control .................................................................................................. 332

Figure 112. IrDA Modulation and Demodulation ................................................................................... 333

Figure 113. USART I/O and IrDA Block Diagram .................................................................................. 335

Figure 114. RS485 Interface and Waveform ......................................................................................... 336

Figure 115. USART Synchronous Transmission Example .................................................................... 338

Figure 116. 8-bit Format USART Synchronous Waveform ................................................................... 339

Figure 117. UART Block Diagram ......................................................................................................... 354

Figure 118. UART Serial Data Format .................................................................................................. 355

Figure 119. UART Clock CK_UART and Data Frame Timing ............................................................... 356

List of Figures

Rev. 1.10 16 of 366 November 09, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230

1

Overview

Introduction

This user manual provides detailed information including how to use the devices, system and
bus architecture, memory organization and peripheral instructions. The target audiences for this
document are software developers, application developers and hardware developers. For more
information regarding pin assignment, package and electrical characteristics, please refer to the
datasheet.

The devices are high performance and low power consumption 32-bit microcontrollers based
around an Arm® Cortex®-M0+ processor core. The Cortex®-M0+ is a next-generation processor
core which is tightly coupled with Nested Vectored Interrupt Controller (NVIC), SysTick timer,
and including advanced debug support.

The devices operate at a frequency of up to 40 MHz for HT32F52220/52230 with a Flash

accelerator to obtain maximum efciency. It provides up to 32 KB of embedded Flash memory for
code/data storage and 4 KB of embedded SRAM memory for system operation and application

program usage. A variety of peripherals, such as ADC, I2C, USART, UART, SPI, GPTM, SCTM,

SW-DP (Serial Wire Debug Port), etc., are also implemented in the device series. Several power
saving modes provide the exibility for maximum optimization between wakeup latency and power

consumption, an especially important consideration in low power applications.

The above features ensure that the devices are suitable for use in a wide range of applications,
especially in areas such as white goods application control, power monitors, alarm systems,
consumer products, handheld equipment, data logging applications, motor control and so on.

Introduction

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32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230

Features

▄

Core

● 32-bit Arm® Cortex®-M0+ processor core

● Up to 40MHz operating frequency for HT32F52220/52230

● 0.93 DMIPS/MHz (Dhrystone v2.1)

● Single-cycle multiplication

● Integrated Nested Vectored Interrupt Controller (NVIC)

● 24-bit SysTick timer

▄

On-chip Memory

● Up to 32 KB on-chip Flash memory for instruction/data and options storage

● Up to 4 KB on-chip SRAM

● Supports multiple boot modes

▄

Flash Memory Controller – FMC

● Flash accelerator for maximum efciency

● 32-bit word programming with In System Programming Interface (ISP) and In Application

Programming (IAP)

● Flash protection capability to prevent illegal access

▄

Reset Control Unit – RSTCU

● Supply supervisor: Power On Reset / Power Down Reset (POR/PDR) and Programmable Low

Voltage Detector (LVD)

▄

Clock Control Unit – CKCU

● External 4 to 16 MHz crystal oscillator

● Internal 8 MHz RC oscillator trimmed to ±2 % accuracy at 3.3 V operating voltage and 25 ºC

operating temperature

● Internal 32 kHz RC oscillator

● Integrated system clock PLL

● Independent clock divider and gating bits for peripheral clock sources

▄

Power management – PWRCU

● Single VDD power supply: 2.0 V to 3.6 V

● Integrated 1.5 V LDO regulator for CPU core, peripherals and memories power supply

● Two power domains: VDD and 1.5 V

● Four power saving modes: Sleep, Deep-Sleep1, Deep-Sleep2, Power-Down

▄

External Interrupt/Event Controller – EXTI

● Up to 16 EXTI lines with congurable trigger source and type

● All GPIO pins can be selected as EXTI trigger source

● Source trigger type includes high level, low level, negative edge, positive edge, or both edge

● Individual interrupt enable, wakeup enable and status bits for each EXTI line

● Software interrupt trigger mode for each EXTI line

● Integrated deglitch lter for short pulse blocking

Introduction

Rev. 1.10 18 of 366 November 09, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230

▄

Analog to Digital Converter – ADC

● 12-bit SAR ADC engine

● Up to 1 MSPS conversion rate – 1 μs at 28 MHz, 1.4 μs at 40 MHz

● Up to 8 external analog input channels

▄

IO ports – GPIO

● Up to 23 GPIOs

● Port A, B are mapped as 16 external interrupts – EXTI

● Almost I/O pins are congurable output driving current

▄

PWM Generation and Capture Timer – GPTM

● One 16-bit up, down, up/down auto-reload counter

● Up to 4 independent channels for each GPTM

● 16-bit programmable prescaler allowing dividing the counter clock frequency by any factor

between 1 and 65536

● Input Capture function

● Compare Match Output

● PWM waveform generation with Edge-aligned and Center-aligned Counting Modes

● Single Pulse Mode Output

● Encoder interface controller with two inputs using quadrature decoder

▄

Single Channel PWM Generation and Capture Timers – SCTM

● One 16-bit up and auto-reload counter

● One channels for each SCTM

● 16-bit programmable prescaler allowing dividing the counter clock frequency by any factor

between 1 and 65536

● Input Capture function

● Compare Match Output

● PWM waveform generation with Edge-aligned

● Single Pulse Mode Output

▄

Basic Function Timer – BFTM

● 32-bit compare/match count-up counter – no I/O control features

● One shot mode – counting stops after a match condition

● Repetitive mode – restart counter after a match condition

▄

Watchdog Timer

● 12-bit down counter with 3-bit prescaler

● Reset event for the system

● Programmable watchdog timer window function

● Registers write protection function

▄

Inter-integrated Circuit – I2C

● Supports both master and slave modes with a frequency of up to 1 MHz

● Provide an arbitration function and clock synchronization

● Supports 7-bit and 10-bit addressing modes and general call addressing

● Supports slave multi-addressing mode with maskable address

Introduction

Rev. 1.10 19 of 366 November 09, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230

▄

Serial Peripheral Interface – SPI

● Supports both master and slave mode

● Frequency of up to (f

● FIFO Depth: 8 levels

● Multi-master and multi-slave operation

▄

Universal Synchronous Asynchronous Receiver Transmitter – USART

● Supports both asynchronous and clocked synchronous serial communication modes

● Asynchronous operating baud rate up to (f

(f

/8) MHz

PCLK

● Capability of full duplex communication

● Fully programmable characteristics of serial communication including: word length, parity bit,

stop bit and bit order

● Error detection: Parity, overrun, and frame error

● Support Auto hardware ow control mode – RTS, CTS

● IrDA SIR encoder and decoder

● RS485 mode with output enable control

● FIFO Depth: 8 × 9 bits for both receiver and transmitter

▄

Universal Asynchronous Receiver Transmitter – UART

● Asynchronous serial communication operating baud-rate up to (f

● Capability of full duplex communication

● Fully programmable characteristics of serial communication including: word length, parity bit,

stop bit and bit order

● Error detection: Parity, overrun, and frame error

▄

Debug Support

● Serial Wire Debug Port – SW-DP

● 4 comparators for hardware breakpoint or code / literal patch

● 2 comparators for hardware watchpoints

▄

Package and Operation Temperature

● 24/28-pin SSOP, 33-pin QFN package

● Operation temperature range: -40 °C to +85 °C

/2) MHz for master mode and (f

PCLK

/16) MHz and synchronous operating rate up to

PCLK

/3) MHz for slave mode

PCLK

/16) MHz

PCLK

Introduction

Rev. 1.10 20 of 366 November 09, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230

Device Information

Table 1. Features and Peripheral List

Peripherals HT32F52220 HT32F52230

Main Flash (KB) 16 31

Option Bytes Flash (KB) 1 1

SRAM (KB) 4 4

GPTM 1

Timers

Communication

EXTI 16

12-bit ADC
Number of channels

GPIO Up to 23

CPU frequency Up to 40 MHz

Operating voltage 2.0 V ~ 3.6 V

Operating temperature -40 °C ~ +85 °C

Package 24/28-pin SSOP, 33-pin QFN

SCTM 2

BFTM 1

WDT 1

SPI 1

USART 1

UART 1

I2C 1

Introduction

1

8 Channels

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32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230

Block Diagram

TX, RX
RTS/TXE
CTS/SCK

TX, RX

SWCLK SWDIO

AF

SW-DP

Cortex® -M0+

Processor

NVIC

Interrupt request

AF

AF

PA; PB

IO Port

GPIO

System

Bus Matrix

USART

UART

AFIO

EXTI

BOOT

AF

Flash Memory

Interface

FMC

Control Registers

AHB Peripherals

SRAM Controller

AHB to APB

Bridge

APB

Powered by V

Flash

Memory

CKCU/RSTCU

Control Registers

SRAM

WDT

SPI

I2C

GPTM

BFTM

SCTM0 ~ 1

DD15

V

DD

DD

V

SS

AF

XTALIN
XTALOUT

CLDO

AF

MOSI, MISO
SCK, SEL

AF

SDA SCL

AF

CH3 ~ CH0

AF

SCTM0 ~
SCTM1

Introduction

CAP.

POR
/PDR

HSE

4 ~ 16

MHz

HSI

8 MHz

Clock and reset control

LDO

1.5 V

BOD

LVD

Powered by V

PLL

Power control

V

AF

ADC_IN0

...

ADC_IN11

V

DDA

V

SSA

Power supply:

Bus:

Control signal:

Alternate function:

12-bit SAR

ADC

Powered by V

AF

ADC

PWRCU

DDA

Powered by V

DD15

Powered by V

LSI

32 kHz

DD

V

AF

WAKEUP

nRST

DD

SS

Figure 1. Block Diagram

Rev. 1.10 22 of 366 November 09, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230

2

Document Conventions

The conventions used in this document are shown in the following table.

Table 2. Document Conventions

Notation Example Description

0x 0x5a05

0xnnnn_nnnn 0x2000_0100 32-bit Hexadecimal address or data.

b b0101

NAME [n] ADDR [5]

NAME [m:n] ADDR [11:5]

X b10X1 Don’t care notation which means any value is allowed.

RW

RO

RC

WC

W0C

WO

Reserved

SERDYIE

HSIRDY

SERDYF

PLLRDYIE

RW 0 RW 0

3 2

RO 1 RO 0

WC 0 WC 0

RXCF

RO 0 W0C 0

WO 0 WO 0

LLRDY

RO 0

HSERDY

1 0

PDF

BAK_PORF

RC 0 RC 1

3 2

PLLRDYF

1 0

PARF

31 30

DB_CKSRC

1

Reserved

19 18

Word Data length of a word is 32-bit.

Half-word Data length of a half-word is 16-bit.

Byte Data length of a byte is 8-bit.

The number string with a 0x prefix indicates a hexadecimal
number.

The number string with a lowercase b prex indicates a binary

number.

Specic bit of NAME. NAME can be a register or eld of register.
For example, ADDR [5] means bit 5 of ADDR register (eld).

Specific bits of NAME. NAME can be a register or field of
register. For example, ADDR [11:5] means bit 11 to 5 of ADDR

register (eld).

Software can read and write to this bit.

Software can only read this bit. A write operation will have no
effect.

Software can only read this bit. Read operation will clear it to 0
automatically.

Software can read this bit or clear it by writing 1. Writing a 0 will
have no effect.

Software can read this bit or clear it by writing 0. Writing a 1 will
have no effect.

Software can only write to this bit. A read operation always
returns 0.

Reserved bit(s) for future use. Data read from these bits is not

0

well defined and should be treated as random data. Normally
these reserved bits should be set to a 0 value. Note that
reserved bit must be kept at reset value.

Document Conventions

Rev. 1.10 23 of 366 November 09, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230

3

System Architecture

The system architecture of devices that includes the Arm® Cortex®-M0+ processor, bus architecture
and memory organization will be described in the following sections. The Cortex®-M0+ is a next
generation processor core which offers many new features. Integrated and advanced features make
the Cortex®-M0+ processor suitable for market products that require microcontrollers with high
performance and low power consumption. In brief, The Cortex®-M0+ processor includes AHB-Lite
bus interface. All memory accesses of the Cortex®-M0+ processor are executed on the AHB-Lite
bus according to the different purposes and the target memory spaces. The memory organization

uses a Harvard architecture, pre-dened memory map and up to 4 GB of memory space, making
the system exible and extendable.

Arm® Cortex®-M0+ Processor

The Cortex®-M0+ processor is a very low gate count, highly energy efficient processor that is
intended for microcontroller and deeply embedded applications that require an area optimized,

low-power processor. The processor is based on the ARMv6-M architecture and supports Thumb®

instruction sets; single-cycle I/O port; hardware multiplier and low latency interrupt respond time.
Some system peripherals listed below are also provided by Cortex®-M0+:

▄

Internal Bus Matrix connected with AHB-Lite Interface, Single-cycle I/O port and Debug
Accesses Port (DAP)

▄

Nested Vectored Interrupt Controller (NVIC)

▄

Optional Wakeup Interrupt Controller (WIC)

▄

Breakpoint and Watchpoint Unit

▄

Optional Memory Protection Unit (MPU)

▄

Serial Wire debug Port (SW-DP)

▄

Optional Micro Trace Buffer Interface (MTB)

The following gure shows the Cortex®-M0+ processor block diagram. For more information, refer

to the Arm® Cortex®-M0+ Technical Reference Manual.

System Architecture

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32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230

®

Cortex

-M0+ Components

Execution Trace Interface

Interrupts

‡ Wakeup

Interrupt

Controller (WIC)

‡ Optional Componect

Figure 2. Cortex®-M0+ Block Diagram

Bus Architecture

The HT32F52220/HT32F52230 series consists of one master and four slaves in the bus architecture.
The Cortex®-M0+ AHB-Lite bus is the master while the internal SRAM access bus, the internal

Flash memory access bus, the AHB peripherals access bus and the AHB to APB bridges are the
slaves. The single 32-bit AHB-Lite system interface provides simple integration to all system
regions include the internal SRAM region and the peripheral region. All of the master buses are
based on 32-bit Advanced High-performance Bus-Lite (AHB-Lite) protocol. The following gure

shows the bus architecture of the HT32F52220/HT32F52230 series.

Cortex-M0+ Processor

Nested

Vectored

Interrupt

Controller

(NVIC)

Cortex®-M0+

Processor

Core

‡ Memory
Protection

Unit

AHB-Lite Interface

to System

Bus Matrix

Debug

‡ Breakpoint

and

Watchpoint

Unit

‡ Debugger

Interface

‡ Single-cycle

I/O Port

‡ Debug

Access Port

(DAP)

‡ Serial Wire or JTAG

Debug Port

System Architecture

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32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230

GPIO

Cortex® -M0+

Processor

NVIC

Interrupt request

Figure 3. Bus Architecture

Memory Organization

I/O Port

System

Flash Memory

Interface

FMC

Control Registers

Bus Matrix

AHB Peripherals

SRAM Controller

AHB to APB

Bridge

Control Registers

Flash

Memory

CKCU/RSTCU

SRAM

APB IPs

System Architecture

The Arm® Cortex®-M0+ processor accesses and debug accesses share the single external

interface to external AHB peripheral. The processor accesses take priority over debug accesses.

The maximum address range of the Cortex®-M0+ is 4 GB since it has 32-bit bus address width.
Additionally, a pre-defined memory map is provided by the Cortex®-M0+ processor to reduce
the software complexity of repeated implementation of different device vendors. However, some
regions are used by the Arm® Cortex®-M0+ system peripherals. Refer to the Arm® Cortex®-M0+

Technical Reference Manual for more information. The following gure shows the memory map
of HT32F52220/HT32F52230 series of devices, including Code, SRAM, peripheral, and other pre­dened regions.

Rev. 1.10 26 of 366 November 09, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230

Memory Map

0xFFFF_FFFF

0xE010_0000

0xE000_0000

0x4010_0000

Peripheral

SRAM

Code

0x4008_0000

0x4000_0000

0x2000_1000

0x2000_0000

0x1FF0_0400

0x1FF0_0000

0x1F00_0800

0x1F00_0000

0x000_8000

Reserved

Private peripheral bus

Reserved

AHB peripherals

APB peripherals

Reserved

Up to

4 KB on-chip SRAM

Reserved

Option byte alias

Reserved

Boot loader

Reserved

512 KB

512 KB

4 KB

1 KB

2 KB

0x400F_FFFF

0x400B_4000

0x400B_0000

0x4008_A000

0x4007_7000

0x4007_6000

0x4007_5000

0x4006_F000

0x4006_E000

0x4006_B000

0x4006_A000

0x4006_9000

0x4006_8000

0x4004_9000

0x4004_8000

0x4003_5000

0x4003_4000

0x4002_5000

0x4002_4000

0x4002_3000

0x4002_2000

0x4001_1000

0x4001_0000

0x4000_5000

0x4000_2000

0x4000_1000
0x4000_0000

Reserved

GPIO A ～ B

Reserved

CKCU/RSTCU0x4008_8000

Reserved0x4008_2000

FMC0x4008_0000

Reserved

BFTM

Reserved

SCTM10x4007_4000

Reserved

GPTM

Reserved

PWRCU

Reserved

WDT

Reserved

I2C

Reserved

SCTM0

Reserved

EXTI

Reserved

AFIO

Reserved

ADC

Reserved

SPI0x4000_4000

Reserved

UART

USART

System Architecture

AHB

APB

Up to

32 KB on-chip Flash

0x0000_0000

Up to
32 KB

Figure 4. Memory Map

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32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230

Table 3. Register Map

Start Address End Address Peripheral Bus

0x4000_0000 0x4000_0FFF USART

0x4000_1000 0x4000_1FFF UART

0x4000_2000 0x4000_3FFF Reserved

0x4000_4000 0x4000_4FFF SPI

0x4000_5000 0x4001_9FFF Reserved

0x4001_0000 0x4001_0FFF ADC

0x4001_1000 0x4002_1FFF Reserved

0x4002_2000 0x4002_2FFF AFIO

0x4002_3000 0x4002_3FFF Reserved

0x4002_4000 0x4002_4FFF EXTI

0x4002_5000 0x4003_3FFF Reserved

0x4003_4000 0x4003_4FFF SCTM0

0x4003_5000 0x4004_7FFF Reserved

0x4004_8000 0x4004_8FFF I2C

0x4004_9000 0x4006_7FFF Reserved

0x4006_8000 0x4006_8FFF WDT

0x4006_9000 0x4006_9FFF Reserved

0x4006_A000 0x4006_AFFF PWRCU

0x4006_B000 0x4006_DFFF Reserved

0x4006_E000 0x4006_EFFF GPTM

0x4006_F000 0x4007_3FFF Reserved

0x4007_4000 0x4007_4FFF SCTM1

0x4007_5000 0x4007_5FFF Reserved

0x4007_6000 0x4007_6FFF BFTM

0x4007_7000 0x4007_FFFF Reserved

0x4008_0000 0x4008_1FFF FMC

0x4008_2000 0x4008_7FFF Reserved

0x4008_8000 0x4008_9FFF CKCU/RSTCU

0x4008_A000 0x400A_FFFF Reserved

0x400B_0000 0x400B_1FFF GPIOA

0x400B_2000 0x400B_3FFF GPIOB

0x400B_4000 0x400F_FFFF Reserved

System Architecture

APB

AHB

Rev. 1.10 28 of 366 November 09, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230

Embedded Flash Memory

The HT32F52220/HT32F52230 series provides up to 32 KB on-chip Flash memory which is

located at address 0x0000_0000. It supports byte, half-word, and word access operations. Note that
the Flash memory only supports read operations for the bus access. Any write operations to the
Flash memory will cause a bus fault exception. The Flash memory has up to capacity of 32 pages.

Each page has a memory capacity of 1 KB and can be erased independently. A 32-bit programming
interface provides the capability of changing bits from 1 to 0. A data storage or rmware upgrade
can be implemented using several methods such as In System Programming (ISP), In Application
Programming (IAP) or In Circuit Programming (ICP). For more information, refer to the Flash

Memory Controller section.

Embedded SRAM Memory

The HT32F52220/HT32F52230 series contain up to 4 KB on-chip SRAM which is located at

address 0x2000_0000. It support byte, half-word and word access operations.

AHB Peripherals

The address of the AHB peripherals ranges from 0x4008_0000 to 0x400F_FFFF. Some peripherals
such as Clock Control Unit, Reset Control Unit and Flash Memory Controller are connected to the
AHB bus directly. The AHB peripherals clocks are always enabled after a system reset. Access to
registers for these peripherals can be achieved directly via the AHB bus. Note that all peripheral
registers in the AHB bus support only word access.

System Architecture

APB Peripherals

The address of APB peripherals ranges from 0x4000_0000 to 0x4007_FFFF. An APB to AHB
Bridge provides access capability between the CPU and the APB peripherals. Additionally, the
APB peripheral clocks are disabled after a system reset. Software must enable the peripheral clock
by setting the APBCCRn register in the Clock Control Unit before accessing the corresponding
peripheral register. Note that the APB to AHB Bridge will duplicate the half-word or byte data to
word width when a half-word or byte access is performed on the APB peripheral registers. In other
words, the access result of a half-word or byte access on the APB peripheral register will vary

depending on the data bit width of the access operation on the peripheral registers.

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HT32F52220/HT32F52230

4

Flash Memory Controller (FMC)

Introduction

The Flash Memory Controller, FMC, provides all the necessary ash operation functions and pre-

fetch buffer for the embedded on-chip Flash memory. Figure below shows the block diagram of the
FMC which includes programming interface, control register, pre-fetch buffer and access interface.

Since the Flash memory access speed is slower than the CPU, a wide access interface with the
pre-fetch buffer is provided to the Flash memory in order to reduce the CPU waiting time which
will cause the CPU instruction execution delays. The Flash memory word program and page erase

functions are also provided for instruction/data storage.

Peripheral Bus

AHB

System Bus

Flash Memory Controller

Control Register

Pre-fetch Buffer

Wait State

Control

Addressing

Data

Programming

Control

Flash Memory Controller (FMC)

Flash

Information

Block

Main Flash

Memory

Figure 5. Flash Memory Controller Block Diagram

Features

▄

Up to 32 KB of on-chip Flash memory for storing instruction/data and options

● 32 KB (instruction/data + Option Byte)

● 16 KB (instruction/data + Option Byte)

▄

Page size of 1K Byte, totally up to 32 pages depending on the main Flash size

▄

Wide access interface with pre-fetch buffer to reduce instruction execution delay

▄

Page erase and mass erase capability

▄

32-bit word programming

▄

Interrupt function to indicate the end of Flash memory operation or an error occurs

▄

Flash read protection to prevent illegal code/data access

▄

Page erase/program protection to prevent unexpected operation

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Functional Descriptions

Flash Memory Map

The following figure is the Flash memory map of the system. The address ranges from

0x0000_0000 to 0x1FFF_FFFF (0.5 GB). The address from 0x1F00_0000 to 0x1F00_07FF is
mapped to Boot Loader Block (2 KB). Additionally, the region addressed from 0x1FF0_0000 to
0x1FF0_03FF is the alias of Option Byte block (1 KB) which is located at the last page of the main

Flash physically. The memory mapping on system view is shown as below.

0x1FFF_FFFF

0x1FF0_0400

0x1FF0_0000

0x1F00_0800

Reserved

Option Byte

Reserved

Flash Memory Controller (FMC)

1 KB

0x1F00_0000

0x0000_8000

Figure 6. Flash Memory Map

0x0000_0000

Boot Loader Block

Reserved

Main Flash Block

User Application

2 KB

32 KB

or

16 KB

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HT32F52220/HT32F52230

Flash Memory Architecture

The Flash memory consists of up to 32 KB main Flash with 1 KB per page and 2 KB Information
Block for Boot Loader. The main Flash memory contains a total of 32 pages (or 16 pages for 16 KB

device) which can be erased individually. The following table shows the base address, size and
protection setting bit of each page.

Table 4. Flash Memory and Option Byte

Block Name Address Page Protection Bit Size

Page 0 0x0000_0000 ~ 0x0000_03FF OB_PP [0] 1 KB

Page 1 0x0000_0400 ~ 0x0000_07FF OB_PP [1] 1 KB

Page 2 0x0000_0800 ~ 0x0000_0BFF OB_PP [2] 1 KB

Page 3 0x0000_0C00 ~ 0x0000_0FFF OB_PP [3] 1 KB

..........

Main Flash
Block

Page 28 0x0000_7000 ~ 0x0000_73FF OB_PP [28] 1 KB

Page 29 0x0000_7400 ~ 0x0000_77FF OB_PP [29] 1 KB

Page 30 0x0000_7800 ~ 0x0000_7BFF OB_PP [30] 1 KB

Page 31
(Option Byte)

Information Block Boot Loader 0x1F00_0000 ~ 0x1F00_07FF NA 2 KB

Notes:

1. The Information Block stores boot loader – this block can not be programmed or erased by user.

2. The Option Byte is always located at last page of main Flash block.

Physical:0x0000_7C00 ~ 0x0000_7FFF
Alias: 0x1FF0_0000 ~ 0x1FF0_03FF

..........

..........

OB_CP [1] 1 KB

..........

Flash Memory Controller (FMC)

Wait State Setting

When the CPU clock, HCLK, is greater than the access speed of the Flash memory, the wait state
cycles must be inserted during the CPU fetch instructions or load data from Flash memory. The
wait state can be changed by setting the WAIT [2:0] of the Flash Cache and Pre-fetch Control
Register, CFCR. In order to match the wait state requirement, the following two rules should be

considered.

▄

HCLK clock is switched from low speed to high speed frequency:
Change the wait state setting rst and then switch the HCLK clock.

▄

HCLK clock is switched from high speed to low speed frequency:
Switch the HCLK clock rst and then change the wait state setting.

The following table shows the relationship between the wait state cycle and HCLK. The default

wait state is 0 since the High Speed Internal oscillator, HSI, which operates at a frequency of 8MHz

is selected as the HCLK clock source after system reset.

Table 5. Relationship between Wait State Cycle and HCLK

Wait State Cycle HCLK

0 0 MHz < HCLK ≤ 20 MHz

1 20 MHz < HCLK ≤ 40 MHz

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Booting Conguration

The system provides two kinds of boot modes which can be selected using the BOOT pin. The
BOOT pin is sampled during a power-on reset or system reset. Once the logic value is decided, the
rst 4 words of vector will be remapped to the corresponding source according to the boot modes.

The boot mode is shown in the following table.

Table 6. Boot Modes

Boot modes selection pin

BOOT

0 Boot Loader The Vector source is Boot Loader

1 Main Flash The Vector source is main Flash

The Vector Mapping Control Register, VMCR, is provided to change the vector remapping setting
temporarily after the chip reset. The reset initial value of the VMCR register is determined by the
BOOT pin status which will be sampled during the reset duration.

Mode Descriptions

Flash Memory Controller (FMC)

Boot Setting

0xC

Hard Fault Handler

0x8

0x4

NMI Handler

Program Counter

Initial Stack Point0x0

Figure 7. Vector Remapping

+ 0xC

+ 0x8

+ 0x4

0x0000 0000

1 : Main Flash 0 : Boot Loader

+ 0xC

+ 0x8

+ 0x4

0x1F00 0000

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Page Erase

The FMC provides a page erase function which is used to initialize the contents of the specific
Flash memory page. Each page can be erased independently without affecting the contents of other
pages. The following steps show the access sequence of the register for a page erase operation.

▄

Check the OPCR register to conrm that no Flash memory operation is in progress (OPM [3:0]
equal to 0xE or 0x6). Otherwise, wait until the previous operation has been nished.

▄

Write the page address to the TADR register.

▄

Write the page erase command to the OCMR register (CMD [3:0] = 0x8).

▄

Commit the page erase command to the FMC by setting the OPCR register (set OPM [3:0]=0xA).

▄

Wait until all the operations have been completed by checking the OPCR register value (OPM

[3:0] equals to 0xE).

▄

Read and verify the page if required.

Note that a correct target page address must be conrmed. The software may run out of control

if the target erase page is being used to fetch code or access data. The FMC will not provide any
notification when this happens. Additionally, the page erase operation will be ignored on the

protected pages. A Flash Operation Error interrupt will be triggered by the FMC if the OREIEN bit
in the OIER register is set. The software can check the PPEF bit in the OISR register to detect this
condition in the interrupt handler. The following gure shows the page erase operation ow.

Flash Memory Controller (FMC)

No

No

Start

Is OPM equal to 0xE or 0x6 ?

Yes

Set TADR, OCMR

Commit command

by setting OPCR

Is OPM equal to 0xE ?

Yes

Finish

Figure 8. Page Erase Operation Flowchart

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Mass Erase

The FMC provides a mass erase function which is used to initialize all the main Flash memory
contents to a high state. The following steps show the mass erase operation register access
sequence.

▄

Check the OPCR register to conrm that no Flash memory operation is in progress (OPM [3:0]
equal to 0xE or 0x6). Otherwise, wait until the previous operation has been nished.

▄

Write the mass erase command to the OCMR register (CMD [3:0] = 0xA).

▄

Commit the mass erase command to the FMC by setting the OPCR register (set OPM [3:0]=0xA).

▄

Wait until all operations have been nished by checking the value of the OPCR register (OPM

[3:0] equals to 0xE).

▄

Read and verify the Flash memory if required.

Since all Flash data will be reset as 0xFFFF_FFFF, the mass erase operation can be implemented

by the program that runs in the SRAM or by the debugging tool that access the FMC register

directly. The software function that is executed on the Flash memory should not trigger a mass

erase operation. The following gure shows the mass erase operation ow.

Flash Memory Controller (FMC)

No

No

Start

Is OPM equal to 0xE or 0x6 ?

Yes

Set OCMR = 0xA

Commit command

by setting OPCR

Is OPM equal to 0xE ?

Yes

Finish

Figure 9. Mass Erase Operation Flowchart

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Word Programming

The FMC provides a 32-bit word programming function which is used to modify the specic Flash

memory word contents. The following steps show the word programming operation register access
sequence.

▄

Check the OPCR register to conrm that no Flash memory operation is in progress (OPM [3:0]
equal to 0xE, or 0x6). Otherwise, wait until the previous operation has been nished.

▄

Write the word address to the TADR register. Write the word data to the WRDR register.

▄

Write the word program command to the OCMR register (CMD [3:0] = 0x4).

▄

Commit the word program command to the FMC by setting the OPCR register (set OPM [3:0]=0xA).

▄

Wait until all operations have been nished by checking the value of the OPCR register (OPM

[3:0] equals to 0xE).

▄

Read and verify the Flash memory if required.

Note that the word programming operation can not be applied to the same address twice.
Successive word programming operations to the same address must be separated by a page erase
operation. Additionally, the word programming operation will be ignored on protected pages.

A Flash operation error interrupt will be triggered by the FMC if the OREIEN bit in the OIER
register is set. The software can check the PPEF bit in the OISR register to detect this condition in
the interrupt handler. The following gure shows the word programming operation ow.

Flash Memory Controller (FMC)

No

No

Start

Is OPM equal to 0xE or 0x6 ?

Yes

Set TADR, WRDR

and OCMR

Commit command

by setting OPCR

Is OPM equal to 0xE ?

Yes

Finish

Figure 10. Word Programming Operation Flowchart

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HT32F52220/HT32F52230

Option Byte Description

The Option Byte region can be treated as an independent Flash memory in which the base address
is 0x1FF0_0000. The following table shows the functional description and the Option Byte

memory map.

Table 7. Option Byte Memory Map

Option Byte Offset Description Reset Value

Option Byte Base Address = 0x1FF0_0000

0x000

OB_PP

OB_CP 0x010

OB_CK 0x020

0x004
0x008
0x00C

OB_PP [n]: Flash Page Erase/Program Protection
(n = 0 ~ 127)

OB_PP [n] (n = 0 ~ 30)

0: Flash Page n Erase / Program Protection is enabled
1: Flash Page n Erase / Program Protection is disabled

OB_PP [n] (n = 31 ~ 127)

Reserved

OB_CP [0]: Flash Security Protection

0: Flash Security protection is enabled
1: Flash Security protection is disabled

OB_CP [1]: Option Byte Protection

0: Option Byte protection is enabled
1: Option Byte protection is disabled

OB_CP [31:2]: Reserved

OB_CK [31:0]: Flash Option Byte Checksum
OB_CK should be set as the sum of the 5 words Option
Byte contents, of which the offset address is from 0x000
to 0x010 (0x000 + 0x004 + 0x008 + 0x00C + 0x010),
when the OB_PP or OB_CP register content is not equal
to 0xFFFF_FFFF. Otherwise, both page erase/program
protection and security protection will be enabled.

Flash Memory Controller (FMC)

0xFFFF_FFFF
0xFFFF_FFFF
0xFFFF_FFFF
0xFFFF_FFFF

0xFFFF_FFFF

0xFFFF_FFFF

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Page Erase/Program Protection

The FMC provides the page erase/program protection function to prevent unexpected operation of

the Flash memory. The page erase (CMD [3:0] = 0x8 in the OCMR register) or word program (CMD
[3:0] = 0x4) command will not be accepted by the FMC on the protected pages. When the page
erase or word programming command is sent to the FMC on a protected page, the PPEF bit in the
OISR register will then be set by the FMC and the Flash operation error interrupt will be triggered
to the CPU by the FMC if the OREIEN bit in the OIER register is set. The page protection function
can be enabled for each page independently by setting the OB_PP registers in the Option Byte. The

following table shows the access permission of the main Flash page when the page protection is
enabled.

Table 8. Access Permission of Protected Main Flash Page

Operation

Read O O

Program X X

Page Erase X X

Mass Erase O O

Mode

Flash Memory Controller (FMC)

ISP/IAP ICP/Debug mode

Notes:

1. The write protection is based on specific pages. The above access permission only
affects the pages of which the protection function has been enabled. Other pages are not
affected.

2. The Main Flash page protection is congured by the OB_PP [126:0] eld. The Option Byte

is physically located at the last page of the main Flash. The Option Byte page protection is

congured by the OB_CP [1] bit.

3. The page erase on the Option Byte area can be used to disable the page protection of the
main Flash.

4. The page protection of the Option Byte can only be disabled by a mass erase operation.

The following steps show the page erase/program protection register access sequence.

▄

Check the OPCR register to conrm that no Flash memory operation is in progress (OPM [3:0]
equal to 0xE or 0x6). Otherwise, wait until the previous operation has been nished.

▄

Write the OB_PP address to the TADR register (TADR = 0x1FF0_0000).

▄

Write the WRDR register, which indicates the protection function of corresponding page is
enabled or disabled (0: Enabled, 1: Disabled).

▄

Write the word program command to the OCMR register (CMD [3:0] = 0x4).

▄

Commit the word program command to the FMC by setting the OPCR register (set OPM [3:0] =

0xA).

▄

Wait until all operations have been nished by checking the value of the OPCR register (OPM

[3:0] equals to 0xE).

▄

Read and verify the Option Byte if required.

▄

The OB_CK eld in the Option Byte must be updated according to the Option Byte checksum

rule.

▄

Apply a system reset to activate the new OB_PP setting.

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Security Protection

The FMC provides a Security protection function to prevent an illegal code/data access of the

Flash memory. This function is useful for protecting the software / rmware from the illegal users.
The function is activated by conguring the Option Byte OB_CP [0] bit. Once the function has
been enabled, all the main Flash data access through ICP/Debug mode, programming and page

erase operation will not be allowed except via the user’s application. However, the mass erase
operation will still be accepted by the FMC in order to disable this security protection function.
The following table shows the access permission of the Flash memory when the security protection
is enabled.

Table 9. Access Permission When Security Protection is Enabled

Operation

Read O X (read as 0)

Program O

Page Erase O

Mass Erase O O

Mode

User application

(Note 1)

(Note 1)

(Note 1)

Flash Memory Controller (FMC)

ICP/Debug mode

X

X

Notes:

1. User application means the software that is executed or booted from the main Flash
memory with the JTAG/SW debugger being disconnected. However, the Option Byte
block and page 0 are still in protection and the Program/Page Erase operation cannot be
executed.

2. The Mass erase operation can erase the Option Byte block and disable the security
protection.

The following steps show the security protection register access sequence:

▄

Check the OPCR register to conrm that no Flash memory operation is in progress (OPM [3:0]
equal to 0xE or 0x6). Otherwise, wait until the pervious operation has been nished.

▄

Write the OB_CP address to the TADR register (TADR = 0x1FF0_0010).

▄

Write the data into the WRDR register to set the OB_CP [0] eld to 0.

▄

Write the word program command to the OCMR register (CMD [3:0] = 0x4).

▄

Commit the word program command to the FMC by setting the OPCR register (set OPM = 0xA).

▄

Wait until all operations have been nished by checking the value of the OPCR register (OPM

[3:0] equals to 0xE).

▄

Read and verify the Option Byte if required.

▄

The OB_CK eld in the Option Byte must be updated according to the Option Byte checksum

rule.

▄

Apply a system reset to active the new OB_CP setting.

Rev. 1.10 39 of 366 November 09, 2018

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HT32F52220/HT32F52230

Register Map

The following table shows the FMC registers and reset values.

Table 10. FMC Register Map

Register Offset Description Reset Value

FMC Base Address = 0x4008_0000

TADR 0x000 Flash Target Address Register 0x0000_0000

WRDR 0x004 Flash Write Data Register 0x0000_0000

OCMR 0x00C Flash Operation Command Register 0x0000_0000

OPCR 0x010 Flash Operation Control Register 0x0000_000C

OIER 0x014 Flash Operation Interrupt Enable Register 0x0000_0000

OISR 0x018 Flash Operation Interrupt and Status Register 0x0001_0000

0x020

PPSR

CPSR 0x030 Flash Security Protection Status Register 0xXXXX_XXXX

VMCR 0x100 Flash Vector Mapping Control Register 0x0000_000X

MDID 0x180 Flash Manufacturer and Device ID Register 0x0376_XXXX

PNSR 0x184 Flash Page Number Status Register 0x0000_00X0

PSSR 0x188 Flash Page Size Status Register 0x0000_0400

CFCR 0x200 Flash Pre-fetch Control Register 0x0000_0011

CIDR0 0x310 Custom ID Register 0 0xXXXX_XXXX

CIDR1 0x314 Custom ID Register 1 0xXXXX_XXXX

CIDR2 0x318 Custom ID Register 2 0xXXXX_XXXX

CIDR3 0x31C Custom ID Register 3 0xXXXX_XXXX

0x024
0x028
0x02C

Flash Page Erase/Program Protection Status Register

Flash Memory Controller (FMC)

0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX

Note:

“X” means various reset values which depend on the Device, Flash value, Option Byte value,

or power on reset setting.

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HT32F52220/HT32F52230

Register Descriptions

Flash Target Address Register – TADR

This register species the target address of the page erase and word programming operations.

Offset: 0x000

Reset value: 0x0000_0000

31 30 29 28 27 26 25 24

TADB

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

23 22 21 20 19 18 17 16

TADB

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

15 14 13 12 11 10 9 8

TADB

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

7 6 5 4 3 2 1 0

TADB

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

Bits Field Descriptions

[31:0] TADB Flash Target Address Bits

For programming operations, the TADR register specifies the address where the
data is written. Since the programming length is 32-bit, the TADR should be set as
word-aligned (4 bytes). The TADB [1:0] bits will be ignored during programming
operations. For page erase operations, the TADR register contains the page address
which is going to be erased. Since the page size is 1 KB, the TADB [9:0] bits will
be ignored in order to limit the target address as 1 Kbyte-aligned. For 32 KB main
Flash addressing, the TADB [31:16] bits should be zero while the TADB [31:15] bits
should be zero for 16 KB main Flash addressing. The region of which the address

ranges from 0x1FF0_0000 to 0x1FF0_03FF is the 1KB Option Byte. This eld for the

available Flash address must be under 0x1FFF_FFFF. Otherwise, the Invalid Target
Address interrupt will occur if the corresponding interrupt enable bit is set.

Flash Memory Controller (FMC)

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Flash Write Data Register – WRDR

This register species the data to be written for programming operation.

Offset: 0x004

Reset value: 0x0000_0000

31 30 29 28 27 26 25 24

WRDB

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

23 22 21 20 19 18 17 16

WRDB

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

15 14 13 12 11 10 9 8

WRDB

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

7 6 5 4 3 2 1 0

WRDB

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

Flash Memory Controller (FMC)

Bits Field Descriptions

[31:0] WRDB Flash Write Data Bits

The data value for programming operation.

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Flash Operation Command Register – OCMR

This register is used to specify the Flash operation commands that include word program, page erase and mass
erase.

Offset: 0x00C

Reset value: 0x0000_0000

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved CMD

Type/Reset RW 0 RW 0 RW 0 RW 0

Bits Field Descriptions

[3:0] CMD Flash Operation Command

The following table shows the denitions of the operation command bits, CMD [3:0],

which specify the Flash memory operation. If an invalid command is set and the
IOCMIEN bit is set to 1, an Invalid Operation Command interrupt will occur.

CMD [3:0] Description

0x0 Idle (default)

0x4 Word program

0x8 Page erase

0xA Mass erase

Others Reserved

Flash Memory Controller (FMC)

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Flash Operation Control Register – OPCR

This register is used for controlling the command commitment and checking the status of the FMC operations.

Offset: 0x010

Reset value: 0x0000_000C

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved OPM Reserved

Type/Reset RW 0 RW 1 RW 1 RW 0

Flash Memory Controller (FMC)

Bits Field Descriptions

[4:1] OPM Operation Mode

The following table shows the operation modes of the FMC. User can commit the
command which is set by the OCMR register to the FMC according to the address
alias setting in the TADR register. The contents of the TADR, WRDR, and OCMR
registers should be prepared before setting this register. After all the operations
have been finished, the OPM field will be set as 0xE by the FMC hardware.

The Idle mode can be set when all the operations have been nished for power

saving purpose. Note that the operation status should be checked before the next
operation is executed to the FMC. The contents of the TADR, WRDR, OCMR,
and OPCR registers should not be changed until the previous operation has been

nished.

OPM [3:0] Description

0x6 Idle (default)

0xA Commit command to main Flash

0xE All operation nished on main Flash

Others Reserved

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Flash Operation Interrupt Enable Register – OIER

This register is used to enable or disable the FMC interrupt function. The FMC generates interrupts to the
controller when corresponding interrupt enable bits are set.

Offset: 0x014

Reset value: 0x0000_0000

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved OREIEN IOCMIEN OBEIEN ITADIEN ORFIEN

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0

Bits Field Descriptions

[4] OREIEN Operation Error Interrupt Enable

0: Operation error interrupt is disabled
1: Operation error interrupt is enabled

[3] IOCMIEN Invalid Operation Command Interrupt Enable

0: Invalid Operation Command interrupt is disabled
1: Invalid Operation Command interrupt is enabled

[2] OBEIEN Option Byte Check Sum Error Interrupt Enable

0: Option Byte Check Sum Error interrupt is disabled
1: Option Byte Check Sum Error interrupt is enabled

[1] ITADIEN Invalid Target Address Interrupt Enable

0: Invalid Target Address interrupt is disabled
1: Invalid Target Address interrupt is enabled

[0] ORFIEN Operation Finished Interrupt Enable

0: Operation Finish interrupt is disabled
1: Operation Finish interrupt is enabled

Flash Memory Controller (FMC)

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Flash Operation Interrupt and Status Register – OISR

This register indicates the FMC interrupt status which is used to check if a Flash operation has been nished or

an error occurs. The status bits, bit [4:0], are available when the corresponding bits in the OIER register are set.

Offset: 0x018

Reset value: 0x0001_0000

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved PPEF RORFF

Type/Reset RO 0 RO 1

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved OREF IOCMF OBEF ITADF ORFF

Type/Reset WC 0 WC 0 WC 0 WC 0 WC 0

Bits Field Descriptions

[17] PPEF Page Erase/Program Protected Error Flag

0: Page Erase/Program Protected Error does not occur
1: Operation error occurs due to an invalid erase/program operation applied to a

protected page

This bit is reset by hardware once a new ash operation command is committed.

[16] RORFF Raw Operation Finished Flag

0: The last ash operation command is not nished
1: The last ash operation command is nished

The RORFF bit is directly connected to the Flash memory for debugging purpose.

[4] OREF Operation Error Flag

0: No Flash operation error occurred

1: The last ash operation is failed

This bit will be set when any Flash operation error occurs such as an invalid
command, program error and erase error, etc. The ORE interrupt occurs if the
OREIEN bit in the OIER register is set. Reset this bit by writing 1.

[3] IOCMF Invalid Operation Command Flag

0: No invalid ash operation command was set
1: An invalid ash operation command has been written into the OCMR register

The IOCM interrupt will occur if the IOCMIEN bit in the OIER register is set. Reset
this bit by writing 1.

[2] OBEF Option Byte Checksum Error Flag

0: Option Byte checksum is correct
1: Option Byte checksum is incorrect

The OBE interrupt will occur if the OBEIEN bit in the OIER register is set. This bit
is cleared to 0 by software writing 1 into it. However, the Option Byte Checksum
Error Flag can not be cleared by software until the interrupt condition is cleared,

which means that the Option Byte check sum value has to be correctly modied

or the corresponding interrupt control is disabled. Otherwise, the interrupt will be
continually generated.

Flash Memory Controller (FMC)

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Bits Field Descriptions

[1] ITADF Invalid Target Address Flag

0: The target address is valid
1: The target address is invalid

The data in the TADR eld must be in the range from 0x0000_0000 to 0x1FFF_

FFFF. Otherwise, an ITAD interrupt will occur if the ITADIEN bit in the OIER register
is set. Reset this bit by writing 1.

[0] ORFF Operation Finished Flag

0: No ash operation is nished
1: Last Flash operation is nished

The ORF interrupt will occur if the ORFIEN bit in the OIER register is set. Reset this
bit by writing 1.

Flash Memory Controller (FMC)

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Flash Page Erase/Program Protection Status Register – PPSR

This register indicates the page protection status of the Flash page erase/program protection functions.

Offset: 0x020 (0) ~ 0x02C (3)

Reset value: 0xXXXX_XXXX

31 30 29 28 27 26 25 24

PPSBn

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

23 22 21 20 19 18 17 16

PPSBn

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

15 14 13 12 11 10 9 8

PPSBn

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

7 6 5 4 3 2 1 0

PPSBn

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

Flash Memory Controller (FMC)

Bits Field Descriptions

[127:0] PPSBn Page Erase/Program Protection Status Bits (n = 0 ~ 127)

PPSB[n] = OB_PP[n]

0: The corresponding page n is protected
1: The corresponding page n is not protected

The content of this register is not dynamically updated and will only be reloaded
from the Option Byte when any kind of reset occurs. The erase or program function
of the specific page is not allowed when the corresponding bits of the PPSR
registers are reset. The reset value of PPSR [127:0] is determined by the Option
Byte OB_PP [127:0] bits. Each page erase/program protection status bit protects
one page. The other remained bits of the OB_PP field and PPSR registers are
reserved.

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Flash Security Protection Status Register – CPSR

This register indicates the Flash Memory Security protection status. The content of this register is not dynamically
updated and will only be reloaded by the Option Byte loader which is active when any kind of reset occurs.

Offset: 0x030

Reset value: 0xXXXX_XXXX

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved OBPSB CPSB

Type/Reset RO X RO X

Bits Field Descriptions

[1] OBPSB Option Byte Page Erase/Program Protection Status Bit

0: The Option Byte page is protected
1: The Option Byte page is not protected

The reset value of the OPBSB bit is determined by the Option Byte OB_CP [1] bit.

[0] CPSB Flash Memory Security Protection Status Bit

0: Flash Memory Security protection is enabled
1: Flash Memory Security protection is not enabled

The reset value of the CPSB bit is determined by the Option Byte OB_CP [0] bit.

Flash Memory Controller (FMC)

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Flash Vector Mapping Control Register – VMCR

This register is used to control the vector mapping. The reset value of the VMCR register is determined by the
external BOOT pin during the power-on reset period.

Offset: 0x100

Reset value: 0x0000_000X

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved VMCB Reserved

Type/Reset RW X

Bits Field Descriptions

[1] VMCB Vector Mapping Control Bit

The VMCB bit is used to control the mapping source of the first 4-word vectors
addressed from 0x0 to 0xC. The following table shows the vector mapping setting.

BOOT VMCB [1] Descriptions

Low 0

High 1

The reset value of the VMCB bit is determined by the BOOT pin status during the
power-on reset and system reset. The vector mapping setting can be changed

temporarily by conguring the VMCB bit when the application program is executed.

Boot Loader mode
The vector mapping source is the boot loader area.

Main Flash mode
The vector mapping source is the main Flash area.

Flash Memory Controller (FMC)

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Flash Manufacturer and Device ID Register – MDID

This register is used to store the manufacture ID and device part number information which can be used as the
product identity.

Offset: 0x180

Reset value: 0x0376_xxxx

31 30 29 28 27 26 25 24

MFID

Type/Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1

23 22 21 20 19 18 17 16

MFID

Type/Reset RO 0 RO 1 RO 1 RO 1 RO 0 RO 1 RO 1 RO 0

15 14 13 12 11 10 9 8

ChipID

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

7 6 5 4 3 2 1 0

ChipID

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

Bits Field Descriptions

[31:16] MFID Manufacturer ID

Read as 0x0376

[15:0] ChipID Chip ID

Read the last 4 digital codes of the MCU device part number.

Flash Memory Controller (FMC)

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Flash Page Number Status Register – PNSR

This register is used to indicate the Flash memory page number.

Offset: 0x184

Reset value: 0x0000_00XX

31 30 29 28 27 26 25 24

PNSB

Type/Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0

23 22 21 20 19 18 17 16

PNSB

Type/Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0

15 14 13 12 11 10 9 8

PNSB

Type/Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0

7 6 5 4 3 2 1 0

PNSB

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

Flash Memory Controller (FMC)

Bits Field Descriptions

[31:0] PNSB Flash Page Number Status Bits

0x0000_0010: Totally 16 pages for the on-chip Flash memory device
0x0000_0020: Totally 32 pages for the on-chip Flash memory device
0x0000_0040: Totally 64 pages for the on-chip Flash memory device
0x0000_0080: Totally 128 pages for the on-chip Flash memory device
0x0000_00FF: Totally 255 pages for the on-chip Flash memory device

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Flash Page Size Status Register – PSSR

This register is used to indicate the page size in bytes.

Offset: 0x188

Reset value: 0x0000_0400

31 30 29 28 27 26 25 24

PSSB

Type/Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0

23 22 21 20 19 18 17 16

PSSB

Type/Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0

15 14 13 12 11 10 9 8

PSSB

Type/Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 0

7 6 5 4 3 2 1 0

PSSB

Type/Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0

Flash Memory Controller (FMC)

Bits Field Descriptions

[31:0] PSSB Flash Page Size Status Bits

0x200: The page size is 512 Bytes per page
0x400: The page size is 1 KB per page
0x800: The page size is 2 KB per page

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Device ID Register – DID

This register is used to store the device part number information which can be used as the product identity.

Offset: 0x18C

Reset value: 0x000X_XXXX

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved ChipID

Type/Reset RO X RO X RO X RO X

15 14 13 12 11 10 9 8

ChipID

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

7 6 5 4 3 2 1 0

ChipID

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

Flash Memory Controller (FMC)

Bits Field Descriptions

[19:0] ChipID Chip ID

Read the complete 5 digital codes of the MCU device part number.

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Flash Pre-fetch Control Register – CFCR

This register is used to control the FMC pre-fetch module.

Offset: 0x200

Reset value: 0x0000_0011

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved PFBE Reserved WAIT

Type/Reset RW 1 RW 0 RW 0 RW 1

Flash Memory Controller (FMC)

Bits Field Descriptions

[4] PFBE Pre-fetch Buffer Enable Bit

0: Pre-fetch buffer is disabled
1: Pre-fetch buffer is enabled (default)

The pre-fetch buffer is enabled in default. When the pre-fetch buffer is disabled,
the instruction and data are directly provided by the Flash memory.

[2:0] WAIT Flash Wait State Setting

The WAIT[2:0] eld is used to set the HCLK wait clock during a non-sequential

address Flash access. The actual wait clock is given by (WAIT[2:0] - 1). Since
a wide access interface with a pre-fetch buffer is provided, the wait state of
sequential Flash access is very close to zero.

WAIT [2:0] Wait Status Allowed HCLK Range

001 0 0 MHz < HCLK ≤ 20 MHz

010 1 20 MHz < HCLK ≤ 40 MHz

Others Reserved Reserved

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Custom ID Register n – CIDRn ( n = 0 ~3)

This register is used to store the custom ID information which can be used as the custom identity.

Offset: 0x310 (0) ~ 0x31C (3)

Reset value: Various depending on Flash Manufacture Privilege Information Block.

31 30 29 28 27 26 25 24

CID

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

23 22 21 20 19 18 17 16

CID

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

15 14 13 12 11 10 9 8

CID

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

7 6 5 4 3 2 1 0

CID

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

Flash Memory Controller (FMC)

Bits Field Descriptions

[31:0] CIDn Custom ID

Read as the CIDn[31:0] (n=0 ~ 3) field in the Custom ID registers in Flash
Manufacture Privilege Block.

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PWR_CTRL

LSI

LDOOFF

DMOSON

SLEEPDEEP

nRST

V

DD15

V

DD

V

DD15

1.5 V Domain

V

DD

Domain

LVD: Low Voltage Detector
POR/PDR: Power On Reset/Power Down Reset

LDO: Voltage Regulator
DMOS: Depletion MOS

SLEEPING

LCM

WKUP1

WAKEUP

WKUP2

WKUP4

LVD

HSI

HSE

DMOS

LDO

CPU

Memories

Digital

Peripheral

APB

INTF

3.3 V

POR/PDR

1.5 V

POR/PDR

PLL

V

LDOOUT

HT32F52220/HT32F52230

5

Power Control Unit (PWRCU)

Introduction

The power consumption can be regarded as one of the most important issues for many embedded

system applications. Accordingly the Power Control Unit, PWRCU, provides many types of power
saving modes such as Sleep, Deep-Sleep1, Deep-Sleep2, and Power-Down modes. These modes

reduce the power consumption and allow the application to achieve the best trade-off between the

conicting demands of CPU operating time, speed and power consumption. The dash line in the
Figure 11 indicates the power supply source of two digital power domains.

Power Control Unit (PWRCU)

Figure 11. PWRCU Block Diagram

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Features

▄

Two power domains: VDD 3.3 V and V

▄

Four power saving modes: Sleep, Deep-Sleep1, Deep-Sleep2 and Power-Down modes.

▄

Internal Voltage regulator supplies 1.5 V voltage source.

▄

Additional Depletion MOS supplies 1.5 V voltage source with low leakage and low operating

current.

▄

A power reset is generated when one of the following events occurs:

● Power-on / Power-down reset (POR / PDR reset).

● When exiting Power-Down mode.

● The control bits BODEN = 1, BODRIS=0 and the supply power VDD ≤ V

▄

BOD Brown Out Detector can issue a system reset or an interrupt when VDD power source is
lower than the Brown Out Detector voltage V

▄

LVD Low Voltage Detector can issue an interrupt or wakeup event when VDD is lower than a

programmable threshold voltage V

1.5 V power domains.

DD15

BOD

.

LVD

Power Control Unit (PWRCU)

.

BOD

.

Functional Descriptions

VDD Power Domain

LDO Power Control

The LDO will be automatically switched off when one of the following conditions occurs:

▄

The Power-Down or Deep-Sleep 2 mode is entered.

▄

The control bits BODEN = 1, BODRIS = 0 and the supply power VDD ≤ V

▄

The supply power VDD ≤ V

The LDO will be automatically switched on by hardware when the supply power VDD > V

of the following conditions occurs:

▄

Resume operation from the power saving mode – LVD wakeup and WAKEUP pin rising edge.

▄

Detect a falling edge on the external reset pin (nRST).

▄

The control bit BODEN = 1 and the supply power VDD > V

To enter the Deep-Sleep1 mode, the PWRCU will request the LDO to operate in a low current
mode, LCM. To enter the Deep-Sleep 2 mode, the PWRCU will turn off the LDO and turn on the
DMOS to supply an alternative 1.5 V power.

Voltage Regulator

The voltage regulator, LDO, Depletion MOS, DMOS, Low voltage Detector, LVD, High Speed
Internal oscillator, HSI, and Low Speed Internal RC oscillator, LSI, are operated under the VDD
power domain. The LDO can be configured to operate in either normal mode (LDOOFF = 0,
LDOLCM = 0, I
= Low current mode) to supply the 1.5 V power. An alternative 1.5 V power source is the output

of the DMOS which has low static and driving current characteristics. It is controlled using the

DMOSON bit in the PWRCR register. The DMOS output has weak output current and regulation

capability and only operate in the Deep-Sleep 2 mode for data retention purposes in the V
power domain.

= High current mode) or low current mode (LDOOFF = 0, LDOLCM =1, I

OUT

PDR

BOD

.

BOD

if any

POR

.

OUT

DD15

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Power On Reset (POR) / Power Down Reset (PDR)

The device has an integrated POR/PDR circuitry that allows proper operation starting from/down
to 2.0 V. The device remains in Power-Down mode when VDD is below a specied threshold V

without the need for an external reset circuit. For more details the power on / power down reset
threshold voltage, refer to the electrical characteristics of the corresponding datasheet.

V

,

PDR

DD

V

POR

Hysteresis

V

PDR

Power Control Unit (PWRCU)

POR Delay Time

t

RESET

RSTD

Figure 12. Power On Reset / Power Down Reset Waveform

Low Voltage Detector / Brown Out Detector

The Low Voltage Detector, LVD, can detect whether the supply voltage VDD is lower than a

programmable threshold voltage V

. It is selected by the LVDS bits in the LVDCSR register.

LV D

When a low voltage on the VDD power pin is detected, the LVDF ag will be active and an interrupt

will be generated and sent to the MCU core if the LVDEN and LVDIWEN bits in the LVDCSR
register are set. For more details concerning the LVD programmable threshold voltage V

to the electrical characteristics of the corresponding datasheet.

The Brown Out Detector, BOD, is used to detect if the VDD supply voltage is equal to or lower

than V
is lower than V

. When the BODEN bit in the LVDCSR register is set to 1 and the VDD supply voltage

BOD

then the BODF ag is active. The PWRCU will regard this as a power down

BOD

reset situation and then immediately disable the internal LDO regulator when the BODRIS bit is
cleared to 0 or issue an interrupt to notify the CPU to execute a power down procedure when the
BODRIS bit is set to 1. For more details concerning the Brown Out Detector voltage V

the electrical characteristics of the corresponding datasheet.

Time

LV D

, refer to

BOD

, refer

High Speed Internal Oscillator

The High Speed Internal Oscillator, HSI, is located in the VDD power domain. When exiting from

the Deep-Sleep mode, the HSI clock will be congured as the system clock for a certain period
by setting the PSRCEN bit to 1 This bit is located in the Global Clock Control Register, GCCR, in
the Clock Control Unit, CKCU. The system clock will not be switched back to the original clock

source used before entering the Deep-Sleep mode until the original clock source, which may be

either sourced from the PLL or HSE stabilizes. Also the system will force the HSI oscillator to be
the system clock after a wake up from Power-Down mode since a 1.5 V power on reset will occur.

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High Speed External Oscillator

The High Speed External Oscillator, HSE, is located in the VDD power domain. The HSE crystal

oscillator can be switched on or off using the HSEEN bit in the Global Clock Control Register,
GCCR. The HSE clock can then be used directly as the system clock source or be used as the PLL

input clock.

Isolation Cells

When the device resumes operation from the 1.5 V power, either by Hardware or Software, access
to the PWRCU registers in the VDD power domain are disabled by the isolation cells which protect

these registers against possible parasitic write accesses. To resume access operations, users must

disable these isolation cells by setting the VDDISO bit to 1 in the LPCR register of the Clock

Control Unit.

1.5 V Power Domain

The main functions that include the APB interface for the VDD domain, CPU core logic, AHB/APB
peripherals and memories and so on are located in this power domain. Once the 1.5 V is powered
up, the POR will generate a reset sequence on 1.5 V power domain. Subsequently, to enter the
expected power saving mode, the associated control bits including the LDOOFF, DMOSON and
LDOLCM bits must be congured. Then, once a WFI or WFE instruction is executed, the device

will enter an expected power saving mode which will be discussed in the following section.

Power Control Unit (PWRCU)

Operation Modes

Run Mode

In the Run mode, the system operates with full functions and all power domains are active. There
are two ways to reduce the power consumption in this mode. The rst is to slow down the system
clock by setting the AHBPRE eld in the CKCU AHBCFGR register, and the second is to turn
off the unused peripherals clock by setting the APBCCR0 and APBCCR1 registers or slow down
peripherals clock by setting the APBPCSR0 and APBPCSR1 registers to meet the application
requirement. Reducing the system clock speed before entering the sleep mode will also help to

minimize power consumption.

Additionally, there are several power saving modes to provide maximum optimization between
device performance and power consumption.

Table 11. Operation Mode Denitions

Mode name Hardware Action

Run After system reset, CPU fetches instructions to execute.

Sleep

Deep-Sleep1~2

Power-Down Shut down the 1.5 V power domain

1. CPU clock will be stopped.

2. Peripherals, Flash and SRAM clocks can be stopped by setting.

1. Stop all clocks in the 1.5 V power domain.

2. Disable HSI, HSE, and PLL.

3. Turning on the LDO low current mode or DMOS to reduce the 1.5 V power
domain current.

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Sleep Mode

By default, only the CPU clock will be stopped in the Sleep mode. Clearing the FMCEN or
SRAMEN bit in the CKCU AHBCCR register to 0 will have the effect of stopping the Flash
clock or SRAM clock after the system enters the Sleep mode. If it is not necessary for the CPU to
access the Flash memory and SRAM in the Sleep mode, it is recommended to clear the FMCEN
and SRAMEN bits in the AHBCCR register to minimize power consumption. To enter the Sleep
mode, it is only CPU executes a WFI or WFE instruction and lets the SLEEPDEEP signal to 0. The

system will exit from the Sleep mode via any interrupt or event trigger. The accompanying table
provides more information about the power saving modes.

Table 12. Enter/Exit Power Saving Modes

Mode Entry

Mode

Sleep

Deep-Sleep1 1 0 0

Deep-Sleep2 1 X 1

Power-Down 1 1 0

Notes:

1. Wakeup event means EXTI line in event mode, LVD, and WAKEUP pin rising edge.

2. If the system allows the LVD activity to wake it up after the system has entered the power saving mode,

CPU

Instruction

WFI or WFE
(Takes effect)

CPU

SLEEPDEEP

0 X X

LDOOFF DMOSON

WFI: Any interrupt
WFE:

Any wakeup event
Any interrupt (NVIC on) or
Any interrupt with SEVONPEND = 1 (NVIC off)

Any EXTI in event mode or
LVD wakeup
WAKEUP pin rising edge

LVD wakeup
WAKEUP pin rising edge

LVD wakeup
WAKEUP pin rising edge or
External reset (nRST)

(2)

(2)

(2)

the LVDEWEN and LVDEN bits in the LVDCSR register must be set to 1 to make sure that the system
can be waked up by a LVD event and then the LDO regulator can be turned on when system is woken
up from the Deep-Sleep2 and Power-Down modes.

or

or

or

Mode Exit

(1)

or

Power Control Unit (PWRCU)

Deep-Sleep Mode

To enter Deep-Sleep mode, configure the registers as shown in the preceding table and execute

the WFI or WFE instruction. In the Deep-Sleep mode, all clocks including PLL and high speed
oscillator, known as HSI and HSE, will be stopped. In addition, Deep-Sleep1 turns the LDO into
low current mode while Deep-Sleep2 turns off the LDO and uses a DMOS to keep 1.5 V power.
Once the PWRCU receives a wakeup event or an interrupt as shown in the preceding Mode-Exiting
table, the LDO will then operate in normal mode and the high speed oscillator will be enabled.
Finally, the CPU will return to Run mode to handle the wakeup interrupt if required. A Low

Voltage Detection also can be regarded as a wakeup event if the corresponding wakeup control bit

LVDEWEN in the LVDCSR register is enabled. The last wakeup event is a transition from low to
high on the external WAKEUP pin sent to the PWRCU to resume from Deep-Sleep mode. During

the Deep-Sleep mode, retaining the register and memory contents will shorten the wakeup latency.

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Power-Down Mode

The Power-Down mode is derived from the Deep-Sleep mode of the CPU together with the
additional control bits LDOOFF and DMOSON. To enter the Power-Down mode, users can
congure the registers shown in the preceding Mode-Entering table and execute the WFI or WFE
instruction. A LVD wakeup, a low to high transition on the external WAKEUP pin or an external
reset (nRST) signal will force the MCU out of the Power-Down mode. In the Power-Down mode,
the 1.5 V power supply will be turned off. The remaining active power supplies are the 3.3 V power

(VDD/V

DDA

).

After a system reset, the PORSTF bit in the GRSR register in the Reset Control Unit, RSTCU, the
PDF and PORF bits in the PWRSR register should be checked by software to conrm if the device
is being resumed from the Power-Down mode, an power on reset or other reset events (nRST, WDT,
…). If the device has entered the Power-Down mode under the correct rmware procedure, then the
PDF bit will be set. The system information could be saved in the VDD power domain registers and
be retrieved when the 1.5 V power domain is powered on again. More information about the PDF
and PORF bits in the PWRSR register and PORSTF bit in the RSTCU GRSR register is shown in

the following table.

Power Control Unit (PWRCU)

Table 13. Power Status After System Reset

PORF PDF PORSTF Description

1 0 1

0 0 1

0 1 1 Restart from the Power-Down mode.

1 1 x Reserved

Register Map

The following table shows the PWRCU registers and reset values. Note all the registers in this unit

are located in the V

Table 14. PWRCU Register Map

Register Offset Description Reset Value

PWRSR 0x100 Power Control Status Register 0x0000_0001

PWRCR 0x104 Power Control Register 0x0000_0000

PWRTEST 0x108 VDD Power Domain Test Register 0x0000_0027

LVDCSR 0x110 Low Voltage/Brown Out Detect Control and Status Register 0x0000_0000

power domain.

DD

Power-up for the rst time after the VDD power domain is reset:

Power on reset when VDD is applied for the rst time or executing
software reset command on the VDD domain.

Restart from unexpected loss of the 1.5 V power or other reset
(nRST, WDT, …)

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Register Descriptions

Power Control Status Register – PWRSR

This register indicates the power control status.

Offset: 0x100

Reset value: 0x0000_0001 (Reset only by VDD domain power on reset)

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

Reserved WUPF

Type/Reset RC 0

7 6 5 4 3 2 1 0

Reserved PDF PORF

Type/Reset RC 0 RC 1

Bits Field Descriptions

[8] WUPF External WAKEUP Pin Flag

0: The Wakeup pin is not asserted
1: The Wakeup pin is asserted

This bit is set by hardware when the WAKEUP pin asserts and is cleared by software
read. Software should read this bit to clear it after a system wake up from the power
saving mode.

[1] PDF Power Down Flag

0: Wakeup from abnormal V
1: Wakeup from Power-Down mode. The loss of V

This bit is set by hardware when the system has successfully entered the Power­Down mode. This bit is cleared by software read.

[0] PORF Power On Reset Flag

0: VDD Power Domain reset does not occur
1: VDD Power Domain reset occurs

This bit is set by hardware when VDD power on reset occurs, either a hardware
power on reset or software reset. The bit is cleared by software read. This bit must
be cleared after the system is first powered on, otherwise it will be impossible to
detect when a VDD Power Domain reset has been triggered. When this bit is read
as 1, a read software loop must be implemented until the bit returns again to 0.

This software loop is necessary to conrm that the VDD Power Domain is ready for

access.

shutdown (Loss of V

DD15

is unexpected)

DD15

is under expectation.

DD15

Power Control Unit (PWRCU)

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Power Control Register – PWRCR

This register provides power control bits for the different kinds of power saving modes.

Offset: 0x104

Reset value: 0x0000_0000 (Reset only by VDD domain power on reset)

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

DMOSSTS Reserved V15RDYSC Reserved WUPIEN WUPEN

Type/Reset RO 0 RW 0 RW 0 RW 0

7 6 5 4 3 2 1 0

DMOSON Reserved LDOOFF LDOLCM Reserved PWRST

Type/Reset RW 0 RW 0 RW 0 WO 0

Power Control Unit (PWRCU)

Bits Field Descriptions

[15] DMOSSTS Depletion MOS Status

This bit is set to 1 if the DMOSON bit in this register has been set to 1.
This bit is cleared to 0 if the DMOSON bit has been set to 0 or if a POR/PDR reset
occurred.

[12] V15RDYSC V

[9] WUPIEN External WAKEUP Pin Interrupt Enable

Ready Source Selection.

DD15

0: VDDISO bit in the LPCR register located in the CKCU
1: V

POR

DD15

Setting this bit to determine what control signal of isolation cells is used to disable
the isolation function of the V

to VDD power domain level shifter.

DD15

0: Disable WAKEUP pin interrupt function
1: Enable WAKEUP pin interrupt function

The software can set the WUPIEN bit to 1 to assert the LPWUP interrupt in the NVIC
unit when both the WUPEN and WUPF bits are set to1.

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Bits Field Descriptions

[8] WUPEN External WAKEUP Pin Enable

0: Disable WAKEUP pin function.
1: Enable WAKEUP pin function.

The Software can set the WUPEN bit as 1 to enable the WAKEUP pin function
before entering the power saving mode. When WUPEN = 1, a rising edge on the
WAKEUP pin wakes up the system from the power saving mode. As the WAKEUP
pin is active high, this bit will set an input pull down mode when the bit is high. The

WAKEUP pin alternate function should rst be selected by conguring the PBCFG12
bit eld in the GPBCFGHR register to 0x0F before the WAKEUP pin is used. The

corresponding pull-up function on the WAKEUP pin should also be disabled by
clearing the PBPU[12] bit in the PBPUR register to 0 while the pull-down function
should be enabled by setting the PBPD[12] bit in the PBPDR register to 1.
Note: This bit is reset by a VDD Power Domain reset. Because this bit is located in

the VDD Power Domain, after reset activity there will be a delay until the bit is

active. The bit will not be active until the system reset nished and the VDD

Power Domain ISO signal has been disabled. This means that the bit cannot
be immediately set by software after a system reset finished and the VDD
Power Domain ISO signal disabled. The necessary delay time is a minimum

of three 32kHz clock periods until the bit reset activity has nished.

[7] DMOSON DMOS Control

0: DMOS is OFF
1: DMOS is ON

A DMOS is implemented to provide an alternative voltage source for the 1.5 V power
domain when the CPU enters the Deep-Sleep mode (SLEEPDEEP = 1). The control
bit DMOSON is set by software and cleared by software or VDD power domain reset.
If the DMOSON bit is set to 1, the LDO will automatically be turned off when the
CPU enters the Deep-Sleep mode.

[3] LDOOFF LDO Operating Mode Control

0: The LDO operates in a low current mode when CPU enters the Deep-Sleep

mode (SLEEPDEEP = 1). The V

1: The LDO is turned off when the CPU enters the Deep-Sleep mode

(SLEEPDEEP=1). The V

Note: This bit is only available when the DMOSON bit is cleared to 0.

[2] LDOLCM LDO Low Current Mode

0: The LDO is operated in normal current mode
1: The LDO is operated in low current mode

Note: This bit is only available when CPU is in the run mode. The LDO output

current capability will be limited at 10mA below and lower static current when
the LDOLCM bit is set. It is suitable for CPU is operated at lower speed
system clock to get a lower current consumption. This bit will be clear to 0
when the LDO is power down or VDD power domain reset.

[0] PWRST VDD Power Domain Software Reset

0: No action
1: VDD Power Domain Software Reset is activated

It will reset the PWRCU registers.

DD15

power is available.

DD15

power is not available.

Power Control Unit (PWRCU)

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V

Power Domain Test Register – PWRTEST

DD

This register species a read-only value for the software to recognize whether VDD Power Domain is ready for

access.

Offset: 0x108

Reset value: 0x0000_0027

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

PWRTEST

Type/Reset RO 0 RO 0 RO 1 RO 0 RO 0 RO 1 RO 1 RO 1

Bits Field Descriptions

[7:0] PWRTEST VDD Power Domain Test Bits

A constant 0x27 will be read when the VDD Power Domain is ready for CPU access.

Power Control Unit (PWRCU)

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Low Voltage / Brown Out Detect Control and Status Register – LVDCSR

This register species ags, enable bits and option bits for low voltage detector.

Offset: 0x110

Reset value: 0x0000_0000 (Reset only by VDD domain power on reset)

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved LVDS [2] LVDEWEN LVDIWEN LVDF LVDS [1:0] LVDEN

Type/Reset RW 0 RW 0 RW 0 RO 0 RW 0 RW 0 RW 0

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved BODF Reserved BODRIS BODEN

Type/Reset RO 0 RW 0 RW 0

Power Control Unit (PWRCU)

Bits Field Descriptions

[21] LVDEWEN LVD Event Wakeup Enable

0: LVD event wakeup is disabled
1: LVD event wakeup is enabled

Setting this bit to 1 will enable the LVD event wakeup function to wake up the
system when a LVD condition occurs which result in the LVDF bit being asserted. If
the system requires to be waked up from the Deep-Sleep or Power-Down mode by
a LVD condition, this bit must be set to 1.

[20] LVDIWEN LVD Interrupt Wakeup Enable

0: LVD interrupt wakeup is disabled
1: LVD interrupt wakeup is enabled

Setting this bit to 1 will enable the LVD interrupt function. When a LVD condition
occurs and the LVDIWEN bit is set to 1, a LVD interrupt will be generated and sent
to the CPU NVIC unit.

[19] LVDF Low Voltage Detect Status Flag

0: VDD is higher than the specic voltage level
1: VDD is equal to or lower than the specic voltage level

When the LVD condition occurs, the LVDF ag will be asserted. When the LVDF ag

is asserted, a LVD interrupt will be generated for CPU if the LVDIWEN bit is set to 1.
However, if the LVDEWEN bit is set to 1 and the LVDIWEN bit is cleared to 0, only

a LVD event will be generated rather than a LVD interrupt when the LVDF ag is

asserted.

[22], [18:17] LVDS [2:0] Low Voltage Detect Level Selection

For more details concerning the LVD programmable threshold voltage, refer to the
electrical characteristics of the corresponding datasheet.

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Bits Field Descriptions

[16] LVDEN Low Voltage Detect Enable

0: Disable Low Voltage Detect
1: Enable Low Voltage Detect

Setting this bit to 1 will generate a LVD event when the VDD power is lower than
the voltage set by LVDS bits. Therefore when the LVD function is enabled before
the system is into the Deep-Sleep2 (DMOS is turn on and LDO is power down) or
Power-Down mode (DMOS and LDO is power down), the LVDEWEN bit has to
be enabled to avoid the LDO does not activate in the meantime when the CPU is
woken up by the low voltage detection activity.

[3] BODF Brow Out Detect Flag

0: VDD > V
1: VDD ≤ V

[1] BODRIS BOD Reset or Interrupt Selection

0: Reset the whole chip
1: Generate Interrupt

[0] BODEN Brown Out Detector Enable

0: Disable Brown Out Detector
1: Enable Brown Out Detector

BOD

BOD

Power Control Unit (PWRCU)

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6

Clock Control Unit (CKCU)

Introduction

The Clock Control unit (CKCU) provides functions of high speed internal RC oscillator (HSI),
High speed external crystal oscillator (HSE), Low speed internal RC oscillator (LSI), Phase Lock
Loop (PLL), HSE clock monitor, clock prescaler, clock multiplexer and clock gating. The clock of
AHB, APB, and CPU are derived from system clock (CK_SYS) which can come from HSI, HSE,
LSI or PLL. The Watchdog Timer uses the LSI as the clock source.

A variety of internal clocks can also be wired out through the CKOUT pin for debugging purpose.

The clock monitor can be used to detect the HSE clock failure. Once the HSE clock does not

normally function, which could be broken down or removed, etc., the CKCU will force to switch

the system clock source to the HSI clock to prevent system halt.

Clock Control Unit (CKCU)

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SPI, USART, UART,

HT32F52220/HT32F52230

8 MHz

HSI RC

HSIEN

4-16 MHz

HSE XTAL

HSEEN

Reserved

32 kHz

LSI RC

(Note1)

LSIEN

CKOUTSRC[2:0]

CKOUT

Legend:
HSE = High Speed External clock
HSI = High Speed Internal clock
LSI = Low Speed Internal clock

PLLSRC

1

0

CK_HSI

CK_HSE

CK_LSI

000

001

010

011

100

101

110

PLLEN

PLL

WDTSRC

1
0

CK_REF

HCLKC/16

CK_SYS/16

CK_HSE/16

CK_HSI/16

Reserved

CK_LSI

CK_PLL

WDTEN

CKREFEN

f

= 40 MHz (Recommended)

CK_PLL,max

SW[2:0]

00x

f

CK_SYS,max

011

CK_SYS

010

111

110

Clock

Monitor

CK_WDT

= 40 MHz

AHB Prescaler

1,2,4,8,16,32

CKREFPRE

CM0PEN

CK_AHB

FMCEN

CM0PEN

SRAMEN

CM0PEN

BMEN

CM0PEN

APBEN

Prescaler

1 ~ 32

Peripherals

Prescaler

ADCEN

GPIOAEN

GPIOBEN

CM0PEN

(control by HW)

Clock

1,2,4,8

PCLK

PCLK/2

PCLK/4

PCLK/8

Divider

2

8

00

01

10

11

Prescaler
1,2,3,4,8...

ADC

SPIEN

EXTIEN

CK_REF

STCLK

(to SysTick)

CK_GPIO

( to GPIO port)

FCLK

( Free running clock)

HCLKC

®

( to Cortex

-M0+)

HCLKF

( to Flash)

HCLKS

( to SRAM)

HCLKBM

( to Bus Matrix)

HCLKAPB

( to APB Bridge)

PCLK ( AFIO, ADC,

I2C, GPTM, BFTM,
EXTI, WDT)

CK_ADC IP

Clock Control Unit (CKCU)

Figure 13. CKCU Block Diagram

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Features

▄

4 ~ 16 MHz external crystal oscillator (HSE)

▄

Internal 8 MHz RC oscillator (HSI) with conguration option calibration and custom trimming

capability.

▄

PLL with selectable clock source (from HSE or HSI) for system clock.

▄

Internal 32 kHz RC oscillator (LSI) for Watchdog Timer or system clock.

▄

HSE clock monitor

Function Descriptions

High Speed External Crystal Oscillator – HSE

The high speed external crystal oscillator (HSE) with a frequency range from 4MHz to 16MHz
produces a highly accurate clock source to the system clock. The related hardware conguration is
shown in the following gure. The crystal with specic frequency must be placed across the two
HSE pins (XTALIN / XTALOUT) and the external components such as resistors and capacitors are

necessary to make it oscillate properly.

Clock Control Unit (CKCU)

The following guidelines are provided to improve the stability of the crystal circuit PCB layout.

▄

The crystal oscillator should be located as close as possible to the MCU so that the trace lengths
are kept as short as possible to reduce any parasitic capacitances.

▄

Shield any lines in the vicinity of the crystal by using a ground plane to isolate signals and
reduce noise.

▄

Keep frequently switching signal lines away from the crystal area to prevent crosstalk.

OSC_EN

XTALOUTXTALIN

Rext

Crystal

4 MHz ~ 16 MHz

CL1 CL2

Figure 14. External Crystal, Ceramic, and Resonators for HSE

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The HSE crystal oscillator can be switched on or off using the HSEEN bit in the Global Clock
Control Register (GCCR). The HSERDY f lag in the Global Clock Status Register (GCSR) will

indicate if the high-speed external crystal oscillator is stable. When switching on the HSE

oscillator, the HSE clock will still not be released until this HSERDY bit is set by the hardware. The
specic delay period is well-known as “Start-up time”. As the HSE becomes stable, an interrupt
will be generated if the related interrupt enable bit, HSERDYIE, in the Global Clock Interrupt
Register (GCIR) is set. The HSE clock can then be used directly as the system clock source or be
used as the PLL input clock.

High Speed Internal RC Oscillator – HSI

The high speed internal 8 MHz RC oscillator (HSI) is the default selection of the clock source for
the CPU when the device is powered up. The HSI RC oscillator provides a clock source in a lower
cost because no external components are required. The HSI RC oscillator can be switched on or off
using the HSIEN bit in the Global Clock Control Register (GCCR). The HSIRDY ag in the Global
Clock Status Register (GCSR) will indicate if the internal RC oscillator is stable. The start-up time

of the HSI oscillator is shorter than the HSE crystal oscillator. An interrupt can be generated if the

related interrupt enable bit, HSIRDYIE, in the Global Clock Interrupt Register (GCIR) is set as the
HSI becomes stable. The HSI clock can also be used as the PLL input clock.

Clock Control Unit (CKCU)

The frequency accuracy of the high speed internal RC oscillator, HSI, can be calibrated via

the trimming operations. However, it is still less accurate than the HSE crystal oscillator. The
considerations of the applications, environments and cost will determine the selection of the
oscillators.

The software program could congure the PSRCEN bit (Power Saving Wakeup RC Clock Enable)
to 1 to force the HSI clock to be the system clock when wake-up from the Deep-Sleep or Power-

Down mode. Subsequently, the system clock is switched back to the original clock source (HSE or

PLL) if the original clock source ready ag is asserted. This function can reduce the wakeup time
when using the HSE or PLL output clock as the system clock.

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Phase Locked Loop – PLL

This PLL can provide 4 ~ 48 MHz clock output which is 1~12 multiples of a fundamental reference
frequency of 4 ~ 16 MHz. The rationale of the clock synthesizer relies on the digital Phase Locked
Loop (PLL) which includes a reference divider, a feedback divider, a digital phase frequency
detector (PFD), a current-controlled charge pump, a built-in loop filter and a voltage-controlled

oscillator (VCO) to achieve a stable phase-locked state.

VCO

= 48 ~ 96 MHz

out

Clock Control Unit (CKCU)

CLK

in

Ref. Divider

(NR)

/2

PD CP

Feedback Divider 2

(NF2)

B3~B0

Figure 15. PLL Block Diagram

The frequency of the PLL output clock can be determined by the following formula:

PLL

= CLKin×

OUT

where NR = Ref divider = 2, NF1 = Feedback Divider 1 = 4, NF2 = Feedback Divider 2 = 1 ~ 16,
NO1 = Output Divider 1 = 2, NO2 = Output Divider 2 = 1, 2, 4, or 8

Considering the duty cycle of 50%, both input and output frequencies are divided by 2. If a
given CLKin frequency used as the PLL input generates a specific PLL output frequency, it is
recommended to load a larger value into the NF2 eld to increase the PLL stability and reduce

the jitter with expense of the settling time. The output and feedback divider 2 setup values are

described in Table 15 and Table 16. All the conguration bits (S1 ~ S0, B3 ~ B0) in Table 15 and
Table 16 are defined in the PLL Configuration Register (PLLCFGR) and PLL Control Register
(PLLCR) in the section of Register Denition. Note that the VCO
range from 48 MHz to 96 MHz. If the selected conguration exceeds this range, the PLL output
frequency will not be guaranteed to match the above PLL

VCO

Loop
Filter

Feedback Divider 1

(NF1)

/4

NF1×NF2

NR×NO1×NO2

Output Divider 1

(NO1)

/2

= CLKin× = CLKin×

4×NF2

2×2×NO2

formula.

OUT

Output Divider 2

frequency should be in the

OUT

(NO2)

S1~S0

NF2

NO2

PLL

out

= 4 ~ 48 MHz

The PLL can be switched on or off using the PLLEN bit in the Global Clock Control Register
(GCCR). The PLLRDY ag in the Global Clock Status Register (GCSR) will indicate if the PLL
clock is stable. An interrupt can be generated if the related interrupt enable bit PLLRDYIE in the
Global Clock Interrupt Register (GCIR) is set as the PLL becomes stable.

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Table 15. Output Divider2 Value Mapping

Output divider 2 setup bits S[1:0]

(POTD bits in the PLLCFGR register)

Table 16. Feedback Divider2 Value Mapping

Feedback divider2 setup bits B[3:0]

(PFBD bits in the PLLCFGR register)

NO2 (Output divider 2 value)

00 1

01 2

10 4

11 8

NF2 (Feedback divider 2 value)

0000 16

0001 1

0010 2

0011 3

0100 4

0101 5

0110 6

0111 7

1000 8

1001 9

1010 10

1011 11

1100 12

:
:

1111 15

Clock Control Unit (CKCU)

:
:

Low Speed Internal RC Oscillator – LSI

The low speed internal RC oscillator with a frequency of about 32 kHz produces a low power clock
source for the Watchdog Timer or system clock. The LSI oscillator offers a low cost clock source
because no external component is required to make it oscillates. The LSI RC oscillator is always
enable. The LSI frequency accuracy is shown in the datasheet. The LSIRDY flag in the Global
Clock Status Register (GCSR) will indicate if the LSI clock is stable. An interrupt can be generated
if the related interrupt enable bit LSIRDYIE in the Global Clock Interrupt Register (GCIR) is set as
the LSI becomes stable.

Clock Ready Flag

The CKCU provides the corresponding clock ready ags for the HSI, HSE, PLL and LSI oscillators
to indicate whether these clocks are stable. Before using them as the system clock source or other

purpose, it is necessary to confirm the specific clock ready flag is set. Software can check the

specific clock is ready or not by polling the corresponding clock ready status bits in the GCSR
register. Additionally, the CKCU can trigger an interrupt to notify that the specic clock is ready
if the corresponding interrupt enable bit in the GCIR register is set. Software should clear the
interrupt status bit in the GCIR register in the interrupt service routine.

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System Clock (CK_SYS) Selection

After the system reset occurs, the default system clock source, CK_SYS, will be the high speed
internal RC oscillator, HSI. The CK_SYS may come from the HSI, HSE, LSI or PLL output clock
and it can be switched from one clock source to another by conguring the System Clock Switch
bits SW in the Global Clock Control Register, GCCR. The system will still run under the original

clock until the destination clock gets ready when the SW value is changed. The corresponding

clock ready status bits in the Global Clock Status Register GCSR will indicate whether the selected
clock is ready to use or not. The CKCU also contains the clock source status bits in the Clock
Source Status Register CKST to indicate which clock is currently used as the system clock. If a
clock source or the PLL output clock is used as the system clock source, it is not possible to stop it.

More details about the clock enable function are described in the following .

If any event in the following occurs, the HSI will be enabled .

▄

Enable PLL and congure its source clock to HSI. (PLLEN, PLLSRC)

▄

Enable Clock monitor. (CKMEN)

▄

Congure clock switch register to HSI. (SW)

▄

Congure HSI enable register to 1. (HSIEN)

Clock Control Unit (CKCU)

If any event in the following occurs, the HSE will be enabled.

▄

Enable PLL and congure its source clock to HSE. (PLLEN, PLLSRC)

▄

Congure clock switch register to HSE. (SW)

▄

Congure HSE enable register to 1. (HSEEN)

If any event in the following occurs, the PLL will be enabled.

▄

Enable USB Enable register. (USBEN)

▄

Congure clock switch register to PLL (SW)

▄

Congure PLL enable register to 1. (PLLEN)

The system clock selection programming guide is listed in the following.

1. Enable any clock source which will become the system clock or PLL input clock.

2. Conguring the PLLSRC register will has no operation until the ready ags of both HSI and

HSE are asserted.

3. Configuring the SW register to change the system clock source will take effect after the
corresponding ready flag of the clock source is asserted. Note that the system clock will be

forced to HSI if the clock monitor is enabled and the PLL output clock or HSE clock congured
as the system clock is stuck at 0 or 1.

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HSE Clock Monitor

The HSE Clock Monitor main function is enabled by the HSE Clock Monitor Enable bit CKMEN
in the Global Clock Control Register, GCCR. The HSE clock monitor function should be enabled

after the HSE oscillator start-up delay and disabled when the HSE oscillator is stopped. Once the
HSE oscillator failure is detected, the HSE oscillator will automatically be disabled. The HSE clock

stuck ag CKSF in the Global Clock Interrupt Register GCIR will be set and the HSE oscillator
failure interrupt will be generated if the clock failure interrupt enable bit CKSIE in the GCIR is
set. This failure interrupt is connected to the CPU Non-Maskable Interrupt, NMI. When the HSE

oscillator failure occurs, the HSE will be turned off and the system clock will be switched to the

HSI automatically by the hardware. If the HSE is used as the clock input of the PLL circuit and the
PLL output clock is used as the system clock, the PLL circuit will also be turned off as well as the

HSE when the failure happens.

Clock Output Capability

The device has the clock output capability to allow the clocks to be output on the specic external
output pin CKOUT. The configuration registers of the corresponding GPIO port must be well

configured in the Alternate Function I/O, AFIO, section to output the selected clock signal.
There are six output clock signals to be selected via the device clock output source selection bits

CKOUTSRC in the Global Clock Conguration Register, GCFGR.

Clock Control Unit (CKCU)

Table 17. CKOUT Clock Source

CKOUTSRC[2:0] Clock Source

000 CK_REF = CK_PLL / (CKREFPRE + 1) / 2

001 CK_AHB / 16

010 CK_SYS / 16

011 CK_HSE / 16

100 CK_HSI / 16

101 Reserved

110 CK_LSI

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Register Map

The following table shows the CKCU register and reset value.

Table 18. CKCU Register Map

Register Offset Description Reset Value

GCFGR 0x000 Global Clock Conguration Register 0x0000_0102

GCCR 0x004 Global Clock Control Register 0x0000_0803

GCSR 0x008 Global Clock Status Register 0x0000_0028

GCIR 0x00C Global Clock Interrupt Register 0x0000_0000

PLLCFGR 0x018 PLL Conguration Register 0x0000_0000

PLLCR 0x01C PLL Control Register 0x0000_0000

AHBCFGR 0x020 AHB Conguration Register 0x0000_0000

AHBCCR 0x024 AHB Clock Control Register 0x0000_0065

APBCFGR 0x028 APB Conguration Register 0x0000_0000

APBCCR0 0x02C APB Clock Control Register 0 0x0000_0000

APBCCR1 0x030 APB Clock Control Register 1 0x0000_0000

CKST 0x034 Clock Source Status Register 0x0100_0003

APBPCSR0 0x038 APB Peripheral Clock Selection Register 0 0x0000_0000

APBPCSR1 0x03C APB Peripheral Clock Selection Register 1 0x0000_0000

LPCR 0x300 Low Power Control Register 0x0000_0000

MCUDBGCR 0x304 MCU Debug Control Register 0x0000_0000

Clock Control Unit (CKCU)

Rev. 1.10 77 of 366 November 09, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230

Register Descriptions

Global Clock Conguration Register – GCFGR

This register species the clock source for the PLL/USART/Watchdog Timer/CKOUT.

Offset: 0x000

Reset value: 0x0000_0102

31 30 29 28 27 26 25 24

LPMOD Reserved

Type/Reset RO 0 RO 0 RO 0

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

CKREFPRE

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 1

7 6 5 4 3 2 1 0

Reserved

Type/Reset RW 0 RW 1 RW 0

Reserved PLLSRC

CKOUTSRC

Bits Field Descriptions

[31:29] LPMOD Lower Power Mode Status

000: When Chip is in running mode
001: When Chip wants to enter Sleep mode
010: When Chip wants to enter Deep Sleep mode1
011: When Chip wants to enter Deep Sleep mode2
100: When Chip wants to enter Power Down mode
Others: Reserved

Set and reset by hardware.

[15:11] CKREFPRE CK_REF Clock Prescaler Selection

CK_REF = CK_PLL / (CKREFPRE + 1) / 2

00000: CK_REF = CK_PLL / 2
00001: CK_REF = CK_PLL / 4
...
11111: CK_REF = CK_PLL / 64

Set and reset by software to control the CK_REF clock prescaler setting.

[8] PLLSRC PLL Clock Source Selection

0: External 4 ~ 16 MHz crystal oscillator clock is selected (HSE)
1: Internal 8 MHz RC oscillator clock is selected (HSI)

Set and reset by software to control the PLL clock source.

Clock Control Unit (CKCU)

Rev. 1.10 78 of 366 November 09, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230

Bits Field Descriptions

[2:0] CKOUTSRC CKOUT Clock Source Selection

000: CK_REF is selected

where CK_REF = CK_PLL / (CKREFPRE+1) / 2

001: (HCLKC / 16) is selected
010: (CK_SYS / 16) is selected
011: (CK_HSE / 16) is selected
100: (CK_HSI / 16) is selected
101: Reserved
110: CK_LSI is selected
111: Reserved

Set and reset by software.

Clock Control Unit (CKCU)

Rev. 1.10 79 of 366 November 09, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230

Global Clock Control Register – GCCR

This register species the clock enable bits.

Offset: 0x004

Reset value: 0x0000_0803

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved PSRCEN CKMEN

Type/Reset RW 0 RW 0

15 14 13 12 11 10 9 8

Reserved HSIEN HSEEN PLLEN HSEGAIN

Type/Reset RW 1 RW 0 RW 0 RW 0

7 6 5 4 3 2 1 0

Reserved SW

Type/Reset RW 0 RW 1 RW 1

Clock Control Unit (CKCU)

Bits Field Descriptions

[17] PSRCEN Power Saving Wakeup RC Clock Enable

0: No action
1: Use Internal 8 MHz RC clock (HSI) as system clock after power down wakeup.

The software can set the PSRCEN bit high before entering the power saving mode
in order to reduce the waiting time after a wakeup. When the PSRCEN bit is set to
1, the HSI will be used as the CK_SYS clock source after waking up from the power
saving mode. This means that the instruction can be executed early before the
original clock CK_SYS source is stable since the HSI clock is provided to CPU. After
the original CK_SYS clock source is ready, the CK_SYS clock will automatically be
switched back to the original selected clock source from the HSI clock.

[16] CKMEN HSE Clock Monitor Enable

0: Disable External 4 ~ 16 MHz crystal oscillator clock monitor
1: Enable External 4 ~ 16 MHz crystal oscillator clock monitor

When the hardware detects that the HSE clock is stuck at a low or high state, the
internal hardware will switch the system clock to the internal high speed RC clock,
HSI.

[11] HSIEN Internal High Speed Oscillator Enable

0: Internal 8 MHz RC oscillator is disabled
1: Internal 8 MHz RC oscillator is enabled

Set and reset by software. This bit can not be reset if the HSI clock is used as
system clock.

[10] HSEEN External High Speed Oscillator Enable

0: External 4 ~ 16 MHz crystal oscillator is disabled
1: External 4 ~ 16 MHz crystal oscillator is enabled

Set and reset by software. This bit can not be reset if the HSE clock is used as the
system clock or the PLL input clock.

Rev. 1.10 80 of 366 November 09, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230

Bits Field Descriptions

[9] PLLEN PLL Enable

0: PLL is disabled
1: PLL is enabled

Set and reset by software. This bit cannot be reset if the PLL clock is used as the
system clock.

[8] HSEGAIN External High Speed Oscillator Gain Selection

0: HSE is in low gain mode
1: HSE is in high gain mode

[2:0] SW System Clock Switch

00x: CK_PLL clock out as system clock
010: CK_HSE as system clock
011: CK_HSI as system clock
110: Reserved
111: CK_LSI as system clock
Other: CK_HSI as system clock

These bits are set and reset by software and used to select the CK_SYS source.
When switching the system clock using the SW bits, the system clock will not be
immediately switched and a certain delay is necessary. The system clock source
selected by the SW bits can be indicated in the CKSWST bits in the clock source
status register CKST to make sure which clock is currently used as the system
clock.
Note that the HSI oscillator will be forced as the system clock when the HSE clock
failure is detected as the HSE clock monitor function is enabled.

Clock Control Unit (CKCU)

Rev. 1.10 81 of 366 November 09, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230

Global Clock Status Register – GCSR

This register indicates the clock ready status.

Offset: 0x008

Reset value: 0x0000_0028

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved LSIRDY Reserved HSIRDY HSERDY PLLRDY Reserved

Type/Reset RO 1 RO 1 RO 0 RO 0

Clock Control Unit (CKCU)

Bits Field Descriptions

[5] LSIRDY Internal Low Speed Oscillator Ready Flag

0: Internal 32 kHz RC oscillator is not ready
1: Internal 32 kHz RC oscillator is ready

Set by hardware to indicate whether the LSI oscillator is stable to be used.

[3] HSIRDY Internal High Speed Oscillator Ready Flag

0: Internal 8 MHz RC oscillator is not ready
1: Internal 8 MHz RC oscillator is ready

Set by hardware to indicate whether the HSI oscillator is stable to be used.

[2] HSERDY External High Speed Oscillator Ready Flag

0: External 4 ~ 16 MHz crystal oscillator is not ready
1: External 4 ~ 16 MHz crystal oscillator is ready

Set by hardware to indicate whether the HSE oscillator is stable to be used.

[1] PLLRDY PLL Clock Ready Flag

0: PLL is not ready
1: PLL is ready

Set by hardware to indicate whether the PLL output clock is stable to be used.

Rev. 1.10 82 of 366 November 09, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230

Global Clock Interrupt Register – GCIR

This register species the interrupt enable and ag bits.

Offset: 0x00C

Reset value: 0x0000_0000

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved CKSIE

Type/Reset RW 0

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved CKSF

Type/Reset WC 0

Clock Control Unit (CKCU)

Bits Field Descriptions

[16] CKSIE Clock Stuck Interrupt Enable

0: Disable clock failure interrupt
1: Enable clock failure interrupt

Set and reset by software to enable or disable the clock failure interrupt caused by
the clock monitor function.

[0] CKSF Clock Stuck Interrupt Flag

0: Clock works normally
1: HSE clock is stuck

Reset by software (Write 1 clear). Set by hardware when the HSE clock is stuck and
the CKMEN bit is set.

Rev. 1.10 83 of 366 November 09, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230

PLL Conguration Register – PLLCFGR

This register species the PLL congurations.

Offset: 0x018

Reset value: 0x0000_0000

31 30 29 28 27 26 25 24

Reserved PFBD

Type/Reset RW 0 RW 0 RW 0

23 22 21 20 19 18 17 16

PFBD POTD Reserved

Type/Reset RW 0 RW 0 RW 0

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved

Type/Reset

Clock Control Unit (CKCU)

Bits Field Descriptions

[26:23] PFBD PLL VCO Output Clock Feedback Divider (Figure 15 B3 ~ B0)

The PLL Feedback Divider divides the output clock from the PLL VCO.

[22:21] POTD PLL Output Clock Divider (Figure 15 S1 ~ S0)

PLL Control Register – PLLCR

This register species the PLL Bypass mode.

Offset: 0x01C

Reset value: 0x0000_0000

31 30 29 28 27 26 25 24

PLLBPS Reserved

Type/Reset RW 0

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved

Type/Reset

Bits Field Descriptions

[31] PLLBPS PLL Bypass Mode Enable

0: Disable PLL Bypass mode
1: Enable PLL Bypass mode which acts as FOUT = FIN

Rev. 1.10 84 of 366 November 09, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230

AHB Conguration Register – AHBCFGR

This register species the system clock frequency.

Offset: 0x020

Reset value: 0x0000_0000

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved AHBPRE

Type/Reset RW 0 RW 0 RW 0

Clock Control Unit (CKCU)

Bits Field Descriptions

[2:0] AHBPRE AHB Pre-scaler

000: CK_AHB = CK_SYS
001: CK_AHB = CK_SYS / 2
010: CK_AHB = CK_SYS / 4
011: CK_AHB = CK_SYS / 8
100: CK_AHB = CK_SYS / 16
101: CK_AHB = CK_SYS / 32
110: CK_AHB = CK_SYS / 32
111: CK_AHB = CK_SYS / 32

Set and reset by software to control the division factor of the AHB clock.

Rev. 1.10 85 of 366 November 09, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230

AHB Clock Control Register – AHBCCR

This register species the AHB clock enable control bits.

Offset: 0x024

Reset value: 0x0000_0065

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved PBEN PAEN

Type/Reset RW 0 RW 0

15 14 13 12 11 10 9 8

Reserved CKREFEN Reserved

Type/Reset RW 0

7 6 5 4 3 2 1 0

Reserved APBEN BMEN Reserved SRAMEN Reserved FMCEN

Type/Reset RW 1 RW 1 RW 1 RW 1

Clock Control Unit (CKCU)

Bits Field Descriptions

[17] PBEN GPIO Port B Clock Enable

0: Port B clock is disabled
1: Port B clock is enabled

Set and reset by software

[16] PAEN GPIO Port A Clock Enable

0: Port A clock is disabled
1: Port A clock is enabled

Set and reset by software

[11] CKREFEN CK_REF Clock Enable

0: CK_REF clock is disabled
1: CK_REF clock is enabled

Set and reset by software

[6] APBEN APB bridge Clock Enable

0: APB bridge clock is automatically disabled by hardware during Sleep mode
1: APB bridge clock is always enabled during Sleep mode

Set and reset by software. User can set the APBEN bit to 0 to reduce the power
consumption if the APB bridge is unused during the Sleep mode.

[5] BMEN Bus Matrix Clock Enable

0: Bus Matrix clock is automatically disabled by hardware during Sleep mode
1: Bus Matrix clock is always enabled during Sleep mode

Set and reset by software. User can set the BMEN bit to 0 to reduce the power
consumption if the bus matrix is unused during the Sleep mode.

[2] SRAMEN SRAM Clock Enable

0: SRAM clock is automatically disabled by hardware during Sleep mode
1: SRAM clock is always enabled during Sleep mode

Set and reset by software. User can set the SRAMEN bit to 0 to reduce the power
consumption if the SRAM is unused during the Sleep mode.

Rev. 1.10 86 of 366 November 09, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230

Bits Field Descriptions

[0] FMCEN Flash Memory Controller Clock Enable

0: FMC clock is automatically disabled by hardware during Sleep mode
1: FMC clock is always enabled during Sleep mode

Set and reset by software. User can set the FMCEN bit to 0 to reduce the power
consumption if the Flash Memory is unused during the Sleep mode.

APB Conguration Register – APBCFGR

This register species the ADC conversion clock frequency.

Offset: 0x028

Reset value: 0x0000_0000

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved ADCDIV

Type/Reset RW 0 RW 0 RW 0

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved

Type/Reset

Clock Control Unit (CKCU)

Bits Field Descriptions

[18:16] ADCDIV ADC Clock Frequency Division Selection

000: CK_ADC = (CK_AHB / 1)
001: CK_ADC = (CK_AHB / 2)
010: CK_ADC = (CK_AHB / 4)
011: CK_ADC = (CK_AHB / 8)
100: CK_ADC = (CK_AHB / 16)
101: CK_ADC = (CK_AHB / 32)
110: CK_ADC = (CK_AHB / 64)
111: CK_ADC = (CK_AHB / 3)

Set and reset by software to control the ADC conversion clock division factor.

Rev. 1.10 87 of 366 November 09, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230

APB Clock Control Register 0 – APBCCR0

This register species the APB peripherals clock enable control bits.

Offset: 0x02C

Reset value: 0x0000_0000

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

EXTIEN AFIOEN Reserved UREN Reserved USREN

Type/Reset RW 0 RW 0 RW 0 RW 0

7 6 5 4 3 2 1 0

Reserved SPIEN Reserved I2CEN

Type/Reset RW 0 RW 0

Clock Control Unit (CKCU)

Bits Field Descriptions

[15] EXTIEN External Interrupt Clock Enable

0: EXTI clock is disabled
1: EXTI clock is enabled

Set and reset by software.

[14] AFIOEN Alternate Function I/O Clock Enable

0: AFIO clock is disabled
1: AFIO clock is enabled

Set and reset by software.

[10] UREN UART Clock Enable

0: UART clock is disabled
1: UART clock is enabled

Set and reset by software.

[8] USREN USART Clock Enable

0: USART clock is disabled
1: USART clock is enabled

Set and reset by software.

[4] SPIEN SPI Clock Enable

0: SPI clock is disabled
1: SPI clock is enabled

Set and reset by software.

[0] I2CEN I2C Clock Enable

0: I2C clock is disabled
1: I2C clock is enabled

Set and reset by software.

Rev. 1.10 88 of 366 November 09, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230

APB Clock Control Register 1 – APBCCR1

This register species the APB peripherals clock enable control bits.

Offset: 0x030

Reset value: 0x0000_0000

31 30 29 28 27 26 25 24

Reserved SCTM1EN SCTM0EN Reserved ADCCEN

Type/Reset RW 0 RW 0 RW 0

23 22 21 20 19 18 17 16

Reserved BFTMEN

Type/Reset RW 0

15 14 13 12 11 10 9 8

Reserved GPTMEN

Type/Reset RW 0

7 6 5 4 3 2 1 0

Reserved VDDREN Reserved WDTREN Reserved

Type/Reset RW 0 RW 0

Clock Control Unit (CKCU)

Bits Field Descriptions

[29] SCTM1EN SCTM1 Clock Enable

0: SCTM1 clock is disabled
1: SCTM1 clock is enabled

Set and reset by software.

[28] SCTM0EN SCTM0 Clock Enable

0: SCTM0 clock is disabled
1: SCTM0 clock is enabled

Set and reset by software.

[24] ADCCEN ADC Controller Clock Enable

0: ADC clock is disabled
1: ADC clock is enabled

Set and reset by software.

[16] BFTMEN BFTM Clock Enable

0: BFTM clock is disabled
1: BFTM clock is enabled

Set and reset by software.

[8] GPTMEN GPTM Clock Enable

0: GPTM clock is disabled
1: GPTM clock is enabled

Set and reset by software.

[6] VDDREN VDD Domain Clock Enable for Registers Access

0: VDD Domain Register access clock is disabled
1: VDD Domain Register access clock is enabled

Set and reset by software.

[4] WDTREN Watchdog Timer Clock Enable for Registers Access

0: Register access clock is disabled
1: Register access clock is enabled

Set and reset by software.

Rev. 1.10 89 of 366 November 09, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230

Clock Source Status Register – CKST

This register species the clock source status.

Offset: 0x034

Reset value: 0x0100_0003

31 30 29 28 27 26 25 24

Reserved HSIST

Type/Reset RO 0 RO 0 RO 1

23 22 21 20 19 18 17 16

Reserved HSEST

Type/Reset RO 0 RO 0

15 14 13 12 11 10 9 8

Reserved PLLST

Type/Reset RO 0 RO 0 RO 0 RO 0

7 6 5 4 3 2 1 0

Reserved CKSWST

Type/Reset RO 0 RO 1 RO 1

Clock Control Unit (CKCU)

Bits Field Descriptions

[26:24] HSIST Internal High Speed Clock Occupation Status (CK_HSI)

xx1: HSI is used by System Clock (CK_SYS) (SW = 0x03)
x1x: HSI is used by PLL
1xx: HSI is used by Clock Monitor

[17:16] HSEST External High Speed Clock Occupation Status (CK_HSE)

x1: HSE is used by System Clock (CK_SYS) (SW = 0x02)
1x: HSE is used by PLL

[11:8] PLLST PLL Clock Occupation Status

xxx1: PLL is used by System Clock (CK_SYS)
xx1x: Reserved
x1xx: Reserved
1xxx: PLL is used by CK_REF

[2:0] CKSWST Clock Switch Status

00x: CK_PLL clock out as system clock
010: CK_HSE as system clock
011: CK_HSI as system clock
110: Reserved
111: CK_LSI as system clock

The elds are status to indicate which clock source is using as system clock currently.

Rev. 1.10 90 of 366 November 09, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230

APB Peripheral Clock Selection Register 0 – APBPCSR0

This register species the APB peripheral clock prescaler selection.

Offset: 0x038

Reset value: 0x0000_0000

31 30 29 28 27 26 25 24

Reserved URPCLK Reserved USRPCLK

Type/Reset RW 0 RW 0 RW 0 RW 0

23 22 21 20 19 18 17 16

Reserved

Type/Reset RW 0 RW 0

15 14 13 12 11 10 9 8

Reserved

Type/Reset RW 0 RW 0

7 6 5 4 3 2 1 0

Reserved SPIPCLK Reserved I2CPCLK

Type/Reset RW 0 RW 0 RW 0 RW 0

GPTMPCLK

BFTMPCLK

Reserved

Reserved

Clock Control Unit (CKCU)

Bits Field Descriptions

[29:28] URPCLK UART Peripheral Clock Selection

00: PCLK = CK_AHB
01: PCLK = CK_AHB / 2
10: PCLK = CK_AHB / 4
11: PCLK = CK_AHB / 8

PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock

[25:24] USRPCLK USART Peripheral Clock Selection

00: PCLK = CK_AHB
01: PCLK = CK_AHB / 2
10: PCLK = CK_AHB / 4
11: PCLK = CK_AHB / 8

PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock

[21:20] GPTMPCLK GPTM Peripheral Clock Selection

00: PCLK = CK_AHB
01: PCLK = CK_AHB / 2
10: PCLK = CK_AHB / 4
11: PCLK = CK_AHB / 8

PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock

[13:12] BFTMPCLK BFTM Peripheral Clock Selection

00: PCLK = CK_AHB
01: PCLK = CK_AHB / 2
10: PCLK = CK_AHB / 4
11: PCLK = CK_AHB / 8

PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock

[5:4] SPIPCLK SPI Peripheral Clock Selection

00: PCLK = CK_AHB
01: PCLK = CK_AHB / 2
10: PCLK = CK_AHB / 4
11: PCLK = CK_AHB / 8

PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock

Rev. 1.10 91 of 366 November 09, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230

Bits Field Descriptions

[1:0] I2CPCLK I2C Peripheral Clock Selection

00: PCLK = CK_AHB
01: PCLK = CK_AHB / 2
10: PCLK = CK_AHB / 4
11: PCLK = CK_AHB / 8

PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock

Clock Control Unit (CKCU)

Rev. 1.10 92 of 366 November 09, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230

APB Peripheral Clock Selection Register 1 – APBPCSR1

This register species the APB peripheral clock prescaler selection.

Offset: 0x03C

Reset value: 0x0000_0000

31 30 29 28 27 26 25 24

Reserved

Type/Reset RW 0 RW 0 RW 0 RW 0

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

VDDRPCLK WDTRPCLK

Type/Reset RW 0 RW 0 RW 0 RW 0

7 6 5 4 3 2 1 0

Reserved

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

ADCCPCLK EXTIPCLK AFIOPCLK

SCTM1PCLK SCTM0PCLK

Reserved

Clock Control Unit (CKCU)

Bits Field Descriptions

[27:26] SCTM1PCLK SCTM1 Peripheral Clock Selection

00: PCLK = CK_AHB
01: PCLK = CK_AHB / 2
10: PCLK = CK_AHB / 4
11: PCLK = CK_AHB / 8

PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock

[25:24] SCTM0PCLK SCTM0 Peripheral Clock Selection

00: PCLK = CK_AHB
01: PCLK = CK_AHB / 2
10: PCLK = CK_AHB / 4
11: PCLK = CK_AHB / 8

PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock

[15:14] VDDRPCLK VDD Domain Register Access Clock Selection

00: PCLK = CK_AHB / 4
01: PCLK = CK_AHB / 8
10: PCLK = CK_AHB / 16
11: PCLK = CK_AHB / 32

PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock

[13:12] WDTRPCLK WDT Register Access Clock Selection

00: PCLK = CK_AHB
01: PCLK = CK_AHB / 2
10: PCLK = CK_AHB / 4
11: PCLK = CK_AHB / 8

PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock

[5:4] ADCCPCLK ADC Controller Peripheral Clock Selection

00: PCLK = CK_AHB
01: PCLK = CK_AHB / 2
10: PCLK = CK_AHB / 4
11: PCLK = CK_AHB / 8

PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock

Rev. 1.10 93 of 366 November 09, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230

Bits Field Descriptions

[3:2] EXTIPCLK EXTI Peripheral Clock Selection

00: PCLK = CK_AHB
01: PCLK = CK_AHB / 2
10: PCLK = CK_AHB / 4
11: PCLK = CK_AHB / 8

PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock

[1:0] AFIOPCLK AFIO Peripheral Clock Selection

00: PCLK = CK_AHB
01: PCLK = CK_AHB / 2
10: PCLK = CK_AHB / 4
11: PCLK = CK_AHB / 8

PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock

Clock Control Unit (CKCU)

Rev. 1.10 94 of 366 November 09, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230

Low Power Control Register – LPCR

This register species the low power control.

Offset: 0x300

Reset value: 0x0000_0000

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved VDDISO

Type/Reset RW 0

Clock Control Unit (CKCU)

Bits Field Descriptions

[0] VDDISO VDD Domain Isolation Control

0: VDD domain is isolated from other power domain
1: VDD domain is accessible by other power domain

Set and reset by software. Please refer to the Power Control Unit chapter for more
information.

Rev. 1.10 95 of 366 November 09, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F52220/HT32F52230

MCU Debug Control Register – MCUDBGCR

This register species the MCU debug control.

Offset: 0x304

Reset value: 0x0000_0000

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

DBSCTM1 DBSCTM0 Reserved DBUR Reserved DBBFTM

Type/Reset RW 0 RW 0 RW 0 RW 0

15 14 13 12 11 10 9 8

Reserved DBDSLP2 Reserved DBI2C Reserved DBSPI Reserved DBUSR

Type/Reset RW 0 RW 0 RW 0 RW 0

7 6 5 4 3 2 1 0

Reserved DBGPTM Reserved DBWDT DBPD DBDSLP1 DBSLP

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0

Clock Control Unit (CKCU)

Bits Field Descriptions

[23] DBSCTM1 SCTM1 Debug Mode Enable

0: SCTM1 counter continues to count even if the core is halted
1: SCTM1 counter stops counting when the core is halted

Set and reset by software.

[22] DBSCTM0 SCTM0 Debug Mode Enable

0: SCTM0 counter continues to count even if the core is halted
1: SCTM0 counter stops counting when the core is halted

Set and reset by software.

[18] DBUR UART Debug Mode Enable

0: Same behavior as in normal mode
1: UART FIFO timeout is frozen when the core is halted

Set and reset by software.

[16] DBBFTM BFTM Debug Mode Enable

0: BFTM counter continues to count even if the core is halted
1: BFTM counter stops counting when the core is halted

Set and reset by software.

[14] DBDSLP2 Debug Deep-Sleep2

0: LDO = Off (but turn on DMOS), FCLK = Off, and HCLK = Off in Deep-Sleep2
1: LDO = On, FCLK = On, and HCLK = On in Deep-Sleep2

Set and reset by software.

[12] DBI2C I2C Debug Mode Enable

0: Same behavior as in normal mode
1: I2C timeout is frozen when the core is halted

Set and reset by software.

[10] DBSPI SPI Debug Mode Enable

0: Same behavior as in normal mode
1: SPI FIFO timeout is frozen when the core is halted

Set and reset by software.

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Bits Field Descriptions

[8] DBUSR USART Debug Mode Enable

0: Same behavior as in normal mode
1: USART FIFO timeout is frozen when the core is halted

Set and reset by software.

[6] DBGPTM GPTM Debug Mode Enable

0: GPTM counter continues to count even if the core is halted
1: GPTM counter stops counting when the core is halted

Set and reset by software.

[3] DBWDT Watchdog Timer Debug Mode Enable

0: Watchdog Timer counter continues to count even if the core is halted
1: Watchdog Timer counter stops counting when the core is halted

Set and reset by software.

[2] DBPD Debug Power-Down Mode

0: LDO = Off, FCLK = Off, and HCLK = Off in Power-Down mode
1: LDO = On, FCLK = On, and HCLK = On in Power-Down mode

Set and reset by software.

[1] DBDSLP1 Debug Deep-Sleep1

0: LDO = Low power mode, FCLK = Off, and HCLK = Off in Deep-Sleep1
1: LDO = On, FCLK = On, and HCLK = On in Deep-Sleep1

Set and reset by software.

[0] DBSLP Debug Sleep Mode

0: LDO = On, FCLK = On, and HCLK = Off in Sleep mode
1: LDO = On, FCLK = On, and HCLK = On in Sleep mode

Set and reset by software.

Clock Control Unit (CKCU)

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7

Reset Control Unit (RSTCU)

Introduction

The Reset Control Unit, RSTCU, has three kinds of reset, the power on reset, system reset and
APB unit reset. The power on reset, known as a cold reset, resets the full system during a power
up. A system reset resets the processor core and peripheral IP components with the exception of

the debug port controller. The resets can be triggered by an external signal, internal events and the
reset generators. More information about these resets will be described in the following section.

V

DD15

1.5 V Core

Brown Out

Detector

RESET

VDDDomain

POR

POR15

BODRST

V

DD

nRST

V

Power POR

DD

WDTRST

SYSRESETREQ

POR

Generator

RSTCU

Filter

Filter

Filter

WDT_RSTn

Filter

PWRST

Reset

Reset Control Unit (RSTCU)

®

-M0+

Cortex

PORRESETn

Delay

----

PWRCU reset

WDT reset

SYSRESETREQ

SYSRESETn

PORRESETn

NVIC

SYSRESETREQ

HRESETn CORERESTn

HRESETn

CM0+ Core

System Components

(BusMatrix, PMU)

System Debug

Components

USARTRST

Reset

Generator

Figure 16. RSTCU Block Diagram

USART reset

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Functional Descriptions

Power On Reset

The Power on reset, POR, is generated by either an external reset or the internal reset generator.
Both types have an internal lter to prevent glitches from causing erroneous reset operations. By
referring to Figure 17, the POR15 active low signal will be de-asserted when the internal LDO
voltage regulator is ready to provide 1.5 V power. In addition to the POR15 signal, the Power
Control Unit, PWRCU, will assert the BODF signal as a Power Down Reset, PDR, when the
BODEN bit in the LVDCSR register is set and the brown-out event occurs. For more details about
the PWRCU function, refer to the PWRCU chapter.

V

DD

V

DD15

Reset Control Unit (RSTCU)

t

1

PORESTn

SYSRESTn

* This timing is dependent on the internal LDO regulator output capacitor value.

Figure 17. Power On Reset Sequence

System Reset

A system reset is generated by a power on reset (PORRESETn), a Watchdog Timer reset (WDT_
RSTn), nRST pin or a software reset (SYSRESETREQ) event. For more information about
SYSRESETREQ event, refer to the related chapter in the Cortex®-M0+ reference manual.

AHB and APB Unit Reset

The AHB and APB unit reset can be divided into hardware and software resets. A hardware
reset can be generated by either power on reset or system reset for all AHB and APB units.
Each functional IP connected to the AHB and APB buses can be reset individually through the
associated software reset bits in the RSTCU. For example, the application software can generate a
USART reset via the USRRST bit in the APBPRSTR0 register.

t

2

t1= 25us *Typical.

= 100us

t

t

3

2

= 150us

t

3

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Register Map

The following table shows the RSTCU registers and reset values.

Table 19. RSTCU Register Map

Register Offset Description Reset Value

RSTCU Base Address = 0x4008_8000

GRSR 0x100 Global Reset Status Register 0x0000_0008

AHBPRSTR 0x104 AHB Peripheral Reset Register 0x0000_0000

APBPRSTR0 0x108 APB Peripheral Reset Register 0 0x0000_0000

APBPRSTR1 0x10C APB Peripheral Reset Register 1 0x0000_0000

Register Descriptions

Global Reset Status Register – GRSR

This register species a variety of reset status conditions.

Offset: 0x100

Reset value: 0x0000_0008

Reset Control Unit (RSTCU)

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved PORSTF WDTRSTF EXTRSTF NVICRSTF

Type/Reset WC 1 WC 0 WC 0 WC 0

Bits Field Descriptions

[3] PORSTF Core 1.5 V Power On Reset Flag

0: No POR occurred
1: POR occurred

This bit is set by hardware when a power on reset occurs and reset by writing 1
into it.

[2] WDTRSTF Watchdog Timer Reset Flag

0: No Watchdog Timer reset occurred
1: Watchdog Timer occurred

This bit is set by hardware when a watchdog timer reset occurs and reset by writing
1 into it or by hardware when a power on reset occurs.

[1] EXTRSTF External Pin Reset Flag

0: No pin reset occurred
1: Pin reset occurred

This bit is set by hardware when an external pin reset occurs and reset by writing 1
into it or by hardware when a power on reset occurs.

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