Holtek HT32F50231, HT32F50241 User Manual

Holtek 32-Bit Microcontroller with Arm® Cortex®-M0+

HT32F50231/HT32F50241

User Manual

Revision: V1.00 Date: July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Table of Contents

1 Introduction ........................................................................................................... 21

Overview .............................................................................................................................. 21

Features ............................................................................................................................... 22

Device Information ............................................................................................................... 25

Block Diagram ..................................................................................................................... 26

2 Document Conventions ....................................................................................... 27

3 System Architecture ............................................................................................. 28

Arm® Cortex®-M0+ Processor .............................................................................................. 28

Bus Architecture ................................................................................................................... 29

Memory Organization .......................................................................................................... 30

Memory Map ................................................................................................................................... 31

Embedded Flash Memory ............................................................................................................... 33

Embedded SRAM Memory ............................................................................................................. 33

AHB Peripherals ............................................................................................................................. 33

APB Peripherals ............................................................................................................................. 33

Table of Contents

4 Flash Memory Controller (FMC) .......................................................................... 34

Introduction .......................................................................................................................... 34

Features ............................................................................................................................... 34

Functional Descriptions ....................................................................................................... 35

Flash Memory Map ......................................................................................................................... 35

Flash Memory Architecture ............................................................................................................. 36

Booting Conguration ..................................................................................................................... 37

Page Erase ..................................................................................................................................... 38

Mass Erase ..................................................................................................................................... 39

Word Programming ......................................................................................................................... 40

Option Byte Description .................................................................................................................. 41

Page Erase / Program Protection ................................................................................................... 42

Security Protection .......................................................................................................................... 43

Register Map ....................................................................................................................... 44

Register Descriptions ........................................................................................................... 45

Flash Target Address Register – TADR .......................................................................................... 45

Flash Write Data Register – WRDR ............................................................................................... 46

Flash Operation Command Register – OCMR ............................................................................... 47

Flash Operation Control Register – OPCR ..................................................................................... 48

Flash Operation Interrupt Enable Register – OIER ........................................................................ 49

Flash Operation Interrupt and Status Register – OISR .................................................................. 50

Flash Page Erase / Program Protection Status Register – PPSR .................................................. 52

Flash Security Protection Status Register – CPSR ........................................................................ 53

Flash Vector Mapping Control Register – VMCR ........................................................................... 54

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32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Flash Manufacturer and Device ID Register – MDID ...................................................................... 55

Flash Page Number Status Register – PNSR ................................................................................ 56

Flash Page Size Status Register – PSSR ...................................................................................... 57

Device ID Register – DIDR ............................................................................................................. 58

Custom ID Register n – CIDRn, n = 0 ~3 ....................................................................................... 59

5 Power Control Unit (PWRCU) .............................................................................. 60

Introduction .......................................................................................................................... 60

Features ............................................................................................................................... 61

Functional Descriptions ....................................................................................................... 61

VDD Power Domain .......................................................................................................................... 61

1.5 V Power Domain ....................................................................................................................... 63

Operation Modes ............................................................................................................................ 63

Register Map ....................................................................................................................... 64

Register Descriptions ........................................................................................................... 65

Power Control Status Register – PWRSR ...................................................................................... 65

Power Control Register – PWRCR ................................................................................................. 66

Low Voltage / Brown Out Detect Control and Status Register – LVDCSR ..................................... 68

6 Clock Control Unit (CKCU) .................................................................................. 70

Introduction .......................................................................................................................... 70

Features ............................................................................................................................... 72

Function Descriptions .......................................................................................................... 72

High Speed External Crystal Oscillator – HSE ............................................................................... 72

High Speed Internal RC Oscillator – HSI ........................................................................................ 73

Auto Trimming of High Speed Internal RC Oscillator – HSI ............................................................ 73

Low Speed External Crystal Oscillator – LSE ................................................................................. 75

Low Speed Internal RC Oscillator – LSI ......................................................................................... 75

Clock Ready Flag ........................................................................................................................... 75

System Clock (CK_SYS) Selection ................................................................................................ 75

HSE Clock Monitor ......................................................................................................................... 76

Clock Output Capability .................................................................................................................. 76

Register Map ....................................................................................................................... 77

Register Descriptions ........................................................................................................... 78

Global Clock Conguration Register – GCFGR .............................................................................. 78

Global Clock Control Register – GCCR .......................................................................................... 79

Global Clock Status Register – GCSR ........................................................................................... 81

Global Clock Interrupt Register – GCIR .......................................................................................... 82

AHB Conguration Register – AHBCFGR ...................................................................................... 83

AHB Clock Control Register – AHBCCR ........................................................................................ 84

APB Conguration Register – APBCFGR ....................................................................................... 85

APB Clock Control Register 0 – APBCCR0 .................................................................................... 86

APB Clock Control Register 1 – APBCCR1 .................................................................................... 87

Clock Source Status Register – CKST ........................................................................................... 89

Table of Contents

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32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

APB Peripheral Clock Selection Register 0 – APBPCSR0 ............................................................. 90

APB Peripheral Clock Selection Register 1 – APBPCSR1 ............................................................. 92

HSI Control Register – HSICR ........................................................................................................ 93

HSI Auto Trimming Counter Register – HSIATCR .......................................................................... 94

APB Peripheral Clock Selection Register 2 – APBPCSR2 ............................................................. 95

MCU Debug Control Register – MCUDBGCR ................................................................................ 96

7 Reset Control Unit (RSTCU) ................................................................................ 98

Introduction .......................................................................................................................... 98

Functional Descriptions ....................................................................................................... 99

Power On Reset ............................................................................................................................. 99

System Reset ................................................................................................................................. 99

AHB and APB Unit Reset ................................................................................................................ 99

Register Map ..................................................................................................................... 100

Register Descriptions ......................................................................................................... 100

Global Reset Status Register – GRSR ......................................................................................... 100

AHB Peripheral Reset Register – AHBPRSTR ............................................................................. 101

APB Peripheral Reset Register 0 – APBPRSTR0 ........................................................................ 102

APB Peripheral Reset Register 1 – APBPRSTR1 ........................................................................ 103

Table of Contents

8 General Purpose I/O (GPIO) ............................................................................... 105

Introduction ........................................................................................................................ 105

Features ............................................................................................................................. 106

Functional Descriptions ..................................................................................................... 106

Default GPIO Pin Conguration .................................................................................................... 106

General Purpose I/O – GPIO ........................................................................................................ 106

GPIO Locking Mechanism ............................................................................................................ 108

Register Map ..................................................................................................................... 108

Register Descriptions ......................................................................................................... 109

Port A Data Direction Control Register – PADIRCR ..................................................................... 109

Port A Input Function Enable Control Register – PAINER .............................................................110

Port A Pull-Up Selection Register – PAPUR ..................................................................................111

Port A Pull-Down Selection Register – PAPDR .............................................................................112

Port A Open-Drain Selection Register – PAODR ...........................................................................113

Port A Output Drive Current Selection Register – PADRVR ..........................................................114

Port A Lock Register – PALOCKR .................................................................................................115

Port A Data Input Register – PADINR ............................................................................................116

Port A Output Data Register – PADOUTR .....................................................................................116

Port A Output Set / Reset Control Register – PASRR ...................................................................117

Port A Output Reset Register – PARR ...........................................................................................118

Port A Sink Current Enhanced Selection Register – PASCER ......................................................118

Port B Data Direction Control Register – PBDIRCR ......................................................................119

Port B Input Function Enable Control Register – PBINER ........................................................... 120

Port B Pull-Up Selection Register – PBPUR ................................................................................ 121

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32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Port B Pull-Down Selection Register – PBPDR ............................................................................ 122

Port B Open-Drain Selection Register – PBODR ......................................................................... 123

Port B Output Drive Current Selection Register – PBDRVR ........................................................ 124

Port B Lock Register – PBLOCKR ................................................................................................ 125

Port B Data Input Register – PBDINR .......................................................................................... 126

Port B Output Data Register – PBDOUTR ................................................................................... 126

Port B Output Set / Reset Control Register – PBSRR .................................................................. 127

Port B Output Reset Register – PBRR ......................................................................................... 128

Port B Sink Current Enhanced Selection Register – PBSCER ..................................................... 128

Port C Data Direction Control Register – PCDIRCR .................................................................... 129

Port C Input Function Enable Control Register – PCINER ........................................................... 130

Port C Pull-Up Selection Register – PCPUR ................................................................................ 131

Port C Pull-Down Selection Register – PCPDR ........................................................................... 132

Port C Open Drain Selection Register – PCODR ......................................................................... 133

Port C Output Current Drive Selection Register – PCDRVR ........................................................ 134

Port C Lock Register – PCLOCKR ............................................................................................... 135

Port C Data Input Register – PCDINR .......................................................................................... 136

Port C Output Data Register – PCDOUTR ................................................................................... 136

Port C Output Set / Reset Control Register – PCSRR ................................................................. 137

Port C Output Reset Register – PCRR ......................................................................................... 138

Port C Sink Current Enhanced Selection Register – PCSCER .................................................... 138

Table of Contents

9 Alternate Function Input / Output Control Unit (AFIO) .................................... 139

Introduction ........................................................................................................................ 139

Features ............................................................................................................................. 140

Functional Descriptions ..................................................................................................... 140

External Interrupt Pin Selection .................................................................................................... 140

Alternate Function ......................................................................................................................... 141

Lock Mechanism .......................................................................................................................... 141

Register Map ..................................................................................................................... 141

Register Descriptions ......................................................................................................... 142

EXTI Source Selection Register 0 – ESSR0 ................................................................................ 142

EXTI Source Selection Register 1 – ESSR1 ................................................................................ 143

GPIO x Conguration Low Register – GPxCFGLR, x = A, B, C ................................................... 144

GPIO x Conguration High Register – GPxCFGHR, x = A, B, C .................................................. 145

10 Nested Vectored Interrupt Controller (NVIC) .................................................. 146

Introduction ........................................................................................................................ 146

Features ............................................................................................................................. 147

Function Descriptions ........................................................................................................ 148

SysTick Calibration ....................................................................................................................... 148

Register Map ..................................................................................................................... 148

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32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

11 External Interrupt / Event Controller (EXTI) .................................................... 149

Introduction ........................................................................................................................ 149

Features ............................................................................................................................. 149

Function Descriptions ........................................................................................................ 150

Wakeup Event Management......................................................................................................... 150

External Interrupt / Event Line Mapping ....................................................................................... 151

Interrupt and Debounce ................................................................................................................ 151

Register Map ..................................................................................................................... 152

Register Descriptions ......................................................................................................... 153

EXTI Interrupt n Conguration Register – EXTICFGRn, n = 0 ~ 15 ............................................. 153

EXTI Interrupt Control Register – EXTICR ................................................................................... 154

EXTI Interrupt Edge Flag Register – EXTIEDGEFLGR ................................................................ 155

EXTI Interrupt Edge Status Register – EXTIEDGESR ................................................................. 156

EXTI Interrupt Software Set Command Register – EXTISSCR .................................................... 157

EXTI Interrupt Wakeup Control Register – EXTIWAKUPCR ........................................................ 158

EXTI Interrupt Wakeup Polarity Register – EXTIWAKUPPOLR ................................................... 159

EXTI Interrupt Wakeup Flag Register – EXTIWAKUPFLG ........................................................... 160

Table of Contents

12 Analog to Digital Converter (ADC) .................................................................. 161

Introduction ........................................................................................................................ 161

Features ............................................................................................................................. 162

Function Descriptions ........................................................................................................ 163

ADC Clock Setup .......................................................................................................................... 163

Channel Selection ......................................................................................................................... 163

Conversion Mode .......................................................................................................................... 163

Start Conversion on External Event .............................................................................................. 166

Sampling Time Setting .................................................................................................................. 167

Data Format .................................................................................................................................. 167

Analog Watchdog.......................................................................................................................... 167

Interrupts ....................................................................................................................................... 168

Register Map ..................................................................................................................... 169

Register Descriptions ......................................................................................................... 170

ADC Conversion Control Register – ADCCR ............................................................................... 170

ADC Conversion List Register 0 – ADCLST0 .............................................................................. 172

ADC Conversion List Register 1 – ADCLST1 ............................................................................... 173

ADC Input Sampling Time Register – ADCSTR ........................................................................... 174

ADC Conversion Data Register y – ADCDRy, y = 0 ~ 7 ............................................................... 175

ADC Trigger Control Register – ADCTCR .................................................................................... 176

ADC Trigger Source Register – ADCTSR ..................................................................................... 177

ADC Watchdog Control Register – ADCWCR .............................................................................. 178

ADC Watchdog Threshold Register – ADCTR .............................................................................. 180

ADC Interrupt Enable Register – ADCIER ................................................................................... 181

ADC Interrupt Raw Status Register – ADCIRAW ......................................................................... 182

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32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

ADC Interrupt Status Register – ADCISR ..................................................................................... 183

ADC Interrupt Clear Register – ADCICLR .................................................................................... 184

13 General-Purpose Timer (GPTM) ...................................................................... 185

Introduction ........................................................................................................................ 185

Features ............................................................................................................................. 185

Functional Descriptions ..................................................................................................... 186

Counter Mode ............................................................................................................................... 186

Clock Controller ............................................................................................................................ 189

Trigger Controller .......................................................................................................................... 190

Slave Controller ............................................................................................................................ 191

Master Controller .......................................................................................................................... 193

Channel Controller ........................................................................................................................ 194

Input Stage ................................................................................................................................... 197

Quadrature Decoder ..................................................................................................................... 199

Output Stage ................................................................................................................................. 201

Update Management .................................................................................................................... 205

Single Pulse Mode ........................................................................................................................ 206

Asymmetric PWM Mode ............................................................................................................... 208

Timer Interconnection ................................................................................................................... 209

Trigger ADC Start.......................................................................................................................... 212

Register Map ..................................................................................................................... 212

Register Descriptions ......................................................................................................... 213

Timer Counter Conguration Register – CNTCFR ....................................................................... 213

Timer Mode Conguration Register – MDCFR ............................................................................. 214

Timer Trigger Conguration Register – TRCFR ............................................................................ 217

Timer Counter Register – CTR ..................................................................................................... 218

Channel 0 Input Conguration Register – CH0ICFR .................................................................... 219

Channel 1 Input Conguration Register – CH1ICFR .................................................................... 220

Channel 2 Input Conguration Register – CH2ICFR .................................................................... 222

Channel 3 Input Conguration Register – CH3ICFR .................................................................... 223

Channel 0 Output Conguration Register – CH0OCFR ............................................................... 224

Channel 1 Output Conguration Register – CH1OCFR ............................................................... 226

Channel 2 Output Conguration Register – CH2OCFR ............................................................... 228

Channel 3 Output Conguration Register – CH3OCFR ............................................................... 230

Channel Control Register – CHCTR ............................................................................................. 232

Channel Polarity Conguration Register – CHPOLR .................................................................... 233

Timer Interrupt Control Register – DICTR .................................................................................... 234

Timer Event Generator Register – EVGR ..................................................................................... 235

Timer Interrupt Status Register – INTSR ...................................................................................... 236

Timer Counter Register – CNTR................................................................................................... 238

Timer Prescaler Register – PSCR ................................................................................................ 239

Timer Counter Reload Register – CRR ........................................................................................ 240

Channel 0 Capture / Compare Register – CH0CCR .................................................................... 241

Table of Contents

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32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Channel 1 Capture / Compare Register – CH1CCR .................................................................... 242

Channel 2 Capture / Compare Register – CH2CCR .................................................................... 243

Channel 3 Capture / Compare Register – CH3CCR .................................................................... 244

Channel 0 Asymmetric Compare Register – CH0ACR ................................................................. 245

Channel 1 Asymmetric Compare Register – CH1ACR ................................................................. 245

Channel 2 Asymmetric Compare Register – CH2ACR ................................................................. 246

Channel 3 Asymmetric Compare Register – CH3ACR ................................................................. 246

14 Pulse Width Modulator (PWM) ......................................................................... 247

Introduction ........................................................................................................................ 247

Features ............................................................................................................................. 248

Functional Descriptions ..................................................................................................... 248

Counter Mode ............................................................................................................................... 248

Clock Controller ............................................................................................................................ 251

Trigger Controller .......................................................................................................................... 252

Slave Controller ............................................................................................................................ 253

Master Controller .......................................................................................................................... 255

Channel Controller ........................................................................................................................ 256

Output Stage ................................................................................................................................. 256

Update Management .................................................................................................................... 260

Single Pulse Mode ........................................................................................................................ 260

Asymmetric PWM Mode ............................................................................................................... 263

Timer Interconnection ................................................................................................................... 263

Trigger Peripherals Start ............................................................................................................... 265

Register Map ..................................................................................................................... 266

Register Descriptions ......................................................................................................... 267

Timer Counter Conguration Register – CNTCFR ....................................................................... 267

Timer Mode Conguration Register – MDCFR ............................................................................. 268

Timer Trigger Conguration Register – TRCFR ............................................................................ 271

Timer Counter Register – CTR ..................................................................................................... 272

Channel 0 Output Conguration Register – CH0OCFR ............................................................... 273

Channel 1 Output Conguration Register – CH1OCFR ............................................................... 275

Channel 2 Output Conguration Register – CH2OCFR ............................................................... 277

Channel 3 Output Conguration Register – CH3OCFR ............................................................... 279

Channel Control Register – CHCTR ............................................................................................. 281

Channel Polarity Conguration Register – CHPOLR .................................................................... 282

Timer Interrupt Control Register – DICTR .................................................................................... 283

Timer Event Generator Register – EVGR ..................................................................................... 284

Timer Interrupt Status Register – INTSR ...................................................................................... 285

Timer Counter Register – CNTR................................................................................................... 286

Timer Prescaler Register – PSCR ................................................................................................ 287

Timer Counter Reload Register – CRR ........................................................................................ 287

Channel 0 Compare Register – CH0CR ....................................................................................... 288

Channel 1 Compare Register – CH1CR ....................................................................................... 288

Channel 2 Compare Register – CH2CR ....................................................................................... 289

Table of Contents

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32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Channel 3 Compare Register – CH3CR ....................................................................................... 289

Channel 0 Asymmetric Compare Register – CH0ACR ................................................................. 290

Channel 1 Asymmetric Compare Register – CH1ACR ................................................................. 290

Channel 2 Asymmetric Compare Register – CH2ACR ................................................................. 291

Channel 3 Asymmetric Compare Register – CH3ACR ................................................................. 291

15 Basic Function Timer (BFTM) .......................................................................... 292

Introduction ........................................................................................................................ 292

Features ............................................................................................................................. 292

Functional Description ....................................................................................................... 293

Repetitive Mode ............................................................................................................................ 293

One Shot Mode ............................................................................................................................. 294

Trigger ADC Start.......................................................................................................................... 294

Register Map ..................................................................................................................... 295

Register Descriptions ......................................................................................................... 295

BFTM Control Register – BFTMCR .............................................................................................. 295

BFTM Status Register – BFTMSR ................................................................................................ 296

BFTM Counter Value Register – BFTMCNTR .............................................................................. 297

BFTM Compare Value Register – BFTMCMPR ........................................................................... 297

16 Motor Control Timer (MCTM) ........................................................................... 298

Introduction ........................................................................................................................ 298

Features ............................................................................................................................. 299

Functional Descriptions ..................................................................................................... 299

Counter Mode ............................................................................................................................... 299

Clock Controller ............................................................................................................................ 303

Trigger Controller .......................................................................................................................... 304

Slave Controller ............................................................................................................................ 305

Master Controller .......................................................................................................................... 307

Channel Controller ........................................................................................................................ 308

Input Stage ................................................................................................................................... 309

Output Stage ..................................................................................................................................311

Update Management .................................................................................................................... 322

Single Pulse Mode ........................................................................................................................ 324

Timer Interconnection ................................................................................................................... 327

Trigger ADC Start.......................................................................................................................... 331

Lock Level Table ........................................................................................................................... 331

Register Map ..................................................................................................................... 331

Register Descriptions ......................................................................................................... 332

Timer Counter Conguration Register – CNTCFR ....................................................................... 332

Timer Mode Conguration Register – MDCFR ............................................................................. 334

Timer Trigger Conguration Register – TRCFR ............................................................................ 337

Timer Control Register – CTR ...................................................................................................... 338

Channel 0 Input Conguration Register – CH0ICFR .................................................................... 339

Table of Contents

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32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Channel 1 Input Conguration Register – CH1ICFR .................................................................... 340

Channel 2 Input Conguration Register – CH2ICFR .................................................................... 342

Channel 3 Input Conguration Register – CH3ICFR .................................................................... 343

Channel 0 Output Conguration Register – CH0OCFR ............................................................... 345

Channel 1 Output Conguration Register – CH1OCFR ............................................................... 347

Channel 2 Output Conguration Register – CH2OCFR ............................................................... 349

Channel 3 Output Conguration Register – CH3OCFR ............................................................... 351

Channel Control Register – CHCTR ............................................................................................. 353

Channel Polarity Conguration Register – CHPOLR .................................................................... 355

Channel Break Conguration Register – CHBRKCFR ................................................................. 356

Channel Break Control Register – CHBRKCTR ........................................................................... 357

Timer Interrupt Control Register – DICTR .................................................................................... 359

Timer Event Generator Register – EVGR ..................................................................................... 360

Timer Interrupt Status Register – INTSR ...................................................................................... 362

Timer Counter Register – CNTR................................................................................................... 364

Timer Prescaler Register – PSCR ................................................................................................ 365

Timer Counter Reload Register – CRR ........................................................................................ 366

Timer Repetition Register – REPR ............................................................................................... 366

Channel 0 Capture/Compare Register – CH0CCR ...................................................................... 367

Channel 1 Capture/Compare Register – CH1CCR ...................................................................... 368

Channel 2 Capture/Compare Register – CH2CCR ...................................................................... 369

Channel 3 Capture/Compare Register – CH3CCR ...................................................................... 370

Channel 0 Asymmetric Compare Register – CH0ACR ................................................................. 371

Channel 1 Asymmetric Compare Register – CH1ACR ................................................................. 371

Channel 2 Asymmetric Compare Register – CH2ACR ................................................................. 372

Channel 3 Asymmetric Compare Register – CH3ACR ................................................................. 372

Table of Contents

17 Real Time Clock (RTC) ..................................................................................... 373

Introduction ........................................................................................................................ 373

Features ............................................................................................................................. 373

Functional Descriptions ..................................................................................................... 374

RTC Related Register Reset ........................................................................................................ 374

Low Speed Clock Conguration ................................................................................................... 374

RTC Counter Operation ................................................................................................................ 374

Interrupt and Wakeup Control ....................................................................................................... 374

RTCOUT Output Pin Conguration............................................................................................... 375

Register Map ..................................................................................................................... 376

Register Descriptions ......................................................................................................... 376

RTC Counter Register – RTCCNT ................................................................................................ 376

RTC Compare Register – RTCCMP ............................................................................................. 377

RTC Control Register – RTCCR ................................................................................................... 378

RTC Status Register – RTCSR..................................................................................................... 380

RTC Interrupt and Wakeup Enable Register – RTCIWEN ........................................................... 381

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32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

18 Watchdog Timer (WDT) .................................................................................... 382

Introduction ........................................................................................................................ 382

Features ............................................................................................................................. 382

Functional Description ....................................................................................................... 383

Register Map ..................................................................................................................... 385

Register Descriptions ......................................................................................................... 385

Watchdog Timer Control Register – WDTCR ............................................................................... 385

Watchdog Timer Mode Register 0 – WDTMR0............................................................................. 386

Watchdog Timer Mode Register 1 – WDTMR1............................................................................. 387

Watchdog Timer Status Register – WDTSR ................................................................................. 388

Watchdog Timer Protection Register – WDTPR ........................................................................... 389

Watchdog Timer Clock Selection Register – WDTCSR ............................................................... 390

19 Inter-Integrated Circuit (I2C) ............................................................................. 391

Introduction ........................................................................................................................ 391

Features ............................................................................................................................. 392

Functional Descriptions ..................................................................................................... 392

Two-Wire Serial Interface ............................................................................................................. 392

START and STOP Conditions ....................................................................................................... 392

Data Validity .................................................................................................................................. 393

Addressing Format ....................................................................................................................... 394

Data Transfer and Acknowledge ................................................................................................... 396

Clock Synchronization .................................................................................................................. 397

Arbitration ..................................................................................................................................... 397

General Call Addressing ............................................................................................................... 398

Bus Error ....................................................................................................................................... 398

Address Mask Enable ................................................................................................................... 398

Address Snoop ............................................................................................................................. 398

Operation Mode ............................................................................................................................ 398

Conditions of Holding SCL Line .................................................................................................... 404

I2C Timeout Function .................................................................................................................... 405

Register Map ..................................................................................................................... 405

Register Descriptions ......................................................................................................... 406

I2C Control Register – I2CCR ....................................................................................................... 406

I2C Interrupt Enable Register – I2CIER ........................................................................................ 407

I2C Address Register – I2CADDR ................................................................................................. 409

I2C Status Register – I2CSR ......................................................................................................... 410

I2C SCL High Period Generation Register – I2CSHPGR .............................................................. 413

I2C SCL Low Period Generation Register – I2CSLPGR ............................................................... 414

I2C Data Register – I2CDR ........................................................................................................... 415

I2C Target Register – I2CTAR ....................................................................................................... 416

I2C Address Mask Register – I2CADDMR .................................................................................... 417

I2C Address Snoop Register – I2CADDSR ................................................................................... 418

I2C Timeout Register – I2CTOUT.................................................................................................. 419

Table of Contents

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32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

20 Serial Peripheral Interface (SPI) ...................................................................... 420

Introduction ........................................................................................................................ 420

Features ............................................................................................................................. 421

Function Descriptions ........................................................................................................ 421

Master Mode ................................................................................................................................. 421

Slave Mode ................................................................................................................................... 421

SPI Serial Frame Format .............................................................................................................. 422

Status Flags .................................................................................................................................. 426

Register Map ..................................................................................................................... 428

Register Descriptions ......................................................................................................... 429

SPI Control Register 0 – SPICR0 ................................................................................................. 429

SPI Control Register 1 – SPICR1 ................................................................................................. 431

SPI Interrupt Enable Register – SPIIER ....................................................................................... 432

SPI Clock Prescaler Register – SPICPR ...................................................................................... 433

SPI Data Register – SPIDR .......................................................................................................... 434

SPI Status Register – SPISR ........................................................................................................ 435

SPI FIFO Control Register – SPIFCR ........................................................................................... 437

SPI FIFO Status Register – SPIFSR ............................................................................................ 438

SPI FIFO Time Out Counter Register – SPIFTOCR ..................................................................... 439

Table of Contents

21 Universal Synchronous Asynchronous Receiver Transmitter (USART) ..... 440

Introduction ........................................................................................................................ 440

Features ............................................................................................................................. 441

Functional Descriptions ..................................................................................................... 441

Serial Data Format ........................................................................................................................ 441

Baud Rate Generation .................................................................................................................. 442

Hardware Flow Control ................................................................................................................. 443

IrDA ............................................................................................................................................... 444

RS485 Mode ................................................................................................................................. 446

Synchronous Master Mode ........................................................................................................... 448

Interrupts and Status .................................................................................................................... 450

Register Map ..................................................................................................................... 450

Register Descriptions ......................................................................................................... 451

USART Data Register – USRDR .................................................................................................. 451

USART Control Register – USRCR .............................................................................................. 452

USART FIFO Control Register – USRFCR................................................................................... 454

USART Interrupt Enable Register – USRIER ............................................................................... 455

USART Status & Interrupt Flag Register – USRSIFR................................................................... 457

USART Timing Parameter Register – USRTPR ........................................................................... 459

USART IrDA Control Register – IrDACR ...................................................................................... 460

USART RS485 Control Register – RS485CR............................................................................... 461

USART Synchronous Control Register – SYNCR ........................................................................ 462

USART Divider Latch Register – USRDLR................................................................................... 463

USART Test Register – USRTSTR ............................................................................................... 464

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32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

22 Universal Asynchronous Receiver Transmitter (UART) ................................ 465

Introduction ........................................................................................................................ 465

Features ............................................................................................................................. 466

Function Descriptions ........................................................................................................ 466

Serial Data Format ........................................................................................................................ 466

Baud Rate Generation .................................................................................................................. 467

Interrupts and Status .................................................................................................................... 468

Register Map ..................................................................................................................... 468

Register Descriptions ......................................................................................................... 469

UART Data Register – URDR ....................................................................................................... 469

UART Control Register – URCR ................................................................................................... 470

UART Interrupt Enable Register – URIER .................................................................................... 471

UART Status & Interrupt Flag Register – URSIFR ....................................................................... 472

UART Divider Latch Register – URDLR ....................................................................................... 474

UART Test Register – URTSTR .................................................................................................... 475

Table of Contents

23 Divider (DIV) ...................................................................................................... 476

Introduction ........................................................................................................................ 476

Features ............................................................................................................................. 476

Functional Descriptions ..................................................................................................... 476

Register Map ..................................................................................................................... 477

Register Descriptions ......................................................................................................... 477

Divider Control Register – CR ...................................................................................................... 477

Dividend Data Register – DDR ..................................................................................................... 478

Divisor Data Register – DSR ........................................................................................................ 478

Quotient Data Register – QTR ...................................................................................................... 479

Remainder Data Register – RMR ................................................................................................. 479

24 Cyclic Redundancy Check (CRC) .................................................................... 480

Introduction ....................................................................................................................... 480

Features ............................................................................................................................. 480

Functional Descriptions ..................................................................................................... 481

CRC Computation ......................................................................................................................... 481

Byte and Bit Reversal for CRC Computation ................................................................................ 481

Register Map ..................................................................................................................... 482

Register Descriptions ......................................................................................................... 482

CRC Control Register – CRCCR .................................................................................................. 482

CRC Seed Register – CRCSDR ................................................................................................... 483

CRC Checksum Register – CRCCSR .......................................................................................... 484

CRC Data Register – CRCDR ...................................................................................................... 485

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32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

List of Tables

Table 1. Features and Peripheral List ..................................................................................................... 25

Table 2. Document Conventions ............................................................................................................. 27

Table 3. Register Map ............................................................................................................................. 32

Table 4. Flash Memory and Option Byte ................................................................................................. 36

Table 5. Booting Modes .......................................................................................................................... 37

Table 6. Option Byte Memory Map ......................................................................................................... 41

Table 7. Access Permission of Protected Main Flash Page .................................................................... 42

Table 8. Access Permission When Security Protection is Enabled ......................................................... 43

Table 9. FMC Register Map .................................................................................................................... 44

Table 10. Operation Mode Denitions ..................................................................................................... 63

Table 11. Enter / Exit Power Saving Modes ............................................................................................ 64

Table 12. Power Status After System Reset ........................................................................................... 64

Table 13. PWRCU Register Map ............................................................................................................ 64

Table 14. CKOUT Clock Source ............................................................................................................. 76

Table 15. CKCU Register Map ............................................................................................................... 77

Table 16. RSTCU Register Map ........................................................................................................... 100

Table 17. AFIO, GPIO and I/O Pad Control Signal True Table.............................................................. 107

Table 18. GPIO Register Map ............................................................................................................... 108

Table 19. AFIO Selection for Peripheral Map Example ......................................................................... 141

Table 20. AFIO Register Map ................................................................................................................ 141

Table 21. Exception Types .................................................................................................................... 146

Table 22. NVIC Register Map ............................................................................................................... 148

Table 23. EXTI Register Map ................................................................................................................ 152

Table 24. Data Format in ADCDR [15:0] ............................................................................................... 167

Table 25. A/D Converter Register Map ................................................................................................. 169

Table 26. Counting Direction and Encoding Signals ............................................................................. 200

Table 27. Compare Match Output Setup .............................................................................................. 201

Table 28. GPTM Register Map ............................................................................................................. 212

Table 29. GPTM Internal Trigger Connection ....................................................................................... 217

Table 30. Compare Match Output Setup .............................................................................................. 257

Table 31. PWM Register Map ............................................................................................................... 266

Table 32. PWM Internal Trigger Connection ......................................................................................... 271

Table 33. BFTM Register Map .............................................................................................................. 295

Table 34. Compare Match Output Setup .............................................................................................. 312

Table 35. Output Control Bits for Complementary Output with a Break Event Occurrence .................. 321

Table 36. Lock Level Table.................................................................................................................... 331

Table 37. MCTM Register Map ............................................................................................................. 331

Table 38. MCTM Internal Trigger Connection ....................................................................................... 337

Table 39. LSE Startup Mode Operating Current and Startup Time ....................................................... 374

List of Tables

Rev. 1.00 14 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Table 40. RTCOUT Output Mode and Active Level Setting .................................................................. 375

Table 41. RTC Register Map................................................................................................................. 376

Table 42. Watchdog Timer Register Map .............................................................................................. 385

Table 43. Conditions of Holding SCL line .............................................................................................. 404

Table 44. I2C Register Map ................................................................................................................... 405

Table 45. I2C Clock Setting Example .................................................................................................... 414

Table 46. SPI Interface Format Setup ................................................................................................... 422

Table 47. SPI Mode Fault Trigger Conditions ....................................................................................... 427

Table 48. SPI Master Mode SEL Pin Status ......................................................................................... 427

Table 49. SPI Register Map .................................................................................................................. 428

Table 50. Baud Rate Deviation Error Calculation – CK_USART = 20 MHz .......................................... 443

Table 51. Baud Rate Deviation Error Calculation – CK_USART = 10 MHz .......................................... 443

Table 52. USART Register Map ............................................................................................................ 450

Table 53. Baud Rate Deviation Error Calculation – CK_UART = 20 MHz ............................................ 467

Table 54. Baud Rate Deviation Error Calculation – CK_UART = 10 MHz ............................................ 468

Table 55. UART Register Map .............................................................................................................. 468

Table 56. DIV Register Map .................................................................................................................. 477

Table 57. CRC Register Map ................................................................................................................ 482

List of Tables

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32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

List of Figures

Figure 1. Block Diagram ......................................................................................................................... 26

Figure 2. Cortex®-M0+ Block Diagram .................................................................................................... 29

Figure 3. Bus Architecture ...................................................................................................................... 30

Figure 4. Memory Map ............................................................................................................................ 31

Figure 5. Flash Memory Controller Block Diagram ................................................................................. 34

Figure 6. Flash Memory Map .................................................................................................................. 35

Figure 7. Vector Remapping ................................................................................................................... 37

Figure 8. Page Erase Operation Flowchart ............................................................................................ 38

Figure 9. Mass Erase Operation Flowchart ............................................................................................ 39

Figure 10. Word Programming Operation Flowchart .............................................................................. 40

Figure 11. PWRCU Block Diagram ......................................................................................................... 60

Figure 12. Power On Reset / Power Down Reset Waveform ................................................................. 62

Figure 13. CKCU Block Diagram ............................................................................................................ 71

Figure 14. External Crystal, Ceramic and Resonators for HSE .............................................................. 72

Figure 15. HSI Auto Trimming Block Diagram ........................................................................................ 74

Figure 16. External Crystal, Ceramic and Resonators for LSE .............................................................. 75

Figure 17. RSTCU Block Diagram .......................................................................................................... 98

Figure 18. Power On Reset Sequence ................................................................................................... 99

Figure 19. GPIO Block Diagram ........................................................................................................... 105

Figure 20. AFIO / GPIO Control Signal ................................................................................................. 107

Figure 21. AFIO Block Diagram ............................................................................................................ 139

Figure 22. EXTI Channel Input Selection ............................................................................................. 140

Figure 23. EXTI Block Diagram ............................................................................................................ 149

Figure 24. EXTI Wakeup Event Management ...................................................................................... 150

Figure 25. EXTI Interrupt Debounce Function ...................................................................................... 151

Figure 26. ADC Block Diagram ............................................................................................................ 161

Figure 27. One Shot Conversion Mode ................................................................................................ 164

Figure 28. Continuous Conversion Mode ............................................................................................. 164

Figure 29. Discontinuous Conversion Mode ......................................................................................... 166

Figure 30. GPTM Block Diagram .......................................................................................................... 185

Figure 31. Up-counting Example .......................................................................................................... 186

Figure 32. Down-counting Example ...................................................................................................... 187

Figure 33. Center-aligned Counting Example ....................................................................................... 188

Figure 34. GPTM Clock Source Selection ............................................................................................ 189

Figure 35. Trigger Controller Block ....................................................................................................... 190

Figure 36. Slave Controller Diagram .................................................................................................... 191

Figure 37. GPTM in Restart Mode ........................................................................................................ 191

Figure 38. GPTM in Pause Mode ......................................................................................................... 192

Figure 39. GPTM in Trigger Mode ........................................................................................................ 192

List of Figures

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32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Figure 40. Master GPTMn and Slave GPTMm / MCTMm Connection ................................................. 193

Figure 41. MTO Selection ..................................................................................................................... 193

Figure 42. Capture / Compare Block Diagram ...................................................................................... 194

Figure 43. Input Capture Mode ............................................................................................................. 195

Figure 44. PWM Pulse Width Measurement Example .......................................................................... 196

Figure 45. Channel 0 and Channel 1 Input Stages ............................................................................... 197

Figure 46. Channel 2 and Channel 3 Input Stages ............................................................................... 198

Figure 47. TI0 Digital Filter Diagram with N = 2 .................................................................................... 198

Figure 48. Input Stage and Quadrature Decoder Block Diagram ......................................................... 199

Figure 49. Both TI0 and TI1 Quadrature Decoder Counting ................................................................. 200

Figure 50. Output Stage Block Diagram ............................................................................................... 201

Figure 51. Toggle Mode Channel Output Reference Signal – CHxPRE = 0 ......................................... 202

Figure 52. Toggle Mode Channel Output Reference Signal – CHxPRE = 1 ......................................... 202

Figure 53. PWM Mode Channel Output Reference Signal and Counter in Up-counting Mode ............ 203

Figure 54. PWM Mode Channel Output Reference Signal and Counter in Down-counting Mode ....... 203

Figure 55. PWM Mode Channel Output Reference Signal and Counter in Centre-aligned Mode ........ 204

Figure 56. Update Event Setting Diagram ............................................................................................ 205

Figure 57. Single Pulse Mode ............................................................................................................... 206

Figure 58. Immediate Active Mode Minimum Delay ............................................................................. 207

Figure 59. Asymmetric PWM Mode versus Center-aligned Counting Mode ......................................... 208

Figure 60. Pausing MCTM using the GPTM CH0OREF Signal ............................................................ 209

Figure 61. Triggering MCTM with GPTM Update Event ....................................................................... 210

Figure 62. Trigger GPTM and MCTM with the GPTM CH0 Input ..........................................................211

Figure 63. PWM Block Diagram ........................................................................................................... 247

Figure 64. Up-counting Example .......................................................................................................... 248

Figure 65. Down-counting Example ...................................................................................................... 249

Figure 66. Center-aligned Counting Example ....................................................................................... 250

Figure 67. PWM Clock Selection Source .............................................................................................. 251

Figure 68. Trigger Control Block ........................................................................................................... 252

Figure 69. Slave Controller Diagram .................................................................................................... 253

Figure 70. PWM in Restart Mode ......................................................................................................... 253

Figure 71. PWM in Pause Mode ........................................................................................................... 254

Figure 72. PWM in Trigger Mode .......................................................................................................... 254

Figure 73. Master PWMn and Slave PWMm / TMm Connection .......................................................... 255

Figure 74. MTO Selection ..................................................................................................................... 255

Figure 75. Compare Block Diagram ..................................................................................................... 256

Figure 76. Output Stage Block Diagram ............................................................................................... 256

Figure 77. Toggle Mode Channel Output Reference Signal (CHxPRE = 0) ......................................... 257

Figure 78. Toggle Mode Channel Output Reference Signal (CHxPRE = 1) ......................................... 258

Figure 79. PWM Mode Channel Output Reference Signal and Counter in Up-counting Mode ............ 258

Figure 80. PWM Mode Channel Output Reference Signal and Counter in Down-counting Mode ....... 259

List of Figures

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32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Figure 81. PWM Mode Channel Output Reference Signal and Counter in Centre-aligned Mode ........ 259

Figure 82. Update Event Setting Diagram ............................................................................................ 260

Figure 83. Single Pulse Mode ............................................................................................................... 261

Figure 84. Immediate Active Mode Minimum Delay ............................................................................. 262

Figure 85. Asymmetric PWM Mode versus Center-aligned Counting Mode ......................................... 263

Figure 86. Pausing PWM1 using the PWM0 CH0OREF Signal ........................................................... 264

Figure 87. Triggering PWM1 with PWM0 Update Event ....................................................................... 264

Figure 88. Trigger PWM0 and PWM1 with the PWM0 Timer Enable Signal ........................................ 265

Figure 89. BFTM Block Diagram .......................................................................................................... 292

Figure 90. BFTM – Repetitive Mode ..................................................................................................... 293

Figure 91. BFTM – One Shot Mode ...................................................................................................... 294

Figure 92. BFTM – One Shot Mode Counter Updating ....................................................................... 294

Figure 93. MCTM Block Diagram ......................................................................................................... 298

Figure 94. Up-counting Example .......................................................................................................... 300

Figure 95. Down-counting Example ...................................................................................................... 300

Figure 96. Center-aligned Counting Example ....................................................................................... 301

Figure 97. Update Event 1 Dependent Repetition Mechanism Example .............................................. 302

Figure 98. MCTM Clock Selection Source ............................................................................................ 303

Figure 99. Trigger Controller Block ....................................................................................................... 304

Figure 100. Slave Controller Diagram .................................................................................................. 305

Figure 101. MCTM in Restart Mode ..................................................................................................... 305

Figure 102. MCTM in Pause Mode ....................................................................................................... 306

Figure 103. MCTM in Trigger Mode ...................................................................................................... 306

Figure 104. Master MCTMn and Slave GPTM Connection .................................................................. 307

Figure 105. MTO Selection ................................................................................................................... 307

Figure 106. Capture/Compare Block Diagram ...................................................................................... 308

Figure 107. Input Capture Mode ........................................................................................................... 308

Figure 108. PWM Pulse Width Measurement Example ........................................................................ 309

Figure 109. Channel 0 and Channel 1 Input Stages ............................................................................. 310

Figure 110. Channel 2 and Channel 3 Input Stages ............................................................................. 310

Figure 111. TI0 Digital Filter Diagram with N = 2 ...................................................................................311

Figure 112. Output Stage Block Diagram ..............................................................................................311

Figure 113. Toggle Mode Channel Output Reference Signal – CHxPRE = 0 ....................................... 312

Figure 114. Toggle Mode Channel Output Reference Signal – CHxPRE = 1 ....................................... 313

Figure 115. PWM Mode Channel Output Reference Signal and Counter in Up-counting Mode .......... 313

Figure 116. PWM Mode Channel Output Reference Signal and Counter in Down-counting Mode ...... 314

Figure 117. PWM Mode 1 Channel Output Reference Signal and Counter in Centre-aligned Counting

Mode ...................................................................................................................................................... 314

Figure 118. Dead-time Insertion Performed for Complementary Outputs............................................. 315

Figure 119. MCTM Break Signal Bolck Diagram .................................................................................. 316

Figure 120. MT_BRK Pin Digital Filter Diagram with N = 2 .................................................................. 316

List of Figures

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32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Figure 121. Channel 3 Output with a Break Event Occurrence ............................................................ 317

Figure 122. Channel 0 ~2 Complementary Outputs with a Break Event Occurrence........................... 318

Figure 123. Channel 0 ~2 Only One Output Enabled when Break Event Occurs ................................ 319

Figure 124. Hardware Protection When Both CHxO and CHxNO are in Active Condition ................... 320

Figure 125. Update Event 1 Setup Diagram ......................................................................................... 322

Figure 126. CHxE, CHxNE and CHxOM Updated by Update Event 2 ................................................. 323

Figure 127. Update Event 2 Setup Diagram ......................................................................................... 323

Figure 128. Single Pulse Mode ............................................................................................................. 324

Figure 129. Immediate Active Mode Minimum Delay ........................................................................... 325

Figure 130. Asymmetric PWM Mode versus Center-aligned Counting Mode ....................................... 326

Figure 131. Pausing GPTM using the MCTM CH0OREF Signal .......................................................... 327

Figure 132. Triggering GPTM with MCTM Update Event 1 .................................................................. 328

Figure 133. Figure 41 Trigger MCTM and GPTM with the MCTM CH0 Input ....................................... 329

Figure 134. CH1XOR Input as Hall Sensor Interface ........................................................................... 330

Figure 135. RTC Block Diagram ........................................................................................................... 373

Figure 136. Watchdog Timer Block Diagram ....................................................................................... 382

Figure 137. Watchdog Timer Behavior ................................................................................................. 384

Figure 138. I2C Module Block Diagram ................................................................................................. 391

Figure 139. START and STOP Condition ............................................................................................. 393

Figure 140. Data Validity ....................................................................................................................... 393

Figure 141. 7-bit Addressing Mode ....................................................................................................... 394

Figure 142. 10-bit Addressing Write Transmit Mode ............................................................................ 395

Figure 143. 10-bits Addressing Read Receive Mode .......................................................................... 395

Figure 144. I2C Bus Acknowledge ........................................................................................................ 396

Figure 145. Clock Synchronization during Arbitration ........................................................................... 397

Figure 146. Two Master Arbitration Procedure ..................................................................................... 397

Figure 147. Master Transmitter Timing Diagram .................................................................................. 399

Figure 148. Master Receiver Timing Diagram ...................................................................................... 401

Figure 149. Slave Transmitter Timing Diagram .................................................................................... 402

Figure 150. Slave Receiver Timing Diagram ........................................................................................ 403

Figure 151. SCL Timing Diagram .......................................................................................................... 414

Figure 152. SPI Block Diagram ............................................................................................................ 420

Figure 153. SPI Single Byte Transfer Timing Diagram – CPOL = 0, CPHA = 0 .................................... 422

Figure 154. SPI Continuous Data Transfer Timing Diagram – CPOL = 0, CPHA = 0 ........................... 423

Figure 155. SPI Single Byte Transfer Timing Diagram – CPOL = 0, CPHA = 1 .................................... 423

Figure 156. SPI Continuous Transfer Timing Diagram – CPOL = 0, CPHA = 1 .................................... 424

Figure 157. SPI Single Byte Transfer Timing Diagram – CPOL = 1, CPHA = 0 .................................... 424

Figure 158. SPI Continuous Transfer Timing Diagram – CPOL = 1, CPHA = 0 .................................... 425

Figure 159. SPI Single Byte Transfer Timing Diagram – CPOL = 1, CPHA = 1 .................................... 425

Figure 160. SPI Continuous Transfer Timing Diagram – CPOL = 1, CPHA = 1 .................................... 425

Figure 161. SPI Multi-Master Slave Environment ................................................................................. 427

List of Figures

Rev. 1.00 19 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Figure 162. USART Block Diagram ...................................................................................................... 440

Figure 163. USART Serial Data Format ............................................................................................... 442

Figure 164. USART Clock CK_USART and Data Frame Timing .......................................................... 442

Figure 165. Hardware Flow Control between 2 USARTs ...................................................................... 443

Figure 166. USART RTS Flow Control ................................................................................................. 444

Figure 167. USART CTS Flow Control ................................................................................................. 444

Figure 168. IrDA Modulation and Demodulation ................................................................................... 445

Figure 169. USART I/O and IrDA Block Diagram ................................................................................. 446

Figure 170. RS485 Interface and Waveform ........................................................................................ 447

Figure 171. USART Synchronous Transmission Example ................................................................... 448

Figure 172. Figure 11. 8-bit Format USART Synchronous Waveform .................................................. 449

Figure 173. UART Block Diagram ......................................................................................................... 465

Figure 174. UART Serial Data Format .................................................................................................. 466

Figure 175. UART Clock CK_UART and Data Frame Timing ............................................................... 467

Figure 176. Divider Functional Diagram ............................................................................................... 476

Figure 177. CRC Block Diagram .......................................................................................................... 480

Figure 178. CRC Data Bit and Byte Reversal Example ........................................................................ 481

List of Figures

Rev. 1.00 20 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

1 Introduction

Overview

This user manual provides detailed information including how to use the devices, system and
bus architecture, memory organization and peripheral instructions. The target audiences for this
document are software developers, application developers and hardware developers. For more
information regarding pin assignment, package and electrical characteristics, please refer to the
datasheet.

The devices are high performance and low power consumption 32-bit microcontrollers based
around an Arm® Cortex®-M0+ processor core. The Cortex®-M0+ is a next-generation processor
core which is tightly coupled with Nested Vectored Interrupt Controller (NVIC), SysTick timer and
advanced debug support.

The devices operate at a frequency of up to 20 MHz for HT32F50231/50241 to obtain maximum

efciency. It provides up to 64 KB of embedded Flash memory for code / data storage and 8 KB

of embedded SRAM memory for system operation and application program usage. A variety of
peripherals, such as Hardware Divider DIV, ADC, I2C, USART, UART, SPI, BFTM, MCTM,

GPTM, PWM, CRC-16/32, RTC, WDT and SW-DP (Serial Wire Debug Port), etc., are also
implemented in the device series. Several power saving modes provide the exibility for maximum

optimization between wakeup latency and power consumption, which is an especially important
consideration in low power applications.

1 Introduction

The above features ensure that the devices are suitable for use in a wide range of applications,
especially in areas such as white goods application control, power monitors, alarm systems,
consumer products, handheld equipment, data logging applications, motor control and so on.

Rev. 1.00 21 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Features

▄

Core

● 32-bit Arm® Cortex®-M0+ processor core

● Up to 20 MHz operating frequency

● Single-cycle multiplication

● Integrated Nested Vectored Interrupt Controller (NVIC)

● 24-bit SysTick timer

▄

On-chip Memory

● Up to 64 KB on-chip Flash memory for instruction / data and option bytes storage

● 8 KB on-chip SRAM

● Supports multiple booting modes

▄

Flash Memory Controller – FMC

● 32-bit word programming with In System Programming Interface (ISP) and In Application

Programming (IAP)

● Flash protection capability to prevent illegal access

▄

Reset Control Unit – RSTCU

● Supply supervisor: Power On Reset / Power Down Reset (POR / PDR), Brown-out Detector

(BOD) and Programmable Low Voltage Detector (LVD)

▄

Clock Control Unit – CKCU

● External 4 to 20 MHz crystal oscillator

● Internal 20 MHz RC oscillator trimmed to ±2 % accuracy at 25 °C operating temperature

● Internal 32 kHz RC oscillator

● Independent clock divider and gating bits for peripheral clock sources

▄

Power Management – PWRCU

● Flexible power supply:

– VDD power supply: 2.5 V to 5.5 V
– V

power supply for I/O pins: 1.8 V to 5.5 V

DDIO

● Integrated 1.5 V LDO regulator for CPU core, peripherals and memories power supply

● Three power domains: VDD, V

● Three power saving modes: Sleep, Deep-Sleep1, Deep-Sleep2

▄

External Interrupt / Event Controller – EXTI

● Up to 16 EXTI lines with congurable trigger source and type

● All GPIO pins can be selected as EXTI trigger source

● Source trigger type includes high level, low level, negative edge, positive edge or both edge

● Individual interrupt enable, wakeup enable and status bits for each EXTI line

● Software interrupt trigger mode for each EXTI line

● Integrated deglitch lter for short pulse blocking

▄

Analog to Digital Converter – ADC

● 12-bit SAR ADC engine

● Up to 1 Msps conversion rate

● Up to 12 external analog input channels

and 1.5 V

DDIO

1 Introduction

Rev. 1.00 22 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

▄

I/O ports – GPIO

● Up to 40 GPIOs

● Port A, B, C are mapped as 16 external interrupts – EXTI

● Almost I/O pins are congurable output driving current

▄

Motor Control Timer – MCTM

● One 16-bit up, down, up/down auto-reload counter

● 16-bit programmable prescaler allowing counter clock frequency division by any factor

between 1 and 65536

● Input Capture function

● Compare Match Output

● PWM waveform generation with Edge-aligned and Center-aligned Counting Modes

● Single Pulse Mode Output

● Complementary Outputs with programmable dead-time insertion

● Break input to force the timer’s output signals into a reset or xed condition

▄

PWM Generation and Capture Timer – GPTM

● One 16-bit up, down, up / down auto-reload counter

● Up to 4 independent channels for each timer

● 16-bit programmable prescaler allowing the counter clock frequency division by any factor

between 1 and 65536

● Input Capture function

● Compare Match Output

● PWM waveform generation with Edge-aligned and Center-aligned Counting Modes

● Single Pulse Mode Output

● Encoder interface controller with two inputs using quadrature decoder

▄

Pulse Width Modulation – PWM

● One 16-bit up, down, up / down auto-reload counter

● Up to 4 independent channels for each timer

● 16-bit programmable prescaler allowing counter clock frequency division by any factor

between 1 and 65536

● Compare Match Output

● PWM waveform generation with Edge-aligned and Center-aligned Counting Modes

● Single Pulse Mode Output

▄

Basic Function Timer – BFTM

● One 32-bit compare / match count-up counter – No I/O control features

● One shot mode – Counting stops after a match condition

● Repetitive mode – Restart counter after a match condition

▄

Watchdog Timer – WDT

● 12-bit down-counter with a 3-bit pre-scaler

● Reset event for the system

● Programmable watchdog timer window function

● Registers write protection function

▄

Real Time Clock – RTC

● 24-bit up-counter with a programmable prescaler

● Alarm function

● Interrupt and Wake-up event

1 Introduction

Rev. 1.00 23 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

▄

Inter-integrated Circuit – I2C

● Supports both master and slave modes with a frequency of up to 1 MHz

● Provides an arbitration function and clock synchronization

● Supports 7-bit and 10-bit addressing modes and general call addressing

● Supports slave multi-addressing mode with maskable address

▄

Serial Peripheral Interface – SPI

● Supports both master and slave modes

● Frequency of up to (f

● FIFO Depth: 8 levels

● Multi-master and multi-slave operation

▄

Universal Synchronous Asynchronous Receiver Transmitter – USART

● Supports both asynchronous and clocked synchronous serial communication modes

● Asynchronous operating baud-rate clock frequency up to (f

operating clock frequency up to (f

● Full duplex communication

● Fully programmable characteristics of serial communication including: word length, parity bit,

stop bit and bit order

● Error detection: Parity, overrun and frame error

● Auto hardware ow control mode – RTS, CTS

● IrDA SIR encoder and decoder

● RS485 mode with output enable control

● FIFO Depth: 8 × 9 bits for both receiver and transmitter

▄

Universal Asynchronous Receiver Transmitter – UART

● Asynchronous serial communication operating baud rate clock frequency of up to (f

● Capability of full duplex communication

● Fully programmable characteristics of serial communication including: word length, parity bit,

stop bit and bit order

● Error detection: Parity, overrun and frame error

▄

Hardware Divider – DIV

● Signed / unsigned 32-bit divider

● Operation in 8 clock cycles, load in 1 clock cycle

● Division by zero error ag

▄

Cyclic Redundancy Check – CRC

● Support CRC16 polynomial: 0x8005, X16 + X15 + X2 + 1

● Support CCITT CRC16 polynomial: 0x1021, X16 + X12 + X5 + 1

● Support IEEE-802.3 CRC32 polynomial: 0x04C11DB7, X32 + X26 + X23 + X22 + X16 + X12 +

X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1

● Supports 1's complement, byte reverse & bit reverse operation on data and checksum

● Supports byte, half-word & word data size

● Programmable CRC initial seed value

● CRC computation executed in 1 AHB clock cycle for 8-bit data and 4 AHB clock cycles for

32-bit data

▄

Debug Support

● Serial Wire Debug Port – SW-DP

● 4 comparators for hardware breakpoint or code / literal patch

● 2 comparators for hardware watchpoints

/2) MHz for master mode and (f

PCLK

/8) MHz

PCLK

/3) MHz for slave mode

PCLK

/16) MHz and synchronous

PCLK

PCLK

1 Introduction

/16) MHz

Rev. 1.00 24 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

▄

Package and Operation Temperature

● 24/28-pin SSOP, 28-pin SOP, 24/33-pin QFN and 44/48-pin LQFP package types

● Operation temperature range: -40 °C to 85 °C

Device Information

Table 1. Features and Peripheral List

Peripherals HT32F50231 HT32F50241

Main Flash (KB) 32 63

Option Bytes Flash (KB) 1 1

SRAM (KB) 4 8

Timers

Communication

Hardware Divider 1

CRC-16/32 1

EXTI 16

12-bit ADC
Number of Channels

GPIO Up to 40

CPU Frequency Up to 20 MHz

Operating Voltage 2.5 V ~ 5.5 V

Operating Temperature -40 °C ~ 85 °C

Package

1 Introduction

MCTM 1

GPTM 1

PWM 2

BFTM 2

WDT 1

RTC 1

SPI 2

USART 1

UART 2

I2C 2

1

12 Channels

24/28-pin SSOP, 28-pin SOP,
24/33-pin QFN and 44/48-pin LQFP

Rev. 1.00 25 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Block Diagram

TX, RX
RTS/TXE
CTS/SCK

TX, RX

CH0 ~CH2

CH0N ~ CH2N

CH3, BRK

PWMx_CH0

~

PWMx_CH3

AF

AF

AF AF

SWCLK
SWDIO

AF

SW-DP

Cortex®-M0+

Processor

NVIC

Interrupt request

PA ~ PB[15:0], PC[7:0]

I/O Port

GPIO

System

USART

UART0 ~ 1

UART0

PWM0 ~ 1

UART0

Bus Matrix

AFIO

EXTI

MCTM

BOOT

AF

Flash Memory

Interface

FMC

Control Registers

AHB Peripherals

SRAM

Controller

AHB to APB

Bridge

APB

CRC

-16/32

Powered by V

Flash

Memory

CKCU/RSTCU

Control Registers

Divider

SRAM

WDT

SPI0 ~ 1

I2C0 ~ 1

GPTM

BFTM0 ~ 1

DD15

POR

/PDR

HSE

4 ~ 20 MHz

Clock and reset contr ol

LDO

1.5 V

VDD

VSS

AF

XTALIN
XTALOUT

CLDO

1 Introduction

CAP.

BOD

LVD

Powered by V

Power control

HSI

20 MHz

DD

AF

MOSI, MISO
SCK, SEL

AF

SDA
SCL

AF

GT_CH0

~

GT_CH3

AF

ADC_IN0

...

ADC_IN11

VDDA

VSSA

Power supply:

Bus:

Control signal:

Alternate function:

12-bit

SAR ADC

Powered by V

AF

DDA

Powered by V

DD15

ADC

RTC

PWRCU

Powered by V

32 kHz

32,768 Hz

X32KIN

X32KOUT

LSI

LSE

AF

DD

AF

RTCOUT

VDD

VSS

AF

WAKEUP0 ~ 1

nRST

Figure 1. Block Diagram

Rev. 1.00 26 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

2 Document Conventions

Unless otherwise specied, this document uses the conventions which showed as follows.

Table 2. Document Conventions

Notation Example Description

0x 0x5a05

0xnnnn_nnnn 0x2000_0100 32-bit Hexadecimal address or data.

b b0101

NAME [n] ADDR [5]

NAME [m:n] ADDR [11:5]

X b10X1 Don’t care notation which means any value is allowed.

19 18

RW

RO

RC

WC

W0C

WO

Reserved

Word

Half-word Data length of a half-word is 16-bit.

Byte Data length of a byte is 8-bit.

SERDYIE PLLRDYIE

RW 0 RW 0

3 2

HSIRDY HSERDY

RO 1 RO 0

1 0

PDF BAK_PORF

RC 0 RC 1

3 2

SERDYF PLLRDYF

WC 0 WC 0

1 0

Reserved MIF

W0C 0

31 30

DB_CKSRC

WO 0 WO 0

1 0
LLRDY Reserved
RO 0

The number string with a 0x prex indicates a hexadecimal

number.

The number string with a lowercase b prefix indicates a
binary number.

Specific bit of NAME. NAME can be a register or field of
register. For example, ADDR [5] means bit 5 of ADDR register

(eld).

Specific bits of NAME. NAME can be a register or field of
register. For example, ADDR [11:5] means bit 11 to 5 of ADDR

register (eld).

Software can read and write to this bit.

Software can only read this bit. A write operation will have
no effect.

Software can only read this bit. Read operation will clear it
to 0 automatically.

Software can read this bit or clear it by writing 1. Writing a 0
will have no effect.

Software can read this bit or clear it by writing 0. Writing a 1
will have no effect.

Software can only write to this bit. A read operation always
returns 0.

Reserved bit(s) for future use. Data read from these bits

is not well dened and should be treated as random data.

Normally these reserved bits should be set to a 0 value.
Note that reserved bit must be kept at reset value.

Data length of a word is 32-bit.

2 Document Conventions

Rev. 1.00 27 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

3 System Architecture

The system architecture of devices that includes the Arm® Cortex®-M0+ processor, bus architecture
and memory organization will be described in the following sections. The Cortex®-M0+ is a next
generation processor core which offers many new features. Integrated and advanced features make
the Cortex®-M0+ processor suitable for market products that require microcontrollers with high
performance and low power consumption. In brief, The Cortex®-M0+ processor includes AHB-Lite
bus interface. All memory accesses of the Cortex®-M0+ processor are executed on the AHB-Lite
bus according to the different purposes and the target memory spaces. The memory organization

uses a Harvard architecture, pre-dened memory map and up to 4 GB of memory space, making
the system exible and extendable.

Arm® Cortex®-M0+ Processor

The Cortex®-M0+ processor is a very low gate count, highly energy efficient processor that is
intended for microcontroller and deeply embedded applications that require an area optimized,

low-power processor. The processor is based on the ARMv6-M architecture and supports Thumb®

instruction sets; single-cycle I/O port; hardware multiplier and low latency interrupt respond time.
Some system peripherals listed below are also provided by Cortex®-M0+:

3 System Architecture

▄

Internal Bus Matrix connected with AHB-Lite Interface, Single-cycle I/O port and Debug

Accesses Port (DAP)

▄

Nested Vectored Interrupt Controller (NVIC)

▄

Optional Wakeup Interrupt Controller (WIC)

▄

Breakpoint and Watchpoint Unit

▄

Optional Memory Protection Unit (MPU)

▄

Serial Wire debug Port (SW-DP)

▄

Optional Micro Trace Buffer Interface (MTB)

The following gure shows the Cortex®-M0+ processor block diagram. For more information, refer

to the Arm® Cortex®-M0+ Technical Reference Manual.

Rev. 1.00 28 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

®

-M0+ Components

Cortex

Execution Trace Interface

Cortex®-M0+ Processor

Interrupts

Vectored
Interrupt

Controller

‡ Wakeup

Interrupt

Controller (WIC)

‡ Optional Component

Figure 2. Cortex®-M0+ Block Diagram

Bus Architecture

Nested

(NVIC)

Cortex®-M0+

Processor

Core

‡ Memory
Protection

Unit

AHB-Lite Interface

to System

Bus Matrix

Debug

‡ Breakpoint

and

Watchpoint

Unit

‡ Debugger

Interface

‡ Single-cycle

I/O Port

3 System Architecture

‡ Debug

Access Port

(DAP)

‡ Serial Wire or

JTAG Debug Port

The HT32F50231/50241 series devices consist of one master and four slaves in the bus architecture.
The Cortex®-M0+ AHB-Lite bus is the master while the internal SRAM access bus, the internal

Flash memory access bus, the AHB peripherals access bus and the AHB to APB bridges are the
slaves. The single 32-bit AHB-Lite system interface provides simple integration to all system

regions include the internal SRAM region and the peripheral region. All of the master buses are

based on 32-bit Advanced High-performance Bus-Lite (AHB-Lite) protocol. The following gure

shows the bus architecture of the HT32F50231/50241 series.

Rev. 1.00 29 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

GPIO

I/O Port

Cortex®-M0+

Processor

System

NVIC

Interrupt request

Figure 3. Bus Architecture

Bus Matrix

Flash Memory

Interface

FMC

Control Registers

AHB Peripherals

SRAM Controller

AHB to APB

Bridge

Flash Memory

3 System Architecture

CKCU/RSTCU

Control Registers

SRAM

APB IPs

Memory Organization

The Arm® Cortex®-M0+ processor accesses and debug accesses share the single external

interface to external AHB peripheral. The processor accesses take priority over debug accesses.

The maximum address range of the Cortex®-M0+ is 4 GB since it has 32-bit bus address width.
Additionally, a pre-defined memory map is provided by the Cortex®-M0+ processor to reduce
the software complexity of repeated implementation of different device vendors. However, some
regions are used by the Arm® Cortex®-M0+ system peripherals. Refer to the Arm® Cortex®-M0+

Technical Reference Manual for more information. The following gure shows the memory map
of HT32F50231/50241 series of devices, including Code, SRAM, peripheral and other pre-dened

regions.

Rev. 1.00 30 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Memory Map

0xFFFF_FFFF

Peripheral

SRAM

Code

0xE010_0000

0xE000_0000

0x4010_0000

0x4008_0000

0x4000_0000

0x2000_2000

0x2000_0000

0x1FF0_0400

0x1FF0_0000

0x1F00_0800

0x1F00_0000

0x0001_0000

Reserved

Private peripheral bus

Reserved

AHB peripherals

APB peripherals

Reserved

8 KB on-chip SRAM

Reserved

Option byte alias

Reserved

Boot loader

Reserved

512 KB

512 KB

8 KB

1 KB

2 KB

0x400F_FFFF

0x400C_C000
0x400C_A000

0x400B_6000

0x400B_0000

0x4008_C000

0x4008_A000

0x4008_8000

0x4008_2000

0x4008_0000

0x4007_8000

0x4007_7000

0x4007_6000
0x4007_2000

0x4007_1000

0x4006_F000

0x4006_E000

0x4006_B000

0x4006_A000

0x4006_9000

0x4006_8000

0x4004_A000

0x4004_9000

0x4004_8000

0x4004_5000

0x4004_4000

0x4004_2000

0x4004_1000

0x4003_2000

0x4003_1000

0x4002_D000

0x4002_C000

0x4002_5000

0x4002_4000

0x4002_3000

0x4002_2000

0x4001_1000

0x4001_0000

0x4000_5000

0x4000_4000

0x4000_2000

0x4000_1000

0x4000_0000

Reserved

DIV

Reserved

GPIO A ～ C

Reserved

CRC

CKCU & RSTCU

Reserved

FMC

Reserved

BFTM1

BFTM0

Reserved

PWM1

Reserved

GPTM

Reserved

RTC & PWRCU

Reserved

WDT

Reserved

I2C1

I2C0

Reserved

SPI1

Reserved

UART1

Reserved

PWM0

Reserved

MCTM

Reserved

EXTI

Reserved

AFIO

Reserved

ADC

Reserved

SPI0

Reserved

UART0

USART

3 System Architecture

AHB

APB

Up to
64 KB

0x0000_0000

Up to

64 KB on-chip Flash

Figure 4. Memory Map

Rev. 1.00 31 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Table 3. Register Map

Start Address End Address Peripheral Bus

0x4000_0000 0x4000_0FFF USART

0x4000_1000 0x4000_1FFF UART0

0x4000_2000 0x4000_3FFF Reserved

0x4000_4000 0x4000_4FFF SPI0

0x4000_5000 0x4000_FFFF Reserved

0x4001_0000 0x4001_0FFF ADC

0x4001_1000 0x4002_1FFF Reserved

0x4002_2000 0x4002_2FFF AFIO

0x4002_3000 0x4002_3FFF Reserved

0x4002_4000 0x4002_4FFF EXTI

0x4002_5000 0x4002_BFFF Reserved

0x4002_C000 0x4002_CFFF MCTM

0x4002_D000 0x4003_0FFF Reserved

0x4003_1000 0x4003_1FFF PWM0

0x4003_2000 0x4004_0FFF Reserved

0x4004_1000 0x4004_1FFF UART1

0x4004_2000 0x4004_3FFF Reserved

0x4004_4000 0x4004_4FFF SPI1

0x4004_5000 0x4004_7FFF Reserved

0x4004_8000 0x4004_8FFF I2C0

0x4004_9000 0x4004_9FFF I2C1

0x4004_A000 0x4006_7FFF Reserved

0x4006_8000 0x4006_8FFF WDT

0x4006_9000 0x4006_9FFF Reserved

0x4006_A000 0x4006_AFFF RTC & PWRCU

0x4006_B000 0x4006_DFFF Reserved

0x4006_E000 0x4006_EFFF GPTM

0x4006_F000 0x4007_0FFF Reserved

0x4007_1000 0x4007_1FFF PWM1

0x4007_2000 0x4007_5FFF Reserved

0x4007_6000 0x4007_6FFF BFTM0

0x4007_7000 0x4007_7FFF BFTM1

0x4007_8000 0x4007_FFFF Reserved

0x4008_0000 0x4008_1FFF FMC

0x4008_2000 0x4008_7FFF Reserved

0x4008_8000 0x4008_9FFF CKCU & RSTCU

0x4008_A000 0x4008_BFFF CRC

0x4008_C000 0x400A_FFFF Reserved

0x400B_0000 0x400B_1FFF GPIOA

0x400B_2000 0x400B_3FFF GPIOB

0x400B_4000 0x400B_5FFF GPIOC

0x400B_6000 0x400C_9FFF Reserved

0x400C_A000 0x400C_BFFF DIV

0x400C_C000 0x400F_FFFF Reserved

3 System Architecture

APB

AHB

Rev. 1.00 32 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Embedded Flash Memory

The HT32F50231/50241 series provide up to 64 KB on-chip Flash memory which is located at

address 0x0000_0000. It supports byte, half-word and word access operations. Note that the
Flash memory only supports read operations for the bus access. Any write operations to the Flash

memory will cause a bus fault exception. The Flash memory has up to capacity of 64 pages. Each
page has a memory capacity of 1 KB and can be erased independently. A 32-bit programming
interface provides the capability of changing bits from 1 to 0. A data storage or rmware upgrade

can be implemented using several methods such as In System Programming (ISP), In Application
Programming (IAP) or In Circuit Programming (ICP). For more information, refer to the Flash
Memory Controller section.

Embedded SRAM Memory

The HT32F50231/50241 series contain up to 8 KB on-chip SRAM which is located at address

0x2000_0000. It support byte, half-word and word access operations.

AHB Peripherals

The address of the AHB peripherals ranges from 0x4008_0000 to 0x400F_FFFF. Some peripherals

such as Clock Control Unit, Reset Control Unit and Flash Memory Controller are connected to the

AHB bus directly. The AHB peripherals clocks are always enabled after a system reset. Access to
registers for these peripherals can be achieved directly via the AHB bus. Note that all peripheral
registers in the AHB bus support only word access.

3 System Architecture

APB Peripherals

The address of APB peripherals ranges from 0x4000_0000 to 0x4007_FFFF. An APB to AHB
Bridge provides access capability between the CPU and the APB peripherals. Additionally, the
APB peripheral clocks are disabled after a system reset. Software must enable the peripheral clock
by setting up the APBCCRn register in the Clock Control Unit before accessing the corresponding
peripheral register. Note that the APB to AHB Bridge will duplicate the half-word or byte data to
word width when a half-word or byte access is performed on the APB peripheral registers. In other
words, the access result of a half-word or byte access on the APB peripheral register will vary

depending on the data bit width of the access operation on the peripheral registers.

Rev. 1.00 33 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

4 Flash Memory Controller (FMC)

Introduction

The Flash Memory Controller, FMC, provides functions of flash operation and pre-fetch buffer
for the embedded on-chip Flash memory. Figure below shows the block diagram of FMC which
includes programming interface, control register, pre-fetch buffer and access interface. Since the
access speed of Flash memory is slower than the CPU, a wide access interface with pre-fetch buffer
is provided to the Flash memory in order to reduce the CPU wait state, which will cause instruction
gaps. The functions of word programming / page erase are also provided for instruction / data
storage of Flash memory.

4 Flash Memory Controller (FMC)

Flash Memory Controller

AHB

Peripheral

Bus

System Bus

Control Register

Pre-fetch Buffer

Figure 5. Flash Memory Controller Block Diagram

Features

▄

Up to 64 KB of on-chip Flash memory for storing instruction / data and option bytes

● 64 KB (instruction / data + Option Byte)

● 32 KB (instruction / data + Option Byte)

▄

Page size of 1 KB, totally up to 64 pages depending on the main Flash size

▄

Wide access interface with pre-fetch buffer to reduce instruction gaps

▄

Page erase and mass erase capability

▄

32-bit word programming

▄

Interrupt capability when ready or error occurs

▄

Flash read protection to prevent illegal code / data access

▄

Page erase / program protection to prevent unexpected operation

Wait State

Control

Addressing

Data

Programming

Control

Flash

Information

Block

Main Flash

Memory

Rev. 1.00 34 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Functional Descriptions

Flash Memory Map

The following figure is the Flash memory map of the system. The address ranges from

0x0000_0000 to 0x1FFF_FFFF (0.5 GB). The address from 0x1F00_0000 to 0x1F00_07FF is
mapped to Boot Loader Block (2 KB). Besides, address 0x1FF0_0000 to 0x1FF0_03FF is the alias
of Option Byte block (1 KB) which locates at the last page of main Flash physically. The memory

mapping on system view is shown as below.

0x1FFF_FFFF

0x1FF0_0400

0x1FF0_0000

0x1F00_0800

Reserved

Option Byte

Reserved

4 Flash Memory Controller (FMC)

1 KB

Figure 6. Flash Memory Map

0x1F00_0000

0x0000_0000

Boot Loader Block

Reserved

Main Flash Block

User Application

2 KB

63 KB

or

32 KB

Rev. 1.00 35 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Flash Memory Architecture

The Flash memory consists of up to 64 KB main Flash with 1 KB per page and 2 KB Information
Block for Boot Loader. The main Flash memory contains totally 64 pages (or 32 pages for 32 KB

device) which can be erased individually. The following table shows the base address, size and
protection setting bit of each page.

Table 4. Flash Memory and Option Byte

Block Name Address Page Protection Bit Size

Page 0 0x0000_0000 ~ 0x0000_03FF OB_PP [0] 1 KB

Page 1 0x0000_0400 ~ 0x0000_07FF OB_PP [1] 1 KB

Page 2 0x0000_0800 ~ 0x0000_0BFF OB_PP [2] 1 KB

Page 3 0x0000_0C00 ~ 0x0000_0FFF OB_PP [3] 1 KB

Main Flash
Block

Information Block Boot Loader 0x1F00_0000 ~ 0x1F00_07FF NA 2 KB

Notes:

1. Information Block stores boot loader – This block can not be programmed or erased by user.

2. Option Byte is always located at last page of main Flash block.

:
:

Page 60 0x0000_F000 ~ 0x0000_F3FF OB_PP [60] 1 KB

Page 61 0x0000_F400 ~ 0x0000_F7FF OB_PP [61] 1 KB

Page 62 0x0000_F800 ~ 0x0000_FBFF OB_PP [62] 1 KB

Page 63
(Option Byte)

:
:

Physical: 0x0000_FC00 ~ 0x0000_FFFF
Alias: 0x1FF0_0000 ~ 0x1FF0_03FF

:
:

OB_CP [1] 1 KB

:
:

4 Flash Memory Controller (FMC)

Rev. 1.00 36 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Booting Conguration

The system provides two kinds of booting mode which can be selected through the BOOT pin. The
value of BOOT pin is sampled during the power-on reset or system reset. Once the logic value is
decided, the rst 4 words of vector will be remapped to the corresponding source according to the

booting mode. The booting mode is shown in the following table.

Table 5. Booting Modes

Booting Mode Selection Pin

BOOT

0 Boot Loader The source of Vector is Boot Loader

1 Main Flash The source of Vector is main Flash

The Flash Vector Mapping Control Register, VMCR, is provided to change the setting of the vector

remapping temporarily after the chip reset. The reset value of VMCR is determined by the BOOT

pin status which will be sampled during the reset duration.

Mode Descriptions

4 Flash Memory Controller (FMC)

Boot Setting

0xC

Hard Fault Handler

0x8

0x4

NMI Handler

Program Counter

Initial Stack Point0x0

Figure 7. Vector Remapping

1 : Main Flash 0 : Boot Loader

+ 0xC

+ 0x8

+ 0x4

0x0000_0000

+ 0xC

+ 0x8

+ 0x4

0x1F00_0000

Rev. 1.00 37 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Page Erase

The FMC provides a page erase function which is used to reset partial content of Flash memory.
Any page can be erased independently without affecting others. The following steps show the
access sequence of the register for page erase.

▄

Check the OPCR register to conrm that no Flash memory operation is in progress (OPM [3:0]
equals to 0xE or 0x6). Otherwise, wait until the previous operation has been nished.

▄

Write the page address to TADR register.

▄

Write the page erase command to OCMR register (Set CMD [3:0] = 0x8).

▄

Commit page erase command to FMC by setting OPCR register (Set OPM [3:0] = 0xA).

▄

Wait until all the operations have been completed by checking the value of OPCR register (OPM

[3:0] equals to 0xE).

▄

Read and verify the page if required.

Note that a correct target page address must be conrmed. The software may run out of control

if the target erase page is being used to fetch code or access data. The FMC will not provide
any notification when this happens. Additionally, the page erase operation will be ignored on
the protected pages. When this occurs, the OREF bit will be set by the FMC and then a Flash
Operation Error interrupt will be generated if the OREIEN bit in the OIER register is set. The
software can check the PPEF bit in the OISR register to detect this condition in the interrupt

handler. The following gure shows the page erase operation ow.

4 Flash Memory Controller (FMC)

No

No

Start

Is OPM equal to 0xE or 0x6 ?

Yes

Set TADR, OCMR

Commit command

by setting OPCR

Is OPM equal to 0xE ?

Yes

Finish

Figure 8. Page Erase Operation Flowchart

Rev. 1.00 38 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Mass Erase

The FMC provides a mass erase function which is used for resetting all the main Flash memory
content. The following steps show the register access sequence for mass erase operation.

▄

Check OPCR register to confirm that no Flash memory operation is in progress (OPM [3:0]
equals to 0xE or 0x6). Otherwise, wait until the previous operation has been nished.

▄

Write mass erase command to OCMR register (Set CMD [3:0] = 0xA).

▄

Commit mass erase command to FMC by setting OPCR register (Set OPM [3:0] = 0xA).

▄

Wait until all operations have been nished by checking the value of OPCR register (OPM [3:0]

equals to 0xE).

▄

Read and verify the Flash memory if required.

Since all Flash data will be reset as 0xFFFF_FFFF, the mass erase operation can be implemented
by the program that runs in the SRAM or by the debugging tool that accesses FMC registers
directly. The software function that is executed on the Flash memory shall not trigger a mass erase

operation. The following gure displays the mass erase operation ow.

4 Flash Memory Controller (FMC)

No

No

Start

Is OPM equal to 0xE or 0x6 ?

Yes

Set OCMR = 0xA

Commit command

by setting OPCR

Is OPM equal to 0xE ?

Yes

Finish

Figure 9. Mass Erase Operation Flowchart

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32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Word Programming

The FMC provides a 32 bits word programming function which is used for modifying the Flash
memory content. The following steps show the sequence of register access for word programming.

▄

Check OPCR register to confirm that no Flash memory operation is in progress (OPM [3:0]
equals to 0xE or 0x6). Otherwise, wait until the previous operation has been nished.

▄

Write word address to TADR register. Write data to WRDR register.

▄

Write word program command to OCMR register (Set CMD [3:0] = 0x4).

▄

Commit word program command to FMC by setting OPCR register (Set OPM [3:0] = 0xA).

▄

Wait until all operations have been nished by checking the value of OPCR register (OPM [3:0]

equals to 0xE).

▄

Read and verify the Flash memory if required.

Note that the word programming operation can not be successively applied to the same address
twice. Successive word programming operation to the same address must be separated by a page

erase operation. Besides, the word program will be ignored on protected pages. When this occurs,

the OREF bit will be set by the FMC and then a Flash Operation Error interrupt will be generated if
the OREIEN bit in the OIER register is set. Software can check the PPEF bit in the OISR register to

detect this condition in the interrupt handler. The following gure displays the word programming
operation ow.

4 Flash Memory Controller (FMC)

No

No

Start

Is OPM equal to 0xE or 0x6 ?

Yes

Set TADR, WRDR

and OCMR

Commit command

by setting OPCR

Is OPM equal to 0xE ?

Yes

Finish

Figure 10. Word Programming Operation Flowchart

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32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Option Byte Description

The Option Byte can be treated as an independent Flash memory of which base address is
0x1FF0_0000. The following table shows the function description and Option Byte memory map.

Table 6. Option Byte Memory Map

Option Byte Offset Description Reset Value

Option Byte Base Address = 0x1FF0_0000

0x000

OB_PP

OB_CP 0x010

OB_CK 0x020

0x004
0x008
0x00C

Flash Page Erase / Program Protection (n = 0 ~ 127)
OB_PP [n] (n = 0 ~ 62)

0: Flash Page n Erase / Program Protection is enabled
1: Flash Page n Erase / Program Protection is disabled

OB_PP [n] (n = 63 ~ 127)

Reserved

Flash Security Protection
OB_CP [0]

0: Flash Security protection is enabled
1: Flash Security protection is disabled

Option Byte Protection
OB_CP [1]

0: Option Byte protection is enabled
1: Option Byte protection is disabled

OB_CP [31:2]

Reserved

Flash Option Byte Checksum
OB_CK [31:0]
OB_CK should be set as the content value sum of 5
registers which offset address is from 0x000 to 0x010 in
Option Byte (0x000 + 0x004 + 0x008 + 0x00C + 0x010)
when the OB_PP or OB_CP register’s content is not equal
to 0xFFFF_FFFF. Otherwise, both page erase / program
protection and security protection will be enabled.

4 Flash Memory Controller (FMC)

0xFFFF_FFFF
0xFFFF_FFFF
0xFFFF_FFFF
0xFFFF_FFFF

0xFFFF_FFFF

0xFFFF_FFFF

Rev. 1.00 41 of 486 July 31, 2018

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HT32F50231/HT32F50241

Page Erase / Program Protection

FMC provides functions of page erase / program protection to prevent unexpected operation of Flash

memory. The page erase (CMD [3:0] = 0x8 in the OCMR register) or word programming (CMD [3:0]
= 0x4) command will not be accepted by FMC on the protected pages. When the page erase or word

programming command aimed at the protected pages is sent to the FMC, the PPEF bit in the OISR
register will then be set by the FMC and the Flash operation error interrupt will be triggered to inform
the CPU if the OREIEN bit in the OIER register is set. The page protection function can be enabled for

each page independently by setting the OB_PP registers of the Option Byte. The following table shows

the access permission of the main Flash page when the page protection is enabled.

Table 7. Access Permission of Protected Main Flash Page

Operation

Read O O

Program X X

Page Erase X X

Mass Erase O O

Mode

4 Flash Memory Controller (FMC)

ISP / IAP ICP / Debug Mode

Notes:

1. Note that the setting of write protection is based on page. The above access permission only
affects the pages that enable protection function. Other pages are not affected.

2. Main Flash page protection is configured by OB_PP [127:0]. Option Byte is physically

located at the last page of main Flash Option Byte page protection is congured by the

OB_CP [1] bit.

3. The page erase on Option Byte area can disable the page protection of main Flash.

4. The page protection of Option Byte can only be disabled by a mass erase operation.

The following steps show the register access sequence for page erase / program protection procedure.

▄

Check OPCR register to confirm that no Flash memory operation is in progress (OPM [3:0]
equals to 0xE or 0x6). Otherwise, wait until the previous operation has been nished.

▄

Write OB_PP address to TADR register (TADR = 0x1FF0_0000).

▄

Write the data, which indicates the protection function of corresponding page is enabled or
disabled, to the WRDR register (0: Enabled, 1: Disabled).

▄

Write word programming command to the OCMR register (Set CMD [3:0] = 0x4).

▄

Commit word programming command to FMC by setting the OPCR register (Set OPM [3:0] = 0xA).

▄

Wait until all operations have been nished by checking the value of the OPCR register (OPM [3:0]

equals to 0xE).

▄

Read and verify the Option Byte if required.

▄

The OB_CK eld in the Option Byte must be updated according to the Option Byte checksum rule.

▄

Apply a system reset to active the new OB_PP setting.

Rev. 1.00 42 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Security Protection

FMC provides a Security protection function to prevent illegal code / data access of the Flash
memory. This function is useful for protecting the software / firmware from illegal users. The

function is activated by setting the Option Byte OB_CP [0] bit. Once the function has been

enabled, all the main Flash data access through ICP / Debug mode, programming and page erase

will not be allowed except the user’s application. But the mass erase operation will still be accepted

by FMC in order to disable this function. The following table shows the access permission of Flash
memory when the security protection is enabled.

Table 8. Access Permission When Security Protection is Enabled

Operation

Read O X (read as 0)

Program O

Page Erase O

Mass Erase O O

Notes:

1. User application means the software that is executed or booted from main Flash memory
with the JTAG / SW debugger being disconnected. However, the Option Byte area and
page 0 are still under protection where the Program / Page Erase operations are not
accepted.

2. The Mass erase operation can erase the Option Byte area and disable the security
protection.

Mode

User Application

(Note 1)

(Note 1)

(Note 1)

4 Flash Memory Controller (FMC)

ICP / Debug Mode

X

X

The following steps show the register access sequence for Security protection procedure.

▄

Check the OPCR register to conrm that no Flash memory operation is in progress (OPM [3:0]
equals to 0xE or 0x6). Otherwise, wait until the previous operation has been nished.

▄

Write OB_CP address to the TADR register (TADR = 0x1FF0_0010).

▄

Write the WRDR register to set the OB_CP [0] as 0.

▄

Write word programming command to the OCMR register (Set CMD [3:0] = 0x4).

▄

Commit word programming command to FMC by setting the OPCR register (Set OPM [3:0] = 0xA).

▄

Wait until all operations have been nished by checking the value of the OPCR register (OPM [3:0]

equals to 0xE).

▄

Read and verify the Option Byte if required.

▄

The OB_CK eld in the Option Byte must be updated according to the Option Byte checksum rule.

▄

Apply a system reset to active the new OB_CP setting.

Rev. 1.00 43 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Register Map

The following table shows the FMC registers and reset values.

Table 9. FMC Register Map

Register Offset Description Reset Value

TADR 0x000 Flash Target Address Register 0x0000_0000

WRDR 0x004 Flash Write Data Register 0x0000_0000

OCMR 0x00C Flash Operation Command Register 0x0000_0000

OPCR 0x010 Flash Operation Control Register 0x0000_000C

OIER 0x014 Flash Operation Interrupt Enable Register 0x0000_0000

OISR 0x018 Flash Operation Interrupt and Status Register 0x0001_0000

0x020

PPSR

CPSR 0x030 Flash Security Protection Status Register 0x0000_000X

VMCR 0x100 Flash Vector Mapping Control Register 0x0000_000X

MDID 0x180 Flash Manufacturer and Device ID Register 0x0376_XXXX

PNSR 0x184 Flash Page Number Status Register 0x0000_00XX

PSSR 0x188 Flash Page Size Status Register 0x0000_0400

DIDR 0x18C Device ID Register 0x000X_XXXX

CIDR0 0x310 Custom ID Register 0 0xXXXX_XXXX

CIDR1 0x314 Custom ID Register 1 0xXXXX_XXXX

CIDR2 0x318 Custom ID Register 2 0xXXXX_XXXX

CIDR3 0x31C Custom ID Register 3 0xXXXX_XXXX

0x024
0x028
0x02C

Flash Page Erase / Program Protection Status Register

4 Flash Memory Controller (FMC)

0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX
0xXXXX_XXXX

Note:

“X” means various reset values which depend on the Device, Flash value, option byte value or

power on reset setting.

Rev. 1.00 44 of 486 July 31, 2018

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HT32F50231/HT32F50241

Register Descriptions

Flash Target Address Register – TADR

This register species the target address of the page erase and word programming operation.

Offset: 0x000

Reset value: 0x0000_0000

31 30 29 28 27 26 25 24

TADB

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

23 22 21 20 19 18 17 16

TADB

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

15 14 13 12 11 10 9 8

TADB

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

7 6 5 4 3 2 1 0

TADB

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

Bits Field Descriptions

[31:0] TADB Flash Target Address Bits

For programming operations, the TADR register species the address where the data

is written. Since the programming length is 32 bits, the TADR shall be set as word­aligned (4 bytes). The TADB [1:0] will be ignored during programming operations. For
page erase operations, the TADR register contains the page address which is going
to be erased. Since the page size is 1 KB, the TADB [9:0] will be ignored in order
to limit the target address as 1 Kbyte-aligned. For 64 KB main Flash addressing,
TADB [31:16] should be zero and TADB [31:15] should be zero for 32 KB. Address

from 0x1FF0_0000 to 0x1FF0_03FF is the 1 KB Option Byte. This eld for available

Flash address, it must be under 0x1FFF_FFFF. Otherwise, the Invalid Target Address
interrupt will be occurred if the corresponding interrupt enable bit is set.

4 Flash Memory Controller (FMC)

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32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Flash Write Data Register – WRDR

This register species the data to be written for programming operation.

Offset: 0x004

Reset value: 0x0000_0000

31 30 29 28 27 26 25 24

WRDB

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

23 22 21 20 19 18 17 16

WRDB

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

15 14 13 12 11 10 9 8

WRDB

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

7 6 5 4 3 2 1 0

WRDB

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

4 Flash Memory Controller (FMC)

Bits Field Descriptions

[31:0] WRDB Flash Write Data Bits

The data value for programming operation.

Rev. 1.00 46 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Flash Operation Command Register – OCMR

This register is used to specify the Flash operation commands that include word programming, page erase and
mass erase.

Offset: 0x00C

Reset value: 0x0000_0000

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved CMD

Type/Reset RW 0 RW 0 RW 0 RW 0

Bits Field Descriptions

[3:0] CMD Flash Operation Command

The following table shows definitions of CMD [3:0] bits which specify the Flash
operation. If an invalid command is set and the IOCMIEN bit is set to 1, an Invalid
Operation Command interrupt will occur.

CMD [3:0] Description

0x0 Idle (default)

0x4 Word programming

0x8 Page erase

0xA Mass erase

Others Reserved

4 Flash Memory Controller (FMC)

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32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Flash Operation Control Register – OPCR

This register is used for controlling the command commitment and checking the status of the FMC operations.

Offset: 0x010

Reset value: 0x0000_000C

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved OPM Reserved

Type/Reset RW 0 RW 1 RW 1 RW 0

4 Flash Memory Controller (FMC)

Bits Field Descriptions

[4:1] OPM Operation Mode

The following table shows the operation modes of the FMC. Users can commit
command which is set by the OCMR register to the FMC according to the address
alias setting in the TADR register. The contents of TADR, WRDR and OCMR
registers shall be prepared before setting this register. After all the operation has

been nished, the OPM eld will be set as 0xE or 0xF by the FMC hardware. The
Idle mode can be set when all the operations have been nished for power saving.

Note that the operation status should be checked before the next action is applied to
the FMC. The contents of TADR, WRDR, OCMR and OPCR registers should not be

changed until the previous operation has been nished.

OPM [3:0] Description

0x6 Idle (default)

0xA Commit command to main Flash

0xE All operation nished on main Flash

Others Reserved

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32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Flash Operation Interrupt Enable Register – OIER

This register is used to enable or disable interrupt function of FMC. The FMC will generate interrupts when the
corresponding interrupt enable bit is set and the interrupt condition occurs.

Offset: 0x014

Reset value: 0x0000_0000

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved OREIEN IOCMIEN OBEIEN ITADIEN ORFIEN

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0

Bits Field Descriptions

[4] OREIEN Operation Error Interrupt Enable

0: Operation error interrupt is disabled
1: Operation error interrupt is enabled

[3] IOCMIEN Invalid Operation Command Interrupt Enable

0: Invalid Operation Command interrupt is disabled
1: Invalid Operation Command interrupt is enabled

[2] OBEIEN Option Byte Check Sum Error Interrupt Enable

0: Option Byte Check Sum Error interrupt is disabled
1: Option Byte Check Sum Error interrupt is enabled

[1] ITADIEN Invalid Target Address Interrupt Enable

0: Invalid Target Address interrupt is disabled
1: Invalid Target Address interrupt is enabled

[0] ORFIEN Operation Finished Interrupt Enable

0: Operation Finish interrupt is disabled
1: Operation Finish interrupt is enabled

4 Flash Memory Controller (FMC)

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HT32F50231/HT32F50241

Flash Operation Interrupt and Status Register – OISR

This register indicates the status of the FMC interrupt to check if an operation has been nished or an error

occurs. The status bits, bit [4:0], if set high, are available to trigger the interrupt when the corresponding enable
bits in the OIER register are set high.

Offset: 0x018

Reset value: 0x0001_0000

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved PPEF RORFF

Type/Reset RO 0 RO 1

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved OREF IOCMF OBEF ITADF ORFF

Type/Reset WC 0 WC 0 WC 0 WC 0 WC 0

Bits Field Descriptions

[17] PPEF Page Erase / Program Protected Error Flag

0: Page Erase / Program Protected Error does not occur
1: Operation error due to an invalid erase / program operation being applied to

a protected page

This bit is reset by hardware once a new ash operation command is committed.

[16] RORFF Raw Operation Finished Flag

0: The last ash operation command is not nished
1: The last ash operation command is nished

The RORFF bit is directly connected to the Flash memory for debugging purpose.

[4] OREF Operation Error Flag

0: No ash operation error occurred
1: The last ash operation is failed

This bit will be set when any Flash operation error, such as invalid command,
program error and erase error, etc., occurs. The ORE interrupt occurs if the
OREIEN bit in the OIER register is set. Reset this bit by writing 1.

[3] IOCMF Invalid Operation Command Flag

0: No invalid ash operation command was set
1: An invalid ash operation command has been written into the OCMR register

This bit will be set high when an invalid ash operation command has been written

into the OCMR register. The IOCM interrupt will occur if the IOCMIEN bit in the
OIER register is set. Reset this bit by writing 1.

4 Flash Memory Controller (FMC)

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HT32F50231/HT32F50241

Bits Field Descriptions

[2] OBEF Option Byte Check Sum Error Flag

0: Check sum of Option Byte is correct
1: Check sum of Option Byte is incorrect

This bit will be set high when the Option Byte checksum is incorrect. The OBE
interrupt will occur if the OBEIEN bit in the OIER register is set. This bit is cleared
to 0 by software writing 1 into it. However, the Option Byte Checksum Error Flag
can not be cleared by software until the interrupt condition is cleared, which
means that the Option Byte check sum value has to be correctly modified or
the corresponding interrupt control is disabled. Otherwise, the interrupt will be
continually generated.

[1] ITADF Invalid Target Address Flag

0: The target address is valid
1: The target address is invalid

The data in the TADR eld must be in the range from 0x0000_0000 to 0x1FFF_

FFFF. Otherwise, this bit will be set high and an ITAD interrupt will be generated if
the ITADIEN bit in the OIER register is set. Reset this bit by writing 1.

[0] ORFF Operation Finished Flag

0: Operation is not nished
1: Last ash operation command is nished

This bit will be set high when the last ash operation is nished. The ORF interrupt

will be generated if the ORFIEN bit in the OIER register is set. Reset this bit by
writing 1.

4 Flash Memory Controller (FMC)

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32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Flash Page Erase / Program Protection Status Register – PPSR

This register indicates the status of Flash page erase / program protection.

Offset: 0x020 (0) ~ 0x02C (3)

Reset value: 0xXXXX_XXXX

31 30 29 28 27 26 25 24

PPSBn

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

23 22 21 20 19 18 17 16

PPSBn

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

15 14 13 12 11 10 9 8

PPSBn

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

7 6 5 4 3 2 1 0

PPSBn

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

4 Flash Memory Controller (FMC)

Bits Field Descriptions

[127:0] PPSBn Page Erase / Program Protection Status Bits (n = 0 ~ 127)

PPSB[n] = OB_PP[n]

0: The corresponding page is protected
1: The corresponding page is not protected

The content of this register is not dynamically updated and will only be reloaded
from the Option Byte when any kind of reset occurs. The erase or program function

of specic pages is not allowed when the corresponding bits of the PPSR registers

are reset. The reset value of PPSR [127:0] is determined by the Option Byte OB_
PP [127:0]. Since the maximum page number of the main flash is various and
dependent on the chip specification. Therefore, the every page erase / program
protection status bit may protect one or two pages and dependent on the chip

specication. The other remained bits of OB_PP and PPSR registers are reserved.

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32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Flash Security Protection Status Register – CPSR

This register indicates the status of the Flash Memory Security protection. The content of this register is not
dynamically updated and will only be reloaded by the Option Byte loader, which is active when any kind of reset
occurs.

Offset: 0x030

Reset value: 0x0000_000X

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved OBPSB CPSB

Type/Reset RO X RO X

Bits Field Descriptions

[1] OBPSB Option Byte Page Erase / Program Protection Status Bit

0: The Option Byte page is protected
1: The Option Byte page is not protected

The reset value of OBPSB is determined by the Option Byte, OB_CP [1].

[0] CPSB Flash Security Protection Status Bit

0: Flash Security protection is enabled
1: Flash Security protection is not enabled

The reset value of CPSB is determined by the Option Byte, OB_CP [0].

4 Flash Memory Controller (FMC)

Rev. 1.00 53 of 486 July 31, 2018

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HT32F50231/HT32F50241

Flash Vector Mapping Control Register – VMCR

This register is used to control the vector mapping. The reset value of the VMCR register is determined by the
external booting pin, BOOT, during the power-on reset period.

Offset: 0x100

Reset value: 0x0000_000X

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved VMCB Reserved

Type/Reset RW X

Bits Field Descriptions

[1] VMCB Vector Mapping Control Bit

The VMCB bits is used to control the mapping source of rst 4-word vector (address

0x0 ~ 0xC). The following table shows the vector mapping setting.

BOOT VMCB Descriptions

Low 0

High 1

Boot Loader mode
The vector mapping source is the boot loader area.

Main Flash mode
The vector mapping source is the main Flash area.

4 Flash Memory Controller (FMC)

The reset value of VMCR is determined by the pins status of BOOT during power-on
reset and system reset. The vector mapping setting can be changed temporarily by
setting the VMCB bit when the application is running.

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32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Flash Manufacturer and Device ID Register – MDID

This register species the manufacture ID and device part number information which can be used as the product

identity.

Offset: 0x180

Reset value: 0x0376_XXXX

31 30 29 28 27 26 25 24

MFID

Type/Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1

23 22 21 20 19 18 17 16

MFID

Type/Reset RO 0 RO 1 RO 1 RO 1 RO 0 RO 1 RO 1 RO 0

15 14 13 12 11 10 9 8

ChipID

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

7 6 5 4 3 2 1 0

ChipID

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

Bits Field Descriptions

[31:16] MFID Manufacturer ID

Read as 0x0376

[15:0] ChipID Chip ID

Read the last 4 digital codes of the MCU device part number.

4 Flash Memory Controller (FMC)

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HT32F50231/HT32F50241

Flash Page Number Status Register – PNSR

This register species the page number of Flash memory.

Offset: 0x184

Reset value: 0x0000_00XX

31 30 29 28 27 26 25 24

PNSB

Type/Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0

23 22 21 20 19 18 17 16

PNSB

Type/Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0

15 14 13 12 11 10 9 8

PNSB

Type/Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0

7 6 5 4 3 2 1 0

PNSB

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

4 Flash Memory Controller (FMC)

Bits Field Descriptions

[31:0] PNSB Flash Page Number Status Bits

0x0000_0010: Totally 16 pages for the on-chip Flash memory device
0x0000_0020: Totally 32 pages for the on-chip Flash memory device
0x0000_0040: Totally 64 pages for the on-chip Flash memory device
0x0000_0080: Totally 128 pages for the on-chip Flash memory device
0x0000_00FF: Totally 255 pages for the on-chip Flash memory device

Rev. 1.00 56 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Flash Page Size Status Register – PSSR

This register species the page size in bytes.

Offset: 0x188

Reset value: 0x0000_0400

31 30 29 28 27 26 25 24

PSSB

Type/Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0

23 22 21 20 19 18 17 16

PSSB

Type/Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0

15 14 13 12 11 10 9 8

PSSB

Type/Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 0

7 6 5 4 3 2 1 0

PSSB

Type/Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0

4 Flash Memory Controller (FMC)

Bits Field Descriptions

[31:0] PSSB Status Bits of Flash Page Size

0x200: That means the page size is 512 Byte per page
0x400: That means the page size is 1 KB per page
0x800: That means the page size is 2 KB per page

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HT32F50231/HT32F50241

Device ID Register – DIDR

This register species the device part number information which can be used as the product identity.

Offset: 0x18C

Reset value: 0x000X_XXXX

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved ChipID

Type/Reset RO X RO X RO X RO X

15 14 13 12 11 10 9 8

ChipID

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

7 6 5 4 3 2 1 0

ChipID

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

4 Flash Memory Controller (FMC)

Bits Field Descriptions

[19:0] ChipID Chip ID

Read the complete 5 digital codes of the MCU device part number.

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HT32F50231/HT32F50241

Custom ID Register n – CIDRn, n = 0 ~ 3

This register species the custom ID information which can be used as the custom identity.

Offset: 0x310 (0) ~ 0x31C (3)

Reset value: Various depending on Flash Manufacture Privilege Information Block.

31 30 29 28 27 26 25 24

CID

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

23 22 21 20 19 18 17 16

CID

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

15 14 13 12 11 10 9 8

CID

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

7 6 5 4 3 2 1 0

CID

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

4 Flash Memory Controller (FMC)

Bits Field Descriptions

[31:0] CIDn Custom ID

Read as the CIDn[31:0] (n = 0 ~ 3) field in the Custom ID registers in Flash
Manufacture Privilege Block.

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HT32F50231/HT32F50241

5 Power Control Unit (PWRCU)

Introduction

The power consumption can be regarded as one of the most important issues for many embedded
system applications. Accordingly the Power Control Unit, PWRCU, provides many types of power
saving modes such as Sleep, Deep-Sleep1 and Deep-Sleep2 modes. These modes reduce the

power consumption and allow the application to achieve the best trade-off between the conicting

demands of CPU operating time, speed and power consumption. The dash line in the Figure 11
indicates the power supply source of two digital power domains.

Domain

V

DD

LDOOFF

VDD

nRST

WAKEUP0

WAKEUP1

RTCOUT

WKUP1

WKUP2

WKUP3

RTCOUT

LCM

DMOSON

LDO

Controller

WKUP5

LDO

DMOS

V

DD15

V

DD

POR/PDR

LVD

1.5 V

POR/PDR

V

LDOOUT

5 Power Control Unit (PWRCU)

LSI

LSE

HSE

LDO: Voltage Regulator
DMOS: Depletion MOS

LVD: Low Voltage Detector
POR/PDR: Power On Reset/Power Down Reset

Figure 11. PWRCU Block Diagram

PWR_CTRL

SLEEPDEEP

SLEEPING

WKUP4

V

1.5 V Domain

DD15

CPU Memories

RTC

Digital

Peripheral

HSI

Rev. 1.00 60 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Features

▄

Three power domains: V

▄

Three power saving modes: Sleep, Deep-Sleep1 and Deep-Sleep2 modes.

▄

Internal Voltage regulator supplies 1.5 V voltage source.

▄

Additional Depletion MOS supplies 1.5 V voltage source with low leakage and low operating current.

▄

A power reset is generated when one of the following events occurs:

● Power-on / Power-down reset (POR / PDR reset).

● The control bits BODEN = 1, BODRIS = 0 and the supply power VDD ≤ V

▄

BOD Brown-out Detector can issue a system reset or an interrupt when VDD power source is
lower than the Brown Out Detector voltage V

▄

LVD Low Voltage Detector can issue an interrupt or wakeup event when VDD is lower than a

programmable threshold voltage V

Functional Descriptions

DD, VDDIO

and V

.

LVD

1.5 V power domains.

DD15

.

BOD

BOD

5 Power Control Unit (PWRCU)

.

VDD Power Domain

LDO Power Control

The LDO will be automatically switched off when the following condition occurs:

▄

The Deep-Sleep2 mode is entered.

The LDO will be automatically switched on by hardware when the supply power VDD > V
of the following conditions occurs:

▄

Resume operation from the power saving mode – RTC wakeup, LVD wakeup, EXTI wakeup and
WAKEUP pins.

▄

Detect a falling edge on the external reset pin (nRST).

▄

The control bit BODEN = 1 and the supply power VDD > V

To enter the Deep-Sleep1 mode, the PWRCU will request the LDO to operate in a low current
mode, LCM. To enter the Deep-Sleep2 mode, the PWRCU will turn off the LDO and turn on the

DMOS to supply an alternative 1.5 V power.

Voltage Regulator

The voltage regulator, LDO, Depletion MOS, DMOS, Low voltage Detector, LVD, Low Speed
Internal RC oscillator, LSI, Low Speed External Crystal oscillator, LSE, and the High Speed External

Crystal oscillator, HSE, are operated under the VDD power domain. The LDO can be configured

to operate in either normal mode (LDOOFF = 0, LDOLCM = 0, I
current mode (LDOOFF = 0, LDOLCM = 1, I

= Low current mode) to supply the 1.5 V power. An

OUT

alternative 1.5 V power source is the output of the DMOS which has low static and driving current
characteristics. It is controlled using the DMOSON bit in the PWRCR register. The DMOS output has
weak output current and regulation capability and only operates in the Deep-Sleep2 mode for data
retention purposes in the V

power domain.

DD15

BOD

.

= High current mode) or low

OUT

POR

if any

Power On Reset (POR) / Power Down Reset (PDR)

The device has an integrated POR / PDR circuitry that allows proper operation starting from
V

. For more details concerning the power on / power down reset threshold voltage, refer to the

POR

electrical characteristics of the corresponding datasheet.

Rev. 1.00 61 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

V

DD

V

POR

Hysteresis

V

PDR

5 Power Control Unit (PWRCU)

POR Delay Time

t

RESET

RSTD

Figure 12. Power On Reset / Power Down Reset Waveform

Low Voltage Detector / Brown Out Detector

The Low Voltage Detector, LVD, can detect whether the supply voltage VDD is lower than a

programmable threshold voltage V

. It is selected by the LVDS bits in the LVDCSR register.

LV D

When a low voltage on the VDD power pin is detected, the LVDF flag will be active and an
interrupt will be generated and sent to the MCU core if the LVDEN and LVDIWEN bits in the
LVDCSR register are set. For more details concerning the LVD programmable threshold voltage

V

, refer to the electrical characteristics of the corresponding datasheet.

LV D

The Brown Out Detector, BOD, is used to detect if the VDD supply voltage is equal to or lower

than V
is lower than V

. When the BODEN bit in the LVDCSR register is set to 1 and the VDD supply voltage

BOD

then the BODF ag is active. The PWRCU will regard this as a power down

BOD

reset situation and then immediately issue a system reset when the BODRIS bit is cleared to 0 or
issue an interrupt to notify the CPU to execute a power down procedure when the BODRIS bit is
set to 1. For more details concerning the Brown Out Detector voltage V

characteristics of the corresponding datasheet.

Time

, refer to the electrical

BOD

High Speed External Oscillator

The High Speed External Oscillator, HSE, is located in the VDD power domain. The HSE crystal
oscillator can be switched on or off using the HSEEN bit in the Global Clock Control Register
(GCCR). The HSE clock can be used directly as the system clock source.

LSE, LSI and RTC

The Real Time Clock Timer clock source can be derived from either the Low Speed Internal RC
oscillator, LSI, or the Low Speed External Crystal oscillator, LSE. Before entering the power

saving mode by executing WFI / WFE instruction, the MCU needs to setup the compare register
with an expected wakeup time and enable the wakeup function to achieve the RTC timer wakeup
event. After entering the power saving mode for a certain amount of time, the Compare Match

ag, CMFLAG, will be asserted to wake up the device when the compare match event occurs. The
details of the RTC conguration for wakeup timer will be described in the RTC chapter.

Rev. 1.00 62 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

1.5 V Power Domain

The main functions that include high speed internal oscillator, HSI, MCU core logic, AHB / APB

peripherals and memories and so on are located in this power domain. Once the 1.5 V is powered
up, the POR will generate a reset sequence on 1.5 V power domain. Subsequently, to enter the

expected power saving mode, the associated control bits including the LDOOFF, DMOSON and
LDOLCM bits must be congured. Then, once a WFI or WFE instruction is executed, the device

will enter an expected power saving mode which will be discussed in the following section.

High Speed Internal Oscillator

The High Speed Internal Oscillator, HSI, is located in the V

the Deep-Sleep mode, the HSI clock will be congured as the system clock for a certain period by

setting the PSRCEN bit to 1. This bit is located in the Global Clock Control Register, GCCR, in the

Clock Control Unit, CKCU. The system clock will not be switched back to the original clock source

used before entering the Deep-Sleep mode until the original clock source stabilizes.

Operation Modes

Run Mode

In the Run mode, the system operates with full functions and all power domains are active. There

are two ways to reduce the power consumption in this mode. The rst is to slow down the system
clock by setting the AHBPRE eld in the CKCU AHBCFGR register, and the second is to turn
off the unused peripherals clock by setting the APBCCR0 and APBCCR1 registers or slow down
peripherals clock by setting the APBPCSR0 and APBPCSR1 registers to meet the application

requirement. Reducing the system clock speed before entering the sleep mode will also help to
minimize power consumption.

power domain. When exiting from

DD15

5 Power Control Unit (PWRCU)

Additionally, there are several power saving modes to provide maximum optimization between
device performance and power consumption.

Table 10. Operation Mode Denitions

Mode Name Hardware Action

Run After system reset, CPU fetches instructions to execute.

Sleep

Deep-Sleep1 ~ 2

1. CPU clock will be stopped.

2. Peripherals, Flash and SRAM clocks can be stopped by setting.

1. Stop all clocks in the 1.5 V power domain.

2. Disable HSI, HSE.

3. Turning on the LDO low current mode or DMOS to reduce the 1.5 V power
domain current.

Sleep Mode

By default, only the CPU clock will be stopped in the Sleep mode. Clearing the FMCEN or
SRAMEN bit in the CKCU AHBCCR register to 0 will have the effect of stopping the Flash

clock or SRAM clock after the system enters the Sleep mode. If it is not necessary for the CPU to
access the Flash memory and SRAM in the Sleep mode, it is recommended to clear the FMCEN

and SRAMEN bits in the AHBCCR register to minimize power consumption. To enter the Sleep
mode, it is only CPU executes a WFI or WFE instruction and lets the SLEEPDEEP signal to 0. The

system will exit from the Sleep mode via any interrupt or event trigger. The accompanying table
provides more information about the power saving modes.

Rev. 1.00 63 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Table 11. Enter / Exit Power Saving Modes

Mode Entry

Mode

Sleep

Deep-Sleep1 1 0 0

Deep-Sleep2 1 X 1

Notes:

1. Wakeup event means EXTI line in event mode, RTC, LVD and WAKEUP pins

2. If the system allows the LVD activity to wake it up after the system has entered the power saving mode,

CPU

Instruction

WFI or WFE
(Takes effect)

CPU

SLEEPDEEP

0 X X

LDOOFF DMOSON

WFI: Any interrupt
WFE:

Any wakeup event
Any interrupt (NVIC on) or
Any interrupt with SEVONPEND = 1 (NVIC off)

Any EXTI in event mode or
RTC wakeup or LVD wakeup
WAKEUP pins

Any EXTI in event mode or
RTC wakeup or LVD wakeup
WAKEUP pins

the LVDEWEN and LVDEN bits in the LVDCSR register must be set to 1 to make sure that the system
can be woken up by an LVD event and then the LDO regulator can be turned on when system is woken
up from the Deep-Sleep2 mode.

Mode Exit

(1)

or

(2)

or

(2)

5 Power Control Unit (PWRCU)

or

Deep-Sleep Mode

To enter Deep-Sleep mode, configure the registers as shown in the preceding table and execute
the WFI or WFE instruction. In the Deep-Sleep mode, all clocks including high speed oscillator,

known as HSI and HSE, will be stopped. In addition, Deep-Sleep1 turns the LDO into low current
mode while Deep-Sleep2 turns off the LDO and uses a DMOS to keep 1.5 V power. Once the

PWRCU receives a wakeup event or an interrupt as shown in the preceding Mode-Exiting table, the

LDO will then operate in normal mode and the high speed oscillator will be enabled. Finally, the
CPU will return to Run mode to handle the wakeup interrupt if required. A Low Voltage Detection
also can be regarded as a wakeup event if the corresponding wakeup control bit LVDEWEN in the
LVDCSR register is enabled. The last wakeup event is a transition on the external WAKEUP pin

sent to the PWRCU to resume from Deep-Sleep mode. During the Deep-Sleep mode, retaining the
register and memory contents will shorten the wakeup latency.

Table 12. Power Status After System Reset

PORF PORSTF Description

1 1

0 1 Restart from unexpected loss of the 1.5 V power or other reset (nRST, WDT, …)

Register Map

The following table shows the PWRCU registers and reset values. Note all the registers in this unit
are located in the V

Power-up for the rst time after the VDD power domain is reset:

Power on reset when VDD is applied for the rst time or executing software reset
command on the VDD domain.

power domain.

DD15

Table 13. PWRCU Register Map

Register Offset Description Reset Value

PWRSR 0x100 Power Control Status Register 0x0000_0010

PWRCR 0x104 Power Control Register 0x0000_0000

LVDCSR 0x110 Low Voltage / Brown Out Detect Control and Status Register 0x0000_0000

Rev. 1.00 64 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Register Descriptions

Power Control Status Register – PWRSR

This register indicates power control status.

Offset: 0x100

Reset value: 0x0000_0010

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

Reserved WUPF1 WUPF

Type/Reset RC 0 RC 0

7 6 5 4 3 2 1 0

Reserved PORF Reserved

Type/Reset RC 1

Bits Field Descriptions

[9] WUPF1 External WAKEUP1 Pin Flag

0: The WAKEUP1 pin is not asserted
1: The WAKEUP1 pin is asserted

This bit is set by hardware when the WAKEUP1 pin asserts and is cleared by
software read. Software should read this bit to clear it after a system wake up from
the power saving mode.

[8] WUPF0 External WAKEUP0 Pin Flag

0: The WAKEUP0 pin is not asserted
1: The WAKEUP0 pin is asserted

This bit is set by hardware when the WAKEUP0 pin asserts and is cleared by
software read. Software should read this bit to clear it after a system wake up from
the power saving mode.

[4] PORF Power On Reset Flag

0: V
1: V

This bit is set by hardware when
power on reset or software reset. The bit is cleared by software read. This bit must be

cleared after the system is rst powered on, otherwise it will be impossible to detect

when a
read software loop must be implemented until the bit returns again to 0.

Power Domain reset does not occur

DD15

Power Domain reset occurs

DD15

V

Power Domain reset has been triggered. When this bit is read as 1, a

DD15

V

power on reset occurs, either a hardware

DD15

5 Power Control Unit (PWRCU)

Rev. 1.00 65 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Power Control Register – PWRCR

This register provides power control bits for the different kinds of power saving modes.

Offset: 0x104

Reset value: 0x0000_0000

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved WUP1TYPE WUP0TYPE

Type/Reset RW 0 RW 0 RW 0 RW 0

15 14 13 12 11 10 9 8

DMOSSTS Reserved WUP1IEN WUP1EN WUP0IEN WUP0EN

Type/Reset RO 0 RW 0 RW 0 RW 0 RW 0

7 6 5 4 3 2 1 0

DMOSON Reserved LDOOFF LDOLCM Reserved PWCURST

Type/Reset RW 0 RW 0 RW 0 WO 0

5 Power Control Unit (PWRCU)

Bits Field Descriptions

[19:18] WUP1TYPE WAKEUP1 Signal Trigger Type

WUP1TYPE [1:0] WAKEUP Signal Trigger Type

0 0 Positive-edge Triggered

0 1 Negative-edge Triggered

1 0 High-level Sensitive

1 1 Low-level Sensitive

[17:16] WUP0TYPE WAKEUP0 Signal Trigger Type

WUP0TYPE [1:0] WAKEUP Signal Trigger Type

0 0 Positive-edge Triggered

0 1 Negative-edge Triggered

1 0 High-level Sensitive

1 1 Low-level Sensitive

[15] DMOSSTS Depletion MOS Status

This bit is set to 1 if the DMOSON bit in this register has been set to 1.
This bit is cleared to 0 if the DMOSON bit has been set to 0 or if a POR / PDR reset occurred.

[11] WUP1IEN External WAKEUP1 Pin Interrupt Enable

0: Disable WAKEUP1 pin interrupt function
1: Enable WAKEUP1 pin interrupt function

The software can set the WUP1IEN bit to 1 to assert the WKUP interrupt in the NVIC
unit when both the WUP1EN and WUPF1 bits are set to 1.

Rev. 1.00 66 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Bits Field Descriptions

[10] WUP1EN External WAKEUP1 Pin Enable

0: Disable WAKEUP1 pin function
1: Enable WAKEUP1 pin function

The Software can set the WUP1EN bit as 1 to enable the WAKEUP1 pin function
before entering the power saving mode. When WUP1EN = 1, a change on the
WAKEUP1 pin wakes up the system from the power saving mode. If the WAKEUP1
pin is active high, this bit will set an input pull down mode. The corresponding
register bits which should be properly setup are the PBPD[9] to 1 in the PBPDR

register, the PBPU[9] to 0 in the PBPUR register and the PBCFG9[3:0] eld to 0xF

in the GPBCFGHR register.
Note: Because this bit is located in the V
Power Domain reset. The WAKEUP1 pin signal has to keep a minimum of three 32
kHz clock periods until the activity has been detected for wake up the system.

[9] WUP0IEN External WAKEUP0 Pin Interrupt Enable

0: Disable WAKEUP0 pin interrupt function
1: Enable WAKEUP0 pin interrupt function

The software can set the WUP0IEN bit to 1 to assert the WKUP interrupt in the NVIC
unit when both the WUP0EN and WUPF0 bits are set to 1.

[8] WUP0EN External WAKEUP0 Pin Enable

0: Disable WAKEUP0 pin function
1: Enable WAKEUP0 pin function

The Software can set the WUP0EN bit as 1 to enable the WAKEUP0 pin function
before entering the power saving mode. When WUP0EN = 1, a change on the
WAKEUP0 pin wakes up the system from the power saving mode. If the WAKEUP0
pin is active high, this bit will set an input pull down mode. The corresponding
register bits which should be properly setup are the PBPD[12] to 1 in the PBPDR

register, the PBPU[12] to 0 in the PBPUR register and the PBCFG12[3:0] eld to

0xF in the GPBCFGHR register.
Note: Because this bit is located in the V

Domain reset. The WAKEUP0 pin signal has to keep a minimum of three 32 kHz
clock periods until the activity has been detected for wake up the system.

[7] DMOSON DMOS Control

0: DMOS is OFF
1: DMOS is ON

A DMOS is implemented to provide an alternative voltage source for the 1.5 V power
domain when the CPU enters the Deep-Sleep mode (SLEEPDEEP = 1). The control
bit DMOSON is set by software and cleared by software or VDD power domain reset.
If the DMOSON bit is set to 1, the LDO will automatically be turned off when the
CPU enters the Deep-Sleep mode.

[3] LDOOFF LDO Operating Mode Control

0: The LDO operates in a low current mode when CPU enters the Deep-Sleep mode

(SLEEPDEEP = 1). The V

1: The LDO is turned off when the CPU enters the Deep-Sleep mode (SLEEPDEEP =

1). The

V

power is not available

DD15

Note: This bit is only available when the DMOSON bit is cleared to 0.

power is available

DD15

Power Domain and reset by a V

DD15

Power Domain and reset by a V

DD15

DD15

DD15

Power

5 Power Control Unit (PWRCU)

Rev. 1.00 67 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Bits Field Descriptions

[2] LDOLCM LDO Low Current Mode

0: The LDO is operated in normal current mode
1: The LDO is operated in low current mode

Note: This bit is only available when CPU is in the run mode. The LDO output

current capability will be limited at 10 mA below and lower static current when
the LDOLCM bit is set. It is suitable for CPU, which is operated at lower speed
system clock, to get a lower current consumption. This bit will be cleared to 0
when the LDO is powered down or VDD power domain is reset.

[0] PWCURST Power Control Unit Software Reset

0: No action
1: Power Control Unit Software Reset is activated

When this bit is set, it will reset all the related RTC and PWRCU registers.

Low Voltage / Brown Out Detect Control and Status Register – LVDCSR

This register species ags, enable bits and option bits for low voltage detector.

Offset: 0x110

Reset value: 0x0000_0000

5 Power Control Unit (PWRCU)

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved LVDS [2] LVDEWEN LVDIWEN LVDF LVDS [1:0] LVDEN

Type/Reset RW 0 RW 0 RW 0 RO 0 RW 0 RW 0 RW 0

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved BODF Reserved BODRIS BODEN

Type/Reset RO 0 RW 0 RW 0

Bits Field Descriptions

[21] LVDEWEN LVD Event Wakeup Enable

0: LVD event wakeup is disabled
1: LVD event wakeup is enabled

Setting this bit to 1 will enable the LVD event wakeup function to wake up the system
when an LVD condition occurs which result in the LVDF bit being asserted. If the
system requires to be woken up from the Deep-Sleep mode by an LVD condition,
this bit must be set to 1.

[20] LVDIWEN LVD Interrupt Wakeup Enable

0: LVD interrupt wakeup is disabled
1: LVD interrupt wakeup is enabled

Setting this bit to 1 will enable the LVD interrupt function. When an LVD condition
occurs and the LVDIWEN bit is set to 1, an LVD interrupt will be generated and sent
to the CPU NVIC unit.

Rev. 1.00 68 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Bits Field Descriptions

[19] LVDF Low Voltage Detect Status Flag

0: VDD is higher than the specic voltage level
1: VDD is equal to or lower than the specic voltage level

When the LVD condition occurs, the LVDF flag will be asserted. When the LVDF flag
is asserted, an LVD interrupt will be generated for CPU if the LVDIWEN bit is set to 1.
However, if the LVDEWEN bit is set to 1 and the LVDIWEN bit is cleared to 0, only an LVD

event will be generated rather than an LVD interrupt when the LVDF ag is asserted.

[22], [18:17] LVDS [2:0] Low Voltage Detect Level Selection

For more details concerning the LVD programmable threshold voltage, refer to the
electrical characteristics of the corresponding datasheet.

[16] LVDEN Low Voltage Detect Enable

0: Disable Low Voltage Detect
1: Enable Low Voltage Detect

Setting this bit to 1 will generate an LVD event when the VDD power is equal to or
lower than the voltage set by LVDS bits. Therefore when the LVD function is enabled
before the system is into the Deep-Sleep2 (DMOS is turn on and LDO is power
down), the LVDEWEN bit has to be enabled to avoid the LDO does not activate in
the meantime when the CPU is woken up by the low voltage detection activity.

[3] BODF Brown Out Detect Flag

0: VDD > V
1: VDD ≤ V

[1] BODRIS BOD Reset or Interrupt Selection

0: Reset the whole chip
1: Generate Interrupt

[0] BODEN Brown Out Detector Enable

0: Disable Brown Out Detector
1: Enable Brown Out Detector

BOD

BOD

5 Power Control Unit (PWRCU)

Rev. 1.00 69 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

6 Clock Control Unit (CKCU)

Introduction

The Clock Control unit, CKCU, provides functions of high speed internal RC oscillator, HSI, High
speed external crystal oscillator, HSE, Low speed internal RC oscillator, LSI, Low speed external
crystal oscillator, LSE, HSE clock monitor, clock prescaler, clock multiplexer and clock gating. The
clock of AHB, APB and CPU are derived from system clock, CK_SYS, which can come from HSI,
HSE, LSI and LSE. Watchdog Timer and Real Time Clock, RTC, use either LSI or LSE as their

clock source.

A variety of internal clocks can also be wired out through CKOUT for debugging purpose. The

clock monitor can be used to get clock failure detection of HSE. Once the clock of HSE does not

function (could be broken down or removed or etc.), CKCU will force to switch the system clock

source to HSI clock to prevent system halt.

6 Clock Control Unit (CKCU)

Rev. 1.00 70 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU

SPIx, USART, UARTx,

HT32F50231/HT32F50241

HSI Auto
Trimming
Controller

20 MHz
HSI RC

HSIEN

4 ~ 20 MHz

HSE XTAL

HSEEN

32.768 kHz

LSE XTAL

(1)

LSEEN

32 kHz

LSI RC

CK_LSE

CK_IN

CK_LSE

CK_LSI

(2)

CK_HSI

CK_HSE

WDTSRC

WDTEN

RTCSRC

SW[2:0]

Clock

Monitor

(1)

CK_SYS

CK_WDT

CK_RTC

CKREFEN

AHB Prescaler

1,2,4,8,16,32

Prescaler

CKREFPRE

CM0PEN

CK_AHB

FMCEN

CM0PEN

SRAMEN

CM0PEN

BMEN

CM0PEN

APBEN

1 ~ 32

GPIOAEN

GPIOCEN

CM0PEN

(control by H/W)

Divider

2

8

CK_REF

STCLK
(to SysTick)

CK_GPIO
(to GPIO port)

FCLK
(Free running clock)

HCLKC

®

-M0+)

(to Cortex

HCLKF
(to Flash)

HCLKS
(to SRAM)

HCLKBM
(to Bus Matrix)

HCLKAPB
(to APB Bridge)

6 Clock Control Unit (CKCU)

(1)

RTCEN

CKOUTSRC[2:0]

000
001
010

CKOUT

011
100
101
110

Legend:

HSE = High Speed External clock

HSI = High Speed Internal clock

LSE = Low Speed External clock

LSI = Low Speed Internal clock

Notes:

1. This control bit is located at RTC Control Register, RTCCR.

2. The CK_IN signal is sourced from the external pin, CKIN.

CK_REF
CK_AHB/16
CK_SYS/16
CK_HSE/16
CK_HSI/16
CK_LSE
CK_LSI

Figure 13. CKCU Block Diagram

Peripherals

Clock

Prescaler

1,2,4,8

ADCEN

DIVEN

CRCEN

CK_AHB

CK_AHB/2

CK_AHB/4

CK_AHB/8

00

01

10

11

ADC

Prescaler

1,2,3,4,8...

CK_DIV
(to DIV)

CK_CRC
(to CRC)

SPIEN

EXTIEN

CK_ADC IP

PCLK (AFIO, ADC,

2

I

Cx, MCTM, GPTM,
PWMx, BFTMx, EXTI,
RTC, WDT)

Rev. 1.00 71 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Features

▄

4 ~ 20 MHz external crystal oscillator (HSE)

▄

Internal 20 MHz RC oscillator (HSI) with conguration option calibration and custom trimming

capability.

▄

32,768 Hz external crystal oscillator (LSE) for Watchdog Timer, RTC or system clock.

▄

Internal 32 kHz RC oscillator (LSI) for Watchdog Timer, RTC or system clock.

▄

HSE clock monitor

Function Descriptions

High Speed External Crystal Oscillator – HSE

The high speed external 4 to 20 MHz crystal oscillator (HSE) produces a highly accurate
clock source to the system clock. The related hardware configuration is shown in the following

gure. The crystal with specic frequency must be placed across the two HSE pins (XTALIN /
XTALOUT) and the external components such as resistors and capacitors are necessary to make it

oscillate properly.

6 Clock Control Unit (CKCU)

The following guidelines are provided to improve the stability of the crystal circuit PCB layout.

▄

The crystal oscillator should be located as close as possible to the MCU so that the trace lengths
are kept as short as possible to reduce any parasitic capacitances.

▄

Shield any lines in the vicinity of the crystal by using a ground plane to isolate signals and
reduce noise.

▄

Keep frequently switching signal lines away from the crystal area to prevent crosstalk.

OSC_EN

XTALOUTXTALIN

R

ext

Crystal

C

L1

C

L2

Figure 14. External Crystal, Ceramic and Resonators for HSE

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32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

The HSE crystal oscillator can be switched on or off using the HSEEN bit in the Global Clock

Control Register (GCCR). The HSERDY f lag in the Global Clock Status Register (GCSR) will

indicate if the high-speed external crystal oscillator is stable. While switching on the HSE, the HSE

clock will still not be released until this HSERDY bit is set by the hardware. The specic delay

period is well-known as “Start-up time”. The HSE clock can then be used directly as the system
clock source.

High Speed Internal RC Oscillator – HSI

The high speed internal RC oscillator (HSI) is the default selection of clock source for the CPU when
the device is powered up. The HSI RC oscillator provides a clock source in a lower cost because no
external components are required. The HSI RC oscillator can be switched on or off using the HSIEN

bit in the Global Clock Control Register (GCCR). The HSIRDY flag in the Global Clock Status

Register (GCSR) will indicate if the internal RC oscillator is stable. The start-up time of HSI is shorter
than the HSE crystal oscillator.

The accuracy of the frequency of the high speed internal RC oscillator HSI can be calibrated via the

conguration options, but it is still less accurate than the HSE crystal oscillator. The applications, the

environments and the cost will determine the use of the oscillators.

Software could congure the PSRCEN bit (Power Saving Wakeup RC Clock Enable) to 1 to force HSI

clock to be system clock when wake-up from Deep-Sleep1/2 mode. Subsequently, the system clock is

back to the original clock source if the original clock source ready ag is asserted. This function can

reduce the wakeup time when using HSE as system clock.

Auto Trimming of High Speed Internal RC Oscillator – HSI

The frequency accuracy of the high speed internal RC oscillator HSI can vary from one chip to
another due to manufacturing process variations, this is why each device is factory calibrated

by HOLTEK for ±2 % accuracy at VDD = 5 V and TA = 25˚C. But the accuracy is not enough for

some applications and environments requirement. Therefore, this device provides the trimming
mechanism for HSI frequency calibration using more accurate external reference clock. The
detailed block diagram is shown as Figure 15.

6 Clock Control Unit (CKCU)

After reset, the factory trimming value is loaded in the HSICOARSE[4:0] and HSIFINE[7:0] bits

in the HSI Control Register (HSICR). The HSI frequency accuracy may be affected by voltage or
temperature variations. If the application has to be driven by a more accurate HSI frequency, users

can trim manually the HSI frequency using the HSIFINE[7:0] bits in the HSI Control Register

(HSICR) or automatically adjust the HSI frequency using the Auto Trimming Controller (ATC)
together with an external reference clock in the application. The reference clock can be provided
form the following clock sources:

▄

32,768 Hz low speed external crystal or ceramic resonator oscillator LSE output clock

▄

External pin (CKIN) with 1 kHz pulse

Rev. 1.00 73 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU

Trimming Bits

HT32F50231/HT32F50241

Auto Trimming HSI Block Diagram

1

0

TMSEL

External pin (CKIN)

LSE

32.768 kHz

1

Factory

0

TRIMEN

/32

1x

0x

REFCLKSEL

Fine [7:0]

Coarse [4:0]

1 kHz

/1.024 kHz

Fine-Trimming

Write Register

ATCEN

Auto Trimming

Controller

Fine-Trimming
Read Register

HSI

RC Oscillator

AT
Counter
Register

6 Clock Control Unit (CKCU)

AHB Bus

Coarse-Trimming

Read Register

Figure 15. HSI Auto Trimming Block Diagram

Rev. 1.00 74 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Low Speed External Crystal Oscillator – LSE

The low speed external crystal or ceramic resonator oscillator with 32.768 kHz frequency produces a

low power but highly accurate clock source for the circuits of Real-Time-Clock peripheral, Watchdog

Timer or system clock. The associated hardware conguration is shown in the following gure. The
crystal or ceramic resonator must be placed across the two LSE pins (X32KIN / X32KOUT) and the
external capacitors are necessary to make it oscillate properly. The LSE oscillator can be switched
on or off by using the LSEEN bit in the RTC Control Register (RTCCR). The LSERDY ag in the
Global Clock Status Register (GCSR) will indicate if the LSE clock is stable.

6 Clock Control Unit (CKCU)

X32KIN

32.768 kHz

C

L1

Figure 16. External Crystal, Ceramic and Resonators for LSE

Low Speed Internal RC Oscillator – LSI

The low speed internal RC oscillator with frequency of about 32 kHz produces a low power
clock source for the circuits of Real-Time-Clock peripheral, Watchdog Timer or system clock.

The LSI is also a clock source of low cost because no external component is needed to make it
oscillates. The accuracy of the frequency of the low speed internal RC oscillator LSI is shown as
the corresponding data sheet. The LSIRDY ag in the Global Clock Status Register (GCSR) will
indicate if the LSI clock is stable.

Clock Ready Flag

CKCU provides clock ready ags for HSI, HSE, LSI and LSE to conrm those clocks are stable
before using them as system clock source or other purpose. Software can check specic clock is

ready or not by polling separate clock ready status bits in GCSR register.

X32KOUT

C

L2

System Clock (CK_SYS) Selection

After the system reset occurs, the default system clock source CK_SYS will be the high speed
internal RC oscillator HSI. The CK_SYS may come from the HSI, HSE, LSI and LSE output clock

and it can be switched from one clock source to another via the System Clock Switch bits, SW, in
the Global Clock Control Register GCCR. The system will still run under the original clock until
the destination clock gets ready. The corresponding clock ready status bits in the Global Clock

Status Register GCSR will indicate whether the selected clock is ready to use or not. The CKCU
also contains the clock source status bits in the Clock Source Status Register CKST to indicate

which clock is currently used as the system clock. More details about function of clock enable are
described in below.

Rev. 1.00 75 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

If any following action takes effect, the HSI is always under enable state.

▄

Enable Clock monitor. (CKMEN)

▄

Congure clock switch register bits to select the HSI. (SW)

▄

Congure HSI enable register bit to 1. (HSIEN)

If any following action takes effect, the HSE is always under enable state.

▄

Congure clock switch register bits to select the HSE. (SW)

▄

Congure HSE enable register bit to 1. (HSEEN)

Programming guide of System clock selection is listed in following.

1. Enable any source clock which will become system clock.

2. Conguring the SW register bits to change system clock source will take effect after ready ag

of source clock is asserted. Note that system clock will force to HSI if clock monitor is enabled

and HSE clock congured as system clock is stuck at 0 or 1.

6 Clock Control Unit (CKCU)

HSE Clock Monitor

The main function of the oscillator check is enabled by the HSE Clock Monitor Enable bit CKMEN

in the Global Clock Control Register, GCCR. The HSE clock monitor should be enabled after the
HSE oscillator start-up delay and be disabled when the HSE oscillator is stopped. Once the HSE
oscillator failure is detected, the HSE oscillator will automatically be disabled. The HSE clock

stuck flag CKSF in the Global Clock Interrupt Register GCIR will be set and an event of main
oscillator failure will be generated if the clock fail interrupt enable bit CKSIE in the GCIR is set.

This failure interrupt is connected to the exception vector of CPU Non-Maskable Interrupt, NMI. If
the HSE is directly used as the system clock, when the HSE oscillator failure occurs, the HSE will
be turned off and the system clock will be switched to the HSI automatically by the hardware.

Clock Output Capability

The device has the clock output capability to allow the clocks to be output on the specic external
output pin CKOUT. The configuration registers of the corresponding GPIO port must be well
congured in the Alternate Function I/O section, AFIO, to output the selected clock signal. There

are seven output clock signals to be selected via the device clock output source selection bits

CKOUTSRC in the Global Clock Conguration Register, GCFGR.

Table 14. CKOUT Clock Source

CKOUTSRC[2:0] Clock Source

000 CK_REF = CK_SYS / (CKREFPRE + 1) / 2

001 CK_AHB / 16

010 CK_SYS / 16

011 CK_HSE / 16

100 CK_HSI / 16

101 CK_LSE

110 CK_LSI

Rev. 1.00 76 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Register Map

The following table shows the CKCU register and reset value.

Table 15. CKCU Register Map

Register Offset Description Reset Value

GCFGR 0x000 Global Clock Conguration Register 0x0000_0002

GCCR 0x004 Global Clock Control Register 0x0000_0803

GCSR 0x008 Global Clock Status Register 0x0000_0028

GCIR 0x00C Global Clock Interrupt Register 0x0000_0000

AHBCFGR 0x020 AHB Conguration Register 0x0000_0001

AHBCCR 0x024 AHB Clock Control Register 0x0000_0065

APBCFGR 0x028 APB Conguration Register 0x0001_0000

APBCCR0 0x02C APB Clock Control Register 0 0x0000_0000

APBCCR1 0x030 APB Clock Control Register 1 0x0000_0000

CKST 0x034 Clock Source Status Register 0x0100_0003

APBPCSR0 0x038 APB Peripheral Clock Selection Register 0 0x0000_0000

APBPCSR1 0x03C APB Peripheral Clock Selection Register 1 0x0000_0000

HSICR 0x040 HSI Control Register

HSIATCR 0x044 HSI Auto Trimming Counter Register 0x0000_0000

APBPCSR2 0x048 APB Peripheral Clock Selection Register 2 0x0000_0000

MCUDBGCR 0x304 MCU Debug Control Register 0x0000_0000

6 Clock Control Unit (CKCU)

0xXXXX_0000

where X is undened

Rev. 1.00 77 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Register Descriptions

Global Clock Conguration Register – GCFGR

This register species the low power mode status and clock source for CKOUT.

Offset: 0x000

Reset value: 0x0000_0002

31 30 29 28 27 26 25 24

LPMOD Reserved

Type/Reset RO 0 RO 0 RO 0

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

CKREFPRE

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0

7 6 5 4 3 2 1 0

Reserved

Type/Reset RW 0 RW 1 RW 0

Reserved

CKOUTSRC

Bits Field Descriptions

[31:29] LPMOD Lower Power Mode Status

000: When Chip is in running mode
001: When Chip wants to enter Sleep mode
010: When Chip wants to enter Deep-Sleep1 mode
011: When Chip wants to enter Deep-Sleep2 mode
Others: Reserved

Set and reset by hardware.

[15:11] CKREFPRE CK_REF Clock Prescaler Selection

CK_REF = CK_SYS / (CKREFPRE + 1) / 2

00000: CK_REF = CK_SYS / 2
00001: CK_REF = CK_SYS / 4
...
11111: CK_REF = CK_SYS / 64

Set and reset by software to control CK_REF clock prescaler setting.

[2:0] CKOUTSRC CKOUT Clock Source Selection

000: (CK_SYS / (CKREFPRE + 1) / 2 ) is selected
001: (CK_AHB / 16) is selected
010: (CK_SYS / 16) is selected
011: (CK_HSE / 16) is selected
100: (CK_HSI / 16) is selected
101: CK_LSE is selected
110: CK_LSI is selected
111: Reserved

Set and reset by software.

6 Clock Control Unit (CKCU)

Rev. 1.00 78 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Global Clock Control Register – GCCR

This register species the clock enable bits.

Offset: 0x004

Reset value: 0x0000_0803

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved PSRCEN CKMEN

Type/Reset RW 0 RW 0

15 14 13 12 11 10 9 8

Reserved HSIEN HSEEN Reserved HSEGAIN

Type/Reset RW 1 RW 0 RW 0

7 6 5 4 3 2 1 0

Reserved SW

Type/Reset RW 0 RW 1 RW 1

6 Clock Control Unit (CKCU)

Bits Field Descriptions

[17] PSRCEN Power Saving Wakeup RC Clock Enable

0: No action
1: Use Internal RC clock (HSI) as system clock after a Deep-Sleep1/2 mode wakeup

Software can set PSRCEN to high before entering Deep-Sleep1/2 mode in order to
reduce the waiting time after wakeup. When PSRCEN = 1, hardware will select HSI
as clock source after the system wakeup from Deep-Sleep1/2 mode. Meanwhile,
instruction can start execution since the HSI clock is provided to MCU. After the
original clock source, which is selected as CK_SYS before entering Deep-Sleep1/2
mode, is ready, hardware will switch back the clock source as originally.

[16] CKMEN HSE Clock Monitor Enable

0: Disable External crystal oscillator clock monitor
1: Enable External crystal oscillator clock monitor

When hardware detects HSE clock stuck at low / high state, internal hardware will switch
the system clock to internal high speed RC clock (HSI). The only way to recover the
system clock is by an external reset, a power on reset or by clearing CKSF by software.

[11] HSIEN Internal High Speed Clock Enable

0: Internal RC oscillator clock is set to off
1: Internal RC oscillator clock is set to on

Set and reset by software. This bit can not be reset if HSI clock is used as system clock.

[10] HSEEN External High Speed Clock Enable

0: External crystal oscillator clock is set to off
1: External crystal oscillator clock is set to on

Set and reset by software. This bit can not be reset if the HSE clock is used as
system clock.

Rev. 1.00 79 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Bits Field Descriptions

[8] HSEGAIN External High Speed Clock Gain Selection

0: HSE low gain mode
1: HSE high gain mode

[2:0] SW System Clock Switch

010: CK_HSE as system clock
011: CK_HSI as system clock
110: CK_LSE as system clock
111: CK_LSI as system clock
Others: CK_HSI as system clock

These bits are set and reset by software to select CK_SYS source. If the HSE
oscillator is used directly or indirectly as the system clock and the HSE clock monitor
function is enabled, once the HSE failure is detected, these bits will be set by
hardware to force HSI (b011) as the system clock.
Note: When switch the system clock using the SW bits, the system clock is not

immediately switched and a certain delay is necessary. The software can
monitor the CKSWST bit in the clock source status register CKSTR to make
sure which clock is currently used as system clock.

6 Clock Control Unit (CKCU)

Rev. 1.00 80 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Global Clock Status Register – GCSR

This register indicates the clock ready status.

Offset: 0x008

Reset value: 0x0000_0028

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved LSIRDY LSERDY HSIRDY HSERDY Reserved

Type/Reset RO 1 RO 0 RO 1 RO 0

6 Clock Control Unit (CKCU)

Bits Field Descriptions

[5] LSIRDY Internal Low Speed Clock Ready Flag

0: Internal 32 kHz RC oscillator clock is not ready
1: Internal 32 kHz RC oscillator clock is ready

Set by hardware to indicate that the LSI is stable to be used.

[4] LSERDY External Low Speed Clock Ready Flag

0: External 32.768 kHz RC oscillator clock is not ready
1: External 32.768 kHz RC oscillator clock is ready

Set by hardware to indicate that the LSE is stable to be used.

[3] HSIRDY Internal High Speed Clock Ready Flag

0: Internal RC oscillator clock is not ready
1: Internal RC oscillator clock is ready

Set by hardware to indicate that the HSI is stable to be used.

[2] HSERDY External High Speed Clock Ready Flag

0: External crystal oscillator clock is not ready
1: External crystal oscillator clock is ready

Set by hardware to indicate that the HSE is stable to be used.

Rev. 1.00 81 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Global Clock Interrupt Register – GCIR

This register species interrupt enable and ag bits.

Offset: 0x00C

Reset value: 0x0000_0000

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved CKSIE

Type/Reset RW 0

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved CKSF

Type/Reset WC 0

6 Clock Control Unit (CKCU)

Bits Field Descriptions

[16] CKSIE Clock Stuck Interrupt Enable

0: Disable clock fail interrupt
1: Enable clock fail interrupt

Set and reset by software to enable / disable interrupt caused by clock monitor.

[0] CKSF Clock Stuck Interrupt Flag

0: Clock works normally
1: HSE clock is stuck

Reset by software (Write 1 clear). Set by hardware when HSE clock stuck and
CKSIE is set.

Rev. 1.00 82 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

AHB Conguration Register – AHBCFGR

This register species frequency of system clock.

Offset: 0x020

Reset value: 0x0000_0001

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved AHBPRE

Type/Reset RW 0 RW 0 RW 1

6 Clock Control Unit (CKCU)

Bits Field Descriptions

[2:0] AHBPRE AHB Pre-scaler

000: CK_AHB = CK_SYS
001: CK_AHB = CK_SYS / 2
010: CK_AHB = CK_SYS / 4
011: CK_AHB = CK_SYS / 8
100: CK_AHB = CK_SYS / 16
101: CK_AHB = CK_SYS / 32
110: CK_AHB = CK_SYS / 32
111: CK_AHB = CK_SYS / 32

Set and reset by software to control the division factor of the AHB clock.

Rev. 1.00 83 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

AHB Clock Control Register – AHBCCR

This register species clock enable bits of AHB.

Offset: 0x024

Reset value: 0x0000_0065

31 30 29 28 27 26 25 24

Reserved DIVEN

Type/Reset RW 0

23 22 21 20 19 18 17 16

Reserved PCEN PBEN PAEN

Type/Reset RW 0 RW 0 RW 0

15 14 13 12 11 10 9 8

Reserved CRCEN Reserved CKREFEN Reserved

Type/Reset RW 0 RW 0

7 6 5 4 3 2 1 0

Reserved APBEN BMEN Reserved SRAMEN Reserved FMCEN

Type/Reset RW 1 RW 1 RW 1 RW 1

6 Clock Control Unit (CKCU)

Bits Field Descriptions

[24] DIVEN Divider Clock Enable

0: Divider clock is disabled
1: Divider clock is enabled

Set and reset by software.

[18] PCEN GPIO Port C Clock Enable

0: Port C clock is disabled
1: Port C clock is enabled

Set and reset by software.

[17] PBEN GPIO Port B Clock Enable

0: Port B clock is disabled
1: Port B clock is enabled

Set and reset by software.

[16] PAEN GPIO Port A Clock Enable

0: Port A clock is disabled
1: Port A clock is enabled

Set and reset by software.

[13] CRCEN CRC Module Clock Enable

0: CRC clock is disabled
1: CRC clock is enabled

Set and reset by software.

[11] CKREFEN CK_REF Clock Enable

0: CK_REF clock is disabled
1: CK_REF clock is enabled

Set and reset by software.

[6] APBEN APB bridge Clock Enable

0: APB bridge clock is automatically disabled by hardware during Sleep mode
1: APB bridge clock is always enabled during Sleep mode

Set and reset by software. Users can set APBEN as 0 to reduce power consumption
if the APB bridge is unused during Sleep mode.

Rev. 1.00 84 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Bits Field Descriptions

[5] BMEN Bus Matrix Clock Enable

0: Bus Matrix clock is automatically disabled by hardware during Sleep mode
1: Bus Matrix clock is always enabled during Sleep mode

Set and reset by software. Users can set BMEN as 0 to reduce power consumption
if the bus matrix is unused during Sleep mode.

[2] SRAMEN SRAM Clock Enable

0: SRAM clock is automatically disabled by hardware during Sleep mode
1: SRAM clock is always enabled during Sleep mode

Set and reset by software. Users can set SRAMEN as 0 to reduce power
consumption if the SRAM is unused during Sleep mode.

[0] FMCEN Flash Memory Controller Clock Enable

0: FMC clock is automatically disabled by hardware during Sleep mode
1: FMC clock is always enabled during Sleep mode

Set and reset by software. Users can set FMCEN as 0 to reduce power consumption
if the Flash Memory is unused during Sleep mode.

6 Clock Control Unit (CKCU)

APB Conguration Register – APBCFGR

This register species the frequency of ADC conversion clock.

Offset: 0x028

Reset value: 0x0001_0000

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved ADCDIV

Type/Reset RW 0 RW 0 RW 1

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved

Type/Reset

Bits Field Descriptions

[18:16] ADCDIV ADC Clock Frequency Divide Selection

000: CK_ADC = (CK_AHB / 1)
001: CK_ADC = (CK_AHB / 2)
010: CK_ADC = (CK_AHB / 4)
011: CK_ADC = (CK_AHB / 8)
100: CK_ADC = (CK_AHB / 16)
101: CK_ADC = (CK_AHB / 32)
110: CK_ADC = (CK_AHB / 64)
111: CK_ADC = (CK_AHB / 3)

Set and reset by software to control ADC conversion clock division factor.

Rev. 1.00 85 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

APB Clock Control Register 0 – APBCCR0

This register species clock enable bits of APB peripherals.

Offset: 0x02C

Reset value: 0x0000_0000

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

EXTIEN AFIOEN Reserved UR1EN UR0EN Reserved USREN

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0

7 6 5 4 3 2 1 0

Reserved SPI1EN SPI0EN Reserved I2C1EN I2C0EN

Type/Reset RW 0 RW 0 RW 0 RW 0

6 Clock Control Unit (CKCU)

Bits Field Descriptions

[15] EXTIEN External Interrupt Clock Enable

0: EXTI clock is disabled
1: EXTI clock is enabled

Set and reset by software.

[14] AFIOEN Alternate Function I/O Clock Enable

0: AFIO clock is disabled
1: AFIO clock is enabled

Set and reset by software.

[11] UR1EN UART1 Clock Enable

0: UART1 clock is disabled
1: UART1 clock is enabled

Set and reset by software.

[10] UR0EN UART0 Clock Enable

0: UART0 clock is disabled
1: UART0 clock is enabled

Set and reset by software.

[8] USREN USART Clock Enable

0: USART clock is disabled
1: USART clock is enabled

Set and reset by software.

[5] SPI1EN SPI1 Clock Enable

0: SPI1 clock is disabled
1: SPI1 clock is enabled

Set and reset by software.

[4] SPI0EN SPI0 Clock Enable

0: SPI0 clock is disabled
1: SPI0 clock is enabled

Set and reset by software.

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32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Bits Field Descriptions

[1] I2C1EN I2C1 Clock Enable

0: I2C1 clock is disabled
1: I2C1 clock is enabled

Set and reset by software.

[0] I2C0EN I2C0 Clock Enable

0: I2C0 clock is disabled
1: I2C0 clock is enabled

Set and reset by software.

APB Clock Control Register 1 – APBCCR1

This register species clock enable bits APB peripherals.

Offset: 0x030

Reset value: 0x0000_0000

31 30 29 28 27 26 25 24

Reserved ADCCEN

Type/Reset RW 0

23 22 21 20 19 18 17 16

Reserved BFTM1EN BFTM0EN

Type/Reset RW 0 RW 0

15 14 13 12 11 10 9 8

Reserved PWM1EN PWM0EN Reserved GPTMEN

Type/Reset RW 0 RW 0 RW 0

7 6 5 4 3 2 1 0

Reserved VDDREN Reserved WDTREN Reserved MCTMEN

Type/Reset RW 0 RW 0 RW 0

6 Clock Control Unit (CKCU)

Bits Field Descriptions

[24] ADCCEN ADC Controller Clock Enable

0: ADC clock is disabled
1: ADC clock is enabled

Set and reset by software.

[17] BFTM1EN BFTM1 Clock Enable

0: BFTM1 clock is disabled
1: BFTM1 clock is enabled

Set and reset by software.

[16] BFTM0EN BFTM0 Clock Enable

0: BFTM0 clock is disabled
1: BFTM0 clock is enabled

Set and reset by software.

[13] PWM1EN PWM1 Clock Enable

0: PWM1 clock is disabled
1: PWM1 clock is enabled

Set and reset by software.

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32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Bits Field Descriptions

[12] PWM0EN PWM0 Clock Enable

0: PWM0 clock is disabled
1: PWM0 clock is enabled

Set and reset by software.

[8] GPTMEN GPTM Clock Enable

0: GPTM clock is disabled
1: GPTM clock is enabled

Set and reset by software.

[6] VDDREN VDD Domain Clock Enable for Registers Access

0: Register access clock is disabled
1: Register access clock is enabled

Set and reset by software.

[4] WDTREN Watchdog Timer Clock Enable for Registers Access

0: Register access clock is disabled
1: Register access clock is enabled

Set and reset by software.

[0] MCTMEN MCTM Clock Enable

0: MCTM clock is disabled
1: MCTM clock is enabled

Set and reset by software.

6 Clock Control Unit (CKCU)

Rev. 1.00 88 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Clock Source Status Register – CKST

This register species status of clock source.

Offset: 0x034

Reset value: 0x0100_0003

31 30 29 28 27 26 25 24

Reserved HSIST

Type/Reset RO 0 RO 0 RO 1

23 22 21 20 19 18 17 16

Reserved HSEST

Type/Reset RO 0 RO 0

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved CKSWST

Type/Reset RO 0 RO 1 RO 1

6 Clock Control Unit (CKCU)

Bits Field Descriptions

[26:24] HSIST Internal High Speed Clock Occupation Status (CK_HSI)

xx1: HSI is used by System Clock (CK_SYS) (SW = 0x3)
x1x: Reserved
1xx: HSI is used by Clock Monitor

[17:16] HSEST External High Speed Clock Occupation Status (CK_HSE)

x1: HSE is used by System Clock (CK_SYS) (SW = 0x2)
1x: Reserved

[2:0] CKSWST Clock Switch Status

00x: Reserved
010: CK_HSE as system clock
011: CK_HSI as system clock
110: CK_LSE as system clock
111: CK_LSI as system clock

The elds are status to indicate which clock source is using as system clock currently.

Rev. 1.00 89 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

APB Peripheral Clock Selection Register 0 – APBPCSR0

This register species APB peripheral clock prescaler selection.

Offset: 0x038

Reset value: 0x0000_0000

31 30 29 28 27 26 25 24

UR1PCLK UR0PCLK Reserved USRPCLK

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

23 22 21 20 19 18 17 16

Reserved

Type/Reset RW 0 RW 0 RW 0 RW 0

15 14 13 12 11 10 9 8

BFTM1PCLK

Type/Reset RW 0 RW 0 RW 0 RW 0

7 6 5 4 3 2 1 0

SPI1PCLK SPI0PCLK I2C1PCLK I2C0PCLK

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

GPTMPCLK

BFTM0PCLK

Reserved

MCTMPCLK

Reserved

6 Clock Control Unit (CKCU)

Bits Field Descriptions

[31:30] UR1PCLK UART1 Peripheral Clock Selection

00: PCLK = CK_AHB
01: PCLK = CK_AHB / 2
10: PCLK = CK_AHB / 4
11: PCLK = CK_AHB / 8

PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock

[29:28] UR0PCLK UART0 Peripheral Clock Selection

00: PCLK = CK_AHB
01: PCLK = CK_AHB / 2
10: PCLK = CK_AHB / 4
11: PCLK = CK_AHB / 8

PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock

[25:24] USRPCLK USART Peripheral Clock Selection

00: PCLK = CK_AHB
01: PCLK = CK_AHB / 2
10: PCLK = CK_AHB / 4
11: PCLK = CK_AHB / 8

PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock

[21:20] GPTMPCLK GPTM Peripheral Clock Selection

00: PCLK = CK_AHB
01: PCLK = CK_AHB / 2
10: PCLK = CK_AHB / 4
11: PCLK = CK_AHB / 8

PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock

[17:16] MCTMPCLK MCTM Peripheral Clock Selection

00: PCLK = CK_AHB
01: PCLK = CK_AHB / 2
10: PCLK = CK_AHB / 4
11: PCLK = CK_AHB / 8

PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock

Rev. 1.00 90 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Bits Field Descriptions

[15:14] BFTM1PCLK BFTM1 Peripheral Clock Selection

00: PCLK = CK_AHB
01: PCLK = CK_AHB / 2
10: PCLK = CK_AHB / 4
11: PCLK = CK_AHB / 8

PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock

[13:12] BFTM0PCLK BFTM0 Peripheral Clock Selection

00: PCLK = CK_AHB
01: PCLK = CK_AHB / 2
10: PCLK = CK_AHB / 4
11: PCLK = CK_AHB / 8

PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock

[7:6] SPI1PCLK SPI1 Peripheral Clock Selection

00: PCLK = CK_AHB
01: PCLK = CK_AHB / 2
10: PCLK = CK_AHB / 4
11: PCLK = CK_AHB / 8

PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock

[5:4] SPI0PCLK SPI0 Peripheral Clock Selection

00: PCLK = CK_AHB
01: PCLK = CK_AHB / 2
10: PCLK = CK_AHB / 4
11: PCLK = CK_AHB / 8

PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock

[3:2] I2C1PCLK I2C1 Peripheral Clock Selection

00: PCLK = CK_AHB
01: PCLK = CK_AHB / 2
10: PCLK = CK_AHB / 4
11: PCLK = CK_AHB / 8

PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock

[1:0] I2C0PCLK I2C0 Peripheral Clock Selection

00: PCLK = CK_AHB
01: PCLK = CK_AHB / 2
10: PCLK = CK_AHB / 4
11: PCLK = CK_AHB / 8

PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock

6 Clock Control Unit (CKCU)

Rev. 1.00 91 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

APB Peripheral Clock Selection Register 1 – APBPCSR1

This register species APB peripheral clock prescaler selection.

Offset: 0x03C

Reset value: 0x0000_0000

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

VDDRPCLK WDTRPCLK

Type/Reset RW 0 RW 0 RW 0 RW 0

7 6 5 4 3 2 1 0

Reserved

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

ADCCPCLK EXTIPCLK AFIOPCLK

Reserved

6 Clock Control Unit (CKCU)

Bits Field Descriptions

[15:14] VDDRCLK VDD Domain Register Access Clock Selection

00: PCLK = CK_AHB / 4
01: PCLK = CK_AHB / 8
10: PCLK = CK_AHB / 16
11: PCLK = CK_AHB / 32

PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock

[13:12] WDTRPCLK WDT Register Access Clock Selection

00: PCLK = CK_AHB
01: PCLK = CK_AHB / 2
10: PCLK = CK_AHB / 4
11: PCLK = CK_AHB / 8

PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock

[5:4] ADCCPCLK ADC Controller Peripheral Clock Selection

00: PCLK = CK_AHB
01: PCLK = CK_AHB / 2
10: PCLK = CK_AHB / 4
11: PCLK = CK_AHB / 8

PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock

[3:2] EXTIPCLK EXTI Peripheral Clock Selection

00: PCLK = CK_AHB
01: PCLK = CK_AHB / 2
10: PCLK = CK_AHB / 4
11: PCLK = CK_AHB / 8

PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock

[1:0] AFIOPCLK AFIO Peripheral Clock Selection

00: PCLK = CK_AHB
01: PCLK = CK_AHB / 2
10: PCLK = CK_AHB / 4
11: PCLK = CK_AHB / 8

PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock

Rev. 1.00 92 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

HSI Control Register – HSICR

This register is to control the frequency trimming of HSI RC oscillation.

Offset: 0x040

Reset value: 0xXXXX_0000 where X is undened

31 30 29 28 27 26 25 24

Reserved

Type/Reset RO X RO X RO X RO X RO X

23 22 21 20 19 18 17 16

HSIFINE

Type/Reset RW X RW X RW X RW X RW X RW X RW X RW X

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

FLOCK

Type/Reset RO 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

REFCLKSEL

TMSEL ATMSEL LTRSEL ATCEN TRIMEN

HSICOARSE

6 Clock Control Unit (CKCU)

Bits Field Descriptions

[28:24] HSICOARSE HSI Clock Coarse Trimming Value

These bits are initialized automatically at startup. They are adjusted by factory
trimming and cannot trim by program.

[23:16] HSIFINE HSI Clock Fine Trimming Value

These bits are initialized automatically at startup. They are also adjusted by factory
trimming. But these bits provide an additional user-programmable trimming value
that is added to the HSICOARSE[4:0] bits to get more accurate or compensate

the variations in voltage and temperature that inuence the frequency of the HSI.

It can be programmed by software or automatically adjusted by the Auto Trimming
Controller (ATC) with an external reference clock.

[7] FLOCK Frequency Lock

0: HSI frequency is not trimmed into target range
1: HSI frequency is trimmed into target range

[6:5] REFCLKSEL Reference Clock Selection

0x: Select 32.768 kHz external low speed clock source (LSE)
1x: Select external pin (CKIN) 1 kHz pulse

These bits are used to select the reference clock for the HSI Auto Trimming Controller.

[4] TMSEL Trimming Mode Selection

0: Automatic by Auto Trimming Controller
1: Manual by user program

This bit is used to select the HSI RC oscillator trimming function by ATC hardware
or user programming via the HSIFINE[7:0] bits in the HSI Control Register.

[3] ATMSEL Automatic Trimming Mode Selection

0: Auto Trimming Controller is used binary search to approach the target range
1: Auto Trimming Controller is used linear search to approach the target range

This bit is selected the automatic trimming method by ATC hardware for HSI RC oscillator.

[2] LTRSEL Lock Target Range Selection

0: 0.1 % variation
1: 0.2 % variation

This bit is selected the lock target range of the internal HSI RC oscillator trimming
function for 0.1 % or 0.2 % variation.

Rev. 1.00 93 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Bits Field Descriptions

[1] ATCEN ATC Enable

0: Disable Auto Trimming Controller
1: Enable Auto Trimming Controller

[0] TRIMEN Trimming Enable

0: HSI Trimming is disable
1: HSI Trimming is enable

The bit enables the HSI RC oscillator trimming function by ATC hardware or user
programming.

HSI Auto Trimming Counter Register – HSIATCR

This register contains the counter value of the HSI auto trimming controller.

Offset: 0x044

Reset value: 0x0000_0000

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

Reserved ATCNT

Type/Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0

7 6 5 4 3 2 1 0

ATCNT

Type/Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0

6 Clock Control Unit (CKCU)

Bits Field Descriptions

[13:0] ATCNT Auto Trimming Counter

These bits contain the counter value of the HSI auto trimming controller.

Rev. 1.00 94 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

APB Peripheral Clock Selection Register 2 – APBPCSR2

This register species APB peripheral clock prescaler selection.

Offset: 0x048

Reset value: 0x0000_0000

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved PWM1PCLK PWM0PCLK

Type/Reset RW 0 RW 0 RW 0 RW 0

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved

Type/Reset

6 Clock Control Unit (CKCU)

Bits Field Descriptions

[19:18] PWM1PCLK PWM1 Peripheral Clock Selection

00: PCLK = CK_AHB
01: PCLK = CK_AHB / 2
10: PCLK = CK_AHB / 4
11: PCLK = CK_AHB / 8

PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock

[17:16] PWM0PCLK PWM0 Peripheral Clock Selection

00: PCLK = CK_AHB
01: PCLK = CK_AHB / 2
10: PCLK = CK_AHB / 4
11: PCLK = CK_AHB / 8

PCLK = Peripheral Clock; CK_AHB = AHB and CPU clock

Rev. 1.00 95 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

MCU Debug Control Register – MCUDBGCR

This register species debug control of MCU.

Offset: 0x304

Reset value: 0x0000_0000

31 30 29 28 27 26 25 24

DBPWM1 DBPWM0 Reserved

Type/Reset RW 0 RW 0

23 22 21 20 19 18 17 16

Reserved DBUR1 DBUR0 DBBFTM1 DBBFTM0

Type/Reset RW 0 RW 0 RW 0 RW 0

15 14 13 12 11 10 9 8

Reserved DBDSLP2 DBI2C1 DBI2C0 DBSPI1 DBSPI0 Reserved DBUSR

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

7 6 5 4 3 2 1 0

Reserved DBGPTM Reserved DBMCTM DBWDT Reserved DBDSLP1 DBSLP

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0

6 Clock Control Unit (CKCU)

Bits Field Descriptions

[31] DBPWM1 PWM1 Debug Mode Enable

0: PWM1 counter continues to count even if the core is halted
1: PWM1 counter is stopped when the core is halted

Set and reset by software.

[30] DBPWM0 PWM0 Debug Mode Enable

0: PWM0 counter continues to count even if the core is halted
1: PWM0 counter is stopped when the core is halted

Set and reset by software.

[19] DBUR1 UART1 Debug Mode Enable

0: Same behavior as in normal mode
1: UART1 timeout is frozen when the core is halted

Set and reset by software.

[18] DBUR0 UART0 Debug Mode Enable

0: Same behavior as in normal mode
1: UART0 timeout is frozen when the core is halted

Set and reset by software.

[17] DBBFTM1 BFTM1 Debug Mode Enable

0: BFTM1 counter continues even if the core is halted
1: BFTM1 counter is stopped when the core is halted

Set and reset by software.

[16] DBBFTM0 BFTM0 Debug Mode Enable

0: BFTM0 counter continues to count even if the core is halted
1: BFTM0 counter is stopped when the core is halted

Set and reset by software.

[14] DBDSLP2 Debug Deep-Sleep2

0: LDO = Off (but turn on DMOS), FCLK = Off and HCLK = Off in Deep-Sleep2 mode
1: LDO = On, FCLK = On and HCLK = On in Deep-Sleep2 mode

Set and reset by software.

Rev. 1.00 96 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Bits Field Descriptions

[13] DBI2C1 I2C1 Debug Mode Enable

0: Same behavior as in normal mode
1: I2C1 timeout is frozen when the core is halted

Set and reset by software.

[12] DBI2C0 I2C0 Debug Mode Enable

0: Same behavior as in normal mode
1: I2C0 timeout is frozen when the core is halted

Set and reset by software.

[11] DBSPI1 SPI1 Debug Mode Enable

0: Same behavior as in normal mode
1: SPI1 FIFO timeout is frozen when the core is halted

Set and reset by software.

[10] DBSPI0 SPI0 Debug Mode Enable

0: Same behavior as in normal mode
1: SPI0 FIFO timeout is frozen when the core is halted

Set and reset by software.

[8] DBUSR USART Debug Mode Enable

0: Same behavior as in normal mode
1: USART timeout is frozen when the core is halted

Set and reset by software.

[6] DBGPTM GPTM Debug Mode Enable

0: GPTM counter continues to count even if the core is halted
1: GPTM counter is stopped when the core is halted

Set and reset by software.

[4] DBMCTM MCTM Debug Mode Enable

0: MCTM counter continues even if the core is halted
1: MCTM counter is stopped when the core is halted

Set and reset by software.

[3] DBWDT Watchdog Timer Debug Mode Enable

0: Watchdog Timer counter continues to count even if the core is halted
1: Watchdog Timer counter is stopped when the core is halted

Set and reset by software.

[1] DBDSLP1 Debug Deep-Sleep1

0: LDO = Low power mode, FCLK = Off and HCLK = Off in Deep-Sleep1 mode
1: LDO = On, FCLK = On and HCLK = On in Deep-Sleep1 mode

Set and reset by software.

[0] DBSLP Debug Sleep Mode

0: LDO = On, FCLK = On and HCLK = Off in Sleep mode
1: LDO = On, FCLK = On and HCLK = On in Sleep mode

Set and reset by software.

6 Clock Control Unit (CKCU)

Rev. 1.00 97 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

7 Reset Control Unit (RSTCU)

Introduction

The Reset Control Unit, RSTCU, has three kinds of reset, the power on reset, system reset and

APB unit reset. The power on reset, known as a cold reset, resets the full system during a power

up. A system reset resets the processor core and peripheral IP components with the exception of
the debug port controller. The resets can be triggered by an external signal, internal events and the
reset generators. More information about these resets will be described in the following section.

1.5 V Core

V

DD15

V

DD

nRST

V

DD

WDTRST

Power

RESET

Brown Out

Detector

RESET

V

DD

Domain

POR

POR15

BODRST

Filter

SYSRESETREQ

POR

Reset

generator

Filter

Filter

WDT_RSTn

----

Filter

PWCURST

Delay

RTC/PWRCU reset

WDT reset

SYSRESETREQPORRESETn

SYSRESETn

PORRESETn

Cortex®-M0+RSTCU

SYSRESETREQ

HRESETn

NVIC

HRESETn

CM0+ Core

CORERESTn

System Components

(BusMatrix, PMU)

System Debug

Components

7 Reset Control Unit (RSTCU)

USRRST

Reset

generator

USART reset

Figure 17. RSTCU Block Diagram

Rev. 1.00 98 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Functional Descriptions

Power On Reset

The Power on reset, POR, is generated by either an external reset or the internal reset generator.

Both types have an internal lter to prevent glitches from causing erroneous reset operations. By
referring to Figure 18, the POR15 active low signal will be de-asserted when the internal LDO

voltage regulator is ready to provide a 1.5 V power. In addition to the POR15 signal, the Power

Control Unit, PWRCU, will assert the BODF signal as a Power Down Reset, PDR, when the
BODEN bit in the LVDCSR register is set and the brown-out event occurs. For more details about

the PWRCU function, refer to the PWRCU chapter.

V

DD

V

DD15

7 Reset Control Unit (RSTCU)

t

1

PORRESETn

SYSRESETn

* This timing is dependent on the internal LDO regulator output capacitor value.

Figure 18. Power On Reset Sequence

System Reset

A system reset is generated by a power on reset (PORRESETn), a Watchdog Timer reset (WDT_RSTn),

nRST pin or a software reset (SYSRESETREQ) event. For more information about SYSRESETREQ

event, refer to the related chapter in the Cortex®-M0+ reference manual.

AHB and APB Unit Reset

The AHB and APB unit reset can be divided into hardware and software resets. A hardware
reset can be generated by either power on reset or system reset for all AHB and APB units.
Each functional IP connected to the AHB and APB buses can be reset individually through the

associated software reset bits in the RSTCU. For example, the application software can generate a

USART reset via the USRRST bit in the APBPRSTR0 register.

t

2

t1= 25 μs *Typical.

= 100 μs

t

t

3

2

= 150 μs

t

3

Rev. 1.00 99 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Register Map

The following table shows the RSTCU registers and reset values.

Table 16. RSTCU Register Map

Register Offset Description Reset Value

GRSR 0x100 Global Reset Status Register 0x0000_0008

AHBPRSTR 0x104 AHB Peripheral Reset Register 0x0000_0000

APBPRSTR0 0x108 APB Peripheral Reset Register 0 0x0000_0000

APBPRSTR1 0x10C APB Peripheral Reset Register 1 0x0000_0000

Register Descriptions

Global Reset Status Register – GRSR

This register species a variety of reset status conditions.

Offset: 0x100

Reset value: 0x0000_0008

7 Reset Control Unit (RSTCU)

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved PORSTF WDTRSTF EXTRSTF NVICRSTF

Type/Reset WC 1 WC 0 WC 0 WC 0

Bits Field Descriptions

[3] PORSTF Core 1.5 V Power On Reset Flag

0: No POR occurred
1: POR occurred

This bit is set by hardware when a power on reset occurs and reset by writing 1 into it.

[2] WDTRSTF Watchdog Timer Reset Flag

0: No Watchdog Timer reset occurred
1: Watchdog Timer occurred

This bit is set by hardware when a watchdog timer reset occurs and reset by writing
1 into it or by hardware when a power on reset occurs.

[1] EXTRSTF External Pin Reset Flag

0: No pin reset occurred
1: Pin reset occurred

This bit is set by hardware when an external pin reset occurs and reset by writing 1
into it or by hardware when a power on reset occurs.

Rev. 1.00 100 of 486 July 31, 2018