Holtek HT32F50231, HT32F50241 User Manual

Holtek 32-Bit Microcontroller with Arm® Cortex®-M0+

HT32F50231/HT32F50241

User Manual

Revision: V1.00 Date: July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Table of Contents

1 Introduction ........................................................................................................... 21

Overview .............................................................................................................................. 21

Features ............................................................................................................................... 22

Device Information ............................................................................................................... 25

Block Diagram ..................................................................................................................... 26

2 Document Conventions ....................................................................................... 27

3 System Architecture ............................................................................................. 28

Arm® Cortex®-M0+ Processor .............................................................................................. 28

Bus Architecture ................................................................................................................... 29

Memory Organization .......................................................................................................... 30

Memory Map ................................................................................................................................... 31

Embedded Flash Memory ............................................................................................................... 33

Embedded SRAM Memory ............................................................................................................. 33

AHB Peripherals ............................................................................................................................. 33

APB Peripherals ............................................................................................................................. 33

Table of Contents

4 Flash Memory Controller (FMC) .......................................................................... 34

Introduction .......................................................................................................................... 34

Features ............................................................................................................................... 34

Functional Descriptions ....................................................................................................... 35

Flash Memory Map ......................................................................................................................... 35

Flash Memory Architecture ............................................................................................................. 36

Booting Conguration ..................................................................................................................... 37

Page Erase ..................................................................................................................................... 38

Mass Erase ..................................................................................................................................... 39

Word Programming ......................................................................................................................... 40

Option Byte Description .................................................................................................................. 41

Page Erase / Program Protection ................................................................................................... 42

Security Protection .......................................................................................................................... 43

Register Map ....................................................................................................................... 44

Register Descriptions ........................................................................................................... 45

Flash Target Address Register – TADR .......................................................................................... 45

Flash Write Data Register – WRDR ............................................................................................... 46

Flash Operation Command Register – OCMR ............................................................................... 47

Flash Operation Control Register – OPCR ..................................................................................... 48

Flash Operation Interrupt Enable Register – OIER ........................................................................ 49

Flash Operation Interrupt and Status Register – OISR .................................................................. 50

Flash Page Erase / Program Protection Status Register – PPSR .................................................. 52

Flash Security Protection Status Register – CPSR ........................................................................ 53

Flash Vector Mapping Control Register – VMCR ........................................................................... 54

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32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Flash Manufacturer and Device ID Register – MDID ...................................................................... 55

Flash Page Number Status Register – PNSR ................................................................................ 56

Flash Page Size Status Register – PSSR ...................................................................................... 57

Device ID Register – DIDR ............................................................................................................. 58

Custom ID Register n – CIDRn, n = 0 ~3 ....................................................................................... 59

5 Power Control Unit (PWRCU) .............................................................................. 60

Introduction .......................................................................................................................... 60

Features ............................................................................................................................... 61

Functional Descriptions ....................................................................................................... 61

VDD Power Domain .......................................................................................................................... 61

1.5 V Power Domain ....................................................................................................................... 63

Operation Modes ............................................................................................................................ 63

Register Map ....................................................................................................................... 64

Register Descriptions ........................................................................................................... 65

Power Control Status Register – PWRSR ...................................................................................... 65

Power Control Register – PWRCR ................................................................................................. 66

Low Voltage / Brown Out Detect Control and Status Register – LVDCSR ..................................... 68

6 Clock Control Unit (CKCU) .................................................................................. 70

Introduction .......................................................................................................................... 70

Features ............................................................................................................................... 72

Function Descriptions .......................................................................................................... 72

High Speed External Crystal Oscillator – HSE ............................................................................... 72

High Speed Internal RC Oscillator – HSI ........................................................................................ 73

Auto Trimming of High Speed Internal RC Oscillator – HSI ............................................................ 73

Low Speed External Crystal Oscillator – LSE ................................................................................. 75

Low Speed Internal RC Oscillator – LSI ......................................................................................... 75

Clock Ready Flag ........................................................................................................................... 75

System Clock (CK_SYS) Selection ................................................................................................ 75

HSE Clock Monitor ......................................................................................................................... 76

Clock Output Capability .................................................................................................................. 76

Register Map ....................................................................................................................... 77

Register Descriptions ........................................................................................................... 78

Global Clock Conguration Register – GCFGR .............................................................................. 78

Global Clock Control Register – GCCR .......................................................................................... 79

Global Clock Status Register – GCSR ........................................................................................... 81

Global Clock Interrupt Register – GCIR .......................................................................................... 82

AHB Conguration Register – AHBCFGR ...................................................................................... 83

AHB Clock Control Register – AHBCCR ........................................................................................ 84

APB Conguration Register – APBCFGR ....................................................................................... 85

APB Clock Control Register 0 – APBCCR0 .................................................................................... 86

APB Clock Control Register 1 – APBCCR1 .................................................................................... 87

Clock Source Status Register – CKST ........................................................................................... 89

Table of Contents

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32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

APB Peripheral Clock Selection Register 0 – APBPCSR0 ............................................................. 90

APB Peripheral Clock Selection Register 1 – APBPCSR1 ............................................................. 92

HSI Control Register – HSICR ........................................................................................................ 93

HSI Auto Trimming Counter Register – HSIATCR .......................................................................... 94

APB Peripheral Clock Selection Register 2 – APBPCSR2 ............................................................. 95

MCU Debug Control Register – MCUDBGCR ................................................................................ 96

7 Reset Control Unit (RSTCU) ................................................................................ 98

Introduction .......................................................................................................................... 98

Functional Descriptions ....................................................................................................... 99

Power On Reset ............................................................................................................................. 99

System Reset ................................................................................................................................. 99

AHB and APB Unit Reset ................................................................................................................ 99

Register Map ..................................................................................................................... 100

Register Descriptions ......................................................................................................... 100

Global Reset Status Register – GRSR ......................................................................................... 100

AHB Peripheral Reset Register – AHBPRSTR ............................................................................. 101

APB Peripheral Reset Register 0 – APBPRSTR0 ........................................................................ 102

APB Peripheral Reset Register 1 – APBPRSTR1 ........................................................................ 103

Table of Contents

8 General Purpose I/O (GPIO) ............................................................................... 105

Introduction ........................................................................................................................ 105

Features ............................................................................................................................. 106

Functional Descriptions ..................................................................................................... 106

Default GPIO Pin Conguration .................................................................................................... 106

General Purpose I/O – GPIO ........................................................................................................ 106

GPIO Locking Mechanism ............................................................................................................ 108

Register Map ..................................................................................................................... 108

Register Descriptions ......................................................................................................... 109

Port A Data Direction Control Register – PADIRCR ..................................................................... 109

Port A Input Function Enable Control Register – PAINER .............................................................110

Port A Pull-Up Selection Register – PAPUR ..................................................................................111

Port A Pull-Down Selection Register – PAPDR .............................................................................112

Port A Open-Drain Selection Register – PAODR ...........................................................................113

Port A Output Drive Current Selection Register – PADRVR ..........................................................114

Port A Lock Register – PALOCKR .................................................................................................115

Port A Data Input Register – PADINR ............................................................................................116

Port A Output Data Register – PADOUTR .....................................................................................116

Port A Output Set / Reset Control Register – PASRR ...................................................................117

Port A Output Reset Register – PARR ...........................................................................................118

Port A Sink Current Enhanced Selection Register – PASCER ......................................................118

Port B Data Direction Control Register – PBDIRCR ......................................................................119

Port B Input Function Enable Control Register – PBINER ........................................................... 120

Port B Pull-Up Selection Register – PBPUR ................................................................................ 121

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32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Port B Pull-Down Selection Register – PBPDR ............................................................................ 122

Port B Open-Drain Selection Register – PBODR ......................................................................... 123

Port B Output Drive Current Selection Register – PBDRVR ........................................................ 124

Port B Lock Register – PBLOCKR ................................................................................................ 125

Port B Data Input Register – PBDINR .......................................................................................... 126

Port B Output Data Register – PBDOUTR ................................................................................... 126

Port B Output Set / Reset Control Register – PBSRR .................................................................. 127

Port B Output Reset Register – PBRR ......................................................................................... 128

Port B Sink Current Enhanced Selection Register – PBSCER ..................................................... 128

Port C Data Direction Control Register – PCDIRCR .................................................................... 129

Port C Input Function Enable Control Register – PCINER ........................................................... 130

Port C Pull-Up Selection Register – PCPUR ................................................................................ 131

Port C Pull-Down Selection Register – PCPDR ........................................................................... 132

Port C Open Drain Selection Register – PCODR ......................................................................... 133

Port C Output Current Drive Selection Register – PCDRVR ........................................................ 134

Port C Lock Register – PCLOCKR ............................................................................................... 135

Port C Data Input Register – PCDINR .......................................................................................... 136

Port C Output Data Register – PCDOUTR ................................................................................... 136

Port C Output Set / Reset Control Register – PCSRR ................................................................. 137

Port C Output Reset Register – PCRR ......................................................................................... 138

Port C Sink Current Enhanced Selection Register – PCSCER .................................................... 138

Table of Contents

9 Alternate Function Input / Output Control Unit (AFIO) .................................... 139

Introduction ........................................................................................................................ 139

Features ............................................................................................................................. 140

Functional Descriptions ..................................................................................................... 140

External Interrupt Pin Selection .................................................................................................... 140

Alternate Function ......................................................................................................................... 141

Lock Mechanism .......................................................................................................................... 141

Register Map ..................................................................................................................... 141

Register Descriptions ......................................................................................................... 142

EXTI Source Selection Register 0 – ESSR0 ................................................................................ 142

EXTI Source Selection Register 1 – ESSR1 ................................................................................ 143

GPIO x Conguration Low Register – GPxCFGLR, x = A, B, C ................................................... 144

GPIO x Conguration High Register – GPxCFGHR, x = A, B, C .................................................. 145

10 Nested Vectored Interrupt Controller (NVIC) .................................................. 146

Introduction ........................................................................................................................ 146

Features ............................................................................................................................. 147

Function Descriptions ........................................................................................................ 148

SysTick Calibration ....................................................................................................................... 148

Register Map ..................................................................................................................... 148

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32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

11 External Interrupt / Event Controller (EXTI) .................................................... 149

Introduction ........................................................................................................................ 149

Features ............................................................................................................................. 149

Function Descriptions ........................................................................................................ 150

Wakeup Event Management......................................................................................................... 150

External Interrupt / Event Line Mapping ....................................................................................... 151

Interrupt and Debounce ................................................................................................................ 151

Register Map ..................................................................................................................... 152

Register Descriptions ......................................................................................................... 153

EXTI Interrupt n Conguration Register – EXTICFGRn, n = 0 ~ 15 ............................................. 153

EXTI Interrupt Control Register – EXTICR ................................................................................... 154

EXTI Interrupt Edge Flag Register – EXTIEDGEFLGR ................................................................ 155

EXTI Interrupt Edge Status Register – EXTIEDGESR ................................................................. 156

EXTI Interrupt Software Set Command Register – EXTISSCR .................................................... 157

EXTI Interrupt Wakeup Control Register – EXTIWAKUPCR ........................................................ 158

EXTI Interrupt Wakeup Polarity Register – EXTIWAKUPPOLR ................................................... 159

EXTI Interrupt Wakeup Flag Register – EXTIWAKUPFLG ........................................................... 160

Table of Contents

12 Analog to Digital Converter (ADC) .................................................................. 161

Introduction ........................................................................................................................ 161

Features ............................................................................................................................. 162

Function Descriptions ........................................................................................................ 163

ADC Clock Setup .......................................................................................................................... 163

Channel Selection ......................................................................................................................... 163

Conversion Mode .......................................................................................................................... 163

Start Conversion on External Event .............................................................................................. 166

Sampling Time Setting .................................................................................................................. 167

Data Format .................................................................................................................................. 167

Analog Watchdog.......................................................................................................................... 167

Interrupts ....................................................................................................................................... 168

Register Map ..................................................................................................................... 169

Register Descriptions ......................................................................................................... 170

ADC Conversion Control Register – ADCCR ............................................................................... 170

ADC Conversion List Register 0 – ADCLST0 .............................................................................. 172

ADC Conversion List Register 1 – ADCLST1 ............................................................................... 173

ADC Input Sampling Time Register – ADCSTR ........................................................................... 174

ADC Conversion Data Register y – ADCDRy, y = 0 ~ 7 ............................................................... 175

ADC Trigger Control Register – ADCTCR .................................................................................... 176

ADC Trigger Source Register – ADCTSR ..................................................................................... 177

ADC Watchdog Control Register – ADCWCR .............................................................................. 178

ADC Watchdog Threshold Register – ADCTR .............................................................................. 180

ADC Interrupt Enable Register – ADCIER ................................................................................... 181

ADC Interrupt Raw Status Register – ADCIRAW ......................................................................... 182

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32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

ADC Interrupt Status Register – ADCISR ..................................................................................... 183

ADC Interrupt Clear Register – ADCICLR .................................................................................... 184

13 General-Purpose Timer (GPTM) ...................................................................... 185

Introduction ........................................................................................................................ 185

Features ............................................................................................................................. 185

Functional Descriptions ..................................................................................................... 186

Counter Mode ............................................................................................................................... 186

Clock Controller ............................................................................................................................ 189

Trigger Controller .......................................................................................................................... 190

Slave Controller ............................................................................................................................ 191

Master Controller .......................................................................................................................... 193

Channel Controller ........................................................................................................................ 194

Input Stage ................................................................................................................................... 197

Quadrature Decoder ..................................................................................................................... 199

Output Stage ................................................................................................................................. 201

Update Management .................................................................................................................... 205

Single Pulse Mode ........................................................................................................................ 206

Asymmetric PWM Mode ............................................................................................................... 208

Timer Interconnection ................................................................................................................... 209

Trigger ADC Start.......................................................................................................................... 212

Register Map ..................................................................................................................... 212

Register Descriptions ......................................................................................................... 213

Timer Counter Conguration Register – CNTCFR ....................................................................... 213

Timer Mode Conguration Register – MDCFR ............................................................................. 214

Timer Trigger Conguration Register – TRCFR ............................................................................ 217

Timer Counter Register – CTR ..................................................................................................... 218

Channel 0 Input Conguration Register – CH0ICFR .................................................................... 219

Channel 1 Input Conguration Register – CH1ICFR .................................................................... 220

Channel 2 Input Conguration Register – CH2ICFR .................................................................... 222

Channel 3 Input Conguration Register – CH3ICFR .................................................................... 223

Channel 0 Output Conguration Register – CH0OCFR ............................................................... 224

Channel 1 Output Conguration Register – CH1OCFR ............................................................... 226

Channel 2 Output Conguration Register – CH2OCFR ............................................................... 228

Channel 3 Output Conguration Register – CH3OCFR ............................................................... 230

Channel Control Register – CHCTR ............................................................................................. 232

Channel Polarity Conguration Register – CHPOLR .................................................................... 233

Timer Interrupt Control Register – DICTR .................................................................................... 234

Timer Event Generator Register – EVGR ..................................................................................... 235

Timer Interrupt Status Register – INTSR ...................................................................................... 236

Timer Counter Register – CNTR................................................................................................... 238

Timer Prescaler Register – PSCR ................................................................................................ 239

Timer Counter Reload Register – CRR ........................................................................................ 240

Channel 0 Capture / Compare Register – CH0CCR .................................................................... 241

Table of Contents

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32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Channel 1 Capture / Compare Register – CH1CCR .................................................................... 242

Channel 2 Capture / Compare Register – CH2CCR .................................................................... 243

Channel 3 Capture / Compare Register – CH3CCR .................................................................... 244

Channel 0 Asymmetric Compare Register – CH0ACR ................................................................. 245

Channel 1 Asymmetric Compare Register – CH1ACR ................................................................. 245

Channel 2 Asymmetric Compare Register – CH2ACR ................................................................. 246

Channel 3 Asymmetric Compare Register – CH3ACR ................................................................. 246

14 Pulse Width Modulator (PWM) ......................................................................... 247

Introduction ........................................................................................................................ 247

Features ............................................................................................................................. 248

Functional Descriptions ..................................................................................................... 248

Counter Mode ............................................................................................................................... 248

Clock Controller ............................................................................................................................ 251

Trigger Controller .......................................................................................................................... 252

Slave Controller ............................................................................................................................ 253

Master Controller .......................................................................................................................... 255

Channel Controller ........................................................................................................................ 256

Output Stage ................................................................................................................................. 256

Update Management .................................................................................................................... 260

Single Pulse Mode ........................................................................................................................ 260

Asymmetric PWM Mode ............................................................................................................... 263

Timer Interconnection ................................................................................................................... 263

Trigger Peripherals Start ............................................................................................................... 265

Register Map ..................................................................................................................... 266

Register Descriptions ......................................................................................................... 267

Timer Counter Conguration Register – CNTCFR ....................................................................... 267

Timer Mode Conguration Register – MDCFR ............................................................................. 268

Timer Trigger Conguration Register – TRCFR ............................................................................ 271

Timer Counter Register – CTR ..................................................................................................... 272

Channel 0 Output Conguration Register – CH0OCFR ............................................................... 273

Channel 1 Output Conguration Register – CH1OCFR ............................................................... 275

Channel 2 Output Conguration Register – CH2OCFR ............................................................... 277

Channel 3 Output Conguration Register – CH3OCFR ............................................................... 279

Channel Control Register – CHCTR ............................................................................................. 281

Channel Polarity Conguration Register – CHPOLR .................................................................... 282

Timer Interrupt Control Register – DICTR .................................................................................... 283

Timer Event Generator Register – EVGR ..................................................................................... 284

Timer Interrupt Status Register – INTSR ...................................................................................... 285

Timer Counter Register – CNTR................................................................................................... 286

Timer Prescaler Register – PSCR ................................................................................................ 287

Timer Counter Reload Register – CRR ........................................................................................ 287

Channel 0 Compare Register – CH0CR ....................................................................................... 288

Channel 1 Compare Register – CH1CR ....................................................................................... 288

Channel 2 Compare Register – CH2CR ....................................................................................... 289

Table of Contents

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32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Channel 3 Compare Register – CH3CR ....................................................................................... 289

Channel 0 Asymmetric Compare Register – CH0ACR ................................................................. 290

Channel 1 Asymmetric Compare Register – CH1ACR ................................................................. 290

Channel 2 Asymmetric Compare Register – CH2ACR ................................................................. 291

Channel 3 Asymmetric Compare Register – CH3ACR ................................................................. 291

15 Basic Function Timer (BFTM) .......................................................................... 292

Introduction ........................................................................................................................ 292

Features ............................................................................................................................. 292

Functional Description ....................................................................................................... 293

Repetitive Mode ............................................................................................................................ 293

One Shot Mode ............................................................................................................................. 294

Trigger ADC Start.......................................................................................................................... 294

Register Map ..................................................................................................................... 295

Register Descriptions ......................................................................................................... 295

BFTM Control Register – BFTMCR .............................................................................................. 295

BFTM Status Register – BFTMSR ................................................................................................ 296

BFTM Counter Value Register – BFTMCNTR .............................................................................. 297

BFTM Compare Value Register – BFTMCMPR ........................................................................... 297

16 Motor Control Timer (MCTM) ........................................................................... 298

Introduction ........................................................................................................................ 298

Features ............................................................................................................................. 299

Functional Descriptions ..................................................................................................... 299

Counter Mode ............................................................................................................................... 299

Clock Controller ............................................................................................................................ 303

Trigger Controller .......................................................................................................................... 304

Slave Controller ............................................................................................................................ 305

Master Controller .......................................................................................................................... 307

Channel Controller ........................................................................................................................ 308

Input Stage ................................................................................................................................... 309

Output Stage ..................................................................................................................................311

Update Management .................................................................................................................... 322

Single Pulse Mode ........................................................................................................................ 324

Timer Interconnection ................................................................................................................... 327

Trigger ADC Start.......................................................................................................................... 331

Lock Level Table ........................................................................................................................... 331

Register Map ..................................................................................................................... 331

Register Descriptions ......................................................................................................... 332

Timer Counter Conguration Register – CNTCFR ....................................................................... 332

Timer Mode Conguration Register – MDCFR ............................................................................. 334

Timer Trigger Conguration Register – TRCFR ............................................................................ 337

Timer Control Register – CTR ...................................................................................................... 338

Channel 0 Input Conguration Register – CH0ICFR .................................................................... 339

Table of Contents

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32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Channel 1 Input Conguration Register – CH1ICFR .................................................................... 340

Channel 2 Input Conguration Register – CH2ICFR .................................................................... 342

Channel 3 Input Conguration Register – CH3ICFR .................................................................... 343

Channel 0 Output Conguration Register – CH0OCFR ............................................................... 345

Channel 1 Output Conguration Register – CH1OCFR ............................................................... 347

Channel 2 Output Conguration Register – CH2OCFR ............................................................... 349

Channel 3 Output Conguration Register – CH3OCFR ............................................................... 351

Channel Control Register – CHCTR ............................................................................................. 353

Channel Polarity Conguration Register – CHPOLR .................................................................... 355

Channel Break Conguration Register – CHBRKCFR ................................................................. 356

Channel Break Control Register – CHBRKCTR ........................................................................... 357

Timer Interrupt Control Register – DICTR .................................................................................... 359

Timer Event Generator Register – EVGR ..................................................................................... 360

Timer Interrupt Status Register – INTSR ...................................................................................... 362

Timer Counter Register – CNTR................................................................................................... 364

Timer Prescaler Register – PSCR ................................................................................................ 365

Timer Counter Reload Register – CRR ........................................................................................ 366

Timer Repetition Register – REPR ............................................................................................... 366

Channel 0 Capture/Compare Register – CH0CCR ...................................................................... 367

Channel 1 Capture/Compare Register – CH1CCR ...................................................................... 368

Channel 2 Capture/Compare Register – CH2CCR ...................................................................... 369

Channel 3 Capture/Compare Register – CH3CCR ...................................................................... 370

Channel 0 Asymmetric Compare Register – CH0ACR ................................................................. 371

Channel 1 Asymmetric Compare Register – CH1ACR ................................................................. 371

Channel 2 Asymmetric Compare Register – CH2ACR ................................................................. 372

Channel 3 Asymmetric Compare Register – CH3ACR ................................................................. 372

Table of Contents

17 Real Time Clock (RTC) ..................................................................................... 373

Introduction ........................................................................................................................ 373

Features ............................................................................................................................. 373

Functional Descriptions ..................................................................................................... 374

RTC Related Register Reset ........................................................................................................ 374

Low Speed Clock Conguration ................................................................................................... 374

RTC Counter Operation ................................................................................................................ 374

Interrupt and Wakeup Control ....................................................................................................... 374

RTCOUT Output Pin Conguration............................................................................................... 375

Register Map ..................................................................................................................... 376

Register Descriptions ......................................................................................................... 376

RTC Counter Register – RTCCNT ................................................................................................ 376

RTC Compare Register – RTCCMP ............................................................................................. 377

RTC Control Register – RTCCR ................................................................................................... 378

RTC Status Register – RTCSR..................................................................................................... 380

RTC Interrupt and Wakeup Enable Register – RTCIWEN ........................................................... 381

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32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

18 Watchdog Timer (WDT) .................................................................................... 382

Introduction ........................................................................................................................ 382

Features ............................................................................................................................. 382

Functional Description ....................................................................................................... 383

Register Map ..................................................................................................................... 385

Register Descriptions ......................................................................................................... 385

Watchdog Timer Control Register – WDTCR ............................................................................... 385

Watchdog Timer Mode Register 0 – WDTMR0............................................................................. 386

Watchdog Timer Mode Register 1 – WDTMR1............................................................................. 387

Watchdog Timer Status Register – WDTSR ................................................................................. 388

Watchdog Timer Protection Register – WDTPR ........................................................................... 389

Watchdog Timer Clock Selection Register – WDTCSR ............................................................... 390

19 Inter-Integrated Circuit (I2C) ............................................................................. 391

Introduction ........................................................................................................................ 391

Features ............................................................................................................................. 392

Functional Descriptions ..................................................................................................... 392

Two-Wire Serial Interface ............................................................................................................. 392

START and STOP Conditions ....................................................................................................... 392

Data Validity .................................................................................................................................. 393

Addressing Format ....................................................................................................................... 394

Data Transfer and Acknowledge ................................................................................................... 396

Clock Synchronization .................................................................................................................. 397

Arbitration ..................................................................................................................................... 397

General Call Addressing ............................................................................................................... 398

Bus Error ....................................................................................................................................... 398

Address Mask Enable ................................................................................................................... 398

Address Snoop ............................................................................................................................. 398

Operation Mode ............................................................................................................................ 398

Conditions of Holding SCL Line .................................................................................................... 404

I2C Timeout Function .................................................................................................................... 405

Register Map ..................................................................................................................... 405

Register Descriptions ......................................................................................................... 406

I2C Control Register – I2CCR ....................................................................................................... 406

I2C Interrupt Enable Register – I2CIER ........................................................................................ 407

I2C Address Register – I2CADDR ................................................................................................. 409

I2C Status Register – I2CSR ......................................................................................................... 410

I2C SCL High Period Generation Register – I2CSHPGR .............................................................. 413

I2C SCL Low Period Generation Register – I2CSLPGR ............................................................... 414

I2C Data Register – I2CDR ........................................................................................................... 415

I2C Target Register – I2CTAR ....................................................................................................... 416

I2C Address Mask Register – I2CADDMR .................................................................................... 417

I2C Address Snoop Register – I2CADDSR ................................................................................... 418

I2C Timeout Register – I2CTOUT.................................................................................................. 419

Table of Contents

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32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

20 Serial Peripheral Interface (SPI) ...................................................................... 420

Introduction ........................................................................................................................ 420

Features ............................................................................................................................. 421

Function Descriptions ........................................................................................................ 421

Master Mode ................................................................................................................................. 421

Slave Mode ................................................................................................................................... 421

SPI Serial Frame Format .............................................................................................................. 422

Status Flags .................................................................................................................................. 426

Register Map ..................................................................................................................... 428

Register Descriptions ......................................................................................................... 429

SPI Control Register 0 – SPICR0 ................................................................................................. 429

SPI Control Register 1 – SPICR1 ................................................................................................. 431

SPI Interrupt Enable Register – SPIIER ....................................................................................... 432

SPI Clock Prescaler Register – SPICPR ...................................................................................... 433

SPI Data Register – SPIDR .......................................................................................................... 434

SPI Status Register – SPISR ........................................................................................................ 435

SPI FIFO Control Register – SPIFCR ........................................................................................... 437

SPI FIFO Status Register – SPIFSR ............................................................................................ 438

SPI FIFO Time Out Counter Register – SPIFTOCR ..................................................................... 439

Table of Contents

21 Universal Synchronous Asynchronous Receiver Transmitter (USART) ..... 440

Introduction ........................................................................................................................ 440

Features ............................................................................................................................. 441

Functional Descriptions ..................................................................................................... 441

Serial Data Format ........................................................................................................................ 441

Baud Rate Generation .................................................................................................................. 442

Hardware Flow Control ................................................................................................................. 443

IrDA ............................................................................................................................................... 444

RS485 Mode ................................................................................................................................. 446

Synchronous Master Mode ........................................................................................................... 448

Interrupts and Status .................................................................................................................... 450

Register Map ..................................................................................................................... 450

Register Descriptions ......................................................................................................... 451

USART Data Register – USRDR .................................................................................................. 451

USART Control Register – USRCR .............................................................................................. 452

USART FIFO Control Register – USRFCR................................................................................... 454

USART Interrupt Enable Register – USRIER ............................................................................... 455

USART Status & Interrupt Flag Register – USRSIFR................................................................... 457

USART Timing Parameter Register – USRTPR ........................................................................... 459

USART IrDA Control Register – IrDACR ...................................................................................... 460

USART RS485 Control Register – RS485CR............................................................................... 461

USART Synchronous Control Register – SYNCR ........................................................................ 462

USART Divider Latch Register – USRDLR................................................................................... 463

USART Test Register – USRTSTR ............................................................................................... 464

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32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

22 Universal Asynchronous Receiver Transmitter (UART) ................................ 465

Introduction ........................................................................................................................ 465

Features ............................................................................................................................. 466

Function Descriptions ........................................................................................................ 466

Serial Data Format ........................................................................................................................ 466

Baud Rate Generation .................................................................................................................. 467

Interrupts and Status .................................................................................................................... 468

Register Map ..................................................................................................................... 468

Register Descriptions ......................................................................................................... 469

UART Data Register – URDR ....................................................................................................... 469

UART Control Register – URCR ................................................................................................... 470

UART Interrupt Enable Register – URIER .................................................................................... 471

UART Status & Interrupt Flag Register – URSIFR ....................................................................... 472

UART Divider Latch Register – URDLR ....................................................................................... 474

UART Test Register – URTSTR .................................................................................................... 475

Table of Contents

23 Divider (DIV) ...................................................................................................... 476

Introduction ........................................................................................................................ 476

Features ............................................................................................................................. 476

Functional Descriptions ..................................................................................................... 476

Register Map ..................................................................................................................... 477

Register Descriptions ......................................................................................................... 477

Divider Control Register – CR ...................................................................................................... 477

Dividend Data Register – DDR ..................................................................................................... 478

Divisor Data Register – DSR ........................................................................................................ 478

Quotient Data Register – QTR ...................................................................................................... 479

Remainder Data Register – RMR ................................................................................................. 479

24 Cyclic Redundancy Check (CRC) .................................................................... 480

Introduction ....................................................................................................................... 480

Features ............................................................................................................................. 480

Functional Descriptions ..................................................................................................... 481

CRC Computation ......................................................................................................................... 481

Byte and Bit Reversal for CRC Computation ................................................................................ 481

Register Map ..................................................................................................................... 482

Register Descriptions ......................................................................................................... 482

CRC Control Register – CRCCR .................................................................................................. 482

CRC Seed Register – CRCSDR ................................................................................................... 483

CRC Checksum Register – CRCCSR .......................................................................................... 484

CRC Data Register – CRCDR ...................................................................................................... 485

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32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

List of Tables

Table 1. Features and Peripheral List ..................................................................................................... 25

Table 2. Document Conventions ............................................................................................................. 27

Table 3. Register Map ............................................................................................................................. 32

Table 4. Flash Memory and Option Byte ................................................................................................. 36

Table 5. Booting Modes .......................................................................................................................... 37

Table 6. Option Byte Memory Map ......................................................................................................... 41

Table 7. Access Permission of Protected Main Flash Page .................................................................... 42

Table 8. Access Permission When Security Protection is Enabled ......................................................... 43

Table 9. FMC Register Map .................................................................................................................... 44

Table 10. Operation Mode Denitions ..................................................................................................... 63

Table 11. Enter / Exit Power Saving Modes ............................................................................................ 64

Table 12. Power Status After System Reset ........................................................................................... 64

Table 13. PWRCU Register Map ............................................................................................................ 64

Table 14. CKOUT Clock Source ............................................................................................................. 76

Table 15. CKCU Register Map ............................................................................................................... 77

Table 16. RSTCU Register Map ........................................................................................................... 100

Table 17. AFIO, GPIO and I/O Pad Control Signal True Table.............................................................. 107

Table 18. GPIO Register Map ............................................................................................................... 108

Table 19. AFIO Selection for Peripheral Map Example ......................................................................... 141

Table 20. AFIO Register Map ................................................................................................................ 141

Table 21. Exception Types .................................................................................................................... 146

Table 22. NVIC Register Map ............................................................................................................... 148

Table 23. EXTI Register Map ................................................................................................................ 152

Table 24. Data Format in ADCDR [15:0] ............................................................................................... 167

Table 25. A/D Converter Register Map ................................................................................................. 169

Table 26. Counting Direction and Encoding Signals ............................................................................. 200

Table 27. Compare Match Output Setup .............................................................................................. 201

Table 28. GPTM Register Map ............................................................................................................. 212

Table 29. GPTM Internal Trigger Connection ....................................................................................... 217

Table 30. Compare Match Output Setup .............................................................................................. 257

Table 31. PWM Register Map ............................................................................................................... 266

Table 32. PWM Internal Trigger Connection ......................................................................................... 271

Table 33. BFTM Register Map .............................................................................................................. 295

Table 34. Compare Match Output Setup .............................................................................................. 312

Table 35. Output Control Bits for Complementary Output with a Break Event Occurrence .................. 321

Table 36. Lock Level Table.................................................................................................................... 331

Table 37. MCTM Register Map ............................................................................................................. 331

Table 38. MCTM Internal Trigger Connection ....................................................................................... 337

Table 39. LSE Startup Mode Operating Current and Startup Time ....................................................... 374

List of Tables

Rev. 1.00 14 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Table 40. RTCOUT Output Mode and Active Level Setting .................................................................. 375

Table 41. RTC Register Map................................................................................................................. 376

Table 42. Watchdog Timer Register Map .............................................................................................. 385

Table 43. Conditions of Holding SCL line .............................................................................................. 404

Table 44. I2C Register Map ................................................................................................................... 405

Table 45. I2C Clock Setting Example .................................................................................................... 414

Table 46. SPI Interface Format Setup ................................................................................................... 422

Table 47. SPI Mode Fault Trigger Conditions ....................................................................................... 427

Table 48. SPI Master Mode SEL Pin Status ......................................................................................... 427

Table 49. SPI Register Map .................................................................................................................. 428

Table 50. Baud Rate Deviation Error Calculation – CK_USART = 20 MHz .......................................... 443

Table 51. Baud Rate Deviation Error Calculation – CK_USART = 10 MHz .......................................... 443

Table 52. USART Register Map ............................................................................................................ 450

Table 53. Baud Rate Deviation Error Calculation – CK_UART = 20 MHz ............................................ 467

Table 54. Baud Rate Deviation Error Calculation – CK_UART = 10 MHz ............................................ 468

Table 55. UART Register Map .............................................................................................................. 468

Table 56. DIV Register Map .................................................................................................................. 477

Table 57. CRC Register Map ................................................................................................................ 482

List of Tables

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32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

List of Figures

Figure 1. Block Diagram ......................................................................................................................... 26

Figure 2. Cortex®-M0+ Block Diagram .................................................................................................... 29

Figure 3. Bus Architecture ...................................................................................................................... 30

Figure 4. Memory Map ............................................................................................................................ 31

Figure 5. Flash Memory Controller Block Diagram ................................................................................. 34

Figure 6. Flash Memory Map .................................................................................................................. 35

Figure 7. Vector Remapping ................................................................................................................... 37

Figure 8. Page Erase Operation Flowchart ............................................................................................ 38

Figure 9. Mass Erase Operation Flowchart ............................................................................................ 39

Figure 10. Word Programming Operation Flowchart .............................................................................. 40

Figure 11. PWRCU Block Diagram ......................................................................................................... 60

Figure 12. Power On Reset / Power Down Reset Waveform ................................................................. 62

Figure 13. CKCU Block Diagram ............................................................................................................ 71

Figure 14. External Crystal, Ceramic and Resonators for HSE .............................................................. 72

Figure 15. HSI Auto Trimming Block Diagram ........................................................................................ 74

Figure 16. External Crystal, Ceramic and Resonators for LSE .............................................................. 75

Figure 17. RSTCU Block Diagram .......................................................................................................... 98

Figure 18. Power On Reset Sequence ................................................................................................... 99

Figure 19. GPIO Block Diagram ........................................................................................................... 105

Figure 20. AFIO / GPIO Control Signal ................................................................................................. 107

Figure 21. AFIO Block Diagram ............................................................................................................ 139

Figure 22. EXTI Channel Input Selection ............................................................................................. 140

Figure 23. EXTI Block Diagram ............................................................................................................ 149

Figure 24. EXTI Wakeup Event Management ...................................................................................... 150

Figure 25. EXTI Interrupt Debounce Function ...................................................................................... 151

Figure 26. ADC Block Diagram ............................................................................................................ 161

Figure 27. One Shot Conversion Mode ................................................................................................ 164

Figure 28. Continuous Conversion Mode ............................................................................................. 164

Figure 29. Discontinuous Conversion Mode ......................................................................................... 166

Figure 30. GPTM Block Diagram .......................................................................................................... 185

Figure 31. Up-counting Example .......................................................................................................... 186

Figure 32. Down-counting Example ...................................................................................................... 187

Figure 33. Center-aligned Counting Example ....................................................................................... 188

Figure 34. GPTM Clock Source Selection ............................................................................................ 189

Figure 35. Trigger Controller Block ....................................................................................................... 190

Figure 36. Slave Controller Diagram .................................................................................................... 191

Figure 37. GPTM in Restart Mode ........................................................................................................ 191

Figure 38. GPTM in Pause Mode ......................................................................................................... 192

Figure 39. GPTM in Trigger Mode ........................................................................................................ 192

List of Figures

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32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Figure 40. Master GPTMn and Slave GPTMm / MCTMm Connection ................................................. 193

Figure 41. MTO Selection ..................................................................................................................... 193

Figure 42. Capture / Compare Block Diagram ...................................................................................... 194

Figure 43. Input Capture Mode ............................................................................................................. 195

Figure 44. PWM Pulse Width Measurement Example .......................................................................... 196

Figure 45. Channel 0 and Channel 1 Input Stages ............................................................................... 197

Figure 46. Channel 2 and Channel 3 Input Stages ............................................................................... 198

Figure 47. TI0 Digital Filter Diagram with N = 2 .................................................................................... 198

Figure 48. Input Stage and Quadrature Decoder Block Diagram ......................................................... 199

Figure 49. Both TI0 and TI1 Quadrature Decoder Counting ................................................................. 200

Figure 50. Output Stage Block Diagram ............................................................................................... 201

Figure 51. Toggle Mode Channel Output Reference Signal – CHxPRE = 0 ......................................... 202

Figure 52. Toggle Mode Channel Output Reference Signal – CHxPRE = 1 ......................................... 202

Figure 53. PWM Mode Channel Output Reference Signal and Counter in Up-counting Mode ............ 203

Figure 54. PWM Mode Channel Output Reference Signal and Counter in Down-counting Mode ....... 203

Figure 55. PWM Mode Channel Output Reference Signal and Counter in Centre-aligned Mode ........ 204

Figure 56. Update Event Setting Diagram ............................................................................................ 205

Figure 57. Single Pulse Mode ............................................................................................................... 206

Figure 58. Immediate Active Mode Minimum Delay ............................................................................. 207

Figure 59. Asymmetric PWM Mode versus Center-aligned Counting Mode ......................................... 208

Figure 60. Pausing MCTM using the GPTM CH0OREF Signal ............................................................ 209

Figure 61. Triggering MCTM with GPTM Update Event ....................................................................... 210

Figure 62. Trigger GPTM and MCTM with the GPTM CH0 Input ..........................................................211

Figure 63. PWM Block Diagram ........................................................................................................... 247

Figure 64. Up-counting Example .......................................................................................................... 248

Figure 65. Down-counting Example ...................................................................................................... 249

Figure 66. Center-aligned Counting Example ....................................................................................... 250

Figure 67. PWM Clock Selection Source .............................................................................................. 251

Figure 68. Trigger Control Block ........................................................................................................... 252

Figure 69. Slave Controller Diagram .................................................................................................... 253

Figure 70. PWM in Restart Mode ......................................................................................................... 253

Figure 71. PWM in Pause Mode ........................................................................................................... 254

Figure 72. PWM in Trigger Mode .......................................................................................................... 254

Figure 73. Master PWMn and Slave PWMm / TMm Connection .......................................................... 255

Figure 74. MTO Selection ..................................................................................................................... 255

Figure 75. Compare Block Diagram ..................................................................................................... 256

Figure 76. Output Stage Block Diagram ............................................................................................... 256

Figure 77. Toggle Mode Channel Output Reference Signal (CHxPRE = 0) ......................................... 257

Figure 78. Toggle Mode Channel Output Reference Signal (CHxPRE = 1) ......................................... 258

Figure 79. PWM Mode Channel Output Reference Signal and Counter in Up-counting Mode ............ 258

Figure 80. PWM Mode Channel Output Reference Signal and Counter in Down-counting Mode ....... 259

List of Figures

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32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Figure 81. PWM Mode Channel Output Reference Signal and Counter in Centre-aligned Mode ........ 259

Figure 82. Update Event Setting Diagram ............................................................................................ 260

Figure 83. Single Pulse Mode ............................................................................................................... 261

Figure 84. Immediate Active Mode Minimum Delay ............................................................................. 262

Figure 85. Asymmetric PWM Mode versus Center-aligned Counting Mode ......................................... 263

Figure 86. Pausing PWM1 using the PWM0 CH0OREF Signal ........................................................... 264

Figure 87. Triggering PWM1 with PWM0 Update Event ....................................................................... 264

Figure 88. Trigger PWM0 and PWM1 with the PWM0 Timer Enable Signal ........................................ 265

Figure 89. BFTM Block Diagram .......................................................................................................... 292

Figure 90. BFTM – Repetitive Mode ..................................................................................................... 293

Figure 91. BFTM – One Shot Mode ...................................................................................................... 294

Figure 92. BFTM – One Shot Mode Counter Updating ....................................................................... 294

Figure 93. MCTM Block Diagram ......................................................................................................... 298

Figure 94. Up-counting Example .......................................................................................................... 300

Figure 95. Down-counting Example ...................................................................................................... 300

Figure 96. Center-aligned Counting Example ....................................................................................... 301

Figure 97. Update Event 1 Dependent Repetition Mechanism Example .............................................. 302

Figure 98. MCTM Clock Selection Source ............................................................................................ 303

Figure 99. Trigger Controller Block ....................................................................................................... 304

Figure 100. Slave Controller Diagram .................................................................................................. 305

Figure 101. MCTM in Restart Mode ..................................................................................................... 305

Figure 102. MCTM in Pause Mode ....................................................................................................... 306

Figure 103. MCTM in Trigger Mode ...................................................................................................... 306

Figure 104. Master MCTMn and Slave GPTM Connection .................................................................. 307

Figure 105. MTO Selection ................................................................................................................... 307

Figure 106. Capture/Compare Block Diagram ...................................................................................... 308

Figure 107. Input Capture Mode ........................................................................................................... 308

Figure 108. PWM Pulse Width Measurement Example ........................................................................ 309

Figure 109. Channel 0 and Channel 1 Input Stages ............................................................................. 310

Figure 110. Channel 2 and Channel 3 Input Stages ............................................................................. 310

Figure 111. TI0 Digital Filter Diagram with N = 2 ...................................................................................311

Figure 112. Output Stage Block Diagram ..............................................................................................311

Figure 113. Toggle Mode Channel Output Reference Signal – CHxPRE = 0 ....................................... 312

Figure 114. Toggle Mode Channel Output Reference Signal – CHxPRE = 1 ....................................... 313

Figure 115. PWM Mode Channel Output Reference Signal and Counter in Up-counting Mode .......... 313

Figure 116. PWM Mode Channel Output Reference Signal and Counter in Down-counting Mode ...... 314

Figure 117. PWM Mode 1 Channel Output Reference Signal and Counter in Centre-aligned Counting

Mode ...................................................................................................................................................... 314

Figure 118. Dead-time Insertion Performed for Complementary Outputs............................................. 315

Figure 119. MCTM Break Signal Bolck Diagram .................................................................................. 316

Figure 120. MT_BRK Pin Digital Filter Diagram with N = 2 .................................................................. 316

List of Figures

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32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Figure 121. Channel 3 Output with a Break Event Occurrence ............................................................ 317

Figure 122. Channel 0 ~2 Complementary Outputs with a Break Event Occurrence........................... 318

Figure 123. Channel 0 ~2 Only One Output Enabled when Break Event Occurs ................................ 319

Figure 124. Hardware Protection When Both CHxO and CHxNO are in Active Condition ................... 320

Figure 125. Update Event 1 Setup Diagram ......................................................................................... 322

Figure 126. CHxE, CHxNE and CHxOM Updated by Update Event 2 ................................................. 323

Figure 127. Update Event 2 Setup Diagram ......................................................................................... 323

Figure 128. Single Pulse Mode ............................................................................................................. 324

Figure 129. Immediate Active Mode Minimum Delay ........................................................................... 325

Figure 130. Asymmetric PWM Mode versus Center-aligned Counting Mode ....................................... 326

Figure 131. Pausing GPTM using the MCTM CH0OREF Signal .......................................................... 327

Figure 132. Triggering GPTM with MCTM Update Event 1 .................................................................. 328

Figure 133. Figure 41 Trigger MCTM and GPTM with the MCTM CH0 Input ....................................... 329

Figure 134. CH1XOR Input as Hall Sensor Interface ........................................................................... 330

Figure 135. RTC Block Diagram ........................................................................................................... 373

Figure 136. Watchdog Timer Block Diagram ....................................................................................... 382

Figure 137. Watchdog Timer Behavior ................................................................................................. 384

Figure 138. I2C Module Block Diagram ................................................................................................. 391

Figure 139. START and STOP Condition ............................................................................................. 393

Figure 140. Data Validity ....................................................................................................................... 393

Figure 141. 7-bit Addressing Mode ....................................................................................................... 394

Figure 142. 10-bit Addressing Write Transmit Mode ............................................................................ 395

Figure 143. 10-bits Addressing Read Receive Mode .......................................................................... 395

Figure 144. I2C Bus Acknowledge ........................................................................................................ 396

Figure 145. Clock Synchronization during Arbitration ........................................................................... 397

Figure 146. Two Master Arbitration Procedure ..................................................................................... 397

Figure 147. Master Transmitter Timing Diagram .................................................................................. 399

Figure 148. Master Receiver Timing Diagram ...................................................................................... 401

Figure 149. Slave Transmitter Timing Diagram .................................................................................... 402

Figure 150. Slave Receiver Timing Diagram ........................................................................................ 403

Figure 151. SCL Timing Diagram .......................................................................................................... 414

Figure 152. SPI Block Diagram ............................................................................................................ 420

Figure 153. SPI Single Byte Transfer Timing Diagram – CPOL = 0, CPHA = 0 .................................... 422

Figure 154. SPI Continuous Data Transfer Timing Diagram – CPOL = 0, CPHA = 0 ........................... 423

Figure 155. SPI Single Byte Transfer Timing Diagram – CPOL = 0, CPHA = 1 .................................... 423

Figure 156. SPI Continuous Transfer Timing Diagram – CPOL = 0, CPHA = 1 .................................... 424

Figure 157. SPI Single Byte Transfer Timing Diagram – CPOL = 1, CPHA = 0 .................................... 424

Figure 158. SPI Continuous Transfer Timing Diagram – CPOL = 1, CPHA = 0 .................................... 425

Figure 159. SPI Single Byte Transfer Timing Diagram – CPOL = 1, CPHA = 1 .................................... 425

Figure 160. SPI Continuous Transfer Timing Diagram – CPOL = 1, CPHA = 1 .................................... 425

Figure 161. SPI Multi-Master Slave Environment ................................................................................. 427

List of Figures

Rev. 1.00 19 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Figure 162. USART Block Diagram ...................................................................................................... 440

Figure 163. USART Serial Data Format ............................................................................................... 442

Figure 164. USART Clock CK_USART and Data Frame Timing .......................................................... 442

Figure 165. Hardware Flow Control between 2 USARTs ...................................................................... 443

Figure 166. USART RTS Flow Control ................................................................................................. 444

Figure 167. USART CTS Flow Control ................................................................................................. 444

Figure 168. IrDA Modulation and Demodulation ................................................................................... 445

Figure 169. USART I/O and IrDA Block Diagram ................................................................................. 446

Figure 170. RS485 Interface and Waveform ........................................................................................ 447

Figure 171. USART Synchronous Transmission Example ................................................................... 448

Figure 172. Figure 11. 8-bit Format USART Synchronous Waveform .................................................. 449

Figure 173. UART Block Diagram ......................................................................................................... 465

Figure 174. UART Serial Data Format .................................................................................................. 466

Figure 175. UART Clock CK_UART and Data Frame Timing ............................................................... 467

Figure 176. Divider Functional Diagram ............................................................................................... 476

Figure 177. CRC Block Diagram .......................................................................................................... 480

Figure 178. CRC Data Bit and Byte Reversal Example ........................................................................ 481

List of Figures

Rev. 1.00 20 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

1 Introduction

Overview

This user manual provides detailed information including how to use the devices, system and
bus architecture, memory organization and peripheral instructions. The target audiences for this
document are software developers, application developers and hardware developers. For more
information regarding pin assignment, package and electrical characteristics, please refer to the
datasheet.

The devices are high performance and low power consumption 32-bit microcontrollers based
around an Arm® Cortex®-M0+ processor core. The Cortex®-M0+ is a next-generation processor
core which is tightly coupled with Nested Vectored Interrupt Controller (NVIC), SysTick timer and
advanced debug support.

The devices operate at a frequency of up to 20 MHz for HT32F50231/50241 to obtain maximum

efciency. It provides up to 64 KB of embedded Flash memory for code / data storage and 8 KB

of embedded SRAM memory for system operation and application program usage. A variety of
peripherals, such as Hardware Divider DIV, ADC, I2C, USART, UART, SPI, BFTM, MCTM,

GPTM, PWM, CRC-16/32, RTC, WDT and SW-DP (Serial Wire Debug Port), etc., are also
implemented in the device series. Several power saving modes provide the exibility for maximum

optimization between wakeup latency and power consumption, which is an especially important
consideration in low power applications.

1 Introduction

The above features ensure that the devices are suitable for use in a wide range of applications,
especially in areas such as white goods application control, power monitors, alarm systems,
consumer products, handheld equipment, data logging applications, motor control and so on.

Rev. 1.00 21 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Features

▄

Core

● 32-bit Arm® Cortex®-M0+ processor core

● Up to 20 MHz operating frequency

● Single-cycle multiplication

● Integrated Nested Vectored Interrupt Controller (NVIC)

● 24-bit SysTick timer

▄

On-chip Memory

● Up to 64 KB on-chip Flash memory for instruction / data and option bytes storage

● 8 KB on-chip SRAM

● Supports multiple booting modes

▄

Flash Memory Controller – FMC

● 32-bit word programming with In System Programming Interface (ISP) and In Application

Programming (IAP)

● Flash protection capability to prevent illegal access

▄

Reset Control Unit – RSTCU

● Supply supervisor: Power On Reset / Power Down Reset (POR / PDR), Brown-out Detector

(BOD) and Programmable Low Voltage Detector (LVD)

▄

Clock Control Unit – CKCU

● External 4 to 20 MHz crystal oscillator

● Internal 20 MHz RC oscillator trimmed to ±2 % accuracy at 25 °C operating temperature

● Internal 32 kHz RC oscillator

● Independent clock divider and gating bits for peripheral clock sources

▄

Power Management – PWRCU

● Flexible power supply:

– VDD power supply: 2.5 V to 5.5 V
– V

power supply for I/O pins: 1.8 V to 5.5 V

DDIO

● Integrated 1.5 V LDO regulator for CPU core, peripherals and memories power supply

● Three power domains: VDD, V

● Three power saving modes: Sleep, Deep-Sleep1, Deep-Sleep2

▄

External Interrupt / Event Controller – EXTI

● Up to 16 EXTI lines with congurable trigger source and type

● All GPIO pins can be selected as EXTI trigger source

● Source trigger type includes high level, low level, negative edge, positive edge or both edge

● Individual interrupt enable, wakeup enable and status bits for each EXTI line

● Software interrupt trigger mode for each EXTI line

● Integrated deglitch lter for short pulse blocking

▄

Analog to Digital Converter – ADC

● 12-bit SAR ADC engine

● Up to 1 Msps conversion rate

● Up to 12 external analog input channels

and 1.5 V

DDIO

1 Introduction

Rev. 1.00 22 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

▄

I/O ports – GPIO

● Up to 40 GPIOs

● Port A, B, C are mapped as 16 external interrupts – EXTI

● Almost I/O pins are congurable output driving current

▄

Motor Control Timer – MCTM

● One 16-bit up, down, up/down auto-reload counter

● 16-bit programmable prescaler allowing counter clock frequency division by any factor

between 1 and 65536

● Input Capture function

● Compare Match Output

● PWM waveform generation with Edge-aligned and Center-aligned Counting Modes

● Single Pulse Mode Output

● Complementary Outputs with programmable dead-time insertion

● Break input to force the timer’s output signals into a reset or xed condition

▄

PWM Generation and Capture Timer – GPTM

● One 16-bit up, down, up / down auto-reload counter

● Up to 4 independent channels for each timer

● 16-bit programmable prescaler allowing the counter clock frequency division by any factor

between 1 and 65536

● Input Capture function

● Compare Match Output

● PWM waveform generation with Edge-aligned and Center-aligned Counting Modes

● Single Pulse Mode Output

● Encoder interface controller with two inputs using quadrature decoder

▄

Pulse Width Modulation – PWM

● One 16-bit up, down, up / down auto-reload counter

● Up to 4 independent channels for each timer

● 16-bit programmable prescaler allowing counter clock frequency division by any factor

between 1 and 65536

● Compare Match Output

● PWM waveform generation with Edge-aligned and Center-aligned Counting Modes

● Single Pulse Mode Output

▄

Basic Function Timer – BFTM

● One 32-bit compare / match count-up counter – No I/O control features

● One shot mode – Counting stops after a match condition

● Repetitive mode – Restart counter after a match condition

▄

Watchdog Timer – WDT

● 12-bit down-counter with a 3-bit pre-scaler

● Reset event for the system

● Programmable watchdog timer window function

● Registers write protection function

▄

Real Time Clock – RTC

● 24-bit up-counter with a programmable prescaler

● Alarm function

● Interrupt and Wake-up event

1 Introduction

Rev. 1.00 23 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

▄

Inter-integrated Circuit – I2C

● Supports both master and slave modes with a frequency of up to 1 MHz

● Provides an arbitration function and clock synchronization

● Supports 7-bit and 10-bit addressing modes and general call addressing

● Supports slave multi-addressing mode with maskable address

▄

Serial Peripheral Interface – SPI

● Supports both master and slave modes

● Frequency of up to (f

● FIFO Depth: 8 levels

● Multi-master and multi-slave operation

▄

Universal Synchronous Asynchronous Receiver Transmitter – USART

● Supports both asynchronous and clocked synchronous serial communication modes

● Asynchronous operating baud-rate clock frequency up to (f

operating clock frequency up to (f

● Full duplex communication

● Fully programmable characteristics of serial communication including: word length, parity bit,

stop bit and bit order

● Error detection: Parity, overrun and frame error

● Auto hardware ow control mode – RTS, CTS

● IrDA SIR encoder and decoder

● RS485 mode with output enable control

● FIFO Depth: 8 × 9 bits for both receiver and transmitter

▄

Universal Asynchronous Receiver Transmitter – UART

● Asynchronous serial communication operating baud rate clock frequency of up to (f

● Capability of full duplex communication

● Fully programmable characteristics of serial communication including: word length, parity bit,

stop bit and bit order

● Error detection: Parity, overrun and frame error

▄

Hardware Divider – DIV

● Signed / unsigned 32-bit divider

● Operation in 8 clock cycles, load in 1 clock cycle

● Division by zero error ag

▄

Cyclic Redundancy Check – CRC

● Support CRC16 polynomial: 0x8005, X16 + X15 + X2 + 1

● Support CCITT CRC16 polynomial: 0x1021, X16 + X12 + X5 + 1

● Support IEEE-802.3 CRC32 polynomial: 0x04C11DB7, X32 + X26 + X23 + X22 + X16 + X12 +

X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1

● Supports 1's complement, byte reverse & bit reverse operation on data and checksum

● Supports byte, half-word & word data size

● Programmable CRC initial seed value

● CRC computation executed in 1 AHB clock cycle for 8-bit data and 4 AHB clock cycles for

32-bit data

▄

Debug Support

● Serial Wire Debug Port – SW-DP

● 4 comparators for hardware breakpoint or code / literal patch

● 2 comparators for hardware watchpoints

/2) MHz for master mode and (f

PCLK

/8) MHz

PCLK

/3) MHz for slave mode

PCLK

/16) MHz and synchronous

PCLK

PCLK

1 Introduction

/16) MHz

Rev. 1.00 24 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

▄

Package and Operation Temperature

● 24/28-pin SSOP, 28-pin SOP, 24/33-pin QFN and 44/48-pin LQFP package types

● Operation temperature range: -40 °C to 85 °C

Device Information

Table 1. Features and Peripheral List

Peripherals HT32F50231 HT32F50241

Main Flash (KB) 32 63

Option Bytes Flash (KB) 1 1

SRAM (KB) 4 8

Timers

Communication

Hardware Divider 1

CRC-16/32 1

EXTI 16

12-bit ADC
Number of Channels

GPIO Up to 40

CPU Frequency Up to 20 MHz

Operating Voltage 2.5 V ~ 5.5 V

Operating Temperature -40 °C ~ 85 °C

Package

1 Introduction

MCTM 1

GPTM 1

PWM 2

BFTM 2

WDT 1

RTC 1

SPI 2

USART 1

UART 2

I2C 2

1

12 Channels

24/28-pin SSOP, 28-pin SOP,
24/33-pin QFN and 44/48-pin LQFP

Rev. 1.00 25 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

Block Diagram

TX, RX
RTS/TXE
CTS/SCK

TX, RX

CH0 ~CH2

CH0N ~ CH2N

CH3, BRK

PWMx_CH0

~

PWMx_CH3

AF

AF

AF AF

SWCLK
SWDIO

AF

SW-DP

Cortex®-M0+

Processor

NVIC

Interrupt request

PA ~ PB[15:0], PC[7:0]

I/O Port

GPIO

System

USART

UART0 ~ 1

UART0

PWM0 ~ 1

UART0

Bus Matrix

AFIO

EXTI

MCTM

BOOT

AF

Flash Memory

Interface

FMC

Control Registers

AHB Peripherals

SRAM

Controller

AHB to APB

Bridge

APB

CRC

-16/32

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Flash

Memory

CKCU/RSTCU

Control Registers

Divider

SRAM

WDT

SPI0 ~ 1

I2C0 ~ 1

GPTM

BFTM0 ~ 1

DD15

POR

/PDR

HSE

4 ~ 20 MHz

Clock and reset contr ol

LDO

1.5 V

VDD

VSS

AF

XTALIN
XTALOUT

CLDO

1 Introduction

CAP.

BOD

LVD

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Power control

HSI

20 MHz

DD

AF

MOSI, MISO
SCK, SEL

AF

SDA
SCL

AF

GT_CH0

~

GT_CH3

AF

ADC_IN0

...

ADC_IN11

VDDA

VSSA

Power supply:

Bus:

Control signal:

Alternate function:

12-bit

SAR ADC

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AF

DDA

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DD15

ADC

RTC

PWRCU

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32 kHz

32,768 Hz

X32KIN

X32KOUT

LSI

LSE

AF

DD

AF

RTCOUT

VDD

VSS

AF

WAKEUP0 ~ 1

nRST

Figure 1. Block Diagram

Rev. 1.00 26 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

2 Document Conventions

Unless otherwise specied, this document uses the conventions which showed as follows.

Table 2. Document Conventions

Notation Example Description

0x 0x5a05

0xnnnn_nnnn 0x2000_0100 32-bit Hexadecimal address or data.

b b0101

NAME [n] ADDR [5]

NAME [m:n] ADDR [11:5]

X b10X1 Don’t care notation which means any value is allowed.

19 18

RW

RO

RC

WC

W0C

WO

Reserved

Word

Half-word Data length of a half-word is 16-bit.

Byte Data length of a byte is 8-bit.

SERDYIE PLLRDYIE

RW 0 RW 0

3 2

HSIRDY HSERDY

RO 1 RO 0

1 0

PDF BAK_PORF

RC 0 RC 1

3 2

SERDYF PLLRDYF

WC 0 WC 0

1 0

Reserved MIF

W0C 0

31 30

DB_CKSRC

WO 0 WO 0

1 0
LLRDY Reserved
RO 0

The number string with a 0x prex indicates a hexadecimal

number.

The number string with a lowercase b prefix indicates a
binary number.

Specific bit of NAME. NAME can be a register or field of
register. For example, ADDR [5] means bit 5 of ADDR register

(eld).

Specific bits of NAME. NAME can be a register or field of
register. For example, ADDR [11:5] means bit 11 to 5 of ADDR

register (eld).

Software can read and write to this bit.

Software can only read this bit. A write operation will have
no effect.

Software can only read this bit. Read operation will clear it
to 0 automatically.

Software can read this bit or clear it by writing 1. Writing a 0
will have no effect.

Software can read this bit or clear it by writing 0. Writing a 1
will have no effect.

Software can only write to this bit. A read operation always
returns 0.

Reserved bit(s) for future use. Data read from these bits

is not well dened and should be treated as random data.

Normally these reserved bits should be set to a 0 value.
Note that reserved bit must be kept at reset value.

Data length of a word is 32-bit.

2 Document Conventions

Rev. 1.00 27 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

3 System Architecture

The system architecture of devices that includes the Arm® Cortex®-M0+ processor, bus architecture
and memory organization will be described in the following sections. The Cortex®-M0+ is a next
generation processor core which offers many new features. Integrated and advanced features make
the Cortex®-M0+ processor suitable for market products that require microcontrollers with high
performance and low power consumption. In brief, The Cortex®-M0+ processor includes AHB-Lite
bus interface. All memory accesses of the Cortex®-M0+ processor are executed on the AHB-Lite
bus according to the different purposes and the target memory spaces. The memory organization

uses a Harvard architecture, pre-dened memory map and up to 4 GB of memory space, making
the system exible and extendable.

Arm® Cortex®-M0+ Processor

The Cortex®-M0+ processor is a very low gate count, highly energy efficient processor that is
intended for microcontroller and deeply embedded applications that require an area optimized,

low-power processor. The processor is based on the ARMv6-M architecture and supports Thumb®

instruction sets; single-cycle I/O port; hardware multiplier and low latency interrupt respond time.
Some system peripherals listed below are also provided by Cortex®-M0+:

3 System Architecture

▄

Internal Bus Matrix connected with AHB-Lite Interface, Single-cycle I/O port and Debug

Accesses Port (DAP)

▄

Nested Vectored Interrupt Controller (NVIC)

▄

Optional Wakeup Interrupt Controller (WIC)

▄

Breakpoint and Watchpoint Unit

▄

Optional Memory Protection Unit (MPU)

▄

Serial Wire debug Port (SW-DP)

▄

Optional Micro Trace Buffer Interface (MTB)

The following gure shows the Cortex®-M0+ processor block diagram. For more information, refer

to the Arm® Cortex®-M0+ Technical Reference Manual.

Rev. 1.00 28 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

®

-M0+ Components

Cortex

Execution Trace Interface

Cortex®-M0+ Processor

Interrupts

Vectored
Interrupt

Controller

‡ Wakeup

Interrupt

Controller (WIC)

‡ Optional Component

Figure 2. Cortex®-M0+ Block Diagram

Bus Architecture

Nested

(NVIC)

Cortex®-M0+

Processor

Core

‡ Memory
Protection

Unit

AHB-Lite Interface

to System

Bus Matrix

Debug

‡ Breakpoint

and

Watchpoint

Unit

‡ Debugger

Interface

‡ Single-cycle

I/O Port

3 System Architecture

‡ Debug

Access Port

(DAP)

‡ Serial Wire or

JTAG Debug Port

The HT32F50231/50241 series devices consist of one master and four slaves in the bus architecture.
The Cortex®-M0+ AHB-Lite bus is the master while the internal SRAM access bus, the internal

Flash memory access bus, the AHB peripherals access bus and the AHB to APB bridges are the
slaves. The single 32-bit AHB-Lite system interface provides simple integration to all system

regions include the internal SRAM region and the peripheral region. All of the master buses are

based on 32-bit Advanced High-performance Bus-Lite (AHB-Lite) protocol. The following gure

shows the bus architecture of the HT32F50231/50241 series.

Rev. 1.00 29 of 486 July 31, 2018

32-Bit Arm® Cortex®-M0+ MCU
HT32F50231/HT32F50241

GPIO

I/O Port

Cortex®-M0+

Processor

System

NVIC

Interrupt request

Figure 3. Bus Architecture

Bus Matrix

Flash Memory

Interface

FMC

Control Registers

AHB Peripherals

SRAM Controller

AHB to APB

Bridge

Flash Memory

3 System Architecture

CKCU/RSTCU

Control Registers

SRAM

APB IPs

Memory Organization

The Arm® Cortex®-M0+ processor accesses and debug accesses share the single external

interface to external AHB peripheral. The processor accesses take priority over debug accesses.

The maximum address range of the Cortex®-M0+ is 4 GB since it has 32-bit bus address width.
Additionally, a pre-defined memory map is provided by the Cortex®-M0+ processor to reduce
the software complexity of repeated implementation of different device vendors. However, some
regions are used by the Arm® Cortex®-M0+ system peripherals. Refer to the Arm® Cortex®-M0+

Technical Reference Manual for more information. The following gure shows the memory map
of HT32F50231/50241 series of devices, including Code, SRAM, peripheral and other pre-dened

regions.

Rev. 1.00 30 of 486 July 31, 2018