Holtek HT32F12345 User Manual

Holtek 32-Bit Microcontroller with Arm® Cortex®-M3 Core

HT32F12345

User Manual

Revision: V1.10 Date: November 28, 2018

32-Bit Arm® Cortex®-M3 MCU
HT32F12345

Table of Contents

1 Introduction ........................................................................................................... 27

Overview .............................................................................................................................. 27

Features ............................................................................................................................... 28

Device Information ............................................................................................................... 32

Block Diagram ..................................................................................................................... 33

2 Document Conventions ....................................................................................... 34

3 System Architecture ............................................................................................. 35

Arm® Cortex®-M3 Processor ................................................................................................ 35

Bus Architecture ................................................................................................................... 36

Memory Organization .......................................................................................................... 37

Memory Map ................................................................................................................................... 38

Embedded Flash Memory ............................................................................................................... 41

Embedded SRAM Memory ............................................................................................................. 41

AHB Peripherals ............................................................................................................................. 41

APB Peripherals ............................................................................................................................. 41

Table of Contents

4 Flash Memory Controller (FMC) .......................................................................... 42

Introduction .......................................................................................................................... 42

Features ............................................................................................................................... 42

Functional Descriptions ....................................................................................................... 43

Flash Memory Map ......................................................................................................................... 43

Flash Memory Architecture ............................................................................................................. 44

Wait State Setting ........................................................................................................................... 44

Booting Conguration ..................................................................................................................... 45

Page Erase ..................................................................................................................................... 46

Mass Erase ..................................................................................................................................... 47

Word Programming ......................................................................................................................... 48

Option Byte Description .................................................................................................................. 49

Page Erase / Program Protection ................................................................................................... 50

Security Protection .......................................................................................................................... 51

Register Map ....................................................................................................................... 52

Register Descriptions ........................................................................................................... 53

Flash Target Address Register – TADR .......................................................................................... 53

Flash Write Data Register – WRDR ............................................................................................... 54

Flash Operation Command Register – OCMR ............................................................................... 55

Flash Operation Control Register – OPCR ..................................................................................... 56

Flash Operation Interrupt Enable Register – OIER ........................................................................ 57

Flash Operation Interrupt and Status Register – OISR .................................................................. 58

Flash Page Erase / program Protection Status Register – PPSR .................................................. 59

Flash Security Protection Status Register – CPSR ........................................................................ 60

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Flash Vector Mapping Control Register – VMCR ........................................................................... 61

Flash Manufacturer and Device ID Register – MDID ...................................................................... 62

Flash Page Number Status Register – PNSR ................................................................................ 63

Flash Page Size Status Register – PSSR ...................................................................................... 64

Device ID Register – DID ................................................................................................................ 65

Flash Pre-fetch Control Register – CFCR ...................................................................................... 66

SRAM Booting Vector Register n – SBVTn, n = 0 ~ 3 .................................................................... 67

Custom ID Register n – CIDRn, n = 0 ~ 3 ...................................................................................... 68

5 Power Control Unit (PWRCU) .............................................................................. 69

Introduction .......................................................................................................................... 69

Features ............................................................................................................................... 70

Functional Descriptions ....................................................................................................... 70

Backup Domain .............................................................................................................................. 70

VDD Power Domain .......................................................................................................................... 71

1.5 V Power Domain ....................................................................................................................... 73

Operation Modes ............................................................................................................................ 73

Register Map ....................................................................................................................... 75

Register Descriptions ........................................................................................................... 76

Backup Domain Status Register – BAKSR ..................................................................................... 76

Backup Domain Control Register – BAKCR ................................................................................... 77

Backup Domain Test Register – BAKTEST .................................................................................... 79

Low Voltage / Brown Out Detect Control and Status Register – LVDCSR ..................................... 79

Backup Register n – BAKREGn, n = 0 ~ 9 ..................................................................................... 81

Table of Contents

6 Clock Control Unit (CKCU) .................................................................................. 82

Introduction .......................................................................................................................... 82

Features ............................................................................................................................... 82

Functional Descriptions ....................................................................................................... 84

High Speed External Crystal Oscillator (HSE) ................................................................................ 84

High Speed Internal RC Oscillator (HSI) ........................................................................................ 85

Auto Trimming of High Speed Internal RC Oscillator (HSI) ............................................................ 85

Phase Locked Loop – PLL .............................................................................................................. 87

USB Phase Locked Loop – USB PLL ............................................................................................. 88

Low Speed External Crystal Oscillator – LSE ................................................................................. 90

Low Speed Internal RC Oscillator – LSI ......................................................................................... 90

Clock Ready Flag ........................................................................................................................... 90

System Clock (CK_SYS) Selection ................................................................................................ 91

HSE Clock Monitor ......................................................................................................................... 91

Clock Output Capability .................................................................................................................. 92

Register Map ....................................................................................................................... 92

Register Descriptions ........................................................................................................... 93

Global Clock Conguration Register – GCFGR .............................................................................. 93

Global Clock Control Register – GCCR .......................................................................................... 94

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Global Clock Status Register – GCSR ........................................................................................... 96

Global Clock Interrupt Register – GCIR .......................................................................................... 97

PLL Conguration Register – PLLCFGR ........................................................................................ 99

PLL Control Register – PLLCR ..................................................................................................... 100

AHB Conguration Register – AHBCFGR .................................................................................... 101

AHB Clock Control Register – AHBCCR ..................................................................................... 102

APB Conguration Register – APBCFGR ..................................................................................... 104

APB Clock Control Register 0 – APBCCR0 .................................................................................. 105

APB Clock Control Register 1 – APBCCR1 .................................................................................. 106

Clock Source Status Register – CKST ......................................................................................... 108

APB Peripheral Clock Selection Register 0 – APBPCSR0 .......................................................... 109

APB Peripheral Clock Selection Register 1 – APBPCSR1 ...........................................................111

HSI Control Register – HSICR ......................................................................................................112

HSI Auto Trimming Counter Register – HSIATCR ........................................................................113

Low Power Control Register – LPCR ..........................................................................................114

MCU Debug Control Register – MCUDBGCR ..............................................................................115

Table of Contents

7 Reset Control Unit (RSTCU) .............................................................................. 117

Introduction ........................................................................................................................ 117

Functional Descriptions ..................................................................................................... 117

Power On Reset ............................................................................................................................117

System Reset ................................................................................................................................118

AHB and APB Unit Reset ...............................................................................................................118

Register Map ..................................................................................................................... 118

Register Descriptions ......................................................................................................... 119

Global Reset Status Register – GRSR ..........................................................................................119

AHB Peripheral Reset Register – AHBPRSTR ............................................................................. 120

APB Peripheral Reset Register 0 – APBPRSTR0 ........................................................................ 121

APB Peripheral Reset Register 1 – APBPRSTR1 ........................................................................ 122

8 General Purpose I/O (GPIO) ............................................................................... 124

Introduction ........................................................................................................................ 124

Features ............................................................................................................................. 125

Functional Descriptions ..................................................................................................... 125

Default GPIO Pin Conguration .................................................................................................... 125

General Purpose I/O – GPIO ........................................................................................................ 125

GPIO Locking Mechanism ............................................................................................................ 127

Register Map ..................................................................................................................... 127

Register Descriptions ......................................................................................................... 128

Port A Data Direction Control Register – PADIRCR ..................................................................... 128

Port A Input Function Enable Control Register – PAINER ............................................................ 129

Port A Pull-Up Selection Register – PAPUR ................................................................................. 129

Port A Pull-Down Selection Register – PAPDR ............................................................................ 130

Port A Open Drain Selection Register – PAODR .......................................................................... 131

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Port A Output Current Drive Selection Register – PADRVR ......................................................... 131

Port A Lock Register – PALOCKR ................................................................................................ 132

Port A Data Input Register – PADINR ........................................................................................... 133

Port A Output Data Register – PADOUTR .................................................................................... 133

Port A Output Set / Reset Control Register – PASRR .................................................................. 134

Port A Output Reset Register – PARR .......................................................................................... 135

Port B Data Direction Control Register – PBDIRCR ..................................................................... 135

Port B Input Function Enable Control Register – PBINER ........................................................... 136

Port B Pull-Up Selection Register – PBPUR ................................................................................ 136

Port B Pull-Down Selection Register – PBPDR ............................................................................ 137

Port B Open Drain Selection Register – PBODR ......................................................................... 137

Port B Output Current Drive Selection Register – PBDRVR ........................................................ 138

Port B Lock Register – PBLOCKR ................................................................................................ 138

Port B Data Input Register – PBDINR .......................................................................................... 139

Port B Output Data Register – PBDOUTR ................................................................................... 140

Port B Output Set / Reset Control Register – PBSRR .................................................................. 141

Port B Output Reset Register – PBRR ......................................................................................... 142

Port C Data Direction Control Register – PCDIRCR .................................................................... 142

Port C Input Function Enable Control Register – PCINER ........................................................... 143

Port C Pull-Up Selection Register – PCPUR ................................................................................ 143

Port C Pull-Down Selection Register – PCPDR ........................................................................... 144

Port C Open Drain Selection Register – PCODR ......................................................................... 145

Port C Output Current Drive Selection Register – PCDRVR ........................................................ 145

Port C Lock Register – PCLOCKR ............................................................................................... 146

Port C Data Input Register – PCDINR .......................................................................................... 147

Port C Output Data Register – PCDOUTR ................................................................................... 148

Port C Output Set / Reset Control Register – PCSRR ................................................................. 149

Port C Output Reset Register – PCRR ......................................................................................... 150

Port D Data Direction Control Register – PDDIRCR .................................................................... 150

Port D Input Function Enable Control Register – PDINER ........................................................... 151

Port D Pull-Up Selection Register – PDPUR ................................................................................ 152

Port D Pull-Down Selection Register – PDPDR ........................................................................... 153

Port D Open Drain Selection Register – PDODR ......................................................................... 154

Port D Output Current Drive Selection Register – PDDRVR ........................................................ 154

Port D Lock Register – PDLOCKR ............................................................................................... 155

Port D Data Input Register – PDDINR .......................................................................................... 156

Port D Output Data Register – PDDOUTR ................................................................................... 156

Port D Output Set / Reset Control Register – PDSRR ................................................................. 157

Port D Output Reset Register – PDRR ......................................................................................... 158

Table of Contents

9 Alternate Function Input / Output Control Unit (AFIO) .................................... 159

Introduction ........................................................................................................................ 159

Features ............................................................................................................................. 160

Functional Descriptions ..................................................................................................... 160

External Interrupt Pin Selection .................................................................................................... 160

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Alternate Function ......................................................................................................................... 161

Lock Mechanism .......................................................................................................................... 161

Register Map ..................................................................................................................... 161

Register Descriptions ......................................................................................................... 162

EXTI Source Selection Register 0 – ESSR0 ................................................................................ 162

EXTI Source Selection Register 1 – ESSR1 ................................................................................ 163

GPIO x Conguration Low Register – GPxCFGLR, x = A, B, C, D ............................................... 164

GPIO x Conguration High Register – GPxCFGHR, x = A, B, C, D ............................................. 165

10 Nested Vectored Interrupt Controller (NVIC) .................................................. 166

Introduction ........................................................................................................................ 166

Features ............................................................................................................................. 169

Functional Descriptions ..................................................................................................... 169

SysTick Calibration ....................................................................................................................... 169

Register Map ..................................................................................................................... 169

Table of Contents

11 External Interrupt / Event Controller (EXTI) .................................................... 171

Introduction ........................................................................................................................ 171

Features ............................................................................................................................. 171

Functional Descriptions ..................................................................................................... 172

Wakeup Event Management......................................................................................................... 172

External Interrupt / Event Line Mapping ....................................................................................... 173

Interrupt and De-bounce ............................................................................................................... 173

Register Map ..................................................................................................................... 174

Register Descriptions ......................................................................................................... 175

EXTI Interrupt Conguration Register n – EXTICFGRn, n = 0 ~ 15 ............................................. 175

EXTI Interrupt Control Register – EXTICR ................................................................................... 176

EXTI Interrupt Edge Flag Register – EXTIEDGEFLGR ................................................................ 176

EXTI Interrupt Edge Status Register – EXTIEDGESR ................................................................. 177

EXTI Interrupt Software Set Command Register – EXTISSCR .................................................... 177

EXTI Interrupt Wakeup Control Register – EXTIWAKUPCR ........................................................ 178

EXTI Interrupt Wakeup Polarity Register – EXTIWAKUPPOLR ................................................... 179

EXTI Interrupt Wakeup Flag Register – EXTIWAKUPFLG ........................................................... 179

12 Analog to Digital Converter (ADC) .................................................................. 180

Introduction ........................................................................................................................ 180

Features ............................................................................................................................. 181

Functional Descriptions ..................................................................................................... 182

ADC Clock Setup .......................................................................................................................... 182

Regular and High Priority Channel Selection ............................................................................... 182

Conversion Modes ........................................................................................................................ 182

Start Conversion on External Event .............................................................................................. 187

High Priority Group Management ................................................................................................. 188

Sampling Time Setting .................................................................................................................. 188

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Data Format and Alignment .......................................................................................................... 190

Analog Watchdog.......................................................................................................................... 190

Interrupts ....................................................................................................................................... 190

PDMA Request ............................................................................................................................ 191

Register Map ..................................................................................................................... 191

Register Descriptions ......................................................................................................... 193

ADC Reset Register – ADCRST ................................................................................................... 193

ADC Regular Conversion Mode Register – ADCCONV ............................................................... 194

ADC High Priority Conversion Mode Register – ADCHCONV ...................................................... 195

ADC Regular Conversion List Register 0 – ADCLST0 ................................................................. 196

ADC Regular Conversion List Register 1 – ADCLST1 ................................................................. 197

ADC Regular Conversion List Register 2 – ADCLST2 ................................................................. 198

ADC High Priority Conversion List Register – ADCHLST ............................................................. 199

ADC Input Offset Register n – ADCOFRn, n = 0 ~ 11 .................................................................. 200

ADC Input Sampling Time Register n – ADCSTRn, n = 0 ~ 11 .................................................... 201

ADC Regular Conversion Data Register y – ADCDRy, y = 0 ~ 11 ................................................ 201

ADC High Priority Conversion Data Register y – ADCHDRy, y = 0 ~ 3 ........................................ 202

ADC Regular Trigger Control Register – ADCTCR ....................................................................... 203

ADC Regular Trigger Source Register – ADCTSR ....................................................................... 204

ADC High Priority Trigger Control Register – ADCHTCR ............................................................. 205

ADC High Priority Trigger Source Register – ADCHTSR ............................................................. 206

ADC Watchdog Control Register – ADCWCR .............................................................................. 207

ADC Watchdog Lower Threshold Register – ADCLTR ................................................................. 208

ADC Watchdog Upper Threshold Register – ADCUTR ................................................................ 208

ADC Interrupt Enable Register – ADCIER .................................................................................... 209

ADC Interrupt Raw Status Register – ADCIRAW ......................................................................... 210

ADC Interrupt Status Register – ADCISR ......................................................................................211

ADC Interrupt Clear Register – ADCICLR .................................................................................... 213

ADC DMA Request Register – ADCDMAR ................................................................................... 214

Table of Contents

13 Comparator (CMP) ............................................................................................ 215

Introduction ........................................................................................................................ 215

Features ............................................................................................................................. 215

Functional Descriptions ..................................................................................................... 216

Comparator Inputs and Output ..................................................................................................... 216

Comparator Reference Voltage .................................................................................................... 216

Interrupts and Wakeup.................................................................................................................. 217

Power Mode and Hysteresis ......................................................................................................... 218

Comparator Write-Protected mechanism ..................................................................................... 218

Register Map ..................................................................................................................... 218

Register Descriptions ......................................................................................................... 219

Comparator Control Register n – CMPCRn, n = 0 ~ 1 ................................................................. 219

Comparator Voltage Reference Value Register n – CVRVALRn, n = 0 ~ 1 .................................. 221

Comparator Interrupt Enable Register n – CMPIERn, n = 0 ~ 1 ................................................... 222

Comparator Transition Flag Register n – CMPTFRn, n = 0 ~ 1 .................................................... 223

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14 General-Purpose Timer (GPTM) ...................................................................... 224

Introduction ........................................................................................................................ 224

Features ............................................................................................................................. 225

Functional Descriptions ..................................................................................................... 225

Counter Mode ............................................................................................................................... 225

Clock Controller ............................................................................................................................ 227

Trigger Controller .......................................................................................................................... 228

Slave Controller ............................................................................................................................ 230

Master Controller .......................................................................................................................... 232

Channel Controller ........................................................................................................................ 232

Input Stage ................................................................................................................................... 235

Output Stage ................................................................................................................................. 236

Update Management .................................................................................................................... 240

Quadrature Decoder ..................................................................................................................... 240

Digital Filter ................................................................................................................................... 242

Clearing the CHxOREF when ETIF is high ................................................................................... 243

Single Pulse Mode ........................................................................................................................ 244

Asymmetric PWM Mode ............................................................................................................... 246

Time Interconnection .................................................................................................................... 246

Trigger ADC Start.......................................................................................................................... 249

PDMA Request ............................................................................................................................. 249

Register Map ..................................................................................................................... 250

Register Descriptions ......................................................................................................... 251

Timer Counter Conguration Register – CNTCFR ....................................................................... 251

Timer Mode Conguration Register – MDCFR ............................................................................. 252

Timer Trigger Conguration Register – TRCFR ............................................................................ 255

Timer Counter Register – CTR ..................................................................................................... 257

Channel 0 Input Conguration Register – CH0ICFR .................................................................... 258

Channel 1 Input Conguration Register – CH1ICFR .................................................................... 259

Channel 2 Input Conguration Register – CH2ICFR .................................................................... 260

Channel 3 Input Conguration Register – CH3ICFR .................................................................... 262

Channel 0 Output Conguration Register – CH0OCFR ............................................................... 263

Channel 1 Output Conguration Register – CH1OCFR ............................................................... 265

Channel 2 Output Conguration Register – CH2OCFR ............................................................... 266

Channel 3 Output Conguration Register – CH3OCFR ............................................................... 268

Channel Control Register – CHCTR ............................................................................................. 270

Channel Polarity Conguration Register – CHPOLR .................................................................... 271

Timer PDMA/Interrupt Control Register – DICTR ......................................................................... 272

Timer Event Generator Register – EVGR ..................................................................................... 273

Timer Interrupt Status Register – INTSR ...................................................................................... 275

Timer Counter Register – CNTR................................................................................................... 277

Timer Prescaler Register – PSCR ................................................................................................ 277

Timer Counter Reload Register – CRR ........................................................................................ 278

Channel 0 Capture / Compare Register – CH0CCR .................................................................... 278

Table of Contents

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Channel 1 Capture / Compare Register – CH1CCR .................................................................... 279

Channel 2 Capture / Compare Register – CH2CCR .................................................................... 280

Channel 3 Capture / Compare Register – CH3CCR .................................................................... 281

Channel 0 Asymmetric Compare Register – CH0ACR ................................................................. 282

Channel 1 Asymmetric Compare Register – CH1ACR ................................................................. 282

Channel 2 Asymmetric Compare Register – CH2ACR ................................................................. 283

Channel 3 Asymmetric Compare Register – CH3ACR ................................................................. 283

15 Basic Function Timer (BFTM) .......................................................................... 284

Introduction ........................................................................................................................ 284

Features ............................................................................................................................. 284

Functional Description ....................................................................................................... 285

Repetitive Mode ............................................................................................................................ 285

One Shot Mode ............................................................................................................................. 286

Trigger ADC Start.......................................................................................................................... 287

Register Map ..................................................................................................................... 287

Register Descriptions ......................................................................................................... 288

BFTM Control Register – BFTMCR .............................................................................................. 288

BFTM Status Register – BFTMSR ................................................................................................ 289

BFTM Counter Register – BFTMCNTR ........................................................................................ 289

BFTM Compare Value Register – BFTMCMPR ........................................................................... 290

Table of Contents

16 Motor Control Timer (MCTM) ........................................................................... 291

Introduction ........................................................................................................................ 291

Features ............................................................................................................................. 292

Functional Descriptions ..................................................................................................... 293

Counter Mode ............................................................................................................................... 293

Clock Controller ............................................................................................................................ 296

Trigger Controller .......................................................................................................................... 297

Slave Controller ............................................................................................................................ 298

Master Controller .......................................................................................................................... 300

Channel Controller ........................................................................................................................ 301

Input Stage ................................................................................................................................... 303

Output Stage ................................................................................................................................. 304

Update Management .................................................................................................................... 313

Quadrature Decoder ..................................................................................................................... 315

Digital Filter ................................................................................................................................... 317

Clearing CHxOREF when ETIF is high ......................................................................................... 317

Single Pulse Mode ........................................................................................................................ 318

Asymmetric PWM Mode ............................................................................................................... 320

Timer Interconnection ................................................................................................................... 320

Trigger ADC Start.......................................................................................................................... 324

Lock Level Table ........................................................................................................................... 324

PDMA Request ............................................................................................................................. 325

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Register Map ..................................................................................................................... 326

Register Descriptions ......................................................................................................... 327

Timer Counter Conguration Register – CNTCFR ....................................................................... 327

Timer Mode Conguration Register – MDCFR ............................................................................. 328

Timer Trigger Conguration Register – TRCFR ............................................................................ 331

Timer Counter Register – CTR ..................................................................................................... 333

Channel 0 Input Conguration Register – CH0ICFR .................................................................... 334

Channel 1 Input Conguration Register – CH1ICFR .................................................................... 335

Channel 2 Input Conguration Register – CH2ICFR .................................................................... 336

Channel 3 Input Conguration Register – CH3ICFR .................................................................... 338

Channel 0 Output Conguration Register – CH0OCFR ............................................................... 339

Channel 1 Output Conguration Register – CH1OCFR ............................................................... 341

Channel 2 Output Conguration Register – CH2OCFR ............................................................... 342

Channel 3 Output Conguration Register – CH3OCFR ............................................................... 344

Channel Control Register – CHCTR ............................................................................................. 345

Channel Polarity Conguration Register – CHPOLR .................................................................... 347

Channel Break Conguration Register – CHBRKCFR ................................................................. 348

Channel Break Control Register – CHBRKCTR ........................................................................... 349

Timer PDMA / Interrupt Control Register – DICTR ....................................................................... 352

Timer Event Generator Register – EVGR ..................................................................................... 353

Timer Interrupt Status Register – INTSR ...................................................................................... 355

Timer Counter Register – CNTR................................................................................................... 357

Timer Prescaler Register – PSCR ................................................................................................ 358

Timer Counter Reload Register – CRR ........................................................................................ 358

Timer Repetition Register – REPR ............................................................................................... 359

Channel 0 Capture / Compare Register – CH0CCR .................................................................... 359

Channel 1 Capture / Compare Register – CH1CCR .................................................................... 360

Channel 2 Capture / Compare Register – CH2CCR .................................................................... 361

Channel 3 Capture / Compare Register – CH3CCR .................................................................... 362

Channel 0 Asymmetric Compare Register – CH0ACR ................................................................. 363

Channel 1 Asymmetric Compare Register – CH1ACR ................................................................. 363

Channel 2 Asymmetric Compare Register – CH2ACR ................................................................. 364

Channel 3 Asymmetric Compare Register – CH3ACR ................................................................. 364

Table of Contents

17 Real Time Clock (RTC) ..................................................................................... 365

Introduction ........................................................................................................................ 365

Features ............................................................................................................................. 365

Functional Descriptions ..................................................................................................... 366

RTC Related Register Reset ........................................................................................................ 366

Reading RTC Register .................................................................................................................. 366

Low Speed Clock Conguration ................................................................................................... 366

RTC Counter Operation ................................................................................................................ 366

Interrupt and Wakeup Control ....................................................................................................... 367

RTCOUT Output Pin Conguration............................................................................................... 367

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Register Map ..................................................................................................................... 368

Register Descriptions ......................................................................................................... 369

RTC Counter Register – RTCCNT ................................................................................................ 369

RTC Compare Register – RTCCMP ............................................................................................. 370

RTC Control Register – RTCCR ................................................................................................... 371

RTC Status Register – RTCSR..................................................................................................... 373

RTC Interrupt and Wakeup Enable Register – RTCIWEN ............................................................ 374

18 Watchdog Timer (WDT) .................................................................................... 375

Introduction ........................................................................................................................ 375

Features ............................................................................................................................. 375

Functional Description ....................................................................................................... 376

Register Map ..................................................................................................................... 377

Register Descriptions ......................................................................................................... 378

Watchdog Timer Control Register – WDTCR ............................................................................... 378

Watchdog Timer Mode Register 0 – WDTMR0............................................................................. 379

Watchdog Timer Mode Register 1 – WDTMR1............................................................................. 380

Watchdog Timer Status Register – WDTSR ................................................................................. 381

Watchdog Timer Protection Register – WDTPR ........................................................................... 382

Watchdog Timer Clock Selection Register – WDTCSR ................................................................ 383

Table of Contents

19 Inter-Integrated Circuit (I2C) ............................................................................ 384

Introduction ........................................................................................................................ 384

Features ............................................................................................................................. 385

Functional Descriptions ..................................................................................................... 385

Two Wire Serial Interface .............................................................................................................. 385

START and STOP Conditions ....................................................................................................... 385

Data Validity .................................................................................................................................. 386

Addressing Format ....................................................................................................................... 386

7-bits Address Format ................................................................................................................... 386

10-bits Address Format ................................................................................................................. 387

Data Transfer and Acknowledge ................................................................................................... 388

Clock Synchronization .................................................................................................................. 389

Arbitration ..................................................................................................................................... 389

General Call Address .................................................................................................................... 390

Bus Error ....................................................................................................................................... 390

Address Mask Enable ................................................................................................................... 390

Address Snoop ............................................................................................................................. 390

Operation Mode ............................................................................................................................ 390

Conditions of Holding SCL Line .................................................................................................... 395

I2C Timeout Function .................................................................................................................... 396

PDMA Interface ............................................................................................................................. 396

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Register Map ..................................................................................................................... 397

Register Descriptions ......................................................................................................... 398

I2C Control Register – I2CCR ....................................................................................................... 398

I2C Interrupt Enable Register – I2CIER ........................................................................................ 400

I2C Address Register – I2CADDR ................................................................................................. 402

I2C Status Register – I2CSR ......................................................................................................... 402

I2C SCL High Period Generation Register – I2CSHPGR .............................................................. 405

I2C SCL Low Period Generation Register – I2CSLPGR ............................................................... 406

I2C Data Register – I2CDR ........................................................................................................... 407

I2C Target Register – I2CTAR ....................................................................................................... 408

I2C Address Mask Register – I2CADDMR .................................................................................... 409

I2C Address Snoop Register – I2CADDSR ................................................................................... 409

I2C Timeout Register – I2CTOUT.................................................................................................. 410

20 Serial Peripheral Interface (SPI) ...................................................................... 411

Introduction ........................................................................................................................ 411

Features ............................................................................................................................. 412

Functional Descriptions ..................................................................................................... 412

Master Mode ................................................................................................................................. 412

Slave Mode ................................................................................................................................... 412

SPI Serial Frame Format .............................................................................................................. 413

Status Flags .................................................................................................................................. 417

Register Map ..................................................................................................................... 420

Register Descriptions ......................................................................................................... 421

SPI Control Register 0 – SPICR0 ................................................................................................. 421

SPI Control Register 1 – SPICR1 ................................................................................................. 422

SPI Interrupt Enable Register – SPIIER ....................................................................................... 424

SPI Clock Prescaler Register – SPICPR ...................................................................................... 425

SPI Data Register – SPIDR .......................................................................................................... 426

SPI Status Register – SPISR ........................................................................................................ 426

SPI FIFO Control Register – SPIFCR ........................................................................................... 428

SPI FIFO Status Register – SPIFSR ............................................................................................ 429

SPI FIFO Time Out Counter Register – SPIFTOCR ..................................................................... 430

Table of Contents

21 Universal Synchronous Asynchronous Receiver Transmitter (USART) ..... 431

Introduction ........................................................................................................................ 431

Features ............................................................................................................................. 432

Functional Descriptions ..................................................................................................... 432

Serial Data Format ........................................................................................................................ 432

Baud Rate Generation .................................................................................................................. 433

Hardware Flow Control ................................................................................................................. 434

IrDA ............................................................................................................................................... 436

RS485 Mode ................................................................................................................................. 438

Synchronous Master Mode ........................................................................................................... 439

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Interrupts and Status .................................................................................................................... 441

PDMA Interface ............................................................................................................................. 441

Register Map ..................................................................................................................... 441

Register Descriptions ......................................................................................................... 442

USART Data Register – USRDR .................................................................................................. 442

USART Control Register – USRCR .............................................................................................. 443

USART FIFO Control Register – USRFCR................................................................................... 444

USART Interrupt Enable Register – USRIER ............................................................................... 446

USART Status & Interrupt Flag Register – USRSIFR................................................................... 447

USART Timing Parameter Register – USRTPR ........................................................................... 449

USART IrDA Control Register – IrDACR ...................................................................................... 450

USART RS485 Control Register – RS485CR............................................................................... 451

USART Synchronous Control Register – SYNCR ........................................................................ 452

USART Divider Latch Register – USRDLR................................................................................... 453

USART Test Register – USRTSTR ............................................................................................... 454

Table of Contents

22 Universal Asynchronous Receiver Transmitter (UART) ................................ 455

Introduction ........................................................................................................................ 455

Features ............................................................................................................................. 456

Functional Descriptions ..................................................................................................... 456

Serial Data Format ........................................................................................................................ 456

Baud Rate Generation .................................................................................................................. 457

Interrupts and Status .................................................................................................................... 458

PDMA Interface ............................................................................................................................. 459

Register Map ..................................................................................................................... 459

Register Descriptions ......................................................................................................... 460

UART Data Register – URDR ....................................................................................................... 460

UART Control Register – URCR ................................................................................................... 461

UART Interrupt Enable Register – URIER .................................................................................... 462

UART Status & Interrupt Flag Register – URSIFR ....................................................................... 463

UART Divider Latch Register – URDLR ....................................................................................... 465

UART Test Register – URTSTR .................................................................................................... 466

23 USB Device Controller (USB) .......................................................................... 467

Introduction ........................................................................................................................ 467

Features ............................................................................................................................. 467

Functional Descriptions ..................................................................................................... 468

Endpoints ...................................................................................................................................... 468

EP_SRAM ..................................................................................................................................... 468

Serial Interface Engine – SIE ........................................................................................................ 469

Double-Buffering ........................................................................................................................... 469

Suspend Mode and Wake-up ....................................................................................................... 471

Remote Wake-up .......................................................................................................................... 471

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Register Map ..................................................................................................................... 471

Register Descriptions ......................................................................................................... 473

USB Control and Status Register – USBCSR .............................................................................. 473

USB Interrupt Enable Register – USBIER .................................................................................... 475

USB Interrupt Status Register – USBISR ..................................................................................... 476

USB Frame Count Register – USBFCR ....................................................................................... 477

USB Device Address Register – USBDEVAR .............................................................................. 478

USB Endpoint 0 Control and Status Register – USBEP0CSR ..................................................... 479

USB Endpoint 0 Interrupt Enable Register – USBEP0IER ........................................................... 480

USB Endpoint 0 Interrupt Status Register – USBEP0ISR ............................................................ 481

USB Endpoint 0 Transfer Count Register – USBEP0TCR ........................................................... 483

USB Endpoint 0 Conguration Register – USBEP0CFGR ........................................................... 484

USB Endpoint 1 ~ 3 Control and Status Register – USBEPnCSR, n = 1 ~ 3 ............................... 485

USB Endpoint 1 ~ 3 Interrupt Enable Register – USBEPnIER, n = 1 ~ 3 ..................................... 486

USB Endpoint 1 ~ 3 Interrupt Status Register – USBEPnISR, n = 1 ~ 3 ...................................... 487

USB Endpoint 1 ~ 3 Transfer Count Register – USBEPnTCR, n = 1 ~ 3 ..................................... 488

USB Endpoint 1 ~ 3 Conguration Register – USBEPnCFGR, n = 1 ~ 3 ..................................... 489

USB Endpoint 4 ~ 7 Control and Status Register – USBEPnCSR, n = 4 ~ 7 ............................... 490

USB Endpoint 4 ~ 7 Interrupt Enable Register – USBEPnIER, n = 4 ~ 7 ..................................... 492

USB Endpoint 4 ~ 7 Interrupt Status Register – USBEPnISR, n = 4 ~ 7 ...................................... 493

USB Endpoint 4 ~ 7 Transfer Count Register – USBEPnTCR, n = 4 ~ 7 ..................................... 494

USB Endpoint 4 ~ 7 Conguration Register – USBEPnCFGR, n = 4 ~ 7 ..................................... 495

Table of Contents

24 Peripheral Direct Memory Access (PDMA) ..................................................... 496

Introduction ........................................................................................................................ 496

Features ............................................................................................................................. 496

Functional Description ....................................................................................................... 497

AHB Master .................................................................................................................................. 497

PDMA Channel ............................................................................................................................. 497

PDMA Request Mapping .............................................................................................................. 497

Channel transfer ........................................................................................................................... 498

Channel Priority ............................................................................................................................ 498

Transfer Request .......................................................................................................................... 499

Address Mode ............................................................................................................................... 499

Auto-Reload .................................................................................................................................. 500

Transfer Interrupt .......................................................................................................................... 500

Register Map ..................................................................................................................... 500

Register Descriptions ......................................................................................................... 503

PDMA Channel n Control Register – PDMACHnCR, n = 0 ~ 11 .................................................. 503

PDMA Channel n Source Address Register – PDMACHnSADR, n = 0 ~ 11 ................................ 505

PDMA Channel n Destination Address Register – PDMACHnDADR, n = 0 ~ 11 ......................... 505

PDMA Channel n Transfer Size Register – PDMACHnTSR, n = 0 ~ 11 ...................................... 506

PDMA Channel n Current Transfer Size Register – PDMACHnCTSR, n = 0 ~ 11 ....................... 507

PDMA Interrupt Status Register 0 – PDMAISR0 .......................................................................... 508

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PDMA Interrupt Status Register 1 – PDMAISR1 .......................................................................... 509

PDMA Interrupt Status Clear Register 0 – PDMAISCR0 .............................................................. 510

PDMA Interrupt Status Clear Register 1 – PDMAISCR1 ...............................................................511

PDMA Interrupt Enable Register 0 – PDMAIER0 ......................................................................... 512

PDMA Interrupt Enable Register 1 – PDMAIER1 ......................................................................... 513

25 Extend Bus Interface (EBI) ............................................................................... 514

Introduction ........................................................................................................................ 514

Features ............................................................................................................................. 514

Functional Descriptions ..................................................................................................... 515

Non-multiplexed 8-bit Data 8-bit Address Mode ........................................................................... 516

Non-multiplexed 16-bit Data N-bit Address Mode ......................................................................... 517

Multiplexed 16-bit Data, 16-bit Address Mode .............................................................................. 518

Multiplexed 8-bit Data, 24-bit Address Mode ................................................................................ 519

Page Read Operation ................................................................................................................... 520

Write Buffer and EBI Status .......................................................................................................... 523

Bus Turn-around and Idle Cycles ................................................................................................. 523

AHB Transaction Width Conversion ............................................................................................. 524

EBI Bank Access .......................................................................................................................... 525

EBI Ready ..................................................................................................................................... 526

PDMA Request ............................................................................................................................. 527

Register Map ..................................................................................................................... 527

Register Descriptions ......................................................................................................... 528

EBI Control Register – EBICR ...................................................................................................... 528

EBI Page Control Register – EBIPCR .......................................................................................... 531

EBI Status Register – EBISR ........................................................................................................ 532

EBI Address Timing Register n – EBIATRn, n = 0 ~ 3 .................................................................. 533

EBI Read Timing Register n – EBIRTRn, n = 0 ~ 3 ...................................................................... 534

EBI Write Timing Register n – EBIWTRn, n = 0 ~ 3 ..................................................................... 535

EBI Parity Register n – EBIPR, n = 0 ~ 3 ..................................................................................... 536

EBI Interrupt Enable Register – EBIIENR ..................................................................................... 537

EBI Interrupt Flag Register – EBIIFR ............................................................................................ 537

EBI Interrupt Clear Register – EBIIFCR ....................................................................................... 538

Table of Contents

26 Inter-IC Sound (I2S) ........................................................................................... 539

Introduction ........................................................................................................................ 539

Features ............................................................................................................................. 539

Functional Description ....................................................................................................... 540

I2S Master and Slave Mode .......................................................................................................... 540

I2S Clock Rate Generator ............................................................................................................. 541

I2S Interface Format ...................................................................................................................... 543

FIFO Control and Arrangement .................................................................................................... 547

PDMA and Interrupt ...................................................................................................................... 549

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Register Map ..................................................................................................................... 549

Register Descriptions ......................................................................................................... 550

I2S Control Register – I2SCR ........................................................................................................ 550

I2S Interrupt Enable Register – I2SIER ......................................................................................... 552

I2S Clock Divider Register – I2SCDR ........................................................................................... 553

I2S TX Data Register – I2STXDR ................................................................................................. 554

I2S RX Data Register – I2SRXDR ................................................................................................. 554

I2S FIFO Control Register – I2SFCR ............................................................................................ 555

I2S Status Register – I2SSR ......................................................................................................... 556

I2S Rate Counter Value Register – I2SRCNTR ............................................................................ 558

27 Cyclic Redundancy Check (CRC) .................................................................... 559

Introduction ....................................................................................................................... 559

Features ............................................................................................................................. 559

Functional Descriptions ..................................................................................................... 560

CRC Computation ......................................................................................................................... 560

Byte and Bit Reversal for CRC Computation ................................................................................ 560

CRC with PDMA ........................................................................................................................... 561

Register Map ..................................................................................................................... 561

Register Descriptions ......................................................................................................... 562

CRC Control Register – CRCCR .................................................................................................. 562

CRC Seed Register – CRCSDR ................................................................................................... 563

CRC Checksum Register – CRCCSR .......................................................................................... 563

CRC Data Register – CRCDR ...................................................................................................... 564

Table of Contents

28 SDIO Host Controller (SDIO) ............................................................................ 565

Introduction ........................................................................................................................ 565

Features ............................................................................................................................. 565

Functional Description ....................................................................................................... 565

SD Clock ....................................................................................................................................... 566

SD Protocol ................................................................................................................................... 567

Command ..................................................................................................................................... 568

Response ...................................................................................................................................... 568

Data .............................................................................................................................................. 569

Buffer Status ................................................................................................................................. 571

Interrupt ........................................................................................................................................ 571

DMA Request ................................................................................................................................ 571

Register Map ..................................................................................................................... 572

Register Description .......................................................................................................... 573

Block Size Register – BLSIZE ...................................................................................................... 573

Block Count Register – BLCNT .................................................................................................... 574

Argument Register – ARG ............................................................................................................ 574

Transfer Mode Register – TMR .................................................................................................... 575

Command Register – CMD ........................................................................................................... 576

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Response Register n – RESPn, n = 0 ~ 3 .................................................................................... 577

Data Port Register – DR ............................................................................................................... 578

Present State Register – PSR ...................................................................................................... 578

Control Register – CR ................................................................................................................... 580

Clock Control Register – CLKCR .................................................................................................. 581

Timeout Control Register – TMOCR ............................................................................................. 582

Software Reset Register – SWRST .............................................................................................. 583

Status Register – SR .................................................................................................................... 584

Status Enable Register – SER ...................................................................................................... 586

Interrupt Enable Register – IER .................................................................................................... 588

Table of Contents

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List of Tables

Table 1. Features and Peripheral List .................................................................................................... 32

Table 2. Document Conventions ............................................................................................................. 34

Table 3. Register Map ............................................................................................................................. 39

Table 4. Flash Memory and Option Byte ................................................................................................. 44

Table 5. Relationship between Wait State Cycle and HCLK ................................................................... 44

Table 6. Booting Modes .......................................................................................................................... 45

Table 7. Option Byte Memory Map ......................................................................................................... 49

Table 8. Access Permission of Protected Main Flash Page .................................................................... 50

Table 9. Access Permission When Security Protection is Enabled ......................................................... 51

Table 10. FMC Register Map ................................................................................................................. 52

Table 11. Operation Mode Denitions ..................................................................................................... 73

Table 12. Enter / Exit Power Saving Modes ............................................................................................ 74

Table 13. Power Status after System Reset ........................................................................................... 75

Table 14. PWRCU Register Map ............................................................................................................ 75

Table 15. Output Divider 2 Value Mapping.............................................................................................. 87

Table 16. Feedback Divider 2 Value Mapping......................................................................................... 88

Table 17. USB PLL Output Divider 2 Value Mapping .............................................................................. 89

Table 18. USB PLL Feedback Divider 2 Value Mapping ......................................................................... 89

Table 19. CKOUT Clock Source ............................................................................................................. 92

Table 20. CKCU Register Map ................................................................................................................ 92

Table 21. RSTCU Register Map ............................................................................................................118

Table 22. AFIO, GPIO and I/O Pad Control Signal True Table.............................................................. 126

Table 23. GPIO Register Map ............................................................................................................... 127

Table 24. AFIO Selection for Peripheral Map Example ......................................................................... 161

Table 25. AFIO Register Map ................................................................................................................ 161

Table 26. Exception types ..................................................................................................................... 166

Table 27. NVIC Register Map ............................................................................................................... 169

Table 28. EXTI Register Map ................................................................................................................ 174

Table 29. Data Format in ADCDRy [15:0] (y = 0 ~ 11) and ADCHDRy [15:0] (y = 0 ~ 3)...................... 190

Table 30. A/D Converter Register Map ................................................................................................. 191

Table 31. CMP Register Map ................................................................................................................ 218

Table 32. Counting Direction and Encoding Signals ............................................................................. 241

Table 33. Register Map of GPTM ......................................................................................................... 250

Table 34. GPTM Internal Trigger Connection ....................................................................................... 256

Table 35. BFTM Register Map .............................................................................................................. 287

Table 36. Compare Match Output Setup .............................................................................................. 305

Table 37. Output Control Bits for Complementary Output with a Break Event Occurrence .................. 313

Table 38. Counting Direction and Encoding Signals ............................................................................. 316

Table 39. Lock Level Table.................................................................................................................... 324

List of Tables

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Table 40. MCTM Register Map ............................................................................................................. 326

Table 41. MCTM Internal Trigger Connection ....................................................................................... 332

Table 42. LSE Startup Mode Operating Current and Startup Time ...................................................... 366

Table 43. RTCOUT Output Mode and Active Level Setting .................................................................. 367

Table 44. RTC Register Map................................................................................................................. 368

Table 45. Watchdog Timer Register Map .............................................................................................. 377

Table 46. Conditions of Holding SCL Line ............................................................................................ 395

Table 47. I2C Register Map ................................................................................................................... 397

Table 48. I2C Clock Setting Example .................................................................................................... 407

Table 49. SPI Interface Format Setup ................................................................................................... 413

Table 50. SPI Mode Fault Trigger Conditions ....................................................................................... 418

Table 51. SPI Master Mode SEL Pin Status ......................................................................................... 419

Table 52. SPI Register Map .................................................................................................................. 420

Table 53. Baud Rate Deviation Error Calculation – CK_USART = 48 MHz .......................................... 434

Table 54. Baud Rate Deviation Error Calculation – CK_USART = 96 MHz .......................................... 434

Table 55. USART Register Map ............................................................................................................ 441

Table 56. Baud Rate Deviation Error Calculation – CK_UART = 48 MHz ............................................ 458

Table 57. Baud Rate Deviation Error Calculation – CK_UART = 96 MHz ............................................ 458

Table 58. UART Register Map .............................................................................................................. 459

Table 59. Endpoint Characteristics ....................................................................................................... 468

Table 60. USB Data Types and Buffer Size .......................................................................................... 468

Table 61. USB Register Map ................................................................................................................ 471

Table 62. Resume Event Detection ...................................................................................................... 474

Table 63. PDMA Channel Assignments ................................................................................................ 498

Table 64. PDMA Address Modes .......................................................................................................... 499

Table 65. PDMA Register Map .............................................................................................................. 500

Table 66. EBI Maps AHB Transactions Width to External Device Transactions ................................... 524

Table 67. EBI Maps AHB Transactions Width to External Device Transactions Width Using Byte Lane

EBI_BL [1:0] ........................................................................................................................................... 525

Table 68. Register Map of EBI .............................................................................................................. 527

Table 69. Recommend FS List @ 8 MHz PCLK ................................................................................... 541

Table 70. Recommend FS List @ 48 MHz PCLK ................................................................................. 542

Table 71. Recommend FS List @ 72 MHz PCLK ................................................................................. 542

Table 72. Recommend FS List @ 96 MHz PCLK ................................................................................. 542

Table 73. I2S Register Map .................................................................................................................. 549

Table 74. Register Map of CRC ............................................................................................................ 561

Table 75. Command Format ................................................................................................................. 568

Table 76. Response R1 Format ............................................................................................................ 568

Table 77. Response R2 Format ............................................................................................................ 569

Table 78. Response R3 Format ............................................................................................................ 569

Table 79. Response R6 Format ............................................................................................................ 569

List of Tables

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Table 80. Response R7 Format ............................................................................................................ 569

Table 81. SDIO Command Register Fields and Values ........................................................................ 571

Table 82. SDIO Register Map ............................................................................................................... 572

List of Tables

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List of Figures

Figure 1. Block Diagram ......................................................................................................................... 33

Figure 2. Cortex®-M3 Block Diagram ...................................................................................................... 36

Figure 3. Bus Architecture ...................................................................................................................... 37

Figure 4. Memory Map ............................................................................................................................ 38

Figure 5. Flash Memory Controller Block Diagram ................................................................................. 42

Figure 6. Flash Memory Map .................................................................................................................. 43

Figure 7. Vector Remapping ................................................................................................................... 45

Figure 8. Page Erases Operation Flowchart ........................................................................................... 46

Figure 9. Mass Erases Operation Flowchart .......................................................................................... 47

Figure 10. Word Programming Operation Flowchart .............................................................................. 48

Figure 11. PWRCU Block Diagram ......................................................................................................... 69

Figure 12. Power On Reset / Power Down Reset Waveform ................................................................. 72

Figure 13. CKCU Block Diagram ............................................................................................................ 83

Figure 14. External Crystal, Ceramic and Resonators for HSE .............................................................. 84

Figure 15. HSI Auto Trimming Block Diagram ........................................................................................ 86

Figure 16. PLL Block Diagram ................................................................................................................ 87

Figure 17. USB PLL Block Diagram ........................................................................................................ 88

Figure 18. External crystal, Ceramic and Resonators for LSE .............................................................. 90

Figure 19. RSTCU Block Diagram .........................................................................................................117

Figure 20. Power On Reset Sequence ..................................................................................................118

Figure 21. GPIO Block Diagram ........................................................................................................... 124

Figure 22. AFIO / GPIO Control Signal ................................................................................................. 126

Figure 23. AFIO Block Diagram ............................................................................................................ 159

Figure 24. EXTI Channel Input Selection ............................................................................................. 160

Figure 25. EXTI Block Diagram ............................................................................................................ 171

Figure 26. EXTI Wake-up Event Management ..................................................................................... 172

Figure 27. EXTI Interrupt De-bounce Function ..................................................................................... 173

Figure 28. ADC Block Diagram ............................................................................................................. 180

Figure 29. One Shot Conversion Mode ................................................................................................ 183

Figure 30. Continuous Conversion Mode ............................................................................................. 184

Figure 31. Regular Group Discontinuous Conversion Mode ................................................................ 186

Figure 32. High Priority Group Discontinuous Conversion Mode ......................................................... 187

Figure 33. High Priority Group Management ........................................................................................ 189

Figure 34. CMP with Digital I/O Block Diagram .................................................................................... 215

Figure 35. 6-Bit Scaler for Comparator Voltage Reference Block Diagram .......................................... 216

Figure 36. Interrupt Signals of Comparators ......................................................................................... 217

Figure 37. Wakeup Signals of Comparators ......................................................................................... 217

Figure 38. Block Diagram of GPTM ..................................................................................................... 224

Figure 39. Up-counting Example .......................................................................................................... 226

List of Figures

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Figure 40. Down-counting Example ...................................................................................................... 226

Figure 41. Center-aligned Counting Example ....................................................................................... 227

Figure 42. GPTM Clock Selection Source ............................................................................................ 228

Figure 43. Trigger Control Block ........................................................................................................... 229

Figure 44. Slave Controller Diagram .................................................................................................... 230

Figure 45. GPTM in Restart Mode ........................................................................................................ 230

Figure 46. GPTM in Pause Mode ......................................................................................................... 231

Figure 47. GPTM in Trigger Mode ........................................................................................................ 231

Figure 48. Master GPTMn and Slave GPTMm/MCTMm Connection ................................................... 232

Figure 49. MTO Selection ..................................................................................................................... 232

Figure 50. Capture / Compare Block Diagram ...................................................................................... 233

Figure 51. Input Capture Mode ............................................................................................................. 233

Figure 52. PWM Pulse Width Measurement Example .......................................................................... 234

Figure 53. Channel 0 and Channel 1 Input Stage ................................................................................ 235

Figure 54. Channel 2 and Channel 3 Input Stage ............................................................................... 236

Figure 55. Output Stage Block Diagram ............................................................................................... 236

Figure 56. Toggle Mode Channel Output Reference Signal (CHxPRE = 0) ......................................... 237

Figure 57. Toggle Mode Channel Output Reference Signal (CHxPRE = 1) ......................................... 238

Figure 58. PWM Mode Channel Output Reference Signal and Counter in Up-counting Mode ........... 238

Figure 59. PWM Mode Channel Output Reference Signal and Counter in Down-counting Mode ....... 239

Figure 60. PWM Mode Channel Output Reference Signal and Counter in Centre-align Mode ............ 239

Figure 61. Update Event Setting Diagram ............................................................................................ 240

Figure 62. Input Stage and Quadrature Decoder Block Diagram ........................................................ 241

Figure 63. Both TI0 and TI1 Quadrature Decoder Counting ................................................................ 242

Figure 64. GTn_ETI Pin Digital Filter Diagram with N = 2 .................................................................... 242

Figure 65. Clearing CHOxREF by ETIF ................................................................................................ 243

Figure 66. Single Pulse Mode ............................................................................................................... 244

Figure 67. Immediate Active Mode Minimum Delay ............................................................................. 245

Figure 68. Asymmetric PWM Mode in Center-aligned Counting Mode ................................................ 246

Figure 69. Pausing GPTM1 Using the GPTM0 CH0OREF Signal ....................................................... 247

Figure 70. Triggering GPTM1 with GPTM0 Update Event .................................................................... 247

Figure 71. Trigger GPTM0 and GPTM1 with the GPTM0 CH0 Input ................................................... 248

Figure 72. GPTM PDMA Mapping Diagram .......................................................................................... 249

Figure 73. BFTM Block Diagram .......................................................................................................... 284

Figure 74. BFTM – Repetitive Mode ..................................................................................................... 285

Figure 75. BFTM – One Shot Mode ...................................................................................................... 286

Figure 76. BFTM – One Shot Mode Counter Updating ....................................................................... 286

Figure 77. MCTM Block Diagram ......................................................................................................... 291

Figure 78. Up-counting Example .......................................................................................................... 293

Figure 79. Down-counting Example ...................................................................................................... 294

Figure 80. Center-aligned Counting Example ....................................................................................... 295

List of Figures

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Figure 81. Update Event 1 Dependent Repetition Mechanism Example .............................................. 295

Figure 82. MCTM Clock Selection Source ............................................................................................ 296

Figure 83. Trigger Control Block ........................................................................................................... 297

Figure 84. Slave Controller Diagram .................................................................................................... 298

Figure 85. MCTM in Restart Mode ....................................................................................................... 298

Figure 86. MCTM in Pause Mode ......................................................................................................... 299

Figure 87. MCTM in Trigger Mode ........................................................................................................ 299

Figure 88. Master MCTMn and Slave GPTMm/MCTMm Connection .................................................. 300

Figure 89. MTO Selection ..................................................................................................................... 300

Figure 90. Capture / Compare Block Diagram ...................................................................................... 301

Figure 91. Input Capture Mode ............................................................................................................. 301

Figure 92. PWM Pulse Width Measurement Example .......................................................................... 302

Figure 93. Channel 0 and Channel 1 Input Stages ............................................................................... 303

Figure 94. Channel 2 and Channel 3 Input Stages ............................................................................... 303

Figure 95. Output Stage Block Diagram ............................................................................................... 304

Figure 96. Toggle Mode Channel Output Reference Signal – CHxPRE = 0 ......................................... 305

Figure 97. Toggle Mode Channel Output Reference Signal – CHxPRE = 1 ......................................... 306

Figure 98. PWM Mode Channel Output Reference Signal and Counter in Up-counting Mode ............ 306

Figure 99. PWM Mode Channel Output Reference Signal and Counter in Down-counting Mode ....... 307

Figure 100. PWM Mode 1 Channel Output Reference Signal and Counter in Centre-aligned Counting

Mode ...................................................................................................................................................... 307

Figure 101. Dead-time Insertion Performed for Complementary Outputs ............................................ 308

Figure 102. MCTM Break Signal Bolck Diagram ................................................................................. 309

Figure 103. MTn_BRK Pin Digital Filter Diagram with N = 2 ................................................................ 309

Figure 104. Channel 3 Output with a Break Event Occurrence ............................................................ 310

Figure 105. Channel 0 ~ 2 Complementary Outputs with a Break Event Occurrence...........................311

Figure 106. Channel 0 ~ 2 Only One Output Enabled when Break Event Occurs ................................311

Figure 107. Hardware Protection When Both CHxO and CHxNO Are in Active Condition ................... 312

Figure 108. Update Event 1 Setup Diagram ......................................................................................... 314

Figure 109. CHxE, CHxNE and CHxOM Updated by Update Event 2 ................................................. 314

Figure 110. Update Event 2 Setup Diagram ......................................................................................... 315

Figure 111. Input Stage and Quadature Decoder Block Diagram ......................................................... 315

Figure 112. Both TI0 and TI1 Quadrature Decoder Counting ............................................................... 316

Figure 113. MTn_ETI Pin Digital Filter Diagram with N = 2 .................................................................. 317

Figure 114. Clearing CHxOREF by ETIF .............................................................................................. 317

Figure 115. Single Pulse Mode ............................................................................................................. 318

Figure 116. Immediate Active Mode Minimum Delay ............................................................................ 319

Figure 117. Asymmetric PWM Mode versus Center-aligned Counting Mode ....................................... 320

Figure 118. Pausing GPTM0 Using the MCTM0 CH0OREF Signal ..................................................... 321

Figure 119. Triggering GPTM0 with MCTM0 Update Event 1............................................................... 321

Figure 120. Trigger MCTM0 and GPTM0 with the MCTM0 CH0 Input ................................................. 322

List of Figures

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Figure 121. CH1XOR Input as Hall Sensor Interface ........................................................................... 323

Figure 122. MCTM PDMA Mapping Diagram ....................................................................................... 325

Figure 123. RTC Block Diagram ........................................................................................................... 365

Figure 124. Watchdog Timer Block Diagram ....................................................................................... 375

Figure 125. Watchdog Timer Behavior ................................................................................................. 377

Figure 126. I2C Module Block Diagram ................................................................................................. 384

Figure 127. START and STOP Condition ............................................................................................. 386

Figure 128. Data Validity ....................................................................................................................... 386

Figure 129. 7-bit Addressing Mode ....................................................................................................... 387

Figure 130. 10-bit Addressing Write Transmit Mode ............................................................................ 387

Figure 131. 10-bits Addressing Read Receive Mode .......................................................................... 388

Figure 132. I2C Bus Acknowledge ........................................................................................................ 388

Figure 133. Clock Synchronization during Arbitration ........................................................................... 389

Figure 134. Two Master Arbitration Procedure ..................................................................................... 389

Figure 135. Master Transmitter Timing Diagram .................................................................................. 391

Figure 136. Master Receiver Timing Diagram ...................................................................................... 393

Figure 137. Slave Transmitter Timing Diagram .................................................................................... 394

Figure 138. Slave Receiver Timing Diagram ........................................................................................ 395

Figure 139. SCL Timing Diagram .......................................................................................................... 406

Figure 140. SPI Block Diagram .............................................................................................................411

Figure 141. SPI Single Byte Transfer Timing Diagram – CPOL = 0, CPHA = 0 .................................... 413

Figure 142. SPI Continuous Data Transfer Timing Diagram – CPOL = 0, CPHA = 0 ........................... 414

Figure 143. SPI Single Byte Transfer Timing Diagram – CPOL = 0, CPHA = 1 .................................... 414

Figure 144. SPI Continuous Transfer Timing Diagram – CPOL = 0, CPHA = 1 .................................... 415

Figure 145. SPI Single Byte Transfer Timing Diagram – CPOL = 1, CPHA = 0 .................................... 415

Figure 146. SPI Continuous Transfer Timing Diagram – CPOL = 1, CPHA = 0 .................................... 416

Figure 147. SPI Single Byte Transfer Timing Diagram – CPOL = 1, CPHA = 1 .................................... 416

Figure 148. SPI Continuous Transfer Timing Diagram – CPOL = 1, CPHA = 1 .................................... 417

Figure 149. SPI Multi-Master Slave Environment ................................................................................. 418

Figure 150. USART Block Diagram ...................................................................................................... 431

Figure 151. USART Serial Data Format ............................................................................................... 433

Figure 152. USART Clock CK_USART and Data Frame Timing .......................................................... 433

Figure 153. Hardware Flow Control between 2 USARTs ...................................................................... 434

Figure 154. USART RTS Flow Control ................................................................................................. 435

Figure 155. USART CTS Flow Control ................................................................................................. 435

Figure 156. IrDA Modulation and Demodulation ................................................................................... 436

Figure 157. USART I/O and IrDA Block Diagram ................................................................................. 437

Figure 158. RS485 Interface and Waveform ........................................................................................ 438

Figure 159. USART Synchronous Transmission Example ................................................................... 439

Figure 160. 8-bit Format USART Synchronous Waveform ................................................................... 440

Figure 161. UART Block Diagram ......................................................................................................... 455

List of Figures

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Figure 162. UART Serial Data Format .................................................................................................. 457

Figure 163. UART Clock CK_UART and Data Frame Timing ............................................................... 457

Figure 164. USB Block Diagram ........................................................................................................... 467

Figure 165. Endpoint Buffer Allocation Example................................................................................... 469

Figure 166. Double-buffering Operation Example ................................................................................ 470

Figure 167. PDMA Block Diagram ........................................................................................................ 496

Figure 168. PDMA Request Mapping Architecture ............................................................................... 497

Figure 169. PDMA Channel Arbitration and Scheduling Example ........................................................ 499

Figure 170. EBI Block Diagram ............................................................................................................ 515

Figure 171. EBI Non-multiplexed 8-bit Data, 8-bit Address Read Operation ........................................ 516

Figure 172. EBI Non-multiplexed 8-bit Data, 8-bit Address Write Operation ........................................ 516

Figure 173. EBI Non-multiplexed 16-bit Data, N-bit Address Read Operation ..................................... 517

Figure 174. EBI Non-multiplexed 16-bit Data, N-bit Address Write Operation...................................... 517

Figure 175. An EBI Address Latch Setup Diagram ............................................................................... 518

Figure 176. EBI Multiplexed 16-bit Data, 16-bit Address Read Operation ............................................ 518

Figure 177. EBI Multiplexed 16-bit Data, 16-bit Address Write Operation ............................................ 519

Figure 178. EBI Multiplexed 8-bit Data, 24-bit Address Read Operation .............................................. 519

Figure 179. EBI Multiplexed 8-bit Data, 24-bit Address Write Operation .............................................. 520

Figure 180. EBI Non-multiplexed 8-bit Data, 8-bit Address Mode for Page Read Operation ............... 521

Figure 181. EBI Non-multiplexed 16-bit Data, N-bit Address Mode for Page Read Operation ............. 521

Figure 182. EBI Multiplexed 16-bit Data, 16-bit Address Mode for Page Read Operation ................... 521

Figure 183. EBI Multiplexed 8-bit Data, 24-bit Address Mode for Page Read Operation ..................... 522

Figure 184. EBI Page Close Example .................................................................................................. 522

Figure 185. EBI Inserts an IDLE Cycle between Transactions in the Same Bank (NOIDLE = 0) ......... 523

Figure 186. EBI De-asserts an IDLE Cycle between Transactions in the Same Bank (NOIDLE = 1) .. 524

Figure 187. EBI Bank Memory Map ...................................................................................................... 526

Figure 188. I2S Block Diagram .............................................................................................................. 539

Figure 189. Simple I2S Master/Slave Conguration .............................................................................. 540

Figure 190. I2S Clock Generator Diagram ............................................................................................ 541

Figure 191. I2S-justied Stereo Mode Waveforms ................................................................................ 543

Figure 192. I2S-justied Stereo Mode Waveforms (32-bit Channel Extended) ..................................... 543

Figure 193. Left-justied Stereo Mode Waveforms ............................................................................... 543

Figure 194. Left-justied Stereo Mode Waveforms (32-bit Channel Extended) .................................... 544

Figure 195. Right-justied Stereo Mode Waveforms ............................................................................ 544

Figure 196. Right-justied Stereo Mode Waveforms (32-bit Channel Extended) ................................. 544

Figure 197. I2S-justied Mono Mode Waveforms .................................................................................. 545

Figure 198. I2S-justied Mono Mode Waveforms (32-bit Channel Extended) ....................................... 545

Figure 199. Left-justied Mono Mode Waveforms ................................................................................ 545

Figure 200. Left-justied Mono Mode Waveforms (32-bit Channel Extended) ..................................... 546

Figure 201. Right-justied Mono Mode Waveforms .............................................................................. 546

Figure 202. Right-justied Mono Mode Waveforms (32-bit Channel Extended) ................................... 546

List of Figures

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Figure 203. I2S-justied Repeat Mode Waveforms ............................................................................... 547

Figure 204. I2S-justied Repeat Mode Waveforms (32-bit Channel Extended) .................................... 547

Figure 205. FIFO Data Content Arrangement for Various Modes ......................................................... 548

Figure 206. CRC Block Diagram .......................................................................................................... 559

Figure 207. CRC Data Bit and Byte Reversal Example ........................................................................ 560

Figure 208. SDIO Bus Topology ........................................................................................................... 565

Figure 209. SDIO Block Diagram ......................................................................................................... 565

Figure 210. Normal Speed Timing ........................................................................................................ 566

Figure 211. High Speed Timing............................................................................................................. 566

Figure 212. SD_CLK Duty Cycle .......................................................................................................... 566

Figure 213. “No Response” and “No Data” Operations ........................................................................ 567

Figure 214. “Multiple” Block Read Operation ........................................................................................ 567

Figure 215. “Multiple” Block Write Operation ........................................................................................ 567

Figure 216. Command Format .............................................................................................................. 568

Figure 217. Response Format .............................................................................................................. 568

Figure 218. Usual Data Format for Standard Bus – only DAT0 used ................................................... 569

Figure 219. Usual Data Format for Wide Bus – DAT0~DAT3 used ...................................................... 570

Figure 220. Wide Width Data Format for Standard Bus – only DAT0 used .......................................... 570

Figure 221. Wide Width Data Format for Wide Bus – DAT0 ~ DAT3 used .......................................... 570

List of Figures

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1

Overview

Introduction

This user manual provides detailed information including how to use the device, system and
bus architecture, memory organization and peripheral instructions. The target audiences for this
document are software developers, application developers and hardware developers. For more
information regarding pin assignment, package and electrical characteristics, please refer to the
HT32F12345 dat asheet.

The device is a high performance and low power consumption 32-bit microcontrollers based around
an Arm® Cortex®-M3 processor core. The Cortex®-M3 is a next-generation processor core which
is tightly coupled with Nested Vectored Interrupt Controller (NVIC), SysTick timer and including
advanced debug support.

The device operates at a frequency of up to 96 MHz with a Flash accelerator to obtain maximum

efciency. It provides 64 KB of embedded Flash memory for code/data storage and up to 16 KB

of embedded SRAM memory for system operation and application program usage. A variety of
peripherals, such as ADC, I2C, USART, UART, SPI, I2S, PDMA, GPTM, MCTM, EBI, CRC-16/32,

USB2.0 FS, SDIO and SW-DP (Serial Wire Debug Port), etc., are also implemented in the device.
Several power saving modes provide the exibility for maximum optimization between wakeup

latency and power consumption, an especially important consideration in low power applications.

The above features ensure that the device is suitable for use in a wide range of applications,
especially in areas such as white goods application control, power monitors, alarm systems,
consumer products, handheld equipment, data logging applications, motor control and so on.

Introduction

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Features

▄

Core

● 32-bit Arm

● Up to 96 MHz operation frequency

● Single-cycle multiplication and hardware division

● Integrated Nested Vectored Interrupt Controller (NVIC)

● 24-bit SysTick timer

▄

On-chip memory

● 64 KB on-chip Flash memory for instruction/data and options storage

● Up to 16 KB on-chip SRAM

● Supports multiple boot modes

▄

Flash Memory Controller – FMC

● Flash accelerator to obtain maximum efciency

● 32-bit word programming with In System Programming Interface (ISP) and In Application

Programming (IAP)

● Flash protection capability to prevent illegal access

▄

Reset Control Unit – RSTCU

● Supply supervisor: Power On Reset / Power Down Rese (POR/PDR), Brown-out Detector

(BOD) and Programmable Low Voltage Detector (LVD)

▄

Clock Control Unit – CKCU

● External 4 to 16 MHz crystal oscillator

● External 32.768 kHz crystal oscillator

● Internal 8 MHz RC oscillator trimmed to ±2 % accuracy at 3.3 V operating voltage and 25 ºC

operating temperature

● Internal 32 kHz RC oscillator

● Integrated system clock PLL

● Independent clock divider and gating bits for peripheral clock sources

▄

Power management – PWRCU

● Single VDD power supply: 2.0 V to 3.6 V

● Integrated 1.5 V LDO regulator for CPU core, peripherals and memories power supply

● V

BAT

● Three power domains: VDD, 1.5 V and Backup

● Four power saving modes: Sleep, Deep-Sleep1, Deep-Sleep2, Power-Down

▄

External Interrupt/Event Controller – EXTI

● Up to 16 EXTI lines with congurable trigger source and type

● All GPIO pins can be selected as EXTI trigger source

● Source trigger type includes high level, low level, negative edge, positive edge, or both edge

● Individual interrupt enable, wakeup enable and status bits for each EXTI line

● Software interrupt trigger mode for each EXTI line

● Integrated deglitch lter for short pulse blocking

▄

Analog to Digital Converter – ADC

● 12-bit SAR ADC engine

● Up to 1 MSPS conversion rate

● Up to 12 external analog input channels

®

battery power supply for RTC and backup registers

Cortex®-M3 processor core

Introduction

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▄

Analog Comparator – CMP

● Rail-to-rail comparator

● Each comparator has congurable negative inputs used for exible voltage selection

– Dedicated I/O pin

– Internal voltage reference provided by 6-bit scaler

● Programmable hysteresis

● Programming speed and consumption

● Comparator output can be output to I/O or to timers or ADC trigger inputs

● Programmable internal voltage reference provided by 6-bit scaler

● Comparator has interrupt generation capability with wakeup from Sleep or Deep Sleep modes

through the EXTI controller.

▄

I/O ports

● Up to 51 GPIOs

● Port A ~ D are mapped on 16 external interrupts (EXTI)

● Almost I/O pins are congurable output driving current

▄

Motor Control Timer – MCTM

● 16-bit up, down, up/down auto-reload counters

● Up to 4 independent channels for each timer

● 16-bit programmable prescaler allowing dividing the counter clock frequency by any factor

between 1 and 65536

● Input Capture function

● Compare Match Output

● PWM waveform generation with Edge-aligned and Center-aligned Counting Modes

● Single Pulse Mode Output

● Complementary Outputs with programmable dead-time insertion

● Supports 3-phase motor control and hall sensor interface

● Break input to force the timer’s output signals into a reset or xed condition

▄

PWM Generation and Capture Timer – GPTM

● 16-bit up, down, up/down auto-reload counters

● Up to 4 independent channels for each timer

● 16-bit programmable prescaler allowing dividing the counter clock frequency by any factor

between 1 and 65536

● Input Capture function

● Compare Match Output

● PWM waveform generation with Edge-aligned and Center-aligned Counting Modes

● Single Pulse Mode Output

● Encoder interface controller with two inputs using quadrature decoder

▄

Basic Function Timer – BFTM

● 32-bit compare/match count-up counters – no I/O control features

● One shot mode – counting stops after a match condition

● Repetitive mode – restart counter after a match condition

▄

Watchdog Timer – WDT

● 12-bit down counter with 3-bit prescaler

● Interrupt or reset event for the system

● Programmable watchdog timer window function

● Registers write protection function

Introduction

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▄

Real Time Clock – RTC

● 32-bit up-counter with a programmable prescaler

● Alarm function

● Interrupt and Wake-up event

▄

Inter-integrated Circuit – I2C

● Supports both master and slave modes with a frequency of up to 1 MHz

● Provides an arbitration function and clock synchronization

● Supports 7-bit and 10-bit addressing modes and general call addressing

● Supports slave multi-addressing mode with maskable address

▄

Serial Peripheral Interface – SPI

● Supports both master and slave mode

● Frequency of up to (f

● FIFO Depth: 8 levels

● Multi-master and multi-slave operations

▄

Universal Synchronous Asynchronous Receiver Transmitter – USART

● Supports both asynchronous and clocked synchronous serial communication modes

● Asynchronous operating baud rate clock frequency up to (f

erating rate clock frequency up to (f

● Capability of full duplex communication

● Fully programmable characteristics of serial communication including: word length, parity bit,

stop bit and bit order

● Error detection: Parity, overrun and frame error

● Supports Auto hardware ow control mode – RTS, CTS

● IrDA SIR encoder and decoder

● RS485 mode with output enable control

● FIFO Depth: 8 × 9 bits for both receiver and transmitter

▄

Universal Asynchronous Receiver Transmitter – UART

● Asynchronous serial communication operating baud rate clock frequency up to (f

● Capability of full duplex communication

● Fully programmable characteristics of serial communication including: word length, parity bit,

stop bit and bit order

● Error detection: Parity, overrun and frame error

▄

Inter-IC Sound – I2S

● Master or slave mode

● Mono and stereo

● I2S-justied, Left-justied and Right-justied mode

● 8/16/24/32-bit sample size with 32-bit channel extended

● 8 × 32-bit TX & RX FIFO with PDMA supported

● 8-bit Fractional Clock Divider with rate control

▄

Cyclic Redundancy Check – CRC

● Supports CRC16 polynomial: 0x8005, X16+X15+X2+1

● Supports CCITT CRC16 polynomial: 0x1021, X16+X12+X5+1

● Supports IEEE-802.3 CRC32 polynomial: 0x04C11DB7, X32+X26+X23+X22+X16+X12+X11+X

+X8+X7+X5+X4+X2+X+1

● Supports 1’s complement, byte reverse and bit reverse operation on data and checksum

/2) MHz for master mode and (f

PCLK

/8) MHz

PCLK

/3) MHz for slave mode

PCLK

/16) MHz and synchronous op-

PCLK

/16) MHz

PCLK

Introduction

10

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