Holtek HT32F12345 User Manual

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Holtek 32-Bit Microcontroller with Arm® Cortex®-M3 Core

HT32F12345

User Manual

Revision: V1.10 Date: November 28, 2018

32-Bit Arm® Cortex®-M3 MCU HT32F12345

Table of Contents

1 Introduction ........................................................................................................... 27

Overview .............................................................................................................................. 27

Features ............................................................................................................................... 28

Device Information ............................................................................................................... 32

Block Diagram ..................................................................................................................... 33

2 Document Conventions ....................................................................................... 34

3 System Architecture ............................................................................................. 35

Arm® Cortex®-M3 Processor ................................................................................................ 35

Bus Architecture ................................................................................................................... 36

Memory Organization .......................................................................................................... 37

Memory Map ................................................................................................................................... 38

Embedded Flash Memory ............................................................................................................... 41

Embedded SRAM Memory ............................................................................................................. 41

AHB Peripherals ............................................................................................................................. 41

APB Peripherals ............................................................................................................................. 41

Table of Contents

4 Flash Memory Controller (FMC) .......................................................................... 42

Introduction .......................................................................................................................... 42

Features ............................................................................................................................... 42

Functional Descriptions ....................................................................................................... 43

Flash Memory Map ......................................................................................................................... 43

Flash Memory Architecture ............................................................................................................. 44

Wait State Setting ........................................................................................................................... 44

Booting Conguration ..................................................................................................................... 45

Page Erase ..................................................................................................................................... 46

Mass Erase ..................................................................................................................................... 47

Word Programming ......................................................................................................................... 48

Option Byte Description .................................................................................................................. 49

Page Erase / Program Protection ................................................................................................... 50

Security Protection .......................................................................................................................... 51

Register Map ....................................................................................................................... 52

Register Descriptions ........................................................................................................... 53

Flash Target Address Register – TADR .......................................................................................... 53

Flash Write Data Register – WRDR ............................................................................................... 54

Flash Operation Command Register – OCMR ............................................................................... 55

Flash Operation Control Register – OPCR ..................................................................................... 56

Flash Operation Interrupt Enable Register – OIER ........................................................................ 57

Flash Operation Interrupt and Status Register – OISR .................................................................. 58

Flash Page Erase / program Protection Status Register – PPSR .................................................. 59

Flash Security Protection Status Register – CPSR ........................................................................ 60

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Flash Vector Mapping Control Register – VMCR ........................................................................... 61

Flash Manufacturer and Device ID Register – MDID ...................................................................... 62

Flash Page Number Status Register – PNSR ................................................................................ 63

Flash Page Size Status Register – PSSR ...................................................................................... 64

Device ID Register – DID ................................................................................................................ 65

Flash Pre-fetch Control Register – CFCR ...................................................................................... 66

SRAM Booting Vector Register n – SBVTn, n = 0 ~ 3 .................................................................... 67

Custom ID Register n – CIDRn, n = 0 ~ 3 ...................................................................................... 68

5 Power Control Unit (PWRCU) .............................................................................. 69

Introduction .......................................................................................................................... 69

Features ............................................................................................................................... 70

Functional Descriptions ....................................................................................................... 70

Backup Domain .............................................................................................................................. 70

VDD Power Domain .......................................................................................................................... 71

1.5 V Power Domain ....................................................................................................................... 73

Operation Modes ............................................................................................................................ 73

Register Map ....................................................................................................................... 75

Register Descriptions ........................................................................................................... 76

Backup Domain Status Register – BAKSR ..................................................................................... 76

Backup Domain Control Register – BAKCR ................................................................................... 77

Backup Domain Test Register – BAKTEST .................................................................................... 79

Low Voltage / Brown Out Detect Control and Status Register – LVDCSR ..................................... 79

Backup Register n – BAKREGn, n = 0 ~ 9 ..................................................................................... 81

Table of Contents

6 Clock Control Unit (CKCU) .................................................................................. 82

Introduction .......................................................................................................................... 82

Features ............................................................................................................................... 82

Functional Descriptions ....................................................................................................... 84

High Speed External Crystal Oscillator (HSE) ................................................................................ 84

High Speed Internal RC Oscillator (HSI) ........................................................................................ 85

Auto Trimming of High Speed Internal RC Oscillator (HSI) ............................................................ 85

Phase Locked Loop – PLL .............................................................................................................. 87

USB Phase Locked Loop – USB PLL ............................................................................................. 88

Low Speed External Crystal Oscillator – LSE ................................................................................. 90

Low Speed Internal RC Oscillator – LSI ......................................................................................... 90

Clock Ready Flag ........................................................................................................................... 90

System Clock (CK_SYS) Selection ................................................................................................ 91

HSE Clock Monitor ......................................................................................................................... 91

Clock Output Capability .................................................................................................................. 92

Register Map ....................................................................................................................... 92

Register Descriptions ........................................................................................................... 93

Global Clock Conguration Register – GCFGR .............................................................................. 93

Global Clock Control Register – GCCR .......................................................................................... 94

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Global Clock Status Register – GCSR ........................................................................................... 96

Global Clock Interrupt Register – GCIR .......................................................................................... 97

PLL Conguration Register – PLLCFGR ........................................................................................ 99

PLL Control Register – PLLCR ..................................................................................................... 100

AHB Conguration Register – AHBCFGR .................................................................................... 101

AHB Clock Control Register – AHBCCR ..................................................................................... 102

APB Conguration Register – APBCFGR ..................................................................................... 104

APB Clock Control Register 0 – APBCCR0 .................................................................................. 105

APB Clock Control Register 1 – APBCCR1 .................................................................................. 106

Clock Source Status Register – CKST ......................................................................................... 108

APB Peripheral Clock Selection Register 0 – APBPCSR0 .......................................................... 109

APB Peripheral Clock Selection Register 1 – APBPCSR1 ...........................................................111

HSI Control Register – HSICR ......................................................................................................112

HSI Auto Trimming Counter Register – HSIATCR ........................................................................113

Low Power Control Register – LPCR ..........................................................................................114

MCU Debug Control Register – MCUDBGCR ..............................................................................115

Table of Contents

7 Reset Control Unit (RSTCU) .............................................................................. 117

Introduction ........................................................................................................................ 117

Functional Descriptions ..................................................................................................... 117

Power On Reset ............................................................................................................................117

System Reset ................................................................................................................................118

AHB and APB Unit Reset ...............................................................................................................118

Register Map ..................................................................................................................... 118

Register Descriptions ......................................................................................................... 119

Global Reset Status Register – GRSR ..........................................................................................119

AHB Peripheral Reset Register – AHBPRSTR ............................................................................. 120

APB Peripheral Reset Register 0 – APBPRSTR0 ........................................................................ 121

APB Peripheral Reset Register 1 – APBPRSTR1 ........................................................................ 122

8 General Purpose I/O (GPIO) ............................................................................... 124

Introduction ........................................................................................................................ 124

Features ............................................................................................................................. 125

Functional Descriptions ..................................................................................................... 125

Default GPIO Pin Conguration .................................................................................................... 125

General Purpose I/O – GPIO ........................................................................................................ 125

GPIO Locking Mechanism ............................................................................................................ 127

Register Map ..................................................................................................................... 127

Register Descriptions ......................................................................................................... 128

Port A Data Direction Control Register – PADIRCR ..................................................................... 128

Port A Input Function Enable Control Register – PAINER ............................................................ 129

Port A Pull-Up Selection Register – PAPUR ................................................................................. 129

Port A Pull-Down Selection Register – PAPDR ............................................................................ 130

Port A Open Drain Selection Register – PAODR .......................................................................... 131

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Port A Output Current Drive Selection Register – PADRVR ......................................................... 131

Port A Lock Register – PALOCKR ................................................................................................ 132

Port A Data Input Register – PADINR ........................................................................................... 133

Port A Output Data Register – PADOUTR .................................................................................... 133

Port A Output Set / Reset Control Register – PASRR .................................................................. 134

Port A Output Reset Register – PARR .......................................................................................... 135

Port B Data Direction Control Register – PBDIRCR ..................................................................... 135

Port B Input Function Enable Control Register – PBINER ........................................................... 136

Port B Pull-Up Selection Register – PBPUR ................................................................................ 136

Port B Pull-Down Selection Register – PBPDR ............................................................................ 137

Port B Open Drain Selection Register – PBODR ......................................................................... 137

Port B Output Current Drive Selection Register – PBDRVR ........................................................ 138

Port B Lock Register – PBLOCKR ................................................................................................ 138

Port B Data Input Register – PBDINR .......................................................................................... 139

Port B Output Data Register – PBDOUTR ................................................................................... 140

Port B Output Set / Reset Control Register – PBSRR .................................................................. 141

Port B Output Reset Register – PBRR ......................................................................................... 142

Port C Data Direction Control Register – PCDIRCR .................................................................... 142

Port C Input Function Enable Control Register – PCINER ........................................................... 143

Port C Pull-Up Selection Register – PCPUR ................................................................................ 143

Port C Pull-Down Selection Register – PCPDR ........................................................................... 144

Port C Open Drain Selection Register – PCODR ......................................................................... 145

Port C Output Current Drive Selection Register – PCDRVR ........................................................ 145

Port C Lock Register – PCLOCKR ............................................................................................... 146

Port C Data Input Register – PCDINR .......................................................................................... 147

Port C Output Data Register – PCDOUTR ................................................................................... 148

Port C Output Set / Reset Control Register – PCSRR ................................................................. 149

Port C Output Reset Register – PCRR ......................................................................................... 150

Port D Data Direction Control Register – PDDIRCR .................................................................... 150

Port D Input Function Enable Control Register – PDINER ........................................................... 151

Port D Pull-Up Selection Register – PDPUR ................................................................................ 152

Port D Pull-Down Selection Register – PDPDR ........................................................................... 153

Port D Open Drain Selection Register – PDODR ......................................................................... 154

Port D Output Current Drive Selection Register – PDDRVR ........................................................ 154

Port D Lock Register – PDLOCKR ............................................................................................... 155

Port D Data Input Register – PDDINR .......................................................................................... 156

Port D Output Data Register – PDDOUTR ................................................................................... 156

Port D Output Set / Reset Control Register – PDSRR ................................................................. 157

Port D Output Reset Register – PDRR ......................................................................................... 158

Table of Contents

9 Alternate Function Input / Output Control Unit (AFIO) .................................... 159

Introduction ........................................................................................................................ 159

Features ............................................................................................................................. 160

Functional Descriptions ..................................................................................................... 160

External Interrupt Pin Selection .................................................................................................... 160

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Alternate Function ......................................................................................................................... 161

Lock Mechanism .......................................................................................................................... 161

Register Map ..................................................................................................................... 161

Register Descriptions ......................................................................................................... 162

EXTI Source Selection Register 0 – ESSR0 ................................................................................ 162

EXTI Source Selection Register 1 – ESSR1 ................................................................................ 163

GPIO x Conguration Low Register – GPxCFGLR, x = A, B, C, D ............................................... 164

GPIO x Conguration High Register – GPxCFGHR, x = A, B, C, D ............................................. 165

10 Nested Vectored Interrupt Controller (NVIC) .................................................. 166

Introduction ........................................................................................................................ 166

Features ............................................................................................................................. 169

Functional Descriptions ..................................................................................................... 169

SysTick Calibration ....................................................................................................................... 169

Register Map ..................................................................................................................... 169

Table of Contents

11 External Interrupt / Event Controller (EXTI) .................................................... 171

Introduction ........................................................................................................................ 171

Features ............................................................................................................................. 171

Functional Descriptions ..................................................................................................... 172

Wakeup Event Management......................................................................................................... 172

External Interrupt / Event Line Mapping ....................................................................................... 173

Interrupt and De-bounce ............................................................................................................... 173

Register Map ..................................................................................................................... 174

Register Descriptions ......................................................................................................... 175

EXTI Interrupt Conguration Register n – EXTICFGRn, n = 0 ~ 15 ............................................. 175

EXTI Interrupt Control Register – EXTICR ................................................................................... 176

EXTI Interrupt Edge Flag Register – EXTIEDGEFLGR ................................................................ 176

EXTI Interrupt Edge Status Register – EXTIEDGESR ................................................................. 177

EXTI Interrupt Software Set Command Register – EXTISSCR .................................................... 177

EXTI Interrupt Wakeup Control Register – EXTIWAKUPCR ........................................................ 178

EXTI Interrupt Wakeup Polarity Register – EXTIWAKUPPOLR ................................................... 179

EXTI Interrupt Wakeup Flag Register – EXTIWAKUPFLG ........................................................... 179

12 Analog to Digital Converter (ADC) .................................................................. 180

Introduction ........................................................................................................................ 180

Features ............................................................................................................................. 181

Functional Descriptions ..................................................................................................... 182

ADC Clock Setup .......................................................................................................................... 182

Regular and High Priority Channel Selection ............................................................................... 182

Conversion Modes ........................................................................................................................ 182

Start Conversion on External Event .............................................................................................. 187

High Priority Group Management ................................................................................................. 188

Sampling Time Setting .................................................................................................................. 188

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Data Format and Alignment .......................................................................................................... 190

Analog Watchdog.......................................................................................................................... 190

Interrupts ....................................................................................................................................... 190

PDMA Request ............................................................................................................................ 191

Register Map ..................................................................................................................... 191

Register Descriptions ......................................................................................................... 193

ADC Reset Register – ADCRST ................................................................................................... 193

ADC Regular Conversion Mode Register – ADCCONV ............................................................... 194

ADC High Priority Conversion Mode Register – ADCHCONV ...................................................... 195

ADC Regular Conversion List Register 0 – ADCLST0 ................................................................. 196

ADC Regular Conversion List Register 1 – ADCLST1 ................................................................. 197

ADC Regular Conversion List Register 2 – ADCLST2 ................................................................. 198

ADC High Priority Conversion List Register – ADCHLST ............................................................. 199

ADC Input Offset Register n – ADCOFRn, n = 0 ~ 11 .................................................................. 200

ADC Input Sampling Time Register n – ADCSTRn, n = 0 ~ 11 .................................................... 201

ADC Regular Conversion Data Register y – ADCDRy, y = 0 ~ 11 ................................................ 201

ADC High Priority Conversion Data Register y – ADCHDRy, y = 0 ~ 3 ........................................ 202

ADC Regular Trigger Control Register – ADCTCR ....................................................................... 203

ADC Regular Trigger Source Register – ADCTSR ....................................................................... 204

ADC High Priority Trigger Control Register – ADCHTCR ............................................................. 205

ADC High Priority Trigger Source Register – ADCHTSR ............................................................. 206

ADC Watchdog Control Register – ADCWCR .............................................................................. 207

ADC Watchdog Lower Threshold Register – ADCLTR ................................................................. 208

ADC Watchdog Upper Threshold Register – ADCUTR ................................................................ 208

ADC Interrupt Enable Register – ADCIER .................................................................................... 209

ADC Interrupt Raw Status Register – ADCIRAW ......................................................................... 210

ADC Interrupt Status Register – ADCISR ......................................................................................211

ADC Interrupt Clear Register – ADCICLR .................................................................................... 213

ADC DMA Request Register – ADCDMAR ................................................................................... 214

Table of Contents

13 Comparator (CMP) ............................................................................................ 215

Introduction ........................................................................................................................ 215

Features ............................................................................................................................. 215

Functional Descriptions ..................................................................................................... 216

Comparator Inputs and Output ..................................................................................................... 216

Comparator Reference Voltage .................................................................................................... 216

Interrupts and Wakeup.................................................................................................................. 217

Power Mode and Hysteresis ......................................................................................................... 218

Comparator Write-Protected mechanism ..................................................................................... 218

Register Map ..................................................................................................................... 218

Register Descriptions ......................................................................................................... 219

Comparator Control Register n – CMPCRn, n = 0 ~ 1 ................................................................. 219

Comparator Voltage Reference Value Register n – CVRVALRn, n = 0 ~ 1 .................................. 221

Comparator Interrupt Enable Register n – CMPIERn, n = 0 ~ 1 ................................................... 222

Comparator Transition Flag Register n – CMPTFRn, n = 0 ~ 1 .................................................... 223

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14 General-Purpose Timer (GPTM) ...................................................................... 224

Introduction ........................................................................................................................ 224

Features ............................................................................................................................. 225

Functional Descriptions ..................................................................................................... 225

Counter Mode ............................................................................................................................... 225

Clock Controller ............................................................................................................................ 227

Trigger Controller .......................................................................................................................... 228

Slave Controller ............................................................................................................................ 230

Master Controller .......................................................................................................................... 232

Channel Controller ........................................................................................................................ 232

Input Stage ................................................................................................................................... 235

Output Stage ................................................................................................................................. 236

Update Management .................................................................................................................... 240

Quadrature Decoder ..................................................................................................................... 240

Digital Filter ................................................................................................................................... 242

Clearing the CHxOREF when ETIF is high ................................................................................... 243

Single Pulse Mode ........................................................................................................................ 244

Asymmetric PWM Mode ............................................................................................................... 246

Time Interconnection .................................................................................................................... 246

Trigger ADC Start.......................................................................................................................... 249

PDMA Request ............................................................................................................................. 249

Register Map ..................................................................................................................... 250

Register Descriptions ......................................................................................................... 251

Timer Counter Conguration Register – CNTCFR ....................................................................... 251

Timer Mode Conguration Register – MDCFR ............................................................................. 252

Timer Trigger Conguration Register – TRCFR ............................................................................ 255

Timer Counter Register – CTR ..................................................................................................... 257

Channel 0 Input Conguration Register – CH0ICFR .................................................................... 258

Channel 1 Input Conguration Register – CH1ICFR .................................................................... 259

Channel 2 Input Conguration Register – CH2ICFR .................................................................... 260

Channel 3 Input Conguration Register – CH3ICFR .................................................................... 262

Channel 0 Output Conguration Register – CH0OCFR ............................................................... 263

Channel 1 Output Conguration Register – CH1OCFR ............................................................... 265

Channel 2 Output Conguration Register – CH2OCFR ............................................................... 266

Channel 3 Output Conguration Register – CH3OCFR ............................................................... 268

Channel Control Register – CHCTR ............................................................................................. 270

Channel Polarity Conguration Register – CHPOLR .................................................................... 271

Timer PDMA/Interrupt Control Register – DICTR ......................................................................... 272

Timer Event Generator Register – EVGR ..................................................................................... 273

Timer Interrupt Status Register – INTSR ...................................................................................... 275

Timer Counter Register – CNTR................................................................................................... 277

Timer Prescaler Register – PSCR ................................................................................................ 277

Timer Counter Reload Register – CRR ........................................................................................ 278

Channel 0 Capture / Compare Register – CH0CCR .................................................................... 278

Table of Contents

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Channel 1 Capture / Compare Register – CH1CCR .................................................................... 279

Channel 2 Capture / Compare Register – CH2CCR .................................................................... 280

Channel 3 Capture / Compare Register – CH3CCR .................................................................... 281

Channel 0 Asymmetric Compare Register – CH0ACR ................................................................. 282

Channel 1 Asymmetric Compare Register – CH1ACR ................................................................. 282

Channel 2 Asymmetric Compare Register – CH2ACR ................................................................. 283

Channel 3 Asymmetric Compare Register – CH3ACR ................................................................. 283

15 Basic Function Timer (BFTM) .......................................................................... 284

Introduction ........................................................................................................................ 284

Features ............................................................................................................................. 284

Functional Description ....................................................................................................... 285

Repetitive Mode ............................................................................................................................ 285

One Shot Mode ............................................................................................................................. 286

Trigger ADC Start.......................................................................................................................... 287

Register Map ..................................................................................................................... 287

Register Descriptions ......................................................................................................... 288

BFTM Control Register – BFTMCR .............................................................................................. 288

BFTM Status Register – BFTMSR ................................................................................................ 289

BFTM Counter Register – BFTMCNTR ........................................................................................ 289

BFTM Compare Value Register – BFTMCMPR ........................................................................... 290

Table of Contents

16 Motor Control Timer (MCTM) ........................................................................... 291

Introduction ........................................................................................................................ 291

Features ............................................................................................................................. 292

Functional Descriptions ..................................................................................................... 293

Counter Mode ............................................................................................................................... 293

Clock Controller ............................................................................................................................ 296

Trigger Controller .......................................................................................................................... 297

Slave Controller ............................................................................................................................ 298

Master Controller .......................................................................................................................... 300

Channel Controller ........................................................................................................................ 301

Input Stage ................................................................................................................................... 303

Output Stage ................................................................................................................................. 304

Update Management .................................................................................................................... 313

Quadrature Decoder ..................................................................................................................... 315

Digital Filter ................................................................................................................................... 317

Clearing CHxOREF when ETIF is high ......................................................................................... 317

Single Pulse Mode ........................................................................................................................ 318

Asymmetric PWM Mode ............................................................................................................... 320

Timer Interconnection ................................................................................................................... 320

Trigger ADC Start.......................................................................................................................... 324

Lock Level Table ........................................................................................................................... 324

PDMA Request ............................................................................................................................. 325

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Register Map ..................................................................................................................... 326

Register Descriptions ......................................................................................................... 327

Timer Counter Conguration Register – CNTCFR ....................................................................... 327

Timer Mode Conguration Register – MDCFR ............................................................................. 328

Timer Trigger Conguration Register – TRCFR ............................................................................ 331

Timer Counter Register – CTR ..................................................................................................... 333

Channel 0 Input Conguration Register – CH0ICFR .................................................................... 334

Channel 1 Input Conguration Register – CH1ICFR .................................................................... 335

Channel 2 Input Conguration Register – CH2ICFR .................................................................... 336

Channel 3 Input Conguration Register – CH3ICFR .................................................................... 338

Channel 0 Output Conguration Register – CH0OCFR ............................................................... 339

Channel 1 Output Conguration Register – CH1OCFR ............................................................... 341

Channel 2 Output Conguration Register – CH2OCFR ............................................................... 342

Channel 3 Output Conguration Register – CH3OCFR ............................................................... 344

Channel Control Register – CHCTR ............................................................................................. 345

Channel Polarity Conguration Register – CHPOLR .................................................................... 347

Channel Break Conguration Register – CHBRKCFR ................................................................. 348

Channel Break Control Register – CHBRKCTR ........................................................................... 349

Timer PDMA / Interrupt Control Register – DICTR ....................................................................... 352

Timer Event Generator Register – EVGR ..................................................................................... 353

Timer Interrupt Status Register – INTSR ...................................................................................... 355

Timer Counter Register – CNTR................................................................................................... 357

Timer Prescaler Register – PSCR ................................................................................................ 358

Timer Counter Reload Register – CRR ........................................................................................ 358

Timer Repetition Register – REPR ............................................................................................... 359

Channel 0 Capture / Compare Register – CH0CCR .................................................................... 359

Channel 1 Capture / Compare Register – CH1CCR .................................................................... 360

Channel 2 Capture / Compare Register – CH2CCR .................................................................... 361

Channel 3 Capture / Compare Register – CH3CCR .................................................................... 362

Channel 0 Asymmetric Compare Register – CH0ACR ................................................................. 363

Channel 1 Asymmetric Compare Register – CH1ACR ................................................................. 363

Channel 2 Asymmetric Compare Register – CH2ACR ................................................................. 364

Channel 3 Asymmetric Compare Register – CH3ACR ................................................................. 364

Table of Contents

17 Real Time Clock (RTC) ..................................................................................... 365

Introduction ........................................................................................................................ 365

Features ............................................................................................................................. 365

Functional Descriptions ..................................................................................................... 366

RTC Related Register Reset ........................................................................................................ 366

Reading RTC Register .................................................................................................................. 366

Low Speed Clock Conguration ................................................................................................... 366

RTC Counter Operation ................................................................................................................ 366

Interrupt and Wakeup Control ....................................................................................................... 367

RTCOUT Output Pin Conguration............................................................................................... 367

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Register Map ..................................................................................................................... 368

Register Descriptions ......................................................................................................... 369

RTC Counter Register – RTCCNT ................................................................................................ 369

RTC Compare Register – RTCCMP ............................................................................................. 370

RTC Control Register – RTCCR ................................................................................................... 371

RTC Status Register – RTCSR..................................................................................................... 373

RTC Interrupt and Wakeup Enable Register – RTCIWEN ............................................................ 374

18 Watchdog Timer (WDT) .................................................................................... 375

Introduction ........................................................................................................................ 375

Features ............................................................................................................................. 375

Functional Description ....................................................................................................... 376

Register Map ..................................................................................................................... 377

Register Descriptions ......................................................................................................... 378

Watchdog Timer Control Register – WDTCR ............................................................................... 378

Watchdog Timer Mode Register 0 – WDTMR0............................................................................. 379

Watchdog Timer Mode Register 1 – WDTMR1............................................................................. 380

Watchdog Timer Status Register – WDTSR ................................................................................. 381

Watchdog Timer Protection Register – WDTPR ........................................................................... 382

Watchdog Timer Clock Selection Register – WDTCSR ................................................................ 383

Table of Contents

19 Inter-Integrated Circuit (I2C) ............................................................................ 384

Introduction ........................................................................................................................ 384

Features ............................................................................................................................. 385

Functional Descriptions ..................................................................................................... 385

Two Wire Serial Interface .............................................................................................................. 385

START and STOP Conditions ....................................................................................................... 385

Data Validity .................................................................................................................................. 386

Addressing Format ....................................................................................................................... 386

7-bits Address Format ................................................................................................................... 386

10-bits Address Format ................................................................................................................. 387

Data Transfer and Acknowledge ................................................................................................... 388

Clock Synchronization .................................................................................................................. 389

Arbitration ..................................................................................................................................... 389

General Call Address .................................................................................................................... 390

Bus Error ....................................................................................................................................... 390

Address Mask Enable ................................................................................................................... 390

Address Snoop ............................................................................................................................. 390

Operation Mode ............................................................................................................................ 390

Conditions of Holding SCL Line .................................................................................................... 395

I2C Timeout Function .................................................................................................................... 396

PDMA Interface ............................................................................................................................. 396

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Register Map ..................................................................................................................... 397

Register Descriptions ......................................................................................................... 398

I2C Control Register – I2CCR ....................................................................................................... 398

I2C Interrupt Enable Register – I2CIER ........................................................................................ 400

I2C Address Register – I2CADDR ................................................................................................. 402

I2C Status Register – I2CSR ......................................................................................................... 402

I2C SCL High Period Generation Register – I2CSHPGR .............................................................. 405

I2C SCL Low Period Generation Register – I2CSLPGR ............................................................... 406

I2C Data Register – I2CDR ........................................................................................................... 407

I2C Target Register – I2CTAR ....................................................................................................... 408

I2C Address Mask Register – I2CADDMR .................................................................................... 409

I2C Address Snoop Register – I2CADDSR ................................................................................... 409

I2C Timeout Register – I2CTOUT.................................................................................................. 410

20 Serial Peripheral Interface (SPI) ...................................................................... 411

Introduction ........................................................................................................................ 411

Features ............................................................................................................................. 412

Functional Descriptions ..................................................................................................... 412

Master Mode ................................................................................................................................. 412

Slave Mode ................................................................................................................................... 412

SPI Serial Frame Format .............................................................................................................. 413

Status Flags .................................................................................................................................. 417

Register Map ..................................................................................................................... 420

Register Descriptions ......................................................................................................... 421

SPI Control Register 0 – SPICR0 ................................................................................................. 421

SPI Control Register 1 – SPICR1 ................................................................................................. 422

SPI Interrupt Enable Register – SPIIER ....................................................................................... 424

SPI Clock Prescaler Register – SPICPR ...................................................................................... 425

SPI Data Register – SPIDR .......................................................................................................... 426

SPI Status Register – SPISR ........................................................................................................ 426

SPI FIFO Control Register – SPIFCR ........................................................................................... 428

SPI FIFO Status Register – SPIFSR ............................................................................................ 429

SPI FIFO Time Out Counter Register – SPIFTOCR ..................................................................... 430

Table of Contents

21 Universal Synchronous Asynchronous Receiver Transmitter (USART) ..... 431

Introduction ........................................................................................................................ 431

Features ............................................................................................................................. 432

Functional Descriptions ..................................................................................................... 432

Serial Data Format ........................................................................................................................ 432

Baud Rate Generation .................................................................................................................. 433

Hardware Flow Control ................................................................................................................. 434

IrDA ............................................................................................................................................... 436

RS485 Mode ................................................................................................................................. 438

Synchronous Master Mode ........................................................................................................... 439

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Interrupts and Status .................................................................................................................... 441

PDMA Interface ............................................................................................................................. 441

Register Map ..................................................................................................................... 441

Register Descriptions ......................................................................................................... 442

USART Data Register – USRDR .................................................................................................. 442

USART Control Register – USRCR .............................................................................................. 443

USART FIFO Control Register – USRFCR................................................................................... 444

USART Interrupt Enable Register – USRIER ............................................................................... 446

USART Status & Interrupt Flag Register – USRSIFR................................................................... 447

USART Timing Parameter Register – USRTPR ........................................................................... 449

USART IrDA Control Register – IrDACR ...................................................................................... 450

USART RS485 Control Register – RS485CR............................................................................... 451

USART Synchronous Control Register – SYNCR ........................................................................ 452

USART Divider Latch Register – USRDLR................................................................................... 453

USART Test Register – USRTSTR ............................................................................................... 454

Table of Contents

22 Universal Asynchronous Receiver Transmitter (UART) ................................ 455

Introduction ........................................................................................................................ 455

Features ............................................................................................................................. 456

Functional Descriptions ..................................................................................................... 456

Serial Data Format ........................................................................................................................ 456

Baud Rate Generation .................................................................................................................. 457

Interrupts and Status .................................................................................................................... 458

PDMA Interface ............................................................................................................................. 459

Register Map ..................................................................................................................... 459

Register Descriptions ......................................................................................................... 460

UART Data Register – URDR ....................................................................................................... 460

UART Control Register – URCR ................................................................................................... 461

UART Interrupt Enable Register – URIER .................................................................................... 462

UART Status & Interrupt Flag Register – URSIFR ....................................................................... 463

UART Divider Latch Register – URDLR ....................................................................................... 465

UART Test Register – URTSTR .................................................................................................... 466

23 USB Device Controller (USB) .......................................................................... 467

Introduction ........................................................................................................................ 467

Features ............................................................................................................................. 467

Functional Descriptions ..................................................................................................... 468

Endpoints ...................................................................................................................................... 468

EP_SRAM ..................................................................................................................................... 468

Serial Interface Engine – SIE ........................................................................................................ 469

Double-Buffering ........................................................................................................................... 469

Suspend Mode and Wake-up ....................................................................................................... 471

Remote Wake-up .......................................................................................................................... 471

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Register Map ..................................................................................................................... 471

Register Descriptions ......................................................................................................... 473

USB Control and Status Register – USBCSR .............................................................................. 473

USB Interrupt Enable Register – USBIER .................................................................................... 475

USB Interrupt Status Register – USBISR ..................................................................................... 476

USB Frame Count Register – USBFCR ....................................................................................... 477

USB Device Address Register – USBDEVAR .............................................................................. 478

USB Endpoint 0 Control and Status Register – USBEP0CSR ..................................................... 479

USB Endpoint 0 Interrupt Enable Register – USBEP0IER ........................................................... 480

USB Endpoint 0 Interrupt Status Register – USBEP0ISR ............................................................ 481

USB Endpoint 0 Transfer Count Register – USBEP0TCR ........................................................... 483

USB Endpoint 0 Conguration Register – USBEP0CFGR ........................................................... 484

USB Endpoint 1 ~ 3 Control and Status Register – USBEPnCSR, n = 1 ~ 3 ............................... 485

USB Endpoint 1 ~ 3 Interrupt Enable Register – USBEPnIER, n = 1 ~ 3 ..................................... 486

USB Endpoint 1 ~ 3 Interrupt Status Register – USBEPnISR, n = 1 ~ 3 ...................................... 487

USB Endpoint 1 ~ 3 Transfer Count Register – USBEPnTCR, n = 1 ~ 3 ..................................... 488

USB Endpoint 1 ~ 3 Conguration Register – USBEPnCFGR, n = 1 ~ 3 ..................................... 489

USB Endpoint 4 ~ 7 Control and Status Register – USBEPnCSR, n = 4 ~ 7 ............................... 490

USB Endpoint 4 ~ 7 Interrupt Enable Register – USBEPnIER, n = 4 ~ 7 ..................................... 492

USB Endpoint 4 ~ 7 Interrupt Status Register – USBEPnISR, n = 4 ~ 7 ...................................... 493

USB Endpoint 4 ~ 7 Transfer Count Register – USBEPnTCR, n = 4 ~ 7 ..................................... 494

USB Endpoint 4 ~ 7 Conguration Register – USBEPnCFGR, n = 4 ~ 7 ..................................... 495

Table of Contents

24 Peripheral Direct Memory Access (PDMA) ..................................................... 496

Introduction ........................................................................................................................ 496

Features ............................................................................................................................. 496

Functional Description ....................................................................................................... 497

AHB Master .................................................................................................................................. 497

PDMA Channel ............................................................................................................................. 497

PDMA Request Mapping .............................................................................................................. 497

Channel transfer ........................................................................................................................... 498

Channel Priority ............................................................................................................................ 498

Transfer Request .......................................................................................................................... 499

Address Mode ............................................................................................................................... 499

Auto-Reload .................................................................................................................................. 500

Transfer Interrupt .......................................................................................................................... 500

Register Map ..................................................................................................................... 500

Register Descriptions ......................................................................................................... 503

PDMA Channel n Control Register – PDMACHnCR, n = 0 ~ 11 .................................................. 503

PDMA Channel n Source Address Register – PDMACHnSADR, n = 0 ~ 11 ................................ 505

PDMA Channel n Destination Address Register – PDMACHnDADR, n = 0 ~ 11 ......................... 505

PDMA Channel n Transfer Size Register – PDMACHnTSR, n = 0 ~ 11 ...................................... 506

PDMA Channel n Current Transfer Size Register – PDMACHnCTSR, n = 0 ~ 11 ....................... 507

PDMA Interrupt Status Register 0 – PDMAISR0 .......................................................................... 508

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PDMA Interrupt Status Register 1 – PDMAISR1 .......................................................................... 509

PDMA Interrupt Status Clear Register 0 – PDMAISCR0 .............................................................. 510

PDMA Interrupt Status Clear Register 1 – PDMAISCR1 ...............................................................511

PDMA Interrupt Enable Register 0 – PDMAIER0 ......................................................................... 512

PDMA Interrupt Enable Register 1 – PDMAIER1 ......................................................................... 513

25 Extend Bus Interface (EBI) ............................................................................... 514

Introduction ........................................................................................................................ 514

Features ............................................................................................................................. 514

Functional Descriptions ..................................................................................................... 515

Non-multiplexed 8-bit Data 8-bit Address Mode ........................................................................... 516

Non-multiplexed 16-bit Data N-bit Address Mode ......................................................................... 517

Multiplexed 16-bit Data, 16-bit Address Mode .............................................................................. 518

Multiplexed 8-bit Data, 24-bit Address Mode ................................................................................ 519

Page Read Operation ................................................................................................................... 520

Write Buffer and EBI Status .......................................................................................................... 523

Bus Turn-around and Idle Cycles ................................................................................................. 523

AHB Transaction Width Conversion ............................................................................................. 524

EBI Bank Access .......................................................................................................................... 525

EBI Ready ..................................................................................................................................... 526

PDMA Request ............................................................................................................................. 527

Register Map ..................................................................................................................... 527

Register Descriptions ......................................................................................................... 528

EBI Control Register – EBICR ...................................................................................................... 528

EBI Page Control Register – EBIPCR .......................................................................................... 531

EBI Status Register – EBISR ........................................................................................................ 532

EBI Address Timing Register n – EBIATRn, n = 0 ~ 3 .................................................................. 533

EBI Read Timing Register n – EBIRTRn, n = 0 ~ 3 ...................................................................... 534

EBI Write Timing Register n – EBIWTRn, n = 0 ~ 3 ..................................................................... 535

EBI Parity Register n – EBIPR, n = 0 ~ 3 ..................................................................................... 536

EBI Interrupt Enable Register – EBIIENR ..................................................................................... 537

EBI Interrupt Flag Register – EBIIFR ............................................................................................ 537

EBI Interrupt Clear Register – EBIIFCR ....................................................................................... 538

Table of Contents

26 Inter-IC Sound (I2S) ........................................................................................... 539

Introduction ........................................................................................................................ 539

Features ............................................................................................................................. 539

Functional Description ....................................................................................................... 540

I2S Master and Slave Mode .......................................................................................................... 540

I2S Clock Rate Generator ............................................................................................................. 541

I2S Interface Format ...................................................................................................................... 543

FIFO Control and Arrangement .................................................................................................... 547

PDMA and Interrupt ...................................................................................................................... 549

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Register Map ..................................................................................................................... 549

Register Descriptions ......................................................................................................... 550

I2S Control Register – I2SCR ........................................................................................................ 550

I2S Interrupt Enable Register – I2SIER ......................................................................................... 552

I2S Clock Divider Register – I2SCDR ........................................................................................... 553

I2S TX Data Register – I2STXDR ................................................................................................. 554

I2S RX Data Register – I2SRXDR ................................................................................................. 554

I2S FIFO Control Register – I2SFCR ............................................................................................ 555

I2S Status Register – I2SSR ......................................................................................................... 556

I2S Rate Counter Value Register – I2SRCNTR ............................................................................ 558

27 Cyclic Redundancy Check (CRC) .................................................................... 559

Introduction ....................................................................................................................... 559

Features ............................................................................................................................. 559

Functional Descriptions ..................................................................................................... 560

CRC Computation ......................................................................................................................... 560

Byte and Bit Reversal for CRC Computation ................................................................................ 560

CRC with PDMA ........................................................................................................................... 561

Register Map ..................................................................................................................... 561

Register Descriptions ......................................................................................................... 562

CRC Control Register – CRCCR .................................................................................................. 562

CRC Seed Register – CRCSDR ................................................................................................... 563

CRC Checksum Register – CRCCSR .......................................................................................... 563

CRC Data Register – CRCDR ...................................................................................................... 564

Table of Contents

28 SDIO Host Controller (SDIO) ............................................................................ 565

Introduction ........................................................................................................................ 565

Features ............................................................................................................................. 565

Functional Description ....................................................................................................... 565

SD Clock ....................................................................................................................................... 566

SD Protocol ................................................................................................................................... 567

Command ..................................................................................................................................... 568

Response ...................................................................................................................................... 568

Data .............................................................................................................................................. 569

Buffer Status ................................................................................................................................. 571

Interrupt ........................................................................................................................................ 571

DMA Request ................................................................................................................................ 571

Register Map ..................................................................................................................... 572

Register Description .......................................................................................................... 573

Block Size Register – BLSIZE ...................................................................................................... 573

Block Count Register – BLCNT .................................................................................................... 574

Argument Register – ARG ............................................................................................................ 574

Transfer Mode Register – TMR .................................................................................................... 575

Command Register – CMD ........................................................................................................... 576

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Response Register n – RESPn, n = 0 ~ 3 .................................................................................... 577

Data Port Register – DR ............................................................................................................... 578

Present State Register – PSR ...................................................................................................... 578

Control Register – CR ................................................................................................................... 580

Clock Control Register – CLKCR .................................................................................................. 581

Timeout Control Register – TMOCR ............................................................................................. 582

Software Reset Register – SWRST .............................................................................................. 583

Status Register – SR .................................................................................................................... 584

Status Enable Register – SER ...................................................................................................... 586

Interrupt Enable Register – IER .................................................................................................... 588

Table of Contents

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List of Tables

Table 1. Features and Peripheral List .................................................................................................... 32

Table 2. Document Conventions ............................................................................................................. 34

Table 3. Register Map ............................................................................................................................. 39

Table 4. Flash Memory and Option Byte ................................................................................................. 44

Table 5. Relationship between Wait State Cycle and HCLK ................................................................... 44

Table 6. Booting Modes .......................................................................................................................... 45

Table 7. Option Byte Memory Map ......................................................................................................... 49

Table 8. Access Permission of Protected Main Flash Page .................................................................... 50

Table 9. Access Permission When Security Protection is Enabled ......................................................... 51

Table 10. FMC Register Map ................................................................................................................. 52

Table 11. Operation Mode Denitions ..................................................................................................... 73

Table 12. Enter / Exit Power Saving Modes ............................................................................................ 74

Table 13. Power Status after System Reset ........................................................................................... 75

Table 14. PWRCU Register Map ............................................................................................................ 75

Table 15. Output Divider 2 Value Mapping.............................................................................................. 87

Table 16. Feedback Divider 2 Value Mapping......................................................................................... 88

Table 17. USB PLL Output Divider 2 Value Mapping .............................................................................. 89

Table 18. USB PLL Feedback Divider 2 Value Mapping ......................................................................... 89

Table 19. CKOUT Clock Source ............................................................................................................. 92

Table 20. CKCU Register Map ................................................................................................................ 92

Table 21. RSTCU Register Map ............................................................................................................118

Table 22. AFIO, GPIO and I/O Pad Control Signal True Table.............................................................. 126

Table 23. GPIO Register Map ............................................................................................................... 127

Table 24. AFIO Selection for Peripheral Map Example ......................................................................... 161

Table 25. AFIO Register Map ................................................................................................................ 161

Table 26. Exception types ..................................................................................................................... 166

Table 27. NVIC Register Map ............................................................................................................... 169

Table 28. EXTI Register Map ................................................................................................................ 174

Table 29. Data Format in ADCDRy [15:0] (y = 0 ~ 11) and ADCHDRy [15:0] (y = 0 ~ 3)...................... 190

Table 30. A/D Converter Register Map ................................................................................................. 191

Table 31. CMP Register Map ................................................................................................................ 218

Table 32. Counting Direction and Encoding Signals ............................................................................. 241

Table 33. Register Map of GPTM ......................................................................................................... 250

Table 34. GPTM Internal Trigger Connection ....................................................................................... 256

Table 35. BFTM Register Map .............................................................................................................. 287

Table 36. Compare Match Output Setup .............................................................................................. 305

Table 37. Output Control Bits for Complementary Output with a Break Event Occurrence .................. 313

Table 38. Counting Direction and Encoding Signals ............................................................................. 316

Table 39. Lock Level Table.................................................................................................................... 324

List of Tables

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Table 40. MCTM Register Map ............................................................................................................. 326

Table 41. MCTM Internal Trigger Connection ....................................................................................... 332

Table 42. LSE Startup Mode Operating Current and Startup Time ...................................................... 366

Table 43. RTCOUT Output Mode and Active Level Setting .................................................................. 367

Table 44. RTC Register Map................................................................................................................. 368

Table 45. Watchdog Timer Register Map .............................................................................................. 377

Table 46. Conditions of Holding SCL Line ............................................................................................ 395

Table 47. I2C Register Map ................................................................................................................... 397

Table 48. I2C Clock Setting Example .................................................................................................... 407

Table 49. SPI Interface Format Setup ................................................................................................... 413

Table 50. SPI Mode Fault Trigger Conditions ....................................................................................... 418

Table 51. SPI Master Mode SEL Pin Status ......................................................................................... 419

Table 52. SPI Register Map .................................................................................................................. 420

Table 53. Baud Rate Deviation Error Calculation – CK_USART = 48 MHz .......................................... 434

Table 54. Baud Rate Deviation Error Calculation – CK_USART = 96 MHz .......................................... 434

Table 55. USART Register Map ............................................................................................................ 441

Table 56. Baud Rate Deviation Error Calculation – CK_UART = 48 MHz ............................................ 458

Table 57. Baud Rate Deviation Error Calculation – CK_UART = 96 MHz ............................................ 458

Table 58. UART Register Map .............................................................................................................. 459

Table 59. Endpoint Characteristics ....................................................................................................... 468

Table 60. USB Data Types and Buffer Size .......................................................................................... 468

Table 61. USB Register Map ................................................................................................................ 471

Table 62. Resume Event Detection ...................................................................................................... 474

Table 63. PDMA Channel Assignments ................................................................................................ 498

Table 64. PDMA Address Modes .......................................................................................................... 499

Table 65. PDMA Register Map .............................................................................................................. 500

Table 66. EBI Maps AHB Transactions Width to External Device Transactions ................................... 524

Table 67. EBI Maps AHB Transactions Width to External Device Transactions Width Using Byte Lane

EBI_BL [1:0] ........................................................................................................................................... 525

Table 68. Register Map of EBI .............................................................................................................. 527

Table 69. Recommend FS List @ 8 MHz PCLK ................................................................................... 541

Table 70. Recommend FS List @ 48 MHz PCLK ................................................................................. 542

Table 71. Recommend FS List @ 72 MHz PCLK ................................................................................. 542

Table 72. Recommend FS List @ 96 MHz PCLK ................................................................................. 542

Table 73. I2S Register Map .................................................................................................................. 549

Table 74. Register Map of CRC ............................................................................................................ 561

Table 75. Command Format ................................................................................................................. 568

Table 76. Response R1 Format ............................................................................................................ 568

Table 77. Response R2 Format ............................................................................................................ 569

Table 78. Response R3 Format ............................................................................................................ 569

Table 79. Response R6 Format ............................................................................................................ 569

List of Tables

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Table 80. Response R7 Format ............................................................................................................ 569

Table 81. SDIO Command Register Fields and Values ........................................................................ 571

Table 82. SDIO Register Map ............................................................................................................... 572

List of Tables

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List of Figures

Figure 1. Block Diagram ......................................................................................................................... 33

Figure 2. Cortex®-M3 Block Diagram ...................................................................................................... 36

Figure 3. Bus Architecture ...................................................................................................................... 37

Figure 4. Memory Map ............................................................................................................................ 38

Figure 5. Flash Memory Controller Block Diagram ................................................................................. 42

Figure 6. Flash Memory Map .................................................................................................................. 43

Figure 7. Vector Remapping ................................................................................................................... 45

Figure 8. Page Erases Operation Flowchart ........................................................................................... 46

Figure 9. Mass Erases Operation Flowchart .......................................................................................... 47

Figure 10. Word Programming Operation Flowchart .............................................................................. 48

Figure 11. PWRCU Block Diagram ......................................................................................................... 69

Figure 12. Power On Reset / Power Down Reset Waveform ................................................................. 72

Figure 13. CKCU Block Diagram ............................................................................................................ 83

Figure 14. External Crystal, Ceramic and Resonators for HSE .............................................................. 84

Figure 15. HSI Auto Trimming Block Diagram ........................................................................................ 86

Figure 16. PLL Block Diagram ................................................................................................................ 87

Figure 17. USB PLL Block Diagram ........................................................................................................ 88

Figure 18. External crystal, Ceramic and Resonators for LSE .............................................................. 90

Figure 19. RSTCU Block Diagram .........................................................................................................117

Figure 20. Power On Reset Sequence ..................................................................................................118

Figure 21. GPIO Block Diagram ........................................................................................................... 124

Figure 22. AFIO / GPIO Control Signal ................................................................................................. 126

Figure 23. AFIO Block Diagram ............................................................................................................ 159

Figure 24. EXTI Channel Input Selection ............................................................................................. 160

Figure 25. EXTI Block Diagram ............................................................................................................ 171

Figure 26. EXTI Wake-up Event Management ..................................................................................... 172

Figure 27. EXTI Interrupt De-bounce Function ..................................................................................... 173

Figure 28. ADC Block Diagram ............................................................................................................. 180

Figure 29. One Shot Conversion Mode ................................................................................................ 183

Figure 30. Continuous Conversion Mode ............................................................................................. 184

Figure 31. Regular Group Discontinuous Conversion Mode ................................................................ 186

Figure 32. High Priority Group Discontinuous Conversion Mode ......................................................... 187

Figure 33. High Priority Group Management ........................................................................................ 189

Figure 34. CMP with Digital I/O Block Diagram .................................................................................... 215

Figure 35. 6-Bit Scaler for Comparator Voltage Reference Block Diagram .......................................... 216

Figure 36. Interrupt Signals of Comparators ......................................................................................... 217

Figure 37. Wakeup Signals of Comparators ......................................................................................... 217

Figure 38. Block Diagram of GPTM ..................................................................................................... 224

Figure 39. Up-counting Example .......................................................................................................... 226

List of Figures

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Figure 40. Down-counting Example ...................................................................................................... 226

Figure 41. Center-aligned Counting Example ....................................................................................... 227

Figure 42. GPTM Clock Selection Source ............................................................................................ 228

Figure 43. Trigger Control Block ........................................................................................................... 229

Figure 44. Slave Controller Diagram .................................................................................................... 230

Figure 45. GPTM in Restart Mode ........................................................................................................ 230

Figure 46. GPTM in Pause Mode ......................................................................................................... 231

Figure 47. GPTM in Trigger Mode ........................................................................................................ 231

Figure 48. Master GPTMn and Slave GPTMm/MCTMm Connection ................................................... 232

Figure 49. MTO Selection ..................................................................................................................... 232

Figure 50. Capture / Compare Block Diagram ...................................................................................... 233

Figure 51. Input Capture Mode ............................................................................................................. 233

Figure 52. PWM Pulse Width Measurement Example .......................................................................... 234

Figure 53. Channel 0 and Channel 1 Input Stage ................................................................................ 235

Figure 54. Channel 2 and Channel 3 Input Stage ............................................................................... 236

Figure 55. Output Stage Block Diagram ............................................................................................... 236

Figure 56. Toggle Mode Channel Output Reference Signal (CHxPRE = 0) ......................................... 237

Figure 57. Toggle Mode Channel Output Reference Signal (CHxPRE = 1) ......................................... 238

Figure 58. PWM Mode Channel Output Reference Signal and Counter in Up-counting Mode ........... 238

Figure 59. PWM Mode Channel Output Reference Signal and Counter in Down-counting Mode ....... 239

Figure 60. PWM Mode Channel Output Reference Signal and Counter in Centre-align Mode ............ 239

Figure 61. Update Event Setting Diagram ............................................................................................ 240

Figure 62. Input Stage and Quadrature Decoder Block Diagram ........................................................ 241

Figure 63. Both TI0 and TI1 Quadrature Decoder Counting ................................................................ 242

Figure 64. GTn_ETI Pin Digital Filter Diagram with N = 2 .................................................................... 242

Figure 65. Clearing CHOxREF by ETIF ................................................................................................ 243

Figure 66. Single Pulse Mode ............................................................................................................... 244

Figure 67. Immediate Active Mode Minimum Delay ............................................................................. 245

Figure 68. Asymmetric PWM Mode in Center-aligned Counting Mode ................................................ 246

Figure 69. Pausing GPTM1 Using the GPTM0 CH0OREF Signal ....................................................... 247

Figure 70. Triggering GPTM1 with GPTM0 Update Event .................................................................... 247

Figure 71. Trigger GPTM0 and GPTM1 with the GPTM0 CH0 Input ................................................... 248

Figure 72. GPTM PDMA Mapping Diagram .......................................................................................... 249

Figure 73. BFTM Block Diagram .......................................................................................................... 284

Figure 74. BFTM – Repetitive Mode ..................................................................................................... 285

Figure 75. BFTM – One Shot Mode ...................................................................................................... 286

Figure 76. BFTM – One Shot Mode Counter Updating ....................................................................... 286

Figure 77. MCTM Block Diagram ......................................................................................................... 291

Figure 78. Up-counting Example .......................................................................................................... 293

Figure 79. Down-counting Example ...................................................................................................... 294

Figure 80. Center-aligned Counting Example ....................................................................................... 295

List of Figures

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Figure 81. Update Event 1 Dependent Repetition Mechanism Example .............................................. 295

Figure 82. MCTM Clock Selection Source ............................................................................................ 296

Figure 83. Trigger Control Block ........................................................................................................... 297

Figure 84. Slave Controller Diagram .................................................................................................... 298

Figure 85. MCTM in Restart Mode ....................................................................................................... 298

Figure 86. MCTM in Pause Mode ......................................................................................................... 299

Figure 87. MCTM in Trigger Mode ........................................................................................................ 299

Figure 88. Master MCTMn and Slave GPTMm/MCTMm Connection .................................................. 300

Figure 89. MTO Selection ..................................................................................................................... 300

Figure 90. Capture / Compare Block Diagram ...................................................................................... 301

Figure 91. Input Capture Mode ............................................................................................................. 301

Figure 92. PWM Pulse Width Measurement Example .......................................................................... 302

Figure 93. Channel 0 and Channel 1 Input Stages ............................................................................... 303

Figure 94. Channel 2 and Channel 3 Input Stages ............................................................................... 303

Figure 95. Output Stage Block Diagram ............................................................................................... 304

Figure 96. Toggle Mode Channel Output Reference Signal – CHxPRE = 0 ......................................... 305

Figure 97. Toggle Mode Channel Output Reference Signal – CHxPRE = 1 ......................................... 306

Figure 98. PWM Mode Channel Output Reference Signal and Counter in Up-counting Mode ............ 306

Figure 99. PWM Mode Channel Output Reference Signal and Counter in Down-counting Mode ....... 307

Figure 100. PWM Mode 1 Channel Output Reference Signal and Counter in Centre-aligned Counting

Mode ...................................................................................................................................................... 307

Figure 101. Dead-time Insertion Performed for Complementary Outputs ............................................ 308

Figure 102. MCTM Break Signal Bolck Diagram ................................................................................. 309

Figure 103. MTn_BRK Pin Digital Filter Diagram with N = 2 ................................................................ 309

Figure 104. Channel 3 Output with a Break Event Occurrence ............................................................ 310

Figure 105. Channel 0 ~ 2 Complementary Outputs with a Break Event Occurrence...........................311

Figure 106. Channel 0 ~ 2 Only One Output Enabled when Break Event Occurs ................................311

Figure 107. Hardware Protection When Both CHxO and CHxNO Are in Active Condition ................... 312

Figure 108. Update Event 1 Setup Diagram ......................................................................................... 314

Figure 109. CHxE, CHxNE and CHxOM Updated by Update Event 2 ................................................. 314

Figure 110. Update Event 2 Setup Diagram ......................................................................................... 315

Figure 111. Input Stage and Quadature Decoder Block Diagram ......................................................... 315

Figure 112. Both TI0 and TI1 Quadrature Decoder Counting ............................................................... 316

Figure 113. MTn_ETI Pin Digital Filter Diagram with N = 2 .................................................................. 317

Figure 114. Clearing CHxOREF by ETIF .............................................................................................. 317

Figure 115. Single Pulse Mode ............................................................................................................. 318

Figure 116. Immediate Active Mode Minimum Delay ............................................................................ 319

Figure 117. Asymmetric PWM Mode versus Center-aligned Counting Mode ....................................... 320

Figure 118. Pausing GPTM0 Using the MCTM0 CH0OREF Signal ..................................................... 321

Figure 119. Triggering GPTM0 with MCTM0 Update Event 1............................................................... 321

Figure 120. Trigger MCTM0 and GPTM0 with the MCTM0 CH0 Input ................................................. 322

List of Figures

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Figure 121. CH1XOR Input as Hall Sensor Interface ........................................................................... 323

Figure 122. MCTM PDMA Mapping Diagram ....................................................................................... 325

Figure 123. RTC Block Diagram ........................................................................................................... 365

Figure 124. Watchdog Timer Block Diagram ....................................................................................... 375

Figure 125. Watchdog Timer Behavior ................................................................................................. 377

Figure 126. I2C Module Block Diagram ................................................................................................. 384

Figure 127. START and STOP Condition ............................................................................................. 386

Figure 128. Data Validity ....................................................................................................................... 386

Figure 129. 7-bit Addressing Mode ....................................................................................................... 387

Figure 130. 10-bit Addressing Write Transmit Mode ............................................................................ 387

Figure 131. 10-bits Addressing Read Receive Mode .......................................................................... 388

Figure 132. I2C Bus Acknowledge ........................................................................................................ 388

Figure 133. Clock Synchronization during Arbitration ........................................................................... 389

Figure 134. Two Master Arbitration Procedure ..................................................................................... 389

Figure 135. Master Transmitter Timing Diagram .................................................................................. 391

Figure 136. Master Receiver Timing Diagram ...................................................................................... 393

Figure 137. Slave Transmitter Timing Diagram .................................................................................... 394

Figure 138. Slave Receiver Timing Diagram ........................................................................................ 395

Figure 139. SCL Timing Diagram .......................................................................................................... 406

Figure 140. SPI Block Diagram .............................................................................................................411

Figure 141. SPI Single Byte Transfer Timing Diagram – CPOL = 0, CPHA = 0 .................................... 413

Figure 142. SPI Continuous Data Transfer Timing Diagram – CPOL = 0, CPHA = 0 ........................... 414

Figure 143. SPI Single Byte Transfer Timing Diagram – CPOL = 0, CPHA = 1 .................................... 414

Figure 144. SPI Continuous Transfer Timing Diagram – CPOL = 0, CPHA = 1 .................................... 415

Figure 145. SPI Single Byte Transfer Timing Diagram – CPOL = 1, CPHA = 0 .................................... 415

Figure 146. SPI Continuous Transfer Timing Diagram – CPOL = 1, CPHA = 0 .................................... 416

Figure 147. SPI Single Byte Transfer Timing Diagram – CPOL = 1, CPHA = 1 .................................... 416

Figure 148. SPI Continuous Transfer Timing Diagram – CPOL = 1, CPHA = 1 .................................... 417

Figure 149. SPI Multi-Master Slave Environment ................................................................................. 418

Figure 150. USART Block Diagram ...................................................................................................... 431

Figure 151. USART Serial Data Format ............................................................................................... 433

Figure 152. USART Clock CK_USART and Data Frame Timing .......................................................... 433

Figure 153. Hardware Flow Control between 2 USARTs ...................................................................... 434

Figure 154. USART RTS Flow Control ................................................................................................. 435

Figure 155. USART CTS Flow Control ................................................................................................. 435

Figure 156. IrDA Modulation and Demodulation ................................................................................... 436

Figure 157. USART I/O and IrDA Block Diagram ................................................................................. 437

Figure 158. RS485 Interface and Waveform ........................................................................................ 438

Figure 159. USART Synchronous Transmission Example ................................................................... 439

Figure 160. 8-bit Format USART Synchronous Waveform ................................................................... 440

Figure 161. UART Block Diagram ......................................................................................................... 455

List of Figures

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Figure 162. UART Serial Data Format .................................................................................................. 457

Figure 163. UART Clock CK_UART and Data Frame Timing ............................................................... 457

Figure 164. USB Block Diagram ........................................................................................................... 467

Figure 165. Endpoint Buffer Allocation Example................................................................................... 469

Figure 166. Double-buffering Operation Example ................................................................................ 470

Figure 167. PDMA Block Diagram ........................................................................................................ 496

Figure 168. PDMA Request Mapping Architecture ............................................................................... 497

Figure 169. PDMA Channel Arbitration and Scheduling Example ........................................................ 499

Figure 170. EBI Block Diagram ............................................................................................................ 515

Figure 171. EBI Non-multiplexed 8-bit Data, 8-bit Address Read Operation ........................................ 516

Figure 172. EBI Non-multiplexed 8-bit Data, 8-bit Address Write Operation ........................................ 516

Figure 173. EBI Non-multiplexed 16-bit Data, N-bit Address Read Operation ..................................... 517

Figure 174. EBI Non-multiplexed 16-bit Data, N-bit Address Write Operation...................................... 517

Figure 175. An EBI Address Latch Setup Diagram ............................................................................... 518

Figure 176. EBI Multiplexed 16-bit Data, 16-bit Address Read Operation ............................................ 518

Figure 177. EBI Multiplexed 16-bit Data, 16-bit Address Write Operation ............................................ 519

Figure 178. EBI Multiplexed 8-bit Data, 24-bit Address Read Operation .............................................. 519

Figure 179. EBI Multiplexed 8-bit Data, 24-bit Address Write Operation .............................................. 520

Figure 180. EBI Non-multiplexed 8-bit Data, 8-bit Address Mode for Page Read Operation ............... 521

Figure 181. EBI Non-multiplexed 16-bit Data, N-bit Address Mode for Page Read Operation ............. 521

Figure 182. EBI Multiplexed 16-bit Data, 16-bit Address Mode for Page Read Operation ................... 521

Figure 183. EBI Multiplexed 8-bit Data, 24-bit Address Mode for Page Read Operation ..................... 522

Figure 184. EBI Page Close Example .................................................................................................. 522

Figure 185. EBI Inserts an IDLE Cycle between Transactions in the Same Bank (NOIDLE = 0) ......... 523

Figure 186. EBI De-asserts an IDLE Cycle between Transactions in the Same Bank (NOIDLE = 1) .. 524

Figure 187. EBI Bank Memory Map ...................................................................................................... 526

Figure 188. I2S Block Diagram .............................................................................................................. 539

Figure 189. Simple I2S Master/Slave Conguration .............................................................................. 540

Figure 190. I2S Clock Generator Diagram ............................................................................................ 541

Figure 191. I2S-justied Stereo Mode Waveforms ................................................................................ 543

Figure 192. I2S-justied Stereo Mode Waveforms (32-bit Channel Extended) ..................................... 543

Figure 193. Left-justied Stereo Mode Waveforms ............................................................................... 543

Figure 194. Left-justied Stereo Mode Waveforms (32-bit Channel Extended) .................................... 544

Figure 195. Right-justied Stereo Mode Waveforms ............................................................................ 544

Figure 196. Right-justied Stereo Mode Waveforms (32-bit Channel Extended) ................................. 544

Figure 197. I2S-justied Mono Mode Waveforms .................................................................................. 545

Figure 198. I2S-justied Mono Mode Waveforms (32-bit Channel Extended) ....................................... 545

Figure 199. Left-justied Mono Mode Waveforms ................................................................................ 545

Figure 200. Left-justied Mono Mode Waveforms (32-bit Channel Extended) ..................................... 546

Figure 201. Right-justied Mono Mode Waveforms .............................................................................. 546

Figure 202. Right-justied Mono Mode Waveforms (32-bit Channel Extended) ................................... 546

List of Figures

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Figure 203. I2S-justied Repeat Mode Waveforms ............................................................................... 547

Figure 204. I2S-justied Repeat Mode Waveforms (32-bit Channel Extended) .................................... 547

Figure 205. FIFO Data Content Arrangement for Various Modes ......................................................... 548

Figure 206. CRC Block Diagram .......................................................................................................... 559

Figure 207. CRC Data Bit and Byte Reversal Example ........................................................................ 560

Figure 208. SDIO Bus Topology ........................................................................................................... 565

Figure 209. SDIO Block Diagram ......................................................................................................... 565

Figure 210. Normal Speed Timing ........................................................................................................ 566

Figure 211. High Speed Timing............................................................................................................. 566

Figure 212. SD_CLK Duty Cycle .......................................................................................................... 566

Figure 213. “No Response” and “No Data” Operations ........................................................................ 567

Figure 214. “Multiple” Block Read Operation ........................................................................................ 567

Figure 215. “Multiple” Block Write Operation ........................................................................................ 567

Figure 216. Command Format .............................................................................................................. 568

Figure 217. Response Format .............................................................................................................. 568

Figure 218. Usual Data Format for Standard Bus – only DAT0 used ................................................... 569

Figure 219. Usual Data Format for Wide Bus – DAT0~DAT3 used ...................................................... 570

Figure 220. Wide Width Data Format for Standard Bus – only DAT0 used .......................................... 570

Figure 221. Wide Width Data Format for Wide Bus – DAT0 ~ DAT3 used .......................................... 570

List of Figures

Rev. 1.10 26 of 590 November 28, 2018

32-Bit Arm® Cortex®-M3 MCU HT32F12345

Overview

Introduction

This user manual provides detailed information including how to use the device, system and bus architecture, memory organization and peripheral instructions. The target audiences for this document are software developers, application developers and hardware developers. For more information regarding pin assignment, package and electrical characteristics, please refer to the HT32F12345 dat asheet.

The device is a high performance and low power consumption 32-bit microcontrollers based around an Arm® Cortex®-M3 processor core. The Cortex®-M3 is a next-generation processor core which is tightly coupled with Nested Vectored Interrupt Controller (NVIC), SysTick timer and including advanced debug support.

The device operates at a frequency of up to 96 MHz with a Flash accelerator to obtain maximum

efciency. It provides 64 KB of embedded Flash memory for code/data storage and up to 16 KB

of embedded SRAM memory for system operation and application program usage. A variety of peripherals, such as ADC, I2C, USART, UART, SPI, I2S, PDMA, GPTM, MCTM, EBI, CRC-16/32,

USB2.0 FS, SDIO and SW-DP (Serial Wire Debug Port), etc., are also implemented in the device. Several power saving modes provide the exibility for maximum optimization between wakeup

latency and power consumption, an especially important consideration in low power applications.

The above features ensure that the device is suitable for use in a wide range of applications, especially in areas such as white goods application control, power monitors, alarm systems, consumer products, handheld equipment, data logging applications, motor control and so on.

Introduction

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Features

▄

Core

● 32-bit Arm

● Up to 96 MHz operation frequency

● Single-cycle multiplication and hardware division

● Integrated Nested Vectored Interrupt Controller (NVIC)

● 24-bit SysTick timer

▄

On-chip memory

● 64 KB on-chip Flash memory for instruction/data and options storage

● Up to 16 KB on-chip SRAM

● Supports multiple boot modes

▄

Flash Memory Controller – FMC

● Flash accelerator to obtain maximum efciency

● 32-bit word programming with In System Programming Interface (ISP) and In Application

Programming (IAP)

● Flash protection capability to prevent illegal access

▄

Reset Control Unit – RSTCU

● Supply supervisor: Power On Reset / Power Down Rese (POR/PDR), Brown-out Detector

(BOD) and Programmable Low Voltage Detector (LVD)

▄

Clock Control Unit – CKCU

● External 4 to 16 MHz crystal oscillator

● External 32.768 kHz crystal oscillator

● Internal 8 MHz RC oscillator trimmed to ±2 % accuracy at 3.3 V operating voltage and 25 ºC

operating temperature

● Internal 32 kHz RC oscillator

● Integrated system clock PLL

● Independent clock divider and gating bits for peripheral clock sources

▄

Power management – PWRCU

● Single VDD power supply: 2.0 V to 3.6 V

● Integrated 1.5 V LDO regulator for CPU core, peripherals and memories power supply

● V

BAT

● Three power domains: VDD, 1.5 V and Backup

● Four power saving modes: Sleep, Deep-Sleep1, Deep-Sleep2, Power-Down

▄

External Interrupt/Event Controller – EXTI

● Up to 16 EXTI lines with congurable trigger source and type

● All GPIO pins can be selected as EXTI trigger source

● Source trigger type includes high level, low level, negative edge, positive edge, or both edge

● Individual interrupt enable, wakeup enable and status bits for each EXTI line

● Software interrupt trigger mode for each EXTI line

● Integrated deglitch lter for short pulse blocking

▄

Analog to Digital Converter – ADC

● 12-bit SAR ADC engine

● Up to 1 MSPS conversion rate

● Up to 12 external analog input channels

battery power supply for RTC and backup registers

Cortex®-M3 processor core

Introduction

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32-Bit Arm® Cortex®-M3 MCU HT32F12345

▄

Analog Comparator – CMP

● Rail-to-rail comparator

● Each comparator has congurable negative inputs used for exible voltage selection

– Dedicated I/O pin

– Internal voltage reference provided by 6-bit scaler

● Programmable hysteresis

● Programming speed and consumption

● Comparator output can be output to I/O or to timers or ADC trigger inputs

● Programmable internal voltage reference provided by 6-bit scaler

● Comparator has interrupt generation capability with wakeup from Sleep or Deep Sleep modes

through the EXTI controller.

▄

I/O ports

● Up to 51 GPIOs

● Port A ~ D are mapped on 16 external interrupts (EXTI)

● Almost I/O pins are congurable output driving current

▄

Motor Control Timer – MCTM

● 16-bit up, down, up/down auto-reload counters

● Up to 4 independent channels for each timer

● 16-bit programmable prescaler allowing dividing the counter clock frequency by any factor

between 1 and 65536

● Input Capture function

● Compare Match Output

● PWM waveform generation with Edge-aligned and Center-aligned Counting Modes

● Single Pulse Mode Output

● Complementary Outputs with programmable dead-time insertion

● Supports 3-phase motor control and hall sensor interface

● Break input to force the timer’s output signals into a reset or xed condition

▄

PWM Generation and Capture Timer – GPTM

● 16-bit up, down, up/down auto-reload counters

● Up to 4 independent channels for each timer

● 16-bit programmable prescaler allowing dividing the counter clock frequency by any factor

between 1 and 65536

● Input Capture function

● Compare Match Output

● PWM waveform generation with Edge-aligned and Center-aligned Counting Modes

● Single Pulse Mode Output

● Encoder interface controller with two inputs using quadrature decoder

▄

Basic Function Timer – BFTM

● 32-bit compare/match count-up counters – no I/O control features

● One shot mode – counting stops after a match condition

● Repetitive mode – restart counter after a match condition

▄

Watchdog Timer – WDT

● 12-bit down counter with 3-bit prescaler

● Interrupt or reset event for the system

● Programmable watchdog timer window function

● Registers write protection function

Introduction

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▄

Real Time Clock – RTC

● 32-bit up-counter with a programmable prescaler

● Alarm function

● Interrupt and Wake-up event

▄

Inter-integrated Circuit – I2C

● Supports both master and slave modes with a frequency of up to 1 MHz

● Provides an arbitration function and clock synchronization

● Supports 7-bit and 10-bit addressing modes and general call addressing

● Supports slave multi-addressing mode with maskable address

▄

Serial Peripheral Interface – SPI

● Supports both master and slave mode

● Frequency of up to (f

● FIFO Depth: 8 levels

● Multi-master and multi-slave operations

▄

Universal Synchronous Asynchronous Receiver Transmitter – USART

● Supports both asynchronous and clocked synchronous serial communication modes

● Asynchronous operating baud rate clock frequency up to (f

erating rate clock frequency up to (f

● Capability of full duplex communication

● Fully programmable characteristics of serial communication including: word length, parity bit,

stop bit and bit order

● Error detection: Parity, overrun and frame error

● Supports Auto hardware ow control mode – RTS, CTS

● IrDA SIR encoder and decoder

● RS485 mode with output enable control

● FIFO Depth: 8 × 9 bits for both receiver and transmitter

▄

Universal Asynchronous Receiver Transmitter – UART

● Asynchronous serial communication operating baud rate clock frequency up to (f

● Capability of full duplex communication

● Fully programmable characteristics of serial communication including: word length, parity bit,

stop bit and bit order

● Error detection: Parity, overrun and frame error

▄

Inter-IC Sound – I2S

● Master or slave mode

● Mono and stereo

● I2S-justied, Left-justied and Right-justied mode

● 8/16/24/32-bit sample size with 32-bit channel extended

● 8 × 32-bit TX & RX FIFO with PDMA supported

● 8-bit Fractional Clock Divider with rate control

▄

Cyclic Redundancy Check – CRC

● Supports CRC16 polynomial: 0x8005, X16+X15+X2+1

● Supports CCITT CRC16 polynomial: 0x1021, X16+X12+X5+1

● Supports IEEE-802.3 CRC32 polynomial: 0x04C11DB7, X32+X26+X23+X22+X16+X12+X11+X

+X8+X7+X5+X4+X2+X+1

● Supports 1’s complement, byte reverse and bit reverse operation on data and checksum

/2) MHz for master mode and (f

PCLK

/8) MHz

PCLK

/3) MHz for slave mode

PCLK

/16) MHz and synchronous op-

PCLK

/16) MHz

PCLK

Introduction

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32-Bit Arm® Cortex®-M3 MCU HT32F12345

● Supports byte, half-word and word data size

● Programmable CRC initial seed value

● CRC computation done in 1 AHB clock cycle for 8-bit data and 4 AHB clock cycles for 32-bit

data

● Supports PDMA to complete a CRC computation of a block of memory

▄

Peripheral Direct Memory Access – PDMA

● 12 channels with trigger source grouping

● 8/16/32-bit width data transfer

● Supports Address increment, decrement or xed mode

● 4-level programmable channel priority

● Auto reload mode

● Supported trigger source: ADC, SPI, EBI, CRC, USART, UART, I2C, I2S, GPTM, MCTM,

SDIO and software request

▄

External Bus Interface – EBI

● Programmable interface for various memory types

● Translates the AHB transactions into the appropriate external device protocol

● 4 Memory bank regions and independent chip select control for each memory bank

● Accurate control of setup, strobe, hold and turn-around timing per memory bank

● Supports page mode read

● Automatic translation when AHB transaction width and external memory interface width is

different

● Write buffer to decrease the stalling of the AHB write burst transaction

● Both multiplexed and non-multiplexed address and data line congurations

– Up to 21 address lines

– Up to 16-bit data bus width

▄

Universal Serial Bus Device Controller – USB

● Complies with USB 2.0 full-speed (12 Mbps) specication

● On-chip USB full-speed transceiver

● 1 control endpoint (EP0) for control transfer

● 3 single-buffered endpoint (EP1 ~ EP3) for bulk and interrupt transfer

● 4 double-buffered endpoint (EP4 ~ EP7) for bulk, interrupt and isochronous transfer

● 1 KB EP_SRAM used as the endpoint data buffers

▄

Secure Digital Input Output Interface – SDIO

● Supports two different data bus modes: 1-bit (default) and 4-bit

● Supports two different speed modes: Normal speed (default) and High speed

● SD clock frequency of up to 48 MHz

● SPI mode and MMC stream mode not supported

▄

Debug support

● Serial Wire Debug Port SW-DP

● 6 instruction comparator and 2 literal comparator for hardware breakpoint/watchpoint or code

patch

● 1-bit asynchronous trace (TRACESWO)

▄

Package and Operation Temperature

● 46-pin QFN, 48/64-pin LQFP package

● Operation temperature range: -40 ºC to 85 ºC

Introduction

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32-Bit Arm® Cortex®-M3 MCU HT32F12345

Device Information

Table 1. Features and Peripheral List

Main Flash (KB) 63

Option Bytes Flash (KB) 1

SRAM (KB) 16

Timers

Communication

PDMA 12 channels

SDIO 1

EBI 1

CRC 1

GPIO Up to 51

EXTI 16

12-bit ADC Number of channels

Comparator 2

CPU frequency Up to 96 MHz

Operating voltage 2.0 V ~ 3.6 V

Operating temperature -40 °C ~ 85 °C

Package 46-pin QFN, 48/64-pin LQFP

Peripherals HT32F12345

MCTM 2

GPTM 2

BFTM 2

RTC 1

WDT 1

USB 1

USART 2

UART 2

SPI 2

I2C 2

I2S 1

Max. 12 Channels

Introduction

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32-Bit Arm® Cortex®-M3 MCU

TPIU SW-DP

APB1

APB0

AHB

Peripherals

ICode DCode

CortexTM-M3

Processor

System

NVIC

SRAM

Controller

FMC

Control

Registers

CKCU/

RSTCU

PDMA

Control

Registers

PDMA

12 Channels

DMA request

Interrupt request

USART0

UART0

AFIO

EXTI

SPI1

MOSI, MISO

SCK, SEL

PLL

Max

: 96 MHz

POR

/PDR

CH3 ~ CH0 ETI

BOOT0 BOOT1

Clock and reset control

BOD

LVD

XTALIN XTALOUT

CLDO

HSI

8 MHz

HSE

4 ~ 16 MHz

Power co ntrol

Bus Matrix

AFAF

AF AF

LDO

1.5 V

DD15

USB

Control/Data

Registers

SDA SCL

USART1

Power supply:

Bus:

Control signal:

Alternate function:

MOSI, MISO SCK, SEL

TX, RX RTS/TXE CTS/SCK

CH0 ~CH2 CH0N ~ CH2N CH3, ETI, BRK

X32KIN

X32KOUT

PORB

BAK

LSI

32 kHz

LSE

32.768kHz

BREG

BAK

Backup Domain

BAT

BAK

PWRSW

RTC

PWRCU

nRST

RTCOUT

WAKEUP

AF AF

GPTM0 ~ 1

DDA

SSA

CN0, CP0

COUT0

CN1, CP1

COUT1

ADC_IN0

...

ADC_IN11

AFAF

I2C0 ~ 1

ADC

12-Bit

SAR ADC

TRACESWO

BFTM0 ~ 1

AHB to APB

Bridge

External Bus

Interface

USB

Device

DP DM

WDT

AD0~AD15 A0~A24 CS0~CS3 OE, WR ALE, RDY BL0~BL1

GPIO

A~D

PA~PC[15:0] PD[2:0]

SPI0

TX, RX

UART1

TX, RX

I2S

MCLK, BCLK

WS, SDO, SDI

DD15

SDIO

SRAM

CLK, CMD DAT0 ~ 3

CAP.

SWCLK SWDIO

MCTM0 ~ 1

USB PLL

f: 48 MHz

CMPCU

Flash

Memory

Analog

CMP0 ~ 1

Flash Memory

Interface

CRC

HT32F12345

Block Diagram

Introduction

Figure 1. Block Diagram

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32-Bit Arm® Cortex®-M3 MCU HT32F12345

Document Conventions

Unless otherwise specied, this document uses the conventions which showed as follows.

Table 2. Document Conventions

Notation Example Description

0x 0x5a05

0xnnnn_nnnn 0x2000_0100 32-bit Hexadecimal address or data.

b b0101

NAME [n] ADDR [5]

NAME [m:n] ADDR [11:5]

X b10X1 Don’t care notation which means any value is allowed.

19 18

W0C

Reserved

Word Data length of word is 32-bit.

Half-word Data length of half-word is 16-bit.

Byte Data length of byte is 8-bit.

SERDYIE PLLRDYIE

RW 0 RW 0

3 2

HSIRDY HSERDY

RO 1 RO 0

1 0

PDF BAK_PORF

RC 0 RC 1

3 2

SERDYF PLLRDYF

WC 0 WC 0

1 0

RXCF PARF

RO 0 W0C 0

31 30

DB_CKSRC

WO 0 WO 0

1 0

LLRDY Reserved

RO 0

The number string with a 0x prefix indicates a hexadecimal number.

The number string with a lowercase b prex indicates a

binary number.

Specic bit of NAME. NAME can be a register or eld of

Specic bits of NAME. NAME can be a register or eld

of register. For example, ADDR [11:5] means bit 11 to 5

of ADDR register (eld).

Software can read and write to this bit.

Software can only read this bit. Write operation has no effort.

Software can read this bit. Read operation clears it to 0 automatically.

Software can read this bit or clear it by writing 1. Write a 0 will have no effect.

Software can read this bit or clear it by writing 0. Write a 1 will have no effect.

Software can only write to this bit. Read operation always returns 0.

Reserved bit(s) for future use. Software should not rely on the value of the reserved bit. In general case, reserved bits are set to 0. Note that reserved bit must be kept at reset value.

Document Conventions

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32-Bit Arm® Cortex®-M3 MCU HT32F12345

System Architecture

The system architecture of the device that includes the Arm® Cortex®-M3 processor, bus architecture and memory organization will be described in the following sections. The Cortex®-M3 is a next generation processor core which offers many new features. Integrated and advanced features make the Cortex®-M3 processor suitable for high performance and low power microcontroller market. In brief, Cortex®-M3 processor includes three AHB-Lite buses, ICode, DCode and System bus. All memory accesses of Cortex®-M3 are performed on those three buses according to the different purpose and target memory space. The memory organization with Harvard architecture, pre-

dened memory map and up to 4 GB memory space makes the system exible and extendable.

Arm® Cortex®-M3 Processor

Cortex®-M3 is a general purpose 32-bit processor core which very suitable for high performance and low power microcontroller market. It offers many new features including a Thumb-2 instruction sets, hardware divide, low latency interrupt response time, atomic bit-banding access and multiple buses for simultaneous accesses. Cortex®-M3 is based on ARMv7 architecture and supports both Thumb and Thumb-2 instruction sets. Some system peripherals are also provided by the Cortex®-M3 including:

▄

Internal Bus Matrix connected with ICode bus, DCode bus, System bus, Private Peripheral Bus (PPB) and debug accesses (AHB-AP)

▄

Nested Vectored Interrupt Controller (NVIC)

▄

Flash Patch and Breakpoint (FPB)

▄

Data Watchpoint and Trace (DWT)

▄

Instrument Trace Macrocell (ITM)

▄

Memory Protection Unit (MPU)

▄

Serial Wire JTAG Debug Port (SWJ-DP)

▄

Embedded Trace Macrocell (ETM)

▄

Trace Port Interface Unit (TPIU)

The following gure shows the Cortex®-M3 block diagram. For more information, please refer to

Arm® Cortex®-M3 Technical Reference Manual.

System Architecture

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32-Bit Arm® Cortex®-M3 MCU HT32F12345

INTNMI

INTISR[239:0]

SLEEPING

SLEEPDEEP

SW/

JTAG

SW/

SWJ-DP

Interrupts

NVIC

Private Peripheral Bus

(internal)

AHB-AP

Sleep

Debug

CM3Core

Inar. Data

MPU

FPB

Cortex-M3

DWT

Bus

Matrix

Trigger

ITM

APB

i/f

ETM

TPIU

System Architecture

Trace port

(serial wire

or multi-pin)

Private

Peripheral

Bus

(external)

ROM

Table

I-code bus

D-code bus

System bus

Figure 2. Cortex®-M3 Block Diagram

Bus Architecture

The HT32F12345 device consists of four master and six slaves in the bus architecture. Cortex®-M3 ICode, DCode, System bus and Peripheral Direct Memory Access (PDMA) are the masters,

internal SRAM, internal Flash memory, AHB peripherals, external bus interface and two AHB to APB bridges are the slaves. The ICode bus is used for instruction and vector fetches from Code region (0x0000_0000 ~ 0x1FFF_FFFF) to Cortex-M3 core. The DCode bus is used for data load/ stores and debugging accesses of Code region. Similarly, the System bus is used for instruction/ vector fetches, data load/stores and debugging accesses of system regions. The system regions

include internal SRAM region and peripheral region. All of these master buses are based on 32-bit

Advanced High-performance Bus-Lite (AHB-Lite) protocol. The following gure shows the bus

architecture of the HT32F12345 device.

Rev. 1.10 36 of 590 November 28, 2018

32-Bit Arm® Cortex®-M3 MCU HT32F12345

ICode DCode

Cortex®-M3

Processor

System

NVIC

Interrupt request

PDMA

12 Channels

DMA request

Figure 3. Bus Architecture

Bus Matrix

Flash Memory

Interface

PDMA

Control

Registers

FMC

Control

Registers

AHB

Peripherals

SRAM Controller

External Bus

Interafce

AHB to APB

Bridge

GPIO

A~D

CRC

-16/32

SDIO

Flash

Memory

Control Registers

SRAM

APB0 IPs

CKCU/RSTCU

USB

Control/Data

Registers

APB1 IPs

USB

Device

System Architecture

Memory Organization

Arm® Cortex®-M3 is structured in Harvard architecture which can use separate buses to fetch

instructions and load/store data. The instruction code and data bus share the same memory address

space but in different address ranges. The maximum addressing range of the Cortex®-M3 is 4 GB

since it has 32-bit bus address width. Additionally, a pre-dened memory map is provided by the

Cortex®-M3 to reduce the software complexity of repeated implementation of different device venders. However, some regions are used by Arm® Cortex®-M3 system peripherals. Refer to Arm® Cortex®-M3 Technical Reference Manual for more information. The following gure shows the

memory map of the device, including Code, SRAM, peripheral and other pre-dene regions.

Rev. 1.10 37 of 590 November 28, 2018

32-Bit Arm® Cortex®-M3 MCU HT32F12345

Memory Map

Peripheral

SRAM

Code

0xFFFF_FFFF

0xE010_0000

0xE000_0000

0x7000_0000

0x6000_0000

0x4400_0000

0x4200_0000

0x4010_0000

0x4008_0000

0x4000_0000

0x2220_0000

0x2200_0000

0x2000_4000

0x2000_0000

0x1FF0_0400

0x1FF0_0000

0x1F00_2000

0x1F00_0000

0x0001_0000

Reserved

Private peripheral bus

Reserved

EBI Selection Bank

Reserved

APB/AHB bit band alias

Reserved

AHB peripherals

APB peripherals

Reserved

SRAM bit band alias

Reserved

16 KB on-chip SRAM

Reserved

Option byte alias

Reserved

Boot loader

Reserved

64 KB on-chip Flash

64 MB x 4

32 MB

512 KB

2 MB

16 KB

1 KB

8 KB

64 KB

0x400F_FFFF

0x400B_8000

0x400B_0000

0x400A_C000

0x400A_8000

0x400A_2000

0x400A_0000

0x4009_A000

0x4009_8000

0x4009_2000

0x4008_C000

0x4008_A000

0x4008_8000

0x4008_2000

0x4008_0000

0x4007_8000

0x4007_7000

0x4007_6000

0x4007_0000

0x4006_F000

0x4006_E000

0x4006_B000

0x4006_A000

0x4006_9000

0x4006_8000

0x4005_8000

0x4004_2000

0x4002_E000

0x4002_D000 0x4002_C000

0x4002_7000

0x4002_6000

0x4002_5000

0x4002_4000

0x4002_3000

0x4002_2000

0x4001_1000

0x4001_0000

0x4000_5000

0x4000_4000

0x4000_2000

0x4000_1000 0x4000_0000

Reserved

GPIOA~D

Reserved

USB

Reserved

SDIO

Reserved

EBI

Reserved

PDMA0x4009_0000

Reserved

CRC-16/32

CKCU/RSTCU

Reserved

FMC

Reserved

BFTM1 BFTM0

Reserved

GPTM1 GPTM0

Reserved

RTC/PWRCU

Reserved

WDT

Reserved0x4005_9000

CMP

Reserved0x4004_A000

I2C10x4004_9000 I2C00x4004_8000

Reserved0x4004_5000

SPI10x4004_4000

Reserved

UART10x4004_1000

USART10x4004_0000

Reserved

MCTM1 MCTM0

Reserved

I2S

Reserved

EXTI

Reserved

AFIO

Reserved

ADC

Reserved

SPI0

Reserved

UART0

USART0

System Architecture

AHB

APB1

APB0

0x0000_0000

Figure 4. Memory Map

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Table 3. Register Map

Start Address End Address Peripheral Bus

0x4000_0000 0x4000_0FFF USART0

0x4000_1000 0x4000_1FFF UART0

0x4000_2000 0x4000_3FFF Reserved

0x4000_4000 0x4000_4FFF SPI0

0x4000_5000 0x4000_FFFF Reserved

0x4001_0000 0x4001_0FFF ADC

0x4001_1000 0x4002_1FFF Reserved

0x4002_2000 0x4002_2FFF AFIO

0x4002_3000 0x4002_3FFF Reserved

0x4002_4000 0x4002_4FFF EXTI

0x4002_5000 0x4002_5FFF Reserved

0x4002_6000 0x4002_6FFF I2S

0x4002_7000 0x4002_BFFF Reserved

0x4002_C000 0x4002_CFFF MCTM0

0x4002_D000 0x4002_DFFF MCTM1

0x4002_E000 0x4003_FFFF Reserved

0x4004_0000 0x4004_0FFF USART1

0x4004_1000 0x4004_1FFF UART1

0x4004_2000 0x4004_3FFF Reserved

0x4004_4000 0x4004_4FFF SPI1

0x4004_5000 0x4004_7FFF Reserved

0x4004_8000 0x4004_8FFF I2C0

0x4004_9000 0x4004_9FFF I2C1

0x4004_A000 0x4005_7FFF Reserved

0x4005_8000 0x4005_8FFF CMP

0x4005_9000 0x4006_7FFF Reserved

0x4006_8000 0x4006_8FFF WDT

0x4006_9000 0x4006_9FFF Reserved

0x4006_A000 0x4006_AFFF RTC/PWRCU

0x4006_B000 0x4006_DFFF Reserved

0x4006_E000 0x4006_EFFF GPTM0

0x4006_F000 0x4006_FFFF GPTM1

0x4007_0000 0x4007_5FFF Reserved

0x4007_6000 0x4007_6FFF BFTM0

0x4007_7000 0x4007_7FFF BFTM1

0x4007_8000 0x4007_FFFF Reserved

System Architecture

APB0

APB1

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Start Address End Address Peripheral Bus

0x4008_0000 0x4008_1FFF FMC

0x4008_2000 0x4008_7FFF Reserved

0x4008_8000 0x4008_9FFF CKCU/RSTCU

0x4008_A000 0x4008_BFFF CRC-16/32

0x4008_C000 0x4008_FFFF Reserved

0x4009_0000 0x4009_1FFF PDMA Control Registers

0x4009_2000 0x4009_7FFF Reserved

0x4009_8000 0x4009_9FFF EBI Control Registers

0x4009_A000 0x4009_FFFF Reserved

0x400A_0000 0x400A_1FFF SDIO

0x400A_2000 0x400A_7FFF Reserved

0x400A_8000 0x400A_9FFF USB Control Registers

0x400A_A000 0x400A_BFFF USB SRAM

0x400A_C000 0x400A_FFFF Reserved

0x400B_0000 0x400B_1FFF GPIOA

0x400B_2000 0x400B_3FFF GPIOB

0x400B_4000 0x400B_5FFF GPIOC

0x400B_6000 0x400B_7FFF GPIOD

0x400B_8000 0x400F_FFFF Reserved

System Architecture

AHB

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Embedded Flash Memory

The HT32F12345 device provides 64 KB on-chip Flash memory which is located at address 0x0000_0000. It supports bytes, halt-words and word access. Note that Flash memory only

supports read operation for Cortex®-M3 ICode or DCode bus access. Any write operation to the Flash memory (via DCode bus) will cause a bus fault exception. The Flash memory has a capacity of 64 pages. Each page has a memory capacity of 1 KB and can be erased independently. A 32- bit

programming interface provides the capability of changing bits from 1 to 0. A data storage or

rmware upgrade can be implemented using several methods such as In System Programming (ISP),

In Application Programming (IAP) or In Circuit Programming (ICP). The above programming methods provide f lexibility to user for data storage and firmware upgrade purpose. For more information, refer to the Flash Memory Controller section.

Embedded SRAM Memory

The HT32F12345 device contains up to 16 KB on-chip SRAM which is located at address 0x2000_0000. It supports bytes, half-words and full words access operations. In order to reduce

the time of read-modify-write operations, the Cortex®-M3 provides a bit-banding function to perform a single atomic bit operation. Users can modify a single bit in SRAM bit-band region by accessing the corresponding bit-band alias. For more information about bit-binding, refer to the Arm® Cortex®-M3 Technical Reference Manual. The following formulas and examples show how to access a bit in the bit-band region by calculate the bit-band alias.

System Architecture

Bit-band alias = Bit-band base + (byte offset × 32) + (bit number × 4)

For example, if you want to access bit 7 of address 0x2000_0200, the bit-band alias is:

Bit-band alias = 0x2200_0000 + (0x200 × 32) + (7 × 4) = 0x2200_401C

Write to address 0x2200_401C causes the bit 7 of address 0x2000_0200 changed. On the contrary, read address 0x2200_401C returns 0x01 or 0x00 according to the value of bit 7 at SRAM address 0x2000_0200.

AHB Peripherals

The address of the AHB peripherals ranges from 0x4008_0000 to 0x400F_FFFF. Some peripherals

such as Clock Control Unit, Reset Control Unit and Flash Memory Controller are connected to the

AHB bus directly. The AHB peripheral clocks are always enabled after system reset. Access to registers for these peripherals can be achieved directly via the AHB bus. Note that all peripheral registers in AHB bus support only word access.

APB Peripherals

The address of APB peripherals ranges from 0x4000_0000 to 0x4007_FFFF. An APB to AHB

bridge provides access capability between the Cortex®-M3 and the APB peripherals. Additionally,

the APB peripheral clocks are disabled after a system reset. Software must enable peripheral clock by setting up the APBCCRn registers in Clock Control Unit before accessing the corresponding peripheral register. Note that the APB to AHB bridge will duplicate the half-word or byte data to word width when a half-word or byte access is performed on APB peripheral register. In other words, the access result of half-word or byte access on APB peripheral register will vary depending

on the data bit width of the access operation on the peripheral registers.

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Flash Memory Controller (FMC)

Introduction

The Flash Memory Controller, FMC, provides all the necessary functions, pre-fetch buffer and branch cache for the embedded on-chip Flash memory. The figure below shows the block diagram of FMC which includes programming interface, control register, pre-fetch buffer and access interface. Since the access speed of Flash memory is slower than the CPU, a wide access interface with a pre-fetch buffer is provided to the Flash memory in order to reduce the CPU waiting timing which will cause CPU instruction execution delay. The Flash memory word program / page erase functions are also provided for instruction / data storage.

System Bus

I/D Code Bus

Flash Memory Controller

Control Register

Pre-fetch Buffer

Branch Cache

Wait State

Control

Addressing

Data

Programming

Control

Flash Memory Controller (FMC)

Flash

Information

Block

Main Flash

Memory

Figure 5. Flash Memory Controller Block Diagram

Features

▄

64 KB of on-chip Flash memory for storing instruction / data and options

● 64 KB: 63 KB + 1 KB (instruction/data + Option Byte)

▄

Page size of 1 KB, totally 64 pages

▄

Wide access interface with pre-fetch buffer and branch cache to reduce instruction gaps

▄

Page erase and mass erase capability

▄

32-bit word programming

▄

Interrupt function to indicate end of Flash memory operations or an error occurs

▄

Flash read protection to prevent illegal code / data access

▄

Page erase / program protection to prevent unexpected operation

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Functional Descriptions

Flash Memory Map

The following figure is the Flash memory map of the system. The address ranges from

0x0000_0000 to 0x1FFF_FFFF (0.5 GB). The address from 0x1F00_0000 to 0x1F00_0FFF is mapped to Boot Loader with a capacity of 4 KB. Additionally, the region addressed from 0x1FF0_0000 to 0x1FF0_03FF is the alias of Option Byte block with a capacity of 1 KB. The

memory mapping on system view is shown as below.

0x1FFF_FFFF

0x1FF0_0400

Flash Memory Controller (FMC)

Reserved

0x1FF0_0000

0x1F00_1000

0x1F00_0000

0x0000_0000

Figure 6. Flash Memory Map

Option Byte

Reserved

Boot Loader Block

Reserved

Main Flash Block

User Application

1 Kbytes

4 Kbytes

63 Kbytes

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Flash Memory Architecture

The Flash memory consists of 63 KB main Flash with 1 KB per page and an 4 KB Information Block for the Boot Loader. The main Flash memory contains a total of 64 pages which can be

erased individually. The following table shows the base address, size and protection setting bit of each page.

Table 4. Flash Memory and Option Byte

Block Name Address Page Protection Bit Size

Page 0 0x0000_0000 ~ 0x0000_03FF OB_PP [0] 1 KB

Page 1 0x0000_0400 ~ 0x0000_07FF OB_PP [1] 1 KB

Page 2 0x0000_0800 ~ 0x0000_0BFF OB_PP [2] 1 KB

Page 3 0x0000_0C00 ~ 0x0000_0FFF OB_PP [3] 1 KB

. . .

Main Flash Block

. . . .

Page 60 0x0000_F000 ~ 0x0000_F3FF OB_PP [60] 1 KB

Page 61 0x0000_F400 ~ 0x0000_F7FF OB_PP [61] 1 KB

Page 62 0x0000_F800 ~ 0x0000_FBFF OB_PP [62] 1 KB

Page 63 (Option Byte)

Information Block

Notes:

1. Information Block stores boot loader, this block cannot be programmed or erased by user.

Boot Loader 0x1F00_0000 ~ 0x1F00_0FFF NA 4 KB

Physical: 0x0000_FC00 ~ 0x0000_FFFF Alias: 0x1FF0_0000 ~ 0x1FF0_03FF

2. Option Byte is always located at last page of main Flash block.

. . . . . . .

OB_CP [1] 1 KB

Flash Memory Controller (FMC)

. . . . . . .

Wait State Setting

When the CPU clock, HCLK, is greater than the access speed of the Flash memory, the wait state cycles must be inserted during the CPU fetch instructions or load data from Flash memory. The wait state can be changed by setting the WAIT [2:0] bits of the Flash Cache and Pre-fetch Control Register, CFCR. In order to match the wait state requirement, the following two rules shall be considered.

▄

HCLK clock is changed from lower to higher: Change the wait state setting rst and then switch the HCLK clock.

▄

HCLK clock is changed from higher to lower: Switch the HCLK clock rst and then change the wait state setting.

The following table shows the relationship between the wait state cycle and HCLK. The default wait state is 0 since the High Speed Internal oscillator HSI which operates at a frequency of 8 MHz is selected as the HCLK clock source after reset.

Table 5. Relationship between Wait State Cycle and HCLK

Wait State Cycle HCLK

0 0 MHz < HCLK ≤ 24 MHz

1 24 MHz < HCLK ≤ 48 MHz

2 48 MHz < HCLK ≤ 72 MHz

3 72 MHz < HCLK ≤ 96 MHz

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Booting Conguration

The system provides three kinds of booting mode which can be selected through BOOT0 and BOOT1 pins. The BOOT0 and BOOT1 pins are sampled during a power-on reset or a system reset. Once the logic value on these pins has been determined, the rst 4 words of vector will be

remapped to the corresponding source according to the booting mode. The booting modes are shown in the following table.

Hard Fault Handler

0xC

NMI Handler

0x8

Program Counter

0x4

Initial Stack Point0x0

Table 6. Booting Modes

Booting mode selection pins

BOOT1 BOOT0

0 0 SRAM The source of Vector is SBVT0 ~ SBVT3

0 1 Boot Loader The source of Vector is Boot Loader

1 X Main Flash The source of Vector is main Flash

Mode Descriptions

The Vector Mapping Control Register (VMCR) is provided to change the setting of the vector remapping setting temporarily after a device reset. The initial reset value of the VMCR register is determined by the BOOT0 and BOOT1 pins which will be sampled during the reset duration.

Boot1 and Boot0 Setting

1x: Main Flash 01: Boot Loader 00: SRAM

+ 0xC

+ 0x8

+ 0x4

0x0000 0000

+ 0xC

+ 0x8

+ 0x4

0x1F00 0000

+ 0xC

+ 0x8

+ 0x4

SBVT3

SBVT2

SBVT1

SBVT00x4008 0300

Flash Memory Controller (FMC)

Figure 7. Vector Remapping

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Page Erase

The FMC provides a page erase function which is used to initialize the contents of a Flash memory. Any page can be erased independently without affecting others. The following steps show the access sequence of the register for a page erase operation.

▄

Check the OPCR register to conrm that no Flash memory operation is in progress (OPM [3:0] equal to 0xE or 0x6). Otherwise, wait until the previous operation has been nished.

▄

Write the page address to TADR register

▄

Write the page erase command to OCMR register (CMD [3:0] = 0x8).

▄

Send the page erase command to FMC by setting OPCR register (set OPM [3:0] = 0xA).

▄

Wait until all the operations have been completed by checking the value of OPCR register (OPM [3:0] equal to 0xE).

▄

Read and verify the page if required using DCODE access.

Note that a correct target page address must be conrmed. The software may run out of control if the target erase page is being used for fetching code or access data. The FMC will not provide

any notication when this occurs. Additionally, the page erase operation will be ignored on the protected pages. A Flash Operation Error interrupt will be triggered by the FMC if the OREIEN bit in the OIER register is set. Software can check the PPEF bit in the OISR register to detect this condition in the interrupt handler. The following gure shows the page erase operation ow.

Flash Memory Controller (FMC)

Start

Is OPM equal to 0xE or 0x6 ?

Yes

Set TADR, OCMR

Commit command

by setting OPCR

Is OPM equal to 0xE ?

Yes

Finish

Figure 8. Page Erase Operation Flowchart

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Mass Erase

The FMC provides a mass erase function which is used to initialize the complete Flash memory contents to a high state. The following steps show the mass erase operation sequence.

▄

Check the OPCR register to conrm that no Flash memory operation is in progress (OPM [3:0] equal to 0xE or 0x6). Otherwise, wait until the previous operation has been nished.

▄

Write the mass erase command to the OCMR register (CMD [3:0] = 0xA).

▄

Send the mass erase command to the FMC by setting the OPCR register (set OPM [3:0] = 0xA).

▄

Wait until all operations have been completed by checking the value of the OPCR register (OPM [3:0] equal to 0xE).

▄

Read and verify the Flash memory if required using DCODE access.

Since all Flash data will be reset as 0xFFFF_FFFF, the mass erase operation can be implemented

by an application that runs in the SRAM or by the debug tool that access the FMC register directly. An application that executes on the Flash memory will not trigger a mass erase operation. The following gure shows the mass erase operation ow.

Flash Memory Controller (FMC)

Start

Is OPM equal to 0xE or 0x6 ?

Yes

Set OCMR = 0xA

Commit command

by setting OPCR

Is OPM equal to 0xE ?

Yes

Finish

Figure 9. Mass Erase Operation Flowchart

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Word Programming

The FMC provides a 32-bit word programming function which is used to modify the Flash memory contents. The following steps show the word programming register access sequence.

▄

Check the OPCR register to conrm that no Flash memory operation is in progress (OPM [3:0] equal to 0xE or 0x6). Otherwise, wait until the previous operation has been nished.

▄

Write the word address to the TADR register. Write data to WRDR register.

▄

Write the word program command to the OCMR register (CMD [3:0] = 0x4).

▄

Send the word program command to the FMC by setting the OPCR register (set OPM [3:0] = 0xA).

▄

Wait until all operations have been completed by checking the value of the OPCR register (OPM [3:0] equal to 0xE).

▄

Read and verify the Flash memory if required using DCODE access.

Note that the word programming operation cannot be applied to the same address twice. Successive word programming operation to the same address must be separated by a page erase operation. Additional ly, the word programming operation will be ignored on protected pages. A Flash

Operation Error interrupt will be triggered by the FMC if the OREIEN bit in the OIER register is set. Software can check the PPEF bit in the OISR register to detect this condition in the interrupt handler. The following gure shows the word programming operation ow.

Flash Memory Controller (FMC)

Start

Is OPM equal to 0xE or 0x6 ?

Yes

Set TADR, WRDR

and OCMR

Commit command

by setting OPCR

Is OPM equal to 0xE ?

Yes

Finish

Figure 10. Word Programming Operation Flowchart

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Option Byte Description

The Option Byte can be treated as an independent Flash memory which base address is 0x1FF0_0000. The following table shows the function description and memory map of Option Byte.

Table 7. Option Byte Memory Map

Option Byte Offset Description Reset Value

Option Byte Base Address = 0x1FF0_0000

0x000

OB_PP

OB_CP 0x010

OB_CK 0x020

0x004 0x008

0x00C

OB_PP [n]: Main Flash Page Erase / program Protection (n = 0 ~ 62 for page 0 ~ page 62)

0: Flash Page n Erase / Program Protection is

enabled

1: Flash Page n Erase / Program Protection is

disabled

(n = 63 ~ 127: Reserved)

OB_CP [0]: Flash Security Protection

0: Flash Security protection is enabled 1: Flash Security protection is disabled

OB_CP [1]: Option Byte Protection

0: Option Byte protection is enabled 1: Option Byte protection is disabled

OB_CP [31:2]: Reserved

OB_CK [31:0]: Flash Option Byte Checksum OB_CK should be set as the sum of 5 words Option Byte content, of which the offset address ranges form 0x000 to 0x010 (0x000 + 0x004 + 0x008 + 0x00C + 0x010), when the OB_PP or OB_CP register content is not equal to 0xFFFF_FFFF. Otherwise, both page erase / program protection and security protection will be enabled.

Flash Memory Controller (FMC)

0xFFFF_FFFF 0xFFFF_FFFF 0xFFFF_FFFF 0xFFFF_FFFF

0xFFFF_FFFF

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Page Erase / Program Protection

The FMC provides page erase / program protection functions to prevent inadvertent operations on the Flash memory. The page erase or word programming command will not be accepted by the FMC on the protected pages. When the page erase or word programming command is sent to the FMC on a protected page, the PPEF bit in the OISR register will then be set by FMC. If the OREIEN bit in the OIER register is also set to 1 then the Flash operation error interrupt will be triggered by the FMC. The page protection function can be individually enabled for each page by conguring the OB_PP [127:0] bit eld in the Option Byte. The following table shows the access permission of the main Flash page when the page protection is enabled.

Table 8. Access Permission of Protected Main Flash Page

Mode

Operation

DCODE Read O O O

Program X X X

Page Erase X X X

Mass Erase O O O

Flash Memory Controller (FMC)

ISP/IAP ICP/Debug Mode Boot from SRAM

Notes:

1. The write protection is based on specic pages. The above access permission only affects the pages of which the protection function has been enabled. Other pages are not affected.

2. Main Flash page protection is configured by OB_PP [126:0]. Option Byte is physically

located at the last page of main Flash. Option Byte page protection is congured by the

OB_CP [1] bit.

3. The page erase on Option Byte area can disable the page protection of main Flash.

4. The page protection of Option Byte can only be disabled by a mass erase operation.

The following steps show the page erase / program protection procedure register access sequence.

▄

Check the OPCR register to conrm that no Flash memory operation is in progress (OPM [3:0] equal to 0xE or 0x6). Otherwise, wait until the previous operation has been nished.

▄

Write the OB_PP address to the TADR register (TADR = 0x1FF0_0000).

▄

Write the data which indicates the protection function of corresponding page is enabled or disabled into the WRDR register (0: Enabled, 1: Disabled).

▄

Write the word program command to the OCMR register (CMD [3:0] = 0x4).

▄

Commit the word program command to the FMC by setting the OPCR register (set OPM [3:0] = 0xA).

▄

Wait until all operations have been nished by checking the value of the OPCR register (OPM [3:0] equal to 0xE).

▄

Read and verify the Option Byte if required using DCODE access.

▄

Before to activate the new OB_PP setting, the OB_CK must be updated according to the Option Byte checksum rule.

▄

Apply a system reset to activate the new setting.

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Security Protection

The FMC provides a security protection function to prevent illegal code / data access of the Flash memory. This function is useful for protecting the software / rmware from the illegal users. The function is activated by conguring the OB_CP [0] bit in the Option Byte. Once the function has been enabled, all the main Flash DCODE access, programming and page erase operations will

not be allowed except for the user’s application. However, the mass erase operation will still be accepted by the FMC in order to disable this security protection function. The following table shows the access permission of Flash memory when the security protection is enabled.

Table 9. Access Permission When Security Protection is Enabled

Mode

Operation

DCODE Read O X (read as 0) X (read as 0)

Program O

Page Erase O

Mass Erase O O O

Notes:

1. User application means the software that is executed or booted from the main Flash memory with the JTAG/SW debugger being disconnected. However, the Option Byte block and page 0 are still protected in which Programming and Page Erase operations cannot be executed.

2. Mass erase operation can erase Option Byte block and disable security protection.

The following steps show the Security protection procedure register access sequence.

User Application

(1)

ICP / Debug Mode Boot from SRAM

X X

Flash Memory Controller (FMC)

▄

Check the OPCR register to conrm that no Flash memory operation is in progress (OPM [3:0] equal to 0xE or 0x6). Otherwise, wait until the pervious operation has been nished.

▄

Write the OB_CP address to the TADR register (TADR = 0x1FF0_0010).

▄

Write the data into the WRDR register to clear OB_CP [0] bit to 0.

▄

Write the word program command to the OCMR register (CMD [3:0] = 0x4).

▄

Send the word program command to the FMC by setting the OPCR register (set OPM = 0xA).

▄

Wait until all operations have been nished by checking the value of the OPCR register (OPM [3:0] equals to 0xE).

▄

Read and verify the Option Byte if required using DCODE access.

▄

Before to activate the security protection function, the OB_CK eld must be update according to the Option Byte checksum rule.

▄

Apply a system reset to activate the new setting.

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Register Map

The following table shows the FMC registers and reset values.

Table 10. FMC Register Map

FMC Base Address = 0x4008_0000

TADR 0x000 Flash Target Address Register 0x0000_0000

WRDR 0x004 Flash Write Data Register 0x0000_0000

OCMR 0x00C Flash Operation Command Register 0x0000_0000

OPCR 0x010 Flash Operation Control Register 0x0000_000C

OIER 0x014 Flash Operation Interrupt Enable Register 0x0000_0000

OISR 0x018 Flash Operation Interrupt and Status Register 0x0001_0000

0x020

PPSR

CPSR 0x030 Flash Security Protection Status Register 0x0000_000X

VMCR 0x100 Flash Vector Mapping Control Register 0x0000_000X

MDID 0x180 Flash Manufacturer and Device ID Register 0x0376_XXXX

PNSR 0x184 Flash Page Number Status Register 0x0000_00XX

PSSR 0x188 Flash Page Size Status Register 0x0000_0400

DIDR 0x18C Device ID Register 0x000X_XXXX

CFCR 0x200 Flash Cache and Pre-fetch Control Register 0x0000_1091

SBVT0 0x300 SRAM Booting Vector 0 (Stack Point) 0x2000_4000

SBVT1 0x304 SRAM Booting Vector 1 (Program Counter) 0x2000_0155

SBVT2 0x308 SRAM Booting Vector 2 (NMI Handler) 0x0000_0000

SBVT3 0x30C SRAM Booting Vector 3 (Hard Fault Handler) 0x0000_0000

CIDR0 0x310 Custom ID Register 0 0xXXXX_XXXX

CIDR1 0x314 Custom ID Register 1 0xXXXX_XXXX

CIDR2 0x318 Custom ID Register 2 0xXXXX_XXXX

CIDR3 0x31C Custom ID Register 3 0xXXXX_XXXX

0x024 0x028 0x02C

Flash Page Erase / program Protection Status Register

Flash Memory Controller (FMC)

0xXXXX_XXXX 0xXXXX_XXXX 0xXXXX_XXXX 0xXXXX_XXXX

Note:

“X” means various reset values which depend on the Device, Flash value, option byte value, or

power on reset setting.

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Register Descriptions

Flash Target Address Register – TADR

This register species the target address of the page erase and word programming operations.

Offset: 0x000

Reset value: 0x0000_0000

31 30 29 28 27 26 25 24

TADB

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

23 22 21 20 19 18 17 16

TADB

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

15 14 13 12 11 10 9 8

TADB

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

7 6 5 4 3 2 1 0

TADB

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

Bits Field Descriptions

[31:0] TADB Flash Target Address Bits

For programming operations, the TADR register species the address where the

data is written. Since the programming length is 32-bit, the TADR should be set as word-aligned (4 bytes). The TADB [1:0] will be ignored during programming operations. For page erase operations, the TADR register contains the page address which is going to be erased. Since the page size is 1 KB, the TADB [9:0] will be ignored in order to limit the target address as 1 KB-aligned. For 64 KB main Flash addressing, TADB [31:16] should be zero. The Option Byte which has

a 1 KB capacity ranges from 0x1FF0_0000 to 0x1FF0_03FF. This eld is used to

specify the Flash address which must be within the range from 0x0000_0000 to 0x1FFF_FFFF. Otherwise, an Invalid Target Address interrupt will be generated if the corresponding interrupt enable bit is set.

Flash Memory Controller (FMC)

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Flash Write Data Register – WRDR

This register stores the data to be written into the TADR register for programming operation.

Offset: 0x004

Reset value: 0x0000_0000

31 30 29 28 27 26 25 24

WRDB

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

23 22 21 20 19 18 17 16

WRDB

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

15 14 13 12 11 10 9 8

WRDB

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

7 6 5 4 3 2 1 0

WRDB

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

Flash Memory Controller (FMC)

Bits Field Descriptions

[31:0] WRDB Flash Write Data Bits

The data value for programming operation.

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Flash Operation Command Register – OCMR

This register is used to specify the Flash operation commands that include word program, page erase and mass erase.

Offset: 0x00C

Reset value: 0x0000_0000

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved CMD

Type/Reset RW 0 RW 0 RW 0 RW 0

Bits Field Descriptions

[3:0] CMD Flash Operation Command

The following table shows the denitions of the operation command bits CMD [3:0]

which determine the Flash memory operation. If an invalid command is set and the IOCMIEN is equal to 1, an Invalid Operation Command interrupt will be generated.

CMD [3:0] Description

0x0 Idle – default

0x4 Word program

0x8 Page erase

0xA Mass erase

Others Reserved

Flash Memory Controller (FMC)

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Flash Operation Control Register – OPCR

This register is used for controlling the command commitment and checking the status of the FMC operations.

Offset: 0x010

Reset value: 0x0000_000C

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved OPM Reserved

Type/Reset RW 0 RW 1 RW 1 RW 0

Flash Memory Controller (FMC)

Bits Field Descriptions

[4:1] OPM Operation Mode

The following table shows the operation modes of the FMC. User can commit the command which is set by the OCMR register for the FMC according to the address alias setting in the TADR register. The contents of the TADR, WRDR and OCMR registers should be prepared before setting this register. After all the operations have been finished, the OPM field will be set as 0xE by the FMC hardware.

The Idle mode can be set when all the operations have been nished for power

saving purpose. Note that the operation status should be checked before the next operation is executed on the FMC. The content of the TADR, WRDR, OCMR and OPCR registers should not be changed until the previous operation has been

nished.

OPM [3:0] Description

0x6 Idle - default

0xA Commit command to main Flash

0xE All operation nished on main Flash

Others Reserved

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Flash Operation Interrupt Enable Register – OIER

This register is used to enable or disable the FMC interrupt function. The FMC generates interrupt to the controller when corresponding interrupt enable bits are set.

Offset: 0x014

Reset value: 0x0000_0000

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved OREIEN IOCMIEN OBEIEN ITADIEN ORFIEN

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0

Bits Field Descriptions

[4] OREIEN Operation Error Interrupt Enable

0: Operation error does not generate an interrupt 1: Operation error generates an interrupt

[3] IOCMIEN Invalid Operation Command Interrupt Enable

0: Invalid Operation Command does not generate an interrupt 1: Invalid Operation Command generates an interrupt

[2] OBEIEN Option Byte Check Sum Error Interrupt Enable

0: Option Byte Check Sum Error does not generate an interrupt 1: Option Byte Check Sum Error generates an interrupt

[1] ITADIEN Invalid Target Address Interrupt Enable

0: Invalid Target Address does not generate an interrupt 1: Invalid Target Address generates an interrupt

[0] ORFIEN Operation Finished Interrupt Enable

0: Operation Finish does not generate an interrupt 1: Operation Finish generates an interrupt

Flash Memory Controller (FMC)

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Flash Operation Interrupt and Status Register – OISR

This register indicates the status which is used to check if an operation has been nished or an error occurs. The

status bits, bit [4:0], are available when the corresponding bits in the OIER register are set.

Offset: 0x018

Reset value: 0x0001_0000

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved PPEF RORFF

Type/Reset RO 0 RO 1

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved OREF IOCMF OBEF ITADF ORFF

Type/Reset WC 0 WC 0 WC 0 WC 0 WC 0

Bits Field Descriptions

[17] PPEF Page Erase / Program Protected Error Flag

0: Page Erase / Program Protected Error does not occur 1: Operation error occurs due to an invalid page erase / program operation

being applied to a protected page

This bit is reset by hardware once a new Flash operation command is committed.

[16] RORFF Raw Operation Finished Flag

0: The last ash operation command is has not yet nished 1: The last ash operation command has nished

This bit is directly connected to the Flash memory for debugging purpose.

[4] OREF Operation Error Flag

0: No ash operation error occurred 1: The last ash operation is failed

This bit will be set when any Flash operation error such as an invalid command, program error and erase error, etc. occurs. The ORE interrupt occurs if the OREIEN bit in the OIER register is set. Reset this bit by writing 1.

[3] IOCMF Invalid Operation Command Flag

0: No invalid ash operation command was set 1: An invalid ash operation command is set into the OCMR register

The IOCM interrupt will be occurred if the IOCMIEN bit in the OIER register is set. Reset this bit by writing 1.

[2] OBEF Option Byte Check Sum Error Flag

0: Check sum of Option Byte is correct

1: Check sum of Option Byte is incorrect The OBE interrupt will occur if the OBEIEN bit in the OIER register is set. However, the Option Byte Check Sum Error Flag has to wait until the interrupt condition is cleared, this bit will be reset by software writes 1, which means the Option Byte

check sum value has been modied to correct one. Otherwise, the interrupt will

be continually kept or the software disables the interrupt enable bit to release the interrupt request.

Flash Memory Controller (FMC)

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Bits Field Descriptions

[1] ITADF Invalid Target Address Flag

0: The target address is valid

1: The target address TADR is invalid The data in the TADR field must be within the range from 0x0000_0000 to 0x1FFF_FFFF. The ITAD interrupt will be occurred if the ITADIEN bit in the OIER register is set. Reset this bit by writing 1.

[0] ORFF Operation Finished Flag

0: No operation nished interrupt occurred

1: Last ash operation command is nished

The ORF interrupt will be occurred if the ORFIEN bit in the OIER register is set. Reset this bit by writing 1.

Flash Page Erase / program Protection Status Register – PPSR

This register indicates the page erase / program protection status of the Flash memory.

Offset: 0x020 (0) ~ 0x02C (3)

Reset value: 0xXXXX_XXXX

Flash Memory Controller (FMC)

31 30 29 28 27 26 25 24

PPSBn

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

23 22 21 20 19 18 17 16

PPSBn

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

15 14 13 12 11 10 9 8

PPSBn

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

7 6 5 4 3 2 1 0

PPSBn

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

Bits Field Descriptions

[127:0] PPSBn Page Erase / program Protection Status Bits (n = 0 ~ 127)

PPSB[n] = OB_PP[n]

0: The corresponding pages are protected

1: The corresponding pages are not protected The content of this register is not dynamically updated and will only be reloaded

from the Option Byte when any kind of reset occurs. The erase or program function of the specific pages is not allowed when the corresponding bits of the PPSR registers are reset. The reset value of PPSR [127:0] is determined by the Option Byte OB_PP [127:0] bits. The other remained bits of OB_PP and PPSR registers are reserved.

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Flash Security Protection Status Register – CPSR

This register indicates the Flash memory security protection status. The content of this register is not dynamically updated and will only be reloaded by the Option Byte loader which is active when any kind of reset occurs.

Offset: 0x030

Reset value: 0x0000_000X

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved OBPSB CPSB

Type/Reset RO X RO X

Bits Field Descriptions

[1] OBPSB Option Byte Page Erase / program Protection Status Bit

0: The Option Byte page is protected

1: The Option Byte page is not protected The reset value of OPBSB is determined by the Option Byte OB_CP [1] bit.

[0] CPSB Flash Memory Security Protection Status Bit

0: Flash Security protection is enabled

1: Flash Security protection is not enabled The reset value of CPSB is determined by the Option Byte OB_CP [0] bit.

Flash Memory Controller (FMC)

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Flash Vector Mapping Control Register – VMCR

This register is used to control the vector mapping. The reset value of the VMCR register is determined by the external booting pins, BOOT0 and BOOT1, during the power-on reset period.

Offset: 0x100

Reset value: 0x0000_000X

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved VMCB

Type/Reset RW X RW X

Bits Field Descriptions

[1:0] VMCB Vector Mapping Control Bit

The VMCB bits are used to control the mapping source of first 4-word vector addressed from 0x0 to 0xC. The following table shows the vector mapping setting.

BOOT1 BOOT0 VMCB [1:0] Descriptions

Low Low 00

Low High 01

SRAM booting mode The vector mapping source is SBVT0 ~ 3.

Boot Loader mode The vector mapping source is the boot loader area.

Flash Memory Controller (FMC)

High Low 10

High High 11

The reset value of the VMCB register is determined by the pins status of the external booting pins BOOT1 and BOOT0 during power on reset and system reset.

The vector mapping setting can be changed temporarily by conguring the VMCB

bits when the application is running.

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Main Flash mode The vector mapping source is the main Flash area.

32-Bit Arm® Cortex®-M3 MCU HT32F12345

Flash Manufacturer and Device ID Register – MDID

This register is used to store the manufacture ID and device part number information which can be used as the product identity.

Offset: 0x180

Reset value: 0x0376_XXXX

31 30 29 28 27 26 25 24

MFID

Type/Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1

23 22 21 20 19 18 17 16

MFID

Type/Reset RO 0 RO 1 RO 1 RO 1 RO 0 RO 1 RO 1 RO 0

15 14 13 12 11 10 9 8

ChipID

Type/Reset RO 0 RO 0 RO 0 RO 1 RO X RO X RO X RO X

7 6 5 4 3 2 1 0

ChipID

Type/Reset RO 0 RO 1 RO 0 RO 1 RO 0 RO 0 RO 1 RO 0

Bits Field Descriptions

[31:16] MFID Manufacturer ID

Read as 0x0376.

[15:0] ChipID Chip ID

Read the last 4 digital code of the MCU device part number.

Flash Memory Controller (FMC)

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Flash Page Number Status Register – PNSR

This register is used to indicate the Flash memory page number.

Offset: 0x184

Reset value: 0x0000_00XX

31 30 29 28 27 26 25 24

PNSB

Type/Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0

23 22 21 20 19 18 17 16

PNSB

Type/Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0

15 14 13 12 11 10 9 8

PNSB

Type/Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0

7 6 5 4 3 2 1 0

PNSB

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

Flash Memory Controller (FMC)

Bits Field Descriptions

[31:0] PNSB Flash Page Number Status Bits

0x0000_0020: Totally 32 pages for the on-chip Flash memory device

0x0000_0040: Totally 64 pages for the on-chip Flash memory device

0x0000_0080: Totally 128 pages for the on-chip Flash memory device

0x0000_00FF: Totally 255 pages for the on-chip Flash memory device They indicated the total pages of the on-chip Flash memory device.

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Flash Page Size Status Register – PSSR

This register is used to indicate the page size in bytes.

Offset: 0x188

Reset value: 0x0000_0400

31 30 29 28 27 26 25 24

PSSB

Type/Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0

23 22 21 20 19 18 17 16

PSSB

Type/Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0

15 14 13 12 11 10 9 8

PSSB

Type/Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 0

7 6 5 4 3 2 1 0

PSSB

Type/Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0

Flash Memory Controller (FMC)

Bits Field Descriptions

[31:0] PSSB Flash Page Size Status Bits

0x200: That means the page size is 512 Byte per page

0x400: That means the page size is 1 KB per page

0x800: That means the page size is 2 KB per page

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Device ID Register – DID

This register is used to store the device part number information which can be used as the product identity.

Offset: 0x18C

Reset value: 0x000X_XXXX

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved ChipID

Type/Reset RO X RO X RO X RO X

15 14 13 12 11 10 9 8

ChipID

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

7 6 5 4 3 2 1 0

ChipID

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

Flash Memory Controller (FMC)

Bits Field Descriptions

[19:0] ChipID Chip ID

Read the complete 5 digital code of the MCU device part number.

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Flash Pre-fetch Control Register – CFCR

This register is used for controlling the FMC cache and pre-fetch module.

Offset: 0x200

Reset value: 0x0000_1091

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

Reserved CE Reserved

Type/Reset RW 1

7 6 5 4 3 2 1 0

DCDB Reserved PFBE Reserved WAIT

Type/Reset RW 1 RW 1 RW 0 RW 0 RW 1

Flash Memory Controller (FMC)

Bits Field Descriptions

[12] CE Branch Cache Enable Bit

0: Cache is disabled 1: Cache is enabled

[7] DCDB DCODE Data Cacheable Control Bit

0: DCODE Data Access is Cacheable 1: DCODE Data Access is Non-Cacheable

[4] PFBE Pre-fetch Buffer Enable Bit

0: Pre-fetch buffer is disabled 1: Pre-fetch buffer is enabled

The pre-fetch buffer is enabled in default state. When the pre-fetch buffer is disabled, the instruction and Data are provided by the Flash memory directly.

[2:0] WAIT Flash Wait State Setting

The WAIT [2:0] are used to set the HCLK wait clock during non-sequential address Flash access. The actual value of the wait clocks is given by (WAIT [2:0] - 1). Since a wide access interface with a pre-fetch buffer and branch cache is provided, the wait state of sequential Flash access is very close to zero.

WAIT [2:0] Wait Status Allowed HCLK Range

001 0 0 MHz < HCLK ≤ 24 MHz

010 1 24 MHz < HCLK ≤ 48 MHz

011 2 48 MHz < HCLK ≤ 72 MHz

Others 3 72 MHz < HCLK ≤ 96 MHz

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SRAM Booting Vector Register n – SBVTn, n = 0 ~ 3

These registers specify the initial values of Stack Point, Program Counter, NMI Handler address and Hard Fault Handler address for the SRAM Booting mode.

Offset: 0x300 (0) ~ 0x30C (3)

Reset value: Various depending on the address offset

31 30 29 28 27 26 25 24

SBVTn

Type/Reset RW X RW X RW X RW X RW X RW X RW X RW X

23 22 21 20 19 18 17 16

SBVTn

Type/Reset RW X RW X RW X RW X RW X RW X RW X RW X

15 14 13 12 11 10 9 8

SBVTn

Type/Reset RW X RW X RW X RW X RW X RW X RW X RW X

7 6 5 4 3 2 1 0

SBVTn

Type/Reset RW X RW X RW X RW X RW X RW X RW X RW X

Bits Field Descriptions

[31:0] SBVTn SRAM Booting Vector n ( n = 0 ~ 3 )

The SRAM Booting Vector 0 ~ 3 provide a SRAM booting capability for applications debugging. The contents of the SBVTn registers are re-mapped into addresses 0x0 ~ 0xC of the Flash memory CODE area under SRAM booting mode. Refer to the description of the VCMR register and BOOT1 / BOOT0 boot pins. The following table shows the purpose and reset value of the SBVTn register.

The reset value provides a xed setting for program execution during the SRAM booting mode. Those registers can be modied by the debugging tool in order to

change the program execution setting. The reset values of SBVTn will be reloaded only by a power-on reset. Other reset sources will have no effect.

Name Address Offset Purpose Descriptions Reset Value

SBVT0 0x300 Stack point 16 KB SRAM: 0x2000_4000

SBVT1 0x304 Program counter 0x2000_0155

SBVT2 0x308 NMI handler address 0x0000_0000

SBVT3 0x30C

This access width of the registers SBVT0 ~ SBVT3 must be 32 bits (Word access), 8 or 16 bits (Byte or Half-Word) access is not allowed.

Hard fault handler address

0x0000_0000

Flash Memory Controller (FMC)

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Custom ID Register n – CIDRn, n = 0 ~ 3

This register is used to store the custom ID information which can be used as the custom identity.

Offset: 0x310 (0) ~ 0x31C (3)

Reset value: Various depending on Flash Manufacture Privilege Information Block

31 30 29 28 27 26 25 24

CID

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

23 22 21 20 19 18 17 16

CID

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

15 14 13 12 11 10 9 8

CID

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

7 6 5 4 3 2 1 0

CID

Type/Reset RO X RO X RO X RO X RO X RO X RO X RO X

Flash Memory Controller (FMC)

Bits Field Descriptions

[31:0] CIDn Custom ID

Read as the CIDn[31:0] (n = 0 ~ 3) field in the Custom ID registers in Flash Manufacture Privilege Block.

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Power Control Unit (PWRCU)

Introduction

The power consumption can be regarded as one of the most important issues for many embedded

system applications. Accordingly the Power Control Unit, PWRCU, provides many types of power

saving modes such as Sleep, Deep-Sleep1, Deep-Sleep2 and Power-Down modes. These modes reduce the power consumption and allow the application to achieve the best trade-off between the

conicting demands of CPU operating time, speed and power consumption. The dash line in the

Figure 11 indicates the power supply source of three digital power domains.

BAT

nRST

WAKEUP

RTCOUT

BAK

PWRSW

WKUP1

WKUP2

LSI

LSE

WKUP3

PORB

BREG

Backup Domain

Power On Reset

BAK

RTC

PORB: V BREG: Backup Registers

PWR_CTRL

LDO: Voltage Regulator DMOS: Depletion MOS

LDOOFF

LCM

DMOSON

WKUP4

SLEEPDEEP

SLEEPING

VDDDomain

LDO

DMOS

HSE

1.5 V Domain

CPU Memories

APB

INTF

LVD: Low Voltage Detector POR/PDR: Power On Reset/Power Down Reset

PLL

HSI

3.3 V

POR/PDR

LVD

1.5 V

POR/PDR

Digital

Peripheral

CLDO

DD15

Power Control Unit (PWRCU)

Figure 11. PWRCU Block Diagram

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Features

▄

Three power domains: Backup, VDD and 1.5 V power domains.

▄

Four power saving modes: Sleep, Deep-Sleep1, Deep-Sleep2 and Power-Down modes.

▄

Internal Voltage regulator supplies 1.5 V voltage source.

▄

Additional Depletion MOS supplies 1.5 V voltage source with low leakage and low operating current.

▄

A power reset is generated when one of the following events occurs:

● Power-on / Power-down reset (POR / PDR reset).

● When exiting Power-Down mode.

● The control bits BODEN = 1, BODRIS=0 and the supply power VDD ≤ V

▄

Brown Out Detector can issue a system reset or an interrupt when VDD power source is lower than the Brown Out Detector voltage V

▄

LVD Low Voltage Detector can issue an interrupt or wakeup event when VDD is lower than a programmable threshold voltage V

▄

Battery power (V

▄

40 bytes of backup registers powered by V

the Power-Down mode.

BOD

LVD

) for backup domain when VDD is lower than V

BAT

for data storage of user application data when in

BAK

voltage.

PDR

BOD

Power Control Unit (PWRCU)

Functional Descriptions

Backup Domain

Power Switch

The Backup Domain is powered by the VDD power source or the battery power source, V is selected by the power switch PWRSW. The operating voltage range of the Back Domain is from 2.0 V to 3.6 V. If VDD is lower than V

automatically switched from VDD to V in the backup domain can operate normally. This means that the backup register contents will be retained, the RTC circuitry will operate normally and the low speed oscillators can keep running.

Backup Domain Reset

The Backup Domain reset sources include the Backup Domain Power-On-Reset (PORB) and the Backup Domain software reset which is activated by setting the BAKRST bit in the BAKCR register. The PORB signal forces the device to stay in the reset mode until the V

. The application software can set the PORBDN bit in the BAKCR register to disable PORB

PORB

circuit to save the current consumption in the Backup Domain. Also the application software can trigger Backup Domain software reset by setting the BAKRST bit in the BAKCR register. All registers of PWRCU and RTC will be reset only by the Backup Domain reset.

LSE, LSI and RTC

The Real Time Clock circuitry clock source can be derived from either the Low Speed Internal

RC oscillator, LSI, or the Low Speed External Crystal oscillator, LSE. Before entering the power saving mode by executing WFI / WFE instruction, the MCU needs to setup the compare register

with an expected wakeup time and enable the wakeup function to achieve the RTC timer wakeup event. After entering the power saving mode for a certain amount of time, the Compare Match

ag, CMFLAG, will be asserted to wakeup the device when the compare match event occurs. The details of the RTC conguration for wakeup timer will be described in the RTC chapter.

, which

BAT

, then the power source of the Back Domain will be

PDR

. Therefore, even if VDD is powered down, all the circuitry

BAT

is greater than

BAK

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Backup Registers and Isolation Cells

Ten 32-bit registers, up to 40 bytes, are located in the Backup Domain for user application data

storage. These registers are powered by V

core power is switched off. The Backup Registers are only reset by the Backup Domain power-onreset, PORB, or the Backup Domain software reset, BAKRST. When the device resumes operation from the 1.5 V power, either by Hardware or Software, access to the Backup registers and the RTC

registers are disabled by the isolation cells which protect these registers against possible parasitic write accesses. To resume access operations, users must disable these isolation cells by setting the

BKISO bit to 1 in the LPCR register of the Clock Control Unit.

LDO Power Control

The LDO will be automatically switched off when one of the following conditions occurs:

▄

The Power-Down or Deep-Sleep 2 mode is entered.

▄

The control bits BODEN = 1, BODRIS = 0 and the supply power VDD ≤ V

▄

The supply power VDD ≤ V

The LDO will be automatically switched on by hardware when the supply power VDD > V

of the following conditions occurs:

PDR

which constantly supplies power when the 1.5 V

BAK

BOD

POR

Power Control Unit (PWRCU)

if any

▄

Resume operation from the power saving mode – RTC wakeup, LVD wakeup and WAKEUP pin

rising edge.

▄

Detect a falling edge on the external reset pin (nRST).

▄

The control bit BODEN = 1 and the supply power VDD > V

BOD

To enter the Deep-Sleep1 mode, the PWRCU will request the LDO to operate in a low current mode, LCM. To enter the Deep-Sleep 2 mode, the PWRCU will turn off the LDO and turn on the DMOS to supply an alternative 1.5 V power.

VDD Power Domain

Voltage Regulator

The voltage regulator, LDO, Depletion MOS, DMOS, Low voltage Detector, LVD and High Speed

Internal oscillator, HSI are operated under the VDD power domain. The LDO can be congured to

operate in either normal mode (LDOOFF = 0, SLEEPDEEP = 0, I current mode (LDOOFF = 0, SLEEPDEEP=1, I

= Low current mode) to supply the 1.5 V power.

OUT

An alternative 1.5 V power source is the output of the DMOS which has low static and driving current characteristics. It is controlled using the DMOSON bit in the BAKCR register. The DMOS

output has weak output current and regulation capability and only operates in the Deep-Sleep 2 mode for data retention purposes in the V

power domain.

DD15

Power On Reset (POR) / Power Down Reset (PDR)

The device has an integrated POR / PDR circuitry that allows proper operation starting from/down to 2.0 V. The device remains in Power-Down mode when VDD is below a specied threshold V

without the need for an external reset circuit. For more details of the power on / power down reset threshold voltage, refer to the electrical characteristics of the corresponding datasheet.

= High current mode) or low

OUT

PDR

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POR

Hysteresis

PDR

Power Control Unit (PWRCU)

POR Delay Time

RESET

RSTD

Figure 12. Power On Reset / Power Down Reset Waveform

Low Voltage Detector / Brown Out Detector

The Low Voltage Detector, LVD, can detect whether the supply voltage VDD is lower than a programmable threshold voltage V

. It is selected by the LVDS bits in the LVDCSR register.

LV D

When a low voltage on the VDD power pin is detected, the LVDF ag will be active and an interrupt will be generated and sent to the MCU core if the LVDEN and LVDIWEN bits in the LVDCSR

register are set. For more details concerning the LVD programmable threshold voltage V to the electrical characteristics of the corresponding datasheet.

The Brown Out Detector, BOD, is used to detect if the VDD supply voltage is equal to or lower

than V is lower than V

. When the BODEN bit in the LVDCSR register is set to 1 and the VDD supply voltage

BOD

then the BODF ag is active. The PWRCU will regard this as a power down

BOD

reset situation and then immediately disable the internal LDO regulator when the BODRIS bit is cleared to 0 or issue an interrupt to notify the CPU to execute a power down procedure when the BODRIS bit is set to 1. For more details concerning the Brown Out Detector voltage V

the electrical characteristics of the corresponding datasheet.

High Speed Internal Oscillator

The High Speed Internal Oscillator, HSI, is located in the VDD power domain. When exiting from the Deep-Sleep mode, the HSI clock will be congured as the system clock for a certain period by

setting the PSRCEN bit to 1. This bit is located in the Global Clock Control Register, GCCR, in

the Clock Control Unit, CKCU. The system clock will not be switched back to the original clock

source used before entering the Deep-Sleep mode until the original clock source, which may be either sourced from the PLL or HSE stabilizes. Also the system will force the HSI oscillator to be the system clock after a wake up from Power-Down mode since a 1.5 V power on reset will occur.

Time

LV D

, refer to

BOD

, refer

High Speed External Oscillator

The High Speed External Oscillator, HSE, is located in the VDD power domain. The HSE crystal

oscillator can be switched on or off using the HSEEN bit in the Global Clock Control Register (GCCR). The HSE clock can then be used directly as the system clock source or be used as the PLL input clock.

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1.5 V Power Domain

The main functions that include the APB interface for the backup domain, CPU core logic, AHB / APB peripherals and memories and so on are located in this power domain. Once the 1.5 V is powered up, the POR will generate a reset sequence (Refer to PORB) on 1.5 V power domain.

Subsequently, to enter the expected power saving mode, the associated control bits including the LDOOFF, DMOSON and SLEEPDEEP bits must be congured. Then, once a WFI or WFE instruction is executed, the device will enter an expected power saving mode which will be discussed in the following section.

Operation Modes

Run Mode

In the Run mode, the system operates with full functions and all power domains are active. There

are two ways to reduce the power consumption in this mode. The rst is to slow down the system clock by setting the AHBPRE field in the CKCU AHBCFGR register and the second is to turn off the unused peripherals clock by setting the APBCCR0 and APBCCR1 registers or slow down peripherals clock by setting the APBPCSR0 and APBPCSR1 registers to meet the application

requirement. Reducing the system clock speed before entering the sleep mode will also help to minimize power consumption.

Power Control Unit (PWRCU)

Additionally, there are several power saving modes to provide maximum optimization between device performance and power consumption.

Table 11. Operation Mode Denitions

Mode name Hardware Action

Run After system reset, CPU fetches instructions to execute.

Sleep

Deep-Sleep1 ~ 2

Power-Down Shut down the 1.5 V power domain

CPU clock will be stopped. Peripherals, Flash and SRAM clocks can be stopped by setting.

Stop all clocks in the 1.5 V power domain. Disable HSI, HSE and PLL. Turning on the LDO low current mode or DMOS to reduce the 1.5 V power domain current.

Sleep Mode

By default, only the CPU clock will be stopped in the Sleep mode. Clearing the FMCEN or SRAMEN bit in the CKCU AHBCCR register to 0 will have the effect of stopping the Flash clock

or SRAM clock after the system enters the Sleep mode. If it is not necessary for the CPU to access the Flash memory and SRAM in the Sleep mode, it is recommended to clear the FMCEN and

SRAMEN bits in the AHBCCR register to minimize power consumption. To enter the Sleep mode, it is only necessary to clear the SLEEPDEEP bit to 0 and execute a WFI or WFE instruction. The

system will exit from the Sleep mode via any interrupt or event trigger. The accompanying table provides more information about the power saving modes.

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Table 12. Enter / Exit Power Saving Modes

Mode

Instruction

Sleep

Deep-Sleep1 1 0 0

Deep-Sleep2 1 X 1

Power-Down 1 1 0

WFI or WFE

CPU

(Takes

effect)

Mode Entry

CPU

SLEEPDEEP

0 X X

LDOOFF DMOSON

Mode Exit

WFI: Any interrupt WFE:

Any wakeup event Any interrupt (NVIC on) or Any interrupt with SEVONPEND = 1 (NVIC off)

Any EXTI in event mode or RTC wakeup or CMP Wakeup or LVD wakeup WAKEUP pin rising edge or USB resume

RTC wakeup or LVD wakeup WAKEUP pin rising edge

RTC wakeup or LVD wakeup WAKEUP pin rising edge or External reset (nRST)

(2)

(1)

Power Control Unit (PWRCU)

Notes:

1. Wakeup event means EXTI line in event mode, RTC, LVD and WAKEUP pin rising edge

2. If the system allows the LVD activity to wake it up after the system has entered the power saving mode, the LVDEWEN and LVDEN bits in the LVDCSR register must be set to 1 to make sure that the system can be waked up by an LVD event and then the LDO regulator can be turned on when system is woken up from the Deep-Sleep2 and Power-Down modes.

Deep-Sleep Mode

To enter Deep-Sleep mode, configure the registers as shown in the preceding table and execute

the WFI or WFE instruction. In the Deep-Sleep mode, all clocks including PLL and high speed oscillator, known as HSI and HSE, will be stopped. In addition, Deep-Sleep1 turns the LDO into low current mode while Deep-Sleep2 turns off the LDO and uses a DMOS to keep 1.5 V power. Once the PWRCU receives a wakeup event or an interrupt as shown in the preceding Mode-Exiting table, the LDO will then operate in normal mode and the high speed oscillator will be enabled.

Finally, the CPU will return to Run mode to handle the wakeup interrupt if required. A Low Voltage Detection also can be regarded as a wakeup event if the corresponding wakeup control bit

LVDEWEN in the LVDCSR register is enabled. The last wakeup event is a transition from low to high on the external WAKEUP pin sent to the PWRCU to resume from Deep-Sleep mode. During

the Deep-Sleep mode, retaining the register and memory contents will shorten the wakeup latency.

Power-Down Mode

The Power-Down mode is derived from the Deep-Sleep mode of the CPU together with the

additional control bits LDOOFF and DMOSON. To enter the Power-Down mode, users can congure the registers shown in the preceding Mode-Entering table and execute the WFI or WFE

instruction. An RTC wakeup trigger event, an LVD wakeup, a low to high transition on the external

WAKEUP pin or an external reset (nRST) signal will force the MCU out of the Power-Down mode.

In the Power-Down mode, the 1.5 V power supply will be turned off. The remaining active power supplies are the 3.3 V power (V

/ V

) and the Backup Domain power (V

DDA

BAK

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After a system reset, the PORSTF bit in the RSTCU GRSR register, the PDF and BAKPORF bits in the BAKSR register should be checked by software to conrm if the device is being resumed

from the Power-Down mode by a backup domain power on reset, an unexpected loss of the 1.5

V power or other reset events (nRST, WDT,…). If the device has entered the Power-Down mode under the correct rmware procedure, then the PDF bit will be set. The System information could be saved in the Backup Registers and be retrieved when the 1.5 V power domain is powered on again. More information about the PDF and BAKPORF bits in the BAKSR register and PORSTF

bit in the RSTCU GRSR register is shown in the following table.

Table 13. Power Status after System Reset

BAKPORF PDF PORSTF Description

1 0 1

0 0 1

0 1 1 Restart from the Power-Down mode.

1 1 x Reserved

Power-up for the rst time after the backup domain is reset:

Power on reset when V software reset command on the backup domain.

Restart from unexpected loss of the 1.5 V power or other reset (nRST, WDT, …)

is applied for the rst time or executing

BAK

Power Control Unit (PWRCU)

Register Map

The following table shows the PWRCU registers and reset values. Note all the registers in this unit

are located in the V

Table 14. PWRCU Register Map

PWRCU Base Address = 0x4006_A000

BAKSR 0x100 Backup Domain Status Register 0x0000_0001

BAKCR 0x104 Backup Domain Control Register 0x0000_0000

BAKTEST 0x108 Backup Domain Test Register 0x0000_0027

LVDCSR 0x110

BAKREG0 0x200 Backup Register 0 0x0000_0000

BAKREG1 0x204 Backup Register 1 0x0000_0000

BAKREG2 0x208 Backup Register 2 0x0000_0000

BAKREG3 0x20C Backup Register 3 0x0000_0000

BAKREG4 0x210 Backup Register 4 0x0000_0000

BAKREG5 0x214 Backup Register 5 0x0000_0000

BAKREG6 0x218 Backup Register 6 0x0000_0000

BAKREG7 0x21C Backup Register 7 0x0000_0000

BAKREG8 0x220 Backup Register 8 0x0000_0000

BAKREG9 0x224 Backup Register 9 0x0000_0000

backup power domain.

BAK

Low Voltage / Brown Out Detect Control and Status Register

0x0000_0000

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Register Descriptions

Backup Domain Status Register – BAKSR

This register indicates backup domain status.

Offset: 0x100

Reset value: 0x0000_0001 (Reset only by Backup Domain reset)

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

Reserved WUPF

Type/Reset RC 0

7 6 5 4 3 2 1 0

Reserved PDF BAKPORF

Type/Reset RC 0 RC 1

Power Control Unit (PWRCU)

Bits Field Descriptions

[8] WUPF External WAKEUP Pin Flag

0: The Wakeup pin is not asserted 1: The Wakeup pin is asserted

This bit is set by hardware when the WAKEUP pin asserts and is cleared by software read. Software should read this bit to clear it after a system wake up from the power saving mode.

[1] PDF Power Down Flag

0: Wakeup from abnormal V 1: Wakeup from Power-Down mode (Loss of V

This bit is set by hardware when the system has successfully entered the PowerDown mode This bit is cleared by software read.

[0] BAKPORF Backup Domain Reset Flag

0: Backup Domain reset does not occur 1: Backup Domain reset occurs

This bit is set by hardware when Backup Domain reset occurs, either a Backup Domain power on reset or Backup Domain software reset. The bit is cleared by

software read. This bit must be cleared after the system is rst powered, otherwise it

will be impossible to detect when a Backup Domain reset has been triggered. When this bit is read as 1, a read software loop must be implemented until the bit returns

again to 0. This software loop is necessary to conrm that the Backup Domain is ready for access. It must be implemented after the Backup Domain is rst powered

up.

shutdown (Loss of V

DD15

is unexpected)

DD15

is under expectation)

DD15

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Backup Domain Control Register – BAKCR

This register provides power control bits for the Deep-Sleep and Power-Down modes.

Offset: 0x104

Reset value: 0x0000_0000 (Reset only by Backup Domain reset)

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

DMOSSTS Reserved V15RDYSC Reserved WUPIEN WUPEN

Type/Reset RO 0 RW 0 RW 0 RW 0

7 6 5 4 3 2 1 0

DMOSON Reserved LDOFTRM LDOOFF LDOLCM Reserved BAKRST

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 WO 0

Power Control Unit (PWRCU)

Bits Field Descriptions

[15] DMOSSTS Depletion MOS Status

This bit is set to 1 if the DMOSON bit in this register has been set to 1. This bit is cleared to 0 if the DMOSON bit has been set to 0 or if a POR / PDR reset occurred.

[12] V15RDYSC V

[9] WUPIEN External WAKEUP Pin Interrupt Enable

Ready Source Selection.

DD15

0: BKISO bit in the LPCR register located in the CKCU 1: V

POR

DD15

Setting this bit to determine what control signal of isolation cells is used to disable the isolation function of the V

to VDD power domain level shifter.

DD15

0: Disable WAKEUP pin interrupt function 1: Enable WAKEUP pin interrupt function

The software can set the WUPIEN bit to 1 to assert the LPWUP interrupt in the NVIC unit when both the WUPEN and WUPF bits are set to1.

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Bits Field Descriptions

[8] WUPEN External WAKEUP Pin Enable

0: Disable WAKEUP pin function 1: Enable WAKEUP pin function

The Software can set the WUPEN bit as 1 to enable the WAKEUP pin function before entering the power saving mode. When WUPEN = 1, a rising edge on the WAKEUP pin wakes up the system from the power saving mode. As the WAKEUP pin is active high, this bit will set an input pull down mode when the bit is high. The corresponding register bits which should be properly setup are the PCPD [15] to 1 in the PCPDR register, the PCPU [15] to 0 in the PCPUR register and the PCCFG15

eld to 0x01 in the GPCCFGHR register.

Note: This bit is reset by a system reset or a Backup Domain reset. Because this bit

is located in the Backup Domain, after reset activity there will be a delay until

the bit is active. The bit will not be active until the system reset nished and

the Backup Domain ISO signal has been disabled. This means that the bit

can not be immediately set by software after a system reset nished and the

Backup domain ISO signal disabled. The delay time needed is a minimum of

three 32 kHz clock periods until the bit reset activity has nished.

[7] DMOSON DMOS Control

0: DMOS is OFF 1: DMOS is ON

A DMOS is implemented to provide an alternative voltage source for the 1.5 V power domain when the CPU enters the Deep-Sleep mode (SLEEPDEEP = 1). The control bit DMOSON is set by software and cleared by software or PORB. If the DMOSON bit is set to 1, the LDO will automatically be turned off when the CPU enters the Deep-Sleep mode.

[5:4] LDOFTRM LDO Output Voltage Fine Trim

00: The LDO default output voltage. 01: The LDO default output voltage offset -5 % 10: The LDO default output voltage offset +3 % 11: The LDO default output voltage offset +7 %

These bits will be clear to 0 when the LDO is power down or VDD power domain reset.

[3] LDOOFF LDO Operating Mode Control

0: The LDO operates in a low current mode when CPU enters the Deep-Sleep

mode (SLEEPDEEP = 1). The V

1: The LDO is turned off when the CPU enters the Deep-Sleep mode

(SLEEPDEEP = 1). The VDD15 power is not available

Note: This bit is only available when the DMOSON bit is cleared to 0.

[2] LDOLCM LDO Low Current Mode

0: The LDO is operated in normal current mode 1: The LDO is operated in low current mode

Note: This bit is only available when CPU is in the run mode. The LDO output current

capability will be limited at 10 mA below and lower static current when the LDOLCM bit is set. It is suitable for CPU is operated at lower speed system clock to get a lower current consumption. This bit will be clear to 0 when the LDO is power down or VDD power domain reset.

[0] BAKRST Backup Domain Software Reset

0: No action 1: Backup Domain Software Reset is activated - includes all the related RTC and

PWRCU registers

power is available

DD15

Power Control Unit (PWRCU)

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Backup Domain Test Register – BAKTEST

This register specifies a read-only value for the software to recognize whether backup domain is ready for access.

Offset: 0x108

Reset value: 0x0000_0027

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

BAKTEST

Type/Reset RO 0 RO 0 RO 1 RO 0 RO 0 RO 1 RO 1 RO 1

Bits Field Descriptions

[7:0] BAKTEST Backup Domain Test Bits

A constant 0x27 will be read when the Backup Domain is ready for CPU access.

Low Voltage / Brown Out Detect Control and Status Register – LVDCSR

This register species ags, enable bits and option bits for Low-voltage / Brown-out detector.

Offset: 0x110

Reset value: 0x0000_0000 (Reset only by Backup Domain reset)

Power Control Unit (PWRCU)

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved LVDS [2] LVDEWEN LVDIWEN LVDF LVDS [1:0] LVDEN

Type/Reset RW 0 RW 0 RW 0 RO 0 RW 0 RW 0 RW 0

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved BODF Reserved BODRIS BODEN

Type/Reset RO 0 RW 0 RW 0

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Bits Field Descriptions

[21] LVDEWEN LVD Event Wakeup Enable

0: LVD event wakeup is disabled 1: LVD event wakeup is enabled

Setting this bit to 1 will enable the LVD event wakeup function to wake up the system when a LVD condition occurs which result in the LVDF bit being asserted. If the system requires to be waked up from the Deep-Sleep or Power-Down mode by a LVD condition, this bit must be set to 1.

[20] LVDIWEN LVD Interrupt Wakeup Enable

0: LVD interrupt wakeup is disabled 1: LVD interrupt wakeup is enabled

Setting this bit to 1 will enable the LVD interrupt function. When a LVD condition occurs and the LVDIWEN bit is set to 1, a LVD interrupt will be generated and sent to the CPU NVIC unit.

[19] LVDF Low Voltage Detect Status Flag

0: V

is higher than the specic voltage level

DDA

1: V

is equal to or lower than the specic voltage level

DDA

When the LVD condition occurs, the LVDF ag will be asserted. When the LVDF ag

is asserted, a LVD interrupt will be generated for CPU if the LVDIWEN bit is set to 1. However, if the LVDEWEN bit is set to 1 and the LVDIWEN bit is cleared to 0, only a LVD event will be generated rather than a LVD interrupt when the LVDF flag is asserted.

[22], [18:17] LVDS [2:0] Low Voltage Detect Level Selection

For more details concerning the LVD programmable threshold voltage, refer to the electrical characteristics of the corresponding datasheet.

[16] LVDEN Low Voltage Detect Enable

0: Disable Low Voltage Detect 1: Enable Low Voltage Detect

Setting this bit to 1 will generate a LVD event when the V the voltage set by LVDS bits. Therefore when the LVD function is enabled before the system enters the Deep-Sleep2 (DMOS is turn on and LDO is power down) or Power-Down mode (DMOS and LDO is power down), the LVDEWEN bit has to be enabled to avoid the LDO does not activate in the meantime when the CPU is woken up by the low voltage detection activity.

[3] BODF Brow Out Detect Flag

0: VDD > V 1: VDD ≤ V

[1] BODRIS BOD Reset or Interrupt Selection

0: Reset the whole chip 1: Generate Interrupt

[0] BODEN Brown Out Detector Enable

0: Disable Brown Out Detector 1: Enable Brown Out Detector

BOD

power is lower than

DDA

Power Control Unit (PWRCU)

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Backup Register n – BAKREGn, n = 0 ~ 9

This register species backup register n for storing data during the V

power-off period.

DD15

Offset: 0x200 ~ 0x224

Reset value: 0x0000_0000 (Reset only by Backup Domain reset)

31 30 29 28 27 26 25 24

BAKREGn

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

23 22 21 20 19 18 17 16

BAKREGn

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

15 14 13 12 11 10 9 8

BAKREGn

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

7 6 5 4 3 2 1 0

BAKREGn

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

Bits Field Descriptions

[31:0] BAKREGn Backup Register n (n = 0 ~ 9)

These registers are used for data storage in general purpose. The contents of BAKREGn registers will remain even if the V

power is lost.

DD15

Power Control Unit (PWRCU)

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Clock Control Unit (CKCU)

Introduction

The Clock Control unit (CKCU) provides functions of high speed internal RC oscillator (HSI),

High speed external crystal oscillator (HSE), Low speed internal RC oscillator (LSI), Low speed external crystal oscillator (LSE), Phase Lock Loop (PLL), HSE clock monitor, clock prescaler,

clock multiplexer and clock gating. The clock of AHB, APB and CPU are derived from system clock (CK_SYS) which can come from HSI, HSE, LSI, LSE or PLL. Watchdog Timer and Real

Time Clock (RTC) use either LSI or LSE as their clock source. The maximum operating frequency of system clock f

A variety of internal clocks can also be wired out though CKOUT for debugging purpose. The clock monitor can be used to get clock failure detection of HSE. Once the clock of HSE does not

function (could be broken down or removed or etc.), CKCU will force to switch the system clock source to HSI clock to prevent system halt.

Features

▄

4 to 16 MHz external crystal oscillator – HSE

▄

Internal 8 MHz RC oscillator (HSI) with conguration option calibration and custom trimming capability

▄

PLL with selectable clock source, either from HSE or HSI, for system clock

▄

32,768 Hz external crystal oscillator (LSE) for Watchdog Timer or RTC or system clock

▄

Internal 32 kHz RC oscillator (LSI) for Watchdog Timer, RTC or system clock

▄

HSE clock monitor

can be up to 96 MHz.

CK_AHB

Clock Control Unit (CKCU)

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ADC, SPIx, USARTx,

HT32F12345

HSI Auto Trimming Controller

8 MHz

HSI RC

HSIEN

4-16 MHz

HSE XTAL

HSEEN

CK_LSE

USB Frame Pulse

USBPLLSRC

PLLSRC

CK_HSI

CK_HSE

USBPLLEN

USB

PLL

PLLEN

PLL

CKREFEN

USBEN

CK_USBPLL

CK_PLL

SW[2:0]

00x

011

CK_SYS

010

111

110

CK_SYS,max

AHB Prescaler

1,2,4,8,16,32

= 96 MHz

CKREFPRE

Prescaler

1 ~ 32

USBPRE

Prescaler

1, 2

USBSRC

GPIOAEN

GPIOEEN

CM3EN

(control by HW)

DMAEN

EBIEN

Divider

CK_REF

= 48MHz

CK_USB

STCLK

(to SysTick)

CK_GPIO

( to GPIO port)

FCLK

( free running clock)

HCLKC

( to Cortex

-M3)

HCLKD

( to PDMA)

CK_EBI ( to EBI)

Clock Control Unit (CKCU)

Clock

Monitor

32.768 kHz LSE OSC

LSEEN

32 kHz LSI RC

(Note1)

LSIEN

CKOUTSRC[2:0]

CKOUT

CK_LSE

(Note1)

CK_LSI

000

001

010

011

100

101

110

WDTSRC

1 0

RTCSRC

1 0

CK_REF

HCLKC/16

CK_SYS/16

CK_HSE/16

CK_HSI/16

CK_LSE

CK_LSI

WDTEN

(Note1)

RTCEN

CK_WDT

CK_RTC

(Note1)

Legend: HSE = High Speed External clock HSI = High Speed Internal clock LSE = Low Speed External clock LSI = Low Speed Internal clock

Note 1: Those control bits are located at RTC Control Register (RTC_CTRL)

CK_AHB

CM3EN

FMCEN

CM3EN

SRAMEN

CM3EN

BMEN

CM3EN

APB0EN

CM3EN

APB1EN

ADCEN

SDIOEN

Peripherals

Clock

Prescaler

1,2,4,8

CRCEN

PCLK

PCLK/2

PCLK/4

PCLK/8

ADC

Prescaler

1,2,4,6,8...

SPIEN

SCIEN

CK_CRC ( to CRC)

CK_SDIO ( to SDIO)

HCLKF

( to Flash)

HCLKS

( to SRAM)

HCLKBM

( to Bus Matrix)

HCLKAPB0

( to APB0 Bridge)

HCLKAPB1

( to APB1 Bridge)

CK_ADC IP

PCLK ( CMP, AFIO,

UARTx, I2Cx, I2S, GPTMx, MCTMx, BFTMx, EXTI, RTC, WDT)

Figure 13. CKCU Block Diagram

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Functional Descriptions

High Speed External Crystal Oscillator (HSE)

The high speed external 4 to 16 MHz crystal oscillator (HSE) produces a highly accurate clock source to the system clock. The related hardware configuration is shown in the following

gure. The crystal with specic frequency must be placed across the two HSE pins (XTALIN / XTALOUT) and the external components such as resistors and capacitors are necessary to make it

oscillate properly.

The following guidelines are provided to improve the stability of the crystal circuit PCB layout.

▄

The crystal oscillator should be located as close as possible to the MCU so that the trace lengths are kept as short as possible to reduce any parasitic capacitances.

▄

Shield any lines in the vicinity of the crystal by using a ground plane to isolate signals and reduce noise.

▄

Keep frequently switching signal lines away from the crystal area to prevent crosstalk.

Clock Control Unit (CKCU)

OSC_EN

XTALOUTXTALIN

Crystal

4 MHz ~ 16 MHz

CL1 CL2

Figure 14. External Crystal, Ceramic and Resonators for HSE

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The HSE crystal oscillator can be switched on or off using the HSEEN bit in the Global Clock

Control Register (GCCR). The HSERDY f lag in the Global Clock Status Register (GCSR) will indicate if the high-speed external crystal oscillator is stable. While switching on the HSE, the HSE clock will still not be released until this HSERDY bit is set by the hardware. The specic delay

period is well-known as “Start-up time”. As the HSE becomes stable, an interrupt will be generated

if the related interrupt enable bit HSERDYIE in the Global Clock Interrupt Register (GCIR) is set.

The HSE clock can then be used directly as the system clock source or be used as the PLL input clock.

High Speed Internal RC Oscillator (HSI)

The high speed internal 8 MHz RC oscillator (HSI) is the default selection of clock source for the CPU when the device is powered up. The HSI RC oscillator provides a clock source in a lower cost because no external components are required. The HSI RC oscillator can be switched on or off

using the HSIEN bit in the Global Clock Control Register (GCCR). The HSIRDY ag in the Global

Clock Status Register (GCSR) will indicate if the internal RC oscillator is stable. The start-up time of HSI is shorter than the HSE crystal oscillator. An interrupt can be generated if the related

interrupt enable bit HSIRDYIE in the Global Clock Interrupt Register (GCIR) is set as the HSI

becomes stable. The HSI clock can also be used as the PLL input clock.

Clock Control Unit (CKCU)

The accuracy of the frequency of the high speed internal RC oscillator HSI can be calibrated via the

conguration options, but it is still less accurate than the HSE crystal oscillator. The applications,

the environments and the cost will determine the use of the oscillators.

Software could congure the Power Saving Wakeup RC Clock Enable bit PSRCEN to 1 to force HSI clock to be system clock when wake-up from Deep-Sleep or Power-Down mode. Subsequently, the system clock is back to the original clock source if the original clock source ready f lag is asserted. This function can reduce the wakeup time when using HSE or PLL as system clock.

Auto Trimming of High Speed Internal RC Oscillator (HSI)

The frequency accuracy of the high speed internal RC oscillator HSI can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated for ±2 % accuracy at VDD = 3.3 V and TA = 25 °C. But the accuracy is not enough for some applications and environments requirement. Therefore, this device provides the trimming mechanism for HSI frequency calibration using more accurate external reference clock. The detail block diagram is shown as Figure 15

After reset, the factory trimming value is loaded in the HSICOARSE [4:0] and HSIFINE [7:0] bits in the HSI Control Register (HSICR). The HSI frequency may be affected by voltage or temperature variations. If the application has to be driven by a more accurate HSI frequency, the HSI frequency can be manually trimmed using the HSIFINE [7:0] bits in the HSI Control Register (HSICR) or automatically adjusted via the Auto Trimming Controller (ATC) together with an external reference clock in the application. The reference clock can be provided from the following clock sources:

▄

32,768 Hz low speed external crystal or ceramic resonator oscillator LSE output clock

▄

1 kHz USB SOF package reception

▄

External pin (CKIN) with 1 kHz pulse

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Auto Trimming HSI Block Diagram

TMSEL

External pin (CKIN)

USB SOF

LSE

32.768 kHz

Factory

Trimming Bits

TRIMEN

/32

REFCLKSEL

Fine [7:0]

Coarse [4:0]

1 kHz

/1.024 kHz

Fine-Trimming Write Register

ATCEN

Auto Trimming

Controller

Fine-Trimming Read Register

8 MHz HSI

Oscillator

8 MHz

Counter

Clock Control Unit (CKCU)

AHB Bus

Coarse-Trimming

Read Register

Figure 15. HSI Auto Trimming Block Diagram

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Phase Locked Loop – PLL

This PLL can provide 8 ~ 96 MHz clock output which is 2 ~ 24 multiples of a fundamental reference frequency of 4 ~ 16 MHz. The rationale of the clock synthesizer relies on the digital Phase Locked Loop (PLL) which includes a reference divider, a feedback divider, a digital phase frequency detector (PFD), a current-controlled charge pump (CP), a built-in loop filter and a

voltage-controlled oscillator (VCO) to achieve a stable phase-locked state.

CLK

= 4 ~ 16 MHz

Ref. Divider

(NR)

CP VCO

Loop Filter

= 128 ~ 192 MHz

VCO

out

Output Divider 1

(NO1)

Clock Control Unit (CKCU)

Output Divider 2

(NO2)

S1 ~ S0

PLL

out

= 8 ~ 96 MHz

Feedback Divider 2

B4 ~ B0

Figure 16. PLL Block Diagram

Frequency of the PLL output clock can be determined by the following formula:

Where NR = Ref divider = 2, NF1 = Feedback Divider 1 = 4, NF2 = Feedback Divider 2 = 1 ~ 32, NO1 = Output Divider 1 = 2, NO2 = Output Divider 2 = 1, 2, 4, or 8.

Considering the duty cycle with 50 %, both input frequency and output frequency is divided by 2. Assume that a given CLKIN frequency as the PLL input generates a specic PLL output frequency;

it is recommended to load a larger value into the NF2 eld to increase the PLL stability and reduce the jitter with the expense of the settling time. The output and feedback divider 2 setup value are described in Table 15 and Table 16. All the conguration bits (S1 ~ S0, B4 ~ B0) in Table 15 and Table 16 are defined in the PLL Configuration Register (PLLCFGR) and PLL Control Register

(PLLCR) in the section of Register Denition. Note that VCO

from 128 MHz to 192 MHz. If the selected configuration exceeds this range, the PLL output frequency cannot be guaranteed to match the above PLL

(NF2)

Feedback Divider 1

(NF1)

NFNF



CKPLL



NONONR





OUT





222

frequency should be in the range

OUT



INININOUT

formula.

The PLL can be switched on or off by using the PLLEN bit in the Global Clock Control Register

(GCCR). The PLLRDY ag in the Global Clock Status Register (GCSR) will indicate if the PLL clock is stable. An interrupt can be generated if the related interrupt enable bit PLLRDYIE in the

Global Clock Interrupt Register (GCIR) is set as the PLL becomes stable.

Table 15. Output Divider 2 Value Mapping

Output divider 2 setting S1 ~ S0 (POTD) NO2 (Output divider 2 value)

00 1

01 2

10 4

11 8

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Table 16. Feedback Divider 2 Value Mapping

Feedback divider 2 setting B4 ~ B0 (PFBD) NF2 (Feedback divider 2 value)

00000 32

00001 1

00010 2

00011 3

00100 4

00101 5

00110 6

00111 7

01000 8

01001 9

01010 10

01011 11

…. ….

11110 30

11111 31

Clock Control Unit (CKCU)

USB Phase Locked Loop – USB PLL

This USB PLL can provide 4 ~ 48 MHz clock output for USB peripheral which is 2 ~ 24 multiples of a fundamental reference frequency of 4 ~ 16 MHz. The rationale of the clock synthesizer relies on the digital Phase Locked Loop (PLL) which includes a reference divider, a feedback divider, a

digital phase frequency detector (PFD), a current-controlled charge pump (CP), a built-in loop lter and a voltage-controlled oscillator (VCO) to achieve a stable phase-locked state.

CLK

= 4 ~ 16 MHz

Figure 17. USB PLL Block Diagram

Ref. Divider

(NR)

Feedback Divider 2

(NF2)

B3 ~ B0

CP VCO

Loop Filter

Feedback Divider 1

(NF1)

= 48 ~ 96 MHz

VCO

out

Output Divider 1

(NO1)

Output Divider 2

(NO2)

S1 ~ S0

PLL

out

= 4 ~ 48 MHz

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Frequency of the PLL output clock can be determined by the following formula:

OUT

NFNF

CLKPLL







CLK

NONONR







CLK

222



ININ

Where NR = Ref divider = 2, NF1 = Feedback Divider 1 = 4, NF2 = Feedback Divider 2 = 1 ~ 16,

NO1 = Output Divider 1 = 2, NO2 = Output Divider 2 = 1, 2, 4, or 8.

Considering the duty cycle with 50 %, both input frequency and output frequency is divided by

2. Assume that a given CLKIN frequency as USB PLL input generates a specic USB PLL output frequency; it is recommended to load a larger value into the NF2 eld to increase the PLL stability

and reduce the jitter with the expense of the settling time. The output and feedback divider 2 value are described in Table 15 and Table 16. All the conguration bits (S1 ~ S0, B3 ~ B0) in Ta bl e 17 and Ta ble 18 are dened in the PLL Conguration Register (PLLCFGR) and PLL Control Register

(PLLCR) in the section of Register Denition. Note that VCO

is ranged from 48 MHz to 96

OUT

MHz. If your configurations exceed this range, the output frequency of USB PLL will not be

promised to match the above PLL

formula.

OUT

The USB PLL can be switched on or off by using the USBPLLEN bit in the Global Clock Control Register (GCCR). The USBPLLRDY ag in the Global Clock Status Register (GCSR) will indicate if the USB PLL clock is stable. An interrupt can be generated if the related interrupt enable bit USBPLLRDYIE in the Global Clock Interrupt Register (GCIR) is set as the USB PLL becomes

stable.

Table 17. USB PLL Output Divider 2 Value Mapping

Output divider 2 setting S1 ~ S0 (USBPOTD) NO2 (Output divider 2 value)

00 1

01 2

10 4

11 8

Clock Control Unit (CKCU)

Table 18. USB PLL Feedback Divider 2 Value Mapping

Feedback divider 2 setting B3 ~B0 (USBPFBD) NF2 (Feedback divider 2 value)

0000 16

0001 1

0010 2

0011 3

0100 4

0101 5

0110 6

0111 7

1000 8

1001 9

1010 10

1011 11

1100 12

...... ......

1111 15

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Low Speed External Crystal Oscillator – LSE

The low speed external crystal or ceramic resonator oscillator with 32,768 Hz frequency produces a low power but highly accurate clock source for the circuits of Real-Time-Clock peripheral,

Watchdog Timer or system clock. The associated hardware conguration is shown in the following figure. The crystal or ceramic resonator must be placed across the two LSE pins (X32KIN / X32KOUT) and the external components such as resistors and capacitors are necessary to make

it oscillate properly. The LSE oscillator can be switched on or off by using the LSEEN bit in the RTC Control Register RTCCR. The LSERDY ag in the Global Clock Status Register (GCSR) will indicate if the LSE clock is stable. An interrupt can be generated if the related interrupt enable bit

LSERDYIE in the Global Clock Interrupt Register (GCIR) is set as the LSE becomes stable.

Clock Control Unit (CKCU)

X32KIN

32.768 kHz

X32KOUT

Figure 18. External crystal, Ceramic and Resonators for LSE

Low Speed Internal RC Oscillator – LSI

The low speed internal RC oscillator with frequency of about 32 kHz produces a low power clock

source for the circuits of Real-Time-Clock peripheral, Watchdog Timer or system clock. The LSI

offers a low clock source because no external component is required to make it oscillates. The LSI RC oscillator can be switched on or off by using the LSIEN bit in the RTC Control Register RTCCR. The LSI frequency accuracy is shown in the Datasheet. The LSIRDY ag in the Global Clock Status Register (GCSR) will indicate if the LSI clock is stable. An interrupt can be generated

if the related interrupt enable bit LSIRDYIE in the Global Clock Interrupt Register (GCIR) is set as

the LSI becomes stable.

Clock Ready Flag

CKCU provides the corresponding clock ready flags for the HIS, HSE, PLL, LSI and LSE to indicate whether these clocks are stable. Before using them as system clock source or other purpose, it is necessary to confirm the specific clock ready flag is set. Software can check if the specific clock is ready or not by polling the individual clock ready status bits in GCSR register. Additionally, the CKCU can trigger an interrupt to notify specific clock is ready if the corresponding interrupt enable bit in the GCIR is set. Software should clear the interrupt status bit in the GCIR register by interrupt service routine.

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System Clock (CK_SYS) Selection

After the system reset occurs, the high speed internal RC oscillator HSI is selected as the system

clock (CK_SYS). The CK_SYS may come from the HSI, HSE, LSE, LSI or PLL output clock and it can be switched from one clock source to another via the System Clock Switch bits (SW) in the

Global Clock Control Register (GCCR). The system will still run under the original clock until the

destination clock gets ready when the SW value is changed. The corresponding clock ready status

bits in the Global Clock Status Register (GCSR) will indicate whether the selected clock is ready to

use or not. The CKCU also contains the clock source status bits in the Clock Source Status Register CKST to indicate which clock is currently used as system clock. If a clock source or the PLL output

clock is used as system clock, it is not possible to stop it. More detail about function of clock enable is described in the following.

▄

If any event in the following occurs, the HSI will be enabled.

● Enable PLL and congure its source clock to HSI. (PLLEN, PLLSRC)

● Enable Clock monitor. (CKMEN)

● Congure clock switch register to HSI. (SW)

● Congure HSI enable register to 1. (HSIEN)

▄

If any event in the following occurs, the HSE will be enabled.

● Enable PLL and congure its source clock to HSE. (PLLEN, PLLSRC)

● Congure clock switch register to HSE. (SW)

● Congure HSE enable register to 1. (HSEEN)

● If any event in the following occurs, the PLL will be enabled.

● Enable USB Enable register. (USBEN)

● Congure clock switch register to PLL. (SW)

● Congure PLL enable register to 1. (PLLEN)

The system clock selection Programming guide is listed in the following.

Clock Control Unit (CKCU)

▄

Enable any source clock which will become system clock or PLL input clock.

▄

Conguring the PLLSRC register after the ready ags of both HSI and HSE are asserted.

▄

Conguring the SW register to change the system clock source will occur after the corresponding ready ag of the clock source is asserted. Note that the system clock will be forced to HSI if the clock monitor is enabled and the PLL output or HSE clock congured as system clock is stuck at 0/1.

HSE Clock Monitor

The HSE clock monitor function is enabled by the HSE Clock Monitor Enable bit CKMEN in the Global Clock Control Register (GCCR). This function should be enabled after the HSE startup delay and be disabled when the HSE oscillator is stopped. Once the HSE failure is detected, the HSE will automatically be disabled. The HSE Clock Stuck Flag CKSF in the Global Clock Interrupt Register, GCIR, will be set and the HSE failure event will be generated if the Clock Fail Interrupt Enable bit CKSIE in the GCIR register is set. This failure interrupt is connected to the Non-Maskable Interrupt NMI. When the HSE oscillator failure occurs, the HSE will be turned off and the system clock will be switched to the HSI automatically by the hardware. If the HSE is used as the clock input of the PLL circuit whose output is used as the system clock, the PLL circuit will also be turned off as well as the HSE when the failure happens.

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Clock Output Capability

The device has the clock output capability to allow the clocks to be output on the specic external output pin CKOUT. The configuration registers of the corresponding GPIO port must be well congured in the Alternate Function I/O section, AFIO, to output the selected clock signal. There

are seven output clock signals to be selected via the device clock output source selection bits CKOUTSRC in the Global Clock Conguration Register GCFGR.

Table 19. CKOUT Clock Source

Register Map

The following table shows the CKCU register and reset value.

Table 20. CKCU Register Map

CKCU Base Address = 0x4008_8000

GCFGR 0x000 Global Clock Conguration Register 0x0000_0302

GCCR 0x004 Global Clock Control Register 0x0000_0803

GCSR 0x008 Global Clock Status Register 0x0000_0028

GCIR 0x00C Global Clock Interrupt Register 0x0000_0000

PLLCFGR 0x018 PLL Conguration Register 0x0000_0000

PLLCR 0x01C PLL Control Register 0x0000_0000

AHBCFGR 0x020 AHB Conguration Register 0x0000_0000

AHBCCR 0x024 AHB Clock Control Register 0x0000_00E5

APBCFGR 0x028 APB Conguration Register 0x0001_0000

APBCCR0 0x02C APB Clock Control Register 0 0x0000_0000

APBCCR1 0x030 APB Clock Control Register 1 0x0000_0000

CKST 0x034 Clock Source Status Register 0x0100_0003

APBPCSR0 0x038 APB Peripheral Clock Selection Register 0 0x0000_0000

APBPCSR1 0x03C APB Peripheral Clock Selection Register 1 0x0000_0000

HSICR 0x040 HSI Control Register

HSIATCR 0x044 HSI Auto Trimming Counter Register 0x0000_0000

LPCR 0x300 Low Power Control Register 0x0000_0000

MCUDBGCR 0x304 MCU Debug Control Register 0x0000_0000

Clock Control Unit (CKCU)

CKOUTSRC [2:0] Clock Source

000 CK_REF = CK_PLL / (CKREFPRE + 1) / 2

001 HCLK / 16

010 CK_SYS / 16

011 CK_HSE / 16

100 CK_HSI / 16

101 CK_LSE

110 CK_LSI

0xXXXX_0000

where X is undened

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Register Descriptions

Global Clock Conguration Register – GCFGR

This register species the clock source for PLL / USART / Watchdog Timer / CKOUT.

Offset: 0x000

Reset value: 0x0000_0302

31 30 29 28 27 26 25 24

LPMOD Reserved

Type/Reset RO 0 RO 0 RO 0

23 22 21 20 19 18 17 16

USBPRE Reserved

Type/Reset RW 0 RW 0

15 14 13 12 11 10 9 8

CKREFPRE

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 1 RW 1

7 6 5 4 3 2 1 0

Reserved

Type/Reset RW 0 RW 1 RW 0

USBSRC

USBPLLSRC

CKOUTSRC

PLLSRC

Clock Control Unit (CKCU)

Bits Field Descriptions

[31:29] LPMOD Lower Power Mode Status

000: When Chip is in running mode 001: When Chip wants to enter Sleep mode 010: When Chip wants to enter Deep Sleep mode 1 011: When Chip wants to enter Deep Sleep mode 2 100: When Chip wants to enter Power Down mode Others: Reserved

Set and reset by hardware.

[23:22] USBPRE USB Clock Prescaler Selection

00: CK_USB = CK_PLL 01: CK_USB = CK_PLL / 2 Others: Reserved

Set and reset by software to control USB clock prescaler setting.

[15:11] CKREFPRE CK_REF Clock Prescaler Selection

CK_REF = CK_PLL / (CKREFPRE + 1) / 2 00000: CK_REF = CK_PLL / 2 00001: CK_REF = CK_PLL / 4 ... 11111: CK_REF = CK_PLL / 64

Set and reset by software to control CK_REF clock prescaler setting.

[10] USBSRC USB Clock Source Selection

0: CK_PLL clock is selected 1: CK_USBPLL clock is selected

Set and reset by software to control USB clock source.

[9] USBPLLSRC USB PLL Clock Source Selection

0: External 4 ~ 16 MHz crystal oscillator clock is selected (HSE) 1: Internal 8 MHz RC oscillator clock is selected (HSI)

Set and reset by software to control USB PLL clock source.

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Bits Field Descriptions

[8] PLLSRC PLL Clock Source Selection

0: External 4 ~ 16 MHz crystal oscillator clock is selected (HSE) 1: Internal 8 MHz RC oscillator clock is selected (HSI)

Set and reset by software to control PLL clock source.

[2:0] CKOUTSRC CKOUT Clock Source Selection

000: CK_REF is selected – Where CK_REF = CK_PLL / (CKREFPRE + 1) / 2 001: (HCLKC / 16) is selected 010: (CK_SYS / 16) is selected 011: (CK_HSE / 16) is selected 100: (CK_HSI / 16) is selected 101: CK_LSE is selected 110: CK_LSI is selected 111: Reserved

Set and reset by software to control CKOUT clock source.

Global Clock Control Register – GCCR

This register species the clock enable bits.

Offset: 0x004

Reset value: 0x0000_0803

Clock Control Unit (CKCU)

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved PSRCEN CKMEN

Type/Reset RW 0 RW 0

15 14 13 12 11 10 9 8

Reserved HSIEN HSEEN PLLEN HSEGAIN

Type/Reset RW 1 RW 0 RW 0 RW 0

7 6 5 4 3 2 1 0

Reserved USBPLLEN SW

Type/Reset RW 0 RW 0 RW 1 RW 1

Bits Field Descriptions

[17] PSRCEN Power Saving Wakeup RC Clock Enable

0: No action 1: Use Internal 8 MHz RC clock (HSI) as system clock after Deep Sleep 1/2

wakeup

The software can set the PSRCEN bit high before entering the Deep Sleep 1 or Deep Sleep 2 mode. In order to reduce the waiting time after a wakeup. When the PSRCEN bit is set to 1, the HSI will be used as the CK_SYS clock source after waking up from the Deep Sleep 1 or Deep Sleep 2 mode. This means that the instruction can be executed before the original CK_SYS source is stable since the HSI clock is provided to CPU. After the original clock source is ready, the CK_SYS clock will automatically be switched back to the original.

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Bits Field Descriptions

[16] CKMEN HSE Clock Monitor Enable

0: Disable External 4 ~ 16 MHz crystal oscillator clock monitor 1: Enable External 4 ~ 16 MHz crystal oscillator clock monitor

When the hardware detects that the HSE clock stuck at a low or high state, the internal hardware will switch the system clock to the internal high speed HSI RC clock.

[11] HSIEN Internal High Speed Clock Enable

0: Internal 8 MHz RC oscillator clock is disabled 1: Internal 8 MHz RC oscillator clock is enabled

Set and reset by software. This bit cannot be reset if HSI clock is used as system clock.

[10] HSEEN External High Speed Clock Enable

0: External 4 ~ 16 MHz crystal oscillator clock is disabled 1: External 4 ~ 16 MHz crystal oscillator clock is enabled

Set and reset by software. This bit cannot be reset if the HSE clock is used as system clock or the PLL input clock.

[9] PLLEN PLL Enable

0: PLL is disabled 1: PLL is enabled

Set and reset by software to enable PLL. This bit cannot be reset if the PLL clock is used as system clock.

[8] HSEGAIN External High Speed Clock Gain Selection

0: HSE is in low gain mode 1: HSE is in high gain mode

[3] USBPLLEN USB PLL Enable

0: USB PLL is disabled 1: USB PLL is enabled

Set and reset by software to enable USB PLL. This bit cannot be reset if the PLL clock is used as system clock.

[2:0] SW System Clock Switch

00x: CK_PLL clock out as system clock 010: CK_HSE as system clock 011: CK_HSI as system clock 110: CK_LSE as system clock 111: CK_LSI as system clock Other: CK_HSI as system clock

This bit eld is set and reset by software to select the CK_SYS clock source. The

HSI oscillator will be forced as the when the HSE oscillator clock failure is detected, where the HSE is used directly or indirectly as system clock, as the clock monitor is enabled. Note: When switching the system clock using the SW bit, the system clock will not be immediately switched and a certain delay is necessary. The system clock source selected by the SW bits can be indicated in the CKSWST bits in the clock source status register CKST to make sure which clock is currently used as the system clock.

Clock Control Unit (CKCU)

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Global Clock Status Register – GCSR

This register indicates the clock ready status.

Offset: 0x008

Reset value: 0x0000_0028

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved

Type/Reset

15 14 13 12 11 10 9 8

Reserved

Type/Reset

7 6 5 4 3 2 1 0

Reserved LSIRDY LSERDY HSIRDY HSERDY PLLRDY USBPLLRDY

Type/Reset RO 1 RO 0 RO 1 RO 0 RO 0 RO 0

Clock Control Unit (CKCU)

Bits Field Descriptions

[5] LSIRDY Internal Low Speed Clock Ready Flag

0: Internal 32 kHz RC oscillator clock is not ready 1: Internal 32 kHz RC oscillator clock is ready

Set by hardware to indicate whether the LSI is stable to be used.

[4] LSERDY External Low Speed Clock Ready Flag

0: External 32,768 Hz crystal oscillator clock is not ready 1: External 32,768 Hz crystal oscillator clock is ready

Set by hardware to indicate whether the LSE is stable to be used.

[3] HSIRDY Internal High Speed Clock Ready Flag

0: Internal 8 MHz RC oscillator clock is not ready 1: Internal 8 MHz RC oscillator clock is ready

Set by hardware to indicate whether the HSI is stable to be used.

[2] HSERDY External High Speed Clock Ready Flag

0: External 4 ~ 16 MHz crystal oscillator clock is not ready 1: External 4 ~ 16 MHz crystal oscillator clock is ready

Set by hardware to indicate whether the HSE is stable to be used.

[1] PLLRDY PLL Clock Ready Flag

0: PLL is not ready 1: PLL is ready

Set by hardware to indicate whether the PLL is stable to be used.

[0] USBPLLRDY USB PLL Clock Ready Flag

0: USB PLL is not ready 1: USB PLL is ready

Set by hardware to indicate whether the USB PLL is stable to be used.

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Global Clock Interrupt Register – GCIR

This register species interrupt enable and ag bits.

Offset: 0x00C

Reset value: 0x0000_0000

31 30 29 28 27 26 25 24

Reserved

Type/Reset

23 22 21 20 19 18 17 16

Reserved LSIRDYIE LSERDYIE HSIRDYIE

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

15 14 13 12 11 10 9 8

Type/Reset

7 6 5 4 3 2 1 0

Reserved LSIRDYF LSERDYF HSIRDYF HSERDYF PLLRDYF

Type/Reset WC 0 WC 0 WC 0 WC 0 WC 0 WC 0 WC 0

HSERDYIE

Reserved

PLLRDYIE

USBPLLRDYIE

USBPLLRDYF

CKSIE

CKSF

Clock Control Unit (CKCU)

Bits Field Descriptions

[22] LSIRDYIE LSI Ready Interrupt Enable

0: Disable LSI ready interrupt 1: Enable LSI ready interrupt

Set and reset by software to enable / disable interrupt caused by LSI stabilization.

[21] LSERDYIE LSE Ready Interrupt Enable

0: Disable LSE ready interrupt 1: Enable LSE ready interrupt

Set and reset by software to enable / disable interrupt caused by LSE stabilization.

[20] HSIRDYIE HSI Ready Interrupt Enable

0: Disable HSI ready interrupt 1: Enable HSI ready interrupt

Set and reset by software to enable / disable interrupt caused by HSI stabilization.

[19] HSERDYIE HSE Ready Interrupt Enable

0: Disable HSE ready interrupt 1: Enable HSE ready interrupt

Set and reset by software to enable / disable interrupt caused by HSE stabilization.

[18] PLLRDYIE PLL Ready Interrupt Enable

0: Disable PLL ready interrupt 1: Enable PLL ready interrupt

Set and reset by software to enable / disable interrupt caused by PLL stabilization.

[17] USBPLLRDYIE USB PLL Ready Interrupt Enable

0: Disable USB PLL ready interrupt 1: Enable USB PLL ready interrupt

Set and reset by software to enable / disable interrupt caused by USB PLL stabilization.

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Bits Field Descriptions

[16] CKSIE Clock Stuck Interrupt Enable

0: Disable clock failure interrupt 1: Enable clock failure interrupt

Set and reset by software to enable or disable the clock failure interrupt caused by clock monitor.

[6] LSIRDYF LSI Ready Interrupt Flag

0: No LSI ready interrupt occurs 1: Clock ready interrupt caused by LSI stabilization

Reset by software (Write 1 clear). Set by hardware when the Internal 32 kHz RC oscillator clock stabilization and LSIRDYDIE is set.

[5] LSERDYF LSE Ready Interrupt Flag

0: No LSE ready interrupt occurs 1: Clock ready interrupt caused by LSE stabilization

Reset by software (Write 1 clear). Set by hardware when the External 32,768 Hz crystal oscillator clock stabilization and LSERDYDIE is set.

[4] HSIRDYF HSI Ready Interrupt Flag

0: No HSI ready interrupt occurs 1: Clock ready interrupt caused by HSI stabilization

Reset by software (Write 1 clear). Set by hardware when the Internal 8 MHz RC oscillator clock stabilization and HSIRDYDIE is set.

[3] HSERDYF HSE Ready Interrupt Flag

0: No HSE ready interrupt occurs 1: Clock ready interrupt caused by HSE stabilization

Reset by software (Write 1 clear). Set by hardware when the External 4 ~ 16 MHz crystal oscillator clock stabilization and HSERDYDIE is set.

[2] PLLRDYF PLL Ready Interrupt Flag

0: No PLL ready interrupt occurs 1: Clock ready interrupt caused by PLL stabilization

Reset by software (Write 1 clear). Set by hardware when the PLL stabilization and PLLRDYDIE is set.

[1] USBPLLRDYF USB PLL Ready Interrupt Flag

0: No USB PLL ready interrupt occurs 1: Clock ready interrupt caused by USB PLL stabilization

Reset by software (Write 1 clear). Set by hardware when the USB PLL stabilization and PLLRDYDIE is set.

[0] CKSF Clock Stuck Interrupt Flag

0: Clock works normally 1: HSE clock is stuck

Reset by software (Write 1 clear). Set by hardware when HSE clock stuck and CKMEN is set.

Clock Control Unit (CKCU)

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PLL Conguration Register – PLLCFGR

This register species the PLL congurations.

Offset: 0x018

Reset value: 0x0000_0000

31 30 29 28 27 26 25 24

Reserved PFBD

Type/Reset RW 0 RW 0 RW 0 RW 0

23 22 21 20 19 18 17 16

PFBD POTD Reserved

Type/Reset RW 0 RW 0 RW 0

15 14 13 12 11 10 9 8

Reserved USBPFBD

Type/Reset RW 0 RW 0 RW 0

7 6 5 4 3 2 1 0

USBPFBD USBPOTD Reserved

Type/Reset RW 0 RW 0 RW 0

Clock Control Unit (CKCU)

Bits Field Descriptions

[27:23] PFBD PLL VCO Output Clock Feedback Divider (B4 ~ B0)

Feedback Divider divides the output clock from VCO of PLL.

[22:21] POTD PLL Output Clock Divider (S1 ~ S0)

[10:7] USBPFBD USB PLL VCO Output Clock Feedback Divider (B3 ~ B0)

Feedback Divider divides the output clock from VCO of PLL.

[6:5] USBPOTD USB PLL Output Clock Divider (S1 ~ S0)

Rev. 1.10 99 of 590 November 28, 2018

32-Bit Arm® Cortex®-M3 MCU HT32F12345

PLL Control Register – PLLCR

This register species the PLL Bypass mode.

Offset: 0x01C

Reset value: 0x0000_0000

31 30 29 28 27 26 25 24

PLLBPS Reserved

Type/Reset RW 0

23 22 21 20 19 18 17 16

Type/Reset

15 14 13 12 11 10 9 8

Type/Reset

7 6 5 4 3 2 1 0

Type/Reset

Clock Control Unit (CKCU)

Reserved

Bits Field Descriptions

[31] PLLBPS PLL Bypass Mode Enable

0: Disable PLL Bypass mode 1: Enable PLL Bypass mode which acts FOUT = FIN

Rev. 1.10 100 of 590 November 28, 2018

Holtek HT32F12345 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Overview

Introduction

Features

Device Information

Block Diagram

Document Conventions

System Architecture

Bus Architecture

Memory Organization

Flash Memory Controller (FMC)

Introduction

Features

Functional Descriptions

Register Map

Register Descriptions

Power Control Unit (PWRCU)

Introduction

Features

Functional Descriptions

Register Map

Register Descriptions

Clock Control Unit (CKCU)

Introduction

Features

Functional Descriptions

Register Map

Register Descriptions