HOLTEK HT1621 User Manual

RAM Mapping 32´4 LCD Controller for I/O MCU

Features

·

Operating voltage: 2.4V~5.2V

·

Built-in 256kHz RC oscillator

·

External 32.768kHz crystal or 256kHz frequency source input

·

Selection of 1/2or1/3 bias, and selection of 1/2or 1/3or1/4 duty LCD applications

·

Internal time base frequency sources

·

Two selectable buzzer frequencies (2kHz/4kHz)

·

Power down command reduces power consumption

·

Built-in time base generator and WDT

·

Time base or WDT overflow output

·

8 kinds of time base/WDT clock sources

·

32´4 LCD driver

General Description

The HT1621 is a 128 pattern (32´4), memory mapping, and multi-function LCD driver. The S/W configuration feature of the HT1621 makes it suitable for multiple LCD applications including LCD modules and display sub

HT1621

·

Built-in 32´4 bit display RAM

·

3-wire serial interface

·

Internal LCD driving frequency source

·

Software configuration feature

·

Data mode and command mode instructions

·

R/W address auto increment

·

Three data accessing modes

·

VLCD pin for adjusting LCD operating voltage

·

HT1621: 48-pin SSOP package HT1621B: 48-pin DIP/SSOP/LQFP package HT1621D: 28-pin SKDIP package HT1621G: Gold bumped chip

systems. Only three or four lines are required for the in terface between the host controller and the HT1621. The HT1621 contains a power down command to re duce power consumption.

-

Selection Table

HT162X HT1620 HT1621 HT1622 HT16220 HT1623 HT1625 HT1626

COM

SEG 32 32 32 32 48 64 48

Built-in Osc.

Crystal Osc.

4 4 888816

¾Ö Ö¾ÖÖÖ

ÖÖ¾ÖÖÖÖ

Rev. 1.30 1 August 6, 2003

Block Diagram

HT1621

O S C O

O S C I

C S

R D

W R

D A T A

V D D

V S S

B Z

Note: CS: Chip selection

: Tone outputs

BZ, BZ

,RD, DATA: Serial interface

WR

COM0~COM3, SEG0~SEG31: LCD outputs

: Time base or WDT overflow output

IRQ

Pin Assignment

S E G 7

S E G 6

S E G 5

S E G 4

S E G 3

S E G 2

S E G 1

S E G 0

D A T A

V S S

O S C O

O S C I

V D D / V L C D

C O M 0

C O M 1

C O M 2

C O M 3

C S

R D

W R

N C

I R Q

B Z

4 8 S S O P - A

1

2

3

4

5

6

7

8

9

1 0

1 1

1 2

1 3

1 4

1 5

1 6

1 7

1 8

1 9

2 0

2 1

2 2

2 3

2 4

H T 1 6 2 1

4 8

S E G 8

4 7

S E G 9

4 6

S E G 1 0

4 5

S E G 1 1

4 4

S E G 1 2

4 3

S E G 1 3

4 2

S E G 1 4

4 1

S E G 1 5

4 0

S E G 1 6

3 9

S E G 1 7

3 8

S E G 1 8

3 7

S E G 1 9

3 6

S E G 2 0

3 5

S E G 2 1

3 4

S E G 2 2

3 3

S E G 2 3

3 2

S E G 2 4

3 1

S E G 2 5

3 0

S E G 2 6

2 9

S E G 2 7

2 8

S E G 2 8

2 7

S E G 2 9

2 6

S E G 3 0

2 5

S E G 3 1

C o n t r o l

a n d T i m i n g C i r c u i t

T o n e F r e q u e n c y

G e n e r a t o r

S E G 7

S E G 6

S E G 5

S E G 4

S E G 3

S E G 2

S E G 1

S E G 0

C S

R D

W R

D A T A

V S S

O S C O

O S C I

V L C D

V D D

I R Q

B Z

C O M 0

C O M 1

C O M 2

C O M 3

4 8 S S O P - A / D I P - A

D i s p l a y R A M

L C D D r i v e r / B i a s C i r c u i t

W a t c h d o g T i m e r

a n d

T i m e B a s e G e n e r a t o r

1

2

3

4

5

6

7

8

9

1 0

1 1

1 2

1 3

1 4

1 5

1 6

1 7

1 8

1 9

2 0

2 1

2 2

2 3

2 4

4 8

4 7

4 6

4 5

4 4

4 3

4 2

4 1

4 0

3 9

3 8

3 7

3 6

3 5

3 4

3 3

3 2

3 1

3 0

2 9

2 8

2 7

2 6

2 5

H T 1 6 2 1 B

S E G 8

S E G 9

S E G 1 0

S E G 1 1

S E G 1 2

S E G 1 3

S E G 1 4

S E G 1 5

S E G 1 6

S E G 1 7

S E G 1 8

S E G 1 9

S E G 2 0

S E G 2 1

S E G 2 2

S E G 2 3

S E G 2 4

S E G 2 5

S E G 2 6

S E G 2 7

S E G 2 8

S E G 2 9

S E G 3 0

S E G 3 1

C O M 0

C O M 3

S E G 0

S E G 3 1

V L C D

I R Q

S E G 5

S E G 3

S E G 1

C S

R D

W R

D A T A

V S S

V L C D

V D D

I R Q

B Z

C O M 0

C O M 1

1

2

3

4

5

6

7

8

9

1 0

1 1

1 2

1 3

1 4

2 8

2 7

2 6

2 5

2 4

2 3

2 2

2 1

2 0

1 9

1 8

1 7

1 6

1 5

H T 1 6 2 1 D

2 8 S K D I P - A

S E G 7

S E G 9

S E G 1 1

S E G 1 3

S E G 1 5

S E G 1 7

S E G 1 9

S E G 2 1

S E G 2 3

S E G 2 5

S E G 2 7

S E G 2 9

S E G 3 1

C O M 2

Rev. 1.30 2 August 6, 2003

HT1621

S E G 1 1

S E G 1 0

S E G 9

S E G 8

S E G 7

S E G 6

S E G 5

S E G 4

S E G 3

S E G 2

S E G 1

S E G 0

Pad Assignment

S E G 0

D A T A

V S S

O S C O

O S C I

V L C D

V D D

4 64 7

4 8

1

C S R D

2

3

W R

4

5

6

7

8

9

I R Q

1 0

1 1

B Z B Z

1 2

S E G 2

S E G 1

1 3

C O M 0

S E G 3

1 4

1 5

C O M 2

C O M 1

S E G 4

4 8 L Q F P - A

1 6

C O M 3

S E G 5

4 34 44 5

4 2

H T 1 6 2 1 B

1 8

1 7

1 9

S E G 2 9

S E G 3 0

S E G 3 1

S E G 7

S E G 6

4 1

2 0

2 1 2 2 2 3 2 4

S E G 2 8

S E G 2 7

S E G 8

3 73 83 94 0

3 6

S E G 1 2

3 5

S E G 1 3

3 4

S E G 1 4

3 3

S E G 1 5

3 2

S E G 1 6

3 1

S E G 1 7

3 0

S E G 1 8

2 9

S G E 1 9

2 8

S E G 2 0

2 7

S E G 2 1

2 6

S E G 2 2

2 5

S E G 2 3

S E G 2 4

S E G 2 5

S E G 2 6

S E G 1 5

S E G 1 4

S E G 1 3

S E G 1 2

S E G 1 1

S E G 1 0

S E G 9

C S

1

4 4

4 54 64 74 8

4 1

4 24 3

3 33 43 53 63 73 83 94 0

2

R D

3

W R

D A T A

V S S

O S C O

O S C I

V L C D

V D D

4

5

6

7

8

9

1 0

I R Q

1 2 1 3

1 1

B Z

1 4 1 5 1 6 1 7 1 8 1 9

C O M 0

C O M 1

Chip size: 127 ´ 131 (mil)

( 0 , 0 )

C O M 2

C O M 3

S E G 2 9

S E G 3 0

S E G 3 1

2

Bump height: 18mm ± 3mm

Min. Bump spacing: 72.36mm

Bump size: 96.042 ´ 96.042mm

2

* The IC substrate should be connected to VDD in the PCB layout artwork.

3 2

S E G 1 6

3 1

S E G 1 7

3 0

S E G 1 8

2 9

S E G 1 9

2 8

S E G 2 0

2 7

S E G 2 1

2 6

S E G 2 2

2 5

S E G 2 3

2 4

S E G 2 4

2 3

S E G 2 5

2 2

S E G 2 6

2 1

S E G 2 7

2 0

S E G 2 8

Rev. 1.30 3 August 6, 2003

HT1621

Pad Coordinates Unit: mil

Pad No. X Y Pad No. X Y

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 6.33 18 12.96 19 19.59 20 58.14 21 58.14 22 58.14 23 58.14 24 58.14

-55.04

-58.52

-58.52 -4.51

-58.52 -11.14

-58.52 -34.76

-58.52 -41.90

-58.52 -49.13

-58.52 -59.08

-44.07 -59.08

-31.58 -59.08

-20.70 -59.08

-13.98 -59.08

-7.05 -59.08

-0.34 -59.08

59.46 25 58.14

22.18 26 58.14

15.56 27 58.14

5.36 28 58.14 29 58.14 1.32 30 58.14 7.95 31 58.14 14.58 32 58.14 21.21 33 55.55 59.46 34 48.92 59.46 35 42.29 59.46 36 35.66 59.46 37 29.03 59.46 38 22.40 59.46 39 15.77 59.46 40 9.14 59.46

-59.08

-58.44

-51.81

-45.18

-38.55

-31.92

41 2.42 59.46 42 43 44 45 46 47 48

-4.21

-10.84

-17.47

-24.10

-30.73

-38.17

-45.39

-25.29

-18.66

-11.94

-5.31

59.46

Pad Description

Pad No. Pad Name I/O Function

Chip selection input with pull-high resistor When the CS

1CS

2RD

3WR

4 DATA I/O Serial data input/output with pull-high resistor

5 VSS

7 OSCI I The OSCI and OSCO pads are connected to a 32.768kHz crystal in order to

6 OSCO O

8 VLCD I LCD power input

9 VDD

10 IRQ

11, 12 BZ, BZ

13~16 COM0~COM3 O LCD common outputs

48~17 SEG0~SEG31 O LCD segment outputs

the HT1621 are disabled. The serial interface circuit is also reset. But if CS

I

is at logic low level and is input to the CS pad, the data and command transmission between the host controller and the HT1621 are all enabled.

READ clock input with pull-high resistor Data in the RAM of the HT1621 are clocked out onthe falling edge of the RD

I

signal. The clocked out data will appear on the DATA line. The host control ler can use the next rising edge to latch the clocked out data.

WRITE clock input with pull-high resistor

I

Data on the DATA line are latched into the HT1621 on the rising edge of the WR

signal.

Negative power supply, ground

¾

generate a system clock. If the system clock comes from an external clock source, the external clock source should be connected to the OSCI pad. But if an on-chip RC oscillator is selected instead, the OSCI and OSCO pads can be left open.

Positive power supply

¾

O Time base or WDT overflow flag, NMOS open drain output

O 2kHz or 4kHz tone frequency output pair

is logic high, the data and command read from or written to

-

Rev. 1.30 4 August 6, 2003

HT1621

Absolute Maximum Ratings

Supply Voltage...........................VSS-0.3V to VSS+5.5V

Input Voltage..............................V

-0.3V to VDD+0.3V

SS

Storage Temperature ............................-50

Operating Temperature...........................-25

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may

cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil ity.

o

Cto125oC

o

Cto75oC

-

D.C. Characteristics

Symbol Parameter

V

Operating Voltage

DD

I

Operating Current

DD1

I

Operating Current

DD2

I

Operating Current

DD3

I

Standby Current

STB

V

Input Low Voltage

IL

V

Input High Voltage

IH

I

DATA, BZ, BZ, IRQ

OL1

I

DATA, BZ, BZ

OH1

I

LCD Common Sink Current

OL2

I

LCD Common Source Current

OH2

I

LCD Segment Sink Current

OL3

I

LCD Segment Source Current

OH3

R

Pull-high Resistor

PH

Test Conditions

V

DD

Conditions

¾¾

3V

No load/LCD ON On-chip RC oscillator

5V

3V

No load/LCD ON Crystal oscillator

5V

3V

No load/LCD ON External clock source

5V

3V

No load, Power down mode

5V

3V

DATA, WR,CS,RD

5V 0

3V

DATA, WR,CS,RD

5V 4.0

=0.3V

V

3V

OL

V

OL

OH

OL

OH

OL

OH

=0.5V

=2.7V

=4.5V

=0.3V

=0.5V

=2.7V

=4.5V

=0.3V

=0.5V

=2.7V

=4.5V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

Min. Typ. Max. Unit

2.4

¾

0

2.4

¾

150 300

300 600

60 120

120 240

100 200

200 400

0.1 5

0.3 10

¾

5.2 V

0.6 V

1.0 V

3.0 V

5.0 V

0.5 1.2

1.3 2.6

-0.4 -0.8 ¾

-0.9 -1.8 ¾

80 150

150 250

-80 -120 ¾mA

-120 -200 ¾mA

60 120

120 200

-40 -70 ¾mA

-70 -100 ¾mA

40 80 150

DATA, WR,CS,RD

5V 30 60 100

Ta=25°C

mA

¾

mA

¾

mA

¾mA

kW

Rev. 1.30 5 August 6, 2003

HT1621

A.C. Characteristics

Symbol Parameter

f

System Clock

SYS1

f

System Clock

SYS2

f

System Clock

SYS3

f

LCD Clock

LCD

t

LCD Common Period

COM

f

Serial Data Clock (WR pin)

CLK1

f

Serial Data Clock (RD pin)

CLK2

f

Tone Frequency

TONE

Serial Interface Reset Pulse

t

CS

Width (Figure 3)

WR,RDInput Pulse Width

t

CLK

(Figure 1)

Rise/Fall Time Serial Data

t

r,tf

Clock Width (Figure 1)

Setup Time for DATA to WR,

t

su

RD

Clock Width (Figure 2)

Hold Time for DATA to WR,RD

t

h

Clock Width (Figure 2)

Setup Time for CS to WR,RD

t

su1

Clock Width (Figure 3)

Hold Time for CS to WR,RD

t

h1

Clock Width (Figure 3)

Test Conditions

V

DD

¾

Conditions

On-chip RC oscillator

Crystal oscillator

External clock source

On-chip RC oscillator

Crystal oscillator

External clock source

n: Number of COM

3V

Duty cycle 50%

5V

3V

Duty cycle 50%

5V

On-chip RC oscillator

¾

CS

¾

Write mode 3.34

3V

Read mode 6.67

Write mode 1.67

5V

Read mode 3.34

¾¾¾

Min. Typ. Max. Unit

32.768

f

SYS1

f

SYS2

f

SYS3

n/f

256

/1024

/128

/1024

LCD

¾

¾¾

2.0 or 4.0

¾

250

¾¾

120

100

Ta=25°C

kHz

¾

kHz

¾

kHz

¾

Hz

¾

Hz

¾

Hz

¾

s

¾

150 kHz

300 kHz

75 kHz

150 kHz

kHz

¾

ns

¾

ms

ns

¾

ns

¾

ns

¾

ns

¾

ns

¾

W R , R D C l o c k

9 0 %

5 0 %

1 0 %

C S

5 0 %

F i r s t C l o c k L a s t C l o c k

t

f

t

C L K

Figure 1

t

S U 1

5 0 %

t

r

t

C L K

t

C S

t

h 1

V

G N D

V

G N D

V

G N D

D D

W R , R D C l o c k

D B

5 0 %

t

S U

Figure 2

V a l i d D a t a

V

D D

t

h

5 0 %

G N D

V

G N D

D D

Figure 3

Rev. 1.30 6 August 6, 2003

HOLTEK HT1621 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

General Description

Selection Table

Block Diagram

Pin Assignment

Pad Assignment

Pad Coordinates Unit: mil

Pad Description

Absolute Maximum Ratings

D.C. Characteristics

A.C. Characteristics