Holtek BS86DH12C User Manual

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High Voltage Touch A/D Flash MCU with HVIO

BS86DH12C

Revision: V1.00 Date: October 26, 2018

BS86DH12C

High Voltage Touch A/D Flash MCU with HVIO

Table of Contents

Features ................................................................................................................. 7

CPU Features ...............................................................................................................................7

Peripheral Features ....................................................................................................................... 7

General Description .............................................................................................. 8

Block Diagram ....................................................................................................... 9

Pin Assignment ..................................................................................................... 9

Pin Descriptions ................................................................................................. 11

Absolute Maximum Ratings ............................................................................... 14

D.C. Electrical Characteristics ........................................................................... 15

Operating Voltage Characteristics ...............................................................................................15

Operating Current Characteristics ...............................................................................................15

Standby Current Characteristics .................................................................................................16

A.C. Characteristics ............................................................................................ 16

High Speed Internal Oscillator – HIRC – Frequency Accuracy ...................................................16

Internal Low Speed Oscillator Characteristics – LIRC ................................................................17

External Low Speed Oscillator Characteristics – LXT ................................................................. 17

Operating Frequency Characteristic Curves ............................................................................... 17

System Start Up Time Characteristics ........................................................................................18

Input/Output Characteristics ............................................................................. 19

Memory Characteristics ..................................................................................... 19

LVD/LVR Electrical Characteristics ................................................................... 20

A/D Converter Electrical Characteristics .......................................................... 20

Internal Reference Voltage Characteristics ...................................................... 21

High Voltage I/O Electrical Characteristics ...................................................... 21

Voltage Detector Electrical Characteristics .................................................................................21

High Voltage I/O Other Electrical Characteristics ........................................................................22

Low Dropout Regulator Electrical Characteristics .......................................... 22

OCP Electrical Characteristics .......................................................................... 24

OVP Electrical Characteristics ..........................................................................24

Power-on Reset Characteristics ........................................................................ 25

System Architecture ........................................................................................... 25

Clocking and Pipelining ............................................................................................................... 25

Program Counter ......................................................................................................................... 26

Stack ...........................................................................................................................................27

Arithmetic and Logic Unit – ALU .................................................................................................27

Flash Program Memory ...................................................................................... 28

Structure ...................................................................................................................................... 28

Special Vectors ...........................................................................................................................28

Rev. 1.00 2 October 26, 2018 Rev. 1.00 3 October 26, 2018

BS86DH12C High Voltage Touch A/D Flash MCU with HVIO

Look-up Table .............................................................................................................................. 28

Table Program Example .............................................................................................................. 29

In Circuit Programming – ICP .....................................................................................................30

On-Chip Debug Support – OCDS ...............................................................................................31

Data Memory ....................................................................................................... 31

Structure ...................................................................................................................................... 31

Data Memory Addressing ............................................................................................................ 32

General Purpose Data Memory ..................................................................................................32

Special Purpose Data Memory ...................................................................................................32

Special Function Register Description ............................................................. 34

Indirect Addressing Registers – IAR0, IAR1, IAR2 .....................................................................34

Memory Pointers – MP0, MP1L/MP1H, MP2L/MP2H ................................................................. 34

Accumulator – ACC .................................................................................................................... 35

Program Counter Low Register – PCL .......................................................................................36

Look-up Table Registers – TBLP, TBHP, TBLH .......................................................................... 36

Status Register – STATUS .........................................................................................................36

EEPROM Data Memory ....................................................................................... 38

EEPROM Data Memory Structure ..............................................................................................38

EEPROM Registers ....................................................................................................................38

Reading Data from the EEPROM ...............................................................................................39

Writing Data to the EEPROM ......................................................................................................40

EEPROM Interrupt ......................................................................................................................40

Programming Considerations ...................................................................................................... 40

Oscillators ...........................................................................................................42

Oscillator Overview .....................................................................................................................42

System Clock Congurations ...................................................................................................... 42

Internal High Speed RC Oscillator – HIRC .................................................................................43

Internal 32kHz Oscillator – LIRC ................................................................................................. 43

External 32.768 kHz Crystal Oscillator – LXT .............................................................................43

Operating Modes and System Clocks .............................................................. 45

System Clocks ............................................................................................................................45

System Operation Modes ............................................................................................................ 46

Control Registers ........................................................................................................................47

Operating Mode Switching .......................................................................................................... 49

Standby Current Considerations ................................................................................................. 53

Wake-up ......................................................................................................................................53

Watchdog Timer .................................................................................................. 54

Watchdog Timer Clock Source .................................................................................................... 54

Watchdog Timer Control Register ............................................................................................... 54

Watchdog Timer Operation ......................................................................................................... 55

Reset and Initialisation ....................................................................................... 56

Reset Functions ..........................................................................................................................56

Reset Initial Conditions ...............................................................................................................59

BS86DH12C

High Voltage Touch A/D Flash MCU with HVIO

Input/Output Ports .............................................................................................. 63

Pull-high Resistors ......................................................................................................................63

Port A Wake-up ...........................................................................................................................64

I/O Port Control Registers ........................................................................................................... 64

I/O Port Source Current Selection ...............................................................................................64

I/O Port Sink Current Selection ................................................................................................... 66

Pin-shared Functions ..................................................................................................................68

I/O Pin Structures ........................................................................................................................ 72

Programming Considerations ...................................................................................................... 72

High Voltage I/O Port .......................................................................................... 73

High Voltage I/O Registers ..........................................................................................................74

Voltage Detector ..........................................................................................................................75

Short-circuit Protection Function ................................................................................................. 76

Low Dropout Regulator – LDO .......................................................................... 77

Timer Modules – TM ...........................................................................................77

Introduction .................................................................................................................................77

TM Operation ..............................................................................................................................77

TM Clock Source ......................................................................................................................... 78

TM Interrupts ............................................................................................................................... 78

TM External Pins ......................................................................................................................... 78

Programming Considerations ...................................................................................................... 79

Compact Type TM – CTM ................................................................................... 80

Compact Type TM Operation ......................................................................................................80

Compact Type TM Register Description......................................................................................81

Compact Type TM Operation Modes ..........................................................................................84

Periodic Type TM – PTM ..................................................................................... 90

Periodic TM Operation ................................................................................................................90

Periodic Type TM Register Description .......................................................................................90

Periodic Type TM Operation Modes ............................................................................................95

Analog to Digital Converter ............................................................................. 104

A/D Overview ............................................................................................................................104

A/D Converter Register Description .......................................................................................... 105

A/D Converter Reference Voltage .............................................................................................107

A/D Converter Input Signals ...................................................................................................... 108

A/D Converter Operation ........................................................................................................... 108

Conversion Rate and Timing Diagram ......................................................................................109

Summary of A/D Conversion Steps ...........................................................................................110

Programming Considerations .................................................................................................... 111

A/D Transfer Function ............................................................................................................... 111

A/D Programming Examples ..................................................................................................... 112

Touch Key Function ......................................................................................... 114

Touch Key Structure .................................................................................................................. 114

Touch Key Register Denition ................................................................................................... 114

Rev. 1.00 4 October 26, 2018 Rev. 1.00 5 October 26, 2018

BS86DH12C High Voltage Touch A/D Flash MCU with HVIO

Touch Key Interrupt ................................................................................................................... 120

Programming Considerations .................................................................................................... 120

Over Current Protection – OCP ....................................................................... 121

Over Current Protection Operation ...........................................................................................121

Over Current Protection Registers ............................................................................................ 122

Input Voltage Range ..................................................................................................................124

Input Offset Calibration .............................................................................................................125

Over Voltage Protection – OVP ........................................................................ 126

Over Voltage Protection Operation ...........................................................................................126

Over Voltage Protection Registers ............................................................................................127

Comparator Input Offset Cancellation ......................................................................................128

I2C Interface ....................................................................................................... 129

I2C Interface Operation .............................................................................................................. 129

I2C Registers .............................................................................................................................131

I2C Bus Communication ............................................................................................................133

I2C Time-out Control ..................................................................................................................137

UART Interface .................................................................................................. 138

UART External Pins ..................................................................................................................139

UART Data Transfer Scheme....................................................................................................139

UART Status and Control Registers..........................................................................................139

Baud Rate Generator ................................................................................................................ 145

UART Setup and Control...........................................................................................................145

UART Transmitter...................................................................................................................... 146

UART Receiver .........................................................................................................................148

Managing Receiver Errors ........................................................................................................149

UART Interrupt Structure...........................................................................................................150

UART Power Down and Wake-up ............................................................................................. 151

Low Voltage Detector – LVD ............................................................................ 152

LVD Register ............................................................................................................................. 152

LVD Operation ........................................................................................................................... 153

Interrupts ........................................................................................................... 154

Interrupt Registers ..................................................................................................................... 154

Interrupt Operation .................................................................................................................... 158

External Interrupt ....................................................................................................................... 159

Touch Key Module Interrupt ......................................................................................................160

Time Base Interrupt ...................................................................................................................160

Multi-function Interrupts ............................................................................................................. 161

I2C Interrupt ............................................................................................................................... 161

UART Transfer Interrupt ............................................................................................................162

LVD Interrupt ............................................................................................................................. 162

A/D Converter Interrupt ............................................................................................................. 162

EEPROM Interrupt ....................................................................................................................162

Over Voltage Protection Interrupt ..............................................................................................163

BS86DH12C

High Voltage Touch A/D Flash MCU with HVIO

Over Current Protection Interrupt .............................................................................................. 163

High Voltage Short Circuit Interrupt ...........................................................................................163

TM Interrupts ............................................................................................................................. 163

Interrupt Wake-up Function .......................................................................................................163

Programming Considerations .................................................................................................... 164

Conguration Options ...................................................................................... 164

Application Circuits .......................................................................................... 165

Instruction Set ................................................................................................... 166

Introduction ...............................................................................................................................166

Instruction Timing ......................................................................................................................166

Moving and Transferring Data ...................................................................................................166

Arithmetic Operations ................................................................................................................ 166

Logical and Rotate Operation ...................................................................................................167

Branches and Control Transfer .................................................................................................167

Bit Operations ...........................................................................................................................167

Table Read Operations .............................................................................................................167

Other Operations ....................................................................................................................... 167

Instruction Set Summary ................................................................................. 168

Table Conventions .....................................................................................................................168

Extended Instruction Set ........................................................................................................... 170

Instruction Denition ........................................................................................ 172

Extended Instruction Denition .................................................................................................181

Package Information ........................................................................................ 188

20-pin SOP (300mil) Outline Dimensions .................................................................................189

28-pin SOP (300mil) Outline Dimensions .................................................................................190

44-pin LQFP (10mm×10mm) (FP2.0mm) Outline Dimensions .................................................191

Rev. 1.00 6 October 26, 2018 Rev. 1.00 7 October 26, 2018

BS86DH12C High Voltage Touch A/D Flash MCU with HVIO

Features

CPU Features

• Operating voltage

♦

=8/12/16MHz, using internal LDO: VDD=5V (Typ.)

SYS

♦

High Voltage Driver: VCC=7V~10V

• Up to 0.25μs instruction cycle with 16MHz system clock at VDD=5V

• Power down and wake-up functions to reduce power consumption

• Oscillator types

♦

Internal High Speed 8/12/16MHz RC – HIRC

♦

Internal Low Speed 32kHz RC – LIRC

♦

External Low Speed 32.768kHz Crystal – LXT

• Multi-mode operation: FAST, SLOW, IDLE and SLEEP

• Fully integrated internal oscillators require no external components

• All instructions executed in 1~3 instruction cycles

• Table read instructions

• 115 powerful instructions

• 8-level subroutine nesting

• Bit manipulation instruction

Peripheral Features

• Flash Program Memory: 8K×16

• Data Memory: 512×8

• True EEPROM Memory: 64×8

• 12 touch key functions – fully integrated without requiring external components

• Watchdog Timer function

• 22 bidirectional I/O lines

• 6 bidirectional High Voltage I/O lines with short circuit protection function

• Programmable I/O port source current and sink current for LED driving applications

• Single external interrupt line shared with I/O pin

• Multiple Timer Modules for time measurement, input capture, compare match output or PWM

output or single pulse output function

• Single Time-Base function for generation of xed time interrupt signals

• 8 external channels 12-bit resolution A/D converter with internal reference voltage V

• Over Current Protection function – OCP

• Over Voltage Protection function – OVP

• Internal 5V LDO with driving current of up to 500mA, providing power supply for MCU and

external components

• I2C interface

• Fully-duplex Universal Asynchronous Receiver and Transmitter Interface – UART

• Low voltage reset function

• Low voltage detect function

• Package types: 20/28-pin SOP, 44-pin LQFP

General Description

The device is a Flash Memory type 8-bit high performance RISC architecture microcontroller with

fully integrated touch key functions. With all touch key functions provided internally and with the

convenience of Flash Memory multi-programming features, the device has all the features to offer

designers a reliable and easy means of implementing touch keys within their products applications.

The touch key functions are fully integrated, completely eliminating the need for external

components. In addition to the Flash program memory, other memory includes an area of RAM

Data Memory as well as an area of true EEPROM memory for storage of non-volatile data such as

serial numbers, calibration data etc. Analog feature includes a multi-channel 12-bit A/D converter

and an internal LDO for power supply. Protective features such as an internal Watchdog Timer, Low

Voltage Reset, Low Voltage Detector, Over Current Protection and Over Voltage Protection coupled

with excellent noise immunity and ESD protection ensure that reliable operation is maintained in

hostile electrical environments.

A full choice of external low, internal high and low speed oscillators are provided including fully

integrated system oscillators which require no external components for its implementation. The

ability to operate and switch dynamically between a range of operating modes using different

clock sources gives users the ability to optimise microcontroller operation and minimise power

consumption. Easy communication with the outside world is provided using the internal I2C and

UART interfaces, while the inclusion of exible I/O programming features, Time-Base function,

Timer Modules and many other features further enhance device functionality and exibility.

This device contains programmable I/O port source current and sink current functions which are

used to implement LED driving function. The High Voltage I/O function specic to high voltage and

high current applications is also fully integrated within the device.

The touch key device will find excellent use in a huge range of modern Touch Key product

applications such as sensor signal processing, household appliances, health care products, industrial

control, consumer products, subsystem control to name but a few.

BS86DH12C

High Voltage Touch A/D Flash MCU with HVIO

Rev. 1.00 8 October 26, 2018 Rev. 1.00 9 October 26, 2018

BS86DH12C High Voltage Touch A/D Flash MCU with HVIO

Block Diagram

VLDO

VCC1

HVSS

VCC2

PD0~PD5

VDD/AVDD/

VLDO

VSS/AVSS/

IOVSS/HVSS

Reset Circuit

Pin-Shared

With Port C

Time Base

XT1 XT2

Pin-Shared With Port A

Port D Driver

Interrupt

Controller

8/12/16MHz

High Voltage Analog Peripherals

INT

: Bus Entry : Pin-Shared Node

8K × 16

EEPROM

Watchdog

LIRC

32kHz

LXT

HIRC

Clock System

LDO (5V)

HV I/O

ROM

64 × 8

Timer

HT8 MCU Core

RAM

512 × 8

Stack

8-Level

LVR/LVD

MUX

Bus

Analog to Digital Converter

Over Current Protection Circuit

Over Voltage Protection Circuit

Touch Key Module 2

Touch Key Module 1

Touch Key Module 0

C to F Circuit

Touch Key Function

Timers

I2C

12-bit

ADC

Analog Peripherals

I/O

UART

Digital Peripherals

MUX

8-bit DAC

V V V

Pin-Shared

CC1O

CC2O

OCPAO

Function

OPA

Pin-Shared

With Port A, B & C

Port A Driver

Port B Driver

Port C Driver

VREF

Pin-Shared With Port A

AN0~AN7

Pin-Shared

With Port A & B

OCPAO

OCPI

Pin-Shared

With Port A & B

OVPI0

OVPI1

Pin-Shared

With Port A, B & C

KEY1~KEY12

PA0~PA7

PB0~PB7

PC0~PC5

Pin Assignment

PB0/RX/CTCK0/OCPI/KEY1 PA6/CTCK1/PTPI/CTP0/PTPB/XT1

PA1/PTCK/SCL/OVPI1/KEY3

PA3/PTPI/SDA/VREF/KEY4 PA0/RX/CTP1/OCPVR/ICPDA/OCDSDA

PD3 VCC2

PD2 VCC1

PD1 VDD/VLDO/AVDD

PD0 PA7/CTCK0/PTCK/PTP/XT2

PA4/AN0/KEY5

PA5/AN1/KEY6 PB2/SCL/AN6/KEY9

VSS/AVSS/IOVSS/HVSSPB1/TX/CTCK1/OVPI0/KEY2

PA2/TX/CTP1B/OCPI/ICPCK/OCDSCK

PB3/SDA/AN7/KEY10

BS86DH12C/BS86DHV12C

20 SOP-A

BS86DH12C

High Voltage Touch A/D Flash MCU with HVIO

PB0/RX/CTCK0/OCPI/KEY1

PB1/TX/CTCK1/OVPI0/KEY2

PA1/PTCK/SCL/OVPI1/KEY3

PA3/PTPI/SDA/VREF/KEY4

PA4/AN0/KEY5

PA5/AN1/KEY6

PB4/CTP0/AN2/KEY7

PB5/CTP0B/AN3/KEY8

PB6/CTP1/AN4/OCPAO

PB7/CTP1B/AN5/OVPCOUT

NC NC NC

PB0/RX/CTCK0/OCPI/KEY1 PB1/TX/CTCK1/OVPI0/KEY2 PA1/PTCK/SCL/OVPI1/KEY3

PA3/PTPI/SDA/VREF/KEY4

PA4/AN0/KEY5 PA5/AN1/KEY6

PB4/CTP0/AN2/KEY7

PB5/CTP0B/AN3/KEY8

PD3

PD2

PD1

PD0

BS86DH12C/BS86DHV12C

28 SOP-A

VCC2

PD0

PD1

1 2 3 4 5

BS86DH12C/BS86DHV12C

6 7 8 9 10 11

44 LQFP-A

12 13 14 15 16 1718 19 20 21 22

4 /

O U T

PB3/SDA/AN7/KEY10

S C L /

A N 6 /

K E Y 9

VCC2

VCC1

VDD/VLDO/AVDD

PA7/CTCK0/PTCK/PTP/XT2

PA6/CTCK1/PTPI/CTP0/PTPB/XT1

VSS/AVSS/IOVSS/HVSS

PC3/CTP0/SDA/TX

PC2/CTP1/SCL/RX

PA2/TX/CTP1B/OCPI/ICPCK/OCDSCK

PA0/RX/CTP1/OCPVR/ICPDA/OCDSDA

PC1/INT/PTPB/OVPI1/KEY12

PC0/PTP/OVPI0/KEY11

PB3/SDA/AN7/KEY10

PB2/SCL/AN6/KEY9

3435363738394041424344

VDD/VLDO/AVDD

PA7/CTCK0/PTCK/PTP/XT2

PA6/CTCK1/PTPI/CTP0/PTPB/XT1

VSS/AVSS/IOVSS/HVSS

PC3/CTP0/SDA/TX

PC2/CTP1/SCL/RX

PA2/TX/CTP1B/OCPI/ICPCK/OCDSCK

PA0/RX/CTP1/OCPVR/ICPDA/OCDSDA

PC1/INT/PTPB/OVPI1/KEY12

PC0/PTP/OVPI0/KEY11

Note: 1. If the pin-shared pin functions have multiple outputs, the desired pin-shared function is determined by the

corresponding software control bits.

2. The OCDSDA and OCDSCK pins are supplied for the OCDS dedicated pins and as such only available for the BS86DHV12C device which is the OCDS EV chip for the BS86DH12C device.

3. For less pin-count package types there will be unbonded pins which should be properly congured to

avoid unwanted current consumption resulting from floating input conditions. Refer to the “Standby Current Considerations” and “Input/Output Ports” sections.

Rev. 1.00 10 October 26, 2018 Rev. 1.00 11 October 26, 2018

BS86DH12C High Voltage Touch A/D Flash MCU with HVIO

Pin Descriptions

With the exception of the power pins, all pins on the device can be referenced by their Port name, e.g.

PA0, PA1 etc., which refer to the digital I/O function of the pins. However these Port pins are also

shared with other function such as the Touch Key function, Timer Module pins etc. The function of

each pin is listed in the following table, however the details behind how each pin is congured is

contained in other sections of the datasheet.

As the Pin Description table shows the situation for the package with the most pins, not all pins in

the table will be available on smaller package sizes.

Pin Name Function OPT I/T O/T

PA0/RX/CTP1/ OCPVR/ICPDA/ OCDSDA

PA1/PTCK/SCL/ OVPI1/KEY3

PA2/TX/CTP1B/ OCPI/ICPCK/ OCDSCK

PA3/PTPI/SDA/ VREF/KEY4

PA4/AN0/KEY5

PA0

CTP1 PAS0 — CMOS CTM1 output

OCPVR PAS0 AN — OCP D/A converter reference voltage input

ICPDA — ST CMOS ICP data/address

OCDSDA — ST CMOS OCDS data/address, for EV chip only

PA1

PTCK

SCL

OVPI1 PAS0 AN — OVP input 1

KEY3 PAS0 NSI — Touch key input

PA2

TX PAS0 — CMOS UART data transmit pin

CTP1B PAS0 — CMOS CTM1 inverted output

OCPI PAS0 AN — OCP input

ICPCK — ST — ICP clock

OCDSCK — ST — OCDS clock, for EV chip only

PA3

PTPI

SDA

VREF PAS0 AN — A/D converter external input channel

KEY4 PAS0 NSI — Touch key input

PA4

AN0 PAS1 AN — A/D converter external input channel

KEY5 PAS1 NSI — Touch key input

PAPU

PAWU

PAS0

IFS0

PAPU

PAWU

PAS0

IFS1

PAS0

IFS0

PAPU

PAWU

PAS0

PAPU

PAWU

PAS0

IFS1

PAS0

IFS0

PAPU

PAWU

PAS1

ST CMOS

ST — UART data receive pin

ST CMOS

ST — PTM clock input

ST NMOS I2C clock line

ST CMOS

ST — PTM capture input

ST NMOS I2C data line

ST CMOS

General purpose I/O. Register enabled pull-up and wake-up

Description

BS86DH12C

High Voltage Touch A/D Flash MCU with HVIO

Pin Name Function OPT I/T O/T

PAPU

PAWU

PAS1

PAPU

PAWU

PAS1

IFS1

PAS1

IFS1

PAPU

PAWU

PAS1

IFS1

PAS1

IFS1

PBPU PBS0

PBS0

IFS0

PBS0

IFS1

PBPU PBS0

PBS0

IFS1

PBPU PBS0

PBS0

IFS0

PBPU PBS0

PBS0

IFS0

PA5/AN1/KEY6

PA6/CTCK1/PTPI/ CTP0/PTPB/XT1

PA7/CTCK0/PTCK/ PTP/XT2

PB0/RX/CTCK0/ OCPI/KEY1

PB1/TX/CTCK1/ OVPI0/KEY2

PB2/SCL/AN6/KEY9

PB3/SDA/AN7/ KEY10

PA5

AN1 PAS1 AN — A/D converter external input channel

KEY6 PAS1 NSI — Touch key input

PA6

CTCK1

PTPI

CTP0 PAS1 — CMOS CTM0 output

PTPB PAS1 — CMOS PTM inverted output

XT1 PAS1 LXT — LXT oscillator pin

PA7

CTCK0

PTCK

PTP PAS1 — CMOS PTM output

XT2 PAS1 — LXT LXT oscillator pin

PB0

CTCK0

OCPI PBS0 AN — OCP input

KEY1 PBS0 NSI — Touch key input

PB1

TX PBS0 — CMOS UART data transmit pin

CTCK1

OVPI0 PBS0 AN — OVP input 0

KEY2 PBS0 NSI — Touch key input

PB2

SCL

AN6 PBS0 AN — A/D converter external input channel

KEY9 PBS0 NSI — Touch key input

PB3

SDA

AN7 PBS0 AN — A/D converter external input channel

KEY10 PBS0 NSI — Touch key input

Description

ST CMOS

ST — CTM1 clock input

ST — PTM capture input

ST CMOS

ST — CTM0 clock input

ST — PTM clock input

ST CMOS General purpose I/O. Register enabled pull-up

ST — UART data receive pin

ST — CTM0 clock input

ST CMOS General purpose I/O. Register enabled pull-up

ST — CTM1 clock input

ST CMOS General purpose I/O. Register enabled pull-up

ST NMOS I2C clock line

ST CMOS General purpose I/O. Register enabled pull-up

ST NMOS I2C data line

General purpose I/O. Register enabled pull-up and wake-up

Rev. 1.00 12 October 26, 2018 Rev. 1.00 13 October 26, 2018

BS86DH12C High Voltage Touch A/D Flash MCU with HVIO

Pin Name Function OPT I/T O/T

PB4

PB4/CTP0/AN2/ KEY7

PB5/CTP0B/AN3/ KEY8

PB6/CTP1/AN4/ OCPAO

PB7/CTP1B/AN5/ OVPCOUT

PC0/PTP/OVPI0/ KEY11

PC1/INT/PTPB/ OVPI1/KEY12

PC2/CTP1/SCL/RX

PC3/CTP0/SDA/TX

PC4~PC5 PC4~PC5 PCPU ST CMOS General purpose I/O. Register enabled pull-up

PD0~PD5 PD0~PD5 — ST CMOS High voltage I/O port

VDD/AVDD/VLDO

CTP0 PBS1 — CMOS CTM0 output

AN2 PBS1 AN — A/D converter external input channel

KEY7 PBS1 NSI — Touch key input

PB5

CTP0B PBS1 — CMOS CTM0 inverted output

AN3 PBS1 AN — A/D converter external input channel

KEY8 PBS1 NSI — Touch key input

PB6

CTP1 PBS1 — CMOS CTM1 output

AN4 PBS1 AN — A/D converter external input channel

OCPAO PBS1 AN — OCP operational amplier output

PB7

CTP1B PBS1 — CMOS CTM1 inverted output

AN5 PBS1 AN — A/D converter external input channel

OVPCOUT PBS1 — CMOS OVP comparator output

PC0

PTP PCS0 — CMOS PTM output

OVPI0 PCS0 AN — OVP input 0

KEY11 PCS0 NSI — Touch key input

PC1

INT

PTPB PCS0 — CMOS PTM inverted output

OVPI1 PCS0 AN — OVP input 1

KEY12 PCS0 NSI — Touch key input

PC2

CTP1 PCS0 — CMOS CTM1 output

SCL

PC3

CTP0 PCS0 — CMOS CTM0 output

SDA

TX PCS0 — CMOS UART data transmit pin

VDD — PWR — Digital positive power supply

AVDD — PWR — Analog positive power supply

VLDO — — PWR LDO output voltage

PBPU

PBS1

PBPU

PBS1

PBPU

PBS1

PBPU

PBS1

PCPU

PCS0

PCPU

PCS0

INTC0

INTEG

PCPU

PCS0

IFS0

PCS0

IFS0

PCPU

PCS0

IFS0

ST CMOS General purpose I/O. Register enabled pull-up

ST — External interrupt input

ST CMOS General purpose I/O. Register enabled pull-up

ST NMOS I2C clock line

ST — UART data receive pin

ST CMOS General purpose I/O. Register enabled pull-up

ST NMOS I2C data line

Description

BS86DH12C

High Voltage Touch A/D Flash MCU with HVIO

Pin Name Function OPT I/T O/T

VSS — PWR — Digital negative power supply, ground

VSS/AVSS/IOVSS/ HVSS

VCC1 VCC1 — PWR —

VCC2 VCC2 — PWR —

NC NC — — — Unused

AVSS — PWR — Analog negative power supply, ground

IOVSS — PWR — I/O port negative power supply, ground

HVSS — PWR — High voltage negative power supply, ground

Provides high voltage positive power supply for LDO input

Provides high voltage positive power supply for High Voltage I/O and Level Shifter

Legend: I/T: Input type; O/T: Output type;

OPT: Optional by register selection;

PWR: Power; ST: Schmitt Trigger input;

CMOS: CMOS output; NMOS: NMOS output;

AN: Analog signal; NSI: Non-standard input;

LXT: Low frequency crystal oscillator.

Absolute Maximum Ratings

Supply Voltage (VCC) ................................................................................................VSS-0.3V to 10.0V

Supply Voltage (VDD) .........................................................................................VSS-0.3V to VSS+6.0V

High Voltage Input Voltage ............................................................................... VSS-0.3V to VCC+0.3V

Input Voltage .....................................................................................................VSS-0.3V to VDD+0.3V

Storage Temperature .....................................................................................................-50°C to 125°C

Operating Temperature ................................................................................................... -40°C to 85°C

High Voltage IOH Total ..............................................................................................................-150mA

IOH Total ......................................................................................................................................-80mA

High Voltage IOL Total ............................................................................................................... 150mA

IOL Total ....................................................................................................................................... 80mA

Total Power Dissipation ........................................................................................................... 500mW

Description

Note: These are stress ratings only. Stresses exceeding the range specified under “Absolute

Maximum Ratings” may cause substantial damage to this device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.

Rev. 1.00 14 October 26, 2018 Rev. 1.00 15 October 26, 2018

BS86DH12C High Voltage Touch A/D Flash MCU with HVIO

D.C. Electrical Characteristics

For data in the following tables, note that factors such as oscillator type, operating voltage, operating

frequency, pin load conditions, temperature and program instruction type, can all exert an inuence

on the measured values.

Operating Voltage Characteristics

Ta=25°C

Symbol Parameter Test Conditions Min. Typ. Max. Unit

=8MHz 4.5 — 5.5

SYS=fHIRC

Operating Voltage – HIRC

Operating Voltage – LIRC f

Operating Voltage – LXT f

Operating Current Characteristics

Symbol Parameter

SLOW Mode – LIRC 5V

SLOW Mode – LXT 5V

FAST Mode – HIRC 5V

SYS=fHIRC

SYS=fLIRC

SYS=fLXT

Test Conditions

SYS=fLIRC

consumption included

SYS=fLXT

consumption included

SYS=fHIRC

consumption included

SYS=fHIRC

consumption included

SYS=fHIRC

consumption included

=12MHz 4.5 — 5.5

=16MHz 4.5 — 5.5

=32kHz 4.5 — 5.5 V

=32.768kHz 4.5 — 5.5 V

Ta=25°C

Conditions

=32kHz, LDO current

=32768Hz, LDO current

=8MHz, LDO current

=12MHz, LDO current

=16MHz, LDO current

Min. Typ. Max. Unit

— 180 200 μA

— 1.6 2.4

— 2.4 3.6

— 6.0 9.0

Note: When using the characteristic table data, the following notes should be taken into consideration:

1. Any digital input is set in a non-oating condition.

2. All measurements are taken under conditions of no load and with all peripherals in an off state.

3. There are no DC current paths.

4. All Operating Current values are measured using a continuous NOP instruction program loop.

BS86DH12C

High Voltage Touch A/D Flash MCU with HVIO

Standby Current Characteristics

Ta=25°C, unless otherwise specied

Symbol Parameter

SLEEP Mode 5V

IDLE0 Mode – LIRC 5V

IDLE0 Mode – LXT 5V

STB

IDLE1 Mode – HIRC 5V

Test Conditions

Conditions

WDT on, LDO current consumption included

on, LDO current

SUB

consumption included

on, LDO current

SUB

consumption included

on, f

SUB

=8MHz, LDO

SYS

current consumption included

on, f

SUB

=12MHz, LDO

SYS

current consumption included

on, f

SUB

=16MHz, LDO

SYS

current consumption included

Min. Typ. Max.

— 160 200 210 μA

— 165 200 215 μA

— 1.0 1.8 2.0

— 1.5 2.6 3.0

— 2.0 3.5 4.0

Note: When using the characteristic table data, the following notes should be taken into consideration:

1. Any digital input is set in a non-oating condition.

2. All measurements are taken under conditions of no load and with all peripherals in an off state.

3. There are no DC current paths.

4. All Standby Current values are taken after a HALT instruction executed thus stopping all instruction execution.

Max.

@85°C

Unit

A.C. Characteristics

For data in the following tables, note that factors such as oscillator type, operating voltage, operating

frequency and temperature etc., can all exert an inuence on the measured values.

High Speed Internal Oscillator – HIRC – Frequency Accuracy

During the program writing operation the writer will trim the HIRC oscillator at a user selected

HIRC frequency and user selected voltage of 5V.

Symbol Parameter

8MHz Writer Trimmed HIRC Frequency

HIRC

12MHz Writer Trimmed HIRC Frequency

16MHz Writer Trimmed HIRC Frequency

Note: 1. The 5V values for VDD are provided as this is the xed voltage at which the HIRC frequency is trimmed

by the writer.

2. The row below the 5V trim voltage row is provided to show the values for the full VDD range operating

voltage. It is recommended that the trim voltage is xed at 5V for application voltage ranges from 3.3V

to 5.5V.

Test Conditions

4.5V~5.5V

Temp.

Min. Typ. Max. Unit

25°C -1% 8 +1%

-40°C~85°C -2% 8 +2%

25°C -2.5% 8 +2.5%

-40°C~85°C -3% 8 +3%

25°C -1% 12 +1%

-40°C~85°C -2% 12 +2%

25°C -2.5% 12 +2.5%

-40°C~85°C -3% 12 +3%

25°C -1% 16 +1%

-40°C~85°C -2% 16 +2%

25°C -2.5% 16 +2.5%

-40°C~85°C -3% 16 +3%

MHz

Rev. 1.00 16 October 26, 2018 Rev. 1.00 17 October 26, 2018

BS86DH12C High Voltage Touch A/D Flash MCU with HVIO

3. The minimum and maximum tolerance values provided in the table are only for the frequency at which the writer trims the HIRC oscillator. After trimming at this chosen specific frequency any change in HIRC oscillator frequency using the oscillator register control bits by the application program will give a frequency tolerance to within ±20%.

Internal Low Speed Oscillator Characteristics – LIRC

Symbol Parameter

LIRC

START

LIRC Frequency 4.5V~5.5V

LIRC Start Up Time — 25°C — — 500 μs

Test Conditions

25°C -10% 32 +10%

-40°C~85°C -50% 32 +60%

Temp.

Min. Typ. Max. Unit

kHz

External Low Speed Oscillator Characteristics – LXT

C1=C2=10pF, RP=10MΩ (C1, C2 and RP are external components), CL=7pF, ESR=30kΩ

Symbol Parameter

LXT

START

LXT Frequency 4.5V~5.5V — — 32768 — Hz LXT Start Up Time 5V — — — 1000 μs

Test Conditions

Conditions

Min. Typ. Max. Unit

Duty Cycle Duty Cycle — — 40 — 60 %

NEG

Negative Resistance 5V — 3×ESR — — Ω

Ta=25°C

Operating Frequency Characteristic Curves

System Operating Frequency

16MHz

12MHz

8MHz

~ ~

4.5V 5.5V

Operating Voltage

BS86DH12C

High Voltage Touch A/D Flash MCU with HVIO

System Start Up Time Characteristics

Symbol Parameter

System Start-up Time Wake-up from Condition where f

SST

System Start-up Time Wake-up from Condition where f

SYS

is Off

is On

System Speed Switch Time FAST to SLOW Mode or SLOW to FAST Mode

System Reset Delay Time Reset Source from Power-on Reset or LVR Hardware Reset

RSTD

System Reset Delay Time LVRC/WDTC/RSTC Software Reset

System Reset Delay Time

Reset Source from WDT Overow

SRESET

Minimum Software Reset Width to Reset — — 45 90 180 μs

Note: 1. For the System Start-up time values, whether f

system oscillator. Details are provided in the System Operating Modes section.

SYS

2. The time units, shown by the symbols t

HIRC

, t

as provided in the frequency tables. For example t

3. If the LIRC is used as the system clock and if it is off when in the SLEEP Mode, then an additional LIRC start up time, t

, as provided in the LIRC frequency table, must be added to the t

START

above.

4. The System Speed Switch Time is effectively the time taken for the newly activated oscillator to start up.

— f

— RR

SYS=fH~fH

SYS=fSUB=fLXT

SYS=fSUB=fLIRC

SYS=fH~fH

SYS=fSUB=fLIRC

HIRC

LXT

Test Conditions

Conditions

/64, fH=f

HIRC

/64, fH=f

HIRC

or f

LXT

switches from off → on — 16 — t

switches from off → on — 1024 — t

=5V/ms

POR

Min. Typ. Max. Unit

— 16 — t

— 1024 — t

— 2 — t

30 48 72 ms

— —

— — 10 16 24 ms

is on or off depends upon the mode type and the chosen

SYS

etc. are the inverse of the corresponding frequency values

SYS

=1/f

, t

=1/f

HIRC

SYS

etc.

time in the table

SST

Ta=25°C

HIRC

LXT

LIRC

SUB

HIRC

LXT

Rev. 1.00 18 October 26, 2018 Rev. 1.00 19 October 26, 2018

BS86DH12C High Voltage Touch A/D Flash MCU with HVIO

Input/Output Characteristics

Ta=25°C

Symbol Parameter

LEAK

TCK

TPI

INT

Input Low Voltage for I/O Ports

Input High Voltage for I/O Ports

Sink Current for I/O Ports (PA, PB, PC)

Source Current for I/O Ports (PA, PB, PC)

Pull-high Resistance for I/O Ports

(Note)

Input Leakage Current 5V VIN=VDD or VIN=V TM Clock Input Pin Minimum Pulse Width — — 0.3 — — μs TM Capture Input Pin Minimum Pulse Width — — 0.3 — — μs External Interrupt Minimum Pulse Width — — 10 — — μs

Note: The RPH internal pull high resistance value is calculated by connecting to ground and enabling the input pin

with a pull-high resistor and then measuring the pin current at the specied supply voltage level. Dividing

the voltage by this measured current provides the RPH value.

Test Conditions

— 0 — 0.2V

— 0.8VDD— V

Conditions

—

VOL=0.1VDD, PxNS=0, x=A, B or C

VOL=0.1VDD, PxNS=1, x=A, B or C

Min. Typ. Max. Unit

0 — 1.5

3.5 — 5.0

32 64 —

50 100 —

VOH=0.9VDD, SLEDCn[m+1:m]=00B

-1.5 -2.9 —

(n=0, 1; m=0, 2, 4 or 6)

VOH=0.9VDD, SLEDCn[m+1:m]=01B (n=0, 1; m=0, 2, 4 or 6)

VOH=0.9VDD, SLEDCn[m+1:m]=10B

-2.5 -5.1 —

-3.6 -7.3 —

(n=0, 1; m=0, 2, 4 or 6)

VOH=0.9VDD, SLEDCn[m+1:m]=11B

-8 -16 —

(n=0, 1; m=0, 2, 4 or 6)

5V — 10 30 50 kΩ

— — ±1 μA

Memory Characteristics

Symbol Parameter

Flash Program / Data EEPROM Memory

DEW

DDPGM

RETD

RAM Data Memory

VDD for Read / Write — — V

Erase / Write Cycle Time – Flash Program Memory

Write Cycle Time – Data EEPROM Memory — — — 4 6 ms

Programming / Erase Current on V

Cell Endurance — — 100K — — E/W

ROM Data Retention Time — Ta=25°C — 40 — Year

RAM Data Retention Voltage — Device in SLEEP Mode 1.0 — — V

Ta=-40°C~85°C, unless otherwise specied

Test Conditions

Conditions

Min. Typ. Max. Unit

DDmin

— V

DDmax

— — — 2 3 ms

— — — — 5.0 mA

High Voltage Touch A/D Flash MCU with HVIO

LVD/LVR Electrical Characteristics

Symbol Parameter

LVDS

LVR

LVD

Low Voltage Reset Voltage

LVR

Low Voltage Detection Voltage

LVD

LVDO Stable Time —

Minimum Low Voltage Width to Reset — — 120 240 480 μs Minimum Low Voltage Width to Interrupt — — 60 120 240 μs

BS86DH12C

Test Conditions

Conditions

— LVR enable, voltage select 2.1V

— LVR enable, voltage select 2.55V 2.55

— LVR enable, voltage select 3.15V 3.15

— LVR enable, voltage select 3.8V 3.8

— LVD enable, voltage select 2.0V

— LVD enable, voltage select 2.2V 2.2

— LVD enable, voltage select 2.4V 2.4

— LVD enable, voltage select 2.7V 2.7

— LVD enable, voltage select 3.0V 3.0

— LVD enable, voltage select 3.3V 3.3

— LVD enable, voltage select 3.6V 3.6

— LVD enable, voltage select 4.0V 4.0

For LVR enable, VBGEN=0,

LVD off → on

Min. Typ. Max. Unit

2.1

-5%

2.0

-5%

— — 15 μs

Ta=25°C

+5% V

A/D Converter Electrical Characteristics

Symbol Parameter

A/D Converter Operating Voltage — — 4.5 — 5.5 V

A/D Converter Input Voltage — — 0 — V

ADI

A/D Converter Reference Voltage — — 2 — V

REF

DNL A/D Converter Differential Non-linearity 5V

INL A/D Converter Integral Non-linearity 5V

ADC

ADCK

ON2ST

ADS

ADC

Additional Current Consumption for A/D Converter Enable

A/D Converter Clock Period — — 0.5 — 10 μs A/D Converter On-to-Start Time — — 4 — — μs

A/D Converter Sampling Time — — — 4 — t

A/D Conversion Time (Including A/D Sampling and Hold Time)

Test Conditions

5V No load, t

— — — 16 — t

Conditions

REF=VDD

Ta=-40°C~85°C

Min. Typ. Max. Unit

, t

=0.5μs

ADCK

, t

=10μs

ADCK

, t

=0.5μs

ADCK

, t

=10μs

ADCK

=0.5μs — 1.5 3.0 mA

ADCK

-3 — +3 LSB

-4 — +4 LSB

REF

ADCK

Rev. 1.00 20 October 26, 2018 Rev. 1.00 21 October 26, 2018

BS86DH12C High Voltage Touch A/D Flash MCU with HVIO

Internal Reference Voltage Characteristics

Ta=25°C

Symbol Parameter

BGS

Bandgap Reference Voltage — — -5% 1.04 +5% V

VBG Turn-on Stable Time — No load — — 150 μs

Test Conditions

Conditions

Min. Typ. Max. Unit

Note: 1. All the above parameters are measured under conditions of no load condition unless otherwise described.

2. A 0.1μF ceramic capacitor should be connected between VDD and GND.

3. The VBG voltage is used as the A/D converter internal signal input.

High Voltage I/O Electrical Characteristics

VDD=5V, Ta=25°C, unless otherwise specied

Symbol Parameter Test Conditions Min. Typ. Max. Unit

Input Voltage — V

Input High Voltage for High Voltage I/O Ports — 0.6VIN— V

Input Low Voltage for High Voltage I/O Ports — 0 — 0.3VINV

DET1

Source Current for High Voltage I/O Ports VOH=0.9×VIN, VIN=10V -40 -70 — mA

Sink Current for High Voltage I/O Ports VOL=0.1×VIN, VIN=10V 50 80 — mA

SFRTC=0, Ta=25°C 2 — 3

Short Circuit Flag Response Time

SFRTC=0, Ta=-40°C~85°C 1.5 — 3.9

SFRTC=1, Ta=25°C 1.0 — 1.5

SFRTC=1, Ta=-40°C~85°C 0.75 — 1.85

— 10 V

Voltage Detector Electrical Characteristics

Symbol Parameter

DET1

RLS1

HYS1

DET2

RLS2

HYS2

Input Voltage — — V

Detect Level

CC2

Release Level

CC2

Hysteresis — VIN=10V ↔ 5V 100 750 1000 mV

VDD Detect Level — VDD=0V → 5V

VDD Release Level

Hysteresis — VDD=0V ↔ 5V 100 250 500 mV

(Note)

— VIN=0V → 10V

— VIN=10V → 0V V

— VDD=5V → 0V V

Test Conditions

Conditions

Ta=25°C

Min. Typ. Max. Unit

DET1

Typ.-

0.5

Typ.

-0.2

— 10 V

Typ.

+0.5

DET1-VHYS1

2.5

DET2-VHYS2

Typ.

+0.2

Note:

BS86DH12C

High Voltage Touch A/D Flash MCU with HVIO

DET1

RLS1

DET2

RLS2

PWRRDY

Undefined

High Voltage I/O Other Electrical Characteristics

Symbol Parameter

CC1O

CC2O

Input Voltage — — 7 — 10 V

Accuracy — VIN=10V -5% 0.2V

CC1O

Accuracy — VIN=10V -5% 0.2V

CC2O

Note: Divider 1: R11:R12=4:1(12kΩ/3kΩ), V

Divider 2: R21:R22=4:1(12kΩ/3kΩ), V

Test Conditions

=R12/(R11+R12)×V

CC1O

=R22/(R21+R22)×V

CC2O

Conditions

CC1

CC2

Min. Typ. Max. Unit

=0.2V

CC1

CC2

Ta=25°C

+5% V

Low Dropout Regulator Electrical Characteristics

=10μF+0.1μF, VIN=V

LOAD

Symbol Parameter

ΔV

OUT

LOAD

DROP

Input Voltage — — 6 — 10 V

Output Voltage

Load Regulation

Dropout Voltage

Output Current

—

(1)

(2)

— 1mA≤I

—

— VIN=V

Test Conditions

Conditions

Ta=25°C, I

=1mA, V

LOAD

OUT

Ta=-40°C~85°C, I V

=5.0V

OUT

≤70mA, VIN=V

LOAD

ΔV

=2%, I

OUT

VIN=V

+1V

OUT

+1V, ΔV

OUT

+2V, ΔV

OUT

LOAD

=5.0V

LOAD

=1mA,

OUT

Rev. 1.00 22 October 26, 2018 Rev. 1.00 23 October 26, 2018

+1V, Ta=25°C, unless otherwise specied

OUT

Min. Typ. Max. Unit

-2% 5.0 +2% V

=1mA,

+1V — 0.015 0.033 %/mA

OUT

-5% 5.0 +5% V

— — 100 mV

=-3% 250 — — mA

=-3% 500 — — mA

BS86DH12C

High Voltage Touch A/D Flash MCU with HVIO

Symbol Parameter

ΔV

LINE

Quiescent Current 10V No load — 120 200 μA Line Regulation — 6V≤VIN≤10V, I

TC Temperature Coefcient — Ta=-40°C~85°C, I ΔV

OUT_RIPPLE

RR Ripple Rejection

LIMIT

START

Output Voltage Ripple 6V I

(3)

—

Current Limit 6V ΔV

LDO Start Up Time 6V I

Test Conditions

Conditions

=1mA — — 0.2 %/V

LOAD

=10mA — ±1.5 ±2.0 mV/°C

LOAD

=10mA — — 40 mV

LOAD

VIN=10VDC+2V

P-P(AC)

, I

LOAD

≤50mA,

f=120Hz

=-10% 600 800 — mA

OUT

LOAD

=1mA, V

settle to ±5% — — 10 ms

OUT

Min. Typ. Max. Unit

35 — — dB

Note: 1. Load regulation is measured at a constant junction temperature, using pulse testing with a low ON time

and is guaranteed up to the maximum power dissipation. Power dissipation is determined by the input/ output differential voltage and the output current. Guaranteed maximum power dissipation will not be available over the full input/output range. The maximum allowable power dissipation at any ambient temperature is PD=(T

J(MAX)-Ta

)/θJA.

2. Dropout voltage is dened as the input voltage minus the output voltage that produces a 2% change in the

output voltage from the value at appointed VIN.

3. Ripple rejection ratio measurement circuit. RR=20×log(ΔVIN/ΔV

OUT

LDO

0.33μF

GND

OUT

10.1μF

Output

4. Application information for LDO load capacitor selection for stability:

Recommended Output Capacitor

Symbol Parameter

LOAD

Output Load Capacitor — Capacitor 4.7 10 — μF

In common with most regulators, the LDO requires an external capacitor connected between V

and ground for regulator stability. If the ESR is less than 10Ω, capacitor values of 4.7μF or large

are acceptable. Any aluminum electrolytic capacitor meeting the requirements described above is

suitable.

For better load transient response purposes, use a combination of a C

0.1μF capacitor on V

. Note that the 0.1μF capacitor is always required on V

OUT

recommended to be a multi-layer ceramic capacitor. The internal regulator is designed to be stable

with an output lter capacitor C

and ESR as recommended.

LOAD

Test Conditions

Conditions

Min. Typ. Max.

10μF and an extra

LOAD

and is strong

OUT

Ta=25°C

Unit

OUT

BS86DH12C

High Voltage Touch A/D Flash MCU with HVIO

OCP Electrical Characteristics

Ta=25°C

Symbol Parameter

OCP

Operating Current 5V

Comparator Input Offset Voltage

OS_CMP

Hysteresis 5V — 10 40 60 mV

HYS

Comparator Common Mode Voltage

CM_CMP

Range

OPA Input Offset Voltage

OS_OPA

OPA Common Mode Voltage Range 5V — V

CM_OPA

OPA Maximum Output Voltage Range 5V — VSS+0.1 — VDD-0.1 V

Ga PGA Gain Accuracy 5V All gains -5 — +5 %

D/A Converter Reference Voltage 5V OCPVRS=1 2 — V

REF

DNL Differential Non-linearity 5V DAC V

INL Integral Non-linearity 5V DAC V

Test Conditions

Conditions

OCPEN[1:0]=01B, DAC V

Without calibration

(OCPCOF[4:0]=10000B)

REF

=2.5V

Min. Typ. Max. Unit

— 730 1250 μA

-15 — 15

5V With calibration -4 — 4

5V — V

Without calibration

(OCPOOF[5:0]=100000B)

-15 — 15

— VDD-1.4 V

5V With calibration -4 — 4

— VDD-1.4 V

REF=VDD

-1 — +1 LSB

-1.5 — +1.5 LSB

OVP Electrical Characteristics

Symbol Parameter

OVP

Operating Current 5V OVPEN=1, DAC V

Input Offset Voltage 5V With calibration -2 — 2 mV

Hysteresis 5V

HYS

Common Mode Voltage Range 5V — V

DNL Differential Non-linearity 5V DAC V

INL Integral Non-linearity 5V DAC V

OVP Response Time 5V

HYS[1:0]=00B 0 0 5

HYS[1:0]=01B 15 30 45

HYS[1:0]=10B 40 60 80

HYS[1:0]=11B 60 80 100

OVPDA[7:0]=10000000B, OVPDEB[2:0]=000B, DAC V OVP input=2.1V~3.6V

Test Conditions

Conditions

REF=VDD

Ta=25°C

Min. Typ. Max. Unit

— 500 750 μA

— VDD-1.4 V

-1 — +1 LSB

-1.5 — +1.5 LSB

— 1.0 1.8 μs

Rev. 1.00 24 October 26, 2018 Rev. 1.00 25 October 26, 2018

BS86DH12C High Voltage Touch A/D Flash MCU with HVIO

Power-on Reset Characteristics

Symbol Parameter

POR

VDD Start Voltage to Ensure Power-on Reset — — — — 100 mV

POR

PORVDD

Rising Rate to Ensure Power-on Reset — — 0.035 — — V/ms

Minimum Time for VDD Stays at V Power-on Reset

to Ensure

POR

Test Conditions

— — 1 — — ms

Conditions

Ta=25°C

Min. Typ. Max. Unit

System Architecture

A key factor in the high-performance features of the range of microcontrollers is attributed to their

internal system architecture. The device takes advantage of the usual features found within RISC

microcontrollers providing increased speed of operation and enhanced performance. The pipelining

scheme is implemented in such a way that instruction fetching and instruction execution are

overlapped, hence instructions are effectively executed in one or two cycles for most of the standard

or extended instructions respectively. The exceptions to this are branch or call instructions which need

one more cycle. An 8-bit wide ALU is used in practically all instruction set operations, which carries

out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc.

The internal data path is simplied by moving data through the Accumulator and the ALU. Certain

internal registers are implemented in the Data Memory and can be directly or indirectly addressed.

The simple addressing methods of these registers along with additional architectural features ensure

that a minimum of external components is required to provide a functional I/O and A/D control

system with maximum reliability and flexibility. This makes the device suitable for low-cost,

high-volume production for controller applications.

Clocking and Pipelining

The main system clock, derived from either a HIRC, LIRC or LXT oscillator is subdivided into four

internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the

beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4

clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms

one instruction cycle. Although the fetching and execution of instructions takes place in consecutive

instruction cycles, the pipelining structure of the microcontroller ensures that instructions are

effectively executed in one instruction cycle. The exception to this are instructions where the

contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the

instruction will take one more instruction cycle to execute.

POR

Time

BS86DH12C

High Voltage Touch A/D Flash MCU with HVIO

(System Clock)

Phase Clock T1

Phase Clock T2

Phase Clock T3

Phase Clock T4

Program Counter PC PC+1 PC+2

SYS

Pipelining

For instructions involving branches, such as jump or call instructions, two machine cycles are

required to complete instruction execution. An extra cycle is required as the program takes one

cycle to rst obtain the actual jump or call address and then another cycle to actually execute the

branch. The requirement for this extra cycle should be taken into account by programmers in timing

sensitive applications.

1 MOV A,[12H] 2 CALL DELAY 3 CPL [12H] 4 : 5 : 6 DELAY: NOP

Program Counter

During program execution, the Program Counter is used to keep track of the address of the next

instruction to be executed. It is automatically incremented by one each time an instruction is executed

except for instructions, such as “JMP” or “CALL” that demand a jump to a non-consecutive Program

Memory address. Only the lower 8 bits, known as the Program Counter Low Register, are directly

addressable by the application program.

When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction,

a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading

the required address into the Program Counter. For conditional skip instructions, once the condition

has been met, the next instruction, which has already been fetched during the present instruction

execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained.

Fetch Inst. (PC)

Execute Inst. (PC-1) Fetch Inst. (PC+1)

Execute Inst. (PC)

System Clocking and Pipelining

Fetch Inst. 1

Execute Inst. 1

Fetch Inst. 2 Execute Inst. 2

Fetch Inst. 3 Flush Pipeline

Instruction Fetching

Program Counter

High Byte Low Byte (PCL)

PC12~PC8 PCL7~PCL0

Program Counter

Fetch Inst. (PC+2)

Execute Inst. (PC+1)

Fetch Inst. 6 Execute Inst. 6

Fetch Inst. 7

The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is

available for program control and is a readable and writeable register. By transferring data directly

into this register, a short program jump can be executed directly; however, as only this low byte

is available for manipulation, the jumps are limited to the present page of memory that is 256

locations. When such program jumps are executed it should also be noted that a dummy cycle

Rev. 1.00 26 October 26, 2018 Rev. 1.00 27 October 26, 2018

BS86DH12C High Voltage Touch A/D Flash MCU with HVIO

will be inserted. Manipulating the PCL register may cause program branching, so an extra cycle is

needed to pre-fetch.

Stack

This is a special part of the memory which is used to save the contents of the Program Counter

only. The stack is organized into 8 levels and neither part of the data nor part of the program space,

and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, and is

neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of

the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine,

signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value

from the stack. After a device reset, the Stack Pointer will point to the top of the stack.

If the stack is full and an enabled interrupt takes place, the interrupt request ag will be recorded but

the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI,

the interrupt will be serviced. This feature prevents stack overow allowing the programmer to use

the structure more easily. However, when the stack is full, a CALL subroutine instruction can still

be executed which will result in a stack overow. Precautions should be taken to avoid such cases

which might cause unpredictable program branching.

If the stack is overow, the rst Program Counter save in the stack will be lost.

Top of Stack

Stack

Pointer

Bottom of Stack

Arithmetic and Logic Unit – ALU

The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic

and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU

receives related instruction codes and performs the required arithmetic or logical operations after

which the result will be placed in the specied register. As these ALU calculation or operations may

result in carry, borrow or other status changes, the status register will be correspondingly updated to

reect these changes. The ALU supports the following functions:

• Arithmetic operations:

ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA,

LADD, LADDM, LADC, LADCM, LSUB, LSUBM, LSBC, LSBCM, LDAA

• Logic operations:

AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA,

LAND, LOR, LXOR, LANDM, LORM, LXORM, LCPL, LCPLA

• Rotation:

RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC,

LRRA, LRR, LRRCA, LRRC, LRLA, LRL, LRLCA, LRLC

• Increment and Decrement:

INCA, INC, DECA, DEC,

LINCA, LINC, LDECA, LDEC

Stack Level 1

Stack Level 2

Stack Level 3

: : :

Stack Level 8

Program Counter

Program Memory

• Branch decision:

JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI,

LSZ, LSZA, LSNZ, LSIZ, LSDZ, LSIZA, LSDZA

Flash Program Memory

The Program Memory is the location where the user code or program is stored. For this device the

Program Memory is Flash type, which means it can be programmed and re-programmed a large

number of times, allowing the user the convenience of code modication on the same device. By

using the appropriate programming tools, the Flash device offers users the exibility to conveniently

debug and develop their applications while also offering a means of eld programming and updating.

Structure

The Program Memory has a capacity of 8K×16 bits. The Program Memory is addressed by the

Program Counter and also contains data, table information and interrupt entries. Table data, which

can be configured in any location within the Program Memory, is addressed by a separate table

pointer register.

BS86DH12C

High Voltage Touch A/D Flash MCU with HVIO

Special Vectors

Within the Program Memory, certain locations are reserved for the reset and interrupts. The location

0000H is reserved for use by the device reset for program initialisation. After a device reset is

initiated, the program will jump to this location and begin execution.

Look-up Table

Any location within the Program Memory can be dened as a look-up table where programmers can store xed data. To use the look-up table, the table pointer must rst be congured by placing

the address of the look up data to be retrieved in the table pointer register, TBLP and TBHP. These

registers dene the total address of the look-up table.

After setting up the table pointer, the table data can be retrieved from the Program Memory using the “TABRD [m]” or “TABRDL [m]” instructions respectively when the memory [m] is located in sector 0. If the memory [m] is located in other sectors except sector 0, the data can be retrieved from the program memory using the corresponding extended table read instruction such as “LTABRD [m]” or “LTABRDL [m]” respectively. When the instruction is executed, the lower order table byte from

the Program Memory will be transferred to the user dened Data Memory register [m] as specied

0000H

0004H

0034H

1FFFH

Program Memory Structure

n00H

nFFH

Initialisation Vector

Interrupt Vectors

Look-up Table

Bank 0

16 bits

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BS86DH12C High Voltage Touch A/D Flash MCU with HVIO

in the instruction. The higher order table data byte from the Program Memory will be transferred to

the TBLH special register.

The accompanying diagram illustrates the addressing data ow of the look-up table.

Program Memory

Last Page or

TBHP Register

TBLP Register

Address

16 bits

Data

Table Program Example

The following example shows how the table pointer and table data is dened and retrieved from the

microcontroller. This example uses raw table data located in the Program Memory which is stored

there using the ORG statement. The value at this ORG statement is “1F00H” which refers to the start

address of the last page within the 8K Program Memory of the microcontroller. The table pointer

low byte register is set here to have an initial value of “06H”. This will ensure that the rst data read

from the data table will be at the Program Memory address “1F06H” or 6 locations after the start of

the last page. Note that the value for the table pointer is referenced to the specic page pointed by

the TBLP and TBHP registers if the “TABRD [m]” or “LTABRD [m]” instruction is being used. The

high byte of the table data which in this case is equal to zero will be transferred to the TBLH register

automatically when the “TABRD [m]” instruction is executed.

Because the TBLH register is a read/write register and can be restored, care should be taken

to ensure its protection if both the main routine and Interrupt Service Routine use table read

instructions. If using the table read instructions, the Interrupt Service Routines may change the

value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is

recommended that simultaneous use of the table read instructions should be avoided. However, in

situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the

execution of any main routine table-read instructions. Note that all table related instructions require

two instruction cycles to complete their operation.

High Byte Low Byte

User Selected

Table Read Program Example

tempreg1 db ? ; temporary register #1

tempreg2 db ? ; temporary register #2 : :

mov a,06h ; initialise low table pointer - note that this address

; is referenced

mov tblp,a ; to the last page or the page that tbhp pointed

mov a,1Fh ; initialise high table pointer

mov tbhp,a : :

tabrd tempreg1 ; transfers value in table referenced by table pointer data at

; program memory address “1F06H” transferred to tempreg1 and TBLH

dec tblp ; reduce value of table pointer by one

tabrd tempreg2 ; transfers value in table referenced by table pointer

; data at program memory address “1F05H” transferred to

; tempreg2 and TBLH, in this example the data “1AH” is

; transferred to tempreg1 and data “0FH” to register tempreg2 : :

org 1F00h ; sets initial address of program memory

dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh : :

In Circuit Programming – ICP

The provision of Flash type Program Memory provides the user with a means of convenient and

easy upgrades and modications to their programs on the same device.

As an additional convenience, Holtek has provided a means of programming the microcontroller

in-circuit using a 4-pin interface. This provides manufacturers with the possibility of manufacturing

their circuit boards complete with a programmed or un-programmed microcontroller, and then

programming or upgrading the program at a later stage. This enables product manufacturers to easily

keep their manufactured products supplied with the latest program releases without removal and

re-insertion of the device.

Holtek Writer Pins MCU Programming Pins Pin Description

ICPDA PA0 Programming Serial Data/Address

ICPCK PA2 Programming Clock

VDD VDD Power Supply

VSS VSS Ground

BS86DH12C

High Voltage Touch A/D Flash MCU with HVIO

The Program Memory can be programmed serially in-circuit using this 4-wire interface. Data

is downloaded and uploaded serially on a single pin with an additional line for the clock. Two

additional lines are required for the power supply. The technical details regarding the in-circuit

programming of the device is beyond the scope of this document and will be supplied in

supplementary literature.

During the programming process, the user must take care of the ICPDA and ICPCK pins for data

and clock programming purposes to ensure that no other outputs are connected to these two pins.

Writer Connector

Signals

Writer_VDD

ICPDA

ICPCK

Writer_VSS

* *

To other Circuit

MCU Programming

Pins

VDD

PA0

PA2

VSS

Note: * may be resistor or capacitor. The resistance of * must be greater than 1kΩ or the capacitance

of * must be less than 1nF.

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BS86DH12C High Voltage Touch A/D Flash MCU with HVIO

On-Chip Debug Support – OCDS

There is an EV chip named BS86DHV12C which is used to emulate the real MCU device named

BS86DH12C. The EV chip device also provides an “On-Chip Debug” function to debug the real

MCU device during the development process. The EV chip and the real MCU device are almost

functionally compatible except for “On-Chip Debug” function. Users can use the EV chip device to

emulate the real chip device behavior by connecting the OCDSDA and OCDSCK pins to the Holtek

HT-IDE development tools. The OCDSDA pin is the OCDS Data/Address input/output pin while the

OCDSCK pin is the OCDS clock input pin. When users use the EV chip device for debugging, the

corresponding pin functions shared with the OCDSDA and OCDSCK pins in the real MCU device

will have no effect in the EV chip. However, the two OCDS pins which are pin-shared with the ICP

programming pins are still used as the Flash Memory programming pins for ICP. For more detailed

OCDS information, refer to the corresponding document named “Holtek e-Link for 8-bit MCU

OCDS User’s Guide”.

Holtek e-Link Pins EV Chip OCDS Pins Pin Description

OCDSDA OCDSDA On-Chip Debug Support Data/Address input/output

OCDSCK OCDSCK On-Chip Debug Support Clock input

VDD VDD Power Supply

VSS VSS Ground

Data Memory

The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where

temporary information is stored.

Categorized into two types, the rst of these is an area of RAM where special function registers are

located. These registers have xed locations and are necessary for correct operation of the device.

Many of these registers can be read from and written to directly under program control, however,

some remain protected from user manipulation. The second area of Data Memory is reserved for

general purpose use. All locations within this area are read and write accessible under program

control.

Structure

The overall Data Memory is subdivided into several sectors, all of which are implemented in 8-bit

wide RAM. Each of the Data Memory Sector is categorized into two types, the special Purpose Data

Memory and the General Purpose Data Memory. The address range of the Special Purpose Data

Memory for the device is from 00H to 7FH while the General Purpose Data Memory address range

is from 80H to FFH. Switching between the different Data Memory sectors is achieved by setting

the Memory Pointers to the correct value if using the indirect addressing method.

Special PurposeData Memory General PurposeData Memory

Located Sectors Capacity Sector: Address

Sector 0: 80H~FFH

Sector 0, Sector 1 512×8

Data Memory Summary

Sector 1: 80H~FFH Sector 2: 80H~FFH Sector 3: 80H~FFH

BS86DH12C

High Voltage Touch A/D Flash MCU with HVIO

00H

Special Purpose Data Memory

(Sector 0 ~ Sector 1)

7FH 80H

General Purpose Data Memory

(Sector 0 ~ Sector 3)

Data Memory Addressing

For this device that supports the extended instructions, there is no Bank Pointer for Data Memory

addressing. For Data Memory the desired Sector is pointed by the MP1H or MP2H register and the

certain Data Memory address in the selected sector is specied by the MP1L or MP2L register when

using indirect addressing access.

Direct Addressing can be used in all sectors using the extended instruction which can address all

available data memory space. For the accessed data memory which is located in any data memory

sectors except sector 0, the extended instructions can be used to access the data memory instead

of using the indirect addressing access. The main difference between standard instructions and

extended instructions is that the data memory address “m” in the extended instructions has 10 valid

bits for the device, the high byte indicates a sector and the low byte indicates a specic address.

General Purpose Data Memory

All microcontroller programs require an area of read/write memory where temporary data can be

stored and retrieved for use later. It is this area of RAM memory that is known as General Purpose

Data Memory. This area of Data Memory is fully accessible by the user programing for both reading

and writing operations. By using the bit operation instructions individual bits can be set or reset

under program control giving the user a large range of exibility for bit manipulation in the Data

Memory.

FFH

Data Memory Structure

Sector 0

Sector 1

Sector 3

Special Purpose Data Memory

This area of Data Memory is where registers, necessary for the correct operation of the

microcontroller, are stored. Most of the registers are both readable and writeable but some are

protected and are readable only, the details of which are located under the relevant Special Function

return the value “00H”.

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BS86DH12C High Voltage Touch A/D Flash MCU with HVIO

00H 01H

02H 03H 04H 05H 06H 07H 08H

09H 0AH 0BH 0CH 0DH 0EH 0FH

10H

11H

12H

13H

14H

15H

16H

17H

18H

19H 1AH 1BH 1CH 1DH 1EH 1FH

20H

21H

22H

23H

24H

25H

26H

27H

28H

29H 2AH 2BH 2CH 2DH 2EH 2FH

30H

31H

32H

33H

34H

35H

36H

37H

38H

39H 3AH 3BH 3CH 3DH 3EH 3FH

Sector 0 Sector 1Sector 0

IAR0 MP0 IAR1

MP1L

MP1H

ACC

PCL TBLP TBLH TBHP

STATUS

IAR2 MP2L

MP2H

RSTFC

INTC0 INTC1 INTC2 INTC3

PAC PAPU

PAWU SLEDC0 SLEDC1

WDTC

TBC

PSCR

LVRC

EEA EED

PBC PBPU IICC0 IICC1

IICD

IICA

IICTOC

USR UCR1 UCR2

TXR_RXR

BRG

SADOL SADOH SADC0 SADC1

INTEG

IFS0

IFS1 LVDC

SCC

HIRCC

LXTC

PCC

PCPU

MFI0 OCPC1

MFI1

PDC

: Unused, read as 00H

Sector 1

PAS0 PAS1 PBS0 PBS1 PCS0

SLEDCOM0 SLEDCOM1 SLEDCOM2

40H 41H

42H 43H 44H 45H 46H 47H 48H

49H 4AH 4BH 4CH 4DH 4EH 4FH

50H

51H

52H

53H

54H

55H

56H

57H

58H

59H 5AH 5BH 5CH 5DH 5EH 5FH

60H

61H

62H

63H

64H

65H

66H

67H

68H

69H 6AH 6BH 6CH 6DH 6EH 6FH

70H

71H

72H

73H

74H

75H

76H

77H

78H

79H 7AH 7BH 7CH 7DH 7EH 7FH

PDOM

PWRDET

RSTC

TKTMR

TKC0 TK16DL TK16DH

TKC1

TKM016DL TKM016DH

TKM0ROL

TKM0ROH

TKM0C0

TKM0C1 TKM116DL TKM116DH

TKM1ROL

TKM1ROH

TKM1C0

TKM1C1 TKM216DL TKM216DH

TKM2ROL

TKM2ROH

TKM2C0

TKM2C1

CTM0C0

CTM0C1

CTM0DL

CTM0DH

CTM0AL

CTM0AH

PTMC0 PTMC1 PTMDL PTMDH PTMAL

PTMAH PTMRPL PTMRPH

CTM1C0 CTM1C1 CTM1DL CTM1DH CTM1AL CTM1AH

OVPC0

OVPC1

OVPC2

OVPDA

OCPC0

OCPDA

OCPOCAL

OCPCCAL

Special Purpose Data Memory Structure

EEC

High Voltage Touch A/D Flash MCU with HVIO

Special Function Register Description

Most of the Special Function Register details will be described in the relevant functional sections.

However, several registers require a separate description in this section.

Indirect Addressing Registers – IAR0, IAR1, IAR2

The Indirect Addressing Registers, IAR0, IAR1 and IAR2, although having their locations in normal

RAM register space, do not actually physically exist as normal registers. The method of indirect

addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory

Pointers, in contrast to direct memory addressing, where the actual memory address is specied.

Actions on the IAR0, IAR1 and IAR2 registers will result in no actual read or write operation to

these registers but rather to the memory location specied by their corresponding Memory Pointers,

MP0, MP1L/MP1H or MP2L/MP2H. Acting as a pair, IAR0 and MP0 can together access data only

from Sector 0 while the IAR1 register together with the MP1L/MP1H register pair and IAR2 register

together with the MP2L/MP2H register pair can access data from any Data Memory Sector. As

the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing

Registers will return a result of “00H” and writing to the registers will result in no operation.

Memory Pointers – MP0, MP1L/MP1H, MP2L/MP2H

Five Memory Pointers, known as MP0, MP1L, MP1H, MP2L, MP2H, are provided. These Memory

Pointers are physically implemented in the Data Memory and can be manipulated in the same way

as normal registers providing a convenient way with which to address and track data. When any

operation to the relevant Indirect Addressing Registers is carried out, the actual address that the

microcontroller is directed to is the address specied by the related Memory Pointer. MP0, together

with Indirect Addressing Register, IAR0, are used to access data from Sector 0, while MP1L/MP1H

together with IAR1 and MP2L/MP2H together with IAR2 are used to access data from all sectors

according to the corresponding MP1H or MP2H register. Direct Addressing can be used in all

sectors using the extended instruction which can address all available Data Memory space.

The following example shows how to clear a section of four Data Memory locations already dened

as locations adres1 to adres4.

BS86DH12C

Indirect Addressing Program Example 1

data .section ´data´ adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 ´code´ org 00h

start:

mov a, 04h ; set size of block mov block, a

 mova,offsetadres1  ;AccumulatorloadedwithrstRAMaddress  movmp0,a    ;setmemorypointerwithrstRAMaddress

loo p:

 clrIAR0     ;clearthedataataddressdenedbyMP0

inc mp0 ; increase memory pointer sdz block ; check if last memory location has been cleared jmp loop continue:

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BS86DH12C High Voltage Touch A/D Flash MCU with HVIO

Indirect Addressing Program Example 2

data .section ´data´ adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 ´code´ org 00h

start:

mov a, 04h ; set size of block mov block, a mov a, 01h ; set the memory sector mov mp1h, a

 mova,offsetadres1  ;AccumulatorloadedwithrstRAMaddress  movmp1l,a    ;setmemorypointerwithrstRAMaddress

loo p:

 clrIAR1     ;clearthedataataddressdenedbyMP1L  incmp1l     ;increasememorypointerMP1L

sdz block ; check if last memory location has been cleared jmp loop continue:

The important point to note here is that in the example shown above, no reference is made to specic

Data Memory addresses.

Direct Addressing Program Example using extended instructions

data .section ´data´ temp db ? code .section at 0 ´code´ org 00h

start:

lmov a, [m] ; move [m] data to acc lsub a, [m +1] ; compare [m] and [m+1] data snz c ; [m]>[m+1]? jmp continue ; no lmo v a, [m] ; y es, exchange [m] and [m +1] data mov temp, a lmov a, [m+1] l m o v [ m ], a mov a, temp lmov [m+1], a continue:

Note: here “m” is a data memory address located in any data memory sectors. For example,

m=1F0H, it indicates address 0F0H in Sector 1.

Accumulator – ACC

The Accumulator is central to the operation of any microcontroller and is closely related with

operations carried out by the ALU. The Accumulator is the place where all intermediate results

from the ALU are stored. Without the Accumulator it would be necessary to write the result of

each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory

resulting in higher programming and timing overheads. Data transfer operations usually involve

the temporary storage function of the Accumulator; for example, when transferring data between

one user-defined register and another, it is necessary to do this by passing the data through the

Accumulator as no direct transfer between two registers is permitted.

High Voltage Touch A/D Flash MCU with HVIO

Program Counter Low Register – PCL

To provide additional program control functions, the low byte of the Program Counter is made

accessible to programmers by locating it within the Special Purpose area of the Data Memory. By

manipulating this register, direct jumps to other program locations are easily implemented. Loading

a value directly into this PCL register will cause a jump to the specied Program Memory location,

however, as the register is only 8-bit wide, only jumps within the current Program Memory page are

permitted. When such operations are used, note that a dummy cycle will be inserted.

Look-up Table Registers – TBLP, TBHP, TBLH

These three special function registers are used to control operation of the look-up table which is

stored in the Program Memory. TBLP and TBHP are the table pointers and indicate the location

where the table data is located. Their value must be set before any table read commands are

executed. Their value can be changed, for example using the “INC” or “DEC” instructions, allowing

for easy table data pointing and reading. TBLH is the location where the high order byte of the table

data is stored after a table read data instruction has been executed. Note that the lower order table

data byte is transferred to a user dened location.

Status Register – STATUS

This 8-bit register contains the SC ag, CZ ag, zero ag (Z), carry ag (C), auxiliary carry ag (AC),

overow ag (OV), power down ag (PDF), and watchdog time-out ag (TO). These arithmetic/

logical operation and system management ags are used to record the status and operation of the

microcontroller.

With the exception of the TO and PDF ags, bits in the status register can be altered by instructions

like most other registers. Any data written into the status register will not change the TO or PDF ag.

In addition, operations related to the status register may give different results due to the different

instruction operations. The TO ag can be affected only by a system power-up, a WDT time-out or

by executing the “CLR WDT” or “HALT” instruction. The PDF ag is affected only by executing

the “HALT” or “CLR WDT” instruction or during a system power-up.

The Z, OV, AC, C, SC and CZ ags generally reect the status of the latest operations.

• C is set if an operation results in a carry during an addition operation or if a borrow does not take

place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through

carry instruction.

• AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from

the high nibble into the low nibble in subtraction; otherwise AC is cleared.

• Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.

• OV is set if an operation results in a carry into the highest-order bit but not a carry out of the

highest-order bit, or vice versa; otherwise OV is cleared.

• PDF is cleared by a system power-up or executing the “CLR WDT” instruction. PDF is set by

executing the “HALT” instruction.

• TO is cleared by a system power-up or executing the “CLR WDT” or “HALT” instruction. TO is

set by a WDT time-out.

• CZ is the operational result of different ags for different instructions. Refer to register denitions

for more details.

• SC is the result of the “XOR” operation which is performed by the OV ag and the MSB of the

current instruction operation result.

BS86DH12C

Rev. 1.00 36 October 26, 2018 Rev. 1.00 37 October 26, 2018

BS86DH12C High Voltage Touch A/D Flash MCU with HVIO

In addition, on entering an interrupt sequence or executing a subroutine call, the status register will

not be pushed onto the stack automatically. If the contents of the status register are important and if

the subroutine can corrupt the status register, precautions must be taken to correctly save it.

• STATUS Register

Bit 7 6 5 4 3 2 1 0

Name SC CZ TO PDF OV Z AC C

R/W R/W R/W R R R/W R/W R/W R/W

POR x x 0 0 x x x x

Bit 7 SC: The result of the “XOR” operation which is performed by the OV ag and the MSB

of the instruction operation result.

Bit 6 CZ: The operational result of different ags for different instructions.

For SUB/SUBM/LSUB/LSUBM instructions, the CZ ag is equal to the Z ag.

For SBC/SBCM/LSBC/LSBCM instructions, the CZ flag is the “AND” operation

result which is performed by the previous operation CZ ag and current operation zero ag.

For other instructions, the CZ ag will not be affected.

Bit 5 TO: Watchdog Time-out ag

0: After power up or executing the “CLR WDT” or “HALT” instruction 1: A watchdog time-out occurred.

Bit 4 PDF: Power down ag

0: After power up or executing the “CLR WDT” instruction 1: By executing the “HALT” instruction

Bit 3 OV: Overow ag

0: No overow

1: An operation results in a carry into the highest-order bit but not a carry out of the

highest-order bit or vice versa.

Bit 2 Z: Zero ag

0: The result of an arithmetic or logical operation is not zero 1: The result of an arithmetic or logical operation is zero

Bit 1 AC: Auxiliary ag

0: No auxiliary carry 1: An operation results in a carry out of the low nibbles in addition, or no borrow

from the high nibble into the low nibble in subtraction

Bit 0 C: Carry ag

0: No carry-out 1: An operation results in a carry during an addition operation or if a borrow does

not take place during a subtraction operation

The “C” ag is also affected by a rotate through carry instruction.

“x”: unknown

EEPROM Data Memory

The device contains an area of internal EEPROM Data Memory. EEPROM is by its nature a non-

volatile form of re-programmable memory, with data retention even when its power supply is

removed. By incorporating this kind of data memory, a whole new host of application possibilities

are made available to the designer. The availability of EEPROM storage allows information such

as product identication numbers, calibration values, specic user data, system setup data or other

product information to be stored directly within the product microcontroller. The process of reading

and writing data to the EEPROM memory has been reduced to a very trivial affair.

EEPROM Data Memory Structure

The EEPROM Data Memory capacity is 64×8 bits for the device. Unlike the Program Memory and

RAM Data Memory, the EEPROM Data Memory is not directly mapped into memory space and

is therefore not directly addressable in the same way as the other types of memory. Read and Write

operations to the EEPROM are carried out in single byte operations using an address and a data

EEPROM Registers

Three registers control the overall operation of the internal EEPROM Data Memory. These are the

address register, EEA, the data register, EED and a single control register, EEC. As both the EEA

and EED registers are located in Sector 0, they can be directly accessed in the same way as any

other Special Function Register. The EEC register however, being located in only Sector 1, can only

be read from or written to indirectly using the MP1L/MP1H or MP2L/MP2H Memory Pointer and

Indirect Addressing Register, IAR1/IAR2. As it is located at address 40H in Sector 1, the MP1L or

MP2L Memory Pointer must rst be set to the value 40H and the MP1H or MP2H Memory Pointer

high byte set to the value, 01H, before any operations on the EEC register are executed.

Name

EEA — — EEA5 EEA4 EEA3 EEA2 EEA1 EEA0

EED D7 D6 D5 D4 D3 D2 D1 D0

EEC — — — — WREN WR RDEN RD

7 6 5 4 3 2 1 0

BS86DH12C

High Voltage Touch A/D Flash MCU with HVIO

Capacity Address

64×8 00H~3FH

Bit

EEPROM Register List

• EEA Register

Bit 7 6 5 4 3 2 1 0

Name — — EEA5 EEA4 EEA3 EEA2 EEA1 EEA0

R/W — — R/W R/W R/W R/W R/W R/W

POR — — 0 0 0 0 0 0

Bit 7~6 Unimplemented, read as “0”

Bit 5~0 EEA5~EEA0: Data EEPROM address bit 5 ~ bit 0

Rev. 1.00 38 October 26, 2018 Rev. 1.00 39 October 26, 2018

BS86DH12C High Voltage Touch A/D Flash MCU with HVIO

• EED Register

Bit 7 6 5 4 3 2 1 0

Name D7 D6 D5 D4 D3 D2 D1 D0

R/W R/W R/W R/W R/W R/W R/W R/W R/W

POR 0 0 0 0 0 0 0 0

Bit 7~0 D7~D0: Data EEPROM data bit 7 ~ bit 0

• EEC Register

Bit 7 6 5 4 3 2 1 0

Name — — — — WREN WR RDEN RD

R/W — — — — R/W R/W R/W R/W

POR — — — — 0 0 0 0

Bit 7~4 Unimplemented, read as “0”

Bit 3 WREN: Data EEPROM Write Enable

0: Disable 1: Enable

This is the Data EEPROM Write Enable Bit which must be set high before Data EEPROM write operations are carried out. Clearing this bit to zero will inhibit Data EEPROM write operations.

Bit 2 WR: EEPROM Write Control

0: Write cycle has nished

1: Activate a write cycle

This is the Data EEPROM Write Control Bit and when set high by the application program will activate a write cycle. This bit will be automatically reset to zero by the

hardware after the write cycle has nished. Setting this bit high will have no effect if the WREN has not rst been set high.

Bit 1 RDEN: Data EEPROM Read Enable

0: Disable 1: Enable

This is the Data EEPROM Read Enable Bit which must be set high before Data EEPROM read operations are carried out. Clearing this bit to zero will inhibit Data EEPROM read operations.

Bit 0 RD: EEPROM Read Control

0: Read cycle has nished

1: Activate a read cycle

This is the Data EEPROM Read Control Bit and when set high by the application program will activate a read cycle. This bit will be automatically reset to zero by the

hardware after the read cycle has nished. Setting this bit high will have no effect if the RDEN has not rst been set high.

Note: 1. The WREN, WR, RDEN and RD bits cannot be set high at the same time in one instruction.

The WR and RD bits cannot be set high at the same time.

2. Ensure that the f

3. Ensure that the write operation is totally complete before changing the EEC register content.

clock is stable before executing the write operation.

SUB

Reading Data from the EEPROM

To read data from the EEPROM, the EEPROM address of the data to be read must rst be placed in

the EEA register. The read enable bit, RDEN, in the EEC register must then be set high to enable the

read function. If the RD bit in the EEC register is now set high, a read cycle will be initiated. Setting

the RD bit high will not initiate a read operation if the RDEN bit has not been set. When the read cycle

terminates, the RD bit will be automatically cleared to zero, after which the data can be read from

the EED register. The data will remain in the EED register until another read or write operation is

executed. The application program can poll the RD bit to determine when the data is valid for reading.

Writing Data to the EEPROM

To write data to the EEPROM, the EEPROM address of the data to be written must rst be placed

in the EEA register and the data placed in the EED register. To initiate a write cycle the write enable

bit, WREN, in the EEC register must rst be set high to enable the write function. After this, the

WR bit in the EEC register must be immediately set high to initiate a write cycle successfully. These

two instructions must be executed in two consecutive instruction cycles. The global interrupt bit

EMI should also rst be cleared before implementing any write operations, and then set high again

after the write cycle has started. Note that setting the WR bit high will not initiate a write cycle if

the WREN bit has not been set. As the EEPROM write cycle is controlled using an internal timer

whose operation is asynchronous to microcontroller system clock, a certain time will elapse before

the data will have been written into the EEPROM. Detecting when the write cycle has finished

can be implemented either by polling the WR bit in the EEC register or by using the EEPROM

interrupt. When the write cycle terminates, the WR bit will be automatically cleared to zero by the

microcontroller, informing the user that the data has been written to the EEPROM. The application

program can therefore poll the WR bit to determine when the write cycle has ended.

Write Protection

Protection against inadvertent write operation is provided in several ways. After the device is

powered-on the Write Enable bit in the control register will be cleared preventing any write

operations. Also at power-on the Memory Pointer high byte register, MP1H or MP2H, will be reset

to zero, which means that Data Memory Sector 0 will be selected. As the EEPROM control register

is located in Sector 1, this adds a further measure of protection against spurious write operations.

During normal program operation, ensuring that the Write Enable bit in the control register is

cleared will safeguard against incorrect write operations.

BS86DH12C

High Voltage Touch A/D Flash MCU with HVIO

EEPROM Interrupt

The EEPROM write interrupt is generated when an EEPROM write cycle has ended. The EEPROM

interrupt must first be enabled by setting the DEE bit in the relevant interrupt register. When an

EEPROM write cycle ends, the DEF request ag will be set. If the global, EEPROM interrupts are

enabled and the stack is not full, a jump to the associated EEPROM Interrupt vector will take place.

When the interrupt is serviced, the EEPROM Interrupt ag, DEF, will be automatically cleared. The

EMI bit will also be automatically cleared to disable other interrupts. More details can be obtained

in the Interrupt section.

Programming Considerations

Care must be taken that data is not inadvertently written to the EEPROM. Protection can be

enhanced by ensuring that the Write Enable bit is normally cleared to zero when not writing. Also

the Memory Pointer high byte register, MP1H or MP2H, could be normally cleared to zero as this

would inhibit access to Sector 1 where the EEPROM control register exists. Although certainly not

necessary, consideration might be given in the application program to the checking of the validity of

new write data by a simple read back process.

When writing data the WR bit must be set high immediately after the WREN bit has been set high,

to ensure the write cycle executes correctly. The global interrupt bit EMI should also be cleared

before a write cycle is executed and then re-enabled after the write cycle starts. Note that the device

should not enter the IDLE or SLEEP mode until the EEPROM read or write operation is totally

complete. Otherwise, the EEPROM read or write operation will fail.

Rev. 1.00 40 October 26, 2018 Rev. 1.00 41 October 26, 2018

BS86DH12C High Voltage Touch A/D Flash MCU with HVIO

Programming Examples

Reading data from the EEPROM – polling method

MOV A,EEPROM_ADRES   ;userdenedaddress MOV EEA,A MOVA,040H;setmemorypointerMP1L MOV MP1L,A     ;MP1LpointstoEECregister MOV A,01H      ;setmemorypointerMP1H MOV MP1H,A SET IAR1.1      ;setRDENbit,enablereadoperations SETIAR1.0;startReadCycle-setRDbit

BACK:

SZIAR1.0;checkforreadcycleend JMP BACK CLR IAR1      ;disableEEPROMreadifnomorereadoperationsarerequired CLR MP1H MOV A,EED     ;movereaddatatoregister MOV READ_DATA,A

Note: For each read operation, the address register should be re-specied followed by setting the RD

bit high to activate a read cycle even if the target address is consecutive.

Writing Data to the EEPROM – polling method

MOV A,EEPROM_ADRES   ;userdenedaddress MOV EEA,A MOV A,EEPROM_DATA   ;userdeneddata MOV EED,A MOVA,040H;setmemorypointerMP1L MOV MP1L,A     ;MP1LpointstoEECregister MOV A,01H      ;setmemorypointerMP1H MOV MP1H,A CLR EMI SET IAR1.3      ;setWRENbit,enablewriteoperations SET IAR1.2     ;startWriteCycle-setWRbit–executedimmediately  ;aftersettingWRENbit SET EMI

BACK:

SZIAR1.2;checkforwritecycleend JMP BACK

CLR MP1H

Oscillators

Various oscillator types offer the user a wide range of functions according to their various application

requirements. The exible features of the oscillator functions ensure that the best optimisation can

be achieved in terms of speed and power saving. Oscillator selections and operation are selected

through a combination of conguration options and relevant control registers.

Oscillator Overview

In addition to being the source of the main system clock the oscillators also provide clock sources

for the Watchdog Timer and Time Base Interrupts. External oscillator requiring some external

components and fully integrated internal oscillators requiring no external components, are provided

to form a wide range of both fast and slow system oscillators. The higher frequency oscillators

provide higher performance but carry with it the disadvantage of higher power requirements, while

the opposite is of course true for the lower frequency oscillators. With the capability of dynamically

switching between fast and slow system clock, the device has the flexibility to optimize the

performance/power ratio, a feature especially important in power sensitive portable applications.

BS86DH12C

High Voltage Touch A/D Flash MCU with HVIO

Type Name Frequency Pins

Internal High Speed RC HIRC 8/12/16MHz —

Internal Low Speed RC LIRC 32kHz —

External Low Speed Crystal LXT 32.768kHz XT1/XT2

Oscillator Types

System Clock Congurations

There are three methods of generating the system clock, one high speed oscillator and two low speed

oscillators. The high speed oscillator is the internal 8/12/16MHz RC oscillator, HIRC. The two low

speed oscillators are the internal 32kHz RC oscillator, LIRC, and the external 32.768kHz crystal

oscillator, LXT. Selecting whether the low or high speed oscillator is used as the system oscillator

is implemented using the CKS2~CKS0 bits in the SCC register and as the system clock can be

dynamically selected.

The actual source clock used for the low speed oscillators is chosen via the FSS bit in the SCC

CKS2~CKS0 bits in the SCC register. Note that two oscillator selections must be made namely one

high speed and one low speed system oscillators. It is not possible to choose a no-oscillator selection

for either the high or low speed oscillator.

Rev. 1.00 42 October 26, 2018 Rev. 1.00 43 October 26, 2018

BS86DH12C High Voltage Touch A/D Flash MCU with HVIO

High Speed

Oscillator

HIRCEN

HIRC

Low Speed

Oscillators

LXT

LIRC

IDLE0

SLEEP

IDLE2

SLEEP

FSS

System Clock Congurations

Internal High Speed RC Oscillator – HIRC

The internal RC oscillator is a fully integrated system oscillator requiring no external components. The internal RC oscillator has three fixed frequencies of 8MHz, 12MHz and 16MHz, which is

selected using a conguration option. The HIRC1~HIRC0 bits in the HIRCC register must also be congured to match the selected conguration option frequency. Setting up these bits is necessary to ensure that the HIRC frequency accuracy specied in the A.C. Characteristics is achieved. Device

trimming during the manufacturing process and the inclusion of internal frequency compensation

circuits are used to ensure that the inuence of the power supply voltage, temperature and process

variations on the oscillation frequency are minimised. Note that this internal system clock option requires no external pins for its operation.

Prescaler

fH/2

fH/4

fH/8

fH/16

fH/32

fH/64

SUB

CKS2~CKS0

SYS

SUB

LIRC

Internal 32kHz Oscillator – LIRC

The Internal 32 kHz System Oscillator is one of the low frequency oscillator choices, which is selected by the FSS bit in the SCC register. It is a fully integrated RC oscillator with a typical frequency of 32kHz, requiring no external components for its implementation. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are

used to ensure that the inuence of the power supply voltage, temperature and process variations on

the oscillation frequency are minimised.

External 32.768 kHz Crystal Oscillator – LXT

The External 32.768 kHz Crystal System Oscillator is one of the low frequency oscillator choices,

which is selected by the FSS bit in the SCC register. This clock source has a xed frequency of

32.768 kHz and requires a 32.768 kHz crystal to be connected between pins XT1 and XT2. The external resistor and capacitor components connected to the 32.768 kHz crystal are necessary to provide oscillation. For applications where precise frequencies are essential, these components may be required to provide frequency compensation due to different crystal manufacturing tolerances. During power-up there is a time delay associated with the LXT oscillator waiting for it to start-up.

When the microcontroller enters the SLEEP or IDLE Mode, the system clock is switched off to stop microcontroller activity and to conserve power. However, in many microcontroller applications it may be necessary to keep the internal timers operational even when the microcontroller is in the SLEEP or IDLE Mode. To do this, another clock, independent of the system clock, must be provided.

BS86DH12C

High Voltage Touch A/D Flash MCU with HVIO

However, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, C1 and C2. The exact values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturer’s specification. The external parallel feedback resistor, RP, is required.

The pin-shared function selection bits determine if the XT1/XT2 pins are used for the LXT oscillator or as I/O or other pin-shared functions.

• If the LXT oscillator is not used for any clock source, the XT1/XT2 pins can be used as normal I/O or other pin-shared functions.

• If the LXT oscillator is used for any clock source, the 32.768 kHz crystal should be connected to the XT1/XT2 pins.

For oscillator stability and to minimise the effects of noise and crosstalk, it is important to ensure that the crystal and any associated resistors and capacitors along with interconnecting lines are all located as close to the MCU as possible.

32.768kHz

Note: 1. RP, C1 and C2 are required.

2. Although not shown pins have a parasitic capacitance of around 7pF.

External LXT Oscillator

LXT Oscillator C1 and C2 Values

Crystal Frequency C1 C2

32.768kHz 10pF 10pF

Note: 1. C1 and C2 values are for guidance only.

2. RP=5M~10MΩ is recommended.

32.768kHz Crystal Recommended Capacitor Values

XT1

XT2

Internal Oscillator Circuit

Internal RC Oscillator

To internal circuits

LXT Oscillator Low Power Function

The LXT oscillator can function in one of two modes, the Quick Start Mode and the Low Power

Mode. The mode selection is executed using the LXTSP bit in the LXTC register.

LXTSP LXT Operating Mode

0 Low Power

1 Quick Start

Setting the LXTSP bit high will enable the LXT Quick Start mode. In the Quick Start Mode the LXT

oscillator will power up and stabilise quickly. However, after the LXT oscillator has fully powered

up it can be placed into the Low power mode by clearing the LXTSP bit to zero. The oscillator will

continue to run but with reduced current consumption, as the higher current consumption is only

required during the LXT oscillator start-up. It is important to note that the LXT operating mode

switching must be properly controlled before the LXT oscillator clock is selected as the system

clock source. Once the LXT oscillator clock is selected as the system clock source using the CKS bit

eld and FSS bit in the SCC register, the LXT oscillator operating mode can not be changed.

It should be noted that, no matter what condition the LXTSP bit is set to, the LXT oscillator will

always function normally. The only difference is that it will take more time to start up if in the

Low-power mode.

Rev. 1.00 44 October 26, 2018 Rev. 1.00 45 October 26, 2018

BS86DH12C High Voltage Touch A/D Flash MCU with HVIO

Operating Modes and System Clocks

Present day applications require that their microcontrollers have high performance but often still

demand that they consume as little power as possible, conicting requirements that are especially

true in battery powered portable applications. The fast clocks required for high performance will

by their nature increase current consumption and of course vice versa, lower speed clocks reduce

current consumption. As Holtek has provided the device with both high and low speed clock sources

and the means to switch between them dynamically, the user can optimise the operation of their

microcontroller to achieve the best performance/power ratio.

System Clocks

The device has many different clock sources for both the CPU and peripheral function operation. By

providing the user with a wide range of clock options using register programming, a clock system

can be congured to obtain maximum application performance.

The main system clock can come from a high frequency fH or low frequency f

selected using the CKS2~CKS0 bits in the SCC register. The high speed system clock is sourced

from the HIRC oscillator. The low speed system clock source can be sourced from the internal clock

. If f

SUB

conguring the FSS bit in the SCC register. The other choice, which is a divided version of the high

speed system oscillator has a range of fH/2~fH/64.

is selected then it can be sourced by either the LXT or LIRC oscillator, selected via

SUB

source, and is

SUB

HIRCEN

High Speed

Oscillator

HIRC

Low Speed

Oscillators

LXT

LIRC

FSS

LIRC

SLEEP

IDLE2

SLEEP

WDT

Prescaler

SUB

SYS

CLKSEL[1:0]

PSC

Prescaler

fH/2

fH/4

fH/8

fH/16

fH/32

fH/64

SUB

CKS2~CKS0

Device Clock Congurations

Note: When the system clock source f

is switched to f

SYS

from fH, the high speed oscillator can be stopped to

SUB

conserve the power or continue to oscillate to provide the clock source, fH ~ fH/64, for peripheral circuits to

use, which is determined by conguring the corresponding high speed oscillator enable control bit.

Time Base

SYS

SUB

System Operation Modes

There are six different modes of operation for the microcontroller, each one with its own

special characteristics and which can be chosen according to the specific performance and

power requirements of the application. There are two modes allowing normal operation of the

microcontroller, the FAST Mode and SLOW Mode. The remaining four modes, the SLEEP, IDLE0,

IDLE1 and IDLE2 Mode are used when the microcontroller CPU is switched off to conserve power.

Operation

Mode

FAST On x x 000~110 fH~fH/64 On On On

SLOW On x x 111 f

IDLE0 Off 0 1

IDLE1 Off 1 1 xxx On On On On

IDLE2 Off 1 0

SLEEP Off 0 0 xxx Off Off Off On

Note: 1. The fH clock will be switched on or off by conguring the corresponding oscillator enable

2. In the SLEEP mode, the f

CPU

bit in the SLOW mode.

BS86DH12C

High Voltage Touch A/D Flash MCU with HVIO

FHIDEN FSIDEN CKS2~CKS0

000~110 Off

111 On

000~110 On

111 Off

clock is on as the WDT function is always enabled.

LIRC

SYS

SUB

On/Off

Off On On

On Off On

(1)

SUB

On On

“x”: don’t care

LIRC

(2)

FAST Mode

This is one of the main operating modes where the microcontroller has all of its functions

operational and where the system clock is provided by the high speed oscillator. This mode operates

allowing the microcontroller to operate normally with a clock source coming from the HIRC

oscillator. The high speed oscillator will however rst be divided by a ratio ranging from 1 to 64,

the actual ratio being selected by the CKS2~CKS0 bits in the SCC register. Although a high speed

oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current.

SLOW Mode

This is also a mode where the microcontroller operates normally although now with a slower speed

clock source. The clock source used will be from f

SUB

. The f

clock is derived from either the

SUB

LIRC or LXT oscillator determined by the FSS bit in the SCC register.

SLEEP Mode

The SLEEP Mode is entered when an HALT instruction is executed and when the FHIDEN and

FSIDEN bit are low. In the SLEEP mode the CPU will be stopped. The f

peripheral function will also be stopped, too. However the f

clock continues to operate as the

LIRC

clock provided to the

SUB

WDT function is enabled.

IDLE0 Mode

The IDLE0 Mode is entered when an HALT instruction is executed and when the FHIDEN bit in the

SCC register is low and the FSIDEN bit in the SCC register is high. In the IDLE0 Mode the CPU

will be switched off but the low speed oscillator will be on to drive some peripheral functions.

IDLE1 Mode

The IDLE1 Mode is entered when an HALT instruction is executed and when the FHIDEN bit in the

SCC register is high and the FSIDEN bit in the SCC register is high. In the IDLE1 Mode the CPU

will be switched off but both the high and low speed oscillators will be on to provide a clock source

to keep some peripheral functions operational.

Rev. 1.00 46 October 26, 2018 Rev. 1.00 47 October 26, 2018

BS86DH12C High Voltage Touch A/D Flash MCU with HVIO

IDLE2 Mode

The IDLE2 Mode is entered when an HALT instruction is executed and when the FHIDEN bit in the

SCC register is high and the FSIDEN bit in the SCC register is low. In the IDLE2 Mode the CPU

will be switched off but the high speed oscillator will be on to provide a clock source to keep some

peripheral functions operational.

Control Registers

The registers, SCC, HIRCC and LXTC, are used to control the system clock and the corresponding

oscillator congurations.

Name

SCC CKS2 CKS1 CKS0 — — FSS FHIDEN FSIDEN

HIRCC — — — — HIRC1 HIRC0 HIRCF HIRCEN

LXTC — — — — — LXTSP LXTF LXTEN

7 6 5 4 3 2 1 0

System Operating Mode Control Register List

• SCC Register

Bit 7 6 5 4 3 2 1 0

Name CKS2 CKS1 CKS0 — — FSS FHIDEN FSIDEN

R/W R/W R/W R/W — — R/W R/W R/W

POR 0 0 0 — — 0 0 0

Bit

Bit 7~5 CKS2~CKS0: System clock selection

000: f

001: fH/2 010: fH/4 011: fH/8 100: fH/16 101: fH/32 110: fH/64 111: f

SUB

These three bits are used to select which clock is used as the system clock source. In addition to the system clock source directly derived from fH or f

, a divided version

SUB

of the high speed system oscillator can also be chosen as the system clock source.

Bit 4~3 Unimplemented, read as “0”

Bit 2 FSS: Low frequency clock selection

0: LIRC 1: LXT

Bit 1 FHIDEN: High frequency oscillator control when CPU is switched off

0: Disable 1: Enable

This bit is used to control whether the high speed oscillator is activated or stopped when the CPU is switched off by executing an “HALT” instruction.

Bit 0 FSIDEN: Low frequency oscillator control when CPU is switched off

0: Disable 1: Enable

This bit is used to control whether the low speed oscillator is activated or stopped when the CPU is switched off by executing an “HALT” instruction.

BS86DH12C

High Voltage Touch A/D Flash MCU with HVIO

• HIRCC Register

Bit 7 6 5 4 3 2 1 0

Name — — — — HIRC1 HIRC0 HIRCF HIRCEN

R/W — — — — R/W R/W R R/W

POR — — — — 0 0 0 1

Bit 7~4 Unimplemented, read as “0”

Bit 3~2 HIRC1~HIRC0: HIRC frequency selection

00: 8MHz 01: 12MHz 10: 16MHz 11: 8MHz

When the HIRC oscillator is enabled or the HIRC frequency selection is changed by application program, the clock frequency will automatically be changed after the

HIRCF ag is set to 1.

It is recommended that the HIRC frequency selected by these two bits should be the

same with the frequency determined by the conguration option to achieve the HIRC frequency accuracy specied in the A.C. Characteristics.

Bit 1 HIRCF: HIRC oscillator stable ag

0: Unstable 1: Stable

This bit is used to indicate whether the HIRC oscillator is stable or not. When the HIRCEN bit is set to 1 to enable the HIRC oscillator, the HIRCF bit will first be cleared to 0 and then set to 1 after the HIRC oscillator is stable.

Bit 0 HIRCEN: HIRC oscillator enable control

0: Disable 1: Enable

• LXTC Register

Bit 7 6 5 4 3 2 1 0

Name — — — — — LXTSP LXTF LXTEN

R/W — — — — — R/W R R/W

POR — — — — — 0 0 0

Bit 7~3 Unimplemented, read as “0”

Bit 2 LXTSP: LXT oscillator quick start control

0: Disable – Low Power 1: Enable – Quick Start

This bit is used to control whether the LXT oscillator is operating in the low power or quick start mode. When the LXTSP bit is set to 1, the LXT oscillator will oscillate quickly but consume more power. If the LXTSP bit is cleared to 0, the LXT oscillator will consume less power but take longer time to stablise. It is important to note that this bit can not be changed after the LXT oscillator is selected as the system clock source using the CKS2~CKS0 and FSS bits in the SCC register.

Bit 1 LXTF: LXT oscillator stable ag

0: Unstable 1: Stable

This bit is used to indicate whether the LXT oscillator is stable or not. When the

LXTEN bit is set to 1 to enable the LXT oscillator, the LXTF bit will rst be cleared

to 0 and then set to 1 after the LXT oscillator is stable.

Bit 0 LXTEN: LXT oscillator enable control

0: Disable 1: Enable

Rev. 1.00 48 October 26, 2018 Rev. 1.00 49 October 26, 2018

BS86DH12C High Voltage Touch A/D Flash MCU with HVIO

Operating Mode Switching

The device can switch between operating modes dynamically allowing the user to select the best

performance/power ratio for the present task in hand. In this way microcontroller operations that

do not require high performance can be executed using slower clocks thus requiring less operating

current and prolonging battery life in portable applications.

In simple terms, mode switching between the FAST Mode and SLOW Mode is executed using the

CKS2~CKS0 bits in the SCC register while mode switching from the FAST/SLOW Mode to the

SLEEP/IDLE Mode is executed via the HALT instruction. When an HALT instruction is executed,

whether the device enters the IDLE Mode or the SLEEP Mode is determined by the condition of the

FHIDEN and FSIDEN bits in the SCC register.

SLEEP

HALT instruction executed

CPU stop FHIDEN=0 FSIDEN=0

off

SUB

FAST

/64

SYS=fH~fH

CPU run

SYS

SUB

IDLE2

HALT instruction executed

CPU stop FHIDEN=1 FSIDEN=0

off

SUB

SLOW

SYS=fSUB

SUB

CPU run

SYS

on/off

IDLE1

HALT instruction executed

CPU stop FHIDEN=1 FSIDEN=1

SUB

HALT instruction executed

IDLE0

CPU stop

FHIDEN=0

FSIDEN=1

off

SUB

BS86DH12C

High Voltage Touch A/D Flash MCU with HVIO

FAST Mode to SLOW Mode Switching

When running in the FAST Mode, which uses the high speed system oscillator, and therefore

consumes more power, the system clock can switch to run in the SLOW Mode by set the

CKS2~CKS0 bits to “111” in the SCC register. This will then use the low speed system oscillator

which will consume less power. Users may decide to do this for certain operations which do not

require high performance and can subsequently reduce power consumption.

The SLOW Mode is sourced from the LXT or LIRC oscillator determined by the FSS bit in the SCC

FAST Mode

CKS2~CKS0 = 111

SLOW Mode

FHIDEN=0, FSIDEN=0 HALT instruction is executed

SLEEP Mode

FHIDEN=0, FSIDEN=1 HALT instruction is executed

IDLE0 Mode

FHIDEN=1, FSIDEN=1 HALT instruction is executed

FHIDEN=1, FSIDEN=0 HALT instruction is executed

IDLE2 Mode

IDLE1 Mode

Rev. 1.00 50 October 26, 2018 Rev. 1.00 51 October 26, 2018

BS86DH12C High Voltage Touch A/D Flash MCU with HVIO

SLOW Mode to FAST Mode Switching

In SLOW mode the system clock is derived from f

FAST mode from f

, the CKS2~CKS0 bits should be set to “000”~“110” and then the system

SUB

clock will respectively be switched to fH~fH/64.

However, if fH is not used in SLOW mode and thus switched off, it will take some time to

re-oscillate and stabilise when switching to the FAST mode from the SLOW Mode. This is

monitored using the HIRCF bit in the HIRCC register. The time duration required for the high speed

system oscillator stabilization is specied in the System Start Up Time Characteristics.

FHIDEN=0, FSIDEN=0 HALT instruction is executed

FHIDEN=0, FSIDEN=1 HALT instruction is executed

. When system clock is switched back to the

SUB

CKS2~CKS0 = 000~110

IDLE0 Mode

SLOW Mode

FAST Mode

SLEEP Mode

FHIDEN=1, FSIDEN=1 HALT instruction is executed

IDLE1 Mode

FHIDEN=1, FSIDEN=0 HALT instruction is executed

IDLE2 Mode

Entering the SLEEP Mode

There is only one way for the device to enter the SLEEP Mode and that is to execute the “HALT”

instruction in the application program with both the FHIDEN and FSIDEN bits in the SCC register

equal to “0”. When this instruction is executed under the conditions described above, the following

will occur:

• The system clock will be stopped and the application program will stop at the “HALT”

instruction.

• The Data Memory contents and registers will maintain their present condition.

• The I/O ports will maintain their present conditions.

• In the status register, the Power Down ag, PDF, will be set and the Watchdog time-out ag, TO,

will be cleared.

• The WDT will be cleared and resume counting as the WDT function is always enabled.

BS86DH12C

High Voltage Touch A/D Flash MCU with HVIO

Entering the IDLE0 Mode

There is only one way for the device to enter the IDLE0 Mode and that is to execute the “HALT”

instruction in the application program with the FHIDEN bit in the SCC register equal to “0” and the

FSIDEN bit in the SCC register equal to “1”. When this instruction is executed under the conditions

described above, the following will occur:

• The fH clock will be stopped and the application program will stop at the “HALT” instruction, but

the f

clock will be on.

SUB

• The Data Memory contents and registers will maintain their present condition.

• The I/O ports will maintain their present conditions.

• In the status register, the Power Down ag, PDF, will be set and the Watchdog time-out ag, TO,

will be cleared.

• The WDT will be cleared and resume counting as the WDT function is always enabled.

Entering the IDLE1 Mode

There is only one way for the device to enter the IDLE1 Mode and that is to execute the “HALT”

instruction in the application program with both the FHIDEN and FSIDEN bits in the SCC register

equal to “1”. When this instruction is executed under the conditions described above, the following

will occur:

• The fH and f

• The Data Memory contents and registers will maintain their present condition.

• The I/O ports will maintain their present conditions.

• In the status register, the Power Down ag, PDF, will be set and the Watchdog time-out ag, TO,

will be cleared.

• The WDT will be cleared and resume counting as the WDT function is always enabled.

clocks will be on but the application program will stop at the “HALT” instruction.

SUB

Entering the IDLE2 Mode

There is only one way for the device to enter the IDLE2 Mode and that is to execute the “HALT”

instruction in the application program with the FHIDEN bit in the SCC register equal to “1” and the

FSIDEN bit in the SCC register equal to “0”. When this instruction is executed under the conditions

described above, the following will occur:

• The fH clock will be on but the f

clock will be off and the application program will stop at the

SUB

“HALT” instruction.

• The Data Memory contents and registers will maintain their present condition.

• The I/O ports will maintain their present conditions.

• In the status register, the Power Down ag, PDF, will be set and the Watchdog time-out ag, TO,

will be cleared.

• The WDT will be cleared and resume counting as the WDT function is always enabled.

Rev. 1.00 52 October 26, 2018 Rev. 1.00 53 October 26, 2018

BS86DH12C High Voltage Touch A/D Flash MCU with HVIO

Standby Current Considerations

As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the

device to as low a value as possible, perhaps only in the order of several micro-amps except in the

IDLE1 and IDLE2 Mode, there are other considerations which must also be taken into account by

the circuit designer if the power consumption is to be minimised. Special attention must be made to

the I/O pins on the device. All high-impedance input pins must be connected to either a xed high or

low level as any oating input pins could create internal oscillations and result in increased current

consumption. This also applies to the device which has different package types, as there may be

unbonded pins. These must either be set as outputs or if set as inputs must have pull-high resistors

connected.

Care must also be taken with the loads, which are connected to I/O pins, which are set as outputs.

These should be placed in a condition in which minimum current is drawn or connected only to

external circuits that do not draw current, such as other CMOS inputs. Also note that additional

standby current will also be required if the LXT or LIRC oscillator has enabled.

In the IDLE1 and IDLE2 Mode the high speed oscillator is on and if the system clock is from the

high speed system oscillator, the additional standby current will also be perhaps in the order of

several hundred micro-amps.

Wake-up

To minimise power consumption the device can enter the SLEEP or any IDLE Mode, where the

CPU will be switched off. However, when the device is woken up again, it will take a considerable

time for the original system oscillator to restart, stabilise and allow normal operation to resume.

After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources

listed as follows:

• An external falling edge on Port A

• A system interrupt

• A WDT overow

When the device executes the “HALT” instruction, it will enter the SLEEP or IDLE mode and the

PDF flag will be set high. The PDF flag will be cleared to 0 if the device experiences a system

power-up or executes the clear Watchdog Timer instruction. If the system is woken up by a WDT

overow, a Watchdog Time-out hardware reset will be initiated and the TO ag will be set to 1. The

TO ag is set if a WDT time-out occurs and causes a wake-up that only resets the Program Counter

and Stack Pointer, other ags remain in their original status.

Each pin on Port A can be set using the PAWU register to permit a negative transition on the pin

to wake-up the system. When a pin wake-up occurs, the program will resume execution at the

instruction following the “HALT” instruction. If the system is woken up by an interrupt, then two

possible situations may occur. The first is where the related interrupt is disabled or the interrupt

is enabled but the stack is full, in which case the program will resume execution at the instruction

following the “HALT” instruction. In this situation, the interrupt which woke-up the device will not

be immediately serviced, but will rather be serviced later when the related interrupt is nally enabled

or when a stack level becomes free. The other situation is where the related interrupt is enabled and

the stack is not full, in which case the regular interrupt response takes place. If an interrupt request

flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related

interrupt will be disabled.

Watchdog Timer

The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to

unknown locations, due to certain uncontrollable external events such as electrical noise.

Watchdog Timer Clock Source

The Watchdog Timer clock source is provided by the internal clock, f

the LIRC oscillator. The LIRC internal oscillator has an approximate frequency of 32kHz and this

specied internal clock period can vary with VDD, temperature and process variations. The Watchdog

Timer source clock is then subdivided by a ratio of 28 to 218 to give longer timeouts, the actual value

being chosen using the WS2~WS0 bits in the WDTC register.

Watchdog Timer Control Register

A single register, WDTC, controls the required time-out period as well as the enable and reset MCU

operation.

• WDTC Register

Bit 7 6 5 4 3 2 1 0

Name WE4 WE3 WE2 WE1 WE0 WS2 WS1 WS0

R/W R/W R/W R/W R/W R/W R/W R/W R/W

POR 0 1 0 1 0 0 1 1

BS86DH12C

High Voltage Touch A/D Flash MCU with HVIO

which is sourced from

LIRC

Bit 7~3 WE4~WE0: WDT function control

10101 or 01010: Enable Other values: Reset MCU

When these bits are changed to any other values due to environmental noise the microcontroller will be reset; this reset operation will be activated after a delay time, t

, and the WRF bit in the RSTFC register will be set high.

SRESET

Bit 2~0 WS2~WS0: WDT time-out period selection

000: 28/f 001: 210/f 010: 212/f 011: 214/f 100: 215/f 101: 216/f 110: 217/f 111: 218/f

LIRC

These three bits determine the division ratio of the Watchdog Timer source clock, which in turn determines the time-out period.

• RSTFC Register

Bit 7 6 5 4 3 2 1 0

Name — — — — RSTF LVRF LRF WRF

R/W — — — — R/W R/W R/W R/W

POR — — — — 0 x 0 0

Bit 7~4 Unimplemented, read as “0”

Bit 3 RSTF: Reset control register software reset ag

Described elsewhere

Bit 2 LVRF: LVR function reset ag

Described elsewhere

“x”: unknown

Rev. 1.00 54 October 26, 2018 Rev. 1.00 55 October 26, 2018

BS86DH12C High Voltage Touch A/D Flash MCU with HVIO

Bit 1 LRF: LVRC register software reset ag

Described elsewhere

Bit 0 WRF: WDTC register software reset ag

0: Not occurred 1: Occurred

This bit is set high by the WDTC register software reset and cleared to zero by the application program. Note that this bit can only be cleared to zero by the application program.

Watchdog Timer Operation

The Watchdog Timer operates by providing a device reset when its timer overows. This means

that in the application program and during normal operation the user has to strategically clear the

Watchdog Timer before it overows to prevent the Watchdog Timer from executing a reset. This is

done using the clear watchdog instruction. If the program malfunctions for whatever reason, jumps

to an unknown location, or enters an endless loop, the clear instruction will not be executed in the

correct manner, in which case the Watchdog Timer will overow and reset the device. There are ve

bits, WE4~WE0, in the WDTC register to offer the enable control and reset control of the Watchdog

Timer. The WDT function will be enabled if the WE4~WE0 bits are equal to 10101B or 01010B.

If the WE4~WE0 bits are set to any other values, other than 01010B and 10101B, it will reset the

device after a delay time, t

. After power on these bits will have a value of 01010B.

SRESET

WE4~WE0 Bits WDT Function

01010B or 10101B Enable

Any other value Reset MCU

Watchdog Timer Enable/Reset Control

Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set

the status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer

time-out occurs, the TO bit in the STATUS register will be set and only the Program Counter and

Stack Pointer will be reset. Three methods can be adopted to clear the contents of the Watchdog

Timer. The rst is a WDTC register software reset, which means a certain value except 01010B and

10101B written into the WE4~WE0 bits, the second is using the Watchdog Timer software clear

instruction and the third is via a HALT instruction.

There is only one method of using software instruction to clear the Watchdog Timer. That is to use

the single “CLR WDT” instruction to clear the WDT.

The maximum time-out period is when the 218 division ratio is selected. As an example, with a

32kHz LIRC oscillator as its source clock, this will give a maximum watchdog period of around 8s

for the 218 division ratio, and a minimum timeout of 8ms for the 28 division ration.

WE4~WE0 bitsWDTC Register Reset MCU

“CLR WDT” Instruction

“HALT” Instruction

LIRC 8-stage Divider WDT Prescaler

LIRC

CLR

LIRC

Watchdog Timer

8-to-1 MUXWS2~WS0

WDT Time-out

~ 218/f

LIRC

)

Reset and Initialisation

A reset function is a fundamental part of any microcontroller ensuring that the device can be set

to some predetermined condition irrespective of outside parameters. The most important reset

condition is after power is rst applied to the microcontroller. In this case, internal circuitry will

ensure that the microcontroller, after a short delay, will be in a well-defined state and ready to

execute the rst program instruction. After this power-on reset, certain important internal registers

will be set to dened states before the program commences. One of these registers is the Program

Counter, which will be reset to zero forcing the microcontroller to begin program execution from the

lowest Program Memory address.

In addition to the power-on reset, another reset exists in the form of a Low Voltage Reset, LVR,

where a full reset is implemented in situations where the power supply voltage falls below a

certain threshold. Another type of reset is when the Watchdog Timer overflows and resets the

microcontroller. All types of reset operations result in different register conditions being set.

Reset Functions

There are several ways in which a microcontroller reset can occur, through events occurring

internally.

Power-on Reset

The most fundamental and unavoidable reset is the one that occurs after power is rst applied to

the microcontroller. As well as ensuring that the Program Memory begins execution from the rst

memory address, a power-on reset also ensures that certain other registers are preset to known

conditions. All the I/O port and port control registers will power up in a high condition ensuring that

all pins will be rst set to inputs.

BS86DH12C

High Voltage Touch A/D Flash MCU with HVIO

Power-on Reset

SST Time-out

Power-On Reset Timing Chart

RSTD

Internal Reset Control

There is an internal reset control register, RSTC, which is used to provide a reset when the device

operates abnormally due to the environmental noise interference. If the content of the RSTC register

is set to any value other than 01010101B or 10101010B, it will reset the device after a delay time,

. After power on the register will have a value of 01010101B.

SRESET

RSTC7~RSTC0 Bits Reset Function

01010101B No operation

10101010B No operation

Any other value Reset MCU

Internal Reset Function Control

Rev. 1.00 56 October 26, 2018 Rev. 1.00 57 October 26, 2018

BS86DH12C High Voltage Touch A/D Flash MCU with HVIO

• RSTC Register

Bit 7 6 5 4 3 2 1 0

Name RSTC7 RSTC6 RSTC5 RSTC4 RSTC3 RSTC2 RSTC1 RSTC0

R/W R/W R/W R/W R/W R/W R/W R/W R/W

POR 0 1 0 1 0 1 0 1

Bit 7~0 RSTC7~RSTC0: Reset function control

01010101: No operation 10101010: No operation Other values: Reset MCU

If these bits are changed due to adverse environmental conditions, the microcontroller will be reset. The reset operation will be activated after a delay time, t RSTF bit in the RSTFC register will be set to 1.

• RSTFC Register

Bit 7 6 5 4 3 2 1 0

Name — — — — RSTF LVRF LRF WRF

R/W — — — — R/W R/W R/W R/W

POR — — — — 0 x 0 0

Bit 7~4 Unimplemented, read as “0”

Bit 3 RSTF: RSTC register software reset ag

0: Not occurred 1: Occurred

This bit is set to 1 by the RSTC control register software reset and cleared to zero by the application program. Note that this bit can only be cleared to zero by the application program.

Bit 2 LVRF: LVR function reset ag

Described elsewhere

Bit 1 LRF: LVRC register software reset ag

Described elsewhere

Bit 0 WRF: WDTC register software reset ag

Described elsewhere

, and the

SRESET

“x”: unknown

Low Voltage Reset – LVR

The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of

the device. The LVR function is always enabled in the FAST and SLOW modes with a specic LVR

voltage, V

. If the supply voltage of the device drops to within a range of 0.9V~V

LVR

such as might

LVR

occur when changing the battery, the LVR will automatically reset the device internally and the

LVRF bit in the RSTFC register will also be set to 1. For a valid LVR signal, a low supply voltage,

i.e., a voltage in the range between 0.9V~V

in the LVD/LVR Electrical Characteristics. If the low supply voltage state does not exceed this

LVR

must exist for a time greater than that specied by

LVR

value, the LVR will ignore the low supply voltage and will not perform a reset function. The actual

value can be selected by the LVS bits in the LVRC register. If the LVS7~LVS0 bits have any

LVR

other value, which may perhaps occur due to adverse environmental conditions such as noise, the

LVR will reset the device after a delay time, t

. When this happens, the LRF bit in the RSTFC

SRESET

enters the SLEEP/IDLE mode.

BS86DH12C

High Voltage Touch A/D Flash MCU with HVIO

LVR

+ t

RSTD

SST

Internal Reset

Low Voltage Reset Timing Chart

• LVRC Register

Bit 7 6 5 4 3 2 1 0

Name LVS7 LVS6 LVS5 LVS4 LVS3 LVS2 LVS1 LVS0

R/W R/W R/W R/W R/W R/W R/W R/W R/W

POR 0 1 0 1 0 1 0 1

Bit 7~0 LVS7~LVS0: LVR voltage selection

01010101: 2.1V 00110011: 2.55V 10011001: 3.15V 10101010: 3.8V Other values: Generates a MCU reset – register is reset to POR value

When an actual low voltage condition occurs, as specied by the LVR voltage value

above, an MCU reset will be generated. The reset operation will be activated after the low voltage condition keeps for greater than a t contents will remain the same after such a reset occurs.

Any register value, other than the four dened register values above, will also result

in the generation of an MCU reset. The reset operation will be activated after a delay time, t

. However in this situation the register contents will be reset to the POR

SRESET

value.

time. In this situation the register

LVR

• RSTFC Register

Bit 7 6 5 4 3 2 1 0

Name — — — — RSTF LVRF LRF WRF

R/W — — — — R/W R/W R/W R/W

POR — — — — 0 x 0 0

Bit 7~4 Unimplemented, read as “0”

Bit 3 RSTF: RSTC register software reset ag

Described elsewhere

Bit 2 LVRF: LVR function reset ag

0: Not occurred 1: Occurred

This bit is set to 1 when a specic low voltage reset condition occurs. Note that this bit

can only be cleared to 0 by the application program.

Bit 1 LRF: LVR control register software reset ag

0: Not occurred 1: Occurred

This bit is set to 1 by the LVRC control register contains any undened LVR voltage

register values. This in effect acts like a software-reset function. Note that this bit can only be cleared to 0 by the application program.

Bit 0 WRF: WDT control register software reset ag

Described elsewhere

“x”: unknown

Rev. 1.00 58 October 26, 2018 Rev. 1.00 59 October 26, 2018

BS86DH12C High Voltage Touch A/D Flash MCU with HVIO

Watchdog Time-out Reset during Normal Operation

The Watchdog time-out ag TO will be set to “1” when Watchdog time-out Reset during normal

operation.

WDT Time-out

Internal Reset

WDT Time-out Reset during Normal Operation Timing Chart

Watchdog Time-out Reset during SLEEP or IDLE Mode

The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds

of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack

Pointer will be cleared to “0” and the TO ag will be set to “1”. Refer to the System Start Up Time

Characteristics for t

details.

SST

WDT Time-out

SST

Internal Reset

WDT Time-out Reset during SLEEP or IDLE Mode Timing Chart

RSTD

+ t

SST

Reset Initial Conditions

The different types of reset described affect the reset ags in different ways. These ags, known

as PDF and TO are located in the status register and are controlled by various microcontroller

operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags are

shown in the table:

TO PDF Reset Conditions

0 0 Power-on reset

u u LVR reset during FAST or SLOW Mode operation

1 u WDT time-out reset during FAST or SLOW Mode operation

1 1 WDT time-out reset during IDLE or SLEEP Mode operation

The following table indicates the way in which the various components of the microcontroller are

affected after a power-on reset occurs.

Program Counter Reset to zero

Interrupts All interrupts will be disabled

WDT, Time Bases Cleared after reset, WDT begins counting

Timer Modules Timer Modules will be turned off

Input/Output Ports I/O ports will be set as inputs

Stack Pointer Stack Pointer will point to the top of the stack

“u” stands for unchanged

Item Condition after Reset

BS86DH12C

High Voltage Touch A/D Flash MCU with HVIO

The different kinds of resets all affect the internal registers of the microcontroller in different ways.

To ensure reliable continuation of normal program execution after a reset occurs, it is important to

know what condition the microcontroller is in after a particular reset occurs. The following table

describes how each type of reset affects the microcontroller internal registers. Note that where more

than one package type exists the table will reect the situation for the larger package type.

IAR0 0000 0000 0000 0000 0000 0000 uuuu uuuu

MP0 0000 0000 0000 0000 0000 0000 uuuu uuuu

IAR1 0000 0000 0000 0000 0000 0000 uuuu uuuu

MP1L 0000 0000 0000 0000 0000 0000 uuuu uuuu

MP1H 0000 0000 0000 0000 0000 0000 uuuu uuuu

ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu

PCL 0000 0000 0000 0000 0000 0000 0000 0000

TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu

TBLH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu

TBHP ---x xxxx ---u uuuu ---u uuuu ---u uuuu

STATUS xx00 xxxx uuuu uuuu uu1u uuuu uu11 uuuu

IAR2 0000 0000 0000 0000 0000 0000 uuuu uuuu

MP2L 0000 0000 0000 0000 0000 0000 uuuu uuuu

MP2H 0000 0000 0000 0000 0000 0000 uuuu uuuu

RSTFC ---- 0x00 ---- u1uu ---- uuuu ---- uuuu

INTC0 -000 0000 -000 0000 -000 0000 -uuu uuuu

INTC1 0000 0000 0000 0000 0000 0000 uuuu uuuu

INTC2 0000 0000 0000 0000 0000 0000 uuuu uuuu

INTC3 --00 --00 --00 --00 --00 --00 --uu --uu

PA 1111 1111 1111 1111 1111 1111 uuuu uuuu

PAC 1111 1111 1111 1111 1111 1111 uuuu uuuu

PAPU 0000 0000 0000 0000 0000 0000 uuu uuuu

PAWU 0000 0000 0000 0000 0000 0000 uuu uuuu

SLEDC0 0000 0000 0000 0000 0000 0000 uuuu uuuu

SLEDC1 ---- 0000 ---- 0000 ---- 0000 ---- uuuu

WDTC 0101 0011 0101 0011 0101 0011 uuuu uuuu

TBC 0--- -000 0--- -000 0--- -000 u--- -uuu

PSCR ---- --00 ---- --00 ---- --00 ---- --uu

LVRC 0101 0101 uuuu uuuu 0101 0101 uuuu uuuu

EEA --00 0000 --00 0000 --00 0000 --uu uuuu

EED 0000 0000 0000 0000 0000 0000 uuuu uuuu

PB 1111 1111 1111 1111 1111 1111 uuuu uuuu

PBC 1111 1111 1111 1111 1111 1111 uuuu uuuu

PBPU 0000 0000 0000 0000 0000 0000 uuuu uuuu

IICC0 ---- 000- ---- 000- ---- 000- ---- uuu-

IICC1 1000 0001 1000 0001 1000 0001 uuuu uuuu

IICD xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

IICA 0000 000- 0000 000- 0000 000- uuuu uuu-

IICTOC 0000 0000 0000 0000 0000 0000 uuuu uuuu

USR 0000 1011 0000 1011 0000 1011 uuuu uuuu

UCR1 0000 00x0 0000 00x0 0000 00x0 uuuu uuuu

UCR2 0000 0000 0000 0000 0000 0000 uuuu uuuu

LVR Reset

(Normal Operation)

WDT Time-out

(Normal Operation)

WDT Time-out

(IDLE/SLEEP)

Rev. 1.00 60 October 26, 2018 Rev. 1.00 61 October 26, 2018

BS86DH12C High Voltage Touch A/D Flash MCU with HVIO

TXR_RXR xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

BRG xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

SADOL xxxx ---- xxxx ---- xxxx ----

SADOH xxxx xxxx xxxx xxxx xxxx xxxx

SADC0 0000 0000 0000 0000 0000 0000 uuuu uuuu

SADC1 0000 0000 0000 0000 0000 0000 uuuu uuuu

INTEG ---- --00 ---- --00 ---- --00 ---- --uu

IFS0 --00 0000 --00 0000 --00 0000 --uu uuuu

IFS1 ---- 0000 ---- 0000 ---- 0000 ---- uuuu

LVDC --00 0000 --00 0000 --00 0000 --uu uuuu

SCC 000- -000 000- -000 000- -000 uuu- -uuu

HIRCC ---- 0001 ---- 0001 ---- 0001 ---- uuuu

LXTC ---- -000 ---- -000 ---- -000 ---- -uuu

PC -- 11 1111 -- 11 1111 - -11 1111 --uu uuuu

PCC --11 1111 --11 1111 -- 11 1111 --uu uuuu

PCPU --00 0000 --00 0000 --00 0000 --uu uuuu

MFI0 0000 0000 0000 0000 0000 0000 uuuu uuuu

MFI1 --00 --00 --00 --00 --00 --00 --uu --uu

PD -- 11 1111 -- 11 1111 - -11 1111 --uu uuuu

PDC --11 1111 --11 1111 -- 11 1111 --uu uuuu

PDOM --00 0000 --00 0000 --00 0000 --uu uuuu

PWRDET x--- ---0 u--- ---0 u--- ---0 u--- ---u

RSTC 0101 0101 0101 0101 0101 0101 uuuu uuuu

TKTMR 0000 0000 0000 0000 0000 0000 uuuu uuuu

TKC0 -000 0000 -000 0000 -000 0000 -uuu uuuu

TK16DL 0000 0000 0000 0000 0000 0000 uuuu uuuu

TK16DH 0000 0000 0000 0000 0000 0000 uuuu uuuu

TKC1 ---- --11 ---- --11 ---- --11 ---- --uu

TKM016DL 0000 0000 0000 0000 0000 0000 uuuu uuuu

TKM016DH 0000 0000 0000 0000 0000 0000 uuuu uuuu

TKM0ROL 0000 0000 0000 0000 0000 0000 uuuu uuuu

TKM0ROH ---- --00 ---- --00 ---- --00 ---- --uu

TKM0C0 0000 0000 0000 0000 0000 0000 uuuu uuuu

TKM0C1 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu

TKM116DL 0000 0000 0000 0000 0000 0000 uuuu uuuu

TKM116DH 0000 0000 0000 0000 0000 0000 uuuu uuuu

TKM1ROL 0000 0000 0000 0000 0000 0000 uuuu uuuu

TKM1ROH ---- --00 ---- --00 ---- --00 ---- --uu

TKM1C0 0000 0000 0000 0000 0000 0000 uuuu uuuu

TKM1C1 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu

TKM216DL 0000 0000 0000 0000 0000 0000 uuuu uuuu

TKM216DH 0000 0000 0000 0000 0000 0000 uuuu uuuu

LVR Reset

(Normal Operation)

WDT Time-out

(Normal Operation)

WDT Time-out

(IDLE/SLEEP)

uuuu ---

(ADRFS=0)

uuuu uuuu

(ADRFS=1)

uuuu uuuu

(ADRFS=0)

---- uuuu (ADRFS=1)

BS86DH12C

High Voltage Touch A/D Flash MCU with HVIO

TKM2ROL 0000 0000 0000 0000 0000 0000 uuuu uuuu

TKM2ROH ---- --00 ---- --00 ---- --00 ---- --uu

TKM2C0 0000 0000 0000 0000 0000 0000 uuuu uuuu

TKM2C1 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu

CTM0C0 0000 0000 0000 0000 0000 0000 uuuu uuuu

CTM0C1 0000 0000 0000 0000 0000 0000 uuuu uuuu

CTM0DL 0000 0000 0000 0000 0000 0000 uuuu uuuu

CTM0DH ---- --00 ---- --00 ---- --00 ---- --uu

CTM0AL 0000 0000 0000 0000 0000 0000 uuuu uuuu

CTM0AH ---- --00 ---- --00 ---- --00 ---- --uu

PTMC0 0000 0--- 0000 0--- 0000 0--- uuuu u---

PTMC1 0000 0000 0000 0000 0000 0000 uuuu uuuu

PTMDL 0000 0000 0000 0000 0000 0000 uuuu uuuu

PTMDH ---- --00 ---- --00 ---- --00 ---- --uu

PTMAL 0000 0000 0000 0000 0000 0000 uuuu uuuu

PTMAH ---- --00 ---- --00 ---- --00 ---- --uu

PTMRPL 0000 0000 0000 0000 0000 0000 uuuu uuuu

PTMRPH ---- --00 ---- --00 ---- --00 ---- --uu

CTM1C0 0000 0000 0000 0000 0000 0000 uuuu uuuu

CTM1C1 0000 0000 0000 0000 0000 0000 uuuu uuuu

CTM1DL 0000 0000 0000 0000 0000 0000 uuuu uuuu

CTM1DH ---- --00 ---- --00 ---- --00 ---- --uu

CTM1AL 0000 0000 0000 0000 0000 0000 uuuu uuuu

CTM1AH ---- --00 ---- --00 ---- --00 ---- --uu

OVPC0 000- -000 000- -000 000- -000 uuu- -uuu

OVPC1 0001 0000 0001 0000 0001 0000 uuuu uuuu

OVPC2 ---- 0000 ---- 0000 ---- 0000 ---- uuuu

OVPDA 0000 0000 0000 0000 0000 0000 uuuu uuuu

OCPC0 0000 ---0 0000 ---0 0000 ---0 uuuu ---u

OCPC1 --00 0000 --00 0000 --00 0000 --uu uuuu

OCPDA 0000 0000 0000 0000 0000 0000 uuuu uuuu

OCPOCAL 0010 0000 0010 0000 0010 0000 uuuu uuuu

OCPCCAL 0001 0000 0001 0000 0001 0000 uuuu uuuu

PAS0 0000 0000 0000 0000 0000 0000 uuuu uuuu

PAS1 0000 0000 0000 0000 0000 0000 uuuu uuuu

PBS0 0000 0000 0000 0000 0000 0000 uuuu uuuu

PBS1 0000 0000 0000 0000 0000 0000 uuuu uuuu

PCS0 0000 0000 0000 0000 0000 0000 uuuu uuuu

SLEDCOM0 0000 0000 0000 0000 0000 0000 uuuu uuuu

SLEDCOM1 0000 0000 0000 0000 0000 0000 uuuu uuuu

SLEDCOM2 --00 0000 --00 0000 --00 0000 --uu uuuu

EEC ---- 0000 ---- 0000 ---- 0000 ---- uuuu

LVR Reset

(Normal Operation)

WDT Time-out

(Normal Operation)

WDT Time-out

(IDLE/SLEEP)

Note: “u” stands for unchanged

“x” stands for unknown “-” stands for unimplemented

Rev. 1.00 62 October 26, 2018 Rev. 1.00 63 October 26, 2018

BS86DH12C High Voltage Touch A/D Flash MCU with HVIO

Input/Output Ports

Holtek microcontrollers offer considerable exibility on their I/O ports. With the input or output

designation of every pin fully under user program control, pull-high selections for all ports and

wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a

wide range of application possibilities.

This device provides bidirectional input/output lines. These I/O ports are mapped to the RAM Data

Memory with specic addresses as shown in the Special Purpose Data Memory table. All of these

I/O ports can be used for input and output operations. For input operation, these ports are non-

latching, which means the inputs must be ready at the T2 rising edge of instruction “MOV A, [m]”,

where “m” denotes the port address. For output operation, all the data is latched and remains

unchanged until the output latch is rewritten.

Name

PA PA 7 PA6 PA5 PA 4 PA3 PA2 PA 1 PA0

PAC PAC7 PAC6 PAC5 PAC4 PAC3 PAC2 PAC1 PAC0

PAPU PAPU7 PAPU6 PAPU5 PAPU4 PAPU3 PAPU2 PAPU1 PAPU0

PAWU PAWU7 PAWU6 PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0

PB PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0

PBC PBC7 PBC6 PBC5 PBC4 PBC3 PBC2 PBC1 PBC0

PBPU PBPU7 PBPU6 PBPU5 PBPU4 PBPU3 PBPU2 PBPU1 PBPU0

PC — — PC5 PC4 PC3 PC2 PC1 PC0

PCC — — PCC5 PCC4 PCC3 PCC2 PCC1 PCC0

PCPU — — PCPU5 PCPU4 PCPU3 PCPU2 PCPU1 PCPU0

7 6 5 4 3 2 1 0

I/O Logic Function Register List

Bit

“—”: Unimplemented, read as “0”

Pull-high Resistors

Many product applications require pull-high resistors for their switch inputs usually requiring

the use of an external resistor. To eliminate the need for these external resistors, all I/O pins,

when congured as a digital input have the capability of being connected to an internal pull-high

resistor. These pull-high resistors are selected using the relevant pull-high control registers and are

implemented using weak PMOS transistors.

Note that the pull-high resistor can be controlled by the relevant pull-high control register only when

the pin-shared functional pin is selected as a digital input or NMOS output. Otherwise, the pull-high

resistors cannot be enabled.

• PxPU Register

Bit 7 6 5 4 3 2 1 0

Name PxPU7 PxPU6 PxPU5 PxPU4 PxPU3 PxPU2 PxPU1 PxPU0

R/W R/W R/W R/W R/W R/W R/W R/W R/W

POR 0 0 0 0 0 0 0 0

PxPUn: I/O Port x Pin pull-high function control

0: Disable 1: Enable

The PxPUn bit is used to control the pin pull-high function. Here the “x” is the Port name which can be A, B or C. However, the actual available bits for each I/O Port may be different.

Port A Wake-up

The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves

power, a feature that is important for battery and other low-power applications. Various methods

exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port

A pins from high to low. This function is especially suitable for applications that can be woken up

via external switches. Each pin on Port A can be selected individually to have this wake-up feature

using the PAWU register.

Note that the wake-up function can be controlled by the wake-up control registers only when the pin

is selected as a general purpose input and the MCU enters the IDLE or SLEEP mode.

• PAWU Register

Bit 7 6 5 4 3 2 1 0

Name PAWU7 PAWU6 PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0

R/W R/W R/W R/W R/W R/W R/W R/W R/W

POR 0 0 0 0 0 0 0 0

Bit 7~0 PAWU7~PAWU0: PA7~PA0 pin Wake-up function control

BS86DH12C

High Voltage Touch A/D Flash MCU with HVIO

0: Disable 1: Enable

I/O Port Control Registers

Each I/O Port has its own control register which controls the input/output conguration. With this

control register, each I/O pin with or without pull-high resistors can be recongured dynamically

under software control. For the I/O pin to function as an input, the corresponding bit of the control

read by instructions. When the corresponding bit of the control register is written as a “0”, the I/

O pin will be set as a CMOS output. If the pin is currently set as an output, instructions can still be

used to read the output register. However, it should be noted that the program will in fact only read

the status of the output data latch and not the actual logic status of the output pin.

• PxC Register

Bit 7 6 5 4 3 2 1 0

Name PxC7 PxC6 PxC5 PxC4 PxC3 PxC2 PxC1 PxC0

R/W R/W R/W R/W R/W R/W R/W R/W R/W

POR 1 1 1 1 1 1 1 1

PxCn: I/O Port x Pin type selection

0: Output 1: Input

The PxCn bit is used to control the pin type selection. Here the “x” is the Port name which can be A, B or C. However, the actual available bits for each I/O Port may be different.

I/O Port Source Current Selection

The device supports different output source current driving capability for each I/O port. With the

selection register, SLEDCn, specic I/O port can support four levels of the source current driving

capability. These source current selection bits are available only when the corresponding pin is

configured as a CMOS output. Otherwise, these select bits have no effect. Users should refer to

the Input/Output Characteristics section to select the desired output source current for different

applications.

Rev. 1.00 64 October 26, 2018 Rev. 1.00 65 October 26, 2018

BS86DH12C High Voltage Touch A/D Flash MCU with HVIO

Name

SLEDC0 SLEDC07 SLEDC06 SLEDC05 SLEDC04 SLEDC03 SLEDC02 SLEDC01 SLEDC00

SLEDC1 — — — — SLEDC13 SLEDC12 SLEDC11 SLEDC10

7 6 5 4 3 2 1 0

I/O Port Source Current Selection Register List

Bit

• SLEDC0 Register

Bit 7 6 5 4 3 2 1 0

Name SLEDC07 SLEDC06 SLEDC05 SLEDC04 SLEDC03 SLEDC02 SLEDC01 SLEDC00

R/W R/W R/W R/W R/W R/W R/W R/W R/W

POR 0 0 0 0 0 0 0 0

Bit 7~6 SLEDC07~SLEDC06: PB7~PB4 source current selection

00: Source current=Level 0 (Min.) 01: Source current=Level 1 10: Source current=Level 2 11: Source current=Level 3 (Max.)

Bit 5~4 SLEDC05~SLEDC04: PB3~PB0 source current selection

00: Source current=Level 0 (Min.) 01: Source current=Level 1 10: Source current=Level 2 11: Source current=Level 3 (Max.)

Bit 3~2 SLEDC03~SLEDC02: PA7~PA4 source current selection

00: Source current=Level 0 (Min.) 01: Source current=Level 1 10: Source current=Level 2 11: Source current=Level 3 (Max.)

Bit 1~0 SLEDC01~SLEDC00: PA3~PA0 source current selection

00: Source current=Level 0 (Min.) 01: Source current=Level 1 10: Source current=Level 2 11: Source current=Level 3 (Max.)

• SLEDC1 Register

Bit 7 6 5 4 3 2 1 0

Name — — — — SLEDC13 SLEDC12 SLEDC11 SLEDC10

R/W — — — — R/W R/W R/W R/W

POR — — — — 0 0 0 0

Bit 7~4 Unimplemented, read as “0”

Bit 3~2 SLEDC13~SLEDC12: PC5~PC4 source current selection

00: Source current=Level 0 (Min.) 01: Source current=Level 1 10: Source current=Level 2 11: Source current=Level 3 (Max.)

Bit 1~0 SLEDC11~SLEDC10: PC3~PC0 source current selection

00: Source current=Level 0 (Min.) 01: Source current=Level 1 10: Source current=Level 2 11: Source current=Level 3 (Max.)

High Voltage Touch A/D Flash MCU with HVIO

I/O Port Sink Current Selection

The device supports different output sink current driving capability for each I/O port. With the

selection register, SLEDCOMn, specic I/O port can support two levels of the sink current driving

capability. These sink current selection bits are available when the corresponding pin is congured

as a CMOS output. Otherwise, these select bits have no effect. Users should refer to the Input/Output

Characteristics section to select the desired output sink current for different applications.

Name

SLEDCOM0 PANS7 PANS6 PANS5 PANS4 PANS3 PANS2 PANS1 PANS0

SLEDCOM1 PBNS7 PBNS6 PBNS5 PBNS4 PBNS3 PBNS2 PBNS1 PBNS0

SLEDCOM2 — — PCNS5 PCNS4 PCNS3 PCNS2 PCNS1 PCNS0

• SLEDCOM0 Register

Bit 7 6 5 4 3 2 1 0

Name PANS7 PANS6 PANS5 PANS4 PANS3 PANS2 PANS1 PANS0

R/W R/W R/W R/W R/W R/W R/W R/W R/W

POR 0 0 0 0 0 0 0 0

7 6 5 4 3 2 1 0

I/O Port Sink Current Selection Register List

BS86DH12C

Bit

Bit 7 PANS7: PA7 sink current selection

0: Sink current=Level 0 (Min.) 1: Sink current=Level 1 (Max.)

Bit 6 PANS6: PA6 sink current selection

0: Sink current=Level 0 (Min.) 1: Sink current=Level 1 (Max.)

Bit 5 PANS5: PA5 sink current selection

0: Sink current=Level 0 (Min.) 1: Sink current=Level 1 (Max.)

Bit 4 PANS4: PA4 sink current selection

0: Sink current=Level 0 (Min.) 1: Sink current=Level 1 (Max.)

Bit 3 PANS3: PA3 sink current selection

0: Sink current=Level 0 (Min.) 1: Sink current=Level 1 (Max.)

Bit 2 PANS2: PA2 sink current selection

0: Sink current=Level 0 (Min.) 1: Sink current=Level 1 (Max.)

Bit 1 PANS1: PA1 sink current selection

0: Sink current=Level 0 (Min.) 1: Sink current=Level 1 (Max.)

Bit 0 PANS0: PA0 sink current selection

0: Sink current=Level 0 (Min.) 1: Sink current=Level 1 (Max.)

Rev. 1.00 66 October 26, 2018 Rev. 1.00 67 October 26, 2018

BS86DH12C High Voltage Touch A/D Flash MCU with HVIO

• SLEDCOM1 Register

Bit 7 6 5 4 3 2 1 0

Name PBNS7 PBNS6 PBNS5 PBNS4 PBNS3 PBNS2 PBNS1 PBNS0

R/W R/W R/W R/W R/W R/W R/W R/W R/W

POR 0 0 0 0 0 0 0 0

Bit 7 PBNS7: PB7 sink current selection

0: Sink current=Level 0 (Min.) 1: Sink current=Level 1 (Max.)

Bit 6 PBNS6: PB6 sink current selection

0: Sink current=Level 0 (Min.) 1: Sink current=Level 1 (Max.)

Bit 5 PBNS5: PB5 sink current selection

0: Sink current=Level 0 (Min.) 1: Sink current=Level 1 (Max.)

Bit 4 PBNS4: PB4 sink current selection

0: Sink current=Level 0 (Min.) 1: Sink current=Level 1 (Max.)

Bit 3 PBNS3: PB3 sink current selection

0: Sink current=Level 0 (Min.) 1: Sink current=Level 1 (Max.)

Bit 2 PBNS2: PB2 sink current selection

0: Sink current=Level 0 (Min.) 1: Sink current=Level 1 (Max.)

Bit 1 PBNS1: PB1 sink current selection

0: Sink current=Level 0 (Min.) 1: Sink current=Level 1 (Max.)

Bit 0 PBNS0: PB0 sink current selection

0: Sink current=Level 0 (Min.) 1: Sink current=Level 1 (Max.)

• SLEDCOM2 Register

Bit 7 6 5 4 3 2 1 0

Name — — PCNS5 PCNS4 PCNS3 PCNS2 PCNS1 PCNS0

R/W — — R/W R/W R/W R/W R/W R/W

POR — — 0 0 0 0 0 0

Bit 7~6 Unimplemented, read as “0”

Bit 5 PCNS5: PC5 sink current selection

0: Sink current=Level 0 (Min.) 1: Sink current=Level 1 (Max.)

Bit 4 PCNS4: PC4 sink current selection

0: Sink current=Level 0 (Min.) 1: Sink current=Level 1 (Max.)

Bit 3 PCNS3: PC3 sink current selection

0: Sink current=Level 0 (Min.) 1: Sink current=Level 1 (Max.)

Bit 2 PCNS2: PC2 sink current selection

0: Sink current=Level 0 (Min.) 1: Sink current=Level 1 (Max.)

Bit 1 PCNS1: PC1 sink current selection

0: Sink current=Level 0 (Min.) 1: Sink current=Level 1 (Max.)

High Voltage Touch A/D Flash MCU with HVIO

Bit 0 PCNS0: PC0 sink current selection

0: Sink current=Level 0 (Min.) 1: Sink current=Level 1 (Max.)

Pin-shared Functions

The exibility of the microcontroller range is greatly enhanced by the use of pins that have more

than one function. Limited numbers of pins can force serious design constraints on designers but by

supplying pins with multi-functions, many of these difculties can be overcome. For these pins, the

desired function of the multi-function I/O pins is selected by a series of registers via the application

program control.

Pin-shared Function Selection Registers

The limited number of supplied pins in a package can impose restrictions on the amount of functions

a certain device can contain. However by allowing the same pins to share several different functions

and providing a means of function selection, a wide range of different functions can be incorporated

into even relatively small package sizes. The device includes Port “x” Output Function Selection

the desired functions of the multi-function pin-shared pins.

The most important point to note is to make sure that the desired pin-shared function is properly

selected and also deselected. For most pin-shared functions, to select the desired pin-shared function,

the pin-shared function should rst be correctly selected using the corresponding pin-shared control

peripheral function can be enabled. However, a special point must be noted for some digital input

pins, such as INT, xTCKn, PTPI, etc, which share the same pin-shared control conguration with

their corresponding general purpose I/O functions when setting the relevant pin-shared control bit

elds. To select these pin functions, in addition to the necessary pin-shared control and peripheral

functional setup aforementioned, they must also be set as an input by setting the corresponding bit

in the I/O port control register. To correctly deselect the pin-shared function, the peripheral function

should first be disabled and then the corresponding pin-shared function control register can be

modied to select other pin-shared functions.

Name

PAS0 PAS07 PAS06 PAS05 PAS04 PAS03 PAS02 PAS01 PAS00

PAS1 PAS17 PAS16 PAS15 PAS14 PAS13 PAS12 PA S11 PAS10

PBS0 PBS07 PBS06 PBS05 PBS04 PBS03 PBS02 PBS01 PBS00

PBS1 PBS17 PBS16 PBS15 PBS14 PBS13 PBS12 PBS11 PBS10

PCS0 PCS07 PCS06 PCS05 PCS04 PCS03 PCS02 PCS01 PCS00

IFS0 — — SDAPS1 SDAPS0 SCLPS1 SCLPS0 RXPS1 RXPS0

IFS1 — — — — PTPIPS PTCKPS CTCK1PS CTCK0PS

7 6 5 4 3 2 1 0

Pin-shared Function Selection Register List

BS86DH12C

Bit

Rev. 1.00 68 October 26, 2018 Rev. 1.00 69 October 26, 2018

BS86DH12C High Voltage Touch A/D Flash MCU with HVIO

• PAS0 Register

Bit 7 6 5 4 3 2 1 0

Name PAS07 PAS06 PAS05 PAS04 PAS03 PAS02 PAS01 PAS00

R/W R/W R/W R/W R/W R/W R/W R/W R/W

POR 0 0 0 0 0 0 0 0

Bit 7~6 PAS07~PAS06: PA3 pin-shared function selection

00: PA3/PTPI 01: SDA 10: VREF 11: KEY4

Bit 5~4 PAS05~PAS04: PA2 pin-shared function selection

00: PA2 01: TX 10: CTP1B 11: OCPI

Bit 3~2 PAS03~PAS02: PA1 pin-shared function selection

00: PA1/PTCK 01: SCL 10: OVPI1 11: KEY3

Bit 1~0 PAS01~PAS00: PA0 pin-shared function selection

00: PA0 01: RX 10: CTP1 11: OCPVR

• PAS1 Register

Bit 7 6 5 4 3 2 1 0

Name PAS17 PAS16 PAS15 PAS14 PAS13 PAS12 PAS11 PAS10

R/W R/W R/W R/W R/W R/W R/W R/W R/W

POR 0 0 0 0 0 0 0 0

Bit 7~6 PAS17~PAS16: PA7 pin-shared function selection

00: PA7/CTCK0/PTCK 01: PA7/CTCK0/PTCK 10: PTP 11: XT2

Bit 5~4 PAS15~PAS14: PA6 pin-shared function selection

00: PA6/CTCK1/PTPI 01: CTP0 10: PTPB 11: XT1

Bit 3~2 PAS13~PAS12: PA5 pin-shared function selection

00: PA5 01: PA5 10: AN1 11: KEY6

Bit 1~0 PAS11~PAS10: PA4 pin-shared function selection

00: PA4 01: PA4 10: AN0 11: KEY5

BS86DH12C

High Voltage Touch A/D Flash MCU with HVIO

• PBS0 Register

Bit 7 6 5 4 3 2 1 0

Name PBS07 PBS06 PBS05 PBS04 PBS03 PBS02 PBS01 PBS00

R/W R/W R/W R/W R/W R/W R/W R/W R/W

POR 0 0 0 0 0 0 0 0

Bit 7~6 PBS07~PBS06: PB3 pin-shared function selection

00: PB3 01: SDA 10: AN7 11: KEY10

Bit 5~4 PBS05~PBS04: PB2 pin-shared function selection

00: PB2 01: SCL 10: AN6 11: KEY9

Bit 3~2 PBS03~PBS02: PB1 pin-shared function selection

00: PB1/CTCK1 01: TX 10: OVPI0 11: KEY2

Bit 1~0 PBS01~PBS00: PB0 pin-shared function selection

00: PB0/CTCK0 01: RX 10: OCPI 11: KEY1

• PBS1 Register

Bit 7 6 5 4 3 2 1 0

Name PBS17 PBS16 PBS15 PBS14 PBS13 PBS12 PBS11 PBS10

R/W R/W R/W R/W R/W R/W R/W R/W R/W

POR 0 0 0 0 0 0 0 0

Bit 7~6 PBS17~PBS16: PB7 pin-shared function selection

00: PB7 01: CTP1B 10: AN5 11: OVPCOUT

Bit 5~4 PBS15~PBS14: PB6 pin-shared function selection

00: PB6 01: CTP1 10: AN4 11: OCPAO

Bit 3~2 PBS13~PBS12: PB5 pin-shared function selection

00: PB5 01: CTP0B 10: AN3 11: KEY8

Bit 1~0 PBS11~PBS10: PB4 pin-shared function selection

00: PB4 01: CTP0 10: AN2 11: KEY7

Rev. 1.00 70 October 26, 2018 Rev. 1.00 71 October 26, 2018

BS86DH12C High Voltage Touch A/D Flash MCU with HVIO

• PCS0 Register

Bit 7 6 5 4 3 2 1 0

Name PCS07 PCS06 PCS05 PCS04 PCS03 PCS02 PCS01 PCS00

R/W R/W R/W R/W R/W R/W R/W R/W R/W

POR 0 0 0 0 0 0 0 0

Bit 7~6 PCS07~PCS06: PC3 pin-shared function selection

00: PC3 01: CTP0 10: SDA 11: TX

Bit 5~4 PCS05~PCS04: PC2 pin-shared function selection

00: PC2 01: CTP1 10: SCL 11: RX

Bit 3~2 PCS03~PCS02: PC1 pin-shared function selection

00: PC1/INT 01: PTPB 10: OVPI1 11: KEY12

Bit 1~0 PCS01~PCS00: PC0 pin-shared function selection

00: PC0 01: PTP 10: OVPI0 11: KEY11

• IFS0 Register

Bit 7 6 5 4 3 2 1 0

Name — — SDAPS1 SDAPS0 SCLPS1 SCLPS0 RXPS1 RXPS0

R/W — — R/W R/W R/W R/W R/W R/W

POR — — 0 0 0 0 0 0

Bit 7~6 Unimplemented, read as “0”

Bit 5~4 SDAPS1~SDAPS0: SDA input source pin selection

00: PB3 01: PB3 10: PC3 11: PA3

Bit 3~2 SCLPS1~SCLPS0: SCL input source pin selection

00: PB2 01: PB2 10: PC2 11: PA1

Bit 1~0 RXPS1~RXPS0: RX input source pin selection

00: PB0 01: PB0 10: PC2 11: PA0

• IFS1 Register

Bit 7 6 5 4 3 2 1 0

Name — — — — PTPIPS PTCKPS CTCK1PS CTCK0PS

R/W — — — — R/W R/W R/W R/W

POR — — — — 0 0 0 0

Bit 7~4 Unimplemented, read as “0”

Bit 3 PTPIPS: PTPI input source pin selection

Bit 2 PTCKPS: PTCK input source pin selection

Bit 1 CTCK1PS: CTCK1 input source pin selection

Bit 0 CTCK0PS: CTCK0 input source pin selection

I/O Pin Structures

The accompanying diagram illustrates the internal structure of the I/O logic function. As the exact

logical construction of the I/O pin will differ from this drawing, it is supplied as a guide only to

assist with the functional understanding of the I/O logic function. The wide range of pin-shared

structures does not permit all types to be shown.

BS86DH12C

High Voltage Touch A/D Flash MCU with HVIO

0: PA6 1: PA3

0: PA1 1: PA7

0: PA6 1: PB1

0: PA7 1: PB0

Data Bus

Write Control Register

Chip Reset

Read Control Register

Write Data Register

Read Data Register

System Wake-up

Programming Considerations

Within the user program, one of the things first to consider is port initialisation. After a reset,

all of the I/O data and port control registers will be set high. This means that all I/O pins will be

defaulted to an input state, the level of which depends on the other connected circuitry and whether

pull-high selections have been chosen. If the port control registers are then programmed to set some

pins as outputs, these output pins will have an initial high output value unless the associated port

Pull-high

Control Bit

Data Bit

Logic Function Input/Output Structure

M U X

wake-up Select

PA only

Weak Pull-up

I/O pin

Rev. 1.00 72 October 26, 2018 Rev. 1.00 73 October 26, 2018

BS86DH12C High Voltage Touch A/D Flash MCU with HVIO

data registers are rst programmed. Selecting which pins are inputs and which are outputs can be

achieved byte-wide by loading the correct values into the appropriate port control register or by

programming individual bits in the port control register using the “SET [m].i” and “CLR [m].i”

instructions. Note that when using these bit control instructions, a read-modify-write operation takes

place. The microcontroller must rst read in the data on the entire port, modify it to the required new

bit values and then rewrite this data back to the output ports.

Port A has the additional capability of providing wake-up functions. When the device is in the SLEEP

or IDLE Mode, various methods are available to wake the device up. One of these is a high to low

transition of any of the Port A pins. Single or multiple pins on Port A can be set to have this function.

High Voltage I/O Port

The device provides several 10V high voltage input/output lines, known as PD0~PD5. These high

voltage I/O ports can convert 5V logic output signals to 10V voltage outputs to directly drive

TRIACs, relays, and buzzers.

PWRRDYF

PDn_DOUT_EN

PDOMn

PDn_DOUT

HVIO 0 ~ HVIO n

LIRC

5-stage Divider

Comparator

/32

LIRC

/16

LIRC

U X

PDn_DIN

VCC2VDD

Level

Shift

VCC2VDD

Level

Shift

Level

Shift

2-bit Counter

VCC2VDD

PWRRDY

PDn_OE

HV I/O Control

PDn

U X

PDCn

VCC2

PDn

HVSS

Read Data Register

Data Bus

To high voltage short circuit interrupt

SFRTC

High Voltage I/O Block Diagram (n=0~5)

Note: 1. The structure contained in the dash line is identical for each PDn HVIO, and the structure contained in the

solid line is shared by all HVIO lines.

2. Each symbol name with a “_” sign in the figure is a circuit node name and not the Special Function Register bit.

PDn_DOUT_EN: PDn data output enable signal

PDn_DOUT: PDn output data

BS86DH12C

High Voltage Touch A/D Flash MCU with HVIO

PDn_OE: PDn output global enable signal

PDn_DIN: PDn input data

3. When the comparison result between PDn_DOUT and PDn_DIN is different, the LIRC oscillator will be enabled by the hardware until the short circuit condition is released even if the CPU and LIRC are both off. After the LIRC clock is stable, the f functions. If the MCU is still in CPU off mode, the LIRC will be turned off after the short circuit condition has been released.

4. The PDn_OE truth table is shown as follows:

PWRRDY PWRRDYF PDOMn PDn_DOUT_EN PDn_OE

0 0 0 0 0

1 1 0 0 0

1 1 0 1 1

1 1 1 0 0

1 1 1 1 0

5. The PDn truth table is shown as follows:

PDn_OE PDn_DOUT PDn PDn Mode

0 0

0 1

1 0 V

1 1 V

Floating Input mode

Output mode (Short-circuit protection is enabled when PWRRDYF=1)

CC2

clock can be used as the clock source of the peripheral

LIRC

High Voltage I/O Registers

Overall operation of high voltage I/O port is controlled using a series of registers. The PD register

is the data register. The PDC register is used to select the input/output type. The PDOM register is

used for output mask control. The remaining register PWRDET is used to monitor the power supply

status and select short ag response time.

Name

PD — — PD5 PD4 PD3 PB2 PD1 PD0

PDC — — PDC5 PBC4 PDC3 PDC2 PDC1 PDC0

PDOM — — PDOM5 PDOM4 PDOM3 PDOM2 PDOM1 PDOM0

PWRDET PWRRDYF — — — — — — SFRTC

• PD Register

Bit 7 6 5 4 3 2 1 0

Name — — PD5 PD4 PD3 PD2 PD1 PD0

R/W — — R/W R/W R/W R/W R/W R/W

POR — — 1 1 1 1 1 1

Bit 7~6 Unimplemented, read as “0”

Bit 5~0 PD5~PD0: HVIO PD5~PD0 Data bit

7 6 5 4 3 2 1 0

Bit

High Voltage I/O Register List

Rev. 1.00 74 October 26, 2018 Rev. 1.00 75 October 26, 2018

BS86DH12C High Voltage Touch A/D Flash MCU with HVIO

• PDC Register

Bit 7 6 5 4 3 2 1 0

Name — — PDC5 PDC4 PDC3 PDC2 PDC1 PDC0

R/W — — R/W R/W R/W R/W R/W R/W

POR — — 1 1 1 1 1 1

Bit 7~6 Unimplemented, read as “0”

Bit 5~0 PDC5~PDC0: HVIO PD5~PD0 pin input/output type selection

0: Output 1: Input

• PDOM Register

Bit 7 6 5 4 3 2 1 0

Name — — PDOM5 PDOM4 PDOM3 PDOM2 PDOM1 PDOM0

R/W — — R/W R/W R/W R/W R/W R/W

POR — — 0 0 0 0 0 0

Bit 7~6 Unimplemented, read as “0”

Bit 5~0 PDOM5~PDOM0: HVIO PD5~PD0 output mask control

0: No output mask 1: Output mask

• PWRDET Register

Bit 7 6 5 4 3 2 1 0

Name PWRRDYF — — — — — — SFRTC

R/W R — — — — — — R/W

POR x — — — — — — 0

Bit 7 PWRRDYF: V

Bit 6~1 Unimplemented, read as “0”

Bit 0 SFRTC: HVIO short ag response time selection

Voltage Detector

An internal voltage detector circuit is used to monitor the V

a power ready flag, PWRRDYF, which can be read by the MCU to indicate the power status. If

the V

is equal to or greater than the V

CC2

PWRRDYF=1, otherwise PWRRDYF=0.

In addition, there is also a V

the internal A/D converter for the power good detection purpose.

The VCC1 is the LDO high voltage power input pin. A power divided voltage V

using a divider resistor, this voltage can be externally connected to the A/D converter internal input

channel for measurement.

“x”: unknown

and VDD Power ready ag

CC2

0: Power not ready – V 1: Power ready – V

CC2

≥ V

< V

DET1

or VDD < V

DET1

and V

≥ V

DET2

During the power-on voltage rising process, when the MCU operates normally and the VDD voltage is equal to or greater than the V whether the V

voltage is equal to or greater than the V

CC2

voltage, it is not yet determined

DET2

voltage, then the

DET1

PWRRDYF read value may be 0 or 1 and therefore in an unknown condition.

0: 64×t 1: 32×t

LIRC

~ 96×t

LIRC

~ 64×t

LIRC

, and the VDD is equal to or greater than the V

DET1

voltage output with a value of 0.2V

CC2O

and VDD voltage levels. It provides

CC2

DET2

, which can be measured by

CC2

is generated

CC1O

, then

BS86DH12C

CWSEL1

High Voltage Touch A/D Flash MCU with HVIO

VDD

VCC2

VCC1

VDD

VCC1

Level

Shift

Reference

R11=12kΩ

R12=3kΩ

HVSS

CC1O

(To A/D Converter)

Voltage Detector

CC2

Voltage Detector

CWSEL2

VDD

VCC2

Level

Shift

Level

Shift

R21=12kΩ

R22=3kΩ

HVSS

VDDVCC2

CC2O

(To A/D Converter)

PWRRDY

PWRRDYF

Note: The CWSEL1 and CWSEL2 are generated by the internal A/D converter input channel selection. When the

A/D converter selects the V

CC1O

or V

signal as its internal input, then CWSEL1=0 or CWSEL2=0, othe-

CC2O

rise CWSEL1=1 or CWSEL2=1.

Voltage Detector Circuit

Short-circuit Protection Function

All high voltage I/O pins share the same short-circuit protection circuit which contains a 2-bit clock

counter. The counter, with an initial value of 0, has a clock source derived from f

which is selected by the SFRTC bit in the PWRDET register.

The high voltage I/O short-circuit protection circuit compares the output signal PDn_DOUT with the

input signal, PDn_DIN. If the PDn_DOUT has the same value as the PDn_DIN, it indicates the high

voltage I/O is in a normal condition, and then the clock counter will be cleared. If the comparison

result of any high voltage I/O pins is different, the common clock counter will not be cleared.

When the comparison result is different and the count value of the clock counter is more than 2~3,

the short-circuit protection circuit will determine it as a short-circuit condition. After the short-

circuit condition occurs, the high voltage short circuit interrupt ag, HVSCF, will be set high.

The short-circuit protection circuits use the same interrupt vector for all high voltage I/O pins. When

a short-circuit situation occurs on any one of the high voltage I/O pins, a high voltage short circuit

interrupt will be triggered. When this condition appears, if the global interrupt enable bit and its

corresponding interrupt control bit are enabled and the stack is not full, a subroutine call to the high

voltage short circuit interrupt vector will take place.

However, it must be noted that the short-circuit protection function is only available when the

voltage detector detects the condition of PWRRDYF=1.

LIRC

/32 or f

LIRC

/16,

Rev. 1.00 76 October 26, 2018 Rev. 1.00 77 October 26, 2018

BS86DH12C High Voltage Touch A/D Flash MCU with HVIO

Low Dropout Regulator – LDO

The device includes an internal low dropout regulator, LDO. The LDO can reduce the higher input

voltage on the VCC1 pin, which ranges from 6V to 10V, to a stable 5V voltage and then output on

the VLDO pin. This 5V voltage can be used as a power for external or internal circuits.

VCC1

Reference

LDO Block Diagram

Timer Modules – TM

One of the most fundamental functions in any microcontroller device is the ability to control and

measure time. To implement time related functions the device includes several Timer Modules,

generally abbreviated to the name TM. The TMs are multi-purpose timing units and serve to provide

operations such as Timer/Counter, Input Capture, Compare Match Output and Single Pulse Output

as well as being the functional unit for the generation of PWM signals. Each of the TMs has two

interrupts. The addition of input and output pins for each TM ensures that users are provided with

timing units with a wide and exible range of features.

The common features of the different TM types are described here with more detailed information

provided in the individual Compact and Periodic TM sections.

LDO VDD/VLDO

HVSS

Introduction

The device contains several TMs and each individual TM can be categorised as a certain type,

namely Compact Type TM or Periodic Type TM. Although similar in nature, the different TM types

vary in their feature complexity. The common features to all of the Compact and Periodic TMs

will be described in this section and the detailed operation regarding each of the TM types will be

described in separate sections. The main features and differences between the two types of TMs are

summarised in the accompanying table.

TM Operation

The different types of TM offer a diverse range of functions, from simple timing operations to PWM

signal generation. The key to understanding how the TM operates is to see it in terms of a free

running count-up counter whose value is then compared with the value of pre-programmed internal

TM Function CTM PTM

Timer/Counter √ √ Input Capture — √ Compare Match Output √ √ PWM Output √ √ Single Pulse Output — √

PWM Alignment Edge Edge

PWM Adjustment Period & Duty Duty or Period Duty or Period

TM Function Summary

CTM0 CTM1 PTM

10-bit CTM 10-bit CTM 10-bit PTM

TM Name/Type Summary

comparators. When the free running count-up counter has the same value as the pre-programmed

comparator, known as a compare match situation, a TM interrupt signal will be generated which

can clear the counter and perhaps also change the condition of the TM output pin. The internal TM

counter is driven by a user selectable clock source, which can be an internal clock or an external pin.

TM Clock Source

The clock source which drives the main counter in each TM can originate from various sources.

The selection of the required clock source is implemented using the xTnCK2~xTnCK0 bits in the

xTMn control registers, where “x” stands for C or P type TM and “n” stands for the specic TM

serial number. For the PTM there is no serial number “n” in the relevant pins, registers and control

bits since there is only one PTM in the device. The clock source can be a ratio of the system clock,

, or the internal high clock, fH, the f

SYS

clock source is used to allow an external signal to drive the TM as an external clock source for event

counting.

TM Interrupts

The Compact or Periodic type TM each has two internal interrupt, one for each of the internal

comparator A or comparator P, which generate a TM interrupt when a compare match condition

occurs. When a TM interrupt is generated, it can be used to clear the counter and also to change the

state of the TM output pin.

BS86DH12C

High Voltage Touch A/D Flash MCU with HVIO

clock source or the external xTCKn pin. The xTCKn pin

SUB

TM External Pins

Each of the TMs, irrespective of what type, has one input pin with the label xTCKn while the

Periodic TM has another input pin with the label PTPI. The xTMn input pin, xTCKn, is essentially a

clock source for the xTMn and is selected using the xTnCK2~xTnCK0 bits in the xTMnC0 register.

This external TM input pin allows an external clock source to drive the internal TM. The xTCKn

input pin can be chosen to have either a rising or falling active edge. The PTCK pin is also used as

the external trigger input pin in single pulse output mode for the PTM.

The other PTM input pin, PTPI, is the capture input whose active edge can be a rising edge, a

falling edge or both rising and falling edges and the active edge transition type is selected using the

PTIO1~PTIO0 bits in the PTMC1 register. There is another capture input, PTCK, for PTM capture

input mode, which can be used as the external trigger input source except the PTPI pin.

The TMs each have two output pins, xTPn and xTPnB. When the TM is in the Compare Match

Output Mode, these pins can be controlled by the TM to switch to a high or low level or to toggle

when a compare match situation occurs. The external xTPn and xTPnB output pins are also the pins

where the xTMn generates the PWM output waveform.

As the TM input and output pins are pin-shared with other functions, the TM input and output

functions must rst be congured using the relevant pin-shared function selection bits described in

the Pin-shared Function section. The details of the pin-shared function selection are described in the

pin-shared function section.

Input Output Input Output Input Output

CTCK0 CTP0, CTP0B CTCK1 CTP1, CTP1B PTCK, PTPI PTP, PTPB

CTM0 CTM1 PTM

TM External Pins

Rev. 1.00 78 October 26, 2018 Rev. 1.00 79 October 26, 2018

BS86DH12C High Voltage Touch A/D Flash MCU with HVIO

Programming Considerations

The TM Counter Registers and the Capture/Compare CCRA and CCRP registers, all have a low and high byte structure. The high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in

a specic way. The important point to note is that data transfer to and from the 8-bit buffer and its

related low byte only takes place when a write or read operation to its corresponding high byte is executed.

As the CCRA and CCRP registers are implemented in the way shown in the following diagram and

accessing these register pairs is carried out in a specic way as described above, it is recommended

to use the “MOV” instruction to access the CCRA and CCRP low byte registers, named xTMnAL and PTMRPL, using the following access procedures. Accessing the CCRA or CCRP low byte

registers without following these access procedures will result in unpredictable values.

Clock input

CTMn

CCR output

CTCKn

CTPn

CTPnB

CTM Function Pin Block Diagram (n=0~1)

Clock/capture input

CCR capture input

PTM

CCR output

PTCK

PTPI

PTP

PTPB

PTM Function Pin Block Diagram

xTMn Counter Register (Read only)

xTMnDHxTMnDL

8-bit Buffer

xTMnAL

xTMn CCRA Register (Read/Write)

PTM CCRP Register (Read/Write)

xTMnAH

PTMRPHPTMRPL

The following steps show the read and write procedures:

• Writing Data to CCRA or CCRP

♦

Step 1. Write data to Low Byte xTMnAL or PTMRPL

– Note that here data is only written to the 8-bit buffer.

Data Bus

♦

Step 2. Write data to High Byte xTMnAH or PTMRPH

– Here data is written directly to the high byte registers and simultaneously data is latched

from the 8-bit buffer to the Low Byte registers.

• Reading Data from the Counter Registers and CCRA or CCRP

♦

Step 1. Read data from the High Byte xTMnDH, xTMnAH or PTMRPH

– Here data is read directly from the High Byte registers and simultaneously data is latched

from the Low Byte register into the 8-bit buffer.

♦

Step 2. Read data from the Low Byte xTMnDL, xTMnAL or PTMRPL

– This step reads data from the 8-bit buffer.

Compact Type TM – CTM

The Compact Type TM contains three operating modes, which are Compare Match Output, Timer/

Event Counter and PWM Output modes. The Compact TM can also be controlled with an external

input pin and can drive two external output pins.

(CTM0, CTM1)

BS86DH12C

High Voltage Touch A/D Flash MCU with HVIO

CTM Core CTM Input Pin CTM Output Pin

10-bit CTM

CTCK0 CTCK1

CTP0, CTP0B CTP1, CTP1B

CCRP

CTCKn

000

SYS

001

SYS

010

fH/16 fH/64

011

100

SUB

101

SUB

110 111

CTnCK2~CTnCK0

CTnON

CTnPAU

3-bit Comparator P

b7~b9

10-bit Count-up Counter

b0~b9

10-bit Comparator A

CCRA

Comparator P Match

Counter Clear 0

CTnCCLR

Comparator A Match

CTMnPF Interrupt

CTnOC

Output

Control

CTnM1~CTnM0

CTnIO1~CTnIO0

CTMnAF Interrupt

Polarity

Control

CTnPOL

CTPn

CTPnB

Note: The CTMn external pins are pin-shared with other functions, so before using the CTMn function the relevant

pin-shared function registers must be set properly.

Compact Type TM Block Diagram (n=0~1)

Compact Type TM Operation

The size of Compact TM is 10-bit wide and its core is a 10-bit count-up counter which is driven by

a user selectable internal or external clock source. There are also two internal comparators with the

names, Comparator A and Comparator P. These comparators will compare the value in the counter

with CCRP and CCRA registers. The CCRP comparator is 3-bit wide whose value is compared with

the highest 3 bits in the counter while the CCRA is the 10 bits and therefore compares all counter bits.

The only way of changing the value of the 10-bit counter using the application program, is to

clear the counter by changing the CTnON bit from low to high. The counter will also be cleared

automatically by a counter overow or a compare match with one of its associated comparators.

When these conditions occur, a CTMn interrupt signal will also usually be generated. The Compact

Type TM can operate in a number of different operational modes, can be driven by different clock

sources including an input pin and can also control two output pins. All operating setup conditions

are selected using relevant internal registers.

Rev. 1.00 80 October 26, 2018 Rev. 1.00 81 October 26, 2018

BS86DH12C High Voltage Touch A/D Flash MCU with HVIO

Compact Type TM Register Description

Overall operation of the Compact TM is controlled using a series of registers. A read only register

pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store the

internal 10-bit CCRA value. The remaining two registers are control registers which set the different

operating and control modes as well as the three CCRP bits.

Name

CTMnC0 CTnPAU CTnCK2 CTnCK1 CTnCK0 CTnON CTnRP2 CTnRP1 CTnRP0

CTMnC1 CTnM1 CTnM0 CTnIO1 CTnIO0 CTnOC CTnPOL CTnDPX CTnCCLR

CTMnDL D7 D6 D5 D4 D3 D2 D1 D0

CTMnDH — — — — — — D9 D8

CTMnAL D7 D6 D5 D4 D3 D2 D1 D0

CTMnAH — — — — — — D9 D8

7 6 5 4 3 2 1 0

10-bit Compact Type TM Register List (n=0~1)

• CTMnC0 Register

Bit 7 6 5 4 3 2 1 0

Name CTnPAU CTnCK2 CTnCK1 CTnCK0 CTnON CTnRP2 CTnRP1 CTnRP0

R/W R/W R/W R/W R/W R/W R/W R/W R/W

POR 0 0 0 0 0 0 0 0

Bit

Bit 7 CTnPAU: CTMn counter pause control

0: Run 1: Pause

The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the CTMn will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again.

Bit 6~4 CTnCK2~CTnCK0: CTMn counter clock selection

000: f 001: f

SYS

010: fH/16 011: fH/64 100: f

SUB

101: f

SUB

110: CTCKn rising edge clock 111: CTCKn falling edge clock

These three bits are used to select the clock source for the CTMn. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source f

is the system clock, while fH and f

SYS

are other internal clocks, the details of which

SUB

can be found in the oscillator section.

Bit 3 CTnON: CTMn counter on/off control

0: Off 1: On

This bit controls the overall on/off function of the CTMn. Setting the bit high enables the counter to run while clearing the bit disables the CTMn. Clearing this bit to zero will stop the counter from counting and turn off the CTMn which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again.

BS86DH12C

High Voltage Touch A/D Flash MCU with HVIO

If the CTMn is in the Compare Match Output Mode or the PWM Output Mode, then

the CTMn output pin will be reset to its initial condition, as specied by the CTnOC

bit, when the CTnON bit changes from low to high.

Bit 2~0 CTnRP2~CTnRP0: CTMn CCRP 3-bit register, compared with the CTMn counter

bit 9 ~ bit 7 Comparator P match period=

0: 1024 CTMn clocks 1~7: (1~7)×128 CTMn clocks

These three bits are used to set the value on the internal CCRP 3-bit register, which are then compared with the internal counter’s highest three bits. The result of this comparison can be selected to clear the internal counter if the CTnCCLR bit is set to zero. Setting the CTnCCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value.

• CTMnC1 Register

Bit 7 6 5 4 3 2 1 0

Name CTnM1 CTnM0 CTnIO1 CTnIO0 CTnOC CTnPOL CTnDPX CTnCCLR

R/W R/W R/W R/W R/W R/W R/W R/W R/W

POR 0 0 0 0 0 0 0 0

Bit 7~6 CTnM1~CTnM0: CTMn operating mode selection

00: Compare Match Output Mode

01: Undened

10: PWM Output Mode 11: Timer/Counter Mode

These bits set the required operating mode for the CTMn. To ensure reliable operation the CTMn should be switched off before any changes are made to the CTnM1 and

CTnM0 bits. In the Timer/Counter Mode, the CTMn output pin pin state is undened.

Bit 5~4 CTnIO1~CTnIO0: CTMn external pin CTPn function selection

Compare Match Output Mode

00: No change 01: Output low 10: Output high 11: Toggle output

PWM Output Mode

00: PWM output inactive state 01: PWM output active state 10: PWM output

11: Undened

Timer/Counter Mode

Unused

These two bits are used to determine how the CTMn external pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the CTMn is running.

In the Compare Match Output Mode, the CTnIO1 and CTnIO0 bits determine how the CTMn output pin changes state when a compare match occurs from the Comparator A. The CTMn output pin can be set to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the CTMn output pin should be set using the CTnOC bit in the CTMnC1 register. Note that the output level requested by the CTnIO1 and CTnIO0 bits must be different from the initial value setup using the CTnOC bit otherwise no change will occur on the CTMn output pin

Rev. 1.00 82 October 26, 2018 Rev. 1.00 83 October 26, 2018

BS86DH12C High Voltage Touch A/D Flash MCU with HVIO

when a compare match occurs. After the CTMn output pin changes state, it can be reset to its initial level by changing the level of the CTnON bit from low to high.

In the PWM Output Mode, the CTnIO1 and CTnIO0 bits determine how the CTMn output pin changes state when a certain compare match condition occurs. The PWM

output function is modied by changing these two bits. It is necessary to only change

the values of the CTnIO1 and CTnIO0 bits only after the CTMn has been switched off. Unpredictable PWM outputs will occur if the CTnIO1 and CTnIO0 bits are changed when the CTMn is running.

Bit 3 CTnOC: CTMn CTPn output control

Compare Match Output Mode

0: Initial low 1: Initial high

PWM Output Mode/Single Pulse Output Mode

0: Active low 1: Active high

This is the output control bit for the CTMn output pin. Its operation depends upon whether CTMn is being used in the Compare Match Output Mode or in the PWM Output Mode. It has no effect if the CTMn is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the CTMn output pin before a compare match occurs. In the PWM Output Mode it determines if the PWM signal is active high or active low.

Bit 2 CTnPOL: CTMn CTPn output polarity control

0: Non-invert 1: Invert

This bit controls the polarity of the CTPn output pin. When the bit is set high the CTMn output pin will be inverted and not inverted when the bit is zero. It has no effect if the CTMn is in the Timer/Counter Mode.

Bit 1 CTnDPX: CTMn PWM duty/period control

0: CCRP – period; CCRA – duty 1: CCRP – duty; CCRA – period

This bit determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform.

Bit 0 CTnCCLR: CTMn counter clear condition selection

0: Comparator P match 1: Comparator A match

This bit is used to select the method which clears the counter. Remember that the CTMn contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the CTnCCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The CTnCCLR bit is not used in the PWM Output mode.

• CTMnDL Register

Bit 7 6 5 4 3 2 1 0

Name D7 D6 D5 D4 D3 D2 D1 D0

R/W R R R R R R R R

POR 0 0 0 0 0 0 0 0

Bit 7~0 D7~D0: CTMn Counter Low Byte Register bit 7 ~ bit 0

CTMn 10-bit Counter bit 7 ~ bit 0

BS86DH12C

High Voltage Touch A/D Flash MCU with HVIO

• CTMnDH Register

Bit 7 6 5 4 3 2 1 0

Name — — — — — — D9 D8

R/W — — — — — — R R

POR — — — — — — 0 0

Bit 7~2 Unimplemented, read as “0”

Bit 1~0 D9~D8: CTMn Counter High Byte Register bit 1 ~ bit 0

CTMn 10-bit Counter bit 9 ~ bit 8

• CTMnAL Register

Bit 7 6 5 4 3 2 1 0

Name D7 D6 D5 D4 D3 D2 D1 D0

R/W R/W R/W R/W R/W R/W R/W R/W R/W

POR 0 0 0 0 0 0 0 0

Bit 7~0 D7~D0: CTMn CCRA Low Byte Register bit 7 ~ bit 0

CTMn 10-bit CCRA bit 7 ~ bit 0

• CTMnAH Register

Bit 7 6 5 4 3 2 1 0

Name — — — — — — D9 D8

R/W — — — — — — R/W R/W

POR — — — — — — 0 0

Bit 7~2 Unimplemented, read as “0”

Bit 1~0 D9~D8: CTMn CCRA High Byte Register bit 7 ~ bit 0

CTMn 10-bit CCRA bit 9 ~ bit 8

Compact Type TM Operation Modes

The Compact Type TM can operate in one of three operating modes, Compare Match Output Mode,

PWM Output Mode or Timer/Counter Mode. The operating mode is selected using the CTnM1 and

CTnM0 bits in the CTMnC1 register.

Compare Match Output Mode

To select this mode, bits CTnM1 and CTnM0 in the CTMnC1 register, should be set to “00”

respectively. In this mode once the counter is enabled and running it can be cleared by three

methods. These are a counter overow, a compare match from Comparator A and a compare match

from Comparator P. When the CTnCCLR bit is low, there are two ways in which the counter can be

cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all

zero which allows the counter to overow. Here both CTMnAF and CTMnPF interrupt request ags

for Comparator A and Comparator P respectively, will both be generated.

If the CTnCCLR bit in the CTMnC1 register is high then the counter will be cleared when a compare

match occurs from Comparator A. However, here only the CTMnAF interrupt request ag will be

generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when

CTnCCLR is high no CTMnPF interrupt request ag will be generated. If the CCRA bits are all

zero, the counter will overow when it reaches its maximum 10-bit, 3FF Hex, value. However, here

the CTMnAF interrupt request ag will not be generated.

As the name of the mode suggests, after a comparison is made, the CTMn output pin, will change

state. The CTMn output pin condition however only changes state when a CTMnAF interrupt

request ag is generated after a compare match occurs from Comparator A. The CTMnPF interrupt

Rev. 1.00 84 October 26, 2018 Rev. 1.00 85 October 26, 2018

BS86DH12C High Voltage Touch A/D Flash MCU with HVIO

request ag, generated from a compare match occurs from Comparator P, will have no effect on

the CTMn output pin. The way in which the CTMn output pin changes state are determined by

the condition of the CTnIO1 and CTnIO0 bits in the CTMnC1 register. The CTMn output pin can

be selected using the CTnIO1 and CTnIO0 bits to go high, to go low or to toggle from its present

condition when a compare match occurs from Comparator A. The initial condition of the CTMn

output pin, which is set after the CTnON bit changes from low to high, is set using the CTnOC bit.

Note that if the CTnIO1 and CTnIO0 bits are zero then no pin change will take place.

Counter Value

0x3FF

CCRP

CCRA

CTnON

CTnPAU

CTnPOL

CCRP Int.

Flag CTMnPF

CCRA Int.

Flag CTMnAF

CCRP=0

Counter overflow

CCRP > 0

Counter cleared by CCRP value

Resume

Pause

CTnCCLR = 0; CTnM [1:0] = 00

Counter

Restart

Stop

Time

CTMn O/P Pin

Output not affected by

Output pin set to initial Level Low if CTnOC=0

Output Toggle with

CTMnAF flag

Here CTnIO [1:0] = 11 Toggle Output select

Note CTnIO [1:0] = 10 Active High Output select

CTMnAF flag. Remains High until reset by CTnON bit

Compare Match Output Mode – CTnCCLR=0 (n=0~1)

Note: 1. With CTnCCLR=0 a Comparator P match will clear the counter

2. The CTMn output pin is controlled only by the CTMnAF ag

3. The output pin is reset to its initial state by a CTnON bit rising edge

Output Inverts when CTnPOL is high

Output Pin

Output controlled by other pin-shared function

Reset to Initial value

BS86DH12C

High Voltage Touch A/D Flash MCU with HVIO

Counter Value

0x3FF

CCRA

CCRP

CTnON

CTnPAU

CTnPOL

CCRA Int.

Flag CTMnAF

CCRP Int.

Flag CTMnPF

CTMn O/P Pin

Output pin set to initial Level Low if CTnOC=0

CTMnPF not generated

Here CTnIO [1:0] = 11 Toggle Output select

CTnCCLR = 1; CTnM [1:0] = 00

CCRA > 0 Counter cleared by CCRA value

CCRA=0

Stop

Output controlled by other pin-shared function

Output Toggle with

CTMnAF flag

Pause

Output not affected by CTMnAF flag. Remains High until reset by CTnON bit

Note CTnIO [1:0] = 10 Active High Output select

Resume

Compare Match Output Mode – CTnCCLR=1 (n=0~1)

CCRA = 0 Counter overflow

Counter Restart

Output Inverts

Output Pin Reset to Initial value

when CTnPOL is high

Time

No CTMnAF flag generated on CCRA overflow

Output does not change

Note: 1. With CTnCCLR=1 a Comparator A match will clear the counter

2. The CTMn output pin is controlled only by the CTMnAF ag

3. The output pin is reset to its initial state by a CTnON bit rising edge

4. A CTMnPF ag is not generated when CTnCCLR=1

Rev. 1.00 86 October 26, 2018 Rev. 1.00 87 October 26, 2018

BS86DH12C High Voltage Touch A/D Flash MCU with HVIO

Timer/Counter Mode

To select this mode, bits CTnM1 and CTnM0 in the CTMnC1 register should be set to “11”

respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output

Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the

CTMn output pin is not used. Therefore the above description and Timing Diagrams for the

Compare Match Output Mode can be used to understand its function. As the CTMn output pin is not

used in this mode, the pin can be used as a normal I/O pin or other pin-shared functions.

PWM Output Mode

To select this mode, bits CTnM1 and CTnM0 in the CTMnC1 register should be set to “10”

respectively. The PWM function within the CTMn is useful for applications which require functions

such as motor control, heating control, illumination control, etc. By providing a signal of fixed

frequency but of varying duty cycle on the CTMn output pin, a square wave AC waveform can be

generated with varying equivalent DC RMS values.

As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated

waveform is extremely exible. In the PWM Output Mode, the CTnCCLR bit has no effect as the

PWM period. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one

the other one is used to control the duty cycle. Which register is used to control either frequency

or duty cycle is determined using the CTnDPX bit in the CTMnC1 register. The PWM waveform

frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers.

An interrupt ag, one for each of the CCRA and CCRP, will be generated when a compare match

occurs from either Comparator A or Comparator P. The CTnOC bit in the CTMnC1 register is used

to select the required polarity of the PWM waveform while the two CTnIO1 and CTnIO0 bits are

used to enable the PWM output or to force the CTMn output pin to a xed high or low level. The

CTnPOL bit is used to reverse the polarity of the PWM output waveform.

• 10-bit CTMn, PWM Output Mode, Edge-aligned Mode, CTnDPX=0

CCRP 1~7 0

Period CCRP×128 1024

Duty CCRA

If f

=16MHz, CTMn clock source is f

SYS

The CTMn PWM output frequency=(f

/4, CCRP=4 and CCRA=128,

SYS

/4)/(4×128)=f

SYS

/2048=8kHz, duty=128/(4×128)=25%.

SYS

If the Duty value dened by the CCRA register is equal to or greater than the Period value, then the

PWM output duty is 100%.

• 10-bit CTMn, PWM Output Mode, Edge-aligned Mode, CTnDPX=1

CCRP 1~7 0

Period CCRA

Duty CCRP×128 1024

The PWM output period is determined by the CCRA register value together with the CTMn clock

while the PWM duty cycle is dened by the CCRP register value except when the CCRP value is

equal to 0.

BS86DH12C

High Voltage Touch A/D Flash MCU with HVIO

Counter Value

CCRP

CCRA

CTnON

CTnPAU

CTnPOL

CCRA Int.

Flag CTMnAF

CCRP Int.

Flag CTMnPF

CTMn O/P Pin

(CTnOC=1)

CTMn O/P Pin

(CTnOC=0)

Counter cleared by

CCRP

Pause

CTnDPX = 0; CTnM [1:0] = 10

Counter Reset when CTnON returns high

Resume

Counter Stop if CTnON bit low

Time

PWM Duty Cycle set by CCRA

PWM Period set by CCRP

PWM Output Mode – CTnDXP=0 (n=0~1)

Note: 1. Here CTnDPX=0 – Counter cleared by CCRP

2. A counter clear sets the PWM Period

3. The internal PWM function continues running even when CTnIO[1:0]=00 or 01

4. The CTnCCLR bit has no inuence on PWM operation

Output controlled by other pin-shared function

PWM resumes operation

Output Inverts when CTnPOL = 1

Rev. 1.00 88 October 26, 2018 Rev. 1.00 89 October 26, 2018

BS86DH12C High Voltage Touch A/D Flash MCU with HVIO

Counter Value

CCRA

CCRP

CTnON

CTnPAU

CTnPOL

CCRP Int.

Flag CTMnPF

CCRA Int.

Flag CTMnAF

CTMn O/P Pin

(CTnOC=1)

CTMn O/P Pin

(CTnOC=0)

Counter cleared by

CCRA

Pause

CTnDPX = 1; CTnM [1:0] = 10

Resume

Counter Stop if

CTnON bit low

Counter Reset when

CTnON returns high

Time

PWM Duty Cycle set by CCRP

PWM Period set by CCRA

PWM Output Mode – CTnDXP=1 (n=0~1)

Note: 1. Here CTnDPX=1 – Counter cleared by CCRA

2. A counter clear sets the PWM Period

3. The internal PWM function continues even when CTnIO[1:0]=00 or 01

4. The CTnCCLR bit has no inuence on PWM operation

other pin-shared function

PWM resumes operationOutput controlled by

Output Inverts when CTnPOL = 1

Periodic Type TM – PTM

The Periodic Type TM contains ve operating modes, which are Compare Match Output, Timer/

Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Periodic TM can

also be controlled with two external input pins and can drive two external output pins.

BS86DH12C

High Voltage Touch A/D Flash MCU with HVIO

PTM Core PTM Input Pin PTM Output Pin

10-bit PTM PTCK, PTPI PTP, PTPB

CCRP

Comparator P Match

Counter Clear 0

PTCCLR

Comparator A Match

PTIO1~PTIO0

Edge

Detector

PTMPF Interrupt

PTOC

Output Control

PTM1, PTM0

PTIO1, PTIO0

PTCAPTS

0 1

PTMAF Interrupt

PTPI

Polarity Control

PTPOL

PTP

PTPB

PTCK

SYS

fH/16 fH/64

SUB

PTCK2~PTCK0

000 001 010 011 100 101 110 111

PTON

PTPAU

10-bit Comparator P

b0~b9

10-bit Count-up Counter

b0~b9

10-bit Comparator A

CCRA

Note: The PTM external pins are pin-shared with other functions, so before using the PTM function the relevant

pin-shared function registers must be set properly.

Periodic Type TM Block Diagram

Periodic TM Operation

The size of Periodic TM is 10-bit wide and its core is a 10-bit count-up counter which is driven by

a user selectable internal or external clock source. There are also two internal comparators with the

names, Comparator A and Comparator P. These comparators will compare the value in the counter

with CCRP and CCRA registers. The CCRP and CCRA comparators are 10-bit wide whose value is

respectively compared with all counter bits.

The only way of changing the value of the 10-bit counter using the application program is to

clear the counter by changing the PTON bit from low to high. The counter will also be cleared

automatically by a counter overow or a compare match with one of its associated comparators.

When these conditions occur, a PTM interrupt signal will also usually be generated. The Periodic

Type TM can operate in a number of different operational modes, can be driven by different clock

sources including an input pin and can also control the output pins. All operating setup conditions

are selected using relevant internal registers.

Periodic Type TM Register Description

Overall operation of the Periodic TM is controlled using a series of registers. A read only register

pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store

the internal 10-bit CCRA and CCRP value. The remaining two registers are control registers which

set the different operating and control modes.

Rev. 1.00 90 October 26, 2018 Rev. 1.00 91 October 26, 2018

BS86DH12C High Voltage Touch A/D Flash MCU with HVIO

Name

PTMC0 PTPAU PTCK2 PTCK1 PTCK0 PTON — — —

PTMC1 PTM1 PTM0 PTIO1 PTIO0 PTOC PTPOL PTCAPTS PTCCLR

PTMDL D7 D6 D5 D4 D3 D2 D1 D0

PTMDH — — — — — — D9 D8

PTMAL D7 D6 D5 D4 D3 D2 D1 D0

PTMAH — — — — — — D9 D8

PTMRPL PTRP7 PTRP6 PTRP5 PTRP4 PTRP3 PTRP2 PTRP1 PTRP0

PTMRPH — — — — — — PTRP9 PTRP8

7 6 5 4 3 2 1 0

10-bit Periodic TM Register List

Bit

• PTMC0 Register

Bit 7 6 5 4 3 2 1 0

Name PTPAU PTCK2 PTCK1 PTCK0 PTON — — —

R/W R/W R/W R/W R/W R/W — — —

POR 0 0 0 0 0 — — —

Bit 7 PTPAU: PTM counter pause control

0: Run 1: Pause

The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the PTM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again.

Bit 6~4 PTCK2~PTCK0: PTM Counter clock selection

000: f 001: f

SYS

010: fH/16 011: fH/64 100: f

SUB

101: f

SUB

110: PTCK rising edge clock 111: PTCK falling edge clock

These three bits are used to select the clock source for the PTM. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source f the system clock, while fH and f

are other internal clocks, the details of which can

SUB

be found in the oscillator section.

Bit 3 PTON: PTM counter on/off control

0: Off 1: On

This bit controls the overall on/off function of the PTM. Setting the bit high enables the counter to run while clearing the bit disables the PTM. Clearing this bit to zero will stop the counter from counting and turn off the PTM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the PTM is in the Compare Match Output Mode, PWM output Mode or Single Pulse Output Mode

then the PTM output pin will be reset to its initial condition, as specied by the PTOC

bit, when the PTON bit changes from low to high.

Bit 2~0 Unimplemented, read as “0”

SYS

BS86DH12C

High Voltage Touch A/D Flash MCU with HVIO

• PTMC1 Register

Bit 7 6 5 4 3 2 1 0

Name PTM1 PTM0 PTIO1 PTIO0 PTOC PTPOL PTCAPTS PTCCLR

R/W R/W R/W R/W R/W R/W R/W R/W R/W

POR 0 0 0 0 0 0 0 0

Bit 7~6 PTM1~PTM0: Select PTM Operating Mode

00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Output Mode or Single Pulse Output Mode 11: Timer/Counter Mode

These bits set the required operating mode for the PTM. To ensure reliable operation the PTM should be switched off before any changes are made to the PTM1 and PTM0

bits. In the Timer/Counter Mode, the PTM output pin state is undened.

Bit 5~4 PTIO1~PTIO0: PTM external pin PTP, PTPI or PTCK function selection

Compare Match Output Mode

00: No change 01: Output low 10: Output high 11: Toggle output

PWM Output Mode/Single Pulse Output Mode

00: PWM output inactive state 01: PWM output active state 10: PWM output 11: Single Pulse Output

Capture Input Mode

00: Input capture at rising edge of PTPI or PTCK 01: Input capture at falling edge of PTPI or PTCK 10: Input capture at rising/falling edge of PTPI or PTCK 11: Input capture disabled

Timer/Counter Mode

Unused

These two bits are used to determine how the PTM external pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the PTM is running.

In the Compare Match Output Mode, the PTIO1 and PTIO0 bits determine how the PTM output pin changes state when a compare match occurs from the Comparator A. The PTM output pin can be set to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the PTM output pin should be set using the PTOC bit in the PTMC1 register. Note that the output level requested by the PTIO1 and PTIO0 bits must be different from the initial value setup using the PTOC bit otherwise no change will occur on the PTM output pin when a compare match occurs. After the PTM output pin changes state, it can be reset to its initial level by changing the level of the PTON bit from low to high.

In the PWM Output Mode, the PTIO1 and PTIO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PTM output function is modified by changing these two bits. It is necessary to only change the values of the PTIO1 and PTIO0 bits only after the PTM has been switched off. Unpredictable PWM outputs will occur if the PTIO1 and PTIO0 bits are changed when the PTM is running.

Rev. 1.00 92 October 26, 2018 Rev. 1.00 93 October 26, 2018

BS86DH12C High Voltage Touch A/D Flash MCU with HVIO

Bit 3 PTOC: PTM PTP output control

Compare Match Output Mode

0: Initial low 1: Initial high

PWM Output Mode/Single Pulse Output Mode

0: Active low 1: Active high

This is the output control bit for the PTM output pin. Its operation depends upon whether PTM is being used in the Compare Match Output Mode or in the PWM Output Mode/Single Pulse Output Mode. It has no effect if the PTM is in the Timer/ Counter Mode. In the Compare Match Output Mode it determines the logic level of the PTM output pin before a compare match occurs. In the PWM Output Mode it determines if the PWM signal is active high or active low. In the Single Pulse Output Mode it determines the logic level of the PTM output pin when the PTON bit changes from low to high.

Bit 2 PTPOL: PTM PTP output polarity control

0: Non-invert 1: Invert

This bit controls the polarity of the PTP output pin. When the bit is set high the PTM output pin will be inverted and not inverted when the bit is zero. It has no effect if the PTM is in the Timer/Counter Mode.

Bit 1 PTCAPTS: PTM capture trigger source selection

0: From PTPI pin 1: From PTCK pin

Bit 0 PTCCLR: PTM counter clear condition selection

0: Comparator P match 1: Comparator A match

This bit is used to select the method which clears the counter. Remember that the Periodic TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the PTCCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from

the Comparator P or with a counter overow. A counter overow clearing method can

only be implemented if the CCRP bits are all cleared to zero. The PTCCLR bit is not used in the PWM Output, Single Pulse Output or Capture Input Mode.

• PTMDL Register

Bit 7 6 5 4 3 2 1 0

Name D7 D6 D5 D4 D3 D2 D1 D0

R/W R R R R R R R R

POR 0 0 0 0 0 0 0 0

Bit 7~0 D7~D0: PTM Counter Low Byte Register bit 7 ~ bit 0

PTM 10-bit Counter bit 7 ~ bit 0

• PTMDH Register

Bit 7 6 5 4 3 2 1 0

Name — — — — — — D9 D8

R/W — — — — — — R R

POR — — — — — — 0 0

Bit 7~2 Unimplemented, read as “0”

Bit 1~0 D9~D8: PTM Counter High Byte Register bit 1 ~ bit 0

PTM 10-bit Counter bit 9 ~ bit 8

BS86DH12C

High Voltage Touch A/D Flash MCU with HVIO

• PTMAL Register

Bit 7 6 5 4 3 2 1 0

Name D7 D6 D5 D4 D3 D2 D1 D0

R/W R/W R/W R/W R/W R/W R/W R/W R/W

POR 0 0 0 0 0 0 0 0

Bit 7~0 D7~D0: PTM CCRA Low Byte Register bit 7 ~ bit 0

PTM 10-bit CCRA bit 7 ~ bit 0

• PTMAH Register

Bit 7 6 5 4 3 2 1 0

Name — — — — — — D9 D8

R/W — — — — — — R/W R/W

POR — — — — — — 0 0

Bit 7~2 Unimplemented, read as “0”

Bit 1~0 D9~D8: PTM CCRA High Byte Register bit 1 ~ bit 0

PTM 10-bit CCRA bit 9 ~ bit 8

• PTMRPL Register

Bit 7 6 5 4 3 2 1 0

Name PTRP7 PTRP6 PTRP5 PTRP4 PTRP3 PTRP2 PTRP1 PTRP0

R/W R/W R/W R/W R/W R/W R/W R/W R/W

POR 0 0 0 0 0 0 0 0

Bit 7~0 PTRP7~PTRP0: PTM CCRP Low Byte Register bit 7 ~ bit 0

PTM 10-bit CCRP bit 7 ~ bit 0

• PTMRPH Register

Bit 7 6 5 4 3 2 1 0

Name — — — — — — PTRP9 PTRP8

R/W — — — — — — R/W R/W

POR — — — — — — 0 0

Bit 7~2 Unimplemented, read as “0”

Bit 1~0 PTRP9~PTRP8: PTM CCRP High Byte Register bit 1 ~ bit 0

PTM 10-bit CCRP bit 9 ~ bit 8

Rev. 1.00 94 October 26, 2018 Rev. 1.00 95 October 26, 2018

BS86DH12C High Voltage Touch A/D Flash MCU with HVIO

Periodic Type TM Operation Modes

The Periodic Type TM can operate in one of ve operating modes, Compare Match Output Mode,

PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The

operating mode is selected using the PTM1 and PTM0 bits in the PTMC1 register.

Compare Match Output Mode

To select this mode, bits PTM1 and PTM0 in the PTMC1 register, should be set to “00” respectively.

In this mode once the counter is enabled and running it can be cleared by three methods. These are

a counter overow, a compare match from Comparator A and a compare match from Comparator P.

When the PTCCLR bit is low, there are two ways in which the counter can be cleared. One is when

a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the

counter to overow. Here both PTMAF and PTMPF interrupt request ags for Comparator A and

Comparator P respectively, will both be generated.

If the PTCCLR bit in the PTMC1 register is high then the counter will be cleared when a compare

match occurs from Comparator A. However, here only the PTMAF interrupt request ag will be

generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when

PTCCLR is high no PTMPF interrupt request ag will be generated. In the Compare Match Output

Mode, the CCRA cannot be cleared to zero. If the CCRA bits are all zero, the counter will overow

when it reaches its maximum 10-bit, 3FF Hex, value, however here the PTMAF interrupt request

ag will not be generated.

As the name of the mode suggests, after a comparison is made, the PTM output pin will change

state. The PTM output pin condition however only changes state when a PTMAF interrupt request

ag is generated after a compare match occurs from Comparator A. The PTMPF interrupt request

ag, generated from a compare match occurs from Comparator P, will have no effect on the PTM

output pin. The way in which the PTM output pin changes state are determined by the condition of

the PTIO1 and PTIO0 bits in the PTMC1 register. The PTM output pin can be selected using the

PTIO1 and PTIO0 bits to go high, to go low or to toggle from its present condition when a compare

match occurs from Comparator A. The initial condition of the PTM output pin, which is set after the

PTON bit changes from low to high, is set using the PTOC bit. Note that if the PTIO1 and PTIO0

bits are zero then no pin change will take place.

BS86DH12C

High Voltage Touch A/D Flash MCU with HVIO

Counter Value

0x3FF

CCRP

CCRA

PTON

PTPAU

PTPOL

CCRP Int.

Flag PTMPF

CCRA Int.

Flag PTMAF

CCRP=0

Counter overflow

CCRP > 0

Counter cleared by CCRP value

Resume

Pause

PTCCLR = 0; PTM [1:0] = 00

Counter

Restart

Stop

Time

PTM O/P Pin

Output not affected by

Output pin set to initial Level Low if PTOC=0

Output Toggle with

PTMAF flag

Here PTIO [1:0] = 11 Toggle Output select

Note PTIO [1:0] = 10 Active High Output select

PTMAF flag. Remains High until reset by PTON bit

Compare Match Output Mode – PTCCLR=0

Note: 1. With PTCCLR=0, a Comparator P match will clear the counter

2. The PTM output pin is controlled only by the PTMAF ag

3. The output pin is reset to its initial state by a PTON bit rising edge

Output Inverts

Output Pin

Reset to Initial value Output controlled by other pin-shared function

when PTPOL is high

Rev. 1.00 96 October 26, 2018 Rev. 1.00 97 October 26, 2018

BS86DH12C High Voltage Touch A/D Flash MCU with HVIO

Counter Value

0x3FF

CCRA

CCRP

PTON

PTPAU

PTPOL

CCRA Int.

Flag PTMAF

CCRP Int.

Flag PTMPF

PTM O/P Pin

Output pin set to initial Level Low if PTOC=0

PTMPF not generated

CCRA > 0 Counter cleared by CCRA value

Output Toggle with

PTMAF flag

Here PTIO [1:0] = 11 Toggle Output select

Note PTIO [1:0] = 10 Active High Output select

Compare Match Output Mode – PTCCLR=1

Resume

Pause

Output not affected by PTMAF flag. Remains High until reset by PTON bit

Output controlled by other pin-shared function

PTCCLR = 1; PTM [1:0] = 00

CCRA = 0 Counter overflow

CCRA=0

Stop

Counter Restart

No PTMAF flag generated on CCRA overflow

Output Inverts

Output Pin Reset to Initial value

when PTPOL is high

Time

Output does not change

Note: 1. With PTCCLR=1, a Comparator A match will clear the counter

2. The PTM output pin is controlled only by the PTMAF ag

3. The output pin is reset to its initial state by a PTON bit rising edge

4. A PTMPF ag is not generated when PTCCLR=1

BS86DH12C

High Voltage Touch A/D Flash MCU with HVIO

Timer/Counter Mode

To select this mode, bits PTM1 and PTM0 in the PTMC1 register should be set to “11” respectively.

The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode

generating the same interrupt flags. The exception is that in the Timer/Counter Mode the PTM

output pin is not used. Therefore the above description and Timing Diagrams for the Compare

Match Output Mode can be used to understand its function. As the PTM output pin is not used in

this mode, the pin can be used as a normal I/O pin or other pin-shared functions.

PWM Output Mode

To select this mode, bits PTM1 and PTM0 in the PTMC1 register should be set to “10” respectively

and also the PTIO1 and PTIO0 bits should be set to “10” respectively. The PWM function within

the PTM is useful for applications which require functions such as motor control, heating control,

illumination control, etc. By providing a signal of xed frequency but of varying duty cycle on the

PTM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS

values.

As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated

waveform is extremely exible. In the PWM Output Mode, the PTCCLR bit has no effect as the

PWM period. Both of the CCRP and CCRA registers are used to generate the PWM waveform, one

the other one is used to control the duty cycle. The PWM waveform frequency and duty cycle can

therefore be controlled by the values in the CCRA and CCRP registers.

An interrupt ag, one for each of the CCRA and CCRP, will be generated when a compare match

occurs from either Comparator A or Comparator P. The PTOC bit in the PTMC1 register is used to

select the required polarity of the PWM waveform while the two PTIO1 and PTIO0 bits are used to

enable the PWM output or to force the PTM output pin to a xed high or low level. The PTPOL bit

is used to reverse the polarity of the PWM output waveform.

• 10-bit PTM, PWM Output Mode, Edge-aligned Mode

CCRP 1~1023 0

Period 1~1023 1024

Duty CCRA

If f

=16MHz, TM clock source select f

SYS

The PTM PWM output frequency=(f

/4, CCRP=512 and CCRA=128,

SYS

/4)/512=f

SYS

/2048=8kHz, duty=128/512=25%,

SYS

If the Duty value dened by the CCRA register is equal to or greater than the Period value, then the

PWM output duty is 100%.

Rev. 1.00 98 October 26, 2018 Rev. 1.00 99 October 26, 2018

BS86DH12C

PTM O/P Pin

Counter Reset when

PTM O/P Pin

High Voltage Touch A/D Flash MCU with HVIO

Counter Value

CCRP

CCRA

PTON

PTPAU

PTPOL

CCRA Int.

Flag PTMAF

CCRP Int.

Flag PTMPF

(PTOC=1)

Counter cleared by

CCRP

Pause

Resume

PTM [1:0] = 10

PTON returns high

Counter Stop if

PTON bit low

Time

(PTOC=0)

PWM Duty Cycle set by CCRA

PWM Period set by CCRP

PWM Output Mode

Note: 1. The counter is cleared by CCRP

2. A counter clear sets the PWM Period

3. The internal PWM function continues running even when PTIO[1:0]=00 or 01

4. The PTCCLR bit has no inuence on PWM operation

PWM resumes

Output controlled by other pin-shared function

operation

Output Inverts When PTPOL = 1

BS86DH12C

High Voltage Touch A/D Flash MCU with HVIO

Single Pulse Output Mode

To select this mode, bits PTM1 and PTM0 in the PTMC1 register should be set to “10” respectively

and also the PTIO1 and PTIO0 bits should be set to “11” respectively. The Single Pulse Output

Mode, as the name suggests, will generate a single shot pulse on the PTM output pin.

The trigger for the pulse output leading edge is a low to high transition of the PTON bit, which

can be implemented using the application program. However in the Single Pulse Output Mode, the

PTON bit can also be made to automatically change from low to high using the external PTCK pin,

which will in turn initiate the Single Pulse output. When the PTON bit transitions to a high level, the

counter will start running and the pulse leading edge will be generated. The PTON bit should remain

high when the pulse is in its active state. The generated pulse trailing edge will be generated when

the PTON bit is cleared to zero, which can be implemented using the application program or when a

compare match occurs from Comparator A.

However a compare match from Comparator A will also automatically clear the PTON bit and thus

generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the

pulse width. A compare match from Comparator A will also generate a PTM interrupt. The counter

can only be reset back to zero when the PTON bit changes from low to high when the counter

restarts. In the Single Pulse Output Mode CCRP is not used. The PTCCLR is not used in this Mode.

S/W Command SET“PTON”

or PTCK Pin Transition

PTP Output Pin

CCRA

Leading Edge

PTON bit

Single Pulse Generation

CCRA

Trailing Edge

PTON bit

Pulse Width = CCRA Value

S/W Command CLR“PTON”

or CCRA Compare Match

Rev. 1.00 100 October 26, 2018 Rev. 1.00 101 October 26, 2018

Holtek BS86DH12C User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

CPU Features

Peripheral Features

General Description

Block Diagram

Pin Assignment

Pin Descriptions

Absolute Maximum Ratings

D.C. Electrical Characteristics

Operating Voltage Characteristics

Operating Current Characteristics

Standby Current Characteristics

A.C. Characteristics

High Speed Internal Oscillator – HIRC – Frequency Accuracy

Internal Low Speed Oscillator Characteristics – LIRC

External Low Speed Oscillator Characteristics – LXT

Operating Frequency Characteristic Curves

System Start Up Time Characteristics

Input/Output Characteristics

Memory Characteristics

LVD/LVR Electrical Characteristics

A/D Converter Electrical Characteristics

Internal Reference Voltage Characteristics

High Voltage I/O Electrical Characteristics

Voltage Detector Electrical Characteristics

High Voltage I/O Other Electrical Characteristics

Low Dropout Regulator Electrical Characteristics

OCP Electrical Characteristics

OVP Electrical Characteristics

Power-on Reset Characteristics

System Architecture

Clocking and Pipelining

Program Counter

Stack

Arithmetic and Logic Unit – ALU

Flash Program Memory

Structure

Special Vectors

Look-up Table

Table Program Example

In Circuit Programming – ICP

On-Chip Debug Support – OCDS

Data Memory

Structure

Special Purpose Data Memory

General Purpose Data Memory

Data Memory Addressing

Special Function Register Description

Indirect Addressing Registers – IAR0, IAR1, IAR2

Memory Pointers – MP0, MP1L/MP1H, MP2L/MP2H

Accumulator – ACC

Program Counter Low Register – PCL

Look-up Table Registers – TBLP, TBHP, TBLH

Status Register – STATUS

EEPROM Data Memory

EEPROM Data Memory Structure

EEPROM Registers

Reading Data from the EEPROM

Writing Data to the EEPROM

EEPROM Interrupt

Programming Considerations

Oscillators

Oscillator Overview

Internal High Speed RC Oscillator – HIRC

Internal 32kHz Oscillator – LIRC

External 32.768 kHz Crystal Oscillator – LXT

Operating Modes and System Clocks

System Clocks

System Operation Modes

Control Registers

Operating Mode Switching

Standby Current Considerations

Wake-up

Watchdog Timer

Watchdog Timer Clock Source

Watchdog Timer Control Register