HOLT HI-8785PST, HI-8785PSI, HI-8784PST, HI-8784PSI, HI-8783PST Datasheet

January2001

HI-8783,HI-8784,HI-8785

DESCRIPTION

TheHI-8783,HI-8784,andHI-8785aresystemcompo­nentsforinterfacing8bitparalleldatatoanARINC429
bus.TheHI-8783isalogicdeviceonlyandrequiresasep­aratelinedrivercircuit,suchastheHI-8382orHI-8585.
TheHI-8784andHI-8785combinelogicandlinedriveron
onechip.TheHI-8784hasanoutputresistanceof37.5
ohms,andtheHI-8785hasanoutputresistanceof10
ohmstofacilitateexternallightningprotectioncicuitry. The
technologyisanalog/digitalCMOS.

TheHI-8783isavailableina22pinDIPformatasasecond
sourcereplacementfortheMicrel/CaliforniaDevices
DLS-111BV.

Theproductsofferhighspeeddatabusdatatransactions
toabufferregister.Afterloading4bytes,dataisautomati­callytransferredandtransmitted.Thedatarateisequalto
theclockrate.Paritycanbeenabledinthe32ndbit.Reset
isusedtoinitializethelogicuponstartup.Wordgapsare
transmittedautomatically.

TheHI-8784andHI-8785require+/-10voltsuppliesinad­ditiontothe5voltsupply.

PINCONFIGURATIONS

1

VCC

D0
D1
D2
D3
D4
D5
D6
D7

10

2
3

HI-8783PSI

4
5

HI-8783PST

6
7
8
9

&

561SYNC

20-PinPlasticSOIC-WBpackage

20

561DATA

19

DATAZERO

18

DATAONE

17

PARITYENB

16

XMTREADY

15

XMITCLK

14

RESET

13

WRITE

12

A0

11

GND

24

FEATURES

l

l

l

l

l

Automaticallyconverts8bitparalleldata
toARINC429or561data

Highspeeddatabusinterface
On-chiplinedriveroption
SOICpackagesavailable
Militaryprocessingoptions

VCC

561SYNC

GND

1
2
3

D0

HI-8784PSI

4

D1
D2
D3
D4
D5
D6

NC

D7

HI-8784PST

5

HI-8785PSI

6
7
8

9
10
11

12 13

&

HI-8785PST

V+
561DATA

23

TXBOUT

22

TXAOUT

21

V-

20

PARITYENB

19

XMTREADY

18

XMITCLK

17

RESET

16

WRITE

15

SLP1.5

14

A0

24-PinPlasticSOIC-WBpackage

(Seepage7foradditionalpinconfigurations)

HOLTINTEGRATEDCIRCUITS

(DS8783Rev.B)01/01

1

HI-8783,HI-8784,HI-8785

PINDESCRIPTIONS

PINPINPINSYMBOLFUNCTIONDESCRIPTION
HI-8783HI-8783HI-8784
(20-pin)(22-pin)HI-8785

1221VCCpowersupply+5voltrail,
212561SYNCdigitaloutputARINC561Syncsignal

3-102-8,103-9,11DndigitalinputsParallel8bitDataInput

111112GNDpowersupplyGround
121213A0digitalinputByteaddress,A0=1for1stbyte,A0=0for2nd,3rd&4thbytes

--14SLP1.5digitalinputSelectstheslopeofthelinedriver.High=1.5us
131415digitalinputWritestrobe,loadsdataonrisingedge
141516digitalinputRegistersandsequencinglogicinitializedwhenlow
151617XMITCLKdigitalinputClockinputforthetransmitter
161718XMTRDYdigitaloutputGoeshighifthebufferregisterisempty
171819PARITYENBdigitali nputWhenhighthe32ndbitoutputisoddparity

--20V-powersupply-10voltrail
1819-DATAONEdigitaloutputGoeshighforeachARINCbitoutputthatisa“one”
1920-DATAZEROdigitaloutputGoeshighforeachARINCbitoutputthatisa“zero”

--21TXAOUTanalogoutputLinedriverouptut-Aside

--22TXBOUTanalogoutputLinedriveroutput-Bside
202123561DATAdigitaloutputSerialoutputforARINC561data

--24V+powersupply+10voltrail

WRITE
RESET

FUNCTIONALDESCRIPTION

TheHI-8783isaparalleltoserialconverter,whichwhen
loadedwithfoureightbitparallelbytes,outputsthedataas
a32bitserialword.Timingcircuitryinsertsa4bitgapatthe
endofeach32bitword.Aninputbufferregisterallowsload
operationstotakeplacewhilethepreviouslyloadedword
isbeingtransmitted.

IfthePARITYENBpinishigh,the32ndbitwillbeaparity
bit,insertedsoastomakethe32bitwordhaveoddparity.If
thePARITYENBpinislow,the32ndbitwillbetheD7bitof
the4thbyte.

OutputsareprovidedforbothARINC429/575(DATAONE
andDATAZEROpins),andARINC561(5 61DATAand
561SYNCpins)typedata.

AlowsignalappliedtothepinresetstheHI-8783’s
internallogicsothatspurioustransmissiondoesnottake
placeduringpower-up.Theregistersareclearedsothata
continuousgapwillbetransmitteduntilthefirstwordis
loadedintothetransmitter.

RESET

InputdatacanbeloadedwhentheXMTRDYsignalis
high,whichindicatestheinputbufferregisterisempty.The
first8bitbyteisthelabelbyteandisloadedwiththeA0in­puthigh,whichinitializestheinternalbytecounter.There­mainingthreebytesareloadedwithA0inthelowstate.
Each8bitbyteisloadedintotheinputbufferregisterbya
lowpulseontheinput.(Seefigure1).Afterthe

WRITE
fourthbyteisloaded,theXMTRDYoutputgoeslow.The
contentsoftheinputbufferregisteraretransferredtothe
outputregisterduringthefourthbitperiodofthegap.Ifthe
fourthgapbitperiodoft hepreviouswordhasalreadybeen
transmitted,thecontentsoftheinputbufferregisterwillbe
transferredtotheoutputshiftregisterduringthefirstbitpe­riodaftertheloadingofthefourthbyte,andtheXMTRDY
outputgoeshigh.

Aftertheoutputshiftregisterisloaded,thedataisshifted
outtotheoutputlogicintheordershowninfigure2.

The561SYNCoutputpulseslowwhentheXMTCLKislow
duringthe8thbitoftheARINCtransmission.
TheXMITCLKisthesameasthedatarate.

HOLTINTEGRATEDCIRCUITS

2

HI-8783,HI-8784,HI-8785

WRITE

DATA
BUS

XMITCLK

byte

A0

8

counter

8to32bit

mux

32bit
buffer

32 32

register

status&
control

logic

32bit

shift

register

wordgap

counter

bit

counter

PARITYENB

SLP1.5

line

driver

output

logic

XMTRDY

TXAOUT

TXBOUT

HI-8784,HI8785

DATAONE

DATAZERO

HI-8783

561SYNC

561DATA

Figure1.BlockDiagram

FUNCTIONALDESCRIPTION(Cont.)

TheHI-8784andHI-8785havethesamedigitallogicfunc­tionastheHI-8783,butincludeanon-chiplinedriverde­signedtodirectlydrivetheARINC429bus.ThetwoARINC
outputs(TXAOUTandTXBOUT)provideadifferentialvolt­agetoproducea+10voltOne,a-10voltZero,anda0volt
Null.TheslopeoftheARINCoutputsiscontrolledbythe
SLP1.5pin.IfSLP1.5ishigh,theoutputriseandfalltimeis
nominally1.5us.IfSLP1.5issetlow,theriseandfalltimes
are10us.DATAONEandDATAZEROoutputsarenotpro­videdfortheHI-8784andHI-8785.

TheHI-8784has37.5ohmsinserieswitheachlin edriver
output.TheHI-8785has10.0ohmsinseries.TheHI-8785
isforapplicationswhereexternalseriesresistanceis
needed,typicallyforlightningprotectiondevices.

A0ByteDataBusARINCBits

1Byte1D0-D7ARINC1-ARINC8
0Byte2D0-D7ARINC9-ARINC16
0Byte3D0-D7ARINC17-ARINC24
0Byte4D0-D7ARINC25-ARINC32

Figure2.Orderoftransmittedbytes

HOLTINTEGRATEDCIRCUITS

3